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TARGET_NUCLEO_F746ZG/TOOLCHAIN_GCC_ARM/stm32f7xx_hal_qspi.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 3 | * @file stm32f7xx_hal_qspi.h |
AnnaBridge | 171:3a7713b1edbc | 4 | * @author MCD Application Team |
AnnaBridge | 171:3a7713b1edbc | 5 | * @brief Header file of QSPI HAL module. |
AnnaBridge | 171:3a7713b1edbc | 6 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * @attention |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 171:3a7713b1edbc | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 171:3a7713b1edbc | 20 | * without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 171:3a7713b1edbc | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 171:3a7713b1edbc | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 171:3a7713b1edbc | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 171:3a7713b1edbc | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 171:3a7713b1edbc | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 171:3a7713b1edbc | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 171:3a7713b1edbc | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 32 | * |
AnnaBridge | 171:3a7713b1edbc | 33 | ****************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 34 | */ |
AnnaBridge | 171:3a7713b1edbc | 35 | |
AnnaBridge | 171:3a7713b1edbc | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 37 | #ifndef __STM32F7xx_HAL_QSPI_H |
AnnaBridge | 171:3a7713b1edbc | 38 | #define __STM32F7xx_HAL_QSPI_H |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 41 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 42 | #endif |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 45 | #include "stm32f7xx_hal_def.h" |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | /** @addtogroup STM32F7xx_HAL_Driver |
AnnaBridge | 171:3a7713b1edbc | 48 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 49 | */ |
AnnaBridge | 171:3a7713b1edbc | 50 | |
AnnaBridge | 171:3a7713b1edbc | 51 | /** @addtogroup QSPI |
AnnaBridge | 171:3a7713b1edbc | 52 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 53 | */ |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | /** @defgroup QSPI_Exported_Types QSPI Exported Types |
AnnaBridge | 171:3a7713b1edbc | 57 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | |
AnnaBridge | 171:3a7713b1edbc | 60 | /** |
AnnaBridge | 171:3a7713b1edbc | 61 | * @brief QSPI Init structure definition |
AnnaBridge | 171:3a7713b1edbc | 62 | */ |
AnnaBridge | 171:3a7713b1edbc | 63 | |
AnnaBridge | 171:3a7713b1edbc | 64 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 65 | { |
AnnaBridge | 171:3a7713b1edbc | 66 | uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. |
AnnaBridge | 171:3a7713b1edbc | 67 | This parameter can be a number between 0 and 255 */ |
AnnaBridge | 171:3a7713b1edbc | 68 | |
AnnaBridge | 171:3a7713b1edbc | 69 | uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) |
AnnaBridge | 171:3a7713b1edbc | 70 | This parameter can be a value between 1 and 32 */ |
AnnaBridge | 171:3a7713b1edbc | 71 | |
AnnaBridge | 171:3a7713b1edbc | 72 | uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to |
AnnaBridge | 171:3a7713b1edbc | 73 | take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) |
AnnaBridge | 171:3a7713b1edbc | 74 | This parameter can be a value of @ref QSPI_SampleShifting */ |
AnnaBridge | 171:3a7713b1edbc | 75 | |
AnnaBridge | 171:3a7713b1edbc | 76 | uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits |
AnnaBridge | 171:3a7713b1edbc | 77 | required to address the flash memory. The flash capacity can be up to 4GB |
AnnaBridge | 171:3a7713b1edbc | 78 | (addressed using 32 bits) in indirect mode, but the addressable space in |
AnnaBridge | 171:3a7713b1edbc | 79 | memory-mapped mode is limited to 256MB |
AnnaBridge | 171:3a7713b1edbc | 80 | This parameter can be a number between 0 and 31 */ |
AnnaBridge | 171:3a7713b1edbc | 81 | |
AnnaBridge | 171:3a7713b1edbc | 82 | uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number |
AnnaBridge | 171:3a7713b1edbc | 83 | of clock cycles which the chip select must remain high between commands. |
AnnaBridge | 171:3a7713b1edbc | 84 | This parameter can be a value of @ref QSPI_ChipSelectHighTime */ |
AnnaBridge | 171:3a7713b1edbc | 85 | |
AnnaBridge | 171:3a7713b1edbc | 86 | uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. |
AnnaBridge | 171:3a7713b1edbc | 87 | This parameter can be a value of @ref QSPI_ClockMode */ |
AnnaBridge | 171:3a7713b1edbc | 88 | |
AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t FlashID; /* Specifies the Flash which will be used, |
AnnaBridge | 171:3a7713b1edbc | 90 | This parameter can be a value of @ref QSPI_Flash_Select */ |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | uint32_t DualFlash; /* Specifies the Dual Flash Mode State |
AnnaBridge | 171:3a7713b1edbc | 93 | This parameter can be a value of @ref QSPI_DualFlash_Mode */ |
AnnaBridge | 171:3a7713b1edbc | 94 | }QSPI_InitTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 95 | |
AnnaBridge | 171:3a7713b1edbc | 96 | /** |
AnnaBridge | 171:3a7713b1edbc | 97 | * @brief HAL QSPI State structures definition |
AnnaBridge | 171:3a7713b1edbc | 98 | */ |
AnnaBridge | 171:3a7713b1edbc | 99 | typedef enum |
AnnaBridge | 171:3a7713b1edbc | 100 | { |
AnnaBridge | 171:3a7713b1edbc | 101 | HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ |
AnnaBridge | 171:3a7713b1edbc | 102 | HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ |
AnnaBridge | 171:3a7713b1edbc | 103 | HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ |
AnnaBridge | 171:3a7713b1edbc | 104 | HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 105 | HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 106 | HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 107 | HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 108 | HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ |
AnnaBridge | 171:3a7713b1edbc | 109 | HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ |
AnnaBridge | 171:3a7713b1edbc | 110 | }HAL_QSPI_StateTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 111 | |
AnnaBridge | 171:3a7713b1edbc | 112 | /** |
AnnaBridge | 171:3a7713b1edbc | 113 | * @brief QSPI Handle Structure definition |
AnnaBridge | 171:3a7713b1edbc | 114 | */ |
AnnaBridge | 171:3a7713b1edbc | 115 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 116 | { |
AnnaBridge | 171:3a7713b1edbc | 117 | QUADSPI_TypeDef *Instance; /* QSPI registers base address */ |
AnnaBridge | 171:3a7713b1edbc | 118 | QSPI_InitTypeDef Init; /* QSPI communication parameters */ |
AnnaBridge | 171:3a7713b1edbc | 119 | uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 120 | __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ |
AnnaBridge | 171:3a7713b1edbc | 121 | __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ |
AnnaBridge | 171:3a7713b1edbc | 122 | uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 123 | __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ |
AnnaBridge | 171:3a7713b1edbc | 124 | __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ |
AnnaBridge | 171:3a7713b1edbc | 125 | DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ |
AnnaBridge | 171:3a7713b1edbc | 126 | __IO HAL_LockTypeDef Lock; /* Locking object */ |
AnnaBridge | 171:3a7713b1edbc | 127 | __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ |
AnnaBridge | 171:3a7713b1edbc | 128 | __IO uint32_t ErrorCode; /* QSPI Error code */ |
AnnaBridge | 171:3a7713b1edbc | 129 | uint32_t Timeout; /* Timeout for the QSPI memory access */ |
AnnaBridge | 171:3a7713b1edbc | 130 | }QSPI_HandleTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 131 | |
AnnaBridge | 171:3a7713b1edbc | 132 | /** |
AnnaBridge | 171:3a7713b1edbc | 133 | * @brief QSPI Command structure definition |
AnnaBridge | 171:3a7713b1edbc | 134 | */ |
AnnaBridge | 171:3a7713b1edbc | 135 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 136 | { |
AnnaBridge | 171:3a7713b1edbc | 137 | uint32_t Instruction; /* Specifies the Instruction to be sent |
AnnaBridge | 171:3a7713b1edbc | 138 | This parameter can be a value (8-bit) between 0x00 and 0xFF */ |
AnnaBridge | 171:3a7713b1edbc | 139 | uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) |
AnnaBridge | 171:3a7713b1edbc | 140 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 141 | uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) |
AnnaBridge | 171:3a7713b1edbc | 142 | This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 143 | uint32_t AddressSize; /* Specifies the Address Size |
AnnaBridge | 171:3a7713b1edbc | 144 | This parameter can be a value of @ref QSPI_AddressSize */ |
AnnaBridge | 171:3a7713b1edbc | 145 | uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size |
AnnaBridge | 171:3a7713b1edbc | 146 | This parameter can be a value of @ref QSPI_AlternateBytesSize */ |
AnnaBridge | 171:3a7713b1edbc | 147 | uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. |
AnnaBridge | 171:3a7713b1edbc | 148 | This parameter can be a number between 0 and 31 */ |
AnnaBridge | 171:3a7713b1edbc | 149 | uint32_t InstructionMode; /* Specifies the Instruction Mode |
AnnaBridge | 171:3a7713b1edbc | 150 | This parameter can be a value of @ref QSPI_InstructionMode */ |
AnnaBridge | 171:3a7713b1edbc | 151 | uint32_t AddressMode; /* Specifies the Address Mode |
AnnaBridge | 171:3a7713b1edbc | 152 | This parameter can be a value of @ref QSPI_AddressMode */ |
AnnaBridge | 171:3a7713b1edbc | 153 | uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode |
AnnaBridge | 171:3a7713b1edbc | 154 | This parameter can be a value of @ref QSPI_AlternateBytesMode */ |
AnnaBridge | 171:3a7713b1edbc | 155 | uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) |
AnnaBridge | 171:3a7713b1edbc | 156 | This parameter can be a value of @ref QSPI_DataMode */ |
AnnaBridge | 171:3a7713b1edbc | 157 | uint32_t NbData; /* Specifies the number of data to transfer. |
AnnaBridge | 171:3a7713b1edbc | 158 | This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length |
AnnaBridge | 171:3a7713b1edbc | 159 | until end of memory)*/ |
AnnaBridge | 171:3a7713b1edbc | 160 | uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase |
AnnaBridge | 171:3a7713b1edbc | 161 | This parameter can be a value of @ref QSPI_DdrMode */ |
AnnaBridge | 171:3a7713b1edbc | 162 | uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of |
AnnaBridge | 171:3a7713b1edbc | 163 | system clock in DDR mode. |
AnnaBridge | 171:3a7713b1edbc | 164 | This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ |
AnnaBridge | 171:3a7713b1edbc | 165 | uint32_t SIOOMode; /* Specifies the send instruction only once mode |
AnnaBridge | 171:3a7713b1edbc | 166 | This parameter can be a value of @ref QSPI_SIOOMode */ |
AnnaBridge | 171:3a7713b1edbc | 167 | }QSPI_CommandTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 168 | |
AnnaBridge | 171:3a7713b1edbc | 169 | /** |
AnnaBridge | 171:3a7713b1edbc | 170 | * @brief QSPI Auto Polling mode configuration structure definition |
AnnaBridge | 171:3a7713b1edbc | 171 | */ |
AnnaBridge | 171:3a7713b1edbc | 172 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 173 | { |
AnnaBridge | 171:3a7713b1edbc | 174 | uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. |
AnnaBridge | 171:3a7713b1edbc | 175 | This parameter can be any value between 0 and 0xFFFFFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 176 | uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. |
AnnaBridge | 171:3a7713b1edbc | 177 | This parameter can be any value between 0 and 0xFFFFFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 178 | uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. |
AnnaBridge | 171:3a7713b1edbc | 179 | This parameter can be any value between 0 and 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 180 | uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. |
AnnaBridge | 171:3a7713b1edbc | 181 | This parameter can be any value between 1 and 4 */ |
AnnaBridge | 171:3a7713b1edbc | 182 | uint32_t MatchMode; /* Specifies the method used for determining a match. |
AnnaBridge | 171:3a7713b1edbc | 183 | This parameter can be a value of @ref QSPI_MatchMode */ |
AnnaBridge | 171:3a7713b1edbc | 184 | uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. |
AnnaBridge | 171:3a7713b1edbc | 185 | This parameter can be a value of @ref QSPI_AutomaticStop */ |
AnnaBridge | 171:3a7713b1edbc | 186 | }QSPI_AutoPollingTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | /** |
AnnaBridge | 171:3a7713b1edbc | 189 | * @brief QSPI Memory Mapped mode configuration structure definition |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | typedef struct |
AnnaBridge | 171:3a7713b1edbc | 192 | { |
AnnaBridge | 171:3a7713b1edbc | 193 | uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. |
AnnaBridge | 171:3a7713b1edbc | 194 | This parameter can be any value between 0 and 0xFFFF */ |
AnnaBridge | 171:3a7713b1edbc | 195 | uint32_t TimeOutActivation; /* Specifies if the time out counter is enabled to release the chip select. |
AnnaBridge | 171:3a7713b1edbc | 196 | This parameter can be a value of @ref QSPI_TimeOutActivation */ |
AnnaBridge | 171:3a7713b1edbc | 197 | }QSPI_MemoryMappedTypeDef; |
AnnaBridge | 171:3a7713b1edbc | 198 | /** |
AnnaBridge | 171:3a7713b1edbc | 199 | * @} |
AnnaBridge | 171:3a7713b1edbc | 200 | */ |
AnnaBridge | 171:3a7713b1edbc | 201 | |
AnnaBridge | 171:3a7713b1edbc | 202 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 203 | /** @defgroup QSPI_Exported_Constants QSPI Exported Constants |
AnnaBridge | 171:3a7713b1edbc | 204 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 205 | */ |
AnnaBridge | 171:3a7713b1edbc | 206 | /** @defgroup QSPI_ErrorCode QSPI Error Code |
AnnaBridge | 171:3a7713b1edbc | 207 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 208 | */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ |
AnnaBridge | 171:3a7713b1edbc | 214 | /** |
AnnaBridge | 171:3a7713b1edbc | 215 | * @} |
AnnaBridge | 171:3a7713b1edbc | 216 | */ |
AnnaBridge | 171:3a7713b1edbc | 217 | |
AnnaBridge | 171:3a7713b1edbc | 218 | /** @defgroup QSPI_SampleShifting QSPI Sample Shifting |
AnnaBridge | 171:3a7713b1edbc | 219 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 220 | */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ |
AnnaBridge | 171:3a7713b1edbc | 223 | /** |
AnnaBridge | 171:3a7713b1edbc | 224 | * @} |
AnnaBridge | 171:3a7713b1edbc | 225 | */ |
AnnaBridge | 171:3a7713b1edbc | 226 | |
AnnaBridge | 171:3a7713b1edbc | 227 | /** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time |
AnnaBridge | 171:3a7713b1edbc | 228 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 229 | */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ |
AnnaBridge | 171:3a7713b1edbc | 238 | /** |
AnnaBridge | 171:3a7713b1edbc | 239 | * @} |
AnnaBridge | 171:3a7713b1edbc | 240 | */ |
AnnaBridge | 171:3a7713b1edbc | 241 | |
AnnaBridge | 171:3a7713b1edbc | 242 | /** @defgroup QSPI_ClockMode QSPI Clock Mode |
AnnaBridge | 171:3a7713b1edbc | 243 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 244 | */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ |
AnnaBridge | 171:3a7713b1edbc | 247 | /** |
AnnaBridge | 171:3a7713b1edbc | 248 | * @} |
AnnaBridge | 171:3a7713b1edbc | 249 | */ |
AnnaBridge | 171:3a7713b1edbc | 250 | |
AnnaBridge | 171:3a7713b1edbc | 251 | /** @defgroup QSPI_Flash_Select QSPI Flash Select |
AnnaBridge | 171:3a7713b1edbc | 252 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 253 | */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 255 | #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) |
AnnaBridge | 171:3a7713b1edbc | 256 | /** |
AnnaBridge | 171:3a7713b1edbc | 257 | * @} |
AnnaBridge | 171:3a7713b1edbc | 258 | */ |
AnnaBridge | 171:3a7713b1edbc | 259 | |
AnnaBridge | 171:3a7713b1edbc | 260 | /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode |
AnnaBridge | 171:3a7713b1edbc | 261 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 262 | */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) |
AnnaBridge | 171:3a7713b1edbc | 264 | #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U) |
AnnaBridge | 171:3a7713b1edbc | 265 | /** |
AnnaBridge | 171:3a7713b1edbc | 266 | * @} |
AnnaBridge | 171:3a7713b1edbc | 267 | */ |
AnnaBridge | 171:3a7713b1edbc | 268 | |
AnnaBridge | 171:3a7713b1edbc | 269 | /** @defgroup QSPI_AddressSize QSPI Address Size |
AnnaBridge | 171:3a7713b1edbc | 270 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 271 | */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ |
AnnaBridge | 171:3a7713b1edbc | 274 | #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ |
AnnaBridge | 171:3a7713b1edbc | 276 | /** |
AnnaBridge | 171:3a7713b1edbc | 277 | * @} |
AnnaBridge | 171:3a7713b1edbc | 278 | */ |
AnnaBridge | 171:3a7713b1edbc | 279 | |
AnnaBridge | 171:3a7713b1edbc | 280 | /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size |
AnnaBridge | 171:3a7713b1edbc | 281 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 282 | */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 284 | #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 285 | #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 286 | #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 287 | /** |
AnnaBridge | 171:3a7713b1edbc | 288 | * @} |
AnnaBridge | 171:3a7713b1edbc | 289 | */ |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | /** @defgroup QSPI_InstructionMode QSPI Instruction Mode |
AnnaBridge | 171:3a7713b1edbc | 292 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 293 | */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/ |
AnnaBridge | 171:3a7713b1edbc | 295 | #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ |
AnnaBridge | 171:3a7713b1edbc | 298 | /** |
AnnaBridge | 171:3a7713b1edbc | 299 | * @} |
AnnaBridge | 171:3a7713b1edbc | 300 | */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | /** @defgroup QSPI_AddressMode QSPI Address Mode |
AnnaBridge | 171:3a7713b1edbc | 303 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 304 | */ |
AnnaBridge | 171:3a7713b1edbc | 305 | #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/ |
AnnaBridge | 171:3a7713b1edbc | 306 | #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ |
AnnaBridge | 171:3a7713b1edbc | 307 | #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ |
AnnaBridge | 171:3a7713b1edbc | 308 | #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ |
AnnaBridge | 171:3a7713b1edbc | 309 | /** |
AnnaBridge | 171:3a7713b1edbc | 310 | * @} |
AnnaBridge | 171:3a7713b1edbc | 311 | */ |
AnnaBridge | 171:3a7713b1edbc | 312 | |
AnnaBridge | 171:3a7713b1edbc | 313 | /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode |
AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ |
AnnaBridge | 171:3a7713b1edbc | 318 | #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ |
AnnaBridge | 171:3a7713b1edbc | 319 | #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ |
AnnaBridge | 171:3a7713b1edbc | 320 | /** |
AnnaBridge | 171:3a7713b1edbc | 321 | * @} |
AnnaBridge | 171:3a7713b1edbc | 322 | */ |
AnnaBridge | 171:3a7713b1edbc | 323 | |
AnnaBridge | 171:3a7713b1edbc | 324 | /** @defgroup QSPI_DataMode QSPI Data Mode |
AnnaBridge | 171:3a7713b1edbc | 325 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 326 | */ |
AnnaBridge | 171:3a7713b1edbc | 327 | #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/ |
AnnaBridge | 171:3a7713b1edbc | 328 | #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ |
AnnaBridge | 171:3a7713b1edbc | 331 | /** |
AnnaBridge | 171:3a7713b1edbc | 332 | * @} |
AnnaBridge | 171:3a7713b1edbc | 333 | */ |
AnnaBridge | 171:3a7713b1edbc | 334 | |
AnnaBridge | 171:3a7713b1edbc | 335 | /** @defgroup QSPI_DdrMode QSPI Ddr Mode |
AnnaBridge | 171:3a7713b1edbc | 336 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 337 | */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ |
AnnaBridge | 171:3a7713b1edbc | 340 | /** |
AnnaBridge | 171:3a7713b1edbc | 341 | * @} |
AnnaBridge | 171:3a7713b1edbc | 342 | */ |
AnnaBridge | 171:3a7713b1edbc | 343 | |
AnnaBridge | 171:3a7713b1edbc | 344 | /** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle |
AnnaBridge | 171:3a7713b1edbc | 345 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 346 | */ |
AnnaBridge | 171:3a7713b1edbc | 347 | #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/ |
AnnaBridge | 171:3a7713b1edbc | 349 | /** |
AnnaBridge | 171:3a7713b1edbc | 350 | * @} |
AnnaBridge | 171:3a7713b1edbc | 351 | */ |
AnnaBridge | 171:3a7713b1edbc | 352 | |
AnnaBridge | 171:3a7713b1edbc | 353 | /** @defgroup QSPI_SIOOMode QSPI SIOO Mode |
AnnaBridge | 171:3a7713b1edbc | 354 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 355 | */ |
AnnaBridge | 171:3a7713b1edbc | 356 | #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/ |
AnnaBridge | 171:3a7713b1edbc | 357 | #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ |
AnnaBridge | 171:3a7713b1edbc | 358 | /** |
AnnaBridge | 171:3a7713b1edbc | 359 | * @} |
AnnaBridge | 171:3a7713b1edbc | 360 | */ |
AnnaBridge | 171:3a7713b1edbc | 361 | |
AnnaBridge | 171:3a7713b1edbc | 362 | /** @defgroup QSPI_MatchMode QSPI Match Mode |
AnnaBridge | 171:3a7713b1edbc | 363 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 364 | */ |
AnnaBridge | 171:3a7713b1edbc | 365 | #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/ |
AnnaBridge | 171:3a7713b1edbc | 366 | #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ |
AnnaBridge | 171:3a7713b1edbc | 367 | /** |
AnnaBridge | 171:3a7713b1edbc | 368 | * @} |
AnnaBridge | 171:3a7713b1edbc | 369 | */ |
AnnaBridge | 171:3a7713b1edbc | 370 | |
AnnaBridge | 171:3a7713b1edbc | 371 | /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop |
AnnaBridge | 171:3a7713b1edbc | 372 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 373 | */ |
AnnaBridge | 171:3a7713b1edbc | 374 | #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/ |
AnnaBridge | 171:3a7713b1edbc | 375 | #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ |
AnnaBridge | 171:3a7713b1edbc | 376 | /** |
AnnaBridge | 171:3a7713b1edbc | 377 | * @} |
AnnaBridge | 171:3a7713b1edbc | 378 | */ |
AnnaBridge | 171:3a7713b1edbc | 379 | |
AnnaBridge | 171:3a7713b1edbc | 380 | /** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation |
AnnaBridge | 171:3a7713b1edbc | 381 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 382 | */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ |
AnnaBridge | 171:3a7713b1edbc | 385 | /** |
AnnaBridge | 171:3a7713b1edbc | 386 | * @} |
AnnaBridge | 171:3a7713b1edbc | 387 | */ |
AnnaBridge | 171:3a7713b1edbc | 388 | |
AnnaBridge | 171:3a7713b1edbc | 389 | /** @defgroup QSPI_Flags QSPI Flags |
AnnaBridge | 171:3a7713b1edbc | 390 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 391 | */ |
AnnaBridge | 171:3a7713b1edbc | 392 | #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ |
AnnaBridge | 171:3a7713b1edbc | 394 | #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ |
AnnaBridge | 171:3a7713b1edbc | 395 | #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ |
AnnaBridge | 171:3a7713b1edbc | 396 | #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ |
AnnaBridge | 171:3a7713b1edbc | 397 | #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ |
AnnaBridge | 171:3a7713b1edbc | 398 | /** |
AnnaBridge | 171:3a7713b1edbc | 399 | * @} |
AnnaBridge | 171:3a7713b1edbc | 400 | */ |
AnnaBridge | 171:3a7713b1edbc | 401 | |
AnnaBridge | 171:3a7713b1edbc | 402 | /** @defgroup QSPI_Interrupts QSPI Interrupts |
AnnaBridge | 171:3a7713b1edbc | 403 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 404 | */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ |
AnnaBridge | 171:3a7713b1edbc | 406 | #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ |
AnnaBridge | 171:3a7713b1edbc | 407 | #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ |
AnnaBridge | 171:3a7713b1edbc | 408 | #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ |
AnnaBridge | 171:3a7713b1edbc | 409 | #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ |
AnnaBridge | 171:3a7713b1edbc | 410 | /** |
AnnaBridge | 171:3a7713b1edbc | 411 | * @} |
AnnaBridge | 171:3a7713b1edbc | 412 | */ |
AnnaBridge | 171:3a7713b1edbc | 413 | |
AnnaBridge | 171:3a7713b1edbc | 414 | /** @defgroup QSPI_Timeout_definition QSPI Timeout definition |
AnnaBridge | 171:3a7713b1edbc | 415 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 416 | */ |
AnnaBridge | 171:3a7713b1edbc | 417 | #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */ |
AnnaBridge | 171:3a7713b1edbc | 418 | /** |
AnnaBridge | 171:3a7713b1edbc | 419 | * @} |
AnnaBridge | 171:3a7713b1edbc | 420 | */ |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | /** |
AnnaBridge | 171:3a7713b1edbc | 423 | * @} |
AnnaBridge | 171:3a7713b1edbc | 424 | */ |
AnnaBridge | 171:3a7713b1edbc | 425 | |
AnnaBridge | 171:3a7713b1edbc | 426 | /* Exported macros -----------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 427 | /** @defgroup QSPI_Exported_Macros QSPI Exported Macros |
AnnaBridge | 171:3a7713b1edbc | 428 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 429 | */ |
AnnaBridge | 171:3a7713b1edbc | 430 | |
AnnaBridge | 171:3a7713b1edbc | 431 | /** @brief Reset QSPI handle state |
AnnaBridge | 171:3a7713b1edbc | 432 | * @param __HANDLE__ QSPI handle. |
AnnaBridge | 171:3a7713b1edbc | 433 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 434 | */ |
AnnaBridge | 171:3a7713b1edbc | 435 | #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) |
AnnaBridge | 171:3a7713b1edbc | 436 | |
AnnaBridge | 171:3a7713b1edbc | 437 | /** @brief Enable QSPI |
AnnaBridge | 171:3a7713b1edbc | 438 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 439 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 440 | */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
AnnaBridge | 171:3a7713b1edbc | 442 | |
AnnaBridge | 171:3a7713b1edbc | 443 | /** @brief Disable QSPI |
AnnaBridge | 171:3a7713b1edbc | 444 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 445 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 446 | */ |
AnnaBridge | 171:3a7713b1edbc | 447 | #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) |
AnnaBridge | 171:3a7713b1edbc | 448 | |
AnnaBridge | 171:3a7713b1edbc | 449 | /** @brief Enables the specified QSPI interrupt. |
AnnaBridge | 171:3a7713b1edbc | 450 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 451 | * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. |
AnnaBridge | 171:3a7713b1edbc | 452 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 453 | * @arg QSPI_IT_TO: QSPI Time out interrupt |
AnnaBridge | 171:3a7713b1edbc | 454 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
AnnaBridge | 171:3a7713b1edbc | 455 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
AnnaBridge | 171:3a7713b1edbc | 456 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
AnnaBridge | 171:3a7713b1edbc | 457 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
AnnaBridge | 171:3a7713b1edbc | 458 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 459 | */ |
AnnaBridge | 171:3a7713b1edbc | 460 | #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 461 | |
AnnaBridge | 171:3a7713b1edbc | 462 | |
AnnaBridge | 171:3a7713b1edbc | 463 | /** @brief Disables the specified QSPI interrupt. |
AnnaBridge | 171:3a7713b1edbc | 464 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 465 | * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. |
AnnaBridge | 171:3a7713b1edbc | 466 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 467 | * @arg QSPI_IT_TO: QSPI Timeout interrupt |
AnnaBridge | 171:3a7713b1edbc | 468 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
AnnaBridge | 171:3a7713b1edbc | 469 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
AnnaBridge | 171:3a7713b1edbc | 470 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
AnnaBridge | 171:3a7713b1edbc | 471 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
AnnaBridge | 171:3a7713b1edbc | 472 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 473 | */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 475 | |
AnnaBridge | 171:3a7713b1edbc | 476 | /** @brief Checks whether the specified QSPI interrupt source is enabled. |
AnnaBridge | 171:3a7713b1edbc | 477 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 478 | * @param __INTERRUPT__ specifies the QSPI interrupt source to check. |
AnnaBridge | 171:3a7713b1edbc | 479 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 480 | * @arg QSPI_IT_TO: QSPI Time out interrupt |
AnnaBridge | 171:3a7713b1edbc | 481 | * @arg QSPI_IT_SM: QSPI Status match interrupt |
AnnaBridge | 171:3a7713b1edbc | 482 | * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt |
AnnaBridge | 171:3a7713b1edbc | 483 | * @arg QSPI_IT_TC: QSPI Transfer complete interrupt |
AnnaBridge | 171:3a7713b1edbc | 484 | * @arg QSPI_IT_TE: QSPI Transfer error interrupt |
AnnaBridge | 171:3a7713b1edbc | 485 | * @retval The new state of __INTERRUPT__ (TRUE or FALSE). |
AnnaBridge | 171:3a7713b1edbc | 486 | */ |
AnnaBridge | 171:3a7713b1edbc | 487 | #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) |
AnnaBridge | 171:3a7713b1edbc | 488 | |
AnnaBridge | 171:3a7713b1edbc | 489 | /** |
AnnaBridge | 171:3a7713b1edbc | 490 | * @brief Get the selected QSPI's flag status. |
AnnaBridge | 171:3a7713b1edbc | 491 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 492 | * @param __FLAG__ specifies the QSPI flag to check. |
AnnaBridge | 171:3a7713b1edbc | 493 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 494 | * @arg QSPI_FLAG_BUSY: QSPI Busy flag |
AnnaBridge | 171:3a7713b1edbc | 495 | * @arg QSPI_FLAG_TO: QSPI Time out flag |
AnnaBridge | 171:3a7713b1edbc | 496 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
AnnaBridge | 171:3a7713b1edbc | 497 | * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag |
AnnaBridge | 171:3a7713b1edbc | 498 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 499 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 500 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 501 | */ |
AnnaBridge | 171:3a7713b1edbc | 502 | #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) |
AnnaBridge | 171:3a7713b1edbc | 503 | |
AnnaBridge | 171:3a7713b1edbc | 504 | /** @brief Clears the specified QSPI's flag status. |
AnnaBridge | 171:3a7713b1edbc | 505 | * @param __HANDLE__ specifies the QSPI Handle. |
AnnaBridge | 171:3a7713b1edbc | 506 | * @param __FLAG__ specifies the QSPI clear register flag that needs to be set |
AnnaBridge | 171:3a7713b1edbc | 507 | * This parameter can be one of the following values: |
AnnaBridge | 171:3a7713b1edbc | 508 | * @arg QSPI_FLAG_TO: QSPI Time out flag |
AnnaBridge | 171:3a7713b1edbc | 509 | * @arg QSPI_FLAG_SM: QSPI Status match flag |
AnnaBridge | 171:3a7713b1edbc | 510 | * @arg QSPI_FLAG_TC: QSPI Transfer complete flag |
AnnaBridge | 171:3a7713b1edbc | 511 | * @arg QSPI_FLAG_TE: QSPI Transfer error flag |
AnnaBridge | 171:3a7713b1edbc | 512 | * @retval None |
AnnaBridge | 171:3a7713b1edbc | 513 | */ |
AnnaBridge | 171:3a7713b1edbc | 514 | #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) |
AnnaBridge | 171:3a7713b1edbc | 515 | /** |
AnnaBridge | 171:3a7713b1edbc | 516 | * @} |
AnnaBridge | 171:3a7713b1edbc | 517 | */ |
AnnaBridge | 171:3a7713b1edbc | 518 | |
AnnaBridge | 171:3a7713b1edbc | 519 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 520 | /** @addtogroup QSPI_Exported_Functions |
AnnaBridge | 171:3a7713b1edbc | 521 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 522 | */ |
AnnaBridge | 171:3a7713b1edbc | 523 | |
AnnaBridge | 171:3a7713b1edbc | 524 | /** @addtogroup QSPI_Exported_Functions_Group1 |
AnnaBridge | 171:3a7713b1edbc | 525 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 526 | */ |
AnnaBridge | 171:3a7713b1edbc | 527 | /* Initialization/de-initialization functions ********************************/ |
AnnaBridge | 171:3a7713b1edbc | 528 | HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 529 | HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 530 | void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 531 | void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 532 | /** |
AnnaBridge | 171:3a7713b1edbc | 533 | * @} |
AnnaBridge | 171:3a7713b1edbc | 534 | */ |
AnnaBridge | 171:3a7713b1edbc | 535 | |
AnnaBridge | 171:3a7713b1edbc | 536 | /** @addtogroup QSPI_Exported_Functions_Group2 |
AnnaBridge | 171:3a7713b1edbc | 537 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 538 | */ |
AnnaBridge | 171:3a7713b1edbc | 539 | /* IO operation functions *****************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 540 | /* QSPI IRQ handler method */ |
AnnaBridge | 171:3a7713b1edbc | 541 | void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 542 | |
AnnaBridge | 171:3a7713b1edbc | 543 | /* QSPI indirect mode */ |
AnnaBridge | 171:3a7713b1edbc | 544 | HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 545 | HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 546 | HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 547 | HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); |
AnnaBridge | 171:3a7713b1edbc | 548 | HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
AnnaBridge | 171:3a7713b1edbc | 549 | HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
AnnaBridge | 171:3a7713b1edbc | 550 | HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
AnnaBridge | 171:3a7713b1edbc | 551 | HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); |
AnnaBridge | 171:3a7713b1edbc | 552 | |
AnnaBridge | 171:3a7713b1edbc | 553 | /* QSPI status flag polling mode */ |
AnnaBridge | 171:3a7713b1edbc | 554 | HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 555 | HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); |
AnnaBridge | 171:3a7713b1edbc | 556 | |
AnnaBridge | 171:3a7713b1edbc | 557 | /* QSPI memory-mapped mode */ |
AnnaBridge | 171:3a7713b1edbc | 558 | HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); |
AnnaBridge | 171:3a7713b1edbc | 559 | /** |
AnnaBridge | 171:3a7713b1edbc | 560 | * @} |
AnnaBridge | 171:3a7713b1edbc | 561 | */ |
AnnaBridge | 171:3a7713b1edbc | 562 | |
AnnaBridge | 171:3a7713b1edbc | 563 | /** @addtogroup QSPI_Exported_Functions_Group3 |
AnnaBridge | 171:3a7713b1edbc | 564 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 565 | */ |
AnnaBridge | 171:3a7713b1edbc | 566 | /* Callback functions in non-blocking modes ***********************************/ |
AnnaBridge | 171:3a7713b1edbc | 567 | void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 568 | void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 569 | void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 570 | |
AnnaBridge | 171:3a7713b1edbc | 571 | /* QSPI indirect mode */ |
AnnaBridge | 171:3a7713b1edbc | 572 | void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 573 | void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 574 | void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 575 | void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 576 | void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 577 | |
AnnaBridge | 171:3a7713b1edbc | 578 | /* QSPI status flag polling mode */ |
AnnaBridge | 171:3a7713b1edbc | 579 | void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 580 | |
AnnaBridge | 171:3a7713b1edbc | 581 | /* QSPI memory-mapped mode */ |
AnnaBridge | 171:3a7713b1edbc | 582 | void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 583 | /** |
AnnaBridge | 171:3a7713b1edbc | 584 | * @} |
AnnaBridge | 171:3a7713b1edbc | 585 | */ |
AnnaBridge | 171:3a7713b1edbc | 586 | |
AnnaBridge | 171:3a7713b1edbc | 587 | /** @addtogroup QSPI_Exported_Functions_Group4 |
AnnaBridge | 171:3a7713b1edbc | 588 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 589 | */ |
AnnaBridge | 171:3a7713b1edbc | 590 | /* Peripheral Control and State functions ************************************/ |
AnnaBridge | 171:3a7713b1edbc | 591 | HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 592 | uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 593 | HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 594 | HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 595 | void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); |
AnnaBridge | 171:3a7713b1edbc | 596 | HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); |
AnnaBridge | 171:3a7713b1edbc | 597 | uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); |
AnnaBridge | 171:3a7713b1edbc | 598 | /** |
AnnaBridge | 171:3a7713b1edbc | 599 | * @} |
AnnaBridge | 171:3a7713b1edbc | 600 | */ |
AnnaBridge | 171:3a7713b1edbc | 601 | |
AnnaBridge | 171:3a7713b1edbc | 602 | /** |
AnnaBridge | 171:3a7713b1edbc | 603 | * @} |
AnnaBridge | 171:3a7713b1edbc | 604 | */ |
AnnaBridge | 171:3a7713b1edbc | 605 | |
AnnaBridge | 171:3a7713b1edbc | 606 | /* Private macros ------------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 607 | /** @defgroup QSPI_Private_Macros QSPI Private Macros |
AnnaBridge | 171:3a7713b1edbc | 608 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 609 | */ |
AnnaBridge | 171:3a7713b1edbc | 610 | /** @defgroup QSPI_ClockPrescaler QSPI Clock Prescaler |
AnnaBridge | 171:3a7713b1edbc | 611 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 612 | */ |
AnnaBridge | 171:3a7713b1edbc | 613 | #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF) |
AnnaBridge | 171:3a7713b1edbc | 614 | /** |
AnnaBridge | 171:3a7713b1edbc | 615 | * @} |
AnnaBridge | 171:3a7713b1edbc | 616 | */ |
AnnaBridge | 171:3a7713b1edbc | 617 | |
AnnaBridge | 171:3a7713b1edbc | 618 | /** @defgroup QSPI_FifoThreshold QSPI Fifo Threshold |
AnnaBridge | 171:3a7713b1edbc | 619 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 620 | */ |
AnnaBridge | 171:3a7713b1edbc | 621 | #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 32)) |
AnnaBridge | 171:3a7713b1edbc | 622 | /** |
AnnaBridge | 171:3a7713b1edbc | 623 | * @} |
AnnaBridge | 171:3a7713b1edbc | 624 | */ |
AnnaBridge | 171:3a7713b1edbc | 625 | |
AnnaBridge | 171:3a7713b1edbc | 626 | #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 627 | ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) |
AnnaBridge | 171:3a7713b1edbc | 628 | |
AnnaBridge | 171:3a7713b1edbc | 629 | /** @defgroup QSPI_FlashSize QSPI Flash Size |
AnnaBridge | 171:3a7713b1edbc | 630 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 631 | */ |
AnnaBridge | 171:3a7713b1edbc | 632 | #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31)) |
AnnaBridge | 171:3a7713b1edbc | 633 | /** |
AnnaBridge | 171:3a7713b1edbc | 634 | * @} |
AnnaBridge | 171:3a7713b1edbc | 635 | */ |
AnnaBridge | 171:3a7713b1edbc | 636 | |
AnnaBridge | 171:3a7713b1edbc | 637 | #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 638 | ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 639 | ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 640 | ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 641 | ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 642 | ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 643 | ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 644 | ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) |
AnnaBridge | 171:3a7713b1edbc | 645 | |
AnnaBridge | 171:3a7713b1edbc | 646 | #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ |
AnnaBridge | 171:3a7713b1edbc | 647 | ((CLKMODE) == QSPI_CLOCK_MODE_3)) |
AnnaBridge | 171:3a7713b1edbc | 648 | |
AnnaBridge | 171:3a7713b1edbc | 649 | #define IS_QSPI_FLASH_ID(FLA) (((FLA) == QSPI_FLASH_ID_1) || \ |
AnnaBridge | 171:3a7713b1edbc | 650 | ((FLA) == QSPI_FLASH_ID_2)) |
AnnaBridge | 171:3a7713b1edbc | 651 | |
AnnaBridge | 171:3a7713b1edbc | 652 | #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 653 | ((MODE) == QSPI_DUALFLASH_DISABLE)) |
AnnaBridge | 171:3a7713b1edbc | 654 | |
AnnaBridge | 171:3a7713b1edbc | 655 | |
AnnaBridge | 171:3a7713b1edbc | 656 | /** @defgroup QSPI_Instruction QSPI Instruction |
AnnaBridge | 171:3a7713b1edbc | 657 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 658 | */ |
AnnaBridge | 171:3a7713b1edbc | 659 | #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF) |
AnnaBridge | 171:3a7713b1edbc | 660 | /** |
AnnaBridge | 171:3a7713b1edbc | 661 | * @} |
AnnaBridge | 171:3a7713b1edbc | 662 | */ |
AnnaBridge | 171:3a7713b1edbc | 663 | |
AnnaBridge | 171:3a7713b1edbc | 664 | #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ |
AnnaBridge | 171:3a7713b1edbc | 665 | ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ |
AnnaBridge | 171:3a7713b1edbc | 666 | ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ |
AnnaBridge | 171:3a7713b1edbc | 667 | ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) |
AnnaBridge | 171:3a7713b1edbc | 668 | |
AnnaBridge | 171:3a7713b1edbc | 669 | #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ |
AnnaBridge | 171:3a7713b1edbc | 670 | ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ |
AnnaBridge | 171:3a7713b1edbc | 671 | ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ |
AnnaBridge | 171:3a7713b1edbc | 672 | ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) |
AnnaBridge | 171:3a7713b1edbc | 673 | |
AnnaBridge | 171:3a7713b1edbc | 674 | |
AnnaBridge | 171:3a7713b1edbc | 675 | /** @defgroup QSPI_DummyCycles QSPI Dummy Cycles |
AnnaBridge | 171:3a7713b1edbc | 676 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 677 | */ |
AnnaBridge | 171:3a7713b1edbc | 678 | #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31) |
AnnaBridge | 171:3a7713b1edbc | 679 | /** |
AnnaBridge | 171:3a7713b1edbc | 680 | * @} |
AnnaBridge | 171:3a7713b1edbc | 681 | */ |
AnnaBridge | 171:3a7713b1edbc | 682 | |
AnnaBridge | 171:3a7713b1edbc | 683 | #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 684 | ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ |
AnnaBridge | 171:3a7713b1edbc | 685 | ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ |
AnnaBridge | 171:3a7713b1edbc | 686 | ((MODE) == QSPI_INSTRUCTION_4_LINES)) |
AnnaBridge | 171:3a7713b1edbc | 687 | |
AnnaBridge | 171:3a7713b1edbc | 688 | #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 689 | ((MODE) == QSPI_ADDRESS_1_LINE) || \ |
AnnaBridge | 171:3a7713b1edbc | 690 | ((MODE) == QSPI_ADDRESS_2_LINES) || \ |
AnnaBridge | 171:3a7713b1edbc | 691 | ((MODE) == QSPI_ADDRESS_4_LINES)) |
AnnaBridge | 171:3a7713b1edbc | 692 | |
AnnaBridge | 171:3a7713b1edbc | 693 | #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 694 | ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ |
AnnaBridge | 171:3a7713b1edbc | 695 | ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ |
AnnaBridge | 171:3a7713b1edbc | 696 | ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) |
AnnaBridge | 171:3a7713b1edbc | 697 | |
AnnaBridge | 171:3a7713b1edbc | 698 | #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ |
AnnaBridge | 171:3a7713b1edbc | 699 | ((MODE) == QSPI_DATA_1_LINE) || \ |
AnnaBridge | 171:3a7713b1edbc | 700 | ((MODE) == QSPI_DATA_2_LINES) || \ |
AnnaBridge | 171:3a7713b1edbc | 701 | ((MODE) == QSPI_DATA_4_LINES)) |
AnnaBridge | 171:3a7713b1edbc | 702 | |
AnnaBridge | 171:3a7713b1edbc | 703 | #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 704 | ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 705 | |
AnnaBridge | 171:3a7713b1edbc | 706 | #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ |
AnnaBridge | 171:3a7713b1edbc | 707 | ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) |
AnnaBridge | 171:3a7713b1edbc | 708 | |
AnnaBridge | 171:3a7713b1edbc | 709 | #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ |
AnnaBridge | 171:3a7713b1edbc | 710 | ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) |
AnnaBridge | 171:3a7713b1edbc | 711 | |
AnnaBridge | 171:3a7713b1edbc | 712 | /** @defgroup QSPI_Interval QSPI Interval |
AnnaBridge | 171:3a7713b1edbc | 713 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 714 | */ |
AnnaBridge | 171:3a7713b1edbc | 715 | #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) |
AnnaBridge | 171:3a7713b1edbc | 716 | /** |
AnnaBridge | 171:3a7713b1edbc | 717 | * @} |
AnnaBridge | 171:3a7713b1edbc | 718 | */ |
AnnaBridge | 171:3a7713b1edbc | 719 | |
AnnaBridge | 171:3a7713b1edbc | 720 | /** @defgroup QSPI_StatusBytesSize QSPI Status Bytes Size |
AnnaBridge | 171:3a7713b1edbc | 721 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 722 | */ |
AnnaBridge | 171:3a7713b1edbc | 723 | #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4)) |
AnnaBridge | 171:3a7713b1edbc | 724 | /** |
AnnaBridge | 171:3a7713b1edbc | 725 | * @} |
AnnaBridge | 171:3a7713b1edbc | 726 | */ |
AnnaBridge | 171:3a7713b1edbc | 727 | #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ |
AnnaBridge | 171:3a7713b1edbc | 728 | ((MODE) == QSPI_MATCH_MODE_OR)) |
AnnaBridge | 171:3a7713b1edbc | 729 | |
AnnaBridge | 171:3a7713b1edbc | 730 | #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 731 | ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 732 | |
AnnaBridge | 171:3a7713b1edbc | 733 | #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ |
AnnaBridge | 171:3a7713b1edbc | 734 | ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) |
AnnaBridge | 171:3a7713b1edbc | 735 | |
AnnaBridge | 171:3a7713b1edbc | 736 | /** @defgroup QSPI_TimeOutPeriod QSPI TimeOut Period |
AnnaBridge | 171:3a7713b1edbc | 737 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 738 | */ |
AnnaBridge | 171:3a7713b1edbc | 739 | #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF) |
AnnaBridge | 171:3a7713b1edbc | 740 | /** |
AnnaBridge | 171:3a7713b1edbc | 741 | * @} |
AnnaBridge | 171:3a7713b1edbc | 742 | */ |
AnnaBridge | 171:3a7713b1edbc | 743 | |
AnnaBridge | 171:3a7713b1edbc | 744 | #define IS_QSPI_GET_FLAG(FLAG) (((FLAG) == QSPI_FLAG_BUSY) || \ |
AnnaBridge | 171:3a7713b1edbc | 745 | ((FLAG) == QSPI_FLAG_TO) || \ |
AnnaBridge | 171:3a7713b1edbc | 746 | ((FLAG) == QSPI_FLAG_SM) || \ |
AnnaBridge | 171:3a7713b1edbc | 747 | ((FLAG) == QSPI_FLAG_FT) || \ |
AnnaBridge | 171:3a7713b1edbc | 748 | ((FLAG) == QSPI_FLAG_TC) || \ |
AnnaBridge | 171:3a7713b1edbc | 749 | ((FLAG) == QSPI_FLAG_TE)) |
AnnaBridge | 171:3a7713b1edbc | 750 | |
AnnaBridge | 171:3a7713b1edbc | 751 | #define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U)) |
AnnaBridge | 171:3a7713b1edbc | 752 | /** |
AnnaBridge | 171:3a7713b1edbc | 753 | * @} |
AnnaBridge | 171:3a7713b1edbc | 754 | */ |
AnnaBridge | 171:3a7713b1edbc | 755 | |
AnnaBridge | 171:3a7713b1edbc | 756 | /* Private functions ---------------------------------------------------------*/ |
AnnaBridge | 171:3a7713b1edbc | 757 | /** @defgroup QSPI_Private_Functions QSPI Private Functions |
AnnaBridge | 171:3a7713b1edbc | 758 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 759 | */ |
AnnaBridge | 171:3a7713b1edbc | 760 | |
AnnaBridge | 171:3a7713b1edbc | 761 | /** |
AnnaBridge | 171:3a7713b1edbc | 762 | * @} |
AnnaBridge | 171:3a7713b1edbc | 763 | */ |
AnnaBridge | 171:3a7713b1edbc | 764 | |
AnnaBridge | 171:3a7713b1edbc | 765 | /** |
AnnaBridge | 171:3a7713b1edbc | 766 | * @} |
AnnaBridge | 171:3a7713b1edbc | 767 | */ |
AnnaBridge | 171:3a7713b1edbc | 768 | |
AnnaBridge | 171:3a7713b1edbc | 769 | /** |
AnnaBridge | 171:3a7713b1edbc | 770 | * @} |
AnnaBridge | 171:3a7713b1edbc | 771 | */ |
AnnaBridge | 171:3a7713b1edbc | 772 | |
AnnaBridge | 171:3a7713b1edbc | 773 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 774 | } |
AnnaBridge | 171:3a7713b1edbc | 775 | #endif |
AnnaBridge | 171:3a7713b1edbc | 776 | |
AnnaBridge | 171:3a7713b1edbc | 777 | #endif /* __STM32F7xx_HAL_QSPI_H */ |
AnnaBridge | 171:3a7713b1edbc | 778 | |
AnnaBridge | 171:3a7713b1edbc | 779 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |