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TARGET_NUCLEO_F031K6/TOOLCHAIN_IAR/stm32f031x6.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file stm32f031x6.h
AnnaBridge 171:3a7713b1edbc 4 * @author MCD Application Team
AnnaBridge 171:3a7713b1edbc 5 * @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
AnnaBridge 171:3a7713b1edbc 6 * This file contains all the peripheral register's definitions, bits
AnnaBridge 171:3a7713b1edbc 7 * definitions and memory mapping for STM32F0xx devices.
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * This file contains:
AnnaBridge 171:3a7713b1edbc 10 * - Data structures and the address mapping for all peripherals
AnnaBridge 171:3a7713b1edbc 11 * - Peripheral's registers declarations and bits definition
AnnaBridge 171:3a7713b1edbc 12 * - Macros to access peripheral’s registers hardware
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 15 * @attention
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 20 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 21 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 22 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 24 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 25 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 171:3a7713b1edbc 27 * may be used to endorse or promote products derived from this software
AnnaBridge 171:3a7713b1edbc 28 * without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 29 *
AnnaBridge 171:3a7713b1edbc 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 171:3a7713b1edbc 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 171:3a7713b1edbc 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 171:3a7713b1edbc 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 171:3a7713b1edbc 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 171:3a7713b1edbc 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 171:3a7713b1edbc 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 171:3a7713b1edbc 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 40 *
AnnaBridge 171:3a7713b1edbc 41 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 /** @addtogroup CMSIS
AnnaBridge 171:3a7713b1edbc 45 * @{
AnnaBridge 171:3a7713b1edbc 46 */
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /** @addtogroup stm32f031x6
AnnaBridge 171:3a7713b1edbc 49 * @{
AnnaBridge 171:3a7713b1edbc 50 */
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52 #ifndef __STM32F031x6_H
AnnaBridge 171:3a7713b1edbc 53 #define __STM32F031x6_H
AnnaBridge 171:3a7713b1edbc 54
AnnaBridge 171:3a7713b1edbc 55 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 56 extern "C" {
AnnaBridge 171:3a7713b1edbc 57 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 58
AnnaBridge 171:3a7713b1edbc 59 /** @addtogroup Configuration_section_for_CMSIS
AnnaBridge 171:3a7713b1edbc 60 * @{
AnnaBridge 171:3a7713b1edbc 61 */
AnnaBridge 171:3a7713b1edbc 62 /**
AnnaBridge 171:3a7713b1edbc 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
AnnaBridge 171:3a7713b1edbc 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
AnnaBridge 171:3a7713b1edbc 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
AnnaBridge 171:3a7713b1edbc 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 /**
AnnaBridge 171:3a7713b1edbc 71 * @}
AnnaBridge 171:3a7713b1edbc 72 */
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /** @addtogroup Peripheral_interrupt_number_definition
AnnaBridge 171:3a7713b1edbc 75 * @{
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /**
AnnaBridge 171:3a7713b1edbc 79 * @brief STM32F0xx Interrupt Number Definition, according to the selected device
AnnaBridge 171:3a7713b1edbc 80 * in @ref Library_configuration_section
AnnaBridge 171:3a7713b1edbc 81 */
AnnaBridge 171:3a7713b1edbc 82
AnnaBridge 171:3a7713b1edbc 83 /*!< Interrupt Number Definition */
AnnaBridge 171:3a7713b1edbc 84 typedef enum
AnnaBridge 171:3a7713b1edbc 85 {
AnnaBridge 171:3a7713b1edbc 86 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
AnnaBridge 171:3a7713b1edbc 87 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 88 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 89 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 90 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 91 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /****** STM32F0 specific Interrupt Numbers ******************************************************************/
AnnaBridge 171:3a7713b1edbc 94 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
AnnaBridge 171:3a7713b1edbc 95 PVD_IRQn = 1, /*!< PVD Interrupt through EXTI Lines 16 */
AnnaBridge 171:3a7713b1edbc 96 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
AnnaBridge 171:3a7713b1edbc 97 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
AnnaBridge 171:3a7713b1edbc 98 RCC_IRQn = 4, /*!< RCC global Interrupt */
AnnaBridge 171:3a7713b1edbc 99 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 100 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 101 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupt */
AnnaBridge 171:3a7713b1edbc 102 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 103 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 104 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupt */
AnnaBridge 171:3a7713b1edbc 105 ADC1_IRQn = 12, /*!< ADC1 Interrupt */
AnnaBridge 171:3a7713b1edbc 106 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupt */
AnnaBridge 171:3a7713b1edbc 107 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
AnnaBridge 171:3a7713b1edbc 108 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
AnnaBridge 171:3a7713b1edbc 109 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
AnnaBridge 171:3a7713b1edbc 110 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
AnnaBridge 171:3a7713b1edbc 111 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
AnnaBridge 171:3a7713b1edbc 112 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
AnnaBridge 171:3a7713b1edbc 113 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
AnnaBridge 171:3a7713b1edbc 114 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
AnnaBridge 171:3a7713b1edbc 115 USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
AnnaBridge 171:3a7713b1edbc 116 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /**
AnnaBridge 171:3a7713b1edbc 119 * @}
AnnaBridge 171:3a7713b1edbc 120 */
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 123 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
AnnaBridge 171:3a7713b1edbc 124 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 125
AnnaBridge 171:3a7713b1edbc 126 /** @addtogroup Peripheral_registers_structures
AnnaBridge 171:3a7713b1edbc 127 * @{
AnnaBridge 171:3a7713b1edbc 128 */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 /**
AnnaBridge 171:3a7713b1edbc 131 * @brief Analog to Digital Converter
AnnaBridge 171:3a7713b1edbc 132 */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 typedef struct
AnnaBridge 171:3a7713b1edbc 135 {
AnnaBridge 171:3a7713b1edbc 136 __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 137 __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 139 __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 140 __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 141 __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 142 uint32_t RESERVED1; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 143 uint32_t RESERVED2; /*!< Reserved, 0x1C */
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 145 uint32_t RESERVED3; /*!< Reserved, 0x24 */
AnnaBridge 171:3a7713b1edbc 146 __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 147 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
AnnaBridge 171:3a7713b1edbc 148 __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 149 } ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 typedef struct
AnnaBridge 171:3a7713b1edbc 152 {
AnnaBridge 171:3a7713b1edbc 153 __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */
AnnaBridge 171:3a7713b1edbc 154 } ADC_Common_TypeDef;
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 /**
AnnaBridge 171:3a7713b1edbc 157 * @brief CRC calculation unit
AnnaBridge 171:3a7713b1edbc 158 */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 typedef struct
AnnaBridge 171:3a7713b1edbc 161 {
AnnaBridge 171:3a7713b1edbc 162 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 163 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 164 uint8_t RESERVED0; /*!< Reserved, 0x05 */
AnnaBridge 171:3a7713b1edbc 165 uint16_t RESERVED1; /*!< Reserved, 0x06 */
AnnaBridge 171:3a7713b1edbc 166 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 167 uint32_t RESERVED2; /*!< Reserved, 0x0C */
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 169 __IO uint32_t RESERVED3; /*!< Reserved, 0x14 */
AnnaBridge 171:3a7713b1edbc 170 } CRC_TypeDef;
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 /**
AnnaBridge 171:3a7713b1edbc 173 * @brief Debug MCU
AnnaBridge 171:3a7713b1edbc 174 */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 typedef struct
AnnaBridge 171:3a7713b1edbc 177 {
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 182 }DBGMCU_TypeDef;
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 /**
AnnaBridge 171:3a7713b1edbc 185 * @brief DMA Controller
AnnaBridge 171:3a7713b1edbc 186 */
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 typedef struct
AnnaBridge 171:3a7713b1edbc 189 {
AnnaBridge 171:3a7713b1edbc 190 __IO uint32_t CCR; /*!< DMA channel x configuration register */
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
AnnaBridge 171:3a7713b1edbc 192 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
AnnaBridge 171:3a7713b1edbc 194 } DMA_Channel_TypeDef;
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 typedef struct
AnnaBridge 171:3a7713b1edbc 197 {
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 199 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 200 } DMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 /**
AnnaBridge 171:3a7713b1edbc 203 * @brief External Interrupt/Event Controller
AnnaBridge 171:3a7713b1edbc 204 */
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 typedef struct
AnnaBridge 171:3a7713b1edbc 207 {
AnnaBridge 171:3a7713b1edbc 208 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 209 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 210 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 211 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 212 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 213 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 214 } EXTI_TypeDef;
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 /**
AnnaBridge 171:3a7713b1edbc 217 * @brief FLASH Registers
AnnaBridge 171:3a7713b1edbc 218 */
AnnaBridge 171:3a7713b1edbc 219 typedef struct
AnnaBridge 171:3a7713b1edbc 220 {
AnnaBridge 171:3a7713b1edbc 221 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 222 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 223 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 224 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 225 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 226 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 227 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
AnnaBridge 171:3a7713b1edbc 228 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 229 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 230 } FLASH_TypeDef;
AnnaBridge 171:3a7713b1edbc 231
AnnaBridge 171:3a7713b1edbc 232 /**
AnnaBridge 171:3a7713b1edbc 233 * @brief Option Bytes Registers
AnnaBridge 171:3a7713b1edbc 234 */
AnnaBridge 171:3a7713b1edbc 235 typedef struct
AnnaBridge 171:3a7713b1edbc 236 {
AnnaBridge 171:3a7713b1edbc 237 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 238 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
AnnaBridge 171:3a7713b1edbc 239 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 240 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
AnnaBridge 171:3a7713b1edbc 241 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 242 } OB_TypeDef;
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 /**
AnnaBridge 171:3a7713b1edbc 245 * @brief General Purpose I/O
AnnaBridge 171:3a7713b1edbc 246 */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 typedef struct
AnnaBridge 171:3a7713b1edbc 249 {
AnnaBridge 171:3a7713b1edbc 250 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 251 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 252 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 253 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
AnnaBridge 171:3a7713b1edbc 259 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 260 } GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 /**
AnnaBridge 171:3a7713b1edbc 263 * @brief SysTem Configuration
AnnaBridge 171:3a7713b1edbc 264 */
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 typedef struct
AnnaBridge 171:3a7713b1edbc 267 {
AnnaBridge 171:3a7713b1edbc 268 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 269 uint32_t RESERVED; /*!< Reserved, 0x04 */
AnnaBridge 171:3a7713b1edbc 270 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
AnnaBridge 171:3a7713b1edbc 271 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 272 } SYSCFG_TypeDef;
AnnaBridge 171:3a7713b1edbc 273
AnnaBridge 171:3a7713b1edbc 274 /**
AnnaBridge 171:3a7713b1edbc 275 * @brief Inter-integrated Circuit Interface
AnnaBridge 171:3a7713b1edbc 276 */
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 typedef struct
AnnaBridge 171:3a7713b1edbc 279 {
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 282 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 283 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 284 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 285 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 286 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 287 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 288 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 289 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 290 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 291 } I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 /**
AnnaBridge 171:3a7713b1edbc 294 * @brief Independent WATCHDOG
AnnaBridge 171:3a7713b1edbc 295 */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 typedef struct
AnnaBridge 171:3a7713b1edbc 298 {
AnnaBridge 171:3a7713b1edbc 299 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 300 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 301 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 302 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 303 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 304 } IWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 /**
AnnaBridge 171:3a7713b1edbc 307 * @brief Power Control
AnnaBridge 171:3a7713b1edbc 308 */
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 typedef struct
AnnaBridge 171:3a7713b1edbc 311 {
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 314 } PWR_TypeDef;
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /**
AnnaBridge 171:3a7713b1edbc 317 * @brief Reset and Clock Control
AnnaBridge 171:3a7713b1edbc 318 */
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 typedef struct
AnnaBridge 171:3a7713b1edbc 321 {
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 324 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 325 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 326 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 327 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 328 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 329 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 330 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 331 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 332 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 334 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 336 } RCC_TypeDef;
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 /**
AnnaBridge 171:3a7713b1edbc 339 * @brief Real-Time Clock
AnnaBridge 171:3a7713b1edbc 340 */
AnnaBridge 171:3a7713b1edbc 341 typedef struct
AnnaBridge 171:3a7713b1edbc 342 {
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 348 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 349 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 350 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 351 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 354 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 356 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 357 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 358 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 359 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 360 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 361 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 362 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 364 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 366 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 367 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 368 } RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 369
AnnaBridge 171:3a7713b1edbc 370 /**
AnnaBridge 171:3a7713b1edbc 371 * @brief Serial Peripheral Interface
AnnaBridge 171:3a7713b1edbc 372 */
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 typedef struct
AnnaBridge 171:3a7713b1edbc 375 {
AnnaBridge 171:3a7713b1edbc 376 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 377 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 378 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 379 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 380 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 381 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 382 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 383 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 385 } SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 386
AnnaBridge 171:3a7713b1edbc 387 /**
AnnaBridge 171:3a7713b1edbc 388 * @brief TIM
AnnaBridge 171:3a7713b1edbc 389 */
AnnaBridge 171:3a7713b1edbc 390 typedef struct
AnnaBridge 171:3a7713b1edbc 391 {
AnnaBridge 171:3a7713b1edbc 392 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 393 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 394 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 395 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 396 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 397 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 399 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 400 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 401 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 402 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 403 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 404 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 405 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 406 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 407 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 409 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 410 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 411 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 412 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 413 } TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 /**
AnnaBridge 171:3a7713b1edbc 416 * @brief Universal Synchronous Asynchronous Receiver Transmitter
AnnaBridge 171:3a7713b1edbc 417 */
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 typedef struct
AnnaBridge 171:3a7713b1edbc 420 {
AnnaBridge 171:3a7713b1edbc 421 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 422 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 423 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 424 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
AnnaBridge 171:3a7713b1edbc 425 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 426 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 427 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 428 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 429 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 430 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 431 uint16_t RESERVED1; /*!< Reserved, 0x26 */
AnnaBridge 171:3a7713b1edbc 432 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 433 uint16_t RESERVED2; /*!< Reserved, 0x2A */
AnnaBridge 171:3a7713b1edbc 434 } USART_TypeDef;
AnnaBridge 171:3a7713b1edbc 435
AnnaBridge 171:3a7713b1edbc 436 /**
AnnaBridge 171:3a7713b1edbc 437 * @brief Window WATCHDOG
AnnaBridge 171:3a7713b1edbc 438 */
AnnaBridge 171:3a7713b1edbc 439 typedef struct
AnnaBridge 171:3a7713b1edbc 440 {
AnnaBridge 171:3a7713b1edbc 441 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
AnnaBridge 171:3a7713b1edbc 443 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
AnnaBridge 171:3a7713b1edbc 444 } WWDG_TypeDef;
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446 /**
AnnaBridge 171:3a7713b1edbc 447 * @}
AnnaBridge 171:3a7713b1edbc 448 */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 /** @addtogroup Peripheral_memory_map
AnnaBridge 171:3a7713b1edbc 451 * @{
AnnaBridge 171:3a7713b1edbc 452 */
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
AnnaBridge 171:3a7713b1edbc 455 #define FLASH_BANK1_END ((uint32_t)0x08007FFFU) /*!< FLASH END address of bank1 */
AnnaBridge 171:3a7713b1edbc 456 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
AnnaBridge 171:3a7713b1edbc 457 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459 /*!< Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 460 #define APBPERIPH_BASE PERIPH_BASE
AnnaBridge 171:3a7713b1edbc 461 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
AnnaBridge 171:3a7713b1edbc 462 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 /*!< APB peripherals */
AnnaBridge 171:3a7713b1edbc 465 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
AnnaBridge 171:3a7713b1edbc 466 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
AnnaBridge 171:3a7713b1edbc 467 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
AnnaBridge 171:3a7713b1edbc 468 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
AnnaBridge 171:3a7713b1edbc 469 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
AnnaBridge 171:3a7713b1edbc 470 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
AnnaBridge 171:3a7713b1edbc 471 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
AnnaBridge 171:3a7713b1edbc 472 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
AnnaBridge 171:3a7713b1edbc 473 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
AnnaBridge 171:3a7713b1edbc 474 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
AnnaBridge 171:3a7713b1edbc 475 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
AnnaBridge 171:3a7713b1edbc 476 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
AnnaBridge 171:3a7713b1edbc 477 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
AnnaBridge 171:3a7713b1edbc 478 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
AnnaBridge 171:3a7713b1edbc 479 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
AnnaBridge 171:3a7713b1edbc 480 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
AnnaBridge 171:3a7713b1edbc 481 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
AnnaBridge 171:3a7713b1edbc 482 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 /*!< AHB peripherals */
AnnaBridge 171:3a7713b1edbc 485 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
AnnaBridge 171:3a7713b1edbc 486 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
AnnaBridge 171:3a7713b1edbc 487 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
AnnaBridge 171:3a7713b1edbc 488 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
AnnaBridge 171:3a7713b1edbc 489 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
AnnaBridge 171:3a7713b1edbc 490 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
AnnaBridge 171:3a7713b1edbc 493 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
AnnaBridge 171:3a7713b1edbc 494 #define OB_BASE ((uint32_t)0x1FFFF800U) /*!< FLASH Option Bytes base address */
AnnaBridge 171:3a7713b1edbc 495 #define FLASHSIZE_BASE ((uint32_t)0x1FFFF7CCU) /*!< FLASH Size register base address */
AnnaBridge 171:3a7713b1edbc 496 #define UID_BASE ((uint32_t)0x1FFFF7ACU) /*!< Unique device ID register base address */
AnnaBridge 171:3a7713b1edbc 497 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
AnnaBridge 171:3a7713b1edbc 498
AnnaBridge 171:3a7713b1edbc 499 /*!< AHB2 peripherals */
AnnaBridge 171:3a7713b1edbc 500 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
AnnaBridge 171:3a7713b1edbc 501 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
AnnaBridge 171:3a7713b1edbc 502 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
AnnaBridge 171:3a7713b1edbc 503 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /**
AnnaBridge 171:3a7713b1edbc 506 * @}
AnnaBridge 171:3a7713b1edbc 507 */
AnnaBridge 171:3a7713b1edbc 508
AnnaBridge 171:3a7713b1edbc 509 /** @addtogroup Peripheral_declaration
AnnaBridge 171:3a7713b1edbc 510 * @{
AnnaBridge 171:3a7713b1edbc 511 */
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
AnnaBridge 171:3a7713b1edbc 514 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
AnnaBridge 171:3a7713b1edbc 515 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
AnnaBridge 171:3a7713b1edbc 516 #define RTC ((RTC_TypeDef *) RTC_BASE)
AnnaBridge 171:3a7713b1edbc 517 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
AnnaBridge 171:3a7713b1edbc 518 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
AnnaBridge 171:3a7713b1edbc 519 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 520 #define PWR ((PWR_TypeDef *) PWR_BASE)
AnnaBridge 171:3a7713b1edbc 521 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
AnnaBridge 171:3a7713b1edbc 522 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
AnnaBridge 171:3a7713b1edbc 523 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 524 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
AnnaBridge 171:3a7713b1edbc 525 #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */
AnnaBridge 171:3a7713b1edbc 526 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
AnnaBridge 171:3a7713b1edbc 527 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 528 #define USART1 ((USART_TypeDef *) USART1_BASE)
AnnaBridge 171:3a7713b1edbc 529 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
AnnaBridge 171:3a7713b1edbc 530 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
AnnaBridge 171:3a7713b1edbc 531 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
AnnaBridge 171:3a7713b1edbc 532 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
AnnaBridge 171:3a7713b1edbc 533 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
AnnaBridge 171:3a7713b1edbc 534 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
AnnaBridge 171:3a7713b1edbc 535 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
AnnaBridge 171:3a7713b1edbc 536 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
AnnaBridge 171:3a7713b1edbc 537 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
AnnaBridge 171:3a7713b1edbc 538 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
AnnaBridge 171:3a7713b1edbc 539 #define OB ((OB_TypeDef *) OB_BASE)
AnnaBridge 171:3a7713b1edbc 540 #define RCC ((RCC_TypeDef *) RCC_BASE)
AnnaBridge 171:3a7713b1edbc 541 #define CRC ((CRC_TypeDef *) CRC_BASE)
AnnaBridge 171:3a7713b1edbc 542 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 543 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 544 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 545 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
AnnaBridge 171:3a7713b1edbc 546 /**
AnnaBridge 171:3a7713b1edbc 547 * @}
AnnaBridge 171:3a7713b1edbc 548 */
AnnaBridge 171:3a7713b1edbc 549
AnnaBridge 171:3a7713b1edbc 550 /** @addtogroup Exported_constants
AnnaBridge 171:3a7713b1edbc 551 * @{
AnnaBridge 171:3a7713b1edbc 552 */
AnnaBridge 171:3a7713b1edbc 553
AnnaBridge 171:3a7713b1edbc 554 /** @addtogroup Peripheral_Registers_Bits_Definition
AnnaBridge 171:3a7713b1edbc 555 * @{
AnnaBridge 171:3a7713b1edbc 556 */
AnnaBridge 171:3a7713b1edbc 557
AnnaBridge 171:3a7713b1edbc 558 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 559 /* Peripheral Registers Bits Definition */
AnnaBridge 171:3a7713b1edbc 560 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 563 /* */
AnnaBridge 171:3a7713b1edbc 564 /* Analog to Digital Converter (ADC) */
AnnaBridge 171:3a7713b1edbc 565 /* */
AnnaBridge 171:3a7713b1edbc 566 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 567
AnnaBridge 171:3a7713b1edbc 568 /*
AnnaBridge 171:3a7713b1edbc 569 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 570 */
AnnaBridge 171:3a7713b1edbc 571 #define ADC_CHANNEL_VBAT_SUPPORT /*!< ADC feature available only on specific devices: ADC internal channel Vbat */
AnnaBridge 171:3a7713b1edbc 572
AnnaBridge 171:3a7713b1edbc 573 /******************** Bits definition for ADC_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 574 #define ADC_ISR_ADRDY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 575 #define ADC_ISR_ADRDY_Msk (0x1U << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 576 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC ready flag */
AnnaBridge 171:3a7713b1edbc 577 #define ADC_ISR_EOSMP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 578 #define ADC_ISR_EOSMP_Msk (0x1U << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 579 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */
AnnaBridge 171:3a7713b1edbc 580 #define ADC_ISR_EOC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 581 #define ADC_ISR_EOC_Msk (0x1U << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 582 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */
AnnaBridge 171:3a7713b1edbc 583 #define ADC_ISR_EOS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 584 #define ADC_ISR_EOS_Msk (0x1U << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 585 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC group regular end of sequence conversions flag */
AnnaBridge 171:3a7713b1edbc 586 #define ADC_ISR_OVR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 587 #define ADC_ISR_OVR_Msk (0x1U << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 588 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */
AnnaBridge 171:3a7713b1edbc 589 #define ADC_ISR_AWD1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 590 #define ADC_ISR_AWD1_Msk (0x1U << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 591 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC analog watchdog 1 flag */
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 594 #define ADC_ISR_AWD (ADC_ISR_AWD1)
AnnaBridge 171:3a7713b1edbc 595 #define ADC_ISR_EOSEQ (ADC_ISR_EOS)
AnnaBridge 171:3a7713b1edbc 596
AnnaBridge 171:3a7713b1edbc 597 /******************** Bits definition for ADC_IER register ******************/
AnnaBridge 171:3a7713b1edbc 598 #define ADC_IER_ADRDYIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 599 #define ADC_IER_ADRDYIE_Msk (0x1U << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 600 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC ready interrupt */
AnnaBridge 171:3a7713b1edbc 601 #define ADC_IER_EOSMPIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 602 #define ADC_IER_EOSMPIE_Msk (0x1U << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 603 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */
AnnaBridge 171:3a7713b1edbc 604 #define ADC_IER_EOCIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 605 #define ADC_IER_EOCIE_Msk (0x1U << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 606 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */
AnnaBridge 171:3a7713b1edbc 607 #define ADC_IER_EOSIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 608 #define ADC_IER_EOSIE_Msk (0x1U << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 609 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC group regular end of sequence conversions interrupt */
AnnaBridge 171:3a7713b1edbc 610 #define ADC_IER_OVRIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 611 #define ADC_IER_OVRIE_Msk (0x1U << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 612 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */
AnnaBridge 171:3a7713b1edbc 613 #define ADC_IER_AWD1IE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 614 #define ADC_IER_AWD1IE_Msk (0x1U << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 615 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC analog watchdog 1 interrupt */
AnnaBridge 171:3a7713b1edbc 616
AnnaBridge 171:3a7713b1edbc 617 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 618 #define ADC_IER_AWDIE (ADC_IER_AWD1IE)
AnnaBridge 171:3a7713b1edbc 619 #define ADC_IER_EOSEQIE (ADC_IER_EOSIE)
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 /******************** Bits definition for ADC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 622 #define ADC_CR_ADEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 623 #define ADC_CR_ADEN_Msk (0x1U << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 624 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */
AnnaBridge 171:3a7713b1edbc 625 #define ADC_CR_ADDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 626 #define ADC_CR_ADDIS_Msk (0x1U << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 627 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC disable */
AnnaBridge 171:3a7713b1edbc 628 #define ADC_CR_ADSTART_Pos (2U)
AnnaBridge 171:3a7713b1edbc 629 #define ADC_CR_ADSTART_Msk (0x1U << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 630 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */
AnnaBridge 171:3a7713b1edbc 631 #define ADC_CR_ADSTP_Pos (4U)
AnnaBridge 171:3a7713b1edbc 632 #define ADC_CR_ADSTP_Msk (0x1U << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 633 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */
AnnaBridge 171:3a7713b1edbc 634 #define ADC_CR_ADCAL_Pos (31U)
AnnaBridge 171:3a7713b1edbc 635 #define ADC_CR_ADCAL_Msk (0x1U << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 636 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /******************* Bits definition for ADC_CFGR1 register *****************/
AnnaBridge 171:3a7713b1edbc 639 #define ADC_CFGR1_DMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 640 #define ADC_CFGR1_DMAEN_Msk (0x1U << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 641 #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */
AnnaBridge 171:3a7713b1edbc 642 #define ADC_CFGR1_DMACFG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 643 #define ADC_CFGR1_DMACFG_Msk (0x1U << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 644 #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */
AnnaBridge 171:3a7713b1edbc 645 #define ADC_CFGR1_SCANDIR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 646 #define ADC_CFGR1_SCANDIR_Msk (0x1U << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 647 #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */
AnnaBridge 171:3a7713b1edbc 648
AnnaBridge 171:3a7713b1edbc 649 #define ADC_CFGR1_RES_Pos (3U)
AnnaBridge 171:3a7713b1edbc 650 #define ADC_CFGR1_RES_Msk (0x3U << ADC_CFGR1_RES_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 651 #define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC data resolution */
AnnaBridge 171:3a7713b1edbc 652 #define ADC_CFGR1_RES_0 (0x1U << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 653 #define ADC_CFGR1_RES_1 (0x2U << ADC_CFGR1_RES_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 #define ADC_CFGR1_ALIGN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 656 #define ADC_CFGR1_ALIGN_Msk (0x1U << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 657 #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 #define ADC_CFGR1_EXTSEL_Pos (6U)
AnnaBridge 171:3a7713b1edbc 660 #define ADC_CFGR1_EXTSEL_Msk (0x7U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */
AnnaBridge 171:3a7713b1edbc 661 #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */
AnnaBridge 171:3a7713b1edbc 662 #define ADC_CFGR1_EXTSEL_0 (0x1U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 663 #define ADC_CFGR1_EXTSEL_1 (0x2U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 664 #define ADC_CFGR1_EXTSEL_2 (0x4U << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 #define ADC_CFGR1_EXTEN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 667 #define ADC_CFGR1_EXTEN_Msk (0x3U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 668 #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */
AnnaBridge 171:3a7713b1edbc 669 #define ADC_CFGR1_EXTEN_0 (0x1U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 670 #define ADC_CFGR1_EXTEN_1 (0x2U << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 671
AnnaBridge 171:3a7713b1edbc 672 #define ADC_CFGR1_OVRMOD_Pos (12U)
AnnaBridge 171:3a7713b1edbc 673 #define ADC_CFGR1_OVRMOD_Msk (0x1U << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 674 #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */
AnnaBridge 171:3a7713b1edbc 675 #define ADC_CFGR1_CONT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 676 #define ADC_CFGR1_CONT_Msk (0x1U << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 677 #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */
AnnaBridge 171:3a7713b1edbc 678 #define ADC_CFGR1_WAIT_Pos (14U)
AnnaBridge 171:3a7713b1edbc 679 #define ADC_CFGR1_WAIT_Msk (0x1U << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 680 #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */
AnnaBridge 171:3a7713b1edbc 681 #define ADC_CFGR1_AUTOFF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 682 #define ADC_CFGR1_AUTOFF_Msk (0x1U << ADC_CFGR1_AUTOFF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 683 #define ADC_CFGR1_AUTOFF ADC_CFGR1_AUTOFF_Msk /*!< ADC low power auto power off */
AnnaBridge 171:3a7713b1edbc 684 #define ADC_CFGR1_DISCEN_Pos (16U)
AnnaBridge 171:3a7713b1edbc 685 #define ADC_CFGR1_DISCEN_Msk (0x1U << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 686 #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */
AnnaBridge 171:3a7713b1edbc 687
AnnaBridge 171:3a7713b1edbc 688 #define ADC_CFGR1_AWD1SGL_Pos (22U)
AnnaBridge 171:3a7713b1edbc 689 #define ADC_CFGR1_AWD1SGL_Msk (0x1U << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 690 #define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */
AnnaBridge 171:3a7713b1edbc 691 #define ADC_CFGR1_AWD1EN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 692 #define ADC_CFGR1_AWD1EN_Msk (0x1U << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 693 #define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */
AnnaBridge 171:3a7713b1edbc 694
AnnaBridge 171:3a7713b1edbc 695 #define ADC_CFGR1_AWD1CH_Pos (26U)
AnnaBridge 171:3a7713b1edbc 696 #define ADC_CFGR1_AWD1CH_Msk (0x1FU << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */
AnnaBridge 171:3a7713b1edbc 697 #define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC analog watchdog 1 monitored channel selection */
AnnaBridge 171:3a7713b1edbc 698 #define ADC_CFGR1_AWD1CH_0 (0x01U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 699 #define ADC_CFGR1_AWD1CH_1 (0x02U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 700 #define ADC_CFGR1_AWD1CH_2 (0x04U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 701 #define ADC_CFGR1_AWD1CH_3 (0x08U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 702 #define ADC_CFGR1_AWD1CH_4 (0x10U << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 703
AnnaBridge 171:3a7713b1edbc 704 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 705 #define ADC_CFGR1_AUTDLY (ADC_CFGR1_WAIT)
AnnaBridge 171:3a7713b1edbc 706 #define ADC_CFGR1_AWDSGL (ADC_CFGR1_AWD1SGL)
AnnaBridge 171:3a7713b1edbc 707 #define ADC_CFGR1_AWDEN (ADC_CFGR1_AWD1EN)
AnnaBridge 171:3a7713b1edbc 708 #define ADC_CFGR1_AWDCH (ADC_CFGR1_AWD1CH)
AnnaBridge 171:3a7713b1edbc 709 #define ADC_CFGR1_AWDCH_0 (ADC_CFGR1_AWD1CH_0)
AnnaBridge 171:3a7713b1edbc 710 #define ADC_CFGR1_AWDCH_1 (ADC_CFGR1_AWD1CH_1)
AnnaBridge 171:3a7713b1edbc 711 #define ADC_CFGR1_AWDCH_2 (ADC_CFGR1_AWD1CH_2)
AnnaBridge 171:3a7713b1edbc 712 #define ADC_CFGR1_AWDCH_3 (ADC_CFGR1_AWD1CH_3)
AnnaBridge 171:3a7713b1edbc 713 #define ADC_CFGR1_AWDCH_4 (ADC_CFGR1_AWD1CH_4)
AnnaBridge 171:3a7713b1edbc 714
AnnaBridge 171:3a7713b1edbc 715 /******************* Bits definition for ADC_CFGR2 register *****************/
AnnaBridge 171:3a7713b1edbc 716 #define ADC_CFGR2_CKMODE_Pos (30U)
AnnaBridge 171:3a7713b1edbc 717 #define ADC_CFGR2_CKMODE_Msk (0x3U << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 718 #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */
AnnaBridge 171:3a7713b1edbc 719 #define ADC_CFGR2_CKMODE_1 (0x2U << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 720 #define ADC_CFGR2_CKMODE_0 (0x1U << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 721
AnnaBridge 171:3a7713b1edbc 722 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 723 #define ADC_CFGR2_JITOFFDIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC clocked by PCLK div4 */
AnnaBridge 171:3a7713b1edbc 724 #define ADC_CFGR2_JITOFFDIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC clocked by PCLK div2 */
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726 /****************** Bit definition for ADC_SMPR register ********************/
AnnaBridge 171:3a7713b1edbc 727 #define ADC_SMPR_SMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 728 #define ADC_SMPR_SMP_Msk (0x7U << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 729 #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */
AnnaBridge 171:3a7713b1edbc 730 #define ADC_SMPR_SMP_0 (0x1U << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 731 #define ADC_SMPR_SMP_1 (0x2U << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 732 #define ADC_SMPR_SMP_2 (0x4U << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 733
AnnaBridge 171:3a7713b1edbc 734 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 735 #define ADC_SMPR1_SMPR (ADC_SMPR_SMP) /*!< SMP[2:0] bits (Sampling time selection) */
AnnaBridge 171:3a7713b1edbc 736 #define ADC_SMPR1_SMPR_0 (ADC_SMPR_SMP_0) /*!< bit 0 */
AnnaBridge 171:3a7713b1edbc 737 #define ADC_SMPR1_SMPR_1 (ADC_SMPR_SMP_1) /*!< bit 1 */
AnnaBridge 171:3a7713b1edbc 738 #define ADC_SMPR1_SMPR_2 (ADC_SMPR_SMP_2) /*!< bit 2 */
AnnaBridge 171:3a7713b1edbc 739
AnnaBridge 171:3a7713b1edbc 740 /******************* Bit definition for ADC_TR register ********************/
AnnaBridge 171:3a7713b1edbc 741 #define ADC_TR1_LT1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 742 #define ADC_TR1_LT1_Msk (0xFFFU << ADC_TR1_LT1_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 743 #define ADC_TR1_LT1 ADC_TR1_LT1_Msk /*!< ADC analog watchdog 1 threshold low */
AnnaBridge 171:3a7713b1edbc 744 #define ADC_TR1_LT1_0 (0x001U << ADC_TR1_LT1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 745 #define ADC_TR1_LT1_1 (0x002U << ADC_TR1_LT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 746 #define ADC_TR1_LT1_2 (0x004U << ADC_TR1_LT1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 747 #define ADC_TR1_LT1_3 (0x008U << ADC_TR1_LT1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 748 #define ADC_TR1_LT1_4 (0x010U << ADC_TR1_LT1_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 749 #define ADC_TR1_LT1_5 (0x020U << ADC_TR1_LT1_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 750 #define ADC_TR1_LT1_6 (0x040U << ADC_TR1_LT1_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 751 #define ADC_TR1_LT1_7 (0x080U << ADC_TR1_LT1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 752 #define ADC_TR1_LT1_8 (0x100U << ADC_TR1_LT1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 753 #define ADC_TR1_LT1_9 (0x200U << ADC_TR1_LT1_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 754 #define ADC_TR1_LT1_10 (0x400U << ADC_TR1_LT1_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 755 #define ADC_TR1_LT1_11 (0x800U << ADC_TR1_LT1_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 756
AnnaBridge 171:3a7713b1edbc 757 #define ADC_TR1_HT1_Pos (16U)
AnnaBridge 171:3a7713b1edbc 758 #define ADC_TR1_HT1_Msk (0xFFFU << ADC_TR1_HT1_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 759 #define ADC_TR1_HT1 ADC_TR1_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */
AnnaBridge 171:3a7713b1edbc 760 #define ADC_TR1_HT1_0 (0x001U << ADC_TR1_HT1_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 761 #define ADC_TR1_HT1_1 (0x002U << ADC_TR1_HT1_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 762 #define ADC_TR1_HT1_2 (0x004U << ADC_TR1_HT1_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 763 #define ADC_TR1_HT1_3 (0x008U << ADC_TR1_HT1_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 764 #define ADC_TR1_HT1_4 (0x010U << ADC_TR1_HT1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 765 #define ADC_TR1_HT1_5 (0x020U << ADC_TR1_HT1_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 766 #define ADC_TR1_HT1_6 (0x040U << ADC_TR1_HT1_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 767 #define ADC_TR1_HT1_7 (0x080U << ADC_TR1_HT1_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 768 #define ADC_TR1_HT1_8 (0x100U << ADC_TR1_HT1_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 769 #define ADC_TR1_HT1_9 (0x200U << ADC_TR1_HT1_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 770 #define ADC_TR1_HT1_10 (0x400U << ADC_TR1_HT1_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 771 #define ADC_TR1_HT1_11 (0x800U << ADC_TR1_HT1_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 772
AnnaBridge 171:3a7713b1edbc 773 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 774 #define ADC_TR_HT (ADC_TR1_HT1)
AnnaBridge 171:3a7713b1edbc 775 #define ADC_TR_LT (ADC_TR1_LT1)
AnnaBridge 171:3a7713b1edbc 776 #define ADC_HTR_HT (ADC_TR1_HT1)
AnnaBridge 171:3a7713b1edbc 777 #define ADC_LTR_LT (ADC_TR1_LT1)
AnnaBridge 171:3a7713b1edbc 778
AnnaBridge 171:3a7713b1edbc 779 /****************** Bit definition for ADC_CHSELR register ******************/
AnnaBridge 171:3a7713b1edbc 780 #define ADC_CHSELR_CHSEL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 781 #define ADC_CHSELR_CHSEL_Msk (0x7FFFFU << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */
AnnaBridge 171:3a7713b1edbc 782 #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 783 #define ADC_CHSELR_CHSEL18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 784 #define ADC_CHSELR_CHSEL18_Msk (0x1U << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 785 #define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 786 #define ADC_CHSELR_CHSEL17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 787 #define ADC_CHSELR_CHSEL17_Msk (0x1U << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 788 #define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 789 #define ADC_CHSELR_CHSEL16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 790 #define ADC_CHSELR_CHSEL16_Msk (0x1U << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 791 #define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 792 #define ADC_CHSELR_CHSEL15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 793 #define ADC_CHSELR_CHSEL15_Msk (0x1U << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 794 #define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 795 #define ADC_CHSELR_CHSEL14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 796 #define ADC_CHSELR_CHSEL14_Msk (0x1U << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 797 #define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 798 #define ADC_CHSELR_CHSEL13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 799 #define ADC_CHSELR_CHSEL13_Msk (0x1U << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 800 #define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 801 #define ADC_CHSELR_CHSEL12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 802 #define ADC_CHSELR_CHSEL12_Msk (0x1U << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 803 #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 804 #define ADC_CHSELR_CHSEL11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 805 #define ADC_CHSELR_CHSEL11_Msk (0x1U << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 806 #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 807 #define ADC_CHSELR_CHSEL10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 808 #define ADC_CHSELR_CHSEL10_Msk (0x1U << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 809 #define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 810 #define ADC_CHSELR_CHSEL9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 811 #define ADC_CHSELR_CHSEL9_Msk (0x1U << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 812 #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 813 #define ADC_CHSELR_CHSEL8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 814 #define ADC_CHSELR_CHSEL8_Msk (0x1U << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 815 #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 816 #define ADC_CHSELR_CHSEL7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 817 #define ADC_CHSELR_CHSEL7_Msk (0x1U << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 818 #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 819 #define ADC_CHSELR_CHSEL6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 820 #define ADC_CHSELR_CHSEL6_Msk (0x1U << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 821 #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 822 #define ADC_CHSELR_CHSEL5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 823 #define ADC_CHSELR_CHSEL5_Msk (0x1U << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 824 #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 825 #define ADC_CHSELR_CHSEL4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 826 #define ADC_CHSELR_CHSEL4_Msk (0x1U << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 827 #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 828 #define ADC_CHSELR_CHSEL3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 829 #define ADC_CHSELR_CHSEL3_Msk (0x1U << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 830 #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 831 #define ADC_CHSELR_CHSEL2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 832 #define ADC_CHSELR_CHSEL2_Msk (0x1U << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 833 #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 834 #define ADC_CHSELR_CHSEL1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 835 #define ADC_CHSELR_CHSEL1_Msk (0x1U << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 836 #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 837 #define ADC_CHSELR_CHSEL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 838 #define ADC_CHSELR_CHSEL0_Msk (0x1U << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 839 #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */
AnnaBridge 171:3a7713b1edbc 840
AnnaBridge 171:3a7713b1edbc 841 /******************** Bit definition for ADC_DR register ********************/
AnnaBridge 171:3a7713b1edbc 842 #define ADC_DR_DATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 843 #define ADC_DR_DATA_Msk (0xFFFFU << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 844 #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */
AnnaBridge 171:3a7713b1edbc 845 #define ADC_DR_DATA_0 (0x0001U << ADC_DR_DATA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 846 #define ADC_DR_DATA_1 (0x0002U << ADC_DR_DATA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 847 #define ADC_DR_DATA_2 (0x0004U << ADC_DR_DATA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 848 #define ADC_DR_DATA_3 (0x0008U << ADC_DR_DATA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 849 #define ADC_DR_DATA_4 (0x0010U << ADC_DR_DATA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 850 #define ADC_DR_DATA_5 (0x0020U << ADC_DR_DATA_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 851 #define ADC_DR_DATA_6 (0x0040U << ADC_DR_DATA_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 852 #define ADC_DR_DATA_7 (0x0080U << ADC_DR_DATA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 853 #define ADC_DR_DATA_8 (0x0100U << ADC_DR_DATA_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 854 #define ADC_DR_DATA_9 (0x0200U << ADC_DR_DATA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 855 #define ADC_DR_DATA_10 (0x0400U << ADC_DR_DATA_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 856 #define ADC_DR_DATA_11 (0x0800U << ADC_DR_DATA_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 857 #define ADC_DR_DATA_12 (0x1000U << ADC_DR_DATA_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 858 #define ADC_DR_DATA_13 (0x2000U << ADC_DR_DATA_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 859 #define ADC_DR_DATA_14 (0x4000U << ADC_DR_DATA_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 860 #define ADC_DR_DATA_15 (0x8000U << ADC_DR_DATA_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 861
AnnaBridge 171:3a7713b1edbc 862 /************************* ADC Common registers *****************************/
AnnaBridge 171:3a7713b1edbc 863 /******************* Bit definition for ADC_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 864 #define ADC_CCR_VREFEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 865 #define ADC_CCR_VREFEN_Msk (0x1U << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 866 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */
AnnaBridge 171:3a7713b1edbc 867 #define ADC_CCR_TSEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 868 #define ADC_CCR_TSEN_Msk (0x1U << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 869 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */
AnnaBridge 171:3a7713b1edbc 870
AnnaBridge 171:3a7713b1edbc 871 #define ADC_CCR_VBATEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 872 #define ADC_CCR_VBATEN_Msk (0x1U << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 873 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< ADC internal path to battery voltage enable */
AnnaBridge 171:3a7713b1edbc 874
AnnaBridge 171:3a7713b1edbc 875 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 876 /* */
AnnaBridge 171:3a7713b1edbc 877 /* CRC calculation unit (CRC) */
AnnaBridge 171:3a7713b1edbc 878 /* */
AnnaBridge 171:3a7713b1edbc 879 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 880 /******************* Bit definition for CRC_DR register *********************/
AnnaBridge 171:3a7713b1edbc 881 #define CRC_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 882 #define CRC_DR_DR_Msk (0xFFFFFFFFU << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 883 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
AnnaBridge 171:3a7713b1edbc 884
AnnaBridge 171:3a7713b1edbc 885 /******************* Bit definition for CRC_IDR register ********************/
AnnaBridge 171:3a7713b1edbc 886 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
AnnaBridge 171:3a7713b1edbc 887
AnnaBridge 171:3a7713b1edbc 888 /******************** Bit definition for CRC_CR register ********************/
AnnaBridge 171:3a7713b1edbc 889 #define CRC_CR_RESET_Pos (0U)
AnnaBridge 171:3a7713b1edbc 890 #define CRC_CR_RESET_Msk (0x1U << CRC_CR_RESET_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 891 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
AnnaBridge 171:3a7713b1edbc 892 #define CRC_CR_REV_IN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 893 #define CRC_CR_REV_IN_Msk (0x3U << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 894 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
AnnaBridge 171:3a7713b1edbc 895 #define CRC_CR_REV_IN_0 (0x1U << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 896 #define CRC_CR_REV_IN_1 (0x2U << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 897 #define CRC_CR_REV_OUT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 898 #define CRC_CR_REV_OUT_Msk (0x1U << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 899 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
AnnaBridge 171:3a7713b1edbc 900
AnnaBridge 171:3a7713b1edbc 901 /******************* Bit definition for CRC_INIT register *******************/
AnnaBridge 171:3a7713b1edbc 902 #define CRC_INIT_INIT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 903 #define CRC_INIT_INIT_Msk (0xFFFFFFFFU << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 904 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
AnnaBridge 171:3a7713b1edbc 905
AnnaBridge 171:3a7713b1edbc 906 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 907 /* */
AnnaBridge 171:3a7713b1edbc 908 /* Debug MCU (DBGMCU) */
AnnaBridge 171:3a7713b1edbc 909 /* */
AnnaBridge 171:3a7713b1edbc 910 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 911
AnnaBridge 171:3a7713b1edbc 912 /**************** Bit definition for DBGMCU_IDCODE register *****************/
AnnaBridge 171:3a7713b1edbc 913 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
AnnaBridge 171:3a7713b1edbc 914 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 915 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk /*!< Device Identifier */
AnnaBridge 171:3a7713b1edbc 916
AnnaBridge 171:3a7713b1edbc 917 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
AnnaBridge 171:3a7713b1edbc 918 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
AnnaBridge 171:3a7713b1edbc 919 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /*!< REV_ID[15:0] bits (Revision Identifier) */
AnnaBridge 171:3a7713b1edbc 920 #define DBGMCU_IDCODE_REV_ID_0 (0x0001U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 921 #define DBGMCU_IDCODE_REV_ID_1 (0x0002U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 922 #define DBGMCU_IDCODE_REV_ID_2 (0x0004U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 923 #define DBGMCU_IDCODE_REV_ID_3 (0x0008U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 924 #define DBGMCU_IDCODE_REV_ID_4 (0x0010U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 925 #define DBGMCU_IDCODE_REV_ID_5 (0x0020U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 926 #define DBGMCU_IDCODE_REV_ID_6 (0x0040U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 927 #define DBGMCU_IDCODE_REV_ID_7 (0x0080U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 928 #define DBGMCU_IDCODE_REV_ID_8 (0x0100U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 929 #define DBGMCU_IDCODE_REV_ID_9 (0x0200U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 930 #define DBGMCU_IDCODE_REV_ID_10 (0x0400U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 931 #define DBGMCU_IDCODE_REV_ID_11 (0x0800U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 932 #define DBGMCU_IDCODE_REV_ID_12 (0x1000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 933 #define DBGMCU_IDCODE_REV_ID_13 (0x2000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 934 #define DBGMCU_IDCODE_REV_ID_14 (0x4000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 935 #define DBGMCU_IDCODE_REV_ID_15 (0x8000U << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 936
AnnaBridge 171:3a7713b1edbc 937 /****************** Bit definition for DBGMCU_CR register *******************/
AnnaBridge 171:3a7713b1edbc 938 #define DBGMCU_CR_DBG_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 939 #define DBGMCU_CR_DBG_STOP_Msk (0x1U << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 940 #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /*!< Debug Stop Mode */
AnnaBridge 171:3a7713b1edbc 941 #define DBGMCU_CR_DBG_STANDBY_Pos (2U)
AnnaBridge 171:3a7713b1edbc 942 #define DBGMCU_CR_DBG_STANDBY_Msk (0x1U << DBGMCU_CR_DBG_STANDBY_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 943 #define DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk /*!< Debug Standby mode */
AnnaBridge 171:3a7713b1edbc 944
AnnaBridge 171:3a7713b1edbc 945 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
AnnaBridge 171:3a7713b1edbc 946 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 947 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 948 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk /*!< TIM2 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 949 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos (1U)
AnnaBridge 171:3a7713b1edbc 950 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 951 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk /*!< TIM3 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 952 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 953 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_TIM14_STOP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 954 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP_Msk /*!< TIM14 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 955 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 956 #define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 957 #define DBGMCU_APB1_FZ_DBG_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk /*!< RTC Calendar frozen when core is halted */
AnnaBridge 171:3a7713b1edbc 958 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 959 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 960 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk /*!< Debug Window Watchdog stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 961 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 962 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 963 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk /*!< Debug Independent Watchdog stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 964 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 965 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 966 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
AnnaBridge 171:3a7713b1edbc 969 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 970 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 971 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP_Msk /*!< TIM1 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 972 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos (17U)
AnnaBridge 171:3a7713b1edbc 973 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 974 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP_Msk /*!< TIM16 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 975 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 976 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 977 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP_Msk /*!< TIM17 counter stopped when core is halted */
AnnaBridge 171:3a7713b1edbc 978
AnnaBridge 171:3a7713b1edbc 979 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 980 /* */
AnnaBridge 171:3a7713b1edbc 981 /* DMA Controller (DMA) */
AnnaBridge 171:3a7713b1edbc 982 /* */
AnnaBridge 171:3a7713b1edbc 983 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 984 /******************* Bit definition for DMA_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 985 #define DMA_ISR_GIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 986 #define DMA_ISR_GIF1_Msk (0x1U << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 987 #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 988 #define DMA_ISR_TCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 989 #define DMA_ISR_TCIF1_Msk (0x1U << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 990 #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 991 #define DMA_ISR_HTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 992 #define DMA_ISR_HTIF1_Msk (0x1U << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 993 #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 994 #define DMA_ISR_TEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 995 #define DMA_ISR_TEIF1_Msk (0x1U << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 996 #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 997 #define DMA_ISR_GIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 998 #define DMA_ISR_GIF2_Msk (0x1U << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 999 #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 1000 #define DMA_ISR_TCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1001 #define DMA_ISR_TCIF2_Msk (0x1U << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1002 #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 1003 #define DMA_ISR_HTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1004 #define DMA_ISR_HTIF2_Msk (0x1U << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1005 #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 1006 #define DMA_ISR_TEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1007 #define DMA_ISR_TEIF2_Msk (0x1U << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1008 #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 1009 #define DMA_ISR_GIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1010 #define DMA_ISR_GIF3_Msk (0x1U << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1011 #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 1012 #define DMA_ISR_TCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1013 #define DMA_ISR_TCIF3_Msk (0x1U << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1014 #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 1015 #define DMA_ISR_HTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1016 #define DMA_ISR_HTIF3_Msk (0x1U << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1017 #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 1018 #define DMA_ISR_TEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1019 #define DMA_ISR_TEIF3_Msk (0x1U << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1020 #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 1021 #define DMA_ISR_GIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1022 #define DMA_ISR_GIF4_Msk (0x1U << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1023 #define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 1024 #define DMA_ISR_TCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1025 #define DMA_ISR_TCIF4_Msk (0x1U << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1026 #define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 1027 #define DMA_ISR_HTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1028 #define DMA_ISR_HTIF4_Msk (0x1U << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1029 #define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 1030 #define DMA_ISR_TEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1031 #define DMA_ISR_TEIF4_Msk (0x1U << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1032 #define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 1033 #define DMA_ISR_GIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1034 #define DMA_ISR_GIF5_Msk (0x1U << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1035 #define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
AnnaBridge 171:3a7713b1edbc 1036 #define DMA_ISR_TCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1037 #define DMA_ISR_TCIF5_Msk (0x1U << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1038 #define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
AnnaBridge 171:3a7713b1edbc 1039 #define DMA_ISR_HTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1040 #define DMA_ISR_HTIF5_Msk (0x1U << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1041 #define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
AnnaBridge 171:3a7713b1edbc 1042 #define DMA_ISR_TEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1043 #define DMA_ISR_TEIF5_Msk (0x1U << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1044 #define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
AnnaBridge 171:3a7713b1edbc 1045
AnnaBridge 171:3a7713b1edbc 1046 /******************* Bit definition for DMA_IFCR register *******************/
AnnaBridge 171:3a7713b1edbc 1047 #define DMA_IFCR_CGIF1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1048 #define DMA_IFCR_CGIF1_Msk (0x1U << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1049 #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 1050 #define DMA_IFCR_CTCIF1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1051 #define DMA_IFCR_CTCIF1_Msk (0x1U << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1052 #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 1053 #define DMA_IFCR_CHTIF1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1054 #define DMA_IFCR_CHTIF1_Msk (0x1U << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1055 #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 1056 #define DMA_IFCR_CTEIF1_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1057 #define DMA_IFCR_CTEIF1_Msk (0x1U << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1058 #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 1059 #define DMA_IFCR_CGIF2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1060 #define DMA_IFCR_CGIF2_Msk (0x1U << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1061 #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 1062 #define DMA_IFCR_CTCIF2_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1063 #define DMA_IFCR_CTCIF2_Msk (0x1U << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1064 #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 1065 #define DMA_IFCR_CHTIF2_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1066 #define DMA_IFCR_CHTIF2_Msk (0x1U << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1067 #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 1068 #define DMA_IFCR_CTEIF2_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1069 #define DMA_IFCR_CTEIF2_Msk (0x1U << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1070 #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 1071 #define DMA_IFCR_CGIF3_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1072 #define DMA_IFCR_CGIF3_Msk (0x1U << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1073 #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 1074 #define DMA_IFCR_CTCIF3_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1075 #define DMA_IFCR_CTCIF3_Msk (0x1U << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1076 #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 1077 #define DMA_IFCR_CHTIF3_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1078 #define DMA_IFCR_CHTIF3_Msk (0x1U << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1079 #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 1080 #define DMA_IFCR_CTEIF3_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1081 #define DMA_IFCR_CTEIF3_Msk (0x1U << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1082 #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 1083 #define DMA_IFCR_CGIF4_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1084 #define DMA_IFCR_CGIF4_Msk (0x1U << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1085 #define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 1086 #define DMA_IFCR_CTCIF4_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1087 #define DMA_IFCR_CTCIF4_Msk (0x1U << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1088 #define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 1089 #define DMA_IFCR_CHTIF4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1090 #define DMA_IFCR_CHTIF4_Msk (0x1U << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1091 #define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 1092 #define DMA_IFCR_CTEIF4_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1093 #define DMA_IFCR_CTEIF4_Msk (0x1U << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1094 #define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 1095 #define DMA_IFCR_CGIF5_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1096 #define DMA_IFCR_CGIF5_Msk (0x1U << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1097 #define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
AnnaBridge 171:3a7713b1edbc 1098 #define DMA_IFCR_CTCIF5_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1099 #define DMA_IFCR_CTCIF5_Msk (0x1U << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1100 #define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
AnnaBridge 171:3a7713b1edbc 1101 #define DMA_IFCR_CHTIF5_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1102 #define DMA_IFCR_CHTIF5_Msk (0x1U << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1103 #define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
AnnaBridge 171:3a7713b1edbc 1104 #define DMA_IFCR_CTEIF5_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1105 #define DMA_IFCR_CTEIF5_Msk (0x1U << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1106 #define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108 /******************* Bit definition for DMA_CCR register ********************/
AnnaBridge 171:3a7713b1edbc 1109 #define DMA_CCR_EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1110 #define DMA_CCR_EN_Msk (0x1U << DMA_CCR_EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1111 #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */
AnnaBridge 171:3a7713b1edbc 1112 #define DMA_CCR_TCIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1113 #define DMA_CCR_TCIE_Msk (0x1U << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1114 #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 1115 #define DMA_CCR_HTIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1116 #define DMA_CCR_HTIE_Msk (0x1U << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1117 #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
AnnaBridge 171:3a7713b1edbc 1118 #define DMA_CCR_TEIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1119 #define DMA_CCR_TEIE_Msk (0x1U << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1120 #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
AnnaBridge 171:3a7713b1edbc 1121 #define DMA_CCR_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1122 #define DMA_CCR_DIR_Msk (0x1U << DMA_CCR_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1123 #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */
AnnaBridge 171:3a7713b1edbc 1124 #define DMA_CCR_CIRC_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1125 #define DMA_CCR_CIRC_Msk (0x1U << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1126 #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */
AnnaBridge 171:3a7713b1edbc 1127 #define DMA_CCR_PINC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1128 #define DMA_CCR_PINC_Msk (0x1U << DMA_CCR_PINC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1129 #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */
AnnaBridge 171:3a7713b1edbc 1130 #define DMA_CCR_MINC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1131 #define DMA_CCR_MINC_Msk (0x1U << DMA_CCR_MINC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1132 #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */
AnnaBridge 171:3a7713b1edbc 1133
AnnaBridge 171:3a7713b1edbc 1134 #define DMA_CCR_PSIZE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1135 #define DMA_CCR_PSIZE_Msk (0x3U << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 1136 #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
AnnaBridge 171:3a7713b1edbc 1137 #define DMA_CCR_PSIZE_0 (0x1U << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1138 #define DMA_CCR_PSIZE_1 (0x2U << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1139
AnnaBridge 171:3a7713b1edbc 1140 #define DMA_CCR_MSIZE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1141 #define DMA_CCR_MSIZE_Msk (0x3U << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 1142 #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
AnnaBridge 171:3a7713b1edbc 1143 #define DMA_CCR_MSIZE_0 (0x1U << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1144 #define DMA_CCR_MSIZE_1 (0x2U << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1145
AnnaBridge 171:3a7713b1edbc 1146 #define DMA_CCR_PL_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1147 #define DMA_CCR_PL_Msk (0x3U << DMA_CCR_PL_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 1148 #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
AnnaBridge 171:3a7713b1edbc 1149 #define DMA_CCR_PL_0 (0x1U << DMA_CCR_PL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1150 #define DMA_CCR_PL_1 (0x2U << DMA_CCR_PL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1151
AnnaBridge 171:3a7713b1edbc 1152 #define DMA_CCR_MEM2MEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1153 #define DMA_CCR_MEM2MEM_Msk (0x1U << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1154 #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
AnnaBridge 171:3a7713b1edbc 1155
AnnaBridge 171:3a7713b1edbc 1156 /****************** Bit definition for DMA_CNDTR register *******************/
AnnaBridge 171:3a7713b1edbc 1157 #define DMA_CNDTR_NDT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1158 #define DMA_CNDTR_NDT_Msk (0xFFFFU << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1159 #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
AnnaBridge 171:3a7713b1edbc 1160
AnnaBridge 171:3a7713b1edbc 1161 /****************** Bit definition for DMA_CPAR register ********************/
AnnaBridge 171:3a7713b1edbc 1162 #define DMA_CPAR_PA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1163 #define DMA_CPAR_PA_Msk (0xFFFFFFFFU << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1164 #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */
AnnaBridge 171:3a7713b1edbc 1165
AnnaBridge 171:3a7713b1edbc 1166 /****************** Bit definition for DMA_CMAR register ********************/
AnnaBridge 171:3a7713b1edbc 1167 #define DMA_CMAR_MA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1168 #define DMA_CMAR_MA_Msk (0xFFFFFFFFU << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1169 #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */
AnnaBridge 171:3a7713b1edbc 1170
AnnaBridge 171:3a7713b1edbc 1171 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1172 /* */
AnnaBridge 171:3a7713b1edbc 1173 /* External Interrupt/Event Controller (EXTI) */
AnnaBridge 171:3a7713b1edbc 1174 /* */
AnnaBridge 171:3a7713b1edbc 1175 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1176 /******************* Bit definition for EXTI_IMR register *******************/
AnnaBridge 171:3a7713b1edbc 1177 #define EXTI_IMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1178 #define EXTI_IMR_MR0_Msk (0x1U << EXTI_IMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1179 #define EXTI_IMR_MR0 EXTI_IMR_MR0_Msk /*!< Interrupt Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 1180 #define EXTI_IMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1181 #define EXTI_IMR_MR1_Msk (0x1U << EXTI_IMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1182 #define EXTI_IMR_MR1 EXTI_IMR_MR1_Msk /*!< Interrupt Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 1183 #define EXTI_IMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1184 #define EXTI_IMR_MR2_Msk (0x1U << EXTI_IMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1185 #define EXTI_IMR_MR2 EXTI_IMR_MR2_Msk /*!< Interrupt Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 1186 #define EXTI_IMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1187 #define EXTI_IMR_MR3_Msk (0x1U << EXTI_IMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1188 #define EXTI_IMR_MR3 EXTI_IMR_MR3_Msk /*!< Interrupt Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 1189 #define EXTI_IMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1190 #define EXTI_IMR_MR4_Msk (0x1U << EXTI_IMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1191 #define EXTI_IMR_MR4 EXTI_IMR_MR4_Msk /*!< Interrupt Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 1192 #define EXTI_IMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1193 #define EXTI_IMR_MR5_Msk (0x1U << EXTI_IMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1194 #define EXTI_IMR_MR5 EXTI_IMR_MR5_Msk /*!< Interrupt Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 1195 #define EXTI_IMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1196 #define EXTI_IMR_MR6_Msk (0x1U << EXTI_IMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1197 #define EXTI_IMR_MR6 EXTI_IMR_MR6_Msk /*!< Interrupt Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 1198 #define EXTI_IMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1199 #define EXTI_IMR_MR7_Msk (0x1U << EXTI_IMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1200 #define EXTI_IMR_MR7 EXTI_IMR_MR7_Msk /*!< Interrupt Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 1201 #define EXTI_IMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1202 #define EXTI_IMR_MR8_Msk (0x1U << EXTI_IMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1203 #define EXTI_IMR_MR8 EXTI_IMR_MR8_Msk /*!< Interrupt Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 1204 #define EXTI_IMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1205 #define EXTI_IMR_MR9_Msk (0x1U << EXTI_IMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1206 #define EXTI_IMR_MR9 EXTI_IMR_MR9_Msk /*!< Interrupt Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 1207 #define EXTI_IMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1208 #define EXTI_IMR_MR10_Msk (0x1U << EXTI_IMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1209 #define EXTI_IMR_MR10 EXTI_IMR_MR10_Msk /*!< Interrupt Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 1210 #define EXTI_IMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1211 #define EXTI_IMR_MR11_Msk (0x1U << EXTI_IMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1212 #define EXTI_IMR_MR11 EXTI_IMR_MR11_Msk /*!< Interrupt Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 1213 #define EXTI_IMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1214 #define EXTI_IMR_MR12_Msk (0x1U << EXTI_IMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1215 #define EXTI_IMR_MR12 EXTI_IMR_MR12_Msk /*!< Interrupt Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 1216 #define EXTI_IMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1217 #define EXTI_IMR_MR13_Msk (0x1U << EXTI_IMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1218 #define EXTI_IMR_MR13 EXTI_IMR_MR13_Msk /*!< Interrupt Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 1219 #define EXTI_IMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1220 #define EXTI_IMR_MR14_Msk (0x1U << EXTI_IMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1221 #define EXTI_IMR_MR14 EXTI_IMR_MR14_Msk /*!< Interrupt Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 1222 #define EXTI_IMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1223 #define EXTI_IMR_MR15_Msk (0x1U << EXTI_IMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1224 #define EXTI_IMR_MR15 EXTI_IMR_MR15_Msk /*!< Interrupt Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 1225 #define EXTI_IMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1226 #define EXTI_IMR_MR16_Msk (0x1U << EXTI_IMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1227 #define EXTI_IMR_MR16 EXTI_IMR_MR16_Msk /*!< Interrupt Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 1228 #define EXTI_IMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1229 #define EXTI_IMR_MR17_Msk (0x1U << EXTI_IMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1230 #define EXTI_IMR_MR17 EXTI_IMR_MR17_Msk /*!< Interrupt Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 1231 #define EXTI_IMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1232 #define EXTI_IMR_MR18_Msk (0x1U << EXTI_IMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1233 #define EXTI_IMR_MR18 EXTI_IMR_MR18_Msk /*!< Interrupt Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 1234 #define EXTI_IMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1235 #define EXTI_IMR_MR19_Msk (0x1U << EXTI_IMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1236 #define EXTI_IMR_MR19 EXTI_IMR_MR19_Msk /*!< Interrupt Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 1237 #define EXTI_IMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1238 #define EXTI_IMR_MR21_Msk (0x1U << EXTI_IMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1239 #define EXTI_IMR_MR21 EXTI_IMR_MR21_Msk /*!< Interrupt Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 1240 #define EXTI_IMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1241 #define EXTI_IMR_MR22_Msk (0x1U << EXTI_IMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1242 #define EXTI_IMR_MR22 EXTI_IMR_MR22_Msk /*!< Interrupt Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 1243 #define EXTI_IMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1244 #define EXTI_IMR_MR23_Msk (0x1U << EXTI_IMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1245 #define EXTI_IMR_MR23 EXTI_IMR_MR23_Msk /*!< Interrupt Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 1246 #define EXTI_IMR_MR25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1247 #define EXTI_IMR_MR25_Msk (0x1U << EXTI_IMR_MR25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1248 #define EXTI_IMR_MR25 EXTI_IMR_MR25_Msk /*!< Interrupt Mask on line 25 */
AnnaBridge 171:3a7713b1edbc 1249 #define EXTI_IMR_MR27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1250 #define EXTI_IMR_MR27_Msk (0x1U << EXTI_IMR_MR27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1251 #define EXTI_IMR_MR27 EXTI_IMR_MR27_Msk /*!< Interrupt Mask on line 27 */
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /* References Defines */
AnnaBridge 171:3a7713b1edbc 1254 #define EXTI_IMR_IM0 EXTI_IMR_MR0
AnnaBridge 171:3a7713b1edbc 1255 #define EXTI_IMR_IM1 EXTI_IMR_MR1
AnnaBridge 171:3a7713b1edbc 1256 #define EXTI_IMR_IM2 EXTI_IMR_MR2
AnnaBridge 171:3a7713b1edbc 1257 #define EXTI_IMR_IM3 EXTI_IMR_MR3
AnnaBridge 171:3a7713b1edbc 1258 #define EXTI_IMR_IM4 EXTI_IMR_MR4
AnnaBridge 171:3a7713b1edbc 1259 #define EXTI_IMR_IM5 EXTI_IMR_MR5
AnnaBridge 171:3a7713b1edbc 1260 #define EXTI_IMR_IM6 EXTI_IMR_MR6
AnnaBridge 171:3a7713b1edbc 1261 #define EXTI_IMR_IM7 EXTI_IMR_MR7
AnnaBridge 171:3a7713b1edbc 1262 #define EXTI_IMR_IM8 EXTI_IMR_MR8
AnnaBridge 171:3a7713b1edbc 1263 #define EXTI_IMR_IM9 EXTI_IMR_MR9
AnnaBridge 171:3a7713b1edbc 1264 #define EXTI_IMR_IM10 EXTI_IMR_MR10
AnnaBridge 171:3a7713b1edbc 1265 #define EXTI_IMR_IM11 EXTI_IMR_MR11
AnnaBridge 171:3a7713b1edbc 1266 #define EXTI_IMR_IM12 EXTI_IMR_MR12
AnnaBridge 171:3a7713b1edbc 1267 #define EXTI_IMR_IM13 EXTI_IMR_MR13
AnnaBridge 171:3a7713b1edbc 1268 #define EXTI_IMR_IM14 EXTI_IMR_MR14
AnnaBridge 171:3a7713b1edbc 1269 #define EXTI_IMR_IM15 EXTI_IMR_MR15
AnnaBridge 171:3a7713b1edbc 1270 #define EXTI_IMR_IM16 EXTI_IMR_MR16
AnnaBridge 171:3a7713b1edbc 1271 #define EXTI_IMR_IM17 EXTI_IMR_MR17
AnnaBridge 171:3a7713b1edbc 1272 #define EXTI_IMR_IM18 EXTI_IMR_MR18
AnnaBridge 171:3a7713b1edbc 1273 #define EXTI_IMR_IM19 EXTI_IMR_MR19
AnnaBridge 171:3a7713b1edbc 1274 #define EXTI_IMR_IM21 EXTI_IMR_MR21
AnnaBridge 171:3a7713b1edbc 1275 #define EXTI_IMR_IM22 EXTI_IMR_MR22
AnnaBridge 171:3a7713b1edbc 1276 #define EXTI_IMR_IM23 EXTI_IMR_MR23
AnnaBridge 171:3a7713b1edbc 1277 #define EXTI_IMR_IM25 EXTI_IMR_MR25
AnnaBridge 171:3a7713b1edbc 1278 #define EXTI_IMR_IM27 EXTI_IMR_MR27
AnnaBridge 171:3a7713b1edbc 1279
AnnaBridge 171:3a7713b1edbc 1280 #define EXTI_IMR_IM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1281 #define EXTI_IMR_IM_Msk (0xAEFFFFFU << EXTI_IMR_IM_Pos) /*!< 0x0AEFFFFF */
AnnaBridge 171:3a7713b1edbc 1282 #define EXTI_IMR_IM EXTI_IMR_IM_Msk /*!< Interrupt Mask All */
AnnaBridge 171:3a7713b1edbc 1283
AnnaBridge 171:3a7713b1edbc 1284
AnnaBridge 171:3a7713b1edbc 1285 /****************** Bit definition for EXTI_EMR register ********************/
AnnaBridge 171:3a7713b1edbc 1286 #define EXTI_EMR_MR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1287 #define EXTI_EMR_MR0_Msk (0x1U << EXTI_EMR_MR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1288 #define EXTI_EMR_MR0 EXTI_EMR_MR0_Msk /*!< Event Mask on line 0 */
AnnaBridge 171:3a7713b1edbc 1289 #define EXTI_EMR_MR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1290 #define EXTI_EMR_MR1_Msk (0x1U << EXTI_EMR_MR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1291 #define EXTI_EMR_MR1 EXTI_EMR_MR1_Msk /*!< Event Mask on line 1 */
AnnaBridge 171:3a7713b1edbc 1292 #define EXTI_EMR_MR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1293 #define EXTI_EMR_MR2_Msk (0x1U << EXTI_EMR_MR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1294 #define EXTI_EMR_MR2 EXTI_EMR_MR2_Msk /*!< Event Mask on line 2 */
AnnaBridge 171:3a7713b1edbc 1295 #define EXTI_EMR_MR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1296 #define EXTI_EMR_MR3_Msk (0x1U << EXTI_EMR_MR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1297 #define EXTI_EMR_MR3 EXTI_EMR_MR3_Msk /*!< Event Mask on line 3 */
AnnaBridge 171:3a7713b1edbc 1298 #define EXTI_EMR_MR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1299 #define EXTI_EMR_MR4_Msk (0x1U << EXTI_EMR_MR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1300 #define EXTI_EMR_MR4 EXTI_EMR_MR4_Msk /*!< Event Mask on line 4 */
AnnaBridge 171:3a7713b1edbc 1301 #define EXTI_EMR_MR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1302 #define EXTI_EMR_MR5_Msk (0x1U << EXTI_EMR_MR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1303 #define EXTI_EMR_MR5 EXTI_EMR_MR5_Msk /*!< Event Mask on line 5 */
AnnaBridge 171:3a7713b1edbc 1304 #define EXTI_EMR_MR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1305 #define EXTI_EMR_MR6_Msk (0x1U << EXTI_EMR_MR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1306 #define EXTI_EMR_MR6 EXTI_EMR_MR6_Msk /*!< Event Mask on line 6 */
AnnaBridge 171:3a7713b1edbc 1307 #define EXTI_EMR_MR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1308 #define EXTI_EMR_MR7_Msk (0x1U << EXTI_EMR_MR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1309 #define EXTI_EMR_MR7 EXTI_EMR_MR7_Msk /*!< Event Mask on line 7 */
AnnaBridge 171:3a7713b1edbc 1310 #define EXTI_EMR_MR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1311 #define EXTI_EMR_MR8_Msk (0x1U << EXTI_EMR_MR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1312 #define EXTI_EMR_MR8 EXTI_EMR_MR8_Msk /*!< Event Mask on line 8 */
AnnaBridge 171:3a7713b1edbc 1313 #define EXTI_EMR_MR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1314 #define EXTI_EMR_MR9_Msk (0x1U << EXTI_EMR_MR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1315 #define EXTI_EMR_MR9 EXTI_EMR_MR9_Msk /*!< Event Mask on line 9 */
AnnaBridge 171:3a7713b1edbc 1316 #define EXTI_EMR_MR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1317 #define EXTI_EMR_MR10_Msk (0x1U << EXTI_EMR_MR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1318 #define EXTI_EMR_MR10 EXTI_EMR_MR10_Msk /*!< Event Mask on line 10 */
AnnaBridge 171:3a7713b1edbc 1319 #define EXTI_EMR_MR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1320 #define EXTI_EMR_MR11_Msk (0x1U << EXTI_EMR_MR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1321 #define EXTI_EMR_MR11 EXTI_EMR_MR11_Msk /*!< Event Mask on line 11 */
AnnaBridge 171:3a7713b1edbc 1322 #define EXTI_EMR_MR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1323 #define EXTI_EMR_MR12_Msk (0x1U << EXTI_EMR_MR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1324 #define EXTI_EMR_MR12 EXTI_EMR_MR12_Msk /*!< Event Mask on line 12 */
AnnaBridge 171:3a7713b1edbc 1325 #define EXTI_EMR_MR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1326 #define EXTI_EMR_MR13_Msk (0x1U << EXTI_EMR_MR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1327 #define EXTI_EMR_MR13 EXTI_EMR_MR13_Msk /*!< Event Mask on line 13 */
AnnaBridge 171:3a7713b1edbc 1328 #define EXTI_EMR_MR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1329 #define EXTI_EMR_MR14_Msk (0x1U << EXTI_EMR_MR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1330 #define EXTI_EMR_MR14 EXTI_EMR_MR14_Msk /*!< Event Mask on line 14 */
AnnaBridge 171:3a7713b1edbc 1331 #define EXTI_EMR_MR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1332 #define EXTI_EMR_MR15_Msk (0x1U << EXTI_EMR_MR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1333 #define EXTI_EMR_MR15 EXTI_EMR_MR15_Msk /*!< Event Mask on line 15 */
AnnaBridge 171:3a7713b1edbc 1334 #define EXTI_EMR_MR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1335 #define EXTI_EMR_MR16_Msk (0x1U << EXTI_EMR_MR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1336 #define EXTI_EMR_MR16 EXTI_EMR_MR16_Msk /*!< Event Mask on line 16 */
AnnaBridge 171:3a7713b1edbc 1337 #define EXTI_EMR_MR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1338 #define EXTI_EMR_MR17_Msk (0x1U << EXTI_EMR_MR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1339 #define EXTI_EMR_MR17 EXTI_EMR_MR17_Msk /*!< Event Mask on line 17 */
AnnaBridge 171:3a7713b1edbc 1340 #define EXTI_EMR_MR18_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1341 #define EXTI_EMR_MR18_Msk (0x1U << EXTI_EMR_MR18_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1342 #define EXTI_EMR_MR18 EXTI_EMR_MR18_Msk /*!< Event Mask on line 18 */
AnnaBridge 171:3a7713b1edbc 1343 #define EXTI_EMR_MR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1344 #define EXTI_EMR_MR19_Msk (0x1U << EXTI_EMR_MR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1345 #define EXTI_EMR_MR19 EXTI_EMR_MR19_Msk /*!< Event Mask on line 19 */
AnnaBridge 171:3a7713b1edbc 1346 #define EXTI_EMR_MR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1347 #define EXTI_EMR_MR21_Msk (0x1U << EXTI_EMR_MR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1348 #define EXTI_EMR_MR21 EXTI_EMR_MR21_Msk /*!< Event Mask on line 21 */
AnnaBridge 171:3a7713b1edbc 1349 #define EXTI_EMR_MR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1350 #define EXTI_EMR_MR22_Msk (0x1U << EXTI_EMR_MR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1351 #define EXTI_EMR_MR22 EXTI_EMR_MR22_Msk /*!< Event Mask on line 22 */
AnnaBridge 171:3a7713b1edbc 1352 #define EXTI_EMR_MR23_Pos (23U)
AnnaBridge 171:3a7713b1edbc 1353 #define EXTI_EMR_MR23_Msk (0x1U << EXTI_EMR_MR23_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1354 #define EXTI_EMR_MR23 EXTI_EMR_MR23_Msk /*!< Event Mask on line 23 */
AnnaBridge 171:3a7713b1edbc 1355 #define EXTI_EMR_MR25_Pos (25U)
AnnaBridge 171:3a7713b1edbc 1356 #define EXTI_EMR_MR25_Msk (0x1U << EXTI_EMR_MR25_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1357 #define EXTI_EMR_MR25 EXTI_EMR_MR25_Msk /*!< Event Mask on line 25 */
AnnaBridge 171:3a7713b1edbc 1358 #define EXTI_EMR_MR27_Pos (27U)
AnnaBridge 171:3a7713b1edbc 1359 #define EXTI_EMR_MR27_Msk (0x1U << EXTI_EMR_MR27_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1360 #define EXTI_EMR_MR27 EXTI_EMR_MR27_Msk /*!< Event Mask on line 27 */
AnnaBridge 171:3a7713b1edbc 1361
AnnaBridge 171:3a7713b1edbc 1362 /* References Defines */
AnnaBridge 171:3a7713b1edbc 1363 #define EXTI_EMR_EM0 EXTI_EMR_MR0
AnnaBridge 171:3a7713b1edbc 1364 #define EXTI_EMR_EM1 EXTI_EMR_MR1
AnnaBridge 171:3a7713b1edbc 1365 #define EXTI_EMR_EM2 EXTI_EMR_MR2
AnnaBridge 171:3a7713b1edbc 1366 #define EXTI_EMR_EM3 EXTI_EMR_MR3
AnnaBridge 171:3a7713b1edbc 1367 #define EXTI_EMR_EM4 EXTI_EMR_MR4
AnnaBridge 171:3a7713b1edbc 1368 #define EXTI_EMR_EM5 EXTI_EMR_MR5
AnnaBridge 171:3a7713b1edbc 1369 #define EXTI_EMR_EM6 EXTI_EMR_MR6
AnnaBridge 171:3a7713b1edbc 1370 #define EXTI_EMR_EM7 EXTI_EMR_MR7
AnnaBridge 171:3a7713b1edbc 1371 #define EXTI_EMR_EM8 EXTI_EMR_MR8
AnnaBridge 171:3a7713b1edbc 1372 #define EXTI_EMR_EM9 EXTI_EMR_MR9
AnnaBridge 171:3a7713b1edbc 1373 #define EXTI_EMR_EM10 EXTI_EMR_MR10
AnnaBridge 171:3a7713b1edbc 1374 #define EXTI_EMR_EM11 EXTI_EMR_MR11
AnnaBridge 171:3a7713b1edbc 1375 #define EXTI_EMR_EM12 EXTI_EMR_MR12
AnnaBridge 171:3a7713b1edbc 1376 #define EXTI_EMR_EM13 EXTI_EMR_MR13
AnnaBridge 171:3a7713b1edbc 1377 #define EXTI_EMR_EM14 EXTI_EMR_MR14
AnnaBridge 171:3a7713b1edbc 1378 #define EXTI_EMR_EM15 EXTI_EMR_MR15
AnnaBridge 171:3a7713b1edbc 1379 #define EXTI_EMR_EM16 EXTI_EMR_MR16
AnnaBridge 171:3a7713b1edbc 1380 #define EXTI_EMR_EM17 EXTI_EMR_MR17
AnnaBridge 171:3a7713b1edbc 1381 #define EXTI_EMR_EM18 EXTI_EMR_MR18
AnnaBridge 171:3a7713b1edbc 1382 #define EXTI_EMR_EM19 EXTI_EMR_MR19
AnnaBridge 171:3a7713b1edbc 1383 #define EXTI_EMR_EM21 EXTI_EMR_MR21
AnnaBridge 171:3a7713b1edbc 1384 #define EXTI_EMR_EM22 EXTI_EMR_MR22
AnnaBridge 171:3a7713b1edbc 1385 #define EXTI_EMR_EM23 EXTI_EMR_MR23
AnnaBridge 171:3a7713b1edbc 1386 #define EXTI_EMR_EM25 EXTI_EMR_MR25
AnnaBridge 171:3a7713b1edbc 1387 #define EXTI_EMR_EM27 EXTI_EMR_MR27
AnnaBridge 171:3a7713b1edbc 1388
AnnaBridge 171:3a7713b1edbc 1389 /******************* Bit definition for EXTI_RTSR register ******************/
AnnaBridge 171:3a7713b1edbc 1390 #define EXTI_RTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1391 #define EXTI_RTSR_TR0_Msk (0x1U << EXTI_RTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1392 #define EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 1393 #define EXTI_RTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1394 #define EXTI_RTSR_TR1_Msk (0x1U << EXTI_RTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1395 #define EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 1396 #define EXTI_RTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1397 #define EXTI_RTSR_TR2_Msk (0x1U << EXTI_RTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1398 #define EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 1399 #define EXTI_RTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1400 #define EXTI_RTSR_TR3_Msk (0x1U << EXTI_RTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1401 #define EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 1402 #define EXTI_RTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1403 #define EXTI_RTSR_TR4_Msk (0x1U << EXTI_RTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1404 #define EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 1405 #define EXTI_RTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1406 #define EXTI_RTSR_TR5_Msk (0x1U << EXTI_RTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1407 #define EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 1408 #define EXTI_RTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1409 #define EXTI_RTSR_TR6_Msk (0x1U << EXTI_RTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1410 #define EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 1411 #define EXTI_RTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1412 #define EXTI_RTSR_TR7_Msk (0x1U << EXTI_RTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1413 #define EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 1414 #define EXTI_RTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1415 #define EXTI_RTSR_TR8_Msk (0x1U << EXTI_RTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1416 #define EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 1417 #define EXTI_RTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1418 #define EXTI_RTSR_TR9_Msk (0x1U << EXTI_RTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1419 #define EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 1420 #define EXTI_RTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1421 #define EXTI_RTSR_TR10_Msk (0x1U << EXTI_RTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1422 #define EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 1423 #define EXTI_RTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1424 #define EXTI_RTSR_TR11_Msk (0x1U << EXTI_RTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1425 #define EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 1426 #define EXTI_RTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1427 #define EXTI_RTSR_TR12_Msk (0x1U << EXTI_RTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1428 #define EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 1429 #define EXTI_RTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1430 #define EXTI_RTSR_TR13_Msk (0x1U << EXTI_RTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1431 #define EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 1432 #define EXTI_RTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1433 #define EXTI_RTSR_TR14_Msk (0x1U << EXTI_RTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1434 #define EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 1435 #define EXTI_RTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1436 #define EXTI_RTSR_TR15_Msk (0x1U << EXTI_RTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1437 #define EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 1438 #define EXTI_RTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1439 #define EXTI_RTSR_TR16_Msk (0x1U << EXTI_RTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1440 #define EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 1441 #define EXTI_RTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1442 #define EXTI_RTSR_TR17_Msk (0x1U << EXTI_RTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1443 #define EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 1444 #define EXTI_RTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1445 #define EXTI_RTSR_TR19_Msk (0x1U << EXTI_RTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1446 #define EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 1447 #define EXTI_RTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1448 #define EXTI_RTSR_TR21_Msk (0x1U << EXTI_RTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1449 #define EXTI_RTSR_TR21 EXTI_RTSR_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 1450 #define EXTI_RTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1451 #define EXTI_RTSR_TR22_Msk (0x1U << EXTI_RTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1452 #define EXTI_RTSR_TR22 EXTI_RTSR_TR22_Msk /*!< Rising trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 1453
AnnaBridge 171:3a7713b1edbc 1454 /* References Defines */
AnnaBridge 171:3a7713b1edbc 1455 #define EXTI_RTSR_RT0 EXTI_RTSR_TR0
AnnaBridge 171:3a7713b1edbc 1456 #define EXTI_RTSR_RT1 EXTI_RTSR_TR1
AnnaBridge 171:3a7713b1edbc 1457 #define EXTI_RTSR_RT2 EXTI_RTSR_TR2
AnnaBridge 171:3a7713b1edbc 1458 #define EXTI_RTSR_RT3 EXTI_RTSR_TR3
AnnaBridge 171:3a7713b1edbc 1459 #define EXTI_RTSR_RT4 EXTI_RTSR_TR4
AnnaBridge 171:3a7713b1edbc 1460 #define EXTI_RTSR_RT5 EXTI_RTSR_TR5
AnnaBridge 171:3a7713b1edbc 1461 #define EXTI_RTSR_RT6 EXTI_RTSR_TR6
AnnaBridge 171:3a7713b1edbc 1462 #define EXTI_RTSR_RT7 EXTI_RTSR_TR7
AnnaBridge 171:3a7713b1edbc 1463 #define EXTI_RTSR_RT8 EXTI_RTSR_TR8
AnnaBridge 171:3a7713b1edbc 1464 #define EXTI_RTSR_RT9 EXTI_RTSR_TR9
AnnaBridge 171:3a7713b1edbc 1465 #define EXTI_RTSR_RT10 EXTI_RTSR_TR10
AnnaBridge 171:3a7713b1edbc 1466 #define EXTI_RTSR_RT11 EXTI_RTSR_TR11
AnnaBridge 171:3a7713b1edbc 1467 #define EXTI_RTSR_RT12 EXTI_RTSR_TR12
AnnaBridge 171:3a7713b1edbc 1468 #define EXTI_RTSR_RT13 EXTI_RTSR_TR13
AnnaBridge 171:3a7713b1edbc 1469 #define EXTI_RTSR_RT14 EXTI_RTSR_TR14
AnnaBridge 171:3a7713b1edbc 1470 #define EXTI_RTSR_RT15 EXTI_RTSR_TR15
AnnaBridge 171:3a7713b1edbc 1471 #define EXTI_RTSR_RT16 EXTI_RTSR_TR16
AnnaBridge 171:3a7713b1edbc 1472 #define EXTI_RTSR_RT17 EXTI_RTSR_TR17
AnnaBridge 171:3a7713b1edbc 1473 #define EXTI_RTSR_RT19 EXTI_RTSR_TR19
AnnaBridge 171:3a7713b1edbc 1474 #define EXTI_RTSR_RT21 EXTI_RTSR_TR21
AnnaBridge 171:3a7713b1edbc 1475 #define EXTI_RTSR_RT22 EXTI_RTSR_TR22
AnnaBridge 171:3a7713b1edbc 1476
AnnaBridge 171:3a7713b1edbc 1477 /******************* Bit definition for EXTI_FTSR register *******************/
AnnaBridge 171:3a7713b1edbc 1478 #define EXTI_FTSR_TR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1479 #define EXTI_FTSR_TR0_Msk (0x1U << EXTI_FTSR_TR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1480 #define EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
AnnaBridge 171:3a7713b1edbc 1481 #define EXTI_FTSR_TR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1482 #define EXTI_FTSR_TR1_Msk (0x1U << EXTI_FTSR_TR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1483 #define EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
AnnaBridge 171:3a7713b1edbc 1484 #define EXTI_FTSR_TR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1485 #define EXTI_FTSR_TR2_Msk (0x1U << EXTI_FTSR_TR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1486 #define EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
AnnaBridge 171:3a7713b1edbc 1487 #define EXTI_FTSR_TR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1488 #define EXTI_FTSR_TR3_Msk (0x1U << EXTI_FTSR_TR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1489 #define EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
AnnaBridge 171:3a7713b1edbc 1490 #define EXTI_FTSR_TR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1491 #define EXTI_FTSR_TR4_Msk (0x1U << EXTI_FTSR_TR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1492 #define EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
AnnaBridge 171:3a7713b1edbc 1493 #define EXTI_FTSR_TR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1494 #define EXTI_FTSR_TR5_Msk (0x1U << EXTI_FTSR_TR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1495 #define EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
AnnaBridge 171:3a7713b1edbc 1496 #define EXTI_FTSR_TR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1497 #define EXTI_FTSR_TR6_Msk (0x1U << EXTI_FTSR_TR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1498 #define EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
AnnaBridge 171:3a7713b1edbc 1499 #define EXTI_FTSR_TR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1500 #define EXTI_FTSR_TR7_Msk (0x1U << EXTI_FTSR_TR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1501 #define EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
AnnaBridge 171:3a7713b1edbc 1502 #define EXTI_FTSR_TR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1503 #define EXTI_FTSR_TR8_Msk (0x1U << EXTI_FTSR_TR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1504 #define EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
AnnaBridge 171:3a7713b1edbc 1505 #define EXTI_FTSR_TR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1506 #define EXTI_FTSR_TR9_Msk (0x1U << EXTI_FTSR_TR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1507 #define EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
AnnaBridge 171:3a7713b1edbc 1508 #define EXTI_FTSR_TR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1509 #define EXTI_FTSR_TR10_Msk (0x1U << EXTI_FTSR_TR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1510 #define EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
AnnaBridge 171:3a7713b1edbc 1511 #define EXTI_FTSR_TR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1512 #define EXTI_FTSR_TR11_Msk (0x1U << EXTI_FTSR_TR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1513 #define EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
AnnaBridge 171:3a7713b1edbc 1514 #define EXTI_FTSR_TR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1515 #define EXTI_FTSR_TR12_Msk (0x1U << EXTI_FTSR_TR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1516 #define EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
AnnaBridge 171:3a7713b1edbc 1517 #define EXTI_FTSR_TR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1518 #define EXTI_FTSR_TR13_Msk (0x1U << EXTI_FTSR_TR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1519 #define EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
AnnaBridge 171:3a7713b1edbc 1520 #define EXTI_FTSR_TR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1521 #define EXTI_FTSR_TR14_Msk (0x1U << EXTI_FTSR_TR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1522 #define EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
AnnaBridge 171:3a7713b1edbc 1523 #define EXTI_FTSR_TR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1524 #define EXTI_FTSR_TR15_Msk (0x1U << EXTI_FTSR_TR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1525 #define EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
AnnaBridge 171:3a7713b1edbc 1526 #define EXTI_FTSR_TR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1527 #define EXTI_FTSR_TR16_Msk (0x1U << EXTI_FTSR_TR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1528 #define EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
AnnaBridge 171:3a7713b1edbc 1529 #define EXTI_FTSR_TR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1530 #define EXTI_FTSR_TR17_Msk (0x1U << EXTI_FTSR_TR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1531 #define EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
AnnaBridge 171:3a7713b1edbc 1532 #define EXTI_FTSR_TR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1533 #define EXTI_FTSR_TR19_Msk (0x1U << EXTI_FTSR_TR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1534 #define EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
AnnaBridge 171:3a7713b1edbc 1535 #define EXTI_FTSR_TR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1536 #define EXTI_FTSR_TR21_Msk (0x1U << EXTI_FTSR_TR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1537 #define EXTI_FTSR_TR21 EXTI_FTSR_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
AnnaBridge 171:3a7713b1edbc 1538 #define EXTI_FTSR_TR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1539 #define EXTI_FTSR_TR22_Msk (0x1U << EXTI_FTSR_TR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1540 #define EXTI_FTSR_TR22 EXTI_FTSR_TR22_Msk /*!< Falling trigger event configuration bit of line 22 */
AnnaBridge 171:3a7713b1edbc 1541
AnnaBridge 171:3a7713b1edbc 1542 /* References Defines */
AnnaBridge 171:3a7713b1edbc 1543 #define EXTI_FTSR_FT0 EXTI_FTSR_TR0
AnnaBridge 171:3a7713b1edbc 1544 #define EXTI_FTSR_FT1 EXTI_FTSR_TR1
AnnaBridge 171:3a7713b1edbc 1545 #define EXTI_FTSR_FT2 EXTI_FTSR_TR2
AnnaBridge 171:3a7713b1edbc 1546 #define EXTI_FTSR_FT3 EXTI_FTSR_TR3
AnnaBridge 171:3a7713b1edbc 1547 #define EXTI_FTSR_FT4 EXTI_FTSR_TR4
AnnaBridge 171:3a7713b1edbc 1548 #define EXTI_FTSR_FT5 EXTI_FTSR_TR5
AnnaBridge 171:3a7713b1edbc 1549 #define EXTI_FTSR_FT6 EXTI_FTSR_TR6
AnnaBridge 171:3a7713b1edbc 1550 #define EXTI_FTSR_FT7 EXTI_FTSR_TR7
AnnaBridge 171:3a7713b1edbc 1551 #define EXTI_FTSR_FT8 EXTI_FTSR_TR8
AnnaBridge 171:3a7713b1edbc 1552 #define EXTI_FTSR_FT9 EXTI_FTSR_TR9
AnnaBridge 171:3a7713b1edbc 1553 #define EXTI_FTSR_FT10 EXTI_FTSR_TR10
AnnaBridge 171:3a7713b1edbc 1554 #define EXTI_FTSR_FT11 EXTI_FTSR_TR11
AnnaBridge 171:3a7713b1edbc 1555 #define EXTI_FTSR_FT12 EXTI_FTSR_TR12
AnnaBridge 171:3a7713b1edbc 1556 #define EXTI_FTSR_FT13 EXTI_FTSR_TR13
AnnaBridge 171:3a7713b1edbc 1557 #define EXTI_FTSR_FT14 EXTI_FTSR_TR14
AnnaBridge 171:3a7713b1edbc 1558 #define EXTI_FTSR_FT15 EXTI_FTSR_TR15
AnnaBridge 171:3a7713b1edbc 1559 #define EXTI_FTSR_FT16 EXTI_FTSR_TR16
AnnaBridge 171:3a7713b1edbc 1560 #define EXTI_FTSR_FT17 EXTI_FTSR_TR17
AnnaBridge 171:3a7713b1edbc 1561 #define EXTI_FTSR_FT19 EXTI_FTSR_TR19
AnnaBridge 171:3a7713b1edbc 1562 #define EXTI_FTSR_FT21 EXTI_FTSR_TR21
AnnaBridge 171:3a7713b1edbc 1563 #define EXTI_FTSR_FT22 EXTI_FTSR_TR22
AnnaBridge 171:3a7713b1edbc 1564
AnnaBridge 171:3a7713b1edbc 1565 /******************* Bit definition for EXTI_SWIER register *******************/
AnnaBridge 171:3a7713b1edbc 1566 #define EXTI_SWIER_SWIER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1567 #define EXTI_SWIER_SWIER0_Msk (0x1U << EXTI_SWIER_SWIER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1568 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk /*!< Software Interrupt on line 0 */
AnnaBridge 171:3a7713b1edbc 1569 #define EXTI_SWIER_SWIER1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1570 #define EXTI_SWIER_SWIER1_Msk (0x1U << EXTI_SWIER_SWIER1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1571 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk /*!< Software Interrupt on line 1 */
AnnaBridge 171:3a7713b1edbc 1572 #define EXTI_SWIER_SWIER2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1573 #define EXTI_SWIER_SWIER2_Msk (0x1U << EXTI_SWIER_SWIER2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1574 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk /*!< Software Interrupt on line 2 */
AnnaBridge 171:3a7713b1edbc 1575 #define EXTI_SWIER_SWIER3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1576 #define EXTI_SWIER_SWIER3_Msk (0x1U << EXTI_SWIER_SWIER3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1577 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk /*!< Software Interrupt on line 3 */
AnnaBridge 171:3a7713b1edbc 1578 #define EXTI_SWIER_SWIER4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1579 #define EXTI_SWIER_SWIER4_Msk (0x1U << EXTI_SWIER_SWIER4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1580 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk /*!< Software Interrupt on line 4 */
AnnaBridge 171:3a7713b1edbc 1581 #define EXTI_SWIER_SWIER5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1582 #define EXTI_SWIER_SWIER5_Msk (0x1U << EXTI_SWIER_SWIER5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1583 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk /*!< Software Interrupt on line 5 */
AnnaBridge 171:3a7713b1edbc 1584 #define EXTI_SWIER_SWIER6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1585 #define EXTI_SWIER_SWIER6_Msk (0x1U << EXTI_SWIER_SWIER6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1586 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk /*!< Software Interrupt on line 6 */
AnnaBridge 171:3a7713b1edbc 1587 #define EXTI_SWIER_SWIER7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1588 #define EXTI_SWIER_SWIER7_Msk (0x1U << EXTI_SWIER_SWIER7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1589 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk /*!< Software Interrupt on line 7 */
AnnaBridge 171:3a7713b1edbc 1590 #define EXTI_SWIER_SWIER8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1591 #define EXTI_SWIER_SWIER8_Msk (0x1U << EXTI_SWIER_SWIER8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1592 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk /*!< Software Interrupt on line 8 */
AnnaBridge 171:3a7713b1edbc 1593 #define EXTI_SWIER_SWIER9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1594 #define EXTI_SWIER_SWIER9_Msk (0x1U << EXTI_SWIER_SWIER9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1595 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk /*!< Software Interrupt on line 9 */
AnnaBridge 171:3a7713b1edbc 1596 #define EXTI_SWIER_SWIER10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1597 #define EXTI_SWIER_SWIER10_Msk (0x1U << EXTI_SWIER_SWIER10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1598 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk /*!< Software Interrupt on line 10 */
AnnaBridge 171:3a7713b1edbc 1599 #define EXTI_SWIER_SWIER11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1600 #define EXTI_SWIER_SWIER11_Msk (0x1U << EXTI_SWIER_SWIER11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1601 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk /*!< Software Interrupt on line 11 */
AnnaBridge 171:3a7713b1edbc 1602 #define EXTI_SWIER_SWIER12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1603 #define EXTI_SWIER_SWIER12_Msk (0x1U << EXTI_SWIER_SWIER12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1604 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk /*!< Software Interrupt on line 12 */
AnnaBridge 171:3a7713b1edbc 1605 #define EXTI_SWIER_SWIER13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1606 #define EXTI_SWIER_SWIER13_Msk (0x1U << EXTI_SWIER_SWIER13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1607 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk /*!< Software Interrupt on line 13 */
AnnaBridge 171:3a7713b1edbc 1608 #define EXTI_SWIER_SWIER14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1609 #define EXTI_SWIER_SWIER14_Msk (0x1U << EXTI_SWIER_SWIER14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1610 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk /*!< Software Interrupt on line 14 */
AnnaBridge 171:3a7713b1edbc 1611 #define EXTI_SWIER_SWIER15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1612 #define EXTI_SWIER_SWIER15_Msk (0x1U << EXTI_SWIER_SWIER15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1613 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk /*!< Software Interrupt on line 15 */
AnnaBridge 171:3a7713b1edbc 1614 #define EXTI_SWIER_SWIER16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1615 #define EXTI_SWIER_SWIER16_Msk (0x1U << EXTI_SWIER_SWIER16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1616 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk /*!< Software Interrupt on line 16 */
AnnaBridge 171:3a7713b1edbc 1617 #define EXTI_SWIER_SWIER17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1618 #define EXTI_SWIER_SWIER17_Msk (0x1U << EXTI_SWIER_SWIER17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1619 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk /*!< Software Interrupt on line 17 */
AnnaBridge 171:3a7713b1edbc 1620 #define EXTI_SWIER_SWIER19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1621 #define EXTI_SWIER_SWIER19_Msk (0x1U << EXTI_SWIER_SWIER19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1622 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk /*!< Software Interrupt on line 19 */
AnnaBridge 171:3a7713b1edbc 1623 #define EXTI_SWIER_SWIER21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1624 #define EXTI_SWIER_SWIER21_Msk (0x1U << EXTI_SWIER_SWIER21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1625 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWIER21_Msk /*!< Software Interrupt on line 21 */
AnnaBridge 171:3a7713b1edbc 1626 #define EXTI_SWIER_SWIER22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1627 #define EXTI_SWIER_SWIER22_Msk (0x1U << EXTI_SWIER_SWIER22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1628 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWIER22_Msk /*!< Software Interrupt on line 22 */
AnnaBridge 171:3a7713b1edbc 1629
AnnaBridge 171:3a7713b1edbc 1630 /* References Defines */
AnnaBridge 171:3a7713b1edbc 1631 #define EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0
AnnaBridge 171:3a7713b1edbc 1632 #define EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1
AnnaBridge 171:3a7713b1edbc 1633 #define EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2
AnnaBridge 171:3a7713b1edbc 1634 #define EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3
AnnaBridge 171:3a7713b1edbc 1635 #define EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4
AnnaBridge 171:3a7713b1edbc 1636 #define EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5
AnnaBridge 171:3a7713b1edbc 1637 #define EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6
AnnaBridge 171:3a7713b1edbc 1638 #define EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7
AnnaBridge 171:3a7713b1edbc 1639 #define EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8
AnnaBridge 171:3a7713b1edbc 1640 #define EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9
AnnaBridge 171:3a7713b1edbc 1641 #define EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10
AnnaBridge 171:3a7713b1edbc 1642 #define EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11
AnnaBridge 171:3a7713b1edbc 1643 #define EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12
AnnaBridge 171:3a7713b1edbc 1644 #define EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13
AnnaBridge 171:3a7713b1edbc 1645 #define EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14
AnnaBridge 171:3a7713b1edbc 1646 #define EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15
AnnaBridge 171:3a7713b1edbc 1647 #define EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16
AnnaBridge 171:3a7713b1edbc 1648 #define EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17
AnnaBridge 171:3a7713b1edbc 1649 #define EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19
AnnaBridge 171:3a7713b1edbc 1650 #define EXTI_SWIER_SWI21 EXTI_SWIER_SWIER21
AnnaBridge 171:3a7713b1edbc 1651 #define EXTI_SWIER_SWI22 EXTI_SWIER_SWIER22
AnnaBridge 171:3a7713b1edbc 1652
AnnaBridge 171:3a7713b1edbc 1653 /****************** Bit definition for EXTI_PR register *********************/
AnnaBridge 171:3a7713b1edbc 1654 #define EXTI_PR_PR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1655 #define EXTI_PR_PR0_Msk (0x1U << EXTI_PR_PR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1656 #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Pending bit 0 */
AnnaBridge 171:3a7713b1edbc 1657 #define EXTI_PR_PR1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1658 #define EXTI_PR_PR1_Msk (0x1U << EXTI_PR_PR1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1659 #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Pending bit 1 */
AnnaBridge 171:3a7713b1edbc 1660 #define EXTI_PR_PR2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1661 #define EXTI_PR_PR2_Msk (0x1U << EXTI_PR_PR2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1662 #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Pending bit 2 */
AnnaBridge 171:3a7713b1edbc 1663 #define EXTI_PR_PR3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 1664 #define EXTI_PR_PR3_Msk (0x1U << EXTI_PR_PR3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1665 #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Pending bit 3 */
AnnaBridge 171:3a7713b1edbc 1666 #define EXTI_PR_PR4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1667 #define EXTI_PR_PR4_Msk (0x1U << EXTI_PR_PR4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1668 #define EXTI_PR_PR4 EXTI_PR_PR4_Msk /*!< Pending bit 4 */
AnnaBridge 171:3a7713b1edbc 1669 #define EXTI_PR_PR5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1670 #define EXTI_PR_PR5_Msk (0x1U << EXTI_PR_PR5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1671 #define EXTI_PR_PR5 EXTI_PR_PR5_Msk /*!< Pending bit 5 */
AnnaBridge 171:3a7713b1edbc 1672 #define EXTI_PR_PR6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1673 #define EXTI_PR_PR6_Msk (0x1U << EXTI_PR_PR6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1674 #define EXTI_PR_PR6 EXTI_PR_PR6_Msk /*!< Pending bit 6 */
AnnaBridge 171:3a7713b1edbc 1675 #define EXTI_PR_PR7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1676 #define EXTI_PR_PR7_Msk (0x1U << EXTI_PR_PR7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1677 #define EXTI_PR_PR7 EXTI_PR_PR7_Msk /*!< Pending bit 7 */
AnnaBridge 171:3a7713b1edbc 1678 #define EXTI_PR_PR8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1679 #define EXTI_PR_PR8_Msk (0x1U << EXTI_PR_PR8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1680 #define EXTI_PR_PR8 EXTI_PR_PR8_Msk /*!< Pending bit 8 */
AnnaBridge 171:3a7713b1edbc 1681 #define EXTI_PR_PR9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1682 #define EXTI_PR_PR9_Msk (0x1U << EXTI_PR_PR9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1683 #define EXTI_PR_PR9 EXTI_PR_PR9_Msk /*!< Pending bit 9 */
AnnaBridge 171:3a7713b1edbc 1684 #define EXTI_PR_PR10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1685 #define EXTI_PR_PR10_Msk (0x1U << EXTI_PR_PR10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1686 #define EXTI_PR_PR10 EXTI_PR_PR10_Msk /*!< Pending bit 10 */
AnnaBridge 171:3a7713b1edbc 1687 #define EXTI_PR_PR11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 1688 #define EXTI_PR_PR11_Msk (0x1U << EXTI_PR_PR11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1689 #define EXTI_PR_PR11 EXTI_PR_PR11_Msk /*!< Pending bit 11 */
AnnaBridge 171:3a7713b1edbc 1690 #define EXTI_PR_PR12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1691 #define EXTI_PR_PR12_Msk (0x1U << EXTI_PR_PR12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1692 #define EXTI_PR_PR12 EXTI_PR_PR12_Msk /*!< Pending bit 12 */
AnnaBridge 171:3a7713b1edbc 1693 #define EXTI_PR_PR13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1694 #define EXTI_PR_PR13_Msk (0x1U << EXTI_PR_PR13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1695 #define EXTI_PR_PR13 EXTI_PR_PR13_Msk /*!< Pending bit 13 */
AnnaBridge 171:3a7713b1edbc 1696 #define EXTI_PR_PR14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1697 #define EXTI_PR_PR14_Msk (0x1U << EXTI_PR_PR14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1698 #define EXTI_PR_PR14 EXTI_PR_PR14_Msk /*!< Pending bit 14 */
AnnaBridge 171:3a7713b1edbc 1699 #define EXTI_PR_PR15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 1700 #define EXTI_PR_PR15_Msk (0x1U << EXTI_PR_PR15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1701 #define EXTI_PR_PR15 EXTI_PR_PR15_Msk /*!< Pending bit 15 */
AnnaBridge 171:3a7713b1edbc 1702 #define EXTI_PR_PR16_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1703 #define EXTI_PR_PR16_Msk (0x1U << EXTI_PR_PR16_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1704 #define EXTI_PR_PR16 EXTI_PR_PR16_Msk /*!< Pending bit 16 */
AnnaBridge 171:3a7713b1edbc 1705 #define EXTI_PR_PR17_Pos (17U)
AnnaBridge 171:3a7713b1edbc 1706 #define EXTI_PR_PR17_Msk (0x1U << EXTI_PR_PR17_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1707 #define EXTI_PR_PR17 EXTI_PR_PR17_Msk /*!< Pending bit 17 */
AnnaBridge 171:3a7713b1edbc 1708 #define EXTI_PR_PR19_Pos (19U)
AnnaBridge 171:3a7713b1edbc 1709 #define EXTI_PR_PR19_Msk (0x1U << EXTI_PR_PR19_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1710 #define EXTI_PR_PR19 EXTI_PR_PR19_Msk /*!< Pending bit 19 */
AnnaBridge 171:3a7713b1edbc 1711 #define EXTI_PR_PR21_Pos (21U)
AnnaBridge 171:3a7713b1edbc 1712 #define EXTI_PR_PR21_Msk (0x1U << EXTI_PR_PR21_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1713 #define EXTI_PR_PR21 EXTI_PR_PR21_Msk /*!< Pending bit 21 */
AnnaBridge 171:3a7713b1edbc 1714 #define EXTI_PR_PR22_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1715 #define EXTI_PR_PR22_Msk (0x1U << EXTI_PR_PR22_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1716 #define EXTI_PR_PR22 EXTI_PR_PR22_Msk /*!< Pending bit 22 */
AnnaBridge 171:3a7713b1edbc 1717
AnnaBridge 171:3a7713b1edbc 1718 /* References Defines */
AnnaBridge 171:3a7713b1edbc 1719 #define EXTI_PR_PIF0 EXTI_PR_PR0
AnnaBridge 171:3a7713b1edbc 1720 #define EXTI_PR_PIF1 EXTI_PR_PR1
AnnaBridge 171:3a7713b1edbc 1721 #define EXTI_PR_PIF2 EXTI_PR_PR2
AnnaBridge 171:3a7713b1edbc 1722 #define EXTI_PR_PIF3 EXTI_PR_PR3
AnnaBridge 171:3a7713b1edbc 1723 #define EXTI_PR_PIF4 EXTI_PR_PR4
AnnaBridge 171:3a7713b1edbc 1724 #define EXTI_PR_PIF5 EXTI_PR_PR5
AnnaBridge 171:3a7713b1edbc 1725 #define EXTI_PR_PIF6 EXTI_PR_PR6
AnnaBridge 171:3a7713b1edbc 1726 #define EXTI_PR_PIF7 EXTI_PR_PR7
AnnaBridge 171:3a7713b1edbc 1727 #define EXTI_PR_PIF8 EXTI_PR_PR8
AnnaBridge 171:3a7713b1edbc 1728 #define EXTI_PR_PIF9 EXTI_PR_PR9
AnnaBridge 171:3a7713b1edbc 1729 #define EXTI_PR_PIF10 EXTI_PR_PR10
AnnaBridge 171:3a7713b1edbc 1730 #define EXTI_PR_PIF11 EXTI_PR_PR11
AnnaBridge 171:3a7713b1edbc 1731 #define EXTI_PR_PIF12 EXTI_PR_PR12
AnnaBridge 171:3a7713b1edbc 1732 #define EXTI_PR_PIF13 EXTI_PR_PR13
AnnaBridge 171:3a7713b1edbc 1733 #define EXTI_PR_PIF14 EXTI_PR_PR14
AnnaBridge 171:3a7713b1edbc 1734 #define EXTI_PR_PIF15 EXTI_PR_PR15
AnnaBridge 171:3a7713b1edbc 1735 #define EXTI_PR_PIF16 EXTI_PR_PR16
AnnaBridge 171:3a7713b1edbc 1736 #define EXTI_PR_PIF17 EXTI_PR_PR17
AnnaBridge 171:3a7713b1edbc 1737 #define EXTI_PR_PIF19 EXTI_PR_PR19
AnnaBridge 171:3a7713b1edbc 1738 #define EXTI_PR_PIF21 EXTI_PR_PR21
AnnaBridge 171:3a7713b1edbc 1739 #define EXTI_PR_PIF22 EXTI_PR_PR22
AnnaBridge 171:3a7713b1edbc 1740
AnnaBridge 171:3a7713b1edbc 1741 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1742 /* */
AnnaBridge 171:3a7713b1edbc 1743 /* FLASH and Option Bytes Registers */
AnnaBridge 171:3a7713b1edbc 1744 /* */
AnnaBridge 171:3a7713b1edbc 1745 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1746
AnnaBridge 171:3a7713b1edbc 1747 /******************* Bit definition for FLASH_ACR register ******************/
AnnaBridge 171:3a7713b1edbc 1748 #define FLASH_ACR_LATENCY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1749 #define FLASH_ACR_LATENCY_Msk (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1750 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< LATENCY bit (Latency) */
AnnaBridge 171:3a7713b1edbc 1751
AnnaBridge 171:3a7713b1edbc 1752 #define FLASH_ACR_PRFTBE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1753 #define FLASH_ACR_PRFTBE_Msk (0x1U << FLASH_ACR_PRFTBE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1754 #define FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk /*!< Prefetch Buffer Enable */
AnnaBridge 171:3a7713b1edbc 1755 #define FLASH_ACR_PRFTBS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1756 #define FLASH_ACR_PRFTBS_Msk (0x1U << FLASH_ACR_PRFTBS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1757 #define FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk /*!< Prefetch Buffer Status */
AnnaBridge 171:3a7713b1edbc 1758
AnnaBridge 171:3a7713b1edbc 1759 /****************** Bit definition for FLASH_KEYR register ******************/
AnnaBridge 171:3a7713b1edbc 1760 #define FLASH_KEYR_FKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1761 #define FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFU << FLASH_KEYR_FKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1762 #define FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk /*!< FPEC Key */
AnnaBridge 171:3a7713b1edbc 1763
AnnaBridge 171:3a7713b1edbc 1764 /***************** Bit definition for FLASH_OPTKEYR register ****************/
AnnaBridge 171:3a7713b1edbc 1765 #define FLASH_OPTKEYR_OPTKEYR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1766 #define FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1767 #define FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk /*!< Option Byte Key */
AnnaBridge 171:3a7713b1edbc 1768
AnnaBridge 171:3a7713b1edbc 1769 /****************** FLASH Keys **********************************************/
AnnaBridge 171:3a7713b1edbc 1770 #define FLASH_KEY1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1771 #define FLASH_KEY1_Msk (0x45670123U << FLASH_KEY1_Pos) /*!< 0x45670123 */
AnnaBridge 171:3a7713b1edbc 1772 #define FLASH_KEY1 FLASH_KEY1_Msk /*!< Flash program erase key1 */
AnnaBridge 171:3a7713b1edbc 1773 #define FLASH_KEY2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1774 #define FLASH_KEY2_Msk (0xCDEF89ABU << FLASH_KEY2_Pos) /*!< 0xCDEF89AB */
AnnaBridge 171:3a7713b1edbc 1775 #define FLASH_KEY2 FLASH_KEY2_Msk /*!< Flash program erase key2: used with FLASH_PEKEY1
AnnaBridge 171:3a7713b1edbc 1776 to unlock the write access to the FPEC. */
AnnaBridge 171:3a7713b1edbc 1777
AnnaBridge 171:3a7713b1edbc 1778 #define FLASH_OPTKEY1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1779 #define FLASH_OPTKEY1_Msk (0x45670123U << FLASH_OPTKEY1_Pos) /*!< 0x45670123 */
AnnaBridge 171:3a7713b1edbc 1780 #define FLASH_OPTKEY1 FLASH_OPTKEY1_Msk /*!< Flash option key1 */
AnnaBridge 171:3a7713b1edbc 1781 #define FLASH_OPTKEY2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1782 #define FLASH_OPTKEY2_Msk (0xCDEF89ABU << FLASH_OPTKEY2_Pos) /*!< 0xCDEF89AB */
AnnaBridge 171:3a7713b1edbc 1783 #define FLASH_OPTKEY2 FLASH_OPTKEY2_Msk /*!< Flash option key2: used with FLASH_OPTKEY1 to
AnnaBridge 171:3a7713b1edbc 1784 unlock the write access to the option byte block */
AnnaBridge 171:3a7713b1edbc 1785
AnnaBridge 171:3a7713b1edbc 1786 /****************** Bit definition for FLASH_SR register *******************/
AnnaBridge 171:3a7713b1edbc 1787 #define FLASH_SR_BSY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1788 #define FLASH_SR_BSY_Msk (0x1U << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1789 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy */
AnnaBridge 171:3a7713b1edbc 1790 #define FLASH_SR_PGERR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1791 #define FLASH_SR_PGERR_Msk (0x1U << FLASH_SR_PGERR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1792 #define FLASH_SR_PGERR FLASH_SR_PGERR_Msk /*!< Programming Error */
AnnaBridge 171:3a7713b1edbc 1793 #define FLASH_SR_WRPRTERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1794 #define FLASH_SR_WRPRTERR_Msk (0x1U << FLASH_SR_WRPRTERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1795 #define FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk /*!< Write Protection Error */
AnnaBridge 171:3a7713b1edbc 1796 #define FLASH_SR_EOP_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1797 #define FLASH_SR_EOP_Msk (0x1U << FLASH_SR_EOP_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1798 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End of operation */
AnnaBridge 171:3a7713b1edbc 1799 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
AnnaBridge 171:3a7713b1edbc 1800
AnnaBridge 171:3a7713b1edbc 1801 /******************* Bit definition for FLASH_CR register *******************/
AnnaBridge 171:3a7713b1edbc 1802 #define FLASH_CR_PG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1803 #define FLASH_CR_PG_Msk (0x1U << FLASH_CR_PG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1804 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Programming */
AnnaBridge 171:3a7713b1edbc 1805 #define FLASH_CR_PER_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1806 #define FLASH_CR_PER_Msk (0x1U << FLASH_CR_PER_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1807 #define FLASH_CR_PER FLASH_CR_PER_Msk /*!< Page Erase */
AnnaBridge 171:3a7713b1edbc 1808 #define FLASH_CR_MER_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1809 #define FLASH_CR_MER_Msk (0x1U << FLASH_CR_MER_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1810 #define FLASH_CR_MER FLASH_CR_MER_Msk /*!< Mass Erase */
AnnaBridge 171:3a7713b1edbc 1811 #define FLASH_CR_OPTPG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1812 #define FLASH_CR_OPTPG_Msk (0x1U << FLASH_CR_OPTPG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1813 #define FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk /*!< Option Byte Programming */
AnnaBridge 171:3a7713b1edbc 1814 #define FLASH_CR_OPTER_Pos (5U)
AnnaBridge 171:3a7713b1edbc 1815 #define FLASH_CR_OPTER_Msk (0x1U << FLASH_CR_OPTER_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1816 #define FLASH_CR_OPTER FLASH_CR_OPTER_Msk /*!< Option Byte Erase */
AnnaBridge 171:3a7713b1edbc 1817 #define FLASH_CR_STRT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1818 #define FLASH_CR_STRT_Msk (0x1U << FLASH_CR_STRT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1819 #define FLASH_CR_STRT FLASH_CR_STRT_Msk /*!< Start */
AnnaBridge 171:3a7713b1edbc 1820 #define FLASH_CR_LOCK_Pos (7U)
AnnaBridge 171:3a7713b1edbc 1821 #define FLASH_CR_LOCK_Msk (0x1U << FLASH_CR_LOCK_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1822 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Lock */
AnnaBridge 171:3a7713b1edbc 1823 #define FLASH_CR_OPTWRE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1824 #define FLASH_CR_OPTWRE_Msk (0x1U << FLASH_CR_OPTWRE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1825 #define FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk /*!< Option Bytes Write Enable */
AnnaBridge 171:3a7713b1edbc 1826 #define FLASH_CR_ERRIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1827 #define FLASH_CR_ERRIE_Msk (0x1U << FLASH_CR_ERRIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1828 #define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1829 #define FLASH_CR_EOPIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1830 #define FLASH_CR_EOPIE_Msk (0x1U << FLASH_CR_EOPIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1831 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End of operation interrupt enable */
AnnaBridge 171:3a7713b1edbc 1832 #define FLASH_CR_OBL_LAUNCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1833 #define FLASH_CR_OBL_LAUNCH_Msk (0x1U << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1834 #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Option Bytes Loader Launch */
AnnaBridge 171:3a7713b1edbc 1835
AnnaBridge 171:3a7713b1edbc 1836 /******************* Bit definition for FLASH_AR register *******************/
AnnaBridge 171:3a7713b1edbc 1837 #define FLASH_AR_FAR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1838 #define FLASH_AR_FAR_Msk (0xFFFFFFFFU << FLASH_AR_FAR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 1839 #define FLASH_AR_FAR FLASH_AR_FAR_Msk /*!< Flash Address */
AnnaBridge 171:3a7713b1edbc 1840
AnnaBridge 171:3a7713b1edbc 1841 /****************** Bit definition for FLASH_OBR register *******************/
AnnaBridge 171:3a7713b1edbc 1842 #define FLASH_OBR_OPTERR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1843 #define FLASH_OBR_OPTERR_Msk (0x1U << FLASH_OBR_OPTERR_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1844 #define FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk /*!< Option Byte Error */
AnnaBridge 171:3a7713b1edbc 1845 #define FLASH_OBR_RDPRT1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 1846 #define FLASH_OBR_RDPRT1_Msk (0x1U << FLASH_OBR_RDPRT1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1847 #define FLASH_OBR_RDPRT1 FLASH_OBR_RDPRT1_Msk /*!< Read protection Level 1 */
AnnaBridge 171:3a7713b1edbc 1848 #define FLASH_OBR_RDPRT2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1849 #define FLASH_OBR_RDPRT2_Msk (0x1U << FLASH_OBR_RDPRT2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1850 #define FLASH_OBR_RDPRT2 FLASH_OBR_RDPRT2_Msk /*!< Read protection Level 2 */
AnnaBridge 171:3a7713b1edbc 1851
AnnaBridge 171:3a7713b1edbc 1852 #define FLASH_OBR_USER_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1853 #define FLASH_OBR_USER_Msk (0x77U << FLASH_OBR_USER_Pos) /*!< 0x00007700 */
AnnaBridge 171:3a7713b1edbc 1854 #define FLASH_OBR_USER FLASH_OBR_USER_Msk /*!< User Option Bytes */
AnnaBridge 171:3a7713b1edbc 1855 #define FLASH_OBR_IWDG_SW_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1856 #define FLASH_OBR_IWDG_SW_Msk (0x1U << FLASH_OBR_IWDG_SW_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1857 #define FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk /*!< IWDG SW */
AnnaBridge 171:3a7713b1edbc 1858 #define FLASH_OBR_nRST_STOP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 1859 #define FLASH_OBR_nRST_STOP_Msk (0x1U << FLASH_OBR_nRST_STOP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1860 #define FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk /*!< nRST_STOP */
AnnaBridge 171:3a7713b1edbc 1861 #define FLASH_OBR_nRST_STDBY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1862 #define FLASH_OBR_nRST_STDBY_Msk (0x1U << FLASH_OBR_nRST_STDBY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1863 #define FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk /*!< nRST_STDBY */
AnnaBridge 171:3a7713b1edbc 1864 #define FLASH_OBR_nBOOT1_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1865 #define FLASH_OBR_nBOOT1_Msk (0x1U << FLASH_OBR_nBOOT1_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1866 #define FLASH_OBR_nBOOT1 FLASH_OBR_nBOOT1_Msk /*!< nBOOT1 */
AnnaBridge 171:3a7713b1edbc 1867 #define FLASH_OBR_VDDA_MONITOR_Pos (13U)
AnnaBridge 171:3a7713b1edbc 1868 #define FLASH_OBR_VDDA_MONITOR_Msk (0x1U << FLASH_OBR_VDDA_MONITOR_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1869 #define FLASH_OBR_VDDA_MONITOR FLASH_OBR_VDDA_MONITOR_Msk /*!< VDDA power supply supervisor */
AnnaBridge 171:3a7713b1edbc 1870 #define FLASH_OBR_RAM_PARITY_CHECK_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1871 #define FLASH_OBR_RAM_PARITY_CHECK_Msk (0x1U << FLASH_OBR_RAM_PARITY_CHECK_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1872 #define FLASH_OBR_RAM_PARITY_CHECK FLASH_OBR_RAM_PARITY_CHECK_Msk /*!< RAM parity check */
AnnaBridge 171:3a7713b1edbc 1873 #define FLASH_OBR_DATA0_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1874 #define FLASH_OBR_DATA0_Msk (0xFFU << FLASH_OBR_DATA0_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 1875 #define FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk /*!< Data0 */
AnnaBridge 171:3a7713b1edbc 1876 #define FLASH_OBR_DATA1_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1877 #define FLASH_OBR_DATA1_Msk (0xFFU << FLASH_OBR_DATA1_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 1878 #define FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk /*!< Data1 */
AnnaBridge 171:3a7713b1edbc 1879
AnnaBridge 171:3a7713b1edbc 1880 /* Old BOOT1 bit definition, maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 1881 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
AnnaBridge 171:3a7713b1edbc 1882
AnnaBridge 171:3a7713b1edbc 1883 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 1884 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
AnnaBridge 171:3a7713b1edbc 1885
AnnaBridge 171:3a7713b1edbc 1886 /****************** Bit definition for FLASH_WRPR register ******************/
AnnaBridge 171:3a7713b1edbc 1887 #define FLASH_WRPR_WRP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1888 #define FLASH_WRPR_WRP_Msk (0xFFFFU << FLASH_WRPR_WRP_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 1889 #define FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk /*!< Write Protect */
AnnaBridge 171:3a7713b1edbc 1890
AnnaBridge 171:3a7713b1edbc 1891 /*----------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 1892
AnnaBridge 171:3a7713b1edbc 1893 /****************** Bit definition for OB_RDP register **********************/
AnnaBridge 171:3a7713b1edbc 1894 #define OB_RDP_RDP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1895 #define OB_RDP_RDP_Msk (0xFFU << OB_RDP_RDP_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1896 #define OB_RDP_RDP OB_RDP_RDP_Msk /*!< Read protection option byte */
AnnaBridge 171:3a7713b1edbc 1897 #define OB_RDP_nRDP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1898 #define OB_RDP_nRDP_Msk (0xFFU << OB_RDP_nRDP_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 1899 #define OB_RDP_nRDP OB_RDP_nRDP_Msk /*!< Read protection complemented option byte */
AnnaBridge 171:3a7713b1edbc 1900
AnnaBridge 171:3a7713b1edbc 1901 /****************** Bit definition for OB_USER register *********************/
AnnaBridge 171:3a7713b1edbc 1902 #define OB_USER_USER_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1903 #define OB_USER_USER_Msk (0xFFU << OB_USER_USER_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 1904 #define OB_USER_USER OB_USER_USER_Msk /*!< User option byte */
AnnaBridge 171:3a7713b1edbc 1905 #define OB_USER_nUSER_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1906 #define OB_USER_nUSER_Msk (0xFFU << OB_USER_nUSER_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 1907 #define OB_USER_nUSER OB_USER_nUSER_Msk /*!< User complemented option byte */
AnnaBridge 171:3a7713b1edbc 1908
AnnaBridge 171:3a7713b1edbc 1909 /****************** Bit definition for OB_WRP0 register *********************/
AnnaBridge 171:3a7713b1edbc 1910 #define OB_WRP0_WRP0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1911 #define OB_WRP0_WRP0_Msk (0xFFU << OB_WRP0_WRP0_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 1912 #define OB_WRP0_WRP0 OB_WRP0_WRP0_Msk /*!< Flash memory write protection option bytes */
AnnaBridge 171:3a7713b1edbc 1913 #define OB_WRP0_nWRP0_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1914 #define OB_WRP0_nWRP0_Msk (0xFFU << OB_WRP0_nWRP0_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 1915 #define OB_WRP0_nWRP0 OB_WRP0_nWRP0_Msk /*!< Flash memory write protection complemented option bytes */
AnnaBridge 171:3a7713b1edbc 1916
AnnaBridge 171:3a7713b1edbc 1917 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1918 /* */
AnnaBridge 171:3a7713b1edbc 1919 /* General Purpose IOs (GPIO) */
AnnaBridge 171:3a7713b1edbc 1920 /* */
AnnaBridge 171:3a7713b1edbc 1921 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 1922 /******************* Bit definition for GPIO_MODER register *****************/
AnnaBridge 171:3a7713b1edbc 1923 #define GPIO_MODER_MODER0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 1924 #define GPIO_MODER_MODER0_Msk (0x3U << GPIO_MODER_MODER0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 1925 #define GPIO_MODER_MODER0 GPIO_MODER_MODER0_Msk
AnnaBridge 171:3a7713b1edbc 1926 #define GPIO_MODER_MODER0_0 (0x1U << GPIO_MODER_MODER0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 1927 #define GPIO_MODER_MODER0_1 (0x2U << GPIO_MODER_MODER0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 1928 #define GPIO_MODER_MODER1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 1929 #define GPIO_MODER_MODER1_Msk (0x3U << GPIO_MODER_MODER1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 1930 #define GPIO_MODER_MODER1 GPIO_MODER_MODER1_Msk
AnnaBridge 171:3a7713b1edbc 1931 #define GPIO_MODER_MODER1_0 (0x1U << GPIO_MODER_MODER1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 1932 #define GPIO_MODER_MODER1_1 (0x2U << GPIO_MODER_MODER1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 1933 #define GPIO_MODER_MODER2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 1934 #define GPIO_MODER_MODER2_Msk (0x3U << GPIO_MODER_MODER2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 1935 #define GPIO_MODER_MODER2 GPIO_MODER_MODER2_Msk
AnnaBridge 171:3a7713b1edbc 1936 #define GPIO_MODER_MODER2_0 (0x1U << GPIO_MODER_MODER2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 1937 #define GPIO_MODER_MODER2_1 (0x2U << GPIO_MODER_MODER2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 1938 #define GPIO_MODER_MODER3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 1939 #define GPIO_MODER_MODER3_Msk (0x3U << GPIO_MODER_MODER3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 1940 #define GPIO_MODER_MODER3 GPIO_MODER_MODER3_Msk
AnnaBridge 171:3a7713b1edbc 1941 #define GPIO_MODER_MODER3_0 (0x1U << GPIO_MODER_MODER3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 1942 #define GPIO_MODER_MODER3_1 (0x2U << GPIO_MODER_MODER3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 1943 #define GPIO_MODER_MODER4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 1944 #define GPIO_MODER_MODER4_Msk (0x3U << GPIO_MODER_MODER4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 1945 #define GPIO_MODER_MODER4 GPIO_MODER_MODER4_Msk
AnnaBridge 171:3a7713b1edbc 1946 #define GPIO_MODER_MODER4_0 (0x1U << GPIO_MODER_MODER4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 1947 #define GPIO_MODER_MODER4_1 (0x2U << GPIO_MODER_MODER4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 1948 #define GPIO_MODER_MODER5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 1949 #define GPIO_MODER_MODER5_Msk (0x3U << GPIO_MODER_MODER5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 1950 #define GPIO_MODER_MODER5 GPIO_MODER_MODER5_Msk
AnnaBridge 171:3a7713b1edbc 1951 #define GPIO_MODER_MODER5_0 (0x1U << GPIO_MODER_MODER5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 1952 #define GPIO_MODER_MODER5_1 (0x2U << GPIO_MODER_MODER5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 1953 #define GPIO_MODER_MODER6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 1954 #define GPIO_MODER_MODER6_Msk (0x3U << GPIO_MODER_MODER6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 1955 #define GPIO_MODER_MODER6 GPIO_MODER_MODER6_Msk
AnnaBridge 171:3a7713b1edbc 1956 #define GPIO_MODER_MODER6_0 (0x1U << GPIO_MODER_MODER6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 1957 #define GPIO_MODER_MODER6_1 (0x2U << GPIO_MODER_MODER6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 1958 #define GPIO_MODER_MODER7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 1959 #define GPIO_MODER_MODER7_Msk (0x3U << GPIO_MODER_MODER7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 1960 #define GPIO_MODER_MODER7 GPIO_MODER_MODER7_Msk
AnnaBridge 171:3a7713b1edbc 1961 #define GPIO_MODER_MODER7_0 (0x1U << GPIO_MODER_MODER7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 1962 #define GPIO_MODER_MODER7_1 (0x2U << GPIO_MODER_MODER7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 1963 #define GPIO_MODER_MODER8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 1964 #define GPIO_MODER_MODER8_Msk (0x3U << GPIO_MODER_MODER8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 1965 #define GPIO_MODER_MODER8 GPIO_MODER_MODER8_Msk
AnnaBridge 171:3a7713b1edbc 1966 #define GPIO_MODER_MODER8_0 (0x1U << GPIO_MODER_MODER8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 1967 #define GPIO_MODER_MODER8_1 (0x2U << GPIO_MODER_MODER8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 1968 #define GPIO_MODER_MODER9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 1969 #define GPIO_MODER_MODER9_Msk (0x3U << GPIO_MODER_MODER9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 1970 #define GPIO_MODER_MODER9 GPIO_MODER_MODER9_Msk
AnnaBridge 171:3a7713b1edbc 1971 #define GPIO_MODER_MODER9_0 (0x1U << GPIO_MODER_MODER9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 1972 #define GPIO_MODER_MODER9_1 (0x2U << GPIO_MODER_MODER9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 1973 #define GPIO_MODER_MODER10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 1974 #define GPIO_MODER_MODER10_Msk (0x3U << GPIO_MODER_MODER10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 1975 #define GPIO_MODER_MODER10 GPIO_MODER_MODER10_Msk
AnnaBridge 171:3a7713b1edbc 1976 #define GPIO_MODER_MODER10_0 (0x1U << GPIO_MODER_MODER10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 1977 #define GPIO_MODER_MODER10_1 (0x2U << GPIO_MODER_MODER10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 1978 #define GPIO_MODER_MODER11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 1979 #define GPIO_MODER_MODER11_Msk (0x3U << GPIO_MODER_MODER11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 1980 #define GPIO_MODER_MODER11 GPIO_MODER_MODER11_Msk
AnnaBridge 171:3a7713b1edbc 1981 #define GPIO_MODER_MODER11_0 (0x1U << GPIO_MODER_MODER11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 1982 #define GPIO_MODER_MODER11_1 (0x2U << GPIO_MODER_MODER11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 1983 #define GPIO_MODER_MODER12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 1984 #define GPIO_MODER_MODER12_Msk (0x3U << GPIO_MODER_MODER12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 1985 #define GPIO_MODER_MODER12 GPIO_MODER_MODER12_Msk
AnnaBridge 171:3a7713b1edbc 1986 #define GPIO_MODER_MODER12_0 (0x1U << GPIO_MODER_MODER12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 1987 #define GPIO_MODER_MODER12_1 (0x2U << GPIO_MODER_MODER12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 1988 #define GPIO_MODER_MODER13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 1989 #define GPIO_MODER_MODER13_Msk (0x3U << GPIO_MODER_MODER13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 1990 #define GPIO_MODER_MODER13 GPIO_MODER_MODER13_Msk
AnnaBridge 171:3a7713b1edbc 1991 #define GPIO_MODER_MODER13_0 (0x1U << GPIO_MODER_MODER13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 1992 #define GPIO_MODER_MODER13_1 (0x2U << GPIO_MODER_MODER13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 1993 #define GPIO_MODER_MODER14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 1994 #define GPIO_MODER_MODER14_Msk (0x3U << GPIO_MODER_MODER14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 1995 #define GPIO_MODER_MODER14 GPIO_MODER_MODER14_Msk
AnnaBridge 171:3a7713b1edbc 1996 #define GPIO_MODER_MODER14_0 (0x1U << GPIO_MODER_MODER14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 1997 #define GPIO_MODER_MODER14_1 (0x2U << GPIO_MODER_MODER14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 1998 #define GPIO_MODER_MODER15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 1999 #define GPIO_MODER_MODER15_Msk (0x3U << GPIO_MODER_MODER15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2000 #define GPIO_MODER_MODER15 GPIO_MODER_MODER15_Msk
AnnaBridge 171:3a7713b1edbc 2001 #define GPIO_MODER_MODER15_0 (0x1U << GPIO_MODER_MODER15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2002 #define GPIO_MODER_MODER15_1 (0x2U << GPIO_MODER_MODER15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2003
AnnaBridge 171:3a7713b1edbc 2004 /****************** Bit definition for GPIO_OTYPER register *****************/
AnnaBridge 171:3a7713b1edbc 2005 #define GPIO_OTYPER_OT_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 2006 #define GPIO_OTYPER_OT_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 2007 #define GPIO_OTYPER_OT_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 2008 #define GPIO_OTYPER_OT_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 2009 #define GPIO_OTYPER_OT_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 2010 #define GPIO_OTYPER_OT_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 2011 #define GPIO_OTYPER_OT_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 2012 #define GPIO_OTYPER_OT_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 2013 #define GPIO_OTYPER_OT_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 2014 #define GPIO_OTYPER_OT_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 2015 #define GPIO_OTYPER_OT_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 2016 #define GPIO_OTYPER_OT_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 2017 #define GPIO_OTYPER_OT_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 2018 #define GPIO_OTYPER_OT_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 2019 #define GPIO_OTYPER_OT_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 2020 #define GPIO_OTYPER_OT_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 2021
AnnaBridge 171:3a7713b1edbc 2022 /**************** Bit definition for GPIO_OSPEEDR register ******************/
AnnaBridge 171:3a7713b1edbc 2023 #define GPIO_OSPEEDR_OSPEEDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2024 #define GPIO_OSPEEDR_OSPEEDR0_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2025 #define GPIO_OSPEEDR_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0_Msk
AnnaBridge 171:3a7713b1edbc 2026 #define GPIO_OSPEEDR_OSPEEDR0_0 (0x1U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2027 #define GPIO_OSPEEDR_OSPEEDR0_1 (0x2U << GPIO_OSPEEDR_OSPEEDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2028 #define GPIO_OSPEEDR_OSPEEDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2029 #define GPIO_OSPEEDR_OSPEEDR1_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2030 #define GPIO_OSPEEDR_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1_Msk
AnnaBridge 171:3a7713b1edbc 2031 #define GPIO_OSPEEDR_OSPEEDR1_0 (0x1U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2032 #define GPIO_OSPEEDR_OSPEEDR1_1 (0x2U << GPIO_OSPEEDR_OSPEEDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2033 #define GPIO_OSPEEDR_OSPEEDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2034 #define GPIO_OSPEEDR_OSPEEDR2_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 2035 #define GPIO_OSPEEDR_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2_Msk
AnnaBridge 171:3a7713b1edbc 2036 #define GPIO_OSPEEDR_OSPEEDR2_0 (0x1U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2037 #define GPIO_OSPEEDR_OSPEEDR2_1 (0x2U << GPIO_OSPEEDR_OSPEEDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2038 #define GPIO_OSPEEDR_OSPEEDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2039 #define GPIO_OSPEEDR_OSPEEDR3_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2040 #define GPIO_OSPEEDR_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3_Msk
AnnaBridge 171:3a7713b1edbc 2041 #define GPIO_OSPEEDR_OSPEEDR3_0 (0x1U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2042 #define GPIO_OSPEEDR_OSPEEDR3_1 (0x2U << GPIO_OSPEEDR_OSPEEDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2043 #define GPIO_OSPEEDR_OSPEEDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2044 #define GPIO_OSPEEDR_OSPEEDR4_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2045 #define GPIO_OSPEEDR_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4_Msk
AnnaBridge 171:3a7713b1edbc 2046 #define GPIO_OSPEEDR_OSPEEDR4_0 (0x1U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2047 #define GPIO_OSPEEDR_OSPEEDR4_1 (0x2U << GPIO_OSPEEDR_OSPEEDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2048 #define GPIO_OSPEEDR_OSPEEDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2049 #define GPIO_OSPEEDR_OSPEEDR5_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2050 #define GPIO_OSPEEDR_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5_Msk
AnnaBridge 171:3a7713b1edbc 2051 #define GPIO_OSPEEDR_OSPEEDR5_0 (0x1U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2052 #define GPIO_OSPEEDR_OSPEEDR5_1 (0x2U << GPIO_OSPEEDR_OSPEEDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2053 #define GPIO_OSPEEDR_OSPEEDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2054 #define GPIO_OSPEEDR_OSPEEDR6_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2055 #define GPIO_OSPEEDR_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6_Msk
AnnaBridge 171:3a7713b1edbc 2056 #define GPIO_OSPEEDR_OSPEEDR6_0 (0x1U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2057 #define GPIO_OSPEEDR_OSPEEDR6_1 (0x2U << GPIO_OSPEEDR_OSPEEDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2058 #define GPIO_OSPEEDR_OSPEEDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2059 #define GPIO_OSPEEDR_OSPEEDR7_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2060 #define GPIO_OSPEEDR_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7_Msk
AnnaBridge 171:3a7713b1edbc 2061 #define GPIO_OSPEEDR_OSPEEDR7_0 (0x1U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2062 #define GPIO_OSPEEDR_OSPEEDR7_1 (0x2U << GPIO_OSPEEDR_OSPEEDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2063 #define GPIO_OSPEEDR_OSPEEDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2064 #define GPIO_OSPEEDR_OSPEEDR8_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2065 #define GPIO_OSPEEDR_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8_Msk
AnnaBridge 171:3a7713b1edbc 2066 #define GPIO_OSPEEDR_OSPEEDR8_0 (0x1U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2067 #define GPIO_OSPEEDR_OSPEEDR8_1 (0x2U << GPIO_OSPEEDR_OSPEEDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2068 #define GPIO_OSPEEDR_OSPEEDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2069 #define GPIO_OSPEEDR_OSPEEDR9_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2070 #define GPIO_OSPEEDR_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9_Msk
AnnaBridge 171:3a7713b1edbc 2071 #define GPIO_OSPEEDR_OSPEEDR9_0 (0x1U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2072 #define GPIO_OSPEEDR_OSPEEDR9_1 (0x2U << GPIO_OSPEEDR_OSPEEDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2073 #define GPIO_OSPEEDR_OSPEEDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2074 #define GPIO_OSPEEDR_OSPEEDR10_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 2075 #define GPIO_OSPEEDR_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10_Msk
AnnaBridge 171:3a7713b1edbc 2076 #define GPIO_OSPEEDR_OSPEEDR10_0 (0x1U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2077 #define GPIO_OSPEEDR_OSPEEDR10_1 (0x2U << GPIO_OSPEEDR_OSPEEDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2078 #define GPIO_OSPEEDR_OSPEEDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2079 #define GPIO_OSPEEDR_OSPEEDR11_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 2080 #define GPIO_OSPEEDR_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11_Msk
AnnaBridge 171:3a7713b1edbc 2081 #define GPIO_OSPEEDR_OSPEEDR11_0 (0x1U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2082 #define GPIO_OSPEEDR_OSPEEDR11_1 (0x2U << GPIO_OSPEEDR_OSPEEDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2083 #define GPIO_OSPEEDR_OSPEEDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2084 #define GPIO_OSPEEDR_OSPEEDR12_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2085 #define GPIO_OSPEEDR_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12_Msk
AnnaBridge 171:3a7713b1edbc 2086 #define GPIO_OSPEEDR_OSPEEDR12_0 (0x1U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2087 #define GPIO_OSPEEDR_OSPEEDR12_1 (0x2U << GPIO_OSPEEDR_OSPEEDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2088 #define GPIO_OSPEEDR_OSPEEDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2089 #define GPIO_OSPEEDR_OSPEEDR13_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 2090 #define GPIO_OSPEEDR_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13_Msk
AnnaBridge 171:3a7713b1edbc 2091 #define GPIO_OSPEEDR_OSPEEDR13_0 (0x1U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2092 #define GPIO_OSPEEDR_OSPEEDR13_1 (0x2U << GPIO_OSPEEDR_OSPEEDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2093 #define GPIO_OSPEEDR_OSPEEDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2094 #define GPIO_OSPEEDR_OSPEEDR14_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 2095 #define GPIO_OSPEEDR_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14_Msk
AnnaBridge 171:3a7713b1edbc 2096 #define GPIO_OSPEEDR_OSPEEDR14_0 (0x1U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2097 #define GPIO_OSPEEDR_OSPEEDR14_1 (0x2U << GPIO_OSPEEDR_OSPEEDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2098 #define GPIO_OSPEEDR_OSPEEDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2099 #define GPIO_OSPEEDR_OSPEEDR15_Msk (0x3U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2100 #define GPIO_OSPEEDR_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15_Msk
AnnaBridge 171:3a7713b1edbc 2101 #define GPIO_OSPEEDR_OSPEEDR15_0 (0x1U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2102 #define GPIO_OSPEEDR_OSPEEDR15_1 (0x2U << GPIO_OSPEEDR_OSPEEDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2103
AnnaBridge 171:3a7713b1edbc 2104 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 2105 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
AnnaBridge 171:3a7713b1edbc 2106 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
AnnaBridge 171:3a7713b1edbc 2107 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
AnnaBridge 171:3a7713b1edbc 2108 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
AnnaBridge 171:3a7713b1edbc 2109 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
AnnaBridge 171:3a7713b1edbc 2110 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
AnnaBridge 171:3a7713b1edbc 2111 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
AnnaBridge 171:3a7713b1edbc 2112 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
AnnaBridge 171:3a7713b1edbc 2113 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
AnnaBridge 171:3a7713b1edbc 2114 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
AnnaBridge 171:3a7713b1edbc 2115 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
AnnaBridge 171:3a7713b1edbc 2116 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
AnnaBridge 171:3a7713b1edbc 2117 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
AnnaBridge 171:3a7713b1edbc 2118 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
AnnaBridge 171:3a7713b1edbc 2119 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
AnnaBridge 171:3a7713b1edbc 2120 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
AnnaBridge 171:3a7713b1edbc 2121 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
AnnaBridge 171:3a7713b1edbc 2122 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
AnnaBridge 171:3a7713b1edbc 2123 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
AnnaBridge 171:3a7713b1edbc 2124 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
AnnaBridge 171:3a7713b1edbc 2125 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
AnnaBridge 171:3a7713b1edbc 2126 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
AnnaBridge 171:3a7713b1edbc 2127 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
AnnaBridge 171:3a7713b1edbc 2128 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
AnnaBridge 171:3a7713b1edbc 2129 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
AnnaBridge 171:3a7713b1edbc 2130 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
AnnaBridge 171:3a7713b1edbc 2131 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
AnnaBridge 171:3a7713b1edbc 2132 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
AnnaBridge 171:3a7713b1edbc 2133 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
AnnaBridge 171:3a7713b1edbc 2134 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
AnnaBridge 171:3a7713b1edbc 2135 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
AnnaBridge 171:3a7713b1edbc 2136 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
AnnaBridge 171:3a7713b1edbc 2137 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
AnnaBridge 171:3a7713b1edbc 2138 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
AnnaBridge 171:3a7713b1edbc 2139 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
AnnaBridge 171:3a7713b1edbc 2140 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
AnnaBridge 171:3a7713b1edbc 2141 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
AnnaBridge 171:3a7713b1edbc 2142 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
AnnaBridge 171:3a7713b1edbc 2143 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
AnnaBridge 171:3a7713b1edbc 2144 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
AnnaBridge 171:3a7713b1edbc 2145 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
AnnaBridge 171:3a7713b1edbc 2146 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
AnnaBridge 171:3a7713b1edbc 2147 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
AnnaBridge 171:3a7713b1edbc 2148 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
AnnaBridge 171:3a7713b1edbc 2149 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
AnnaBridge 171:3a7713b1edbc 2150 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
AnnaBridge 171:3a7713b1edbc 2151 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
AnnaBridge 171:3a7713b1edbc 2152 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
AnnaBridge 171:3a7713b1edbc 2153
AnnaBridge 171:3a7713b1edbc 2154 /******************* Bit definition for GPIO_PUPDR register ******************/
AnnaBridge 171:3a7713b1edbc 2155 #define GPIO_PUPDR_PUPDR0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2156 #define GPIO_PUPDR_PUPDR0_Msk (0x3U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2157 #define GPIO_PUPDR_PUPDR0 GPIO_PUPDR_PUPDR0_Msk
AnnaBridge 171:3a7713b1edbc 2158 #define GPIO_PUPDR_PUPDR0_0 (0x1U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2159 #define GPIO_PUPDR_PUPDR0_1 (0x2U << GPIO_PUPDR_PUPDR0_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2160 #define GPIO_PUPDR_PUPDR1_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2161 #define GPIO_PUPDR_PUPDR1_Msk (0x3U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2162 #define GPIO_PUPDR_PUPDR1 GPIO_PUPDR_PUPDR1_Msk
AnnaBridge 171:3a7713b1edbc 2163 #define GPIO_PUPDR_PUPDR1_0 (0x1U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2164 #define GPIO_PUPDR_PUPDR1_1 (0x2U << GPIO_PUPDR_PUPDR1_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2165 #define GPIO_PUPDR_PUPDR2_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2166 #define GPIO_PUPDR_PUPDR2_Msk (0x3U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 2167 #define GPIO_PUPDR_PUPDR2 GPIO_PUPDR_PUPDR2_Msk
AnnaBridge 171:3a7713b1edbc 2168 #define GPIO_PUPDR_PUPDR2_0 (0x1U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2169 #define GPIO_PUPDR_PUPDR2_1 (0x2U << GPIO_PUPDR_PUPDR2_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2170 #define GPIO_PUPDR_PUPDR3_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2171 #define GPIO_PUPDR_PUPDR3_Msk (0x3U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x000000C0 */
AnnaBridge 171:3a7713b1edbc 2172 #define GPIO_PUPDR_PUPDR3 GPIO_PUPDR_PUPDR3_Msk
AnnaBridge 171:3a7713b1edbc 2173 #define GPIO_PUPDR_PUPDR3_0 (0x1U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2174 #define GPIO_PUPDR_PUPDR3_1 (0x2U << GPIO_PUPDR_PUPDR3_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2175 #define GPIO_PUPDR_PUPDR4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2176 #define GPIO_PUPDR_PUPDR4_Msk (0x3U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2177 #define GPIO_PUPDR_PUPDR4 GPIO_PUPDR_PUPDR4_Msk
AnnaBridge 171:3a7713b1edbc 2178 #define GPIO_PUPDR_PUPDR4_0 (0x1U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2179 #define GPIO_PUPDR_PUPDR4_1 (0x2U << GPIO_PUPDR_PUPDR4_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2180 #define GPIO_PUPDR_PUPDR5_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2181 #define GPIO_PUPDR_PUPDR5_Msk (0x3U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 2182 #define GPIO_PUPDR_PUPDR5 GPIO_PUPDR_PUPDR5_Msk
AnnaBridge 171:3a7713b1edbc 2183 #define GPIO_PUPDR_PUPDR5_0 (0x1U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2184 #define GPIO_PUPDR_PUPDR5_1 (0x2U << GPIO_PUPDR_PUPDR5_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2185 #define GPIO_PUPDR_PUPDR6_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2186 #define GPIO_PUPDR_PUPDR6_Msk (0x3U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 2187 #define GPIO_PUPDR_PUPDR6 GPIO_PUPDR_PUPDR6_Msk
AnnaBridge 171:3a7713b1edbc 2188 #define GPIO_PUPDR_PUPDR6_0 (0x1U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2189 #define GPIO_PUPDR_PUPDR6_1 (0x2U << GPIO_PUPDR_PUPDR6_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2190 #define GPIO_PUPDR_PUPDR7_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2191 #define GPIO_PUPDR_PUPDR7_Msk (0x3U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x0000C000 */
AnnaBridge 171:3a7713b1edbc 2192 #define GPIO_PUPDR_PUPDR7 GPIO_PUPDR_PUPDR7_Msk
AnnaBridge 171:3a7713b1edbc 2193 #define GPIO_PUPDR_PUPDR7_0 (0x1U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2194 #define GPIO_PUPDR_PUPDR7_1 (0x2U << GPIO_PUPDR_PUPDR7_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2195 #define GPIO_PUPDR_PUPDR8_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2196 #define GPIO_PUPDR_PUPDR8_Msk (0x3U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00030000 */
AnnaBridge 171:3a7713b1edbc 2197 #define GPIO_PUPDR_PUPDR8 GPIO_PUPDR_PUPDR8_Msk
AnnaBridge 171:3a7713b1edbc 2198 #define GPIO_PUPDR_PUPDR8_0 (0x1U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2199 #define GPIO_PUPDR_PUPDR8_1 (0x2U << GPIO_PUPDR_PUPDR8_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2200 #define GPIO_PUPDR_PUPDR9_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2201 #define GPIO_PUPDR_PUPDR9_Msk (0x3U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x000C0000 */
AnnaBridge 171:3a7713b1edbc 2202 #define GPIO_PUPDR_PUPDR9 GPIO_PUPDR_PUPDR9_Msk
AnnaBridge 171:3a7713b1edbc 2203 #define GPIO_PUPDR_PUPDR9_0 (0x1U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2204 #define GPIO_PUPDR_PUPDR9_1 (0x2U << GPIO_PUPDR_PUPDR9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2205 #define GPIO_PUPDR_PUPDR10_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2206 #define GPIO_PUPDR_PUPDR10_Msk (0x3U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 2207 #define GPIO_PUPDR_PUPDR10 GPIO_PUPDR_PUPDR10_Msk
AnnaBridge 171:3a7713b1edbc 2208 #define GPIO_PUPDR_PUPDR10_0 (0x1U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2209 #define GPIO_PUPDR_PUPDR10_1 (0x2U << GPIO_PUPDR_PUPDR10_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2210 #define GPIO_PUPDR_PUPDR11_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2211 #define GPIO_PUPDR_PUPDR11_Msk (0x3U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00C00000 */
AnnaBridge 171:3a7713b1edbc 2212 #define GPIO_PUPDR_PUPDR11 GPIO_PUPDR_PUPDR11_Msk
AnnaBridge 171:3a7713b1edbc 2213 #define GPIO_PUPDR_PUPDR11_0 (0x1U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2214 #define GPIO_PUPDR_PUPDR11_1 (0x2U << GPIO_PUPDR_PUPDR11_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2215 #define GPIO_PUPDR_PUPDR12_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2216 #define GPIO_PUPDR_PUPDR12_Msk (0x3U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x03000000 */
AnnaBridge 171:3a7713b1edbc 2217 #define GPIO_PUPDR_PUPDR12 GPIO_PUPDR_PUPDR12_Msk
AnnaBridge 171:3a7713b1edbc 2218 #define GPIO_PUPDR_PUPDR12_0 (0x1U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2219 #define GPIO_PUPDR_PUPDR12_1 (0x2U << GPIO_PUPDR_PUPDR12_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2220 #define GPIO_PUPDR_PUPDR13_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2221 #define GPIO_PUPDR_PUPDR13_Msk (0x3U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x0C000000 */
AnnaBridge 171:3a7713b1edbc 2222 #define GPIO_PUPDR_PUPDR13 GPIO_PUPDR_PUPDR13_Msk
AnnaBridge 171:3a7713b1edbc 2223 #define GPIO_PUPDR_PUPDR13_0 (0x1U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2224 #define GPIO_PUPDR_PUPDR13_1 (0x2U << GPIO_PUPDR_PUPDR13_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 2225 #define GPIO_PUPDR_PUPDR14_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2226 #define GPIO_PUPDR_PUPDR14_Msk (0x3U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 2227 #define GPIO_PUPDR_PUPDR14 GPIO_PUPDR_PUPDR14_Msk
AnnaBridge 171:3a7713b1edbc 2228 #define GPIO_PUPDR_PUPDR14_0 (0x1U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 2229 #define GPIO_PUPDR_PUPDR14_1 (0x2U << GPIO_PUPDR_PUPDR14_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 2230 #define GPIO_PUPDR_PUPDR15_Pos (30U)
AnnaBridge 171:3a7713b1edbc 2231 #define GPIO_PUPDR_PUPDR15_Msk (0x3U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0xC0000000 */
AnnaBridge 171:3a7713b1edbc 2232 #define GPIO_PUPDR_PUPDR15 GPIO_PUPDR_PUPDR15_Msk
AnnaBridge 171:3a7713b1edbc 2233 #define GPIO_PUPDR_PUPDR15_0 (0x1U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 2234 #define GPIO_PUPDR_PUPDR15_1 (0x2U << GPIO_PUPDR_PUPDR15_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2235
AnnaBridge 171:3a7713b1edbc 2236 /******************* Bit definition for GPIO_IDR register *******************/
AnnaBridge 171:3a7713b1edbc 2237 #define GPIO_IDR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 2238 #define GPIO_IDR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 2239 #define GPIO_IDR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 2240 #define GPIO_IDR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 2241 #define GPIO_IDR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 2242 #define GPIO_IDR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 2243 #define GPIO_IDR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 2244 #define GPIO_IDR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 2245 #define GPIO_IDR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 2246 #define GPIO_IDR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 2247 #define GPIO_IDR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 2248 #define GPIO_IDR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 2249 #define GPIO_IDR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 2250 #define GPIO_IDR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 2251 #define GPIO_IDR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 2252 #define GPIO_IDR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 2253
AnnaBridge 171:3a7713b1edbc 2254 /****************** Bit definition for GPIO_ODR register ********************/
AnnaBridge 171:3a7713b1edbc 2255 #define GPIO_ODR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 2256 #define GPIO_ODR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 2257 #define GPIO_ODR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 2258 #define GPIO_ODR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 2259 #define GPIO_ODR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 2260 #define GPIO_ODR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 2261 #define GPIO_ODR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 2262 #define GPIO_ODR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 2263 #define GPIO_ODR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 2264 #define GPIO_ODR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 2265 #define GPIO_ODR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 2266 #define GPIO_ODR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 2267 #define GPIO_ODR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 2268 #define GPIO_ODR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 2269 #define GPIO_ODR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 2270 #define GPIO_ODR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 2271
AnnaBridge 171:3a7713b1edbc 2272 /****************** Bit definition for GPIO_BSRR register ********************/
AnnaBridge 171:3a7713b1edbc 2273 #define GPIO_BSRR_BS_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 2274 #define GPIO_BSRR_BS_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 2275 #define GPIO_BSRR_BS_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 2276 #define GPIO_BSRR_BS_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 2277 #define GPIO_BSRR_BS_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 2278 #define GPIO_BSRR_BS_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 2279 #define GPIO_BSRR_BS_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 2280 #define GPIO_BSRR_BS_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 2281 #define GPIO_BSRR_BS_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 2282 #define GPIO_BSRR_BS_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 2283 #define GPIO_BSRR_BS_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 2284 #define GPIO_BSRR_BS_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 2285 #define GPIO_BSRR_BS_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 2286 #define GPIO_BSRR_BS_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 2287 #define GPIO_BSRR_BS_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 2288 #define GPIO_BSRR_BS_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 2289 #define GPIO_BSRR_BR_0 (0x00010000U)
AnnaBridge 171:3a7713b1edbc 2290 #define GPIO_BSRR_BR_1 (0x00020000U)
AnnaBridge 171:3a7713b1edbc 2291 #define GPIO_BSRR_BR_2 (0x00040000U)
AnnaBridge 171:3a7713b1edbc 2292 #define GPIO_BSRR_BR_3 (0x00080000U)
AnnaBridge 171:3a7713b1edbc 2293 #define GPIO_BSRR_BR_4 (0x00100000U)
AnnaBridge 171:3a7713b1edbc 2294 #define GPIO_BSRR_BR_5 (0x00200000U)
AnnaBridge 171:3a7713b1edbc 2295 #define GPIO_BSRR_BR_6 (0x00400000U)
AnnaBridge 171:3a7713b1edbc 2296 #define GPIO_BSRR_BR_7 (0x00800000U)
AnnaBridge 171:3a7713b1edbc 2297 #define GPIO_BSRR_BR_8 (0x01000000U)
AnnaBridge 171:3a7713b1edbc 2298 #define GPIO_BSRR_BR_9 (0x02000000U)
AnnaBridge 171:3a7713b1edbc 2299 #define GPIO_BSRR_BR_10 (0x04000000U)
AnnaBridge 171:3a7713b1edbc 2300 #define GPIO_BSRR_BR_11 (0x08000000U)
AnnaBridge 171:3a7713b1edbc 2301 #define GPIO_BSRR_BR_12 (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2302 #define GPIO_BSRR_BR_13 (0x20000000U)
AnnaBridge 171:3a7713b1edbc 2303 #define GPIO_BSRR_BR_14 (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2304 #define GPIO_BSRR_BR_15 (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2305
AnnaBridge 171:3a7713b1edbc 2306 /****************** Bit definition for GPIO_LCKR register ********************/
AnnaBridge 171:3a7713b1edbc 2307 #define GPIO_LCKR_LCK0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2308 #define GPIO_LCKR_LCK0_Msk (0x1U << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2309 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
AnnaBridge 171:3a7713b1edbc 2310 #define GPIO_LCKR_LCK1_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2311 #define GPIO_LCKR_LCK1_Msk (0x1U << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2312 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
AnnaBridge 171:3a7713b1edbc 2313 #define GPIO_LCKR_LCK2_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2314 #define GPIO_LCKR_LCK2_Msk (0x1U << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2315 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
AnnaBridge 171:3a7713b1edbc 2316 #define GPIO_LCKR_LCK3_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2317 #define GPIO_LCKR_LCK3_Msk (0x1U << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2318 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
AnnaBridge 171:3a7713b1edbc 2319 #define GPIO_LCKR_LCK4_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2320 #define GPIO_LCKR_LCK4_Msk (0x1U << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2321 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
AnnaBridge 171:3a7713b1edbc 2322 #define GPIO_LCKR_LCK5_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2323 #define GPIO_LCKR_LCK5_Msk (0x1U << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2324 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
AnnaBridge 171:3a7713b1edbc 2325 #define GPIO_LCKR_LCK6_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2326 #define GPIO_LCKR_LCK6_Msk (0x1U << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2327 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
AnnaBridge 171:3a7713b1edbc 2328 #define GPIO_LCKR_LCK7_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2329 #define GPIO_LCKR_LCK7_Msk (0x1U << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2330 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
AnnaBridge 171:3a7713b1edbc 2331 #define GPIO_LCKR_LCK8_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2332 #define GPIO_LCKR_LCK8_Msk (0x1U << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2333 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
AnnaBridge 171:3a7713b1edbc 2334 #define GPIO_LCKR_LCK9_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2335 #define GPIO_LCKR_LCK9_Msk (0x1U << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2336 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
AnnaBridge 171:3a7713b1edbc 2337 #define GPIO_LCKR_LCK10_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2338 #define GPIO_LCKR_LCK10_Msk (0x1U << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2339 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
AnnaBridge 171:3a7713b1edbc 2340 #define GPIO_LCKR_LCK11_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2341 #define GPIO_LCKR_LCK11_Msk (0x1U << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2342 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
AnnaBridge 171:3a7713b1edbc 2343 #define GPIO_LCKR_LCK12_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2344 #define GPIO_LCKR_LCK12_Msk (0x1U << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2345 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
AnnaBridge 171:3a7713b1edbc 2346 #define GPIO_LCKR_LCK13_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2347 #define GPIO_LCKR_LCK13_Msk (0x1U << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2348 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
AnnaBridge 171:3a7713b1edbc 2349 #define GPIO_LCKR_LCK14_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2350 #define GPIO_LCKR_LCK14_Msk (0x1U << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2351 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
AnnaBridge 171:3a7713b1edbc 2352 #define GPIO_LCKR_LCK15_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2353 #define GPIO_LCKR_LCK15_Msk (0x1U << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2354 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
AnnaBridge 171:3a7713b1edbc 2355 #define GPIO_LCKR_LCKK_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2356 #define GPIO_LCKR_LCKK_Msk (0x1U << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2357 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
AnnaBridge 171:3a7713b1edbc 2358
AnnaBridge 171:3a7713b1edbc 2359 /****************** Bit definition for GPIO_AFRL register ********************/
AnnaBridge 171:3a7713b1edbc 2360 #define GPIO_AFRL_AFSEL0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2361 #define GPIO_AFRL_AFSEL0_Msk (0xFU << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2362 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
AnnaBridge 171:3a7713b1edbc 2363 #define GPIO_AFRL_AFSEL1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2364 #define GPIO_AFRL_AFSEL1_Msk (0xFU << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 2365 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
AnnaBridge 171:3a7713b1edbc 2366 #define GPIO_AFRL_AFSEL2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2367 #define GPIO_AFRL_AFSEL2_Msk (0xFU << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 2368 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
AnnaBridge 171:3a7713b1edbc 2369 #define GPIO_AFRL_AFSEL3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2370 #define GPIO_AFRL_AFSEL3_Msk (0xFU << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 2371 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
AnnaBridge 171:3a7713b1edbc 2372 #define GPIO_AFRL_AFSEL4_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2373 #define GPIO_AFRL_AFSEL4_Msk (0xFU << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 2374 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
AnnaBridge 171:3a7713b1edbc 2375 #define GPIO_AFRL_AFSEL5_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2376 #define GPIO_AFRL_AFSEL5_Msk (0xFU << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 2377 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
AnnaBridge 171:3a7713b1edbc 2378 #define GPIO_AFRL_AFSEL6_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2379 #define GPIO_AFRL_AFSEL6_Msk (0xFU << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 2380 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
AnnaBridge 171:3a7713b1edbc 2381 #define GPIO_AFRL_AFSEL7_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2382 #define GPIO_AFRL_AFSEL7_Msk (0xFU << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 2383 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
AnnaBridge 171:3a7713b1edbc 2384
AnnaBridge 171:3a7713b1edbc 2385 /* Legacy aliases */
AnnaBridge 171:3a7713b1edbc 2386 #define GPIO_AFRL_AFRL0_Pos GPIO_AFRL_AFSEL0_Pos
AnnaBridge 171:3a7713b1edbc 2387 #define GPIO_AFRL_AFRL0_Msk GPIO_AFRL_AFSEL0_Msk
AnnaBridge 171:3a7713b1edbc 2388 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
AnnaBridge 171:3a7713b1edbc 2389 #define GPIO_AFRL_AFRL1_Pos GPIO_AFRL_AFSEL1_Pos
AnnaBridge 171:3a7713b1edbc 2390 #define GPIO_AFRL_AFRL1_Msk GPIO_AFRL_AFSEL1_Msk
AnnaBridge 171:3a7713b1edbc 2391 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
AnnaBridge 171:3a7713b1edbc 2392 #define GPIO_AFRL_AFRL2_Pos GPIO_AFRL_AFSEL2_Pos
AnnaBridge 171:3a7713b1edbc 2393 #define GPIO_AFRL_AFRL2_Msk GPIO_AFRL_AFSEL2_Msk
AnnaBridge 171:3a7713b1edbc 2394 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
AnnaBridge 171:3a7713b1edbc 2395 #define GPIO_AFRL_AFRL3_Pos GPIO_AFRL_AFSEL3_Pos
AnnaBridge 171:3a7713b1edbc 2396 #define GPIO_AFRL_AFRL3_Msk GPIO_AFRL_AFSEL3_Msk
AnnaBridge 171:3a7713b1edbc 2397 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
AnnaBridge 171:3a7713b1edbc 2398 #define GPIO_AFRL_AFRL4_Pos GPIO_AFRL_AFSEL4_Pos
AnnaBridge 171:3a7713b1edbc 2399 #define GPIO_AFRL_AFRL4_Msk GPIO_AFRL_AFSEL4_Msk
AnnaBridge 171:3a7713b1edbc 2400 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
AnnaBridge 171:3a7713b1edbc 2401 #define GPIO_AFRL_AFRL5_Pos GPIO_AFRL_AFSEL5_Pos
AnnaBridge 171:3a7713b1edbc 2402 #define GPIO_AFRL_AFRL5_Msk GPIO_AFRL_AFSEL5_Msk
AnnaBridge 171:3a7713b1edbc 2403 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
AnnaBridge 171:3a7713b1edbc 2404 #define GPIO_AFRL_AFRL6_Pos GPIO_AFRL_AFSEL6_Pos
AnnaBridge 171:3a7713b1edbc 2405 #define GPIO_AFRL_AFRL6_Msk GPIO_AFRL_AFSEL6_Msk
AnnaBridge 171:3a7713b1edbc 2406 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
AnnaBridge 171:3a7713b1edbc 2407 #define GPIO_AFRL_AFRL7_Pos GPIO_AFRL_AFSEL7_Pos
AnnaBridge 171:3a7713b1edbc 2408 #define GPIO_AFRL_AFRL7_Msk GPIO_AFRL_AFSEL7_Msk
AnnaBridge 171:3a7713b1edbc 2409 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
AnnaBridge 171:3a7713b1edbc 2410
AnnaBridge 171:3a7713b1edbc 2411 /****************** Bit definition for GPIO_AFRH register ********************/
AnnaBridge 171:3a7713b1edbc 2412 #define GPIO_AFRH_AFSEL8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2413 #define GPIO_AFRH_AFSEL8_Msk (0xFU << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 2414 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
AnnaBridge 171:3a7713b1edbc 2415 #define GPIO_AFRH_AFSEL9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2416 #define GPIO_AFRH_AFSEL9_Msk (0xFU << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 2417 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
AnnaBridge 171:3a7713b1edbc 2418 #define GPIO_AFRH_AFSEL10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2419 #define GPIO_AFRH_AFSEL10_Msk (0xFU << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 2420 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
AnnaBridge 171:3a7713b1edbc 2421 #define GPIO_AFRH_AFSEL11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2422 #define GPIO_AFRH_AFSEL11_Msk (0xFU << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 2423 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
AnnaBridge 171:3a7713b1edbc 2424 #define GPIO_AFRH_AFSEL12_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2425 #define GPIO_AFRH_AFSEL12_Msk (0xFU << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 2426 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
AnnaBridge 171:3a7713b1edbc 2427 #define GPIO_AFRH_AFSEL13_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2428 #define GPIO_AFRH_AFSEL13_Msk (0xFU << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 2429 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
AnnaBridge 171:3a7713b1edbc 2430 #define GPIO_AFRH_AFSEL14_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2431 #define GPIO_AFRH_AFSEL14_Msk (0xFU << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 2432 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
AnnaBridge 171:3a7713b1edbc 2433 #define GPIO_AFRH_AFSEL15_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2434 #define GPIO_AFRH_AFSEL15_Msk (0xFU << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 2435 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
AnnaBridge 171:3a7713b1edbc 2436
AnnaBridge 171:3a7713b1edbc 2437 /* Legacy aliases */
AnnaBridge 171:3a7713b1edbc 2438 #define GPIO_AFRH_AFRH0_Pos GPIO_AFRH_AFSEL8_Pos
AnnaBridge 171:3a7713b1edbc 2439 #define GPIO_AFRH_AFRH0_Msk GPIO_AFRH_AFSEL8_Msk
AnnaBridge 171:3a7713b1edbc 2440 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
AnnaBridge 171:3a7713b1edbc 2441 #define GPIO_AFRH_AFRH1_Pos GPIO_AFRH_AFSEL9_Pos
AnnaBridge 171:3a7713b1edbc 2442 #define GPIO_AFRH_AFRH1_Msk GPIO_AFRH_AFSEL9_Msk
AnnaBridge 171:3a7713b1edbc 2443 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
AnnaBridge 171:3a7713b1edbc 2444 #define GPIO_AFRH_AFRH2_Pos GPIO_AFRH_AFSEL10_Pos
AnnaBridge 171:3a7713b1edbc 2445 #define GPIO_AFRH_AFRH2_Msk GPIO_AFRH_AFSEL10_Msk
AnnaBridge 171:3a7713b1edbc 2446 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
AnnaBridge 171:3a7713b1edbc 2447 #define GPIO_AFRH_AFRH3_Pos GPIO_AFRH_AFSEL11_Pos
AnnaBridge 171:3a7713b1edbc 2448 #define GPIO_AFRH_AFRH3_Msk GPIO_AFRH_AFSEL11_Msk
AnnaBridge 171:3a7713b1edbc 2449 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
AnnaBridge 171:3a7713b1edbc 2450 #define GPIO_AFRH_AFRH4_Pos GPIO_AFRH_AFSEL12_Pos
AnnaBridge 171:3a7713b1edbc 2451 #define GPIO_AFRH_AFRH4_Msk GPIO_AFRH_AFSEL12_Msk
AnnaBridge 171:3a7713b1edbc 2452 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
AnnaBridge 171:3a7713b1edbc 2453 #define GPIO_AFRH_AFRH5_Pos GPIO_AFRH_AFSEL13_Pos
AnnaBridge 171:3a7713b1edbc 2454 #define GPIO_AFRH_AFRH5_Msk GPIO_AFRH_AFSEL13_Msk
AnnaBridge 171:3a7713b1edbc 2455 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
AnnaBridge 171:3a7713b1edbc 2456 #define GPIO_AFRH_AFRH6_Pos GPIO_AFRH_AFSEL14_Pos
AnnaBridge 171:3a7713b1edbc 2457 #define GPIO_AFRH_AFRH6_Msk GPIO_AFRH_AFSEL14_Msk
AnnaBridge 171:3a7713b1edbc 2458 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
AnnaBridge 171:3a7713b1edbc 2459 #define GPIO_AFRH_AFRH7_Pos GPIO_AFRH_AFSEL15_Pos
AnnaBridge 171:3a7713b1edbc 2460 #define GPIO_AFRH_AFRH7_Msk GPIO_AFRH_AFSEL15_Msk
AnnaBridge 171:3a7713b1edbc 2461 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
AnnaBridge 171:3a7713b1edbc 2462
AnnaBridge 171:3a7713b1edbc 2463 /****************** Bit definition for GPIO_BRR register *********************/
AnnaBridge 171:3a7713b1edbc 2464 #define GPIO_BRR_BR_0 (0x00000001U)
AnnaBridge 171:3a7713b1edbc 2465 #define GPIO_BRR_BR_1 (0x00000002U)
AnnaBridge 171:3a7713b1edbc 2466 #define GPIO_BRR_BR_2 (0x00000004U)
AnnaBridge 171:3a7713b1edbc 2467 #define GPIO_BRR_BR_3 (0x00000008U)
AnnaBridge 171:3a7713b1edbc 2468 #define GPIO_BRR_BR_4 (0x00000010U)
AnnaBridge 171:3a7713b1edbc 2469 #define GPIO_BRR_BR_5 (0x00000020U)
AnnaBridge 171:3a7713b1edbc 2470 #define GPIO_BRR_BR_6 (0x00000040U)
AnnaBridge 171:3a7713b1edbc 2471 #define GPIO_BRR_BR_7 (0x00000080U)
AnnaBridge 171:3a7713b1edbc 2472 #define GPIO_BRR_BR_8 (0x00000100U)
AnnaBridge 171:3a7713b1edbc 2473 #define GPIO_BRR_BR_9 (0x00000200U)
AnnaBridge 171:3a7713b1edbc 2474 #define GPIO_BRR_BR_10 (0x00000400U)
AnnaBridge 171:3a7713b1edbc 2475 #define GPIO_BRR_BR_11 (0x00000800U)
AnnaBridge 171:3a7713b1edbc 2476 #define GPIO_BRR_BR_12 (0x00001000U)
AnnaBridge 171:3a7713b1edbc 2477 #define GPIO_BRR_BR_13 (0x00002000U)
AnnaBridge 171:3a7713b1edbc 2478 #define GPIO_BRR_BR_14 (0x00004000U)
AnnaBridge 171:3a7713b1edbc 2479 #define GPIO_BRR_BR_15 (0x00008000U)
AnnaBridge 171:3a7713b1edbc 2480
AnnaBridge 171:3a7713b1edbc 2481 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2482 /* */
AnnaBridge 171:3a7713b1edbc 2483 /* Inter-integrated Circuit Interface (I2C) */
AnnaBridge 171:3a7713b1edbc 2484 /* */
AnnaBridge 171:3a7713b1edbc 2485 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 2486
AnnaBridge 171:3a7713b1edbc 2487 /******************* Bit definition for I2C_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 2488 #define I2C_CR1_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2489 #define I2C_CR1_PE_Msk (0x1U << I2C_CR1_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2490 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
AnnaBridge 171:3a7713b1edbc 2491 #define I2C_CR1_TXIE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2492 #define I2C_CR1_TXIE_Msk (0x1U << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2493 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
AnnaBridge 171:3a7713b1edbc 2494 #define I2C_CR1_RXIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2495 #define I2C_CR1_RXIE_Msk (0x1U << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2496 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
AnnaBridge 171:3a7713b1edbc 2497 #define I2C_CR1_ADDRIE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2498 #define I2C_CR1_ADDRIE_Msk (0x1U << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2499 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
AnnaBridge 171:3a7713b1edbc 2500 #define I2C_CR1_NACKIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2501 #define I2C_CR1_NACKIE_Msk (0x1U << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2502 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
AnnaBridge 171:3a7713b1edbc 2503 #define I2C_CR1_STOPIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2504 #define I2C_CR1_STOPIE_Msk (0x1U << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2505 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
AnnaBridge 171:3a7713b1edbc 2506 #define I2C_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2507 #define I2C_CR1_TCIE_Msk (0x1U << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2508 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
AnnaBridge 171:3a7713b1edbc 2509 #define I2C_CR1_ERRIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2510 #define I2C_CR1_ERRIE_Msk (0x1U << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2511 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
AnnaBridge 171:3a7713b1edbc 2512 #define I2C_CR1_DNF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2513 #define I2C_CR1_DNF_Msk (0xFU << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 2514 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
AnnaBridge 171:3a7713b1edbc 2515 #define I2C_CR1_ANFOFF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2516 #define I2C_CR1_ANFOFF_Msk (0x1U << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2517 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
AnnaBridge 171:3a7713b1edbc 2518 #define I2C_CR1_SWRST_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2519 #define I2C_CR1_SWRST_Msk (0x1U << I2C_CR1_SWRST_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2520 #define I2C_CR1_SWRST I2C_CR1_SWRST_Msk /*!< Software reset */
AnnaBridge 171:3a7713b1edbc 2521 #define I2C_CR1_TXDMAEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2522 #define I2C_CR1_TXDMAEN_Msk (0x1U << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2523 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
AnnaBridge 171:3a7713b1edbc 2524 #define I2C_CR1_RXDMAEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2525 #define I2C_CR1_RXDMAEN_Msk (0x1U << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2526 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
AnnaBridge 171:3a7713b1edbc 2527 #define I2C_CR1_SBC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2528 #define I2C_CR1_SBC_Msk (0x1U << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2529 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
AnnaBridge 171:3a7713b1edbc 2530 #define I2C_CR1_NOSTRETCH_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2531 #define I2C_CR1_NOSTRETCH_Msk (0x1U << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2532 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
AnnaBridge 171:3a7713b1edbc 2533 #define I2C_CR1_WUPEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2534 #define I2C_CR1_WUPEN_Msk (0x1U << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2535 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
AnnaBridge 171:3a7713b1edbc 2536 #define I2C_CR1_GCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2537 #define I2C_CR1_GCEN_Msk (0x1U << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2538 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
AnnaBridge 171:3a7713b1edbc 2539 #define I2C_CR1_SMBHEN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2540 #define I2C_CR1_SMBHEN_Msk (0x1U << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 2541 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
AnnaBridge 171:3a7713b1edbc 2542 #define I2C_CR1_SMBDEN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 2543 #define I2C_CR1_SMBDEN_Msk (0x1U << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 2544 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
AnnaBridge 171:3a7713b1edbc 2545 #define I2C_CR1_ALERTEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 2546 #define I2C_CR1_ALERTEN_Msk (0x1U << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 2547 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
AnnaBridge 171:3a7713b1edbc 2548 #define I2C_CR1_PECEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 2549 #define I2C_CR1_PECEN_Msk (0x1U << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 2550 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
AnnaBridge 171:3a7713b1edbc 2551
AnnaBridge 171:3a7713b1edbc 2552 /****************** Bit definition for I2C_CR2 register ********************/
AnnaBridge 171:3a7713b1edbc 2553 #define I2C_CR2_SADD_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2554 #define I2C_CR2_SADD_Msk (0x3FFU << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 2555 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
AnnaBridge 171:3a7713b1edbc 2556 #define I2C_CR2_RD_WRN_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2557 #define I2C_CR2_RD_WRN_Msk (0x1U << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2558 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
AnnaBridge 171:3a7713b1edbc 2559 #define I2C_CR2_ADD10_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2560 #define I2C_CR2_ADD10_Msk (0x1U << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2561 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
AnnaBridge 171:3a7713b1edbc 2562 #define I2C_CR2_HEAD10R_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2563 #define I2C_CR2_HEAD10R_Msk (0x1U << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2564 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
AnnaBridge 171:3a7713b1edbc 2565 #define I2C_CR2_START_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2566 #define I2C_CR2_START_Msk (0x1U << I2C_CR2_START_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2567 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
AnnaBridge 171:3a7713b1edbc 2568 #define I2C_CR2_STOP_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2569 #define I2C_CR2_STOP_Msk (0x1U << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2570 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
AnnaBridge 171:3a7713b1edbc 2571 #define I2C_CR2_NACK_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2572 #define I2C_CR2_NACK_Msk (0x1U << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2573 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
AnnaBridge 171:3a7713b1edbc 2574 #define I2C_CR2_NBYTES_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2575 #define I2C_CR2_NBYTES_Msk (0xFFU << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
AnnaBridge 171:3a7713b1edbc 2576 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
AnnaBridge 171:3a7713b1edbc 2577 #define I2C_CR2_RELOAD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2578 #define I2C_CR2_RELOAD_Msk (0x1U << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2579 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
AnnaBridge 171:3a7713b1edbc 2580 #define I2C_CR2_AUTOEND_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2581 #define I2C_CR2_AUTOEND_Msk (0x1U << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2582 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
AnnaBridge 171:3a7713b1edbc 2583 #define I2C_CR2_PECBYTE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 2584 #define I2C_CR2_PECBYTE_Msk (0x1U << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 2585 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
AnnaBridge 171:3a7713b1edbc 2586
AnnaBridge 171:3a7713b1edbc 2587 /******************* Bit definition for I2C_OAR1 register ******************/
AnnaBridge 171:3a7713b1edbc 2588 #define I2C_OAR1_OA1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2589 #define I2C_OAR1_OA1_Msk (0x3FFU << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
AnnaBridge 171:3a7713b1edbc 2590 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
AnnaBridge 171:3a7713b1edbc 2591 #define I2C_OAR1_OA1MODE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2592 #define I2C_OAR1_OA1MODE_Msk (0x1U << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2593 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
AnnaBridge 171:3a7713b1edbc 2594 #define I2C_OAR1_OA1EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2595 #define I2C_OAR1_OA1EN_Msk (0x1U << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2596 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
AnnaBridge 171:3a7713b1edbc 2597
AnnaBridge 171:3a7713b1edbc 2598 /******************* Bit definition for I2C_OAR2 register ******************/
AnnaBridge 171:3a7713b1edbc 2599 #define I2C_OAR2_OA2_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2600 #define I2C_OAR2_OA2_Msk (0x7FU << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
AnnaBridge 171:3a7713b1edbc 2601 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
AnnaBridge 171:3a7713b1edbc 2602 #define I2C_OAR2_OA2MSK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2603 #define I2C_OAR2_OA2MSK_Msk (0x7U << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 2604 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
AnnaBridge 171:3a7713b1edbc 2605 #define I2C_OAR2_OA2NOMASK (0x00000000U) /*!< No mask */
AnnaBridge 171:3a7713b1edbc 2606 #define I2C_OAR2_OA2MASK01_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2607 #define I2C_OAR2_OA2MASK01_Msk (0x1U << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2608 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
AnnaBridge 171:3a7713b1edbc 2609 #define I2C_OAR2_OA2MASK02_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2610 #define I2C_OAR2_OA2MASK02_Msk (0x1U << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2611 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
AnnaBridge 171:3a7713b1edbc 2612 #define I2C_OAR2_OA2MASK03_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2613 #define I2C_OAR2_OA2MASK03_Msk (0x3U << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 2614 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
AnnaBridge 171:3a7713b1edbc 2615 #define I2C_OAR2_OA2MASK04_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2616 #define I2C_OAR2_OA2MASK04_Msk (0x1U << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2617 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
AnnaBridge 171:3a7713b1edbc 2618 #define I2C_OAR2_OA2MASK05_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2619 #define I2C_OAR2_OA2MASK05_Msk (0x5U << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
AnnaBridge 171:3a7713b1edbc 2620 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
AnnaBridge 171:3a7713b1edbc 2621 #define I2C_OAR2_OA2MASK06_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2622 #define I2C_OAR2_OA2MASK06_Msk (0x3U << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 2623 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
AnnaBridge 171:3a7713b1edbc 2624 #define I2C_OAR2_OA2MASK07_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2625 #define I2C_OAR2_OA2MASK07_Msk (0x7U << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 2626 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
AnnaBridge 171:3a7713b1edbc 2627 #define I2C_OAR2_OA2EN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2628 #define I2C_OAR2_OA2EN_Msk (0x1U << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2629 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
AnnaBridge 171:3a7713b1edbc 2630
AnnaBridge 171:3a7713b1edbc 2631 /******************* Bit definition for I2C_TIMINGR register ****************/
AnnaBridge 171:3a7713b1edbc 2632 #define I2C_TIMINGR_SCLL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2633 #define I2C_TIMINGR_SCLL_Msk (0xFFU << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2634 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
AnnaBridge 171:3a7713b1edbc 2635 #define I2C_TIMINGR_SCLH_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2636 #define I2C_TIMINGR_SCLH_Msk (0xFFU << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2637 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
AnnaBridge 171:3a7713b1edbc 2638 #define I2C_TIMINGR_SDADEL_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2639 #define I2C_TIMINGR_SDADEL_Msk (0xFU << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 2640 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
AnnaBridge 171:3a7713b1edbc 2641 #define I2C_TIMINGR_SCLDEL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 2642 #define I2C_TIMINGR_SCLDEL_Msk (0xFU << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 2643 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
AnnaBridge 171:3a7713b1edbc 2644 #define I2C_TIMINGR_PRESC_Pos (28U)
AnnaBridge 171:3a7713b1edbc 2645 #define I2C_TIMINGR_PRESC_Msk (0xFU << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
AnnaBridge 171:3a7713b1edbc 2646 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
AnnaBridge 171:3a7713b1edbc 2647
AnnaBridge 171:3a7713b1edbc 2648 /******************* Bit definition for I2C_TIMEOUTR register ****************/
AnnaBridge 171:3a7713b1edbc 2649 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2650 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 2651 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
AnnaBridge 171:3a7713b1edbc 2652 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2653 #define I2C_TIMEOUTR_TIDLE_Msk (0x1U << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2654 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
AnnaBridge 171:3a7713b1edbc 2655 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2656 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1U << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2657 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
AnnaBridge 171:3a7713b1edbc 2658 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2659 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFU << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
AnnaBridge 171:3a7713b1edbc 2660 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
AnnaBridge 171:3a7713b1edbc 2661 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
AnnaBridge 171:3a7713b1edbc 2662 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1U << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 2663 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
AnnaBridge 171:3a7713b1edbc 2664
AnnaBridge 171:3a7713b1edbc 2665 /****************** Bit definition for I2C_ISR register ********************/
AnnaBridge 171:3a7713b1edbc 2666 #define I2C_ISR_TXE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2667 #define I2C_ISR_TXE_Msk (0x1U << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2668 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
AnnaBridge 171:3a7713b1edbc 2669 #define I2C_ISR_TXIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2670 #define I2C_ISR_TXIS_Msk (0x1U << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2671 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
AnnaBridge 171:3a7713b1edbc 2672 #define I2C_ISR_RXNE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2673 #define I2C_ISR_RXNE_Msk (0x1U << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2674 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
AnnaBridge 171:3a7713b1edbc 2675 #define I2C_ISR_ADDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2676 #define I2C_ISR_ADDR_Msk (0x1U << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2677 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
AnnaBridge 171:3a7713b1edbc 2678 #define I2C_ISR_NACKF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2679 #define I2C_ISR_NACKF_Msk (0x1U << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2680 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
AnnaBridge 171:3a7713b1edbc 2681 #define I2C_ISR_STOPF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2682 #define I2C_ISR_STOPF_Msk (0x1U << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2683 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
AnnaBridge 171:3a7713b1edbc 2684 #define I2C_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 2685 #define I2C_ISR_TC_Msk (0x1U << I2C_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2686 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
AnnaBridge 171:3a7713b1edbc 2687 #define I2C_ISR_TCR_Pos (7U)
AnnaBridge 171:3a7713b1edbc 2688 #define I2C_ISR_TCR_Msk (0x1U << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2689 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
AnnaBridge 171:3a7713b1edbc 2690 #define I2C_ISR_BERR_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2691 #define I2C_ISR_BERR_Msk (0x1U << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2692 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
AnnaBridge 171:3a7713b1edbc 2693 #define I2C_ISR_ARLO_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2694 #define I2C_ISR_ARLO_Msk (0x1U << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2695 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
AnnaBridge 171:3a7713b1edbc 2696 #define I2C_ISR_OVR_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2697 #define I2C_ISR_OVR_Msk (0x1U << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2698 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
AnnaBridge 171:3a7713b1edbc 2699 #define I2C_ISR_PECERR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2700 #define I2C_ISR_PECERR_Msk (0x1U << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2701 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
AnnaBridge 171:3a7713b1edbc 2702 #define I2C_ISR_TIMEOUT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2703 #define I2C_ISR_TIMEOUT_Msk (0x1U << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2704 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
AnnaBridge 171:3a7713b1edbc 2705 #define I2C_ISR_ALERT_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2706 #define I2C_ISR_ALERT_Msk (0x1U << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2707 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
AnnaBridge 171:3a7713b1edbc 2708 #define I2C_ISR_BUSY_Pos (15U)
AnnaBridge 171:3a7713b1edbc 2709 #define I2C_ISR_BUSY_Msk (0x1U << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2710 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
AnnaBridge 171:3a7713b1edbc 2711 #define I2C_ISR_DIR_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2712 #define I2C_ISR_DIR_Msk (0x1U << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2713 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
AnnaBridge 171:3a7713b1edbc 2714 #define I2C_ISR_ADDCODE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2715 #define I2C_ISR_ADDCODE_Msk (0x7FU << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
AnnaBridge 171:3a7713b1edbc 2716 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
AnnaBridge 171:3a7713b1edbc 2717
AnnaBridge 171:3a7713b1edbc 2718 /****************** Bit definition for I2C_ICR register ********************/
AnnaBridge 171:3a7713b1edbc 2719 #define I2C_ICR_ADDRCF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2720 #define I2C_ICR_ADDRCF_Msk (0x1U << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2721 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
AnnaBridge 171:3a7713b1edbc 2722 #define I2C_ICR_NACKCF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2723 #define I2C_ICR_NACKCF_Msk (0x1U << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2724 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
AnnaBridge 171:3a7713b1edbc 2725 #define I2C_ICR_STOPCF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2726 #define I2C_ICR_STOPCF_Msk (0x1U << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2727 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
AnnaBridge 171:3a7713b1edbc 2728 #define I2C_ICR_BERRCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2729 #define I2C_ICR_BERRCF_Msk (0x1U << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2730 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
AnnaBridge 171:3a7713b1edbc 2731 #define I2C_ICR_ARLOCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2732 #define I2C_ICR_ARLOCF_Msk (0x1U << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2733 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
AnnaBridge 171:3a7713b1edbc 2734 #define I2C_ICR_OVRCF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2735 #define I2C_ICR_OVRCF_Msk (0x1U << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2736 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
AnnaBridge 171:3a7713b1edbc 2737 #define I2C_ICR_PECCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 2738 #define I2C_ICR_PECCF_Msk (0x1U << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2739 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
AnnaBridge 171:3a7713b1edbc 2740 #define I2C_ICR_TIMOUTCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 2741 #define I2C_ICR_TIMOUTCF_Msk (0x1U << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2742 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
AnnaBridge 171:3a7713b1edbc 2743 #define I2C_ICR_ALERTCF_Pos (13U)
AnnaBridge 171:3a7713b1edbc 2744 #define I2C_ICR_ALERTCF_Msk (0x1U << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2745 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
AnnaBridge 171:3a7713b1edbc 2746
AnnaBridge 171:3a7713b1edbc 2747 /****************** Bit definition for I2C_PECR register *******************/
AnnaBridge 171:3a7713b1edbc 2748 #define I2C_PECR_PEC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2749 #define I2C_PECR_PEC_Msk (0xFFU << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2750 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
AnnaBridge 171:3a7713b1edbc 2751
AnnaBridge 171:3a7713b1edbc 2752 /****************** Bit definition for I2C_RXDR register *********************/
AnnaBridge 171:3a7713b1edbc 2753 #define I2C_RXDR_RXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2754 #define I2C_RXDR_RXDATA_Msk (0xFFU << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2755 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
AnnaBridge 171:3a7713b1edbc 2756
AnnaBridge 171:3a7713b1edbc 2757 /****************** Bit definition for I2C_TXDR register *******************/
AnnaBridge 171:3a7713b1edbc 2758 #define I2C_TXDR_TXDATA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2759 #define I2C_TXDR_TXDATA_Msk (0xFFU << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 2760 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
AnnaBridge 171:3a7713b1edbc 2761
AnnaBridge 171:3a7713b1edbc 2762 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2763 /* */
AnnaBridge 171:3a7713b1edbc 2764 /* Independent WATCHDOG (IWDG) */
AnnaBridge 171:3a7713b1edbc 2765 /* */
AnnaBridge 171:3a7713b1edbc 2766 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2767 /******************* Bit definition for IWDG_KR register *******************/
AnnaBridge 171:3a7713b1edbc 2768 #define IWDG_KR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2769 #define IWDG_KR_KEY_Msk (0xFFFFU << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 2770 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!< Key value (write only, read 0000h) */
AnnaBridge 171:3a7713b1edbc 2771
AnnaBridge 171:3a7713b1edbc 2772 /******************* Bit definition for IWDG_PR register *******************/
AnnaBridge 171:3a7713b1edbc 2773 #define IWDG_PR_PR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2774 #define IWDG_PR_PR_Msk (0x7U << IWDG_PR_PR_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 2775 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!< PR[2:0] (Prescaler divider) */
AnnaBridge 171:3a7713b1edbc 2776 #define IWDG_PR_PR_0 (0x1U << IWDG_PR_PR_Pos) /*!< 0x01 */
AnnaBridge 171:3a7713b1edbc 2777 #define IWDG_PR_PR_1 (0x2U << IWDG_PR_PR_Pos) /*!< 0x02 */
AnnaBridge 171:3a7713b1edbc 2778 #define IWDG_PR_PR_2 (0x4U << IWDG_PR_PR_Pos) /*!< 0x04 */
AnnaBridge 171:3a7713b1edbc 2779
AnnaBridge 171:3a7713b1edbc 2780 /******************* Bit definition for IWDG_RLR register ******************/
AnnaBridge 171:3a7713b1edbc 2781 #define IWDG_RLR_RL_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2782 #define IWDG_RLR_RL_Msk (0xFFFU << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 2783 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!< Watchdog counter reload value */
AnnaBridge 171:3a7713b1edbc 2784
AnnaBridge 171:3a7713b1edbc 2785 /******************* Bit definition for IWDG_SR register *******************/
AnnaBridge 171:3a7713b1edbc 2786 #define IWDG_SR_PVU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2787 #define IWDG_SR_PVU_Msk (0x1U << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2788 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
AnnaBridge 171:3a7713b1edbc 2789 #define IWDG_SR_RVU_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2790 #define IWDG_SR_RVU_Msk (0x1U << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2791 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
AnnaBridge 171:3a7713b1edbc 2792 #define IWDG_SR_WVU_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2793 #define IWDG_SR_WVU_Msk (0x1U << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2794 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
AnnaBridge 171:3a7713b1edbc 2795
AnnaBridge 171:3a7713b1edbc 2796 /******************* Bit definition for IWDG_KR register *******************/
AnnaBridge 171:3a7713b1edbc 2797 #define IWDG_WINR_WIN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2798 #define IWDG_WINR_WIN_Msk (0xFFFU << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
AnnaBridge 171:3a7713b1edbc 2799 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
AnnaBridge 171:3a7713b1edbc 2800
AnnaBridge 171:3a7713b1edbc 2801 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2802 /* */
AnnaBridge 171:3a7713b1edbc 2803 /* Power Control (PWR) */
AnnaBridge 171:3a7713b1edbc 2804 /* */
AnnaBridge 171:3a7713b1edbc 2805 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2806
AnnaBridge 171:3a7713b1edbc 2807 #define PWR_PVD_SUPPORT /*!< PWR feature available only on specific devices: Power Voltage Detection feature */
AnnaBridge 171:3a7713b1edbc 2808
AnnaBridge 171:3a7713b1edbc 2809
AnnaBridge 171:3a7713b1edbc 2810 /******************** Bit definition for PWR_CR register *******************/
AnnaBridge 171:3a7713b1edbc 2811 #define PWR_CR_LPDS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2812 #define PWR_CR_LPDS_Msk (0x1U << PWR_CR_LPDS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2813 #define PWR_CR_LPDS PWR_CR_LPDS_Msk /*!< Low-power Deepsleep */
AnnaBridge 171:3a7713b1edbc 2814 #define PWR_CR_PDDS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2815 #define PWR_CR_PDDS_Msk (0x1U << PWR_CR_PDDS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2816 #define PWR_CR_PDDS PWR_CR_PDDS_Msk /*!< Power Down Deepsleep */
AnnaBridge 171:3a7713b1edbc 2817 #define PWR_CR_CWUF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2818 #define PWR_CR_CWUF_Msk (0x1U << PWR_CR_CWUF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2819 #define PWR_CR_CWUF PWR_CR_CWUF_Msk /*!< Clear Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 2820 #define PWR_CR_CSBF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2821 #define PWR_CR_CSBF_Msk (0x1U << PWR_CR_CSBF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2822 #define PWR_CR_CSBF PWR_CR_CSBF_Msk /*!< Clear Standby Flag */
AnnaBridge 171:3a7713b1edbc 2823 #define PWR_CR_PVDE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2824 #define PWR_CR_PVDE_Msk (0x1U << PWR_CR_PVDE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2825 #define PWR_CR_PVDE PWR_CR_PVDE_Msk /*!< Power Voltage Detector Enable */
AnnaBridge 171:3a7713b1edbc 2826
AnnaBridge 171:3a7713b1edbc 2827 #define PWR_CR_PLS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 2828 #define PWR_CR_PLS_Msk (0x7U << PWR_CR_PLS_Pos) /*!< 0x000000E0 */
AnnaBridge 171:3a7713b1edbc 2829 #define PWR_CR_PLS PWR_CR_PLS_Msk /*!< PLS[2:0] bits (PVD Level Selection) */
AnnaBridge 171:3a7713b1edbc 2830 #define PWR_CR_PLS_0 (0x1U << PWR_CR_PLS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2831 #define PWR_CR_PLS_1 (0x2U << PWR_CR_PLS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2832 #define PWR_CR_PLS_2 (0x4U << PWR_CR_PLS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2833
AnnaBridge 171:3a7713b1edbc 2834 /*!< PVD level configuration */
AnnaBridge 171:3a7713b1edbc 2835 #define PWR_CR_PLS_LEV0 (0x00000000U) /*!< PVD level 0 */
AnnaBridge 171:3a7713b1edbc 2836 #define PWR_CR_PLS_LEV1 (0x00000020U) /*!< PVD level 1 */
AnnaBridge 171:3a7713b1edbc 2837 #define PWR_CR_PLS_LEV2 (0x00000040U) /*!< PVD level 2 */
AnnaBridge 171:3a7713b1edbc 2838 #define PWR_CR_PLS_LEV3 (0x00000060U) /*!< PVD level 3 */
AnnaBridge 171:3a7713b1edbc 2839 #define PWR_CR_PLS_LEV4 (0x00000080U) /*!< PVD level 4 */
AnnaBridge 171:3a7713b1edbc 2840 #define PWR_CR_PLS_LEV5 (0x000000A0U) /*!< PVD level 5 */
AnnaBridge 171:3a7713b1edbc 2841 #define PWR_CR_PLS_LEV6 (0x000000C0U) /*!< PVD level 6 */
AnnaBridge 171:3a7713b1edbc 2842 #define PWR_CR_PLS_LEV7 (0x000000E0U) /*!< PVD level 7 */
AnnaBridge 171:3a7713b1edbc 2843
AnnaBridge 171:3a7713b1edbc 2844 #define PWR_CR_DBP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2845 #define PWR_CR_DBP_Msk (0x1U << PWR_CR_DBP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2846 #define PWR_CR_DBP PWR_CR_DBP_Msk /*!< Disable Backup Domain write protection */
AnnaBridge 171:3a7713b1edbc 2847
AnnaBridge 171:3a7713b1edbc 2848 /******************* Bit definition for PWR_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 2849 #define PWR_CSR_WUF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2850 #define PWR_CSR_WUF_Msk (0x1U << PWR_CSR_WUF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2851 #define PWR_CSR_WUF PWR_CSR_WUF_Msk /*!< Wakeup Flag */
AnnaBridge 171:3a7713b1edbc 2852 #define PWR_CSR_SBF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2853 #define PWR_CSR_SBF_Msk (0x1U << PWR_CSR_SBF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2854 #define PWR_CSR_SBF PWR_CSR_SBF_Msk /*!< Standby Flag */
AnnaBridge 171:3a7713b1edbc 2855 #define PWR_CSR_PVDO_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2856 #define PWR_CSR_PVDO_Msk (0x1U << PWR_CSR_PVDO_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2857 #define PWR_CSR_PVDO PWR_CSR_PVDO_Msk /*!< PVD Output */
AnnaBridge 171:3a7713b1edbc 2858 #define PWR_CSR_VREFINTRDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2859 #define PWR_CSR_VREFINTRDYF_Msk (0x1U << PWR_CSR_VREFINTRDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2860 #define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDYF_Msk /*!< Internal voltage reference (VREFINT) ready flag */
AnnaBridge 171:3a7713b1edbc 2861
AnnaBridge 171:3a7713b1edbc 2862 #define PWR_CSR_EWUP1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2863 #define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2864 #define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */
AnnaBridge 171:3a7713b1edbc 2865 #define PWR_CSR_EWUP2_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2866 #define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2867 #define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */
AnnaBridge 171:3a7713b1edbc 2868
AnnaBridge 171:3a7713b1edbc 2869 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2870 /* */
AnnaBridge 171:3a7713b1edbc 2871 /* Reset and Clock Control */
AnnaBridge 171:3a7713b1edbc 2872 /* */
AnnaBridge 171:3a7713b1edbc 2873 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2874 /*
AnnaBridge 171:3a7713b1edbc 2875 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 2876 */
AnnaBridge 171:3a7713b1edbc 2877
AnnaBridge 171:3a7713b1edbc 2878 /******************** Bit definition for RCC_CR register *******************/
AnnaBridge 171:3a7713b1edbc 2879 #define RCC_CR_HSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2880 #define RCC_CR_HSION_Msk (0x1U << RCC_CR_HSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2881 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
AnnaBridge 171:3a7713b1edbc 2882 #define RCC_CR_HSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 2883 #define RCC_CR_HSIRDY_Msk (0x1U << RCC_CR_HSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2884 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 2885
AnnaBridge 171:3a7713b1edbc 2886 #define RCC_CR_HSITRIM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 2887 #define RCC_CR_HSITRIM_Msk (0x1FU << RCC_CR_HSITRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 171:3a7713b1edbc 2888 #define RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk /*!< Internal High Speed clock trimming */
AnnaBridge 171:3a7713b1edbc 2889 #define RCC_CR_HSITRIM_0 (0x01U << RCC_CR_HSITRIM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2890 #define RCC_CR_HSITRIM_1 (0x02U << RCC_CR_HSITRIM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2891 #define RCC_CR_HSITRIM_2 (0x04U << RCC_CR_HSITRIM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2892 #define RCC_CR_HSITRIM_3 (0x08U << RCC_CR_HSITRIM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2893 #define RCC_CR_HSITRIM_4 (0x10U << RCC_CR_HSITRIM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2894
AnnaBridge 171:3a7713b1edbc 2895 #define RCC_CR_HSICAL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2896 #define RCC_CR_HSICAL_Msk (0xFFU << RCC_CR_HSICAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 2897 #define RCC_CR_HSICAL RCC_CR_HSICAL_Msk /*!< Internal High Speed clock Calibration */
AnnaBridge 171:3a7713b1edbc 2898 #define RCC_CR_HSICAL_0 (0x01U << RCC_CR_HSICAL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2899 #define RCC_CR_HSICAL_1 (0x02U << RCC_CR_HSICAL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2900 #define RCC_CR_HSICAL_2 (0x04U << RCC_CR_HSICAL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2901 #define RCC_CR_HSICAL_3 (0x08U << RCC_CR_HSICAL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 2902 #define RCC_CR_HSICAL_4 (0x10U << RCC_CR_HSICAL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 2903 #define RCC_CR_HSICAL_5 (0x20U << RCC_CR_HSICAL_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 2904 #define RCC_CR_HSICAL_6 (0x40U << RCC_CR_HSICAL_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2905 #define RCC_CR_HSICAL_7 (0x80U << RCC_CR_HSICAL_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 2906
AnnaBridge 171:3a7713b1edbc 2907 #define RCC_CR_HSEON_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2908 #define RCC_CR_HSEON_Msk (0x1U << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 2909 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
AnnaBridge 171:3a7713b1edbc 2910 #define RCC_CR_HSERDY_Pos (17U)
AnnaBridge 171:3a7713b1edbc 2911 #define RCC_CR_HSERDY_Msk (0x1U << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 2912 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready flag */
AnnaBridge 171:3a7713b1edbc 2913 #define RCC_CR_HSEBYP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 2914 #define RCC_CR_HSEBYP_Msk (0x1U << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 2915 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
AnnaBridge 171:3a7713b1edbc 2916 #define RCC_CR_CSSON_Pos (19U)
AnnaBridge 171:3a7713b1edbc 2917 #define RCC_CR_CSSON_Msk (0x1U << RCC_CR_CSSON_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 2918 #define RCC_CR_CSSON RCC_CR_CSSON_Msk /*!< Clock Security System enable */
AnnaBridge 171:3a7713b1edbc 2919 #define RCC_CR_PLLON_Pos (24U)
AnnaBridge 171:3a7713b1edbc 2920 #define RCC_CR_PLLON_Msk (0x1U << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 2921 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< PLL enable */
AnnaBridge 171:3a7713b1edbc 2922 #define RCC_CR_PLLRDY_Pos (25U)
AnnaBridge 171:3a7713b1edbc 2923 #define RCC_CR_PLLRDY_Msk (0x1U << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 2924 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< PLL clock ready flag */
AnnaBridge 171:3a7713b1edbc 2925
AnnaBridge 171:3a7713b1edbc 2926 /******************** Bit definition for RCC_CFGR register *****************/
AnnaBridge 171:3a7713b1edbc 2927 /*!< SW configuration */
AnnaBridge 171:3a7713b1edbc 2928 #define RCC_CFGR_SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 2929 #define RCC_CFGR_SW_Msk (0x3U << RCC_CFGR_SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 2930 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[1:0] bits (System clock Switch) */
AnnaBridge 171:3a7713b1edbc 2931 #define RCC_CFGR_SW_0 (0x1U << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 2932 #define RCC_CFGR_SW_1 (0x2U << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 2933
AnnaBridge 171:3a7713b1edbc 2934 #define RCC_CFGR_SW_HSI (0x00000000U) /*!< HSI selected as system clock */
AnnaBridge 171:3a7713b1edbc 2935 #define RCC_CFGR_SW_HSE (0x00000001U) /*!< HSE selected as system clock */
AnnaBridge 171:3a7713b1edbc 2936 #define RCC_CFGR_SW_PLL (0x00000002U) /*!< PLL selected as system clock */
AnnaBridge 171:3a7713b1edbc 2937
AnnaBridge 171:3a7713b1edbc 2938 /*!< SWS configuration */
AnnaBridge 171:3a7713b1edbc 2939 #define RCC_CFGR_SWS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 2940 #define RCC_CFGR_SWS_Msk (0x3U << RCC_CFGR_SWS_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 2941 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[1:0] bits (System Clock Switch Status) */
AnnaBridge 171:3a7713b1edbc 2942 #define RCC_CFGR_SWS_0 (0x1U << RCC_CFGR_SWS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 2943 #define RCC_CFGR_SWS_1 (0x2U << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 2944
AnnaBridge 171:3a7713b1edbc 2945 #define RCC_CFGR_SWS_HSI (0x00000000U) /*!< HSI oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 2946 #define RCC_CFGR_SWS_HSE (0x00000004U) /*!< HSE oscillator used as system clock */
AnnaBridge 171:3a7713b1edbc 2947 #define RCC_CFGR_SWS_PLL (0x00000008U) /*!< PLL used as system clock */
AnnaBridge 171:3a7713b1edbc 2948
AnnaBridge 171:3a7713b1edbc 2949 /*!< HPRE configuration */
AnnaBridge 171:3a7713b1edbc 2950 #define RCC_CFGR_HPRE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 2951 #define RCC_CFGR_HPRE_Msk (0xFU << RCC_CFGR_HPRE_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 2952 #define RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB prescaler) */
AnnaBridge 171:3a7713b1edbc 2953 #define RCC_CFGR_HPRE_0 (0x1U << RCC_CFGR_HPRE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 2954 #define RCC_CFGR_HPRE_1 (0x2U << RCC_CFGR_HPRE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 2955 #define RCC_CFGR_HPRE_2 (0x4U << RCC_CFGR_HPRE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 2956 #define RCC_CFGR_HPRE_3 (0x8U << RCC_CFGR_HPRE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 2957
AnnaBridge 171:3a7713b1edbc 2958 #define RCC_CFGR_HPRE_DIV1 (0x00000000U) /*!< SYSCLK not divided */
AnnaBridge 171:3a7713b1edbc 2959 #define RCC_CFGR_HPRE_DIV2 (0x00000080U) /*!< SYSCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 2960 #define RCC_CFGR_HPRE_DIV4 (0x00000090U) /*!< SYSCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 2961 #define RCC_CFGR_HPRE_DIV8 (0x000000A0U) /*!< SYSCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 2962 #define RCC_CFGR_HPRE_DIV16 (0x000000B0U) /*!< SYSCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 2963 #define RCC_CFGR_HPRE_DIV64 (0x000000C0U) /*!< SYSCLK divided by 64 */
AnnaBridge 171:3a7713b1edbc 2964 #define RCC_CFGR_HPRE_DIV128 (0x000000D0U) /*!< SYSCLK divided by 128 */
AnnaBridge 171:3a7713b1edbc 2965 #define RCC_CFGR_HPRE_DIV256 (0x000000E0U) /*!< SYSCLK divided by 256 */
AnnaBridge 171:3a7713b1edbc 2966 #define RCC_CFGR_HPRE_DIV512 (0x000000F0U) /*!< SYSCLK divided by 512 */
AnnaBridge 171:3a7713b1edbc 2967
AnnaBridge 171:3a7713b1edbc 2968 /*!< PPRE configuration */
AnnaBridge 171:3a7713b1edbc 2969 #define RCC_CFGR_PPRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2970 #define RCC_CFGR_PPRE_Msk (0x7U << RCC_CFGR_PPRE_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 2971 #define RCC_CFGR_PPRE RCC_CFGR_PPRE_Msk /*!< PRE[2:0] bits (APB prescaler) */
AnnaBridge 171:3a7713b1edbc 2972 #define RCC_CFGR_PPRE_0 (0x1U << RCC_CFGR_PPRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 2973 #define RCC_CFGR_PPRE_1 (0x2U << RCC_CFGR_PPRE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 2974 #define RCC_CFGR_PPRE_2 (0x4U << RCC_CFGR_PPRE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2975
AnnaBridge 171:3a7713b1edbc 2976 #define RCC_CFGR_PPRE_DIV1 (0x00000000U) /*!< HCLK not divided */
AnnaBridge 171:3a7713b1edbc 2977 #define RCC_CFGR_PPRE_DIV2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 2978 #define RCC_CFGR_PPRE_DIV2_Msk (0x1U << RCC_CFGR_PPRE_DIV2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 2979 #define RCC_CFGR_PPRE_DIV2 RCC_CFGR_PPRE_DIV2_Msk /*!< HCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 2980 #define RCC_CFGR_PPRE_DIV4_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2981 #define RCC_CFGR_PPRE_DIV4_Msk (0x5U << RCC_CFGR_PPRE_DIV4_Pos) /*!< 0x00000500 */
AnnaBridge 171:3a7713b1edbc 2982 #define RCC_CFGR_PPRE_DIV4 RCC_CFGR_PPRE_DIV4_Msk /*!< HCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 2983 #define RCC_CFGR_PPRE_DIV8_Pos (9U)
AnnaBridge 171:3a7713b1edbc 2984 #define RCC_CFGR_PPRE_DIV8_Msk (0x3U << RCC_CFGR_PPRE_DIV8_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 2985 #define RCC_CFGR_PPRE_DIV8 RCC_CFGR_PPRE_DIV8_Msk /*!< HCLK divided by 8 */
AnnaBridge 171:3a7713b1edbc 2986 #define RCC_CFGR_PPRE_DIV16_Pos (8U)
AnnaBridge 171:3a7713b1edbc 2987 #define RCC_CFGR_PPRE_DIV16_Msk (0x7U << RCC_CFGR_PPRE_DIV16_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 2988 #define RCC_CFGR_PPRE_DIV16 RCC_CFGR_PPRE_DIV16_Msk /*!< HCLK divided by 16 */
AnnaBridge 171:3a7713b1edbc 2989
AnnaBridge 171:3a7713b1edbc 2990 /*!< ADCPPRE configuration */
AnnaBridge 171:3a7713b1edbc 2991 #define RCC_CFGR_ADCPRE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 2992 #define RCC_CFGR_ADCPRE_Msk (0x1U << RCC_CFGR_ADCPRE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 2993 #define RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk /*!< ADCPRE bit (ADC prescaler) */
AnnaBridge 171:3a7713b1edbc 2994
AnnaBridge 171:3a7713b1edbc 2995 #define RCC_CFGR_ADCPRE_DIV2 (0x00000000U) /*!< PCLK divided by 2 */
AnnaBridge 171:3a7713b1edbc 2996 #define RCC_CFGR_ADCPRE_DIV4 (0x00004000U) /*!< PCLK divided by 4 */
AnnaBridge 171:3a7713b1edbc 2997
AnnaBridge 171:3a7713b1edbc 2998 #define RCC_CFGR_PLLSRC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 2999 #define RCC_CFGR_PLLSRC_Msk (0x1U << RCC_CFGR_PLLSRC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3000 #define RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk /*!< PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 3001 #define RCC_CFGR_PLLSRC_HSI_DIV2 (0x00000000U) /*!< HSI clock divided by 2 selected as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 3002 #define RCC_CFGR_PLLSRC_HSE_PREDIV (0x00010000U) /*!< HSE/PREDIV clock selected as PLL entry clock source */
AnnaBridge 171:3a7713b1edbc 3003
AnnaBridge 171:3a7713b1edbc 3004 #define RCC_CFGR_PLLXTPRE_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3005 #define RCC_CFGR_PLLXTPRE_Msk (0x1U << RCC_CFGR_PLLXTPRE_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3006 #define RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk /*!< HSE divider for PLL entry */
AnnaBridge 171:3a7713b1edbc 3007 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 (0x00000000U) /*!< HSE/PREDIV clock not divided for PLL entry */
AnnaBridge 171:3a7713b1edbc 3008 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 (0x00020000U) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
AnnaBridge 171:3a7713b1edbc 3009
AnnaBridge 171:3a7713b1edbc 3010 /*!< PLLMUL configuration */
AnnaBridge 171:3a7713b1edbc 3011 #define RCC_CFGR_PLLMUL_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3012 #define RCC_CFGR_PLLMUL_Msk (0xFU << RCC_CFGR_PLLMUL_Pos) /*!< 0x003C0000 */
AnnaBridge 171:3a7713b1edbc 3013 #define RCC_CFGR_PLLMUL RCC_CFGR_PLLMUL_Msk /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
AnnaBridge 171:3a7713b1edbc 3014 #define RCC_CFGR_PLLMUL_0 (0x1U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3015 #define RCC_CFGR_PLLMUL_1 (0x2U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3016 #define RCC_CFGR_PLLMUL_2 (0x4U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3017 #define RCC_CFGR_PLLMUL_3 (0x8U << RCC_CFGR_PLLMUL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3018
AnnaBridge 171:3a7713b1edbc 3019 #define RCC_CFGR_PLLMUL2 (0x00000000U) /*!< PLL input clock*2 */
AnnaBridge 171:3a7713b1edbc 3020 #define RCC_CFGR_PLLMUL3 (0x00040000U) /*!< PLL input clock*3 */
AnnaBridge 171:3a7713b1edbc 3021 #define RCC_CFGR_PLLMUL4 (0x00080000U) /*!< PLL input clock*4 */
AnnaBridge 171:3a7713b1edbc 3022 #define RCC_CFGR_PLLMUL5 (0x000C0000U) /*!< PLL input clock*5 */
AnnaBridge 171:3a7713b1edbc 3023 #define RCC_CFGR_PLLMUL6 (0x00100000U) /*!< PLL input clock*6 */
AnnaBridge 171:3a7713b1edbc 3024 #define RCC_CFGR_PLLMUL7 (0x00140000U) /*!< PLL input clock*7 */
AnnaBridge 171:3a7713b1edbc 3025 #define RCC_CFGR_PLLMUL8 (0x00180000U) /*!< PLL input clock*8 */
AnnaBridge 171:3a7713b1edbc 3026 #define RCC_CFGR_PLLMUL9 (0x001C0000U) /*!< PLL input clock*9 */
AnnaBridge 171:3a7713b1edbc 3027 #define RCC_CFGR_PLLMUL10 (0x00200000U) /*!< PLL input clock10 */
AnnaBridge 171:3a7713b1edbc 3028 #define RCC_CFGR_PLLMUL11 (0x00240000U) /*!< PLL input clock*11 */
AnnaBridge 171:3a7713b1edbc 3029 #define RCC_CFGR_PLLMUL12 (0x00280000U) /*!< PLL input clock*12 */
AnnaBridge 171:3a7713b1edbc 3030 #define RCC_CFGR_PLLMUL13 (0x002C0000U) /*!< PLL input clock*13 */
AnnaBridge 171:3a7713b1edbc 3031 #define RCC_CFGR_PLLMUL14 (0x00300000U) /*!< PLL input clock*14 */
AnnaBridge 171:3a7713b1edbc 3032 #define RCC_CFGR_PLLMUL15 (0x00340000U) /*!< PLL input clock*15 */
AnnaBridge 171:3a7713b1edbc 3033 #define RCC_CFGR_PLLMUL16 (0x00380000U) /*!< PLL input clock*16 */
AnnaBridge 171:3a7713b1edbc 3034
AnnaBridge 171:3a7713b1edbc 3035 /*!< MCO configuration */
AnnaBridge 171:3a7713b1edbc 3036 #define RCC_CFGR_MCO_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3037 #define RCC_CFGR_MCO_Msk (0xFU << RCC_CFGR_MCO_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3038 #define RCC_CFGR_MCO RCC_CFGR_MCO_Msk /*!< MCO[3:0] bits (Microcontroller Clock Output) */
AnnaBridge 171:3a7713b1edbc 3039 #define RCC_CFGR_MCO_0 (0x1U << RCC_CFGR_MCO_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3040 #define RCC_CFGR_MCO_1 (0x2U << RCC_CFGR_MCO_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3041 #define RCC_CFGR_MCO_2 (0x4U << RCC_CFGR_MCO_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3042
AnnaBridge 171:3a7713b1edbc 3043 #define RCC_CFGR_MCO_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 171:3a7713b1edbc 3044 #define RCC_CFGR_MCO_HSI14 (0x01000000U) /*!< HSI14 clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3045 #define RCC_CFGR_MCO_LSI (0x02000000U) /*!< LSI clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3046 #define RCC_CFGR_MCO_LSE (0x03000000U) /*!< LSE clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3047 #define RCC_CFGR_MCO_SYSCLK (0x04000000U) /*!< System clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3048 #define RCC_CFGR_MCO_HSI (0x05000000U) /*!< HSI clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3049 #define RCC_CFGR_MCO_HSE (0x06000000U) /*!< HSE clock selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3050 #define RCC_CFGR_MCO_PLL (0x07000000U) /*!< PLL clock divided by 2 selected as MCO source */
AnnaBridge 171:3a7713b1edbc 3051
AnnaBridge 171:3a7713b1edbc 3052 #define RCC_CFGR_MCOPRE_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3053 #define RCC_CFGR_MCOPRE_Msk (0x7U << RCC_CFGR_MCOPRE_Pos) /*!< 0x70000000 */
AnnaBridge 171:3a7713b1edbc 3054 #define RCC_CFGR_MCOPRE RCC_CFGR_MCOPRE_Msk /*!< MCO prescaler */
AnnaBridge 171:3a7713b1edbc 3055 #define RCC_CFGR_MCOPRE_DIV1 (0x00000000U) /*!< MCO is divided by 1 */
AnnaBridge 171:3a7713b1edbc 3056 #define RCC_CFGR_MCOPRE_DIV2 (0x10000000U) /*!< MCO is divided by 2 */
AnnaBridge 171:3a7713b1edbc 3057 #define RCC_CFGR_MCOPRE_DIV4 (0x20000000U) /*!< MCO is divided by 4 */
AnnaBridge 171:3a7713b1edbc 3058 #define RCC_CFGR_MCOPRE_DIV8 (0x30000000U) /*!< MCO is divided by 8 */
AnnaBridge 171:3a7713b1edbc 3059 #define RCC_CFGR_MCOPRE_DIV16 (0x40000000U) /*!< MCO is divided by 16 */
AnnaBridge 171:3a7713b1edbc 3060 #define RCC_CFGR_MCOPRE_DIV32 (0x50000000U) /*!< MCO is divided by 32 */
AnnaBridge 171:3a7713b1edbc 3061 #define RCC_CFGR_MCOPRE_DIV64 (0x60000000U) /*!< MCO is divided by 64 */
AnnaBridge 171:3a7713b1edbc 3062 #define RCC_CFGR_MCOPRE_DIV128 (0x70000000U) /*!< MCO is divided by 128 */
AnnaBridge 171:3a7713b1edbc 3063
AnnaBridge 171:3a7713b1edbc 3064 #define RCC_CFGR_PLLNODIV_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3065 #define RCC_CFGR_PLLNODIV_Msk (0x1U << RCC_CFGR_PLLNODIV_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3066 #define RCC_CFGR_PLLNODIV RCC_CFGR_PLLNODIV_Msk /*!< PLL is not divided to MCO */
AnnaBridge 171:3a7713b1edbc 3067
AnnaBridge 171:3a7713b1edbc 3068 /* Reference defines */
AnnaBridge 171:3a7713b1edbc 3069 #define RCC_CFGR_MCOSEL RCC_CFGR_MCO
AnnaBridge 171:3a7713b1edbc 3070 #define RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0
AnnaBridge 171:3a7713b1edbc 3071 #define RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1
AnnaBridge 171:3a7713b1edbc 3072 #define RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2
AnnaBridge 171:3a7713b1edbc 3073 #define RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK
AnnaBridge 171:3a7713b1edbc 3074 #define RCC_CFGR_MCOSEL_HSI14 RCC_CFGR_MCO_HSI14
AnnaBridge 171:3a7713b1edbc 3075 #define RCC_CFGR_MCOSEL_LSI RCC_CFGR_MCO_LSI
AnnaBridge 171:3a7713b1edbc 3076 #define RCC_CFGR_MCOSEL_LSE RCC_CFGR_MCO_LSE
AnnaBridge 171:3a7713b1edbc 3077 #define RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK
AnnaBridge 171:3a7713b1edbc 3078 #define RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI
AnnaBridge 171:3a7713b1edbc 3079 #define RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE
AnnaBridge 171:3a7713b1edbc 3080 #define RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLL
AnnaBridge 171:3a7713b1edbc 3081
AnnaBridge 171:3a7713b1edbc 3082 /*!<****************** Bit definition for RCC_CIR register *****************/
AnnaBridge 171:3a7713b1edbc 3083 #define RCC_CIR_LSIRDYF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3084 #define RCC_CIR_LSIRDYF_Msk (0x1U << RCC_CIR_LSIRDYF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3085 #define RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk /*!< LSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3086 #define RCC_CIR_LSERDYF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3087 #define RCC_CIR_LSERDYF_Msk (0x1U << RCC_CIR_LSERDYF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3088 #define RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk /*!< LSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3089 #define RCC_CIR_HSIRDYF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3090 #define RCC_CIR_HSIRDYF_Msk (0x1U << RCC_CIR_HSIRDYF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3091 #define RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk /*!< HSI Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3092 #define RCC_CIR_HSERDYF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3093 #define RCC_CIR_HSERDYF_Msk (0x1U << RCC_CIR_HSERDYF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3094 #define RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk /*!< HSE Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3095 #define RCC_CIR_PLLRDYF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3096 #define RCC_CIR_PLLRDYF_Msk (0x1U << RCC_CIR_PLLRDYF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3097 #define RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk /*!< PLL Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3098 #define RCC_CIR_HSI14RDYF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3099 #define RCC_CIR_HSI14RDYF_Msk (0x1U << RCC_CIR_HSI14RDYF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3100 #define RCC_CIR_HSI14RDYF RCC_CIR_HSI14RDYF_Msk /*!< HSI14 Ready Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3101 #define RCC_CIR_CSSF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3102 #define RCC_CIR_CSSF_Msk (0x1U << RCC_CIR_CSSF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3103 #define RCC_CIR_CSSF RCC_CIR_CSSF_Msk /*!< Clock Security System Interrupt flag */
AnnaBridge 171:3a7713b1edbc 3104 #define RCC_CIR_LSIRDYIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3105 #define RCC_CIR_LSIRDYIE_Msk (0x1U << RCC_CIR_LSIRDYIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3106 #define RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk /*!< LSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3107 #define RCC_CIR_LSERDYIE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3108 #define RCC_CIR_LSERDYIE_Msk (0x1U << RCC_CIR_LSERDYIE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3109 #define RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk /*!< LSE Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3110 #define RCC_CIR_HSIRDYIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3111 #define RCC_CIR_HSIRDYIE_Msk (0x1U << RCC_CIR_HSIRDYIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3112 #define RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk /*!< HSI Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3113 #define RCC_CIR_HSERDYIE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3114 #define RCC_CIR_HSERDYIE_Msk (0x1U << RCC_CIR_HSERDYIE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3115 #define RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk /*!< HSE Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3116 #define RCC_CIR_PLLRDYIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3117 #define RCC_CIR_PLLRDYIE_Msk (0x1U << RCC_CIR_PLLRDYIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3118 #define RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk /*!< PLL Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3119 #define RCC_CIR_HSI14RDYIE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3120 #define RCC_CIR_HSI14RDYIE_Msk (0x1U << RCC_CIR_HSI14RDYIE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3121 #define RCC_CIR_HSI14RDYIE RCC_CIR_HSI14RDYIE_Msk /*!< HSI14 Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3122 #define RCC_CIR_LSIRDYC_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3123 #define RCC_CIR_LSIRDYC_Msk (0x1U << RCC_CIR_LSIRDYC_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3124 #define RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk /*!< LSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3125 #define RCC_CIR_LSERDYC_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3126 #define RCC_CIR_LSERDYC_Msk (0x1U << RCC_CIR_LSERDYC_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3127 #define RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk /*!< LSE Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3128 #define RCC_CIR_HSIRDYC_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3129 #define RCC_CIR_HSIRDYC_Msk (0x1U << RCC_CIR_HSIRDYC_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3130 #define RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk /*!< HSI Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3131 #define RCC_CIR_HSERDYC_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3132 #define RCC_CIR_HSERDYC_Msk (0x1U << RCC_CIR_HSERDYC_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3133 #define RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk /*!< HSE Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3134 #define RCC_CIR_PLLRDYC_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3135 #define RCC_CIR_PLLRDYC_Msk (0x1U << RCC_CIR_PLLRDYC_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3136 #define RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk /*!< PLL Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3137 #define RCC_CIR_HSI14RDYC_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3138 #define RCC_CIR_HSI14RDYC_Msk (0x1U << RCC_CIR_HSI14RDYC_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3139 #define RCC_CIR_HSI14RDYC RCC_CIR_HSI14RDYC_Msk /*!< HSI14 Ready Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3140 #define RCC_CIR_CSSC_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3141 #define RCC_CIR_CSSC_Msk (0x1U << RCC_CIR_CSSC_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3142 #define RCC_CIR_CSSC RCC_CIR_CSSC_Msk /*!< Clock Security System Interrupt Clear */
AnnaBridge 171:3a7713b1edbc 3143
AnnaBridge 171:3a7713b1edbc 3144 /***************** Bit definition for RCC_APB2RSTR register ****************/
AnnaBridge 171:3a7713b1edbc 3145 #define RCC_APB2RSTR_SYSCFGRST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3146 #define RCC_APB2RSTR_SYSCFGRST_Msk (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3147 #define RCC_APB2RSTR_SYSCFGRST RCC_APB2RSTR_SYSCFGRST_Msk /*!< SYSCFG reset */
AnnaBridge 171:3a7713b1edbc 3148 #define RCC_APB2RSTR_ADCRST_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3149 #define RCC_APB2RSTR_ADCRST_Msk (0x1U << RCC_APB2RSTR_ADCRST_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3150 #define RCC_APB2RSTR_ADCRST RCC_APB2RSTR_ADCRST_Msk /*!< ADC reset */
AnnaBridge 171:3a7713b1edbc 3151 #define RCC_APB2RSTR_TIM1RST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3152 #define RCC_APB2RSTR_TIM1RST_Msk (0x1U << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3153 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk /*!< TIM1 reset */
AnnaBridge 171:3a7713b1edbc 3154 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3155 #define RCC_APB2RSTR_SPI1RST_Msk (0x1U << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3156 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk /*!< SPI1 reset */
AnnaBridge 171:3a7713b1edbc 3157 #define RCC_APB2RSTR_USART1RST_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3158 #define RCC_APB2RSTR_USART1RST_Msk (0x1U << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3159 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk /*!< USART1 reset */
AnnaBridge 171:3a7713b1edbc 3160 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3161 #define RCC_APB2RSTR_TIM16RST_Msk (0x1U << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3162 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk /*!< TIM16 reset */
AnnaBridge 171:3a7713b1edbc 3163 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3164 #define RCC_APB2RSTR_TIM17RST_Msk (0x1U << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3165 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk /*!< TIM17 reset */
AnnaBridge 171:3a7713b1edbc 3166 #define RCC_APB2RSTR_DBGMCURST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3167 #define RCC_APB2RSTR_DBGMCURST_Msk (0x1U << RCC_APB2RSTR_DBGMCURST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3168 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGMCURST_Msk /*!< DBGMCU reset */
AnnaBridge 171:3a7713b1edbc 3169
AnnaBridge 171:3a7713b1edbc 3170 /*!< Old ADC1 reset bit definition maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 3171 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
AnnaBridge 171:3a7713b1edbc 3172
AnnaBridge 171:3a7713b1edbc 3173 /***************** Bit definition for RCC_APB1RSTR register ****************/
AnnaBridge 171:3a7713b1edbc 3174 #define RCC_APB1RSTR_TIM2RST_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3175 #define RCC_APB1RSTR_TIM2RST_Msk (0x1U << RCC_APB1RSTR_TIM2RST_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3176 #define RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk /*!< Timer 2 reset */
AnnaBridge 171:3a7713b1edbc 3177 #define RCC_APB1RSTR_TIM3RST_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3178 #define RCC_APB1RSTR_TIM3RST_Msk (0x1U << RCC_APB1RSTR_TIM3RST_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3179 #define RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk /*!< Timer 3 reset */
AnnaBridge 171:3a7713b1edbc 3180 #define RCC_APB1RSTR_TIM14RST_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3181 #define RCC_APB1RSTR_TIM14RST_Msk (0x1U << RCC_APB1RSTR_TIM14RST_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3182 #define RCC_APB1RSTR_TIM14RST RCC_APB1RSTR_TIM14RST_Msk /*!< Timer 14 reset */
AnnaBridge 171:3a7713b1edbc 3183 #define RCC_APB1RSTR_WWDGRST_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3184 #define RCC_APB1RSTR_WWDGRST_Msk (0x1U << RCC_APB1RSTR_WWDGRST_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3185 #define RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk /*!< Window Watchdog reset */
AnnaBridge 171:3a7713b1edbc 3186 #define RCC_APB1RSTR_I2C1RST_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3187 #define RCC_APB1RSTR_I2C1RST_Msk (0x1U << RCC_APB1RSTR_I2C1RST_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3188 #define RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk /*!< I2C 1 reset */
AnnaBridge 171:3a7713b1edbc 3189 #define RCC_APB1RSTR_PWRRST_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3190 #define RCC_APB1RSTR_PWRRST_Msk (0x1U << RCC_APB1RSTR_PWRRST_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3191 #define RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk /*!< PWR reset */
AnnaBridge 171:3a7713b1edbc 3192
AnnaBridge 171:3a7713b1edbc 3193 /****************** Bit definition for RCC_AHBENR register *****************/
AnnaBridge 171:3a7713b1edbc 3194 #define RCC_AHBENR_DMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3195 #define RCC_AHBENR_DMAEN_Msk (0x1U << RCC_AHBENR_DMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3196 #define RCC_AHBENR_DMAEN RCC_AHBENR_DMAEN_Msk /*!< DMA1 clock enable */
AnnaBridge 171:3a7713b1edbc 3197 #define RCC_AHBENR_SRAMEN_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3198 #define RCC_AHBENR_SRAMEN_Msk (0x1U << RCC_AHBENR_SRAMEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3199 #define RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk /*!< SRAM interface clock enable */
AnnaBridge 171:3a7713b1edbc 3200 #define RCC_AHBENR_FLITFEN_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3201 #define RCC_AHBENR_FLITFEN_Msk (0x1U << RCC_AHBENR_FLITFEN_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3202 #define RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk /*!< FLITF clock enable */
AnnaBridge 171:3a7713b1edbc 3203 #define RCC_AHBENR_CRCEN_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3204 #define RCC_AHBENR_CRCEN_Msk (0x1U << RCC_AHBENR_CRCEN_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3205 #define RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk /*!< CRC clock enable */
AnnaBridge 171:3a7713b1edbc 3206 #define RCC_AHBENR_GPIOAEN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3207 #define RCC_AHBENR_GPIOAEN_Msk (0x1U << RCC_AHBENR_GPIOAEN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3208 #define RCC_AHBENR_GPIOAEN RCC_AHBENR_GPIOAEN_Msk /*!< GPIOA clock enable */
AnnaBridge 171:3a7713b1edbc 3209 #define RCC_AHBENR_GPIOBEN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3210 #define RCC_AHBENR_GPIOBEN_Msk (0x1U << RCC_AHBENR_GPIOBEN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3211 #define RCC_AHBENR_GPIOBEN RCC_AHBENR_GPIOBEN_Msk /*!< GPIOB clock enable */
AnnaBridge 171:3a7713b1edbc 3212 #define RCC_AHBENR_GPIOCEN_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3213 #define RCC_AHBENR_GPIOCEN_Msk (0x1U << RCC_AHBENR_GPIOCEN_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3214 #define RCC_AHBENR_GPIOCEN RCC_AHBENR_GPIOCEN_Msk /*!< GPIOC clock enable */
AnnaBridge 171:3a7713b1edbc 3215 #define RCC_AHBENR_GPIOFEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3216 #define RCC_AHBENR_GPIOFEN_Msk (0x1U << RCC_AHBENR_GPIOFEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3217 #define RCC_AHBENR_GPIOFEN RCC_AHBENR_GPIOFEN_Msk /*!< GPIOF clock enable */
AnnaBridge 171:3a7713b1edbc 3218
AnnaBridge 171:3a7713b1edbc 3219 /* Old Bit definition maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 3220 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
AnnaBridge 171:3a7713b1edbc 3221 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
AnnaBridge 171:3a7713b1edbc 3222
AnnaBridge 171:3a7713b1edbc 3223 /***************** Bit definition for RCC_APB2ENR register *****************/
AnnaBridge 171:3a7713b1edbc 3224 #define RCC_APB2ENR_SYSCFGCOMPEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3225 #define RCC_APB2ENR_SYSCFGCOMPEN_Msk (0x1U << RCC_APB2ENR_SYSCFGCOMPEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3226 #define RCC_APB2ENR_SYSCFGCOMPEN RCC_APB2ENR_SYSCFGCOMPEN_Msk /*!< SYSCFG and comparator clock enable */
AnnaBridge 171:3a7713b1edbc 3227 #define RCC_APB2ENR_ADCEN_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3228 #define RCC_APB2ENR_ADCEN_Msk (0x1U << RCC_APB2ENR_ADCEN_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3229 #define RCC_APB2ENR_ADCEN RCC_APB2ENR_ADCEN_Msk /*!< ADC1 clock enable */
AnnaBridge 171:3a7713b1edbc 3230 #define RCC_APB2ENR_TIM1EN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3231 #define RCC_APB2ENR_TIM1EN_Msk (0x1U << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3232 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk /*!< TIM1 clock enable */
AnnaBridge 171:3a7713b1edbc 3233 #define RCC_APB2ENR_SPI1EN_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3234 #define RCC_APB2ENR_SPI1EN_Msk (0x1U << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3235 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk /*!< SPI1 clock enable */
AnnaBridge 171:3a7713b1edbc 3236 #define RCC_APB2ENR_USART1EN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3237 #define RCC_APB2ENR_USART1EN_Msk (0x1U << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3238 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk /*!< USART1 clock enable */
AnnaBridge 171:3a7713b1edbc 3239 #define RCC_APB2ENR_TIM16EN_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3240 #define RCC_APB2ENR_TIM16EN_Msk (0x1U << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3241 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk /*!< TIM16 clock enable */
AnnaBridge 171:3a7713b1edbc 3242 #define RCC_APB2ENR_TIM17EN_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3243 #define RCC_APB2ENR_TIM17EN_Msk (0x1U << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3244 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk /*!< TIM17 clock enable */
AnnaBridge 171:3a7713b1edbc 3245 #define RCC_APB2ENR_DBGMCUEN_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3246 #define RCC_APB2ENR_DBGMCUEN_Msk (0x1U << RCC_APB2ENR_DBGMCUEN_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3247 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGMCUEN_Msk /*!< DBGMCU clock enable */
AnnaBridge 171:3a7713b1edbc 3248
AnnaBridge 171:3a7713b1edbc 3249 /* Old Bit definition maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 3250 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
AnnaBridge 171:3a7713b1edbc 3251 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
AnnaBridge 171:3a7713b1edbc 3252
AnnaBridge 171:3a7713b1edbc 3253 /***************** Bit definition for RCC_APB1ENR register *****************/
AnnaBridge 171:3a7713b1edbc 3254 #define RCC_APB1ENR_TIM2EN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3255 #define RCC_APB1ENR_TIM2EN_Msk (0x1U << RCC_APB1ENR_TIM2EN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3256 #define RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk /*!< Timer 2 clock enable */
AnnaBridge 171:3a7713b1edbc 3257 #define RCC_APB1ENR_TIM3EN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3258 #define RCC_APB1ENR_TIM3EN_Msk (0x1U << RCC_APB1ENR_TIM3EN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3259 #define RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk /*!< Timer 3 clock enable */
AnnaBridge 171:3a7713b1edbc 3260 #define RCC_APB1ENR_TIM14EN_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3261 #define RCC_APB1ENR_TIM14EN_Msk (0x1U << RCC_APB1ENR_TIM14EN_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3262 #define RCC_APB1ENR_TIM14EN RCC_APB1ENR_TIM14EN_Msk /*!< Timer 14 clock enable */
AnnaBridge 171:3a7713b1edbc 3263 #define RCC_APB1ENR_WWDGEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3264 #define RCC_APB1ENR_WWDGEN_Msk (0x1U << RCC_APB1ENR_WWDGEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3265 #define RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk /*!< Window Watchdog clock enable */
AnnaBridge 171:3a7713b1edbc 3266 #define RCC_APB1ENR_I2C1EN_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3267 #define RCC_APB1ENR_I2C1EN_Msk (0x1U << RCC_APB1ENR_I2C1EN_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3268 #define RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk /*!< I2C1 clock enable */
AnnaBridge 171:3a7713b1edbc 3269 #define RCC_APB1ENR_PWREN_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3270 #define RCC_APB1ENR_PWREN_Msk (0x1U << RCC_APB1ENR_PWREN_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3271 #define RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk /*!< PWR clock enable */
AnnaBridge 171:3a7713b1edbc 3272
AnnaBridge 171:3a7713b1edbc 3273 /******************* Bit definition for RCC_BDCR register ******************/
AnnaBridge 171:3a7713b1edbc 3274 #define RCC_BDCR_LSEON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3275 #define RCC_BDCR_LSEON_Msk (0x1U << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3276 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk /*!< External Low Speed oscillator enable */
AnnaBridge 171:3a7713b1edbc 3277 #define RCC_BDCR_LSERDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3278 #define RCC_BDCR_LSERDY_Msk (0x1U << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3279 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk /*!< External Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 3280 #define RCC_BDCR_LSEBYP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3281 #define RCC_BDCR_LSEBYP_Msk (0x1U << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3282 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk /*!< External Low Speed oscillator Bypass */
AnnaBridge 171:3a7713b1edbc 3283
AnnaBridge 171:3a7713b1edbc 3284 #define RCC_BDCR_LSEDRV_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3285 #define RCC_BDCR_LSEDRV_Msk (0x3U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
AnnaBridge 171:3a7713b1edbc 3286 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
AnnaBridge 171:3a7713b1edbc 3287 #define RCC_BDCR_LSEDRV_0 (0x1U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3288 #define RCC_BDCR_LSEDRV_1 (0x2U << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3289
AnnaBridge 171:3a7713b1edbc 3290 #define RCC_BDCR_RTCSEL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3291 #define RCC_BDCR_RTCSEL_Msk (0x3U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 3292 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk /*!< RTCSEL[1:0] bits (RTC clock source selection) */
AnnaBridge 171:3a7713b1edbc 3293 #define RCC_BDCR_RTCSEL_0 (0x1U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3294 #define RCC_BDCR_RTCSEL_1 (0x2U << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3295
AnnaBridge 171:3a7713b1edbc 3296 /*!< RTC configuration */
AnnaBridge 171:3a7713b1edbc 3297 #define RCC_BDCR_RTCSEL_NOCLOCK (0x00000000U) /*!< No clock */
AnnaBridge 171:3a7713b1edbc 3298 #define RCC_BDCR_RTCSEL_LSE (0x00000100U) /*!< LSE oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 3299 #define RCC_BDCR_RTCSEL_LSI (0x00000200U) /*!< LSI oscillator clock used as RTC clock */
AnnaBridge 171:3a7713b1edbc 3300 #define RCC_BDCR_RTCSEL_HSE (0x00000300U) /*!< HSE oscillator clock divided by 128 used as RTC clock */
AnnaBridge 171:3a7713b1edbc 3301
AnnaBridge 171:3a7713b1edbc 3302 #define RCC_BDCR_RTCEN_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3303 #define RCC_BDCR_RTCEN_Msk (0x1U << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3304 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk /*!< RTC clock enable */
AnnaBridge 171:3a7713b1edbc 3305 #define RCC_BDCR_BDRST_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3306 #define RCC_BDCR_BDRST_Msk (0x1U << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3307 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk /*!< Backup domain software reset */
AnnaBridge 171:3a7713b1edbc 3308
AnnaBridge 171:3a7713b1edbc 3309 /******************* Bit definition for RCC_CSR register *******************/
AnnaBridge 171:3a7713b1edbc 3310 #define RCC_CSR_LSION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3311 #define RCC_CSR_LSION_Msk (0x1U << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3312 #define RCC_CSR_LSION RCC_CSR_LSION_Msk /*!< Internal Low Speed oscillator enable */
AnnaBridge 171:3a7713b1edbc 3313 #define RCC_CSR_LSIRDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3314 #define RCC_CSR_LSIRDY_Msk (0x1U << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3315 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk /*!< Internal Low Speed oscillator Ready */
AnnaBridge 171:3a7713b1edbc 3316 #define RCC_CSR_V18PWRRSTF_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3317 #define RCC_CSR_V18PWRRSTF_Msk (0x1U << RCC_CSR_V18PWRRSTF_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3318 #define RCC_CSR_V18PWRRSTF RCC_CSR_V18PWRRSTF_Msk /*!< V1.8 power domain reset flag */
AnnaBridge 171:3a7713b1edbc 3319 #define RCC_CSR_RMVF_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3320 #define RCC_CSR_RMVF_Msk (0x1U << RCC_CSR_RMVF_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3321 #define RCC_CSR_RMVF RCC_CSR_RMVF_Msk /*!< Remove reset flag */
AnnaBridge 171:3a7713b1edbc 3322 #define RCC_CSR_OBLRSTF_Pos (25U)
AnnaBridge 171:3a7713b1edbc 3323 #define RCC_CSR_OBLRSTF_Msk (0x1U << RCC_CSR_OBLRSTF_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3324 #define RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF_Msk /*!< OBL reset flag */
AnnaBridge 171:3a7713b1edbc 3325 #define RCC_CSR_PINRSTF_Pos (26U)
AnnaBridge 171:3a7713b1edbc 3326 #define RCC_CSR_PINRSTF_Msk (0x1U << RCC_CSR_PINRSTF_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3327 #define RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk /*!< PIN reset flag */
AnnaBridge 171:3a7713b1edbc 3328 #define RCC_CSR_PORRSTF_Pos (27U)
AnnaBridge 171:3a7713b1edbc 3329 #define RCC_CSR_PORRSTF_Msk (0x1U << RCC_CSR_PORRSTF_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3330 #define RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk /*!< POR/PDR reset flag */
AnnaBridge 171:3a7713b1edbc 3331 #define RCC_CSR_SFTRSTF_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3332 #define RCC_CSR_SFTRSTF_Msk (0x1U << RCC_CSR_SFTRSTF_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3333 #define RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk /*!< Software Reset flag */
AnnaBridge 171:3a7713b1edbc 3334 #define RCC_CSR_IWDGRSTF_Pos (29U)
AnnaBridge 171:3a7713b1edbc 3335 #define RCC_CSR_IWDGRSTF_Msk (0x1U << RCC_CSR_IWDGRSTF_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3336 #define RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk /*!< Independent Watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 3337 #define RCC_CSR_WWDGRSTF_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3338 #define RCC_CSR_WWDGRSTF_Msk (0x1U << RCC_CSR_WWDGRSTF_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3339 #define RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk /*!< Window watchdog reset flag */
AnnaBridge 171:3a7713b1edbc 3340 #define RCC_CSR_LPWRRSTF_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3341 #define RCC_CSR_LPWRRSTF_Msk (0x1U << RCC_CSR_LPWRRSTF_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3342 #define RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk /*!< Low-Power reset flag */
AnnaBridge 171:3a7713b1edbc 3343
AnnaBridge 171:3a7713b1edbc 3344 /* Old Bit definition maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 3345 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
AnnaBridge 171:3a7713b1edbc 3346
AnnaBridge 171:3a7713b1edbc 3347 /******************* Bit definition for RCC_AHBRSTR register ***************/
AnnaBridge 171:3a7713b1edbc 3348 #define RCC_AHBRSTR_GPIOARST_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3349 #define RCC_AHBRSTR_GPIOARST_Msk (0x1U << RCC_AHBRSTR_GPIOARST_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3350 #define RCC_AHBRSTR_GPIOARST RCC_AHBRSTR_GPIOARST_Msk /*!< GPIOA reset */
AnnaBridge 171:3a7713b1edbc 3351 #define RCC_AHBRSTR_GPIOBRST_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3352 #define RCC_AHBRSTR_GPIOBRST_Msk (0x1U << RCC_AHBRSTR_GPIOBRST_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3353 #define RCC_AHBRSTR_GPIOBRST RCC_AHBRSTR_GPIOBRST_Msk /*!< GPIOB reset */
AnnaBridge 171:3a7713b1edbc 3354 #define RCC_AHBRSTR_GPIOCRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3355 #define RCC_AHBRSTR_GPIOCRST_Msk (0x1U << RCC_AHBRSTR_GPIOCRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3356 #define RCC_AHBRSTR_GPIOCRST RCC_AHBRSTR_GPIOCRST_Msk /*!< GPIOC reset */
AnnaBridge 171:3a7713b1edbc 3357 #define RCC_AHBRSTR_GPIOFRST_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3358 #define RCC_AHBRSTR_GPIOFRST_Msk (0x1U << RCC_AHBRSTR_GPIOFRST_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3359 #define RCC_AHBRSTR_GPIOFRST RCC_AHBRSTR_GPIOFRST_Msk /*!< GPIOF reset */
AnnaBridge 171:3a7713b1edbc 3360
AnnaBridge 171:3a7713b1edbc 3361 /******************* Bit definition for RCC_CFGR2 register *****************/
AnnaBridge 171:3a7713b1edbc 3362 /*!< PREDIV configuration */
AnnaBridge 171:3a7713b1edbc 3363 #define RCC_CFGR2_PREDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3364 #define RCC_CFGR2_PREDIV_Msk (0xFU << RCC_CFGR2_PREDIV_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3365 #define RCC_CFGR2_PREDIV RCC_CFGR2_PREDIV_Msk /*!< PREDIV[3:0] bits */
AnnaBridge 171:3a7713b1edbc 3366 #define RCC_CFGR2_PREDIV_0 (0x1U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3367 #define RCC_CFGR2_PREDIV_1 (0x2U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3368 #define RCC_CFGR2_PREDIV_2 (0x4U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3369 #define RCC_CFGR2_PREDIV_3 (0x8U << RCC_CFGR2_PREDIV_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3370
AnnaBridge 171:3a7713b1edbc 3371 #define RCC_CFGR2_PREDIV_DIV1 (0x00000000U) /*!< PREDIV input clock not divided */
AnnaBridge 171:3a7713b1edbc 3372 #define RCC_CFGR2_PREDIV_DIV2 (0x00000001U) /*!< PREDIV input clock divided by 2 */
AnnaBridge 171:3a7713b1edbc 3373 #define RCC_CFGR2_PREDIV_DIV3 (0x00000002U) /*!< PREDIV input clock divided by 3 */
AnnaBridge 171:3a7713b1edbc 3374 #define RCC_CFGR2_PREDIV_DIV4 (0x00000003U) /*!< PREDIV input clock divided by 4 */
AnnaBridge 171:3a7713b1edbc 3375 #define RCC_CFGR2_PREDIV_DIV5 (0x00000004U) /*!< PREDIV input clock divided by 5 */
AnnaBridge 171:3a7713b1edbc 3376 #define RCC_CFGR2_PREDIV_DIV6 (0x00000005U) /*!< PREDIV input clock divided by 6 */
AnnaBridge 171:3a7713b1edbc 3377 #define RCC_CFGR2_PREDIV_DIV7 (0x00000006U) /*!< PREDIV input clock divided by 7 */
AnnaBridge 171:3a7713b1edbc 3378 #define RCC_CFGR2_PREDIV_DIV8 (0x00000007U) /*!< PREDIV input clock divided by 8 */
AnnaBridge 171:3a7713b1edbc 3379 #define RCC_CFGR2_PREDIV_DIV9 (0x00000008U) /*!< PREDIV input clock divided by 9 */
AnnaBridge 171:3a7713b1edbc 3380 #define RCC_CFGR2_PREDIV_DIV10 (0x00000009U) /*!< PREDIV input clock divided by 10 */
AnnaBridge 171:3a7713b1edbc 3381 #define RCC_CFGR2_PREDIV_DIV11 (0x0000000AU) /*!< PREDIV input clock divided by 11 */
AnnaBridge 171:3a7713b1edbc 3382 #define RCC_CFGR2_PREDIV_DIV12 (0x0000000BU) /*!< PREDIV input clock divided by 12 */
AnnaBridge 171:3a7713b1edbc 3383 #define RCC_CFGR2_PREDIV_DIV13 (0x0000000CU) /*!< PREDIV input clock divided by 13 */
AnnaBridge 171:3a7713b1edbc 3384 #define RCC_CFGR2_PREDIV_DIV14 (0x0000000DU) /*!< PREDIV input clock divided by 14 */
AnnaBridge 171:3a7713b1edbc 3385 #define RCC_CFGR2_PREDIV_DIV15 (0x0000000EU) /*!< PREDIV input clock divided by 15 */
AnnaBridge 171:3a7713b1edbc 3386 #define RCC_CFGR2_PREDIV_DIV16 (0x0000000FU) /*!< PREDIV input clock divided by 16 */
AnnaBridge 171:3a7713b1edbc 3387
AnnaBridge 171:3a7713b1edbc 3388 /******************* Bit definition for RCC_CFGR3 register *****************/
AnnaBridge 171:3a7713b1edbc 3389 /*!< USART1 Clock source selection */
AnnaBridge 171:3a7713b1edbc 3390 #define RCC_CFGR3_USART1SW_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3391 #define RCC_CFGR3_USART1SW_Msk (0x3U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 3392 #define RCC_CFGR3_USART1SW RCC_CFGR3_USART1SW_Msk /*!< USART1SW[1:0] bits */
AnnaBridge 171:3a7713b1edbc 3393 #define RCC_CFGR3_USART1SW_0 (0x1U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3394 #define RCC_CFGR3_USART1SW_1 (0x2U << RCC_CFGR3_USART1SW_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3395
AnnaBridge 171:3a7713b1edbc 3396 #define RCC_CFGR3_USART1SW_PCLK (0x00000000U) /*!< PCLK clock used as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 3397 #define RCC_CFGR3_USART1SW_SYSCLK (0x00000001U) /*!< System clock selected as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 3398 #define RCC_CFGR3_USART1SW_LSE (0x00000002U) /*!< LSE oscillator clock used as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 3399 #define RCC_CFGR3_USART1SW_HSI (0x00000003U) /*!< HSI oscillator clock used as USART1 clock source */
AnnaBridge 171:3a7713b1edbc 3400
AnnaBridge 171:3a7713b1edbc 3401 /*!< I2C1 Clock source selection */
AnnaBridge 171:3a7713b1edbc 3402 #define RCC_CFGR3_I2C1SW_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3403 #define RCC_CFGR3_I2C1SW_Msk (0x1U << RCC_CFGR3_I2C1SW_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3404 #define RCC_CFGR3_I2C1SW RCC_CFGR3_I2C1SW_Msk /*!< I2C1SW bits */
AnnaBridge 171:3a7713b1edbc 3405
AnnaBridge 171:3a7713b1edbc 3406 #define RCC_CFGR3_I2C1SW_HSI (0x00000000U) /*!< HSI oscillator clock used as I2C1 clock source */
AnnaBridge 171:3a7713b1edbc 3407 #define RCC_CFGR3_I2C1SW_SYSCLK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3408 #define RCC_CFGR3_I2C1SW_SYSCLK_Msk (0x1U << RCC_CFGR3_I2C1SW_SYSCLK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3409 #define RCC_CFGR3_I2C1SW_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK_Msk /*!< System clock selected as I2C1 clock source */
AnnaBridge 171:3a7713b1edbc 3410
AnnaBridge 171:3a7713b1edbc 3411 /******************* Bit definition for RCC_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 3412 #define RCC_CR2_HSI14ON_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3413 #define RCC_CR2_HSI14ON_Msk (0x1U << RCC_CR2_HSI14ON_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3414 #define RCC_CR2_HSI14ON RCC_CR2_HSI14ON_Msk /*!< Internal High Speed 14MHz clock enable */
AnnaBridge 171:3a7713b1edbc 3415 #define RCC_CR2_HSI14RDY_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3416 #define RCC_CR2_HSI14RDY_Msk (0x1U << RCC_CR2_HSI14RDY_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3417 #define RCC_CR2_HSI14RDY RCC_CR2_HSI14RDY_Msk /*!< Internal High Speed 14MHz clock ready flag */
AnnaBridge 171:3a7713b1edbc 3418 #define RCC_CR2_HSI14DIS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3419 #define RCC_CR2_HSI14DIS_Msk (0x1U << RCC_CR2_HSI14DIS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3420 #define RCC_CR2_HSI14DIS RCC_CR2_HSI14DIS_Msk /*!< Internal High Speed 14MHz clock disable */
AnnaBridge 171:3a7713b1edbc 3421 #define RCC_CR2_HSI14TRIM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3422 #define RCC_CR2_HSI14TRIM_Msk (0x1FU << RCC_CR2_HSI14TRIM_Pos) /*!< 0x000000F8 */
AnnaBridge 171:3a7713b1edbc 3423 #define RCC_CR2_HSI14TRIM RCC_CR2_HSI14TRIM_Msk /*!< Internal High Speed 14MHz clock trimming */
AnnaBridge 171:3a7713b1edbc 3424 #define RCC_CR2_HSI14CAL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3425 #define RCC_CR2_HSI14CAL_Msk (0xFFU << RCC_CR2_HSI14CAL_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 3426 #define RCC_CR2_HSI14CAL RCC_CR2_HSI14CAL_Msk /*!< Internal High Speed 14MHz clock Calibration */
AnnaBridge 171:3a7713b1edbc 3427
AnnaBridge 171:3a7713b1edbc 3428 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3429 /* */
AnnaBridge 171:3a7713b1edbc 3430 /* Real-Time Clock (RTC) */
AnnaBridge 171:3a7713b1edbc 3431 /* */
AnnaBridge 171:3a7713b1edbc 3432 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3433 /*
AnnaBridge 171:3a7713b1edbc 3434 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 3435 */
AnnaBridge 171:3a7713b1edbc 3436 #define RTC_TAMPER1_SUPPORT /*!< TAMPER 1 feature support */
AnnaBridge 171:3a7713b1edbc 3437 #define RTC_TAMPER2_SUPPORT /*!< TAMPER 2 feature support */
AnnaBridge 171:3a7713b1edbc 3438 #define RTC_BACKUP_SUPPORT /*!< BACKUP register feature support */
AnnaBridge 171:3a7713b1edbc 3439
AnnaBridge 171:3a7713b1edbc 3440 /******************** Bits definition for RTC_TR register ******************/
AnnaBridge 171:3a7713b1edbc 3441 #define RTC_TR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3442 #define RTC_TR_PM_Msk (0x1U << RTC_TR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3443 #define RTC_TR_PM RTC_TR_PM_Msk
AnnaBridge 171:3a7713b1edbc 3444 #define RTC_TR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3445 #define RTC_TR_HT_Msk (0x3U << RTC_TR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 3446 #define RTC_TR_HT RTC_TR_HT_Msk
AnnaBridge 171:3a7713b1edbc 3447 #define RTC_TR_HT_0 (0x1U << RTC_TR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3448 #define RTC_TR_HT_1 (0x2U << RTC_TR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3449 #define RTC_TR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3450 #define RTC_TR_HU_Msk (0xFU << RTC_TR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3451 #define RTC_TR_HU RTC_TR_HU_Msk
AnnaBridge 171:3a7713b1edbc 3452 #define RTC_TR_HU_0 (0x1U << RTC_TR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3453 #define RTC_TR_HU_1 (0x2U << RTC_TR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3454 #define RTC_TR_HU_2 (0x4U << RTC_TR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3455 #define RTC_TR_HU_3 (0x8U << RTC_TR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3456 #define RTC_TR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3457 #define RTC_TR_MNT_Msk (0x7U << RTC_TR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 3458 #define RTC_TR_MNT RTC_TR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 3459 #define RTC_TR_MNT_0 (0x1U << RTC_TR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3460 #define RTC_TR_MNT_1 (0x2U << RTC_TR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3461 #define RTC_TR_MNT_2 (0x4U << RTC_TR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3462 #define RTC_TR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3463 #define RTC_TR_MNU_Msk (0xFU << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3464 #define RTC_TR_MNU RTC_TR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 3465 #define RTC_TR_MNU_0 (0x1U << RTC_TR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3466 #define RTC_TR_MNU_1 (0x2U << RTC_TR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3467 #define RTC_TR_MNU_2 (0x4U << RTC_TR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3468 #define RTC_TR_MNU_3 (0x8U << RTC_TR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3469 #define RTC_TR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3470 #define RTC_TR_ST_Msk (0x7U << RTC_TR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 3471 #define RTC_TR_ST RTC_TR_ST_Msk
AnnaBridge 171:3a7713b1edbc 3472 #define RTC_TR_ST_0 (0x1U << RTC_TR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3473 #define RTC_TR_ST_1 (0x2U << RTC_TR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3474 #define RTC_TR_ST_2 (0x4U << RTC_TR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3475 #define RTC_TR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3476 #define RTC_TR_SU_Msk (0xFU << RTC_TR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3477 #define RTC_TR_SU RTC_TR_SU_Msk
AnnaBridge 171:3a7713b1edbc 3478 #define RTC_TR_SU_0 (0x1U << RTC_TR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3479 #define RTC_TR_SU_1 (0x2U << RTC_TR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3480 #define RTC_TR_SU_2 (0x4U << RTC_TR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3481 #define RTC_TR_SU_3 (0x8U << RTC_TR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3482
AnnaBridge 171:3a7713b1edbc 3483 /******************** Bits definition for RTC_DR register ******************/
AnnaBridge 171:3a7713b1edbc 3484 #define RTC_DR_YT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3485 #define RTC_DR_YT_Msk (0xFU << RTC_DR_YT_Pos) /*!< 0x00F00000 */
AnnaBridge 171:3a7713b1edbc 3486 #define RTC_DR_YT RTC_DR_YT_Msk
AnnaBridge 171:3a7713b1edbc 3487 #define RTC_DR_YT_0 (0x1U << RTC_DR_YT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3488 #define RTC_DR_YT_1 (0x2U << RTC_DR_YT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3489 #define RTC_DR_YT_2 (0x4U << RTC_DR_YT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3490 #define RTC_DR_YT_3 (0x8U << RTC_DR_YT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3491 #define RTC_DR_YU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3492 #define RTC_DR_YU_Msk (0xFU << RTC_DR_YU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3493 #define RTC_DR_YU RTC_DR_YU_Msk
AnnaBridge 171:3a7713b1edbc 3494 #define RTC_DR_YU_0 (0x1U << RTC_DR_YU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3495 #define RTC_DR_YU_1 (0x2U << RTC_DR_YU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3496 #define RTC_DR_YU_2 (0x4U << RTC_DR_YU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3497 #define RTC_DR_YU_3 (0x8U << RTC_DR_YU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3498 #define RTC_DR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3499 #define RTC_DR_WDU_Msk (0x7U << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 3500 #define RTC_DR_WDU RTC_DR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 3501 #define RTC_DR_WDU_0 (0x1U << RTC_DR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3502 #define RTC_DR_WDU_1 (0x2U << RTC_DR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3503 #define RTC_DR_WDU_2 (0x4U << RTC_DR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3504 #define RTC_DR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3505 #define RTC_DR_MT_Msk (0x1U << RTC_DR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3506 #define RTC_DR_MT RTC_DR_MT_Msk
AnnaBridge 171:3a7713b1edbc 3507 #define RTC_DR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3508 #define RTC_DR_MU_Msk (0xFU << RTC_DR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3509 #define RTC_DR_MU RTC_DR_MU_Msk
AnnaBridge 171:3a7713b1edbc 3510 #define RTC_DR_MU_0 (0x1U << RTC_DR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3511 #define RTC_DR_MU_1 (0x2U << RTC_DR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3512 #define RTC_DR_MU_2 (0x4U << RTC_DR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3513 #define RTC_DR_MU_3 (0x8U << RTC_DR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3514 #define RTC_DR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3515 #define RTC_DR_DT_Msk (0x3U << RTC_DR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 3516 #define RTC_DR_DT RTC_DR_DT_Msk
AnnaBridge 171:3a7713b1edbc 3517 #define RTC_DR_DT_0 (0x1U << RTC_DR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3518 #define RTC_DR_DT_1 (0x2U << RTC_DR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3519 #define RTC_DR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3520 #define RTC_DR_DU_Msk (0xFU << RTC_DR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3521 #define RTC_DR_DU RTC_DR_DU_Msk
AnnaBridge 171:3a7713b1edbc 3522 #define RTC_DR_DU_0 (0x1U << RTC_DR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3523 #define RTC_DR_DU_1 (0x2U << RTC_DR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3524 #define RTC_DR_DU_2 (0x4U << RTC_DR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3525 #define RTC_DR_DU_3 (0x8U << RTC_DR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3526
AnnaBridge 171:3a7713b1edbc 3527 /******************** Bits definition for RTC_CR register ******************/
AnnaBridge 171:3a7713b1edbc 3528 #define RTC_CR_COE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3529 #define RTC_CR_COE_Msk (0x1U << RTC_CR_COE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3530 #define RTC_CR_COE RTC_CR_COE_Msk
AnnaBridge 171:3a7713b1edbc 3531 #define RTC_CR_OSEL_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3532 #define RTC_CR_OSEL_Msk (0x3U << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 3533 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
AnnaBridge 171:3a7713b1edbc 3534 #define RTC_CR_OSEL_0 (0x1U << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3535 #define RTC_CR_OSEL_1 (0x2U << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3536 #define RTC_CR_POL_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3537 #define RTC_CR_POL_Msk (0x1U << RTC_CR_POL_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3538 #define RTC_CR_POL RTC_CR_POL_Msk
AnnaBridge 171:3a7713b1edbc 3539 #define RTC_CR_COSEL_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3540 #define RTC_CR_COSEL_Msk (0x1U << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3541 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
AnnaBridge 171:3a7713b1edbc 3542 #define RTC_CR_BKP_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3543 #define RTC_CR_BKP_Msk (0x1U << RTC_CR_BKP_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3544 #define RTC_CR_BKP RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 3545 #define RTC_CR_SUB1H_Pos (17U)
AnnaBridge 171:3a7713b1edbc 3546 #define RTC_CR_SUB1H_Msk (0x1U << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3547 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
AnnaBridge 171:3a7713b1edbc 3548 #define RTC_CR_ADD1H_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3549 #define RTC_CR_ADD1H_Msk (0x1U << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3550 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
AnnaBridge 171:3a7713b1edbc 3551 #define RTC_CR_TSIE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3552 #define RTC_CR_TSIE_Msk (0x1U << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3553 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
AnnaBridge 171:3a7713b1edbc 3554 #define RTC_CR_ALRAIE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3555 #define RTC_CR_ALRAIE_Msk (0x1U << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3556 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
AnnaBridge 171:3a7713b1edbc 3557 #define RTC_CR_TSE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3558 #define RTC_CR_TSE_Msk (0x1U << RTC_CR_TSE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3559 #define RTC_CR_TSE RTC_CR_TSE_Msk
AnnaBridge 171:3a7713b1edbc 3560 #define RTC_CR_ALRAE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3561 #define RTC_CR_ALRAE_Msk (0x1U << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3562 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
AnnaBridge 171:3a7713b1edbc 3563 #define RTC_CR_FMT_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3564 #define RTC_CR_FMT_Msk (0x1U << RTC_CR_FMT_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3565 #define RTC_CR_FMT RTC_CR_FMT_Msk
AnnaBridge 171:3a7713b1edbc 3566 #define RTC_CR_BYPSHAD_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3567 #define RTC_CR_BYPSHAD_Msk (0x1U << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3568 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
AnnaBridge 171:3a7713b1edbc 3569 #define RTC_CR_REFCKON_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3570 #define RTC_CR_REFCKON_Msk (0x1U << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3571 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
AnnaBridge 171:3a7713b1edbc 3572 #define RTC_CR_TSEDGE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3573 #define RTC_CR_TSEDGE_Msk (0x1U << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3574 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
AnnaBridge 171:3a7713b1edbc 3575
AnnaBridge 171:3a7713b1edbc 3576 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 3577 #define RTC_CR_BCK_Pos RTC_CR_BKP_Pos
AnnaBridge 171:3a7713b1edbc 3578 #define RTC_CR_BCK_Msk RTC_CR_BKP_Msk
AnnaBridge 171:3a7713b1edbc 3579 #define RTC_CR_BCK RTC_CR_BKP
AnnaBridge 171:3a7713b1edbc 3580
AnnaBridge 171:3a7713b1edbc 3581 /******************** Bits definition for RTC_ISR register *****************/
AnnaBridge 171:3a7713b1edbc 3582 #define RTC_ISR_RECALPF_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3583 #define RTC_ISR_RECALPF_Msk (0x1U << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3584 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
AnnaBridge 171:3a7713b1edbc 3585 #define RTC_ISR_TAMP2F_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3586 #define RTC_ISR_TAMP2F_Msk (0x1U << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3587 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
AnnaBridge 171:3a7713b1edbc 3588 #define RTC_ISR_TAMP1F_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3589 #define RTC_ISR_TAMP1F_Msk (0x1U << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3590 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
AnnaBridge 171:3a7713b1edbc 3591 #define RTC_ISR_TSOVF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3592 #define RTC_ISR_TSOVF_Msk (0x1U << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3593 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
AnnaBridge 171:3a7713b1edbc 3594 #define RTC_ISR_TSF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3595 #define RTC_ISR_TSF_Msk (0x1U << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3596 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
AnnaBridge 171:3a7713b1edbc 3597 #define RTC_ISR_ALRAF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3598 #define RTC_ISR_ALRAF_Msk (0x1U << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3599 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
AnnaBridge 171:3a7713b1edbc 3600 #define RTC_ISR_INIT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3601 #define RTC_ISR_INIT_Msk (0x1U << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3602 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
AnnaBridge 171:3a7713b1edbc 3603 #define RTC_ISR_INITF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3604 #define RTC_ISR_INITF_Msk (0x1U << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3605 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
AnnaBridge 171:3a7713b1edbc 3606 #define RTC_ISR_RSF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3607 #define RTC_ISR_RSF_Msk (0x1U << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3608 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
AnnaBridge 171:3a7713b1edbc 3609 #define RTC_ISR_INITS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3610 #define RTC_ISR_INITS_Msk (0x1U << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3611 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
AnnaBridge 171:3a7713b1edbc 3612 #define RTC_ISR_SHPF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3613 #define RTC_ISR_SHPF_Msk (0x1U << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3614 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
AnnaBridge 171:3a7713b1edbc 3615 #define RTC_ISR_ALRAWF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3616 #define RTC_ISR_ALRAWF_Msk (0x1U << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3617 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
AnnaBridge 171:3a7713b1edbc 3618
AnnaBridge 171:3a7713b1edbc 3619 /******************** Bits definition for RTC_PRER register ****************/
AnnaBridge 171:3a7713b1edbc 3620 #define RTC_PRER_PREDIV_A_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3621 #define RTC_PRER_PREDIV_A_Msk (0x7FU << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
AnnaBridge 171:3a7713b1edbc 3622 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
AnnaBridge 171:3a7713b1edbc 3623 #define RTC_PRER_PREDIV_S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3624 #define RTC_PRER_PREDIV_S_Msk (0x7FFFU << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 3625 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
AnnaBridge 171:3a7713b1edbc 3626
AnnaBridge 171:3a7713b1edbc 3627 /******************** Bits definition for RTC_ALRMAR register **************/
AnnaBridge 171:3a7713b1edbc 3628 #define RTC_ALRMAR_MSK4_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3629 #define RTC_ALRMAR_MSK4_Msk (0x1U << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3630 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
AnnaBridge 171:3a7713b1edbc 3631 #define RTC_ALRMAR_WDSEL_Pos (30U)
AnnaBridge 171:3a7713b1edbc 3632 #define RTC_ALRMAR_WDSEL_Msk (0x1U << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
AnnaBridge 171:3a7713b1edbc 3633 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
AnnaBridge 171:3a7713b1edbc 3634 #define RTC_ALRMAR_DT_Pos (28U)
AnnaBridge 171:3a7713b1edbc 3635 #define RTC_ALRMAR_DT_Msk (0x3U << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
AnnaBridge 171:3a7713b1edbc 3636 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
AnnaBridge 171:3a7713b1edbc 3637 #define RTC_ALRMAR_DT_0 (0x1U << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
AnnaBridge 171:3a7713b1edbc 3638 #define RTC_ALRMAR_DT_1 (0x2U << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
AnnaBridge 171:3a7713b1edbc 3639 #define RTC_ALRMAR_DU_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3640 #define RTC_ALRMAR_DU_Msk (0xFU << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3641 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
AnnaBridge 171:3a7713b1edbc 3642 #define RTC_ALRMAR_DU_0 (0x1U << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3643 #define RTC_ALRMAR_DU_1 (0x2U << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3644 #define RTC_ALRMAR_DU_2 (0x4U << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3645 #define RTC_ALRMAR_DU_3 (0x8U << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3646 #define RTC_ALRMAR_MSK3_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3647 #define RTC_ALRMAR_MSK3_Msk (0x1U << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3648 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
AnnaBridge 171:3a7713b1edbc 3649 #define RTC_ALRMAR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3650 #define RTC_ALRMAR_PM_Msk (0x1U << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3651 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
AnnaBridge 171:3a7713b1edbc 3652 #define RTC_ALRMAR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3653 #define RTC_ALRMAR_HT_Msk (0x3U << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 3654 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
AnnaBridge 171:3a7713b1edbc 3655 #define RTC_ALRMAR_HT_0 (0x1U << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3656 #define RTC_ALRMAR_HT_1 (0x2U << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3657 #define RTC_ALRMAR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3658 #define RTC_ALRMAR_HU_Msk (0xFU << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3659 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
AnnaBridge 171:3a7713b1edbc 3660 #define RTC_ALRMAR_HU_0 (0x1U << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3661 #define RTC_ALRMAR_HU_1 (0x2U << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3662 #define RTC_ALRMAR_HU_2 (0x4U << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3663 #define RTC_ALRMAR_HU_3 (0x8U << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3664 #define RTC_ALRMAR_MSK2_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3665 #define RTC_ALRMAR_MSK2_Msk (0x1U << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3666 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
AnnaBridge 171:3a7713b1edbc 3667 #define RTC_ALRMAR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3668 #define RTC_ALRMAR_MNT_Msk (0x7U << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 3669 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 3670 #define RTC_ALRMAR_MNT_0 (0x1U << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3671 #define RTC_ALRMAR_MNT_1 (0x2U << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3672 #define RTC_ALRMAR_MNT_2 (0x4U << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3673 #define RTC_ALRMAR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3674 #define RTC_ALRMAR_MNU_Msk (0xFU << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3675 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 3676 #define RTC_ALRMAR_MNU_0 (0x1U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3677 #define RTC_ALRMAR_MNU_1 (0x2U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3678 #define RTC_ALRMAR_MNU_2 (0x4U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3679 #define RTC_ALRMAR_MNU_3 (0x8U << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3680 #define RTC_ALRMAR_MSK1_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3681 #define RTC_ALRMAR_MSK1_Msk (0x1U << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3682 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
AnnaBridge 171:3a7713b1edbc 3683 #define RTC_ALRMAR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3684 #define RTC_ALRMAR_ST_Msk (0x7U << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 3685 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
AnnaBridge 171:3a7713b1edbc 3686 #define RTC_ALRMAR_ST_0 (0x1U << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3687 #define RTC_ALRMAR_ST_1 (0x2U << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3688 #define RTC_ALRMAR_ST_2 (0x4U << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3689 #define RTC_ALRMAR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3690 #define RTC_ALRMAR_SU_Msk (0xFU << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3691 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
AnnaBridge 171:3a7713b1edbc 3692 #define RTC_ALRMAR_SU_0 (0x1U << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3693 #define RTC_ALRMAR_SU_1 (0x2U << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3694 #define RTC_ALRMAR_SU_2 (0x4U << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3695 #define RTC_ALRMAR_SU_3 (0x8U << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3696
AnnaBridge 171:3a7713b1edbc 3697 /******************** Bits definition for RTC_WPR register *****************/
AnnaBridge 171:3a7713b1edbc 3698 #define RTC_WPR_KEY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3699 #define RTC_WPR_KEY_Msk (0xFFU << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 3700 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
AnnaBridge 171:3a7713b1edbc 3701
AnnaBridge 171:3a7713b1edbc 3702 /******************** Bits definition for RTC_SSR register *****************/
AnnaBridge 171:3a7713b1edbc 3703 #define RTC_SSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3704 #define RTC_SSR_SS_Msk (0xFFFFU << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 3705 #define RTC_SSR_SS RTC_SSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 3706
AnnaBridge 171:3a7713b1edbc 3707 /******************** Bits definition for RTC_SHIFTR register **************/
AnnaBridge 171:3a7713b1edbc 3708 #define RTC_SHIFTR_SUBFS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3709 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFU << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 3710 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
AnnaBridge 171:3a7713b1edbc 3711 #define RTC_SHIFTR_ADD1S_Pos (31U)
AnnaBridge 171:3a7713b1edbc 3712 #define RTC_SHIFTR_ADD1S_Msk (0x1U << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
AnnaBridge 171:3a7713b1edbc 3713 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
AnnaBridge 171:3a7713b1edbc 3714
AnnaBridge 171:3a7713b1edbc 3715 /******************** Bits definition for RTC_TSTR register ****************/
AnnaBridge 171:3a7713b1edbc 3716 #define RTC_TSTR_PM_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3717 #define RTC_TSTR_PM_Msk (0x1U << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3718 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
AnnaBridge 171:3a7713b1edbc 3719 #define RTC_TSTR_HT_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3720 #define RTC_TSTR_HT_Msk (0x3U << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 3721 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
AnnaBridge 171:3a7713b1edbc 3722 #define RTC_TSTR_HT_0 (0x1U << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3723 #define RTC_TSTR_HT_1 (0x2U << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3724 #define RTC_TSTR_HU_Pos (16U)
AnnaBridge 171:3a7713b1edbc 3725 #define RTC_TSTR_HU_Msk (0xFU << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
AnnaBridge 171:3a7713b1edbc 3726 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
AnnaBridge 171:3a7713b1edbc 3727 #define RTC_TSTR_HU_0 (0x1U << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 3728 #define RTC_TSTR_HU_1 (0x2U << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 3729 #define RTC_TSTR_HU_2 (0x4U << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3730 #define RTC_TSTR_HU_3 (0x8U << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3731 #define RTC_TSTR_MNT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3732 #define RTC_TSTR_MNT_Msk (0x7U << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 3733 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
AnnaBridge 171:3a7713b1edbc 3734 #define RTC_TSTR_MNT_0 (0x1U << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3735 #define RTC_TSTR_MNT_1 (0x2U << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3736 #define RTC_TSTR_MNT_2 (0x4U << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3737 #define RTC_TSTR_MNU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3738 #define RTC_TSTR_MNU_Msk (0xFU << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3739 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
AnnaBridge 171:3a7713b1edbc 3740 #define RTC_TSTR_MNU_0 (0x1U << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3741 #define RTC_TSTR_MNU_1 (0x2U << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3742 #define RTC_TSTR_MNU_2 (0x4U << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3743 #define RTC_TSTR_MNU_3 (0x8U << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3744 #define RTC_TSTR_ST_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3745 #define RTC_TSTR_ST_Msk (0x7U << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 3746 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
AnnaBridge 171:3a7713b1edbc 3747 #define RTC_TSTR_ST_0 (0x1U << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3748 #define RTC_TSTR_ST_1 (0x2U << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3749 #define RTC_TSTR_ST_2 (0x4U << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3750 #define RTC_TSTR_SU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3751 #define RTC_TSTR_SU_Msk (0xFU << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3752 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
AnnaBridge 171:3a7713b1edbc 3753 #define RTC_TSTR_SU_0 (0x1U << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3754 #define RTC_TSTR_SU_1 (0x2U << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3755 #define RTC_TSTR_SU_2 (0x4U << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3756 #define RTC_TSTR_SU_3 (0x8U << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3757
AnnaBridge 171:3a7713b1edbc 3758 /******************** Bits definition for RTC_TSDR register ****************/
AnnaBridge 171:3a7713b1edbc 3759 #define RTC_TSDR_WDU_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3760 #define RTC_TSDR_WDU_Msk (0x7U << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
AnnaBridge 171:3a7713b1edbc 3761 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
AnnaBridge 171:3a7713b1edbc 3762 #define RTC_TSDR_WDU_0 (0x1U << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3763 #define RTC_TSDR_WDU_1 (0x2U << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3764 #define RTC_TSDR_WDU_2 (0x4U << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3765 #define RTC_TSDR_MT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3766 #define RTC_TSDR_MT_Msk (0x1U << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3767 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
AnnaBridge 171:3a7713b1edbc 3768 #define RTC_TSDR_MU_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3769 #define RTC_TSDR_MU_Msk (0xFU << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 3770 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
AnnaBridge 171:3a7713b1edbc 3771 #define RTC_TSDR_MU_0 (0x1U << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3772 #define RTC_TSDR_MU_1 (0x2U << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3773 #define RTC_TSDR_MU_2 (0x4U << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3774 #define RTC_TSDR_MU_3 (0x8U << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3775 #define RTC_TSDR_DT_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3776 #define RTC_TSDR_DT_Msk (0x3U << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 3777 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
AnnaBridge 171:3a7713b1edbc 3778 #define RTC_TSDR_DT_0 (0x1U << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3779 #define RTC_TSDR_DT_1 (0x2U << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3780 #define RTC_TSDR_DU_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3781 #define RTC_TSDR_DU_Msk (0xFU << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 3782 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
AnnaBridge 171:3a7713b1edbc 3783 #define RTC_TSDR_DU_0 (0x1U << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3784 #define RTC_TSDR_DU_1 (0x2U << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3785 #define RTC_TSDR_DU_2 (0x4U << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3786 #define RTC_TSDR_DU_3 (0x8U << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3787
AnnaBridge 171:3a7713b1edbc 3788 /******************** Bits definition for RTC_TSSSR register ***************/
AnnaBridge 171:3a7713b1edbc 3789 #define RTC_TSSSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3790 #define RTC_TSSSR_SS_Msk (0xFFFFU << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 3791 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 3792
AnnaBridge 171:3a7713b1edbc 3793 /******************** Bits definition for RTC_CALR register ****************/
AnnaBridge 171:3a7713b1edbc 3794 #define RTC_CALR_CALP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3795 #define RTC_CALR_CALP_Msk (0x1U << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3796 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
AnnaBridge 171:3a7713b1edbc 3797 #define RTC_CALR_CALW8_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3798 #define RTC_CALR_CALW8_Msk (0x1U << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3799 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
AnnaBridge 171:3a7713b1edbc 3800 #define RTC_CALR_CALW16_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3801 #define RTC_CALR_CALW16_Msk (0x1U << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3802 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
AnnaBridge 171:3a7713b1edbc 3803 #define RTC_CALR_CALM_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3804 #define RTC_CALR_CALM_Msk (0x1FFU << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
AnnaBridge 171:3a7713b1edbc 3805 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
AnnaBridge 171:3a7713b1edbc 3806 #define RTC_CALR_CALM_0 (0x001U << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3807 #define RTC_CALR_CALM_1 (0x002U << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3808 #define RTC_CALR_CALM_2 (0x004U << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3809 #define RTC_CALR_CALM_3 (0x008U << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3810 #define RTC_CALR_CALM_4 (0x010U << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3811 #define RTC_CALR_CALM_5 (0x020U << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3812 #define RTC_CALR_CALM_6 (0x040U << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3813 #define RTC_CALR_CALM_7 (0x080U << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3814 #define RTC_CALR_CALM_8 (0x100U << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3815
AnnaBridge 171:3a7713b1edbc 3816 /******************** Bits definition for RTC_TAFCR register ***************/
AnnaBridge 171:3a7713b1edbc 3817 #define RTC_TAFCR_PC15MODE_Pos (23U)
AnnaBridge 171:3a7713b1edbc 3818 #define RTC_TAFCR_PC15MODE_Msk (0x1U << RTC_TAFCR_PC15MODE_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 3819 #define RTC_TAFCR_PC15MODE RTC_TAFCR_PC15MODE_Msk
AnnaBridge 171:3a7713b1edbc 3820 #define RTC_TAFCR_PC15VALUE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 3821 #define RTC_TAFCR_PC15VALUE_Msk (0x1U << RTC_TAFCR_PC15VALUE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 3822 #define RTC_TAFCR_PC15VALUE RTC_TAFCR_PC15VALUE_Msk
AnnaBridge 171:3a7713b1edbc 3823 #define RTC_TAFCR_PC14MODE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 3824 #define RTC_TAFCR_PC14MODE_Msk (0x1U << RTC_TAFCR_PC14MODE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 3825 #define RTC_TAFCR_PC14MODE RTC_TAFCR_PC14MODE_Msk
AnnaBridge 171:3a7713b1edbc 3826 #define RTC_TAFCR_PC14VALUE_Pos (20U)
AnnaBridge 171:3a7713b1edbc 3827 #define RTC_TAFCR_PC14VALUE_Msk (0x1U << RTC_TAFCR_PC14VALUE_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 3828 #define RTC_TAFCR_PC14VALUE RTC_TAFCR_PC14VALUE_Msk
AnnaBridge 171:3a7713b1edbc 3829 #define RTC_TAFCR_PC13MODE_Pos (19U)
AnnaBridge 171:3a7713b1edbc 3830 #define RTC_TAFCR_PC13MODE_Msk (0x1U << RTC_TAFCR_PC13MODE_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 3831 #define RTC_TAFCR_PC13MODE RTC_TAFCR_PC13MODE_Msk
AnnaBridge 171:3a7713b1edbc 3832 #define RTC_TAFCR_PC13VALUE_Pos (18U)
AnnaBridge 171:3a7713b1edbc 3833 #define RTC_TAFCR_PC13VALUE_Msk (0x1U << RTC_TAFCR_PC13VALUE_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 3834 #define RTC_TAFCR_PC13VALUE RTC_TAFCR_PC13VALUE_Msk
AnnaBridge 171:3a7713b1edbc 3835 #define RTC_TAFCR_TAMPPUDIS_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3836 #define RTC_TAFCR_TAMPPUDIS_Msk (0x1U << RTC_TAFCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3837 #define RTC_TAFCR_TAMPPUDIS RTC_TAFCR_TAMPPUDIS_Msk
AnnaBridge 171:3a7713b1edbc 3838 #define RTC_TAFCR_TAMPPRCH_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3839 #define RTC_TAFCR_TAMPPRCH_Msk (0x3U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00006000 */
AnnaBridge 171:3a7713b1edbc 3840 #define RTC_TAFCR_TAMPPRCH RTC_TAFCR_TAMPPRCH_Msk
AnnaBridge 171:3a7713b1edbc 3841 #define RTC_TAFCR_TAMPPRCH_0 (0x1U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3842 #define RTC_TAFCR_TAMPPRCH_1 (0x2U << RTC_TAFCR_TAMPPRCH_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3843 #define RTC_TAFCR_TAMPFLT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3844 #define RTC_TAFCR_TAMPFLT_Msk (0x3U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 3845 #define RTC_TAFCR_TAMPFLT RTC_TAFCR_TAMPFLT_Msk
AnnaBridge 171:3a7713b1edbc 3846 #define RTC_TAFCR_TAMPFLT_0 (0x1U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3847 #define RTC_TAFCR_TAMPFLT_1 (0x2U << RTC_TAFCR_TAMPFLT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3848 #define RTC_TAFCR_TAMPFREQ_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3849 #define RTC_TAFCR_TAMPFREQ_Msk (0x7U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000700 */
AnnaBridge 171:3a7713b1edbc 3850 #define RTC_TAFCR_TAMPFREQ RTC_TAFCR_TAMPFREQ_Msk
AnnaBridge 171:3a7713b1edbc 3851 #define RTC_TAFCR_TAMPFREQ_0 (0x1U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3852 #define RTC_TAFCR_TAMPFREQ_1 (0x2U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3853 #define RTC_TAFCR_TAMPFREQ_2 (0x4U << RTC_TAFCR_TAMPFREQ_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3854 #define RTC_TAFCR_TAMPTS_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3855 #define RTC_TAFCR_TAMPTS_Msk (0x1U << RTC_TAFCR_TAMPTS_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3856 #define RTC_TAFCR_TAMPTS RTC_TAFCR_TAMPTS_Msk
AnnaBridge 171:3a7713b1edbc 3857 #define RTC_TAFCR_TAMP2TRG_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3858 #define RTC_TAFCR_TAMP2TRG_Msk (0x1U << RTC_TAFCR_TAMP2TRG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3859 #define RTC_TAFCR_TAMP2TRG RTC_TAFCR_TAMP2TRG_Msk
AnnaBridge 171:3a7713b1edbc 3860 #define RTC_TAFCR_TAMP2E_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3861 #define RTC_TAFCR_TAMP2E_Msk (0x1U << RTC_TAFCR_TAMP2E_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3862 #define RTC_TAFCR_TAMP2E RTC_TAFCR_TAMP2E_Msk
AnnaBridge 171:3a7713b1edbc 3863 #define RTC_TAFCR_TAMPIE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3864 #define RTC_TAFCR_TAMPIE_Msk (0x1U << RTC_TAFCR_TAMPIE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3865 #define RTC_TAFCR_TAMPIE RTC_TAFCR_TAMPIE_Msk
AnnaBridge 171:3a7713b1edbc 3866 #define RTC_TAFCR_TAMP1TRG_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3867 #define RTC_TAFCR_TAMP1TRG_Msk (0x1U << RTC_TAFCR_TAMP1TRG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3868 #define RTC_TAFCR_TAMP1TRG RTC_TAFCR_TAMP1TRG_Msk
AnnaBridge 171:3a7713b1edbc 3869 #define RTC_TAFCR_TAMP1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3870 #define RTC_TAFCR_TAMP1E_Msk (0x1U << RTC_TAFCR_TAMP1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3871 #define RTC_TAFCR_TAMP1E RTC_TAFCR_TAMP1E_Msk
AnnaBridge 171:3a7713b1edbc 3872
AnnaBridge 171:3a7713b1edbc 3873 /* Reference defines */
AnnaBridge 171:3a7713b1edbc 3874 #define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
AnnaBridge 171:3a7713b1edbc 3875
AnnaBridge 171:3a7713b1edbc 3876 /******************** Bits definition for RTC_ALRMASSR register ************/
AnnaBridge 171:3a7713b1edbc 3877 #define RTC_ALRMASSR_MASKSS_Pos (24U)
AnnaBridge 171:3a7713b1edbc 3878 #define RTC_ALRMASSR_MASKSS_Msk (0xFU << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
AnnaBridge 171:3a7713b1edbc 3879 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
AnnaBridge 171:3a7713b1edbc 3880 #define RTC_ALRMASSR_MASKSS_0 (0x1U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 3881 #define RTC_ALRMASSR_MASKSS_1 (0x2U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 3882 #define RTC_ALRMASSR_MASKSS_2 (0x4U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 3883 #define RTC_ALRMASSR_MASKSS_3 (0x8U << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 3884 #define RTC_ALRMASSR_SS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3885 #define RTC_ALRMASSR_SS_Msk (0x7FFFU << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
AnnaBridge 171:3a7713b1edbc 3886 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
AnnaBridge 171:3a7713b1edbc 3887
AnnaBridge 171:3a7713b1edbc 3888 /******************** Bits definition for RTC_BKP0R register ***************/
AnnaBridge 171:3a7713b1edbc 3889 #define RTC_BKP0R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3890 #define RTC_BKP0R_Msk (0xFFFFFFFFU << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3891 #define RTC_BKP0R RTC_BKP0R_Msk
AnnaBridge 171:3a7713b1edbc 3892
AnnaBridge 171:3a7713b1edbc 3893 /******************** Bits definition for RTC_BKP1R register ***************/
AnnaBridge 171:3a7713b1edbc 3894 #define RTC_BKP1R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3895 #define RTC_BKP1R_Msk (0xFFFFFFFFU << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3896 #define RTC_BKP1R RTC_BKP1R_Msk
AnnaBridge 171:3a7713b1edbc 3897
AnnaBridge 171:3a7713b1edbc 3898 /******************** Bits definition for RTC_BKP2R register ***************/
AnnaBridge 171:3a7713b1edbc 3899 #define RTC_BKP2R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3900 #define RTC_BKP2R_Msk (0xFFFFFFFFU << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3901 #define RTC_BKP2R RTC_BKP2R_Msk
AnnaBridge 171:3a7713b1edbc 3902
AnnaBridge 171:3a7713b1edbc 3903 /******************** Bits definition for RTC_BKP3R register ***************/
AnnaBridge 171:3a7713b1edbc 3904 #define RTC_BKP3R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3905 #define RTC_BKP3R_Msk (0xFFFFFFFFU << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3906 #define RTC_BKP3R RTC_BKP3R_Msk
AnnaBridge 171:3a7713b1edbc 3907
AnnaBridge 171:3a7713b1edbc 3908 /******************** Bits definition for RTC_BKP4R register ***************/
AnnaBridge 171:3a7713b1edbc 3909 #define RTC_BKP4R_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3910 #define RTC_BKP4R_Msk (0xFFFFFFFFU << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 3911 #define RTC_BKP4R RTC_BKP4R_Msk
AnnaBridge 171:3a7713b1edbc 3912
AnnaBridge 171:3a7713b1edbc 3913 /******************** Number of backup registers ******************************/
AnnaBridge 171:3a7713b1edbc 3914 #define RTC_BKP_NUMBER 0x00000005U
AnnaBridge 171:3a7713b1edbc 3915
AnnaBridge 171:3a7713b1edbc 3916 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3917 /* */
AnnaBridge 171:3a7713b1edbc 3918 /* Serial Peripheral Interface (SPI) */
AnnaBridge 171:3a7713b1edbc 3919 /* */
AnnaBridge 171:3a7713b1edbc 3920 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3921
AnnaBridge 171:3a7713b1edbc 3922 /*
AnnaBridge 171:3a7713b1edbc 3923 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 3924 */
AnnaBridge 171:3a7713b1edbc 3925 #define SPI_I2S_SUPPORT /*!< I2S support */
AnnaBridge 171:3a7713b1edbc 3926
AnnaBridge 171:3a7713b1edbc 3927 /******************* Bit definition for SPI_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 3928 #define SPI_CR1_CPHA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3929 #define SPI_CR1_CPHA_Msk (0x1U << SPI_CR1_CPHA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3930 #define SPI_CR1_CPHA SPI_CR1_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 3931 #define SPI_CR1_CPOL_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3932 #define SPI_CR1_CPOL_Msk (0x1U << SPI_CR1_CPOL_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3933 #define SPI_CR1_CPOL SPI_CR1_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 3934 #define SPI_CR1_MSTR_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3935 #define SPI_CR1_MSTR_Msk (0x1U << SPI_CR1_MSTR_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3936 #define SPI_CR1_MSTR SPI_CR1_MSTR_Msk /*!< Master Selection */
AnnaBridge 171:3a7713b1edbc 3937 #define SPI_CR1_BR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3938 #define SPI_CR1_BR_Msk (0x7U << SPI_CR1_BR_Pos) /*!< 0x00000038 */
AnnaBridge 171:3a7713b1edbc 3939 #define SPI_CR1_BR SPI_CR1_BR_Msk /*!< BR[2:0] bits (Baud Rate Control) */
AnnaBridge 171:3a7713b1edbc 3940 #define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3941 #define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3942 #define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3943 #define SPI_CR1_SPE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3944 #define SPI_CR1_SPE_Msk (0x1U << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3945 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!< SPI Enable */
AnnaBridge 171:3a7713b1edbc 3946 #define SPI_CR1_LSBFIRST_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3947 #define SPI_CR1_LSBFIRST_Msk (0x1U << SPI_CR1_LSBFIRST_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3948 #define SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk /*!< Frame Format */
AnnaBridge 171:3a7713b1edbc 3949 #define SPI_CR1_SSI_Pos (8U)
AnnaBridge 171:3a7713b1edbc 3950 #define SPI_CR1_SSI_Msk (0x1U << SPI_CR1_SSI_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 3951 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!< Internal slave select */
AnnaBridge 171:3a7713b1edbc 3952 #define SPI_CR1_SSM_Pos (9U)
AnnaBridge 171:3a7713b1edbc 3953 #define SPI_CR1_SSM_Msk (0x1U << SPI_CR1_SSM_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 3954 #define SPI_CR1_SSM SPI_CR1_SSM_Msk /*!< Software slave management */
AnnaBridge 171:3a7713b1edbc 3955 #define SPI_CR1_RXONLY_Pos (10U)
AnnaBridge 171:3a7713b1edbc 3956 #define SPI_CR1_RXONLY_Msk (0x1U << SPI_CR1_RXONLY_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 3957 #define SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk /*!< Receive only */
AnnaBridge 171:3a7713b1edbc 3958 #define SPI_CR1_CRCL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 3959 #define SPI_CR1_CRCL_Msk (0x1U << SPI_CR1_CRCL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 3960 #define SPI_CR1_CRCL SPI_CR1_CRCL_Msk /*!< CRC Length */
AnnaBridge 171:3a7713b1edbc 3961 #define SPI_CR1_CRCNEXT_Pos (12U)
AnnaBridge 171:3a7713b1edbc 3962 #define SPI_CR1_CRCNEXT_Msk (0x1U << SPI_CR1_CRCNEXT_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 3963 #define SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk /*!< Transmit CRC next */
AnnaBridge 171:3a7713b1edbc 3964 #define SPI_CR1_CRCEN_Pos (13U)
AnnaBridge 171:3a7713b1edbc 3965 #define SPI_CR1_CRCEN_Msk (0x1U << SPI_CR1_CRCEN_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 3966 #define SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk /*!< Hardware CRC calculation enable */
AnnaBridge 171:3a7713b1edbc 3967 #define SPI_CR1_BIDIOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 3968 #define SPI_CR1_BIDIOE_Msk (0x1U << SPI_CR1_BIDIOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 3969 #define SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk /*!< Output enable in bidirectional mode */
AnnaBridge 171:3a7713b1edbc 3970 #define SPI_CR1_BIDIMODE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 3971 #define SPI_CR1_BIDIMODE_Msk (0x1U << SPI_CR1_BIDIMODE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 3972 #define SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk /*!< Bidirectional data mode enable */
AnnaBridge 171:3a7713b1edbc 3973
AnnaBridge 171:3a7713b1edbc 3974 /******************* Bit definition for SPI_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 3975 #define SPI_CR2_RXDMAEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 3976 #define SPI_CR2_RXDMAEN_Msk (0x1U << SPI_CR2_RXDMAEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 3977 #define SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk /*!< Rx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 3978 #define SPI_CR2_TXDMAEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 3979 #define SPI_CR2_TXDMAEN_Msk (0x1U << SPI_CR2_TXDMAEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 3980 #define SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk /*!< Tx Buffer DMA Enable */
AnnaBridge 171:3a7713b1edbc 3981 #define SPI_CR2_SSOE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 3982 #define SPI_CR2_SSOE_Msk (0x1U << SPI_CR2_SSOE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 3983 #define SPI_CR2_SSOE SPI_CR2_SSOE_Msk /*!< SS Output Enable */
AnnaBridge 171:3a7713b1edbc 3984 #define SPI_CR2_NSSP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 3985 #define SPI_CR2_NSSP_Msk (0x1U << SPI_CR2_NSSP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 3986 #define SPI_CR2_NSSP SPI_CR2_NSSP_Msk /*!< NSS pulse management Enable */
AnnaBridge 171:3a7713b1edbc 3987 #define SPI_CR2_FRF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 3988 #define SPI_CR2_FRF_Msk (0x1U << SPI_CR2_FRF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 3989 #define SPI_CR2_FRF SPI_CR2_FRF_Msk /*!< Frame Format Enable */
AnnaBridge 171:3a7713b1edbc 3990 #define SPI_CR2_ERRIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 3991 #define SPI_CR2_ERRIE_Msk (0x1U << SPI_CR2_ERRIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 3992 #define SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3993 #define SPI_CR2_RXNEIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 3994 #define SPI_CR2_RXNEIE_Msk (0x1U << SPI_CR2_RXNEIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 3995 #define SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk /*!< RX buffer Not Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3996 #define SPI_CR2_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 3997 #define SPI_CR2_TXEIE_Msk (0x1U << SPI_CR2_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 3998 #define SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk /*!< Tx buffer Empty Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 3999 #define SPI_CR2_DS_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4000 #define SPI_CR2_DS_Msk (0xFU << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4001 #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
AnnaBridge 171:3a7713b1edbc 4002 #define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4003 #define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4004 #define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4005 #define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4006 #define SPI_CR2_FRXTH_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4007 #define SPI_CR2_FRXTH_Msk (0x1U << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4008 #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
AnnaBridge 171:3a7713b1edbc 4009 #define SPI_CR2_LDMARX_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4010 #define SPI_CR2_LDMARX_Msk (0x1U << SPI_CR2_LDMARX_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4011 #define SPI_CR2_LDMARX SPI_CR2_LDMARX_Msk /*!< Last DMA transfer for reception */
AnnaBridge 171:3a7713b1edbc 4012 #define SPI_CR2_LDMATX_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4013 #define SPI_CR2_LDMATX_Msk (0x1U << SPI_CR2_LDMATX_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4014 #define SPI_CR2_LDMATX SPI_CR2_LDMATX_Msk /*!< Last DMA transfer for transmission */
AnnaBridge 171:3a7713b1edbc 4015
AnnaBridge 171:3a7713b1edbc 4016 /******************** Bit definition for SPI_SR register *******************/
AnnaBridge 171:3a7713b1edbc 4017 #define SPI_SR_RXNE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4018 #define SPI_SR_RXNE_Msk (0x1U << SPI_SR_RXNE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4019 #define SPI_SR_RXNE SPI_SR_RXNE_Msk /*!< Receive buffer Not Empty */
AnnaBridge 171:3a7713b1edbc 4020 #define SPI_SR_TXE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4021 #define SPI_SR_TXE_Msk (0x1U << SPI_SR_TXE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4022 #define SPI_SR_TXE SPI_SR_TXE_Msk /*!< Transmit buffer Empty */
AnnaBridge 171:3a7713b1edbc 4023 #define SPI_SR_CHSIDE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4024 #define SPI_SR_CHSIDE_Msk (0x1U << SPI_SR_CHSIDE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4025 #define SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk /*!< Channel side */
AnnaBridge 171:3a7713b1edbc 4026 #define SPI_SR_UDR_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4027 #define SPI_SR_UDR_Msk (0x1U << SPI_SR_UDR_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4028 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!< Underrun flag */
AnnaBridge 171:3a7713b1edbc 4029 #define SPI_SR_CRCERR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4030 #define SPI_SR_CRCERR_Msk (0x1U << SPI_SR_CRCERR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4031 #define SPI_SR_CRCERR SPI_SR_CRCERR_Msk /*!< CRC Error flag */
AnnaBridge 171:3a7713b1edbc 4032 #define SPI_SR_MODF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4033 #define SPI_SR_MODF_Msk (0x1U << SPI_SR_MODF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4034 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!< Mode fault */
AnnaBridge 171:3a7713b1edbc 4035 #define SPI_SR_OVR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4036 #define SPI_SR_OVR_Msk (0x1U << SPI_SR_OVR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4037 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!< Overrun flag */
AnnaBridge 171:3a7713b1edbc 4038 #define SPI_SR_BSY_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4039 #define SPI_SR_BSY_Msk (0x1U << SPI_SR_BSY_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4040 #define SPI_SR_BSY SPI_SR_BSY_Msk /*!< Busy flag */
AnnaBridge 171:3a7713b1edbc 4041 #define SPI_SR_FRE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4042 #define SPI_SR_FRE_Msk (0x1U << SPI_SR_FRE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4043 #define SPI_SR_FRE SPI_SR_FRE_Msk /*!< TI frame format error */
AnnaBridge 171:3a7713b1edbc 4044 #define SPI_SR_FRLVL_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4045 #define SPI_SR_FRLVL_Msk (0x3U << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
AnnaBridge 171:3a7713b1edbc 4046 #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
AnnaBridge 171:3a7713b1edbc 4047 #define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4048 #define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4049 #define SPI_SR_FTLVL_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4050 #define SPI_SR_FTLVL_Msk (0x3U << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
AnnaBridge 171:3a7713b1edbc 4051 #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
AnnaBridge 171:3a7713b1edbc 4052 #define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4053 #define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4054
AnnaBridge 171:3a7713b1edbc 4055 /******************** Bit definition for SPI_DR register *******************/
AnnaBridge 171:3a7713b1edbc 4056 #define SPI_DR_DR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4057 #define SPI_DR_DR_Msk (0xFFFFFFFFU << SPI_DR_DR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4058 #define SPI_DR_DR SPI_DR_DR_Msk /*!< Data Register */
AnnaBridge 171:3a7713b1edbc 4059
AnnaBridge 171:3a7713b1edbc 4060 /******************* Bit definition for SPI_CRCPR register *****************/
AnnaBridge 171:3a7713b1edbc 4061 #define SPI_CRCPR_CRCPOLY_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4062 #define SPI_CRCPR_CRCPOLY_Msk (0xFFFFFFFFU << SPI_CRCPR_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4063 #define SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk /*!< CRC polynomial register */
AnnaBridge 171:3a7713b1edbc 4064
AnnaBridge 171:3a7713b1edbc 4065 /****************** Bit definition for SPI_RXCRCR register *****************/
AnnaBridge 171:3a7713b1edbc 4066 #define SPI_RXCRCR_RXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4067 #define SPI_RXCRCR_RXCRC_Msk (0xFFFFFFFFU << SPI_RXCRCR_RXCRC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4068 #define SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk /*!< Rx CRC Register */
AnnaBridge 171:3a7713b1edbc 4069
AnnaBridge 171:3a7713b1edbc 4070 /****************** Bit definition for SPI_TXCRCR register *****************/
AnnaBridge 171:3a7713b1edbc 4071 #define SPI_TXCRCR_TXCRC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4072 #define SPI_TXCRCR_TXCRC_Msk (0xFFFFFFFFU << SPI_TXCRCR_TXCRC_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4073 #define SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk /*!< Tx CRC Register */
AnnaBridge 171:3a7713b1edbc 4074
AnnaBridge 171:3a7713b1edbc 4075 /****************** Bit definition for SPI_I2SCFGR register ****************/
AnnaBridge 171:3a7713b1edbc 4076 #define SPI_I2SCFGR_CHLEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4077 #define SPI_I2SCFGR_CHLEN_Msk (0x1U << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4078 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
AnnaBridge 171:3a7713b1edbc 4079 #define SPI_I2SCFGR_DATLEN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4080 #define SPI_I2SCFGR_DATLEN_Msk (0x3U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000006 */
AnnaBridge 171:3a7713b1edbc 4081 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] bits (Data length to be transferred) */
AnnaBridge 171:3a7713b1edbc 4082 #define SPI_I2SCFGR_DATLEN_0 (0x1U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4083 #define SPI_I2SCFGR_DATLEN_1 (0x2U << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4084 #define SPI_I2SCFGR_CKPOL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4085 #define SPI_I2SCFGR_CKPOL_Msk (0x1U << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4086 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<steady state clock polarity */
AnnaBridge 171:3a7713b1edbc 4087 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4088 #define SPI_I2SCFGR_I2SSTD_Msk (0x3U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
AnnaBridge 171:3a7713b1edbc 4089 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] bits (I2S standard selection) */
AnnaBridge 171:3a7713b1edbc 4090 #define SPI_I2SCFGR_I2SSTD_0 (0x1U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4091 #define SPI_I2SCFGR_I2SSTD_1 (0x2U << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4092 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4093 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1U << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4094 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
AnnaBridge 171:3a7713b1edbc 4095 #define SPI_I2SCFGR_I2SCFG_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4096 #define SPI_I2SCFGR_I2SCFG_Msk (0x3U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 4097 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[1:0] bits (I2S configuration mode) */
AnnaBridge 171:3a7713b1edbc 4098 #define SPI_I2SCFGR_I2SCFG_0 (0x1U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4099 #define SPI_I2SCFGR_I2SCFG_1 (0x2U << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4100 #define SPI_I2SCFGR_I2SE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4101 #define SPI_I2SCFGR_I2SE_Msk (0x1U << SPI_I2SCFGR_I2SE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4102 #define SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk /*!<I2S Enable */
AnnaBridge 171:3a7713b1edbc 4103 #define SPI_I2SCFGR_I2SMOD_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4104 #define SPI_I2SCFGR_I2SMOD_Msk (0x1U << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4105 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
AnnaBridge 171:3a7713b1edbc 4106
AnnaBridge 171:3a7713b1edbc 4107 /****************** Bit definition for SPI_I2SPR register ******************/
AnnaBridge 171:3a7713b1edbc 4108 #define SPI_I2SPR_I2SDIV_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4109 #define SPI_I2SPR_I2SDIV_Msk (0xFFU << SPI_I2SPR_I2SDIV_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4110 #define SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk /*!<I2S Linear prescaler */
AnnaBridge 171:3a7713b1edbc 4111 #define SPI_I2SPR_ODD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4112 #define SPI_I2SPR_ODD_Msk (0x1U << SPI_I2SPR_ODD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4113 #define SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk /*!<Odd factor for the prescaler */
AnnaBridge 171:3a7713b1edbc 4114 #define SPI_I2SPR_MCKOE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4115 #define SPI_I2SPR_MCKOE_Msk (0x1U << SPI_I2SPR_MCKOE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4116 #define SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk /*!<Master Clock Output Enable */
AnnaBridge 171:3a7713b1edbc 4117
AnnaBridge 171:3a7713b1edbc 4118 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 4119 /* */
AnnaBridge 171:3a7713b1edbc 4120 /* System Configuration (SYSCFG) */
AnnaBridge 171:3a7713b1edbc 4121 /* */
AnnaBridge 171:3a7713b1edbc 4122 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 4123 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
AnnaBridge 171:3a7713b1edbc 4124 #define SYSCFG_CFGR1_MEM_MODE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4125 #define SYSCFG_CFGR1_MEM_MODE_Msk (0x3U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 4126 #define SYSCFG_CFGR1_MEM_MODE SYSCFG_CFGR1_MEM_MODE_Msk /*!< SYSCFG_Memory Remap Config */
AnnaBridge 171:3a7713b1edbc 4127 #define SYSCFG_CFGR1_MEM_MODE_0 (0x1U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4128 #define SYSCFG_CFGR1_MEM_MODE_1 (0x2U << SYSCFG_CFGR1_MEM_MODE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4129
AnnaBridge 171:3a7713b1edbc 4130 #define SYSCFG_CFGR1_DMA_RMP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4131 #define SYSCFG_CFGR1_DMA_RMP_Msk (0x1FU << SYSCFG_CFGR1_DMA_RMP_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 4132 #define SYSCFG_CFGR1_DMA_RMP SYSCFG_CFGR1_DMA_RMP_Msk /*!< DMA remap mask */
AnnaBridge 171:3a7713b1edbc 4133 #define SYSCFG_CFGR1_ADC_DMA_RMP_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4134 #define SYSCFG_CFGR1_ADC_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_ADC_DMA_RMP_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4135 #define SYSCFG_CFGR1_ADC_DMA_RMP SYSCFG_CFGR1_ADC_DMA_RMP_Msk /*!< ADC DMA remap */
AnnaBridge 171:3a7713b1edbc 4136 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4137 #define SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1TX_DMA_RMP_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4138 #define SYSCFG_CFGR1_USART1TX_DMA_RMP SYSCFG_CFGR1_USART1TX_DMA_RMP_Msk /*!< USART1 TX DMA remap */
AnnaBridge 171:3a7713b1edbc 4139 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4140 #define SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_USART1RX_DMA_RMP_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4141 #define SYSCFG_CFGR1_USART1RX_DMA_RMP SYSCFG_CFGR1_USART1RX_DMA_RMP_Msk /*!< USART1 RX DMA remap */
AnnaBridge 171:3a7713b1edbc 4142 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4143 #define SYSCFG_CFGR1_TIM16_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM16_DMA_RMP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4144 #define SYSCFG_CFGR1_TIM16_DMA_RMP SYSCFG_CFGR1_TIM16_DMA_RMP_Msk /*!< Timer 16 DMA remap */
AnnaBridge 171:3a7713b1edbc 4145 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4146 #define SYSCFG_CFGR1_TIM17_DMA_RMP_Msk (0x1U << SYSCFG_CFGR1_TIM17_DMA_RMP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4147 #define SYSCFG_CFGR1_TIM17_DMA_RMP SYSCFG_CFGR1_TIM17_DMA_RMP_Msk /*!< Timer 17 DMA remap */
AnnaBridge 171:3a7713b1edbc 4148
AnnaBridge 171:3a7713b1edbc 4149 #define SYSCFG_CFGR1_I2C_FMP_PB6_Pos (16U)
AnnaBridge 171:3a7713b1edbc 4150 #define SYSCFG_CFGR1_I2C_FMP_PB6_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB6_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 4151 #define SYSCFG_CFGR1_I2C_FMP_PB6 SYSCFG_CFGR1_I2C_FMP_PB6_Msk /*!< I2C PB6 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 4152 #define SYSCFG_CFGR1_I2C_FMP_PB7_Pos (17U)
AnnaBridge 171:3a7713b1edbc 4153 #define SYSCFG_CFGR1_I2C_FMP_PB7_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB7_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 4154 #define SYSCFG_CFGR1_I2C_FMP_PB7 SYSCFG_CFGR1_I2C_FMP_PB7_Msk /*!< I2C PB7 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 4155 #define SYSCFG_CFGR1_I2C_FMP_PB8_Pos (18U)
AnnaBridge 171:3a7713b1edbc 4156 #define SYSCFG_CFGR1_I2C_FMP_PB8_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB8_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 4157 #define SYSCFG_CFGR1_I2C_FMP_PB8 SYSCFG_CFGR1_I2C_FMP_PB8_Msk /*!< I2C PB8 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 4158 #define SYSCFG_CFGR1_I2C_FMP_PB9_Pos (19U)
AnnaBridge 171:3a7713b1edbc 4159 #define SYSCFG_CFGR1_I2C_FMP_PB9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PB9_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 4160 #define SYSCFG_CFGR1_I2C_FMP_PB9 SYSCFG_CFGR1_I2C_FMP_PB9_Msk /*!< I2C PB9 Fast mode plus */
AnnaBridge 171:3a7713b1edbc 4161 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Pos (20U)
AnnaBridge 171:3a7713b1edbc 4162 #define SYSCFG_CFGR1_I2C_FMP_I2C1_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_I2C1_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 4163 #define SYSCFG_CFGR1_I2C_FMP_I2C1 SYSCFG_CFGR1_I2C_FMP_I2C1_Msk /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
AnnaBridge 171:3a7713b1edbc 4164 #define SYSCFG_CFGR1_I2C_FMP_PA9_Pos (22U)
AnnaBridge 171:3a7713b1edbc 4165 #define SYSCFG_CFGR1_I2C_FMP_PA9_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PA9_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 4166 #define SYSCFG_CFGR1_I2C_FMP_PA9 SYSCFG_CFGR1_I2C_FMP_PA9_Msk /*!< Enable Fast Mode Plus on PA9 */
AnnaBridge 171:3a7713b1edbc 4167 #define SYSCFG_CFGR1_I2C_FMP_PA10_Pos (23U)
AnnaBridge 171:3a7713b1edbc 4168 #define SYSCFG_CFGR1_I2C_FMP_PA10_Msk (0x1U << SYSCFG_CFGR1_I2C_FMP_PA10_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 4169 #define SYSCFG_CFGR1_I2C_FMP_PA10 SYSCFG_CFGR1_I2C_FMP_PA10_Msk /*!< Enable Fast Mode Plus on PA10 */
AnnaBridge 171:3a7713b1edbc 4170
AnnaBridge 171:3a7713b1edbc 4171 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
AnnaBridge 171:3a7713b1edbc 4172 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4173 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFU << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4174 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!< EXTI 0 configuration */
AnnaBridge 171:3a7713b1edbc 4175 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4176 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFU << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4177 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!< EXTI 1 configuration */
AnnaBridge 171:3a7713b1edbc 4178 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4179 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFU << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4180 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!< EXTI 2 configuration */
AnnaBridge 171:3a7713b1edbc 4181 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4182 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFU << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 4183 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!< EXTI 3 configuration */
AnnaBridge 171:3a7713b1edbc 4184
AnnaBridge 171:3a7713b1edbc 4185 /**
AnnaBridge 171:3a7713b1edbc 4186 * @brief EXTI0 configuration
AnnaBridge 171:3a7713b1edbc 4187 */
AnnaBridge 171:3a7713b1edbc 4188 #define SYSCFG_EXTICR1_EXTI0_PA (0x00000000U) /*!< PA[0] pin */
AnnaBridge 171:3a7713b1edbc 4189 #define SYSCFG_EXTICR1_EXTI0_PB (0x00000001U) /*!< PB[0] pin */
AnnaBridge 171:3a7713b1edbc 4190 #define SYSCFG_EXTICR1_EXTI0_PC (0x00000002U) /*!< PC[0] pin */
AnnaBridge 171:3a7713b1edbc 4191 #define SYSCFG_EXTICR1_EXTI0_PD (0x00000003U) /*!< PD[0] pin */
AnnaBridge 171:3a7713b1edbc 4192 #define SYSCFG_EXTICR1_EXTI0_PF (0x00000005U) /*!< PF[0] pin */
AnnaBridge 171:3a7713b1edbc 4193
AnnaBridge 171:3a7713b1edbc 4194 /**
AnnaBridge 171:3a7713b1edbc 4195 * @brief EXTI1 configuration
AnnaBridge 171:3a7713b1edbc 4196 */
AnnaBridge 171:3a7713b1edbc 4197 #define SYSCFG_EXTICR1_EXTI1_PA (0x00000000U) /*!< PA[1] pin */
AnnaBridge 171:3a7713b1edbc 4198 #define SYSCFG_EXTICR1_EXTI1_PB (0x00000010U) /*!< PB[1] pin */
AnnaBridge 171:3a7713b1edbc 4199 #define SYSCFG_EXTICR1_EXTI1_PC (0x00000020U) /*!< PC[1] pin */
AnnaBridge 171:3a7713b1edbc 4200 #define SYSCFG_EXTICR1_EXTI1_PD (0x00000030U) /*!< PD[1] pin */
AnnaBridge 171:3a7713b1edbc 4201 #define SYSCFG_EXTICR1_EXTI1_PF (0x00000050U) /*!< PF[1] pin */
AnnaBridge 171:3a7713b1edbc 4202
AnnaBridge 171:3a7713b1edbc 4203 /**
AnnaBridge 171:3a7713b1edbc 4204 * @brief EXTI2 configuration
AnnaBridge 171:3a7713b1edbc 4205 */
AnnaBridge 171:3a7713b1edbc 4206 #define SYSCFG_EXTICR1_EXTI2_PA (0x00000000U) /*!< PA[2] pin */
AnnaBridge 171:3a7713b1edbc 4207 #define SYSCFG_EXTICR1_EXTI2_PB (0x00000100U) /*!< PB[2] pin */
AnnaBridge 171:3a7713b1edbc 4208 #define SYSCFG_EXTICR1_EXTI2_PC (0x00000200U) /*!< PC[2] pin */
AnnaBridge 171:3a7713b1edbc 4209 #define SYSCFG_EXTICR1_EXTI2_PD (0x00000300U) /*!< PD[2] pin */
AnnaBridge 171:3a7713b1edbc 4210 #define SYSCFG_EXTICR1_EXTI2_PF (0x00000500U) /*!< PF[2] pin */
AnnaBridge 171:3a7713b1edbc 4211
AnnaBridge 171:3a7713b1edbc 4212 /**
AnnaBridge 171:3a7713b1edbc 4213 * @brief EXTI3 configuration
AnnaBridge 171:3a7713b1edbc 4214 */
AnnaBridge 171:3a7713b1edbc 4215 #define SYSCFG_EXTICR1_EXTI3_PA (0x00000000U) /*!< PA[3] pin */
AnnaBridge 171:3a7713b1edbc 4216 #define SYSCFG_EXTICR1_EXTI3_PB (0x00001000U) /*!< PB[3] pin */
AnnaBridge 171:3a7713b1edbc 4217 #define SYSCFG_EXTICR1_EXTI3_PC (0x00002000U) /*!< PC[3] pin */
AnnaBridge 171:3a7713b1edbc 4218 #define SYSCFG_EXTICR1_EXTI3_PD (0x00003000U) /*!< PD[3] pin */
AnnaBridge 171:3a7713b1edbc 4219 #define SYSCFG_EXTICR1_EXTI3_PF (0x00005000U) /*!< PF[3] pin */
AnnaBridge 171:3a7713b1edbc 4220
AnnaBridge 171:3a7713b1edbc 4221 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
AnnaBridge 171:3a7713b1edbc 4222 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4223 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFU << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4224 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!< EXTI 4 configuration */
AnnaBridge 171:3a7713b1edbc 4225 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4226 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFU << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4227 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!< EXTI 5 configuration */
AnnaBridge 171:3a7713b1edbc 4228 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4229 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFU << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4230 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!< EXTI 6 configuration */
AnnaBridge 171:3a7713b1edbc 4231 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4232 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFU << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 4233 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!< EXTI 7 configuration */
AnnaBridge 171:3a7713b1edbc 4234
AnnaBridge 171:3a7713b1edbc 4235 /**
AnnaBridge 171:3a7713b1edbc 4236 * @brief EXTI4 configuration
AnnaBridge 171:3a7713b1edbc 4237 */
AnnaBridge 171:3a7713b1edbc 4238 #define SYSCFG_EXTICR2_EXTI4_PA (0x00000000U) /*!< PA[4] pin */
AnnaBridge 171:3a7713b1edbc 4239 #define SYSCFG_EXTICR2_EXTI4_PB (0x00000001U) /*!< PB[4] pin */
AnnaBridge 171:3a7713b1edbc 4240 #define SYSCFG_EXTICR2_EXTI4_PC (0x00000002U) /*!< PC[4] pin */
AnnaBridge 171:3a7713b1edbc 4241 #define SYSCFG_EXTICR2_EXTI4_PD (0x00000003U) /*!< PD[4] pin */
AnnaBridge 171:3a7713b1edbc 4242 #define SYSCFG_EXTICR2_EXTI4_PF (0x00000005U) /*!< PF[4] pin */
AnnaBridge 171:3a7713b1edbc 4243
AnnaBridge 171:3a7713b1edbc 4244 /**
AnnaBridge 171:3a7713b1edbc 4245 * @brief EXTI5 configuration
AnnaBridge 171:3a7713b1edbc 4246 */
AnnaBridge 171:3a7713b1edbc 4247 #define SYSCFG_EXTICR2_EXTI5_PA (0x00000000U) /*!< PA[5] pin */
AnnaBridge 171:3a7713b1edbc 4248 #define SYSCFG_EXTICR2_EXTI5_PB (0x00000010U) /*!< PB[5] pin */
AnnaBridge 171:3a7713b1edbc 4249 #define SYSCFG_EXTICR2_EXTI5_PC (0x00000020U) /*!< PC[5] pin */
AnnaBridge 171:3a7713b1edbc 4250 #define SYSCFG_EXTICR2_EXTI5_PD (0x00000030U) /*!< PD[5] pin */
AnnaBridge 171:3a7713b1edbc 4251 #define SYSCFG_EXTICR2_EXTI5_PF (0x00000050U) /*!< PF[5] pin */
AnnaBridge 171:3a7713b1edbc 4252
AnnaBridge 171:3a7713b1edbc 4253 /**
AnnaBridge 171:3a7713b1edbc 4254 * @brief EXTI6 configuration
AnnaBridge 171:3a7713b1edbc 4255 */
AnnaBridge 171:3a7713b1edbc 4256 #define SYSCFG_EXTICR2_EXTI6_PA (0x00000000U) /*!< PA[6] pin */
AnnaBridge 171:3a7713b1edbc 4257 #define SYSCFG_EXTICR2_EXTI6_PB (0x00000100U) /*!< PB[6] pin */
AnnaBridge 171:3a7713b1edbc 4258 #define SYSCFG_EXTICR2_EXTI6_PC (0x00000200U) /*!< PC[6] pin */
AnnaBridge 171:3a7713b1edbc 4259 #define SYSCFG_EXTICR2_EXTI6_PD (0x00000300U) /*!< PD[6] pin */
AnnaBridge 171:3a7713b1edbc 4260 #define SYSCFG_EXTICR2_EXTI6_PF (0x00000500U) /*!< PF[6] pin */
AnnaBridge 171:3a7713b1edbc 4261
AnnaBridge 171:3a7713b1edbc 4262 /**
AnnaBridge 171:3a7713b1edbc 4263 * @brief EXTI7 configuration
AnnaBridge 171:3a7713b1edbc 4264 */
AnnaBridge 171:3a7713b1edbc 4265 #define SYSCFG_EXTICR2_EXTI7_PA (0x00000000U) /*!< PA[7] pin */
AnnaBridge 171:3a7713b1edbc 4266 #define SYSCFG_EXTICR2_EXTI7_PB (0x00001000U) /*!< PB[7] pin */
AnnaBridge 171:3a7713b1edbc 4267 #define SYSCFG_EXTICR2_EXTI7_PC (0x00002000U) /*!< PC[7] pin */
AnnaBridge 171:3a7713b1edbc 4268 #define SYSCFG_EXTICR2_EXTI7_PD (0x00003000U) /*!< PD[7] pin */
AnnaBridge 171:3a7713b1edbc 4269 #define SYSCFG_EXTICR2_EXTI7_PF (0x00005000U) /*!< PF[7] pin */
AnnaBridge 171:3a7713b1edbc 4270
AnnaBridge 171:3a7713b1edbc 4271 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
AnnaBridge 171:3a7713b1edbc 4272 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4273 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFU << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4274 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!< EXTI 8 configuration */
AnnaBridge 171:3a7713b1edbc 4275 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4276 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFU << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4277 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!< EXTI 9 configuration */
AnnaBridge 171:3a7713b1edbc 4278 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4279 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFU << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4280 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!< EXTI 10 configuration */
AnnaBridge 171:3a7713b1edbc 4281 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4282 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFU << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 4283 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!< EXTI 11 configuration */
AnnaBridge 171:3a7713b1edbc 4284
AnnaBridge 171:3a7713b1edbc 4285 /**
AnnaBridge 171:3a7713b1edbc 4286 * @brief EXTI8 configuration
AnnaBridge 171:3a7713b1edbc 4287 */
AnnaBridge 171:3a7713b1edbc 4288 #define SYSCFG_EXTICR3_EXTI8_PA (0x00000000U) /*!< PA[8] pin */
AnnaBridge 171:3a7713b1edbc 4289 #define SYSCFG_EXTICR3_EXTI8_PB (0x00000001U) /*!< PB[8] pin */
AnnaBridge 171:3a7713b1edbc 4290 #define SYSCFG_EXTICR3_EXTI8_PC (0x00000002U) /*!< PC[8] pin */
AnnaBridge 171:3a7713b1edbc 4291 #define SYSCFG_EXTICR3_EXTI8_PD (0x00000003U) /*!< PD[8] pin */
AnnaBridge 171:3a7713b1edbc 4292 #define SYSCFG_EXTICR3_EXTI8_PF (0x00000005U) /*!< PF[8] pin */
AnnaBridge 171:3a7713b1edbc 4293
AnnaBridge 171:3a7713b1edbc 4294
AnnaBridge 171:3a7713b1edbc 4295 /**
AnnaBridge 171:3a7713b1edbc 4296 * @brief EXTI9 configuration
AnnaBridge 171:3a7713b1edbc 4297 */
AnnaBridge 171:3a7713b1edbc 4298 #define SYSCFG_EXTICR3_EXTI9_PA (0x00000000U) /*!< PA[9] pin */
AnnaBridge 171:3a7713b1edbc 4299 #define SYSCFG_EXTICR3_EXTI9_PB (0x00000010U) /*!< PB[9] pin */
AnnaBridge 171:3a7713b1edbc 4300 #define SYSCFG_EXTICR3_EXTI9_PC (0x00000020U) /*!< PC[9] pin */
AnnaBridge 171:3a7713b1edbc 4301 #define SYSCFG_EXTICR3_EXTI9_PD (0x00000030U) /*!< PD[9] pin */
AnnaBridge 171:3a7713b1edbc 4302 #define SYSCFG_EXTICR3_EXTI9_PF (0x00000050U) /*!< PF[9] pin */
AnnaBridge 171:3a7713b1edbc 4303
AnnaBridge 171:3a7713b1edbc 4304 /**
AnnaBridge 171:3a7713b1edbc 4305 * @brief EXTI10 configuration
AnnaBridge 171:3a7713b1edbc 4306 */
AnnaBridge 171:3a7713b1edbc 4307 #define SYSCFG_EXTICR3_EXTI10_PA (0x00000000U) /*!< PA[10] pin */
AnnaBridge 171:3a7713b1edbc 4308 #define SYSCFG_EXTICR3_EXTI10_PB (0x00000100U) /*!< PB[10] pin */
AnnaBridge 171:3a7713b1edbc 4309 #define SYSCFG_EXTICR3_EXTI10_PC (0x00000200U) /*!< PC[10] pin */
AnnaBridge 171:3a7713b1edbc 4310 #define SYSCFG_EXTICR3_EXTI10_PD (0x00000300U) /*!< PD[10] pin */
AnnaBridge 171:3a7713b1edbc 4311 #define SYSCFG_EXTICR3_EXTI10_PF (0x00000500U) /*!< PF[10] pin */
AnnaBridge 171:3a7713b1edbc 4312
AnnaBridge 171:3a7713b1edbc 4313 /**
AnnaBridge 171:3a7713b1edbc 4314 * @brief EXTI11 configuration
AnnaBridge 171:3a7713b1edbc 4315 */
AnnaBridge 171:3a7713b1edbc 4316 #define SYSCFG_EXTICR3_EXTI11_PA (0x00000000U) /*!< PA[11] pin */
AnnaBridge 171:3a7713b1edbc 4317 #define SYSCFG_EXTICR3_EXTI11_PB (0x00001000U) /*!< PB[11] pin */
AnnaBridge 171:3a7713b1edbc 4318 #define SYSCFG_EXTICR3_EXTI11_PC (0x00002000U) /*!< PC[11] pin */
AnnaBridge 171:3a7713b1edbc 4319 #define SYSCFG_EXTICR3_EXTI11_PD (0x00003000U) /*!< PD[11] pin */
AnnaBridge 171:3a7713b1edbc 4320 #define SYSCFG_EXTICR3_EXTI11_PF (0x00005000U) /*!< PF[11] pin */
AnnaBridge 171:3a7713b1edbc 4321
AnnaBridge 171:3a7713b1edbc 4322 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
AnnaBridge 171:3a7713b1edbc 4323 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4324 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFU << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 4325 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!< EXTI 12 configuration */
AnnaBridge 171:3a7713b1edbc 4326 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4327 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFU << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4328 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!< EXTI 13 configuration */
AnnaBridge 171:3a7713b1edbc 4329 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4330 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFU << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4331 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!< EXTI 14 configuration */
AnnaBridge 171:3a7713b1edbc 4332 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4333 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFU << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 4334 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!< EXTI 15 configuration */
AnnaBridge 171:3a7713b1edbc 4335
AnnaBridge 171:3a7713b1edbc 4336 /**
AnnaBridge 171:3a7713b1edbc 4337 * @brief EXTI12 configuration
AnnaBridge 171:3a7713b1edbc 4338 */
AnnaBridge 171:3a7713b1edbc 4339 #define SYSCFG_EXTICR4_EXTI12_PA (0x00000000U) /*!< PA[12] pin */
AnnaBridge 171:3a7713b1edbc 4340 #define SYSCFG_EXTICR4_EXTI12_PB (0x00000001U) /*!< PB[12] pin */
AnnaBridge 171:3a7713b1edbc 4341 #define SYSCFG_EXTICR4_EXTI12_PC (0x00000002U) /*!< PC[12] pin */
AnnaBridge 171:3a7713b1edbc 4342 #define SYSCFG_EXTICR4_EXTI12_PD (0x00000003U) /*!< PD[12] pin */
AnnaBridge 171:3a7713b1edbc 4343 #define SYSCFG_EXTICR4_EXTI12_PF (0x00000005U) /*!< PF[12] pin */
AnnaBridge 171:3a7713b1edbc 4344
AnnaBridge 171:3a7713b1edbc 4345 /**
AnnaBridge 171:3a7713b1edbc 4346 * @brief EXTI13 configuration
AnnaBridge 171:3a7713b1edbc 4347 */
AnnaBridge 171:3a7713b1edbc 4348 #define SYSCFG_EXTICR4_EXTI13_PA (0x00000000U) /*!< PA[13] pin */
AnnaBridge 171:3a7713b1edbc 4349 #define SYSCFG_EXTICR4_EXTI13_PB (0x00000010U) /*!< PB[13] pin */
AnnaBridge 171:3a7713b1edbc 4350 #define SYSCFG_EXTICR4_EXTI13_PC (0x00000020U) /*!< PC[13] pin */
AnnaBridge 171:3a7713b1edbc 4351 #define SYSCFG_EXTICR4_EXTI13_PD (0x00000030U) /*!< PD[13] pin */
AnnaBridge 171:3a7713b1edbc 4352 #define SYSCFG_EXTICR4_EXTI13_PF (0x00000050U) /*!< PF[13] pin */
AnnaBridge 171:3a7713b1edbc 4353
AnnaBridge 171:3a7713b1edbc 4354 /**
AnnaBridge 171:3a7713b1edbc 4355 * @brief EXTI14 configuration
AnnaBridge 171:3a7713b1edbc 4356 */
AnnaBridge 171:3a7713b1edbc 4357 #define SYSCFG_EXTICR4_EXTI14_PA (0x00000000U) /*!< PA[14] pin */
AnnaBridge 171:3a7713b1edbc 4358 #define SYSCFG_EXTICR4_EXTI14_PB (0x00000100U) /*!< PB[14] pin */
AnnaBridge 171:3a7713b1edbc 4359 #define SYSCFG_EXTICR4_EXTI14_PC (0x00000200U) /*!< PC[14] pin */
AnnaBridge 171:3a7713b1edbc 4360 #define SYSCFG_EXTICR4_EXTI14_PD (0x00000300U) /*!< PD[14] pin */
AnnaBridge 171:3a7713b1edbc 4361 #define SYSCFG_EXTICR4_EXTI14_PF (0x00000500U) /*!< PF[14] pin */
AnnaBridge 171:3a7713b1edbc 4362
AnnaBridge 171:3a7713b1edbc 4363 /**
AnnaBridge 171:3a7713b1edbc 4364 * @brief EXTI15 configuration
AnnaBridge 171:3a7713b1edbc 4365 */
AnnaBridge 171:3a7713b1edbc 4366 #define SYSCFG_EXTICR4_EXTI15_PA (0x00000000U) /*!< PA[15] pin */
AnnaBridge 171:3a7713b1edbc 4367 #define SYSCFG_EXTICR4_EXTI15_PB (0x00001000U) /*!< PB[15] pin */
AnnaBridge 171:3a7713b1edbc 4368 #define SYSCFG_EXTICR4_EXTI15_PC (0x00002000U) /*!< PC[15] pin */
AnnaBridge 171:3a7713b1edbc 4369 #define SYSCFG_EXTICR4_EXTI15_PD (0x00003000U) /*!< PD[15] pin */
AnnaBridge 171:3a7713b1edbc 4370 #define SYSCFG_EXTICR4_EXTI15_PF (0x00005000U) /*!< PF[15] pin */
AnnaBridge 171:3a7713b1edbc 4371
AnnaBridge 171:3a7713b1edbc 4372 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
AnnaBridge 171:3a7713b1edbc 4373 #define SYSCFG_CFGR2_LOCKUP_LOCK_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4374 #define SYSCFG_CFGR2_LOCKUP_LOCK_Msk (0x1U << SYSCFG_CFGR2_LOCKUP_LOCK_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4375 #define SYSCFG_CFGR2_LOCKUP_LOCK SYSCFG_CFGR2_LOCKUP_LOCK_Msk /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
AnnaBridge 171:3a7713b1edbc 4376 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4377 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk (0x1U << SYSCFG_CFGR2_SRAM_PARITY_LOCK_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4378 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK SYSCFG_CFGR2_SRAM_PARITY_LOCK_Msk /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
AnnaBridge 171:3a7713b1edbc 4379 #define SYSCFG_CFGR2_PVD_LOCK_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4380 #define SYSCFG_CFGR2_PVD_LOCK_Msk (0x1U << SYSCFG_CFGR2_PVD_LOCK_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4381 #define SYSCFG_CFGR2_PVD_LOCK SYSCFG_CFGR2_PVD_LOCK_Msk /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
AnnaBridge 171:3a7713b1edbc 4382 #define SYSCFG_CFGR2_SRAM_PEF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4383 #define SYSCFG_CFGR2_SRAM_PEF_Msk (0x1U << SYSCFG_CFGR2_SRAM_PEF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4384 #define SYSCFG_CFGR2_SRAM_PEF SYSCFG_CFGR2_SRAM_PEF_Msk /*!< SRAM Parity error flag */
AnnaBridge 171:3a7713b1edbc 4385 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
AnnaBridge 171:3a7713b1edbc 4386
AnnaBridge 171:3a7713b1edbc 4387 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 4388 /* */
AnnaBridge 171:3a7713b1edbc 4389 /* Timers (TIM) */
AnnaBridge 171:3a7713b1edbc 4390 /* */
AnnaBridge 171:3a7713b1edbc 4391 /*****************************************************************************/
AnnaBridge 171:3a7713b1edbc 4392 /******************* Bit definition for TIM_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 4393 #define TIM_CR1_CEN_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4394 #define TIM_CR1_CEN_Msk (0x1U << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4395 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
AnnaBridge 171:3a7713b1edbc 4396 #define TIM_CR1_UDIS_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4397 #define TIM_CR1_UDIS_Msk (0x1U << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4398 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
AnnaBridge 171:3a7713b1edbc 4399 #define TIM_CR1_URS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4400 #define TIM_CR1_URS_Msk (0x1U << TIM_CR1_URS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4401 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
AnnaBridge 171:3a7713b1edbc 4402 #define TIM_CR1_OPM_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4403 #define TIM_CR1_OPM_Msk (0x1U << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4404 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
AnnaBridge 171:3a7713b1edbc 4405 #define TIM_CR1_DIR_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4406 #define TIM_CR1_DIR_Msk (0x1U << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4407 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
AnnaBridge 171:3a7713b1edbc 4408
AnnaBridge 171:3a7713b1edbc 4409 #define TIM_CR1_CMS_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4410 #define TIM_CR1_CMS_Msk (0x3U << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
AnnaBridge 171:3a7713b1edbc 4411 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
AnnaBridge 171:3a7713b1edbc 4412 #define TIM_CR1_CMS_0 (0x1U << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4413 #define TIM_CR1_CMS_1 (0x2U << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4414
AnnaBridge 171:3a7713b1edbc 4415 #define TIM_CR1_ARPE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4416 #define TIM_CR1_ARPE_Msk (0x1U << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4417 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
AnnaBridge 171:3a7713b1edbc 4418
AnnaBridge 171:3a7713b1edbc 4419 #define TIM_CR1_CKD_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4420 #define TIM_CR1_CKD_Msk (0x3U << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 4421 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
AnnaBridge 171:3a7713b1edbc 4422 #define TIM_CR1_CKD_0 (0x1U << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4423 #define TIM_CR1_CKD_1 (0x2U << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4424
AnnaBridge 171:3a7713b1edbc 4425 /******************* Bit definition for TIM_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 4426 #define TIM_CR2_CCPC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4427 #define TIM_CR2_CCPC_Msk (0x1U << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4428 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
AnnaBridge 171:3a7713b1edbc 4429 #define TIM_CR2_CCUS_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4430 #define TIM_CR2_CCUS_Msk (0x1U << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4431 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
AnnaBridge 171:3a7713b1edbc 4432 #define TIM_CR2_CCDS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4433 #define TIM_CR2_CCDS_Msk (0x1U << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4434 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
AnnaBridge 171:3a7713b1edbc 4435
AnnaBridge 171:3a7713b1edbc 4436 #define TIM_CR2_MMS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4437 #define TIM_CR2_MMS_Msk (0x7U << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 4438 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
AnnaBridge 171:3a7713b1edbc 4439 #define TIM_CR2_MMS_0 (0x1U << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4440 #define TIM_CR2_MMS_1 (0x2U << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4441 #define TIM_CR2_MMS_2 (0x4U << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4442
AnnaBridge 171:3a7713b1edbc 4443 #define TIM_CR2_TI1S_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4444 #define TIM_CR2_TI1S_Msk (0x1U << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4445 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
AnnaBridge 171:3a7713b1edbc 4446 #define TIM_CR2_OIS1_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4447 #define TIM_CR2_OIS1_Msk (0x1U << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4448 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
AnnaBridge 171:3a7713b1edbc 4449 #define TIM_CR2_OIS1N_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4450 #define TIM_CR2_OIS1N_Msk (0x1U << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4451 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
AnnaBridge 171:3a7713b1edbc 4452 #define TIM_CR2_OIS2_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4453 #define TIM_CR2_OIS2_Msk (0x1U << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4454 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
AnnaBridge 171:3a7713b1edbc 4455 #define TIM_CR2_OIS2N_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4456 #define TIM_CR2_OIS2N_Msk (0x1U << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4457 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
AnnaBridge 171:3a7713b1edbc 4458 #define TIM_CR2_OIS3_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4459 #define TIM_CR2_OIS3_Msk (0x1U << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4460 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
AnnaBridge 171:3a7713b1edbc 4461 #define TIM_CR2_OIS3N_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4462 #define TIM_CR2_OIS3N_Msk (0x1U << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4463 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
AnnaBridge 171:3a7713b1edbc 4464 #define TIM_CR2_OIS4_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4465 #define TIM_CR2_OIS4_Msk (0x1U << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4466 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
AnnaBridge 171:3a7713b1edbc 4467
AnnaBridge 171:3a7713b1edbc 4468 /******************* Bit definition for TIM_SMCR register ******************/
AnnaBridge 171:3a7713b1edbc 4469 #define TIM_SMCR_SMS_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4470 #define TIM_SMCR_SMS_Msk (0x7U << TIM_SMCR_SMS_Pos) /*!< 0x00000007 */
AnnaBridge 171:3a7713b1edbc 4471 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
AnnaBridge 171:3a7713b1edbc 4472 #define TIM_SMCR_SMS_0 (0x1U << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4473 #define TIM_SMCR_SMS_1 (0x2U << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4474 #define TIM_SMCR_SMS_2 (0x4U << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4475
AnnaBridge 171:3a7713b1edbc 4476 #define TIM_SMCR_OCCS_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4477 #define TIM_SMCR_OCCS_Msk (0x1U << TIM_SMCR_OCCS_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4478 #define TIM_SMCR_OCCS TIM_SMCR_OCCS_Msk /*!< OCREF clear selection */
AnnaBridge 171:3a7713b1edbc 4479
AnnaBridge 171:3a7713b1edbc 4480 #define TIM_SMCR_TS_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4481 #define TIM_SMCR_TS_Msk (0x7U << TIM_SMCR_TS_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 4482 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[2:0] bits (Trigger selection) */
AnnaBridge 171:3a7713b1edbc 4483 #define TIM_SMCR_TS_0 (0x1U << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4484 #define TIM_SMCR_TS_1 (0x2U << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4485 #define TIM_SMCR_TS_2 (0x4U << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4486
AnnaBridge 171:3a7713b1edbc 4487 #define TIM_SMCR_MSM_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4488 #define TIM_SMCR_MSM_Msk (0x1U << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4489 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
AnnaBridge 171:3a7713b1edbc 4490
AnnaBridge 171:3a7713b1edbc 4491 #define TIM_SMCR_ETF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4492 #define TIM_SMCR_ETF_Msk (0xFU << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
AnnaBridge 171:3a7713b1edbc 4493 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
AnnaBridge 171:3a7713b1edbc 4494 #define TIM_SMCR_ETF_0 (0x1U << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4495 #define TIM_SMCR_ETF_1 (0x2U << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4496 #define TIM_SMCR_ETF_2 (0x4U << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4497 #define TIM_SMCR_ETF_3 (0x8U << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4498
AnnaBridge 171:3a7713b1edbc 4499 #define TIM_SMCR_ETPS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4500 #define TIM_SMCR_ETPS_Msk (0x3U << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 4501 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
AnnaBridge 171:3a7713b1edbc 4502 #define TIM_SMCR_ETPS_0 (0x1U << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4503 #define TIM_SMCR_ETPS_1 (0x2U << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4504
AnnaBridge 171:3a7713b1edbc 4505 #define TIM_SMCR_ECE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4506 #define TIM_SMCR_ECE_Msk (0x1U << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4507 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
AnnaBridge 171:3a7713b1edbc 4508 #define TIM_SMCR_ETP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4509 #define TIM_SMCR_ETP_Msk (0x1U << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4510 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
AnnaBridge 171:3a7713b1edbc 4511
AnnaBridge 171:3a7713b1edbc 4512 /******************* Bit definition for TIM_DIER register ******************/
AnnaBridge 171:3a7713b1edbc 4513 #define TIM_DIER_UIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4514 #define TIM_DIER_UIE_Msk (0x1U << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4515 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
AnnaBridge 171:3a7713b1edbc 4516 #define TIM_DIER_CC1IE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4517 #define TIM_DIER_CC1IE_Msk (0x1U << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4518 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
AnnaBridge 171:3a7713b1edbc 4519 #define TIM_DIER_CC2IE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4520 #define TIM_DIER_CC2IE_Msk (0x1U << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4521 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
AnnaBridge 171:3a7713b1edbc 4522 #define TIM_DIER_CC3IE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4523 #define TIM_DIER_CC3IE_Msk (0x1U << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4524 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
AnnaBridge 171:3a7713b1edbc 4525 #define TIM_DIER_CC4IE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4526 #define TIM_DIER_CC4IE_Msk (0x1U << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4527 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
AnnaBridge 171:3a7713b1edbc 4528 #define TIM_DIER_COMIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4529 #define TIM_DIER_COMIE_Msk (0x1U << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4530 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
AnnaBridge 171:3a7713b1edbc 4531 #define TIM_DIER_TIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4532 #define TIM_DIER_TIE_Msk (0x1U << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4533 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
AnnaBridge 171:3a7713b1edbc 4534 #define TIM_DIER_BIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4535 #define TIM_DIER_BIE_Msk (0x1U << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4536 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
AnnaBridge 171:3a7713b1edbc 4537 #define TIM_DIER_UDE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4538 #define TIM_DIER_UDE_Msk (0x1U << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4539 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
AnnaBridge 171:3a7713b1edbc 4540 #define TIM_DIER_CC1DE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4541 #define TIM_DIER_CC1DE_Msk (0x1U << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4542 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
AnnaBridge 171:3a7713b1edbc 4543 #define TIM_DIER_CC2DE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4544 #define TIM_DIER_CC2DE_Msk (0x1U << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4545 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
AnnaBridge 171:3a7713b1edbc 4546 #define TIM_DIER_CC3DE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4547 #define TIM_DIER_CC3DE_Msk (0x1U << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4548 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
AnnaBridge 171:3a7713b1edbc 4549 #define TIM_DIER_CC4DE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4550 #define TIM_DIER_CC4DE_Msk (0x1U << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4551 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
AnnaBridge 171:3a7713b1edbc 4552 #define TIM_DIER_COMDE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4553 #define TIM_DIER_COMDE_Msk (0x1U << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4554 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
AnnaBridge 171:3a7713b1edbc 4555 #define TIM_DIER_TDE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4556 #define TIM_DIER_TDE_Msk (0x1U << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4557 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
AnnaBridge 171:3a7713b1edbc 4558
AnnaBridge 171:3a7713b1edbc 4559 /******************** Bit definition for TIM_SR register *******************/
AnnaBridge 171:3a7713b1edbc 4560 #define TIM_SR_UIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4561 #define TIM_SR_UIF_Msk (0x1U << TIM_SR_UIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4562 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4563 #define TIM_SR_CC1IF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4564 #define TIM_SR_CC1IF_Msk (0x1U << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4565 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4566 #define TIM_SR_CC2IF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4567 #define TIM_SR_CC2IF_Msk (0x1U << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4568 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4569 #define TIM_SR_CC3IF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4570 #define TIM_SR_CC3IF_Msk (0x1U << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4571 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4572 #define TIM_SR_CC4IF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4573 #define TIM_SR_CC4IF_Msk (0x1U << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4574 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4575 #define TIM_SR_COMIF_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4576 #define TIM_SR_COMIF_Msk (0x1U << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4577 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4578 #define TIM_SR_TIF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4579 #define TIM_SR_TIF_Msk (0x1U << TIM_SR_TIF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4580 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4581 #define TIM_SR_BIF_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4582 #define TIM_SR_BIF_Msk (0x1U << TIM_SR_BIF_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4583 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
AnnaBridge 171:3a7713b1edbc 4584 #define TIM_SR_CC1OF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4585 #define TIM_SR_CC1OF_Msk (0x1U << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4586 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 4587 #define TIM_SR_CC2OF_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4588 #define TIM_SR_CC2OF_Msk (0x1U << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4589 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 4590 #define TIM_SR_CC3OF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4591 #define TIM_SR_CC3OF_Msk (0x1U << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4592 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 4593 #define TIM_SR_CC4OF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4594 #define TIM_SR_CC4OF_Msk (0x1U << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4595 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
AnnaBridge 171:3a7713b1edbc 4596
AnnaBridge 171:3a7713b1edbc 4597 /******************* Bit definition for TIM_EGR register *******************/
AnnaBridge 171:3a7713b1edbc 4598 #define TIM_EGR_UG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4599 #define TIM_EGR_UG_Msk (0x1U << TIM_EGR_UG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4600 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
AnnaBridge 171:3a7713b1edbc 4601 #define TIM_EGR_CC1G_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4602 #define TIM_EGR_CC1G_Msk (0x1U << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4603 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
AnnaBridge 171:3a7713b1edbc 4604 #define TIM_EGR_CC2G_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4605 #define TIM_EGR_CC2G_Msk (0x1U << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4606 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
AnnaBridge 171:3a7713b1edbc 4607 #define TIM_EGR_CC3G_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4608 #define TIM_EGR_CC3G_Msk (0x1U << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4609 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
AnnaBridge 171:3a7713b1edbc 4610 #define TIM_EGR_CC4G_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4611 #define TIM_EGR_CC4G_Msk (0x1U << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4612 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
AnnaBridge 171:3a7713b1edbc 4613 #define TIM_EGR_COMG_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4614 #define TIM_EGR_COMG_Msk (0x1U << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4615 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
AnnaBridge 171:3a7713b1edbc 4616 #define TIM_EGR_TG_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4617 #define TIM_EGR_TG_Msk (0x1U << TIM_EGR_TG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4618 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
AnnaBridge 171:3a7713b1edbc 4619 #define TIM_EGR_BG_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4620 #define TIM_EGR_BG_Msk (0x1U << TIM_EGR_BG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4621 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
AnnaBridge 171:3a7713b1edbc 4622
AnnaBridge 171:3a7713b1edbc 4623 /****************** Bit definition for TIM_CCMR1 register ******************/
AnnaBridge 171:3a7713b1edbc 4624 #define TIM_CCMR1_CC1S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4625 #define TIM_CCMR1_CC1S_Msk (0x3U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 4626 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
AnnaBridge 171:3a7713b1edbc 4627 #define TIM_CCMR1_CC1S_0 (0x1U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4628 #define TIM_CCMR1_CC1S_1 (0x2U << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4629
AnnaBridge 171:3a7713b1edbc 4630 #define TIM_CCMR1_OC1FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4631 #define TIM_CCMR1_OC1FE_Msk (0x1U << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4632 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
AnnaBridge 171:3a7713b1edbc 4633 #define TIM_CCMR1_OC1PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4634 #define TIM_CCMR1_OC1PE_Msk (0x1U << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4635 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
AnnaBridge 171:3a7713b1edbc 4636
AnnaBridge 171:3a7713b1edbc 4637 #define TIM_CCMR1_OC1M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4638 #define TIM_CCMR1_OC1M_Msk (0x7U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 4639 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
AnnaBridge 171:3a7713b1edbc 4640 #define TIM_CCMR1_OC1M_0 (0x1U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4641 #define TIM_CCMR1_OC1M_1 (0x2U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4642 #define TIM_CCMR1_OC1M_2 (0x4U << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4643
AnnaBridge 171:3a7713b1edbc 4644 #define TIM_CCMR1_OC1CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4645 #define TIM_CCMR1_OC1CE_Msk (0x1U << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4646 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
AnnaBridge 171:3a7713b1edbc 4647
AnnaBridge 171:3a7713b1edbc 4648 #define TIM_CCMR1_CC2S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4649 #define TIM_CCMR1_CC2S_Msk (0x3U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 4650 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
AnnaBridge 171:3a7713b1edbc 4651 #define TIM_CCMR1_CC2S_0 (0x1U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4652 #define TIM_CCMR1_CC2S_1 (0x2U << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4653
AnnaBridge 171:3a7713b1edbc 4654 #define TIM_CCMR1_OC2FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4655 #define TIM_CCMR1_OC2FE_Msk (0x1U << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4656 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
AnnaBridge 171:3a7713b1edbc 4657 #define TIM_CCMR1_OC2PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4658 #define TIM_CCMR1_OC2PE_Msk (0x1U << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4659 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
AnnaBridge 171:3a7713b1edbc 4660
AnnaBridge 171:3a7713b1edbc 4661 #define TIM_CCMR1_OC2M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4662 #define TIM_CCMR1_OC2M_Msk (0x7U << TIM_CCMR1_OC2M_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 4663 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
AnnaBridge 171:3a7713b1edbc 4664 #define TIM_CCMR1_OC2M_0 (0x1U << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4665 #define TIM_CCMR1_OC2M_1 (0x2U << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4666 #define TIM_CCMR1_OC2M_2 (0x4U << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4667
AnnaBridge 171:3a7713b1edbc 4668 #define TIM_CCMR1_OC2CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4669 #define TIM_CCMR1_OC2CE_Msk (0x1U << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4670 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
AnnaBridge 171:3a7713b1edbc 4671
AnnaBridge 171:3a7713b1edbc 4672 /*---------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 4673
AnnaBridge 171:3a7713b1edbc 4674 #define TIM_CCMR1_IC1PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4675 #define TIM_CCMR1_IC1PSC_Msk (0x3U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 4676 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
AnnaBridge 171:3a7713b1edbc 4677 #define TIM_CCMR1_IC1PSC_0 (0x1U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4678 #define TIM_CCMR1_IC1PSC_1 (0x2U << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4679
AnnaBridge 171:3a7713b1edbc 4680 #define TIM_CCMR1_IC1F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4681 #define TIM_CCMR1_IC1F_Msk (0xFU << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4682 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
AnnaBridge 171:3a7713b1edbc 4683 #define TIM_CCMR1_IC1F_0 (0x1U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4684 #define TIM_CCMR1_IC1F_1 (0x2U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4685 #define TIM_CCMR1_IC1F_2 (0x4U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4686 #define TIM_CCMR1_IC1F_3 (0x8U << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4687
AnnaBridge 171:3a7713b1edbc 4688 #define TIM_CCMR1_IC2PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4689 #define TIM_CCMR1_IC2PSC_Msk (0x3U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 4690 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
AnnaBridge 171:3a7713b1edbc 4691 #define TIM_CCMR1_IC2PSC_0 (0x1U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4692 #define TIM_CCMR1_IC2PSC_1 (0x2U << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4693
AnnaBridge 171:3a7713b1edbc 4694 #define TIM_CCMR1_IC2F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4695 #define TIM_CCMR1_IC2F_Msk (0xFU << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 4696 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
AnnaBridge 171:3a7713b1edbc 4697 #define TIM_CCMR1_IC2F_0 (0x1U << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4698 #define TIM_CCMR1_IC2F_1 (0x2U << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4699 #define TIM_CCMR1_IC2F_2 (0x4U << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4700 #define TIM_CCMR1_IC2F_3 (0x8U << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4701
AnnaBridge 171:3a7713b1edbc 4702 /****************** Bit definition for TIM_CCMR2 register ******************/
AnnaBridge 171:3a7713b1edbc 4703 #define TIM_CCMR2_CC3S_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4704 #define TIM_CCMR2_CC3S_Msk (0x3U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 4705 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
AnnaBridge 171:3a7713b1edbc 4706 #define TIM_CCMR2_CC3S_0 (0x1U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4707 #define TIM_CCMR2_CC3S_1 (0x2U << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4708
AnnaBridge 171:3a7713b1edbc 4709 #define TIM_CCMR2_OC3FE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4710 #define TIM_CCMR2_OC3FE_Msk (0x1U << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4711 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
AnnaBridge 171:3a7713b1edbc 4712 #define TIM_CCMR2_OC3PE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4713 #define TIM_CCMR2_OC3PE_Msk (0x1U << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4714 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
AnnaBridge 171:3a7713b1edbc 4715
AnnaBridge 171:3a7713b1edbc 4716 #define TIM_CCMR2_OC3M_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4717 #define TIM_CCMR2_OC3M_Msk (0x7U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
AnnaBridge 171:3a7713b1edbc 4718 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
AnnaBridge 171:3a7713b1edbc 4719 #define TIM_CCMR2_OC3M_0 (0x1U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4720 #define TIM_CCMR2_OC3M_1 (0x2U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4721 #define TIM_CCMR2_OC3M_2 (0x4U << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4722
AnnaBridge 171:3a7713b1edbc 4723 #define TIM_CCMR2_OC3CE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4724 #define TIM_CCMR2_OC3CE_Msk (0x1U << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4725 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
AnnaBridge 171:3a7713b1edbc 4726
AnnaBridge 171:3a7713b1edbc 4727 #define TIM_CCMR2_CC4S_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4728 #define TIM_CCMR2_CC4S_Msk (0x3U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 4729 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
AnnaBridge 171:3a7713b1edbc 4730 #define TIM_CCMR2_CC4S_0 (0x1U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4731 #define TIM_CCMR2_CC4S_1 (0x2U << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4732
AnnaBridge 171:3a7713b1edbc 4733 #define TIM_CCMR2_OC4FE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4734 #define TIM_CCMR2_OC4FE_Msk (0x1U << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4735 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
AnnaBridge 171:3a7713b1edbc 4736 #define TIM_CCMR2_OC4PE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4737 #define TIM_CCMR2_OC4PE_Msk (0x1U << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4738 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
AnnaBridge 171:3a7713b1edbc 4739
AnnaBridge 171:3a7713b1edbc 4740 #define TIM_CCMR2_OC4M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4741 #define TIM_CCMR2_OC4M_Msk (0x7U << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
AnnaBridge 171:3a7713b1edbc 4742 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
AnnaBridge 171:3a7713b1edbc 4743 #define TIM_CCMR2_OC4M_0 (0x1U << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4744 #define TIM_CCMR2_OC4M_1 (0x2U << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4745 #define TIM_CCMR2_OC4M_2 (0x4U << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4746
AnnaBridge 171:3a7713b1edbc 4747 #define TIM_CCMR2_OC4CE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4748 #define TIM_CCMR2_OC4CE_Msk (0x1U << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4749 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
AnnaBridge 171:3a7713b1edbc 4750
AnnaBridge 171:3a7713b1edbc 4751 /*---------------------------------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 4752
AnnaBridge 171:3a7713b1edbc 4753 #define TIM_CCMR2_IC3PSC_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4754 #define TIM_CCMR2_IC3PSC_Msk (0x3U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
AnnaBridge 171:3a7713b1edbc 4755 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
AnnaBridge 171:3a7713b1edbc 4756 #define TIM_CCMR2_IC3PSC_0 (0x1U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4757 #define TIM_CCMR2_IC3PSC_1 (0x2U << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4758
AnnaBridge 171:3a7713b1edbc 4759 #define TIM_CCMR2_IC3F_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4760 #define TIM_CCMR2_IC3F_Msk (0xFU << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
AnnaBridge 171:3a7713b1edbc 4761 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
AnnaBridge 171:3a7713b1edbc 4762 #define TIM_CCMR2_IC3F_0 (0x1U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4763 #define TIM_CCMR2_IC3F_1 (0x2U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4764 #define TIM_CCMR2_IC3F_2 (0x4U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4765 #define TIM_CCMR2_IC3F_3 (0x8U << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4766
AnnaBridge 171:3a7713b1edbc 4767 #define TIM_CCMR2_IC4PSC_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4768 #define TIM_CCMR2_IC4PSC_Msk (0x3U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
AnnaBridge 171:3a7713b1edbc 4769 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
AnnaBridge 171:3a7713b1edbc 4770 #define TIM_CCMR2_IC4PSC_0 (0x1U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4771 #define TIM_CCMR2_IC4PSC_1 (0x2U << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4772
AnnaBridge 171:3a7713b1edbc 4773 #define TIM_CCMR2_IC4F_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4774 #define TIM_CCMR2_IC4F_Msk (0xFU << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
AnnaBridge 171:3a7713b1edbc 4775 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
AnnaBridge 171:3a7713b1edbc 4776 #define TIM_CCMR2_IC4F_0 (0x1U << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4777 #define TIM_CCMR2_IC4F_1 (0x2U << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4778 #define TIM_CCMR2_IC4F_2 (0x4U << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4779 #define TIM_CCMR2_IC4F_3 (0x8U << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4780
AnnaBridge 171:3a7713b1edbc 4781 /******************* Bit definition for TIM_CCER register ******************/
AnnaBridge 171:3a7713b1edbc 4782 #define TIM_CCER_CC1E_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4783 #define TIM_CCER_CC1E_Msk (0x1U << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4784 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
AnnaBridge 171:3a7713b1edbc 4785 #define TIM_CCER_CC1P_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4786 #define TIM_CCER_CC1P_Msk (0x1U << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4787 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
AnnaBridge 171:3a7713b1edbc 4788 #define TIM_CCER_CC1NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4789 #define TIM_CCER_CC1NE_Msk (0x1U << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4790 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 4791 #define TIM_CCER_CC1NP_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4792 #define TIM_CCER_CC1NP_Msk (0x1U << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4793 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 4794 #define TIM_CCER_CC2E_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4795 #define TIM_CCER_CC2E_Msk (0x1U << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4796 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
AnnaBridge 171:3a7713b1edbc 4797 #define TIM_CCER_CC2P_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4798 #define TIM_CCER_CC2P_Msk (0x1U << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4799 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
AnnaBridge 171:3a7713b1edbc 4800 #define TIM_CCER_CC2NE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4801 #define TIM_CCER_CC2NE_Msk (0x1U << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4802 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 4803 #define TIM_CCER_CC2NP_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4804 #define TIM_CCER_CC2NP_Msk (0x1U << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4805 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 4806 #define TIM_CCER_CC3E_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4807 #define TIM_CCER_CC3E_Msk (0x1U << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4808 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
AnnaBridge 171:3a7713b1edbc 4809 #define TIM_CCER_CC3P_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4810 #define TIM_CCER_CC3P_Msk (0x1U << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4811 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
AnnaBridge 171:3a7713b1edbc 4812 #define TIM_CCER_CC3NE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4813 #define TIM_CCER_CC3NE_Msk (0x1U << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4814 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
AnnaBridge 171:3a7713b1edbc 4815 #define TIM_CCER_CC3NP_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4816 #define TIM_CCER_CC3NP_Msk (0x1U << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4817 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 4818 #define TIM_CCER_CC4E_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4819 #define TIM_CCER_CC4E_Msk (0x1U << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4820 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
AnnaBridge 171:3a7713b1edbc 4821 #define TIM_CCER_CC4P_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4822 #define TIM_CCER_CC4P_Msk (0x1U << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4823 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
AnnaBridge 171:3a7713b1edbc 4824 #define TIM_CCER_CC4NP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4825 #define TIM_CCER_CC4NP_Msk (0x1U << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4826 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
AnnaBridge 171:3a7713b1edbc 4827
AnnaBridge 171:3a7713b1edbc 4828 /******************* Bit definition for TIM_CNT register *******************/
AnnaBridge 171:3a7713b1edbc 4829 #define TIM_CNT_CNT_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4830 #define TIM_CNT_CNT_Msk (0xFFFFFFFFU << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4831 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
AnnaBridge 171:3a7713b1edbc 4832
AnnaBridge 171:3a7713b1edbc 4833 /******************* Bit definition for TIM_PSC register *******************/
AnnaBridge 171:3a7713b1edbc 4834 #define TIM_PSC_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4835 #define TIM_PSC_PSC_Msk (0xFFFFU << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4836 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
AnnaBridge 171:3a7713b1edbc 4837
AnnaBridge 171:3a7713b1edbc 4838 /******************* Bit definition for TIM_ARR register *******************/
AnnaBridge 171:3a7713b1edbc 4839 #define TIM_ARR_ARR_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4840 #define TIM_ARR_ARR_Msk (0xFFFFFFFFU << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
AnnaBridge 171:3a7713b1edbc 4841 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
AnnaBridge 171:3a7713b1edbc 4842
AnnaBridge 171:3a7713b1edbc 4843 /******************* Bit definition for TIM_RCR register *******************/
AnnaBridge 171:3a7713b1edbc 4844 #define TIM_RCR_REP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4845 #define TIM_RCR_REP_Msk (0xFFU << TIM_RCR_REP_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4846 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
AnnaBridge 171:3a7713b1edbc 4847
AnnaBridge 171:3a7713b1edbc 4848 /******************* Bit definition for TIM_CCR1 register ******************/
AnnaBridge 171:3a7713b1edbc 4849 #define TIM_CCR1_CCR1_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4850 #define TIM_CCR1_CCR1_Msk (0xFFFFU << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4851 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
AnnaBridge 171:3a7713b1edbc 4852
AnnaBridge 171:3a7713b1edbc 4853 /******************* Bit definition for TIM_CCR2 register ******************/
AnnaBridge 171:3a7713b1edbc 4854 #define TIM_CCR2_CCR2_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4855 #define TIM_CCR2_CCR2_Msk (0xFFFFU << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4856 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
AnnaBridge 171:3a7713b1edbc 4857
AnnaBridge 171:3a7713b1edbc 4858 /******************* Bit definition for TIM_CCR3 register ******************/
AnnaBridge 171:3a7713b1edbc 4859 #define TIM_CCR3_CCR3_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4860 #define TIM_CCR3_CCR3_Msk (0xFFFFU << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4861 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
AnnaBridge 171:3a7713b1edbc 4862
AnnaBridge 171:3a7713b1edbc 4863 /******************* Bit definition for TIM_CCR4 register ******************/
AnnaBridge 171:3a7713b1edbc 4864 #define TIM_CCR4_CCR4_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4865 #define TIM_CCR4_CCR4_Msk (0xFFFFU << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4866 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
AnnaBridge 171:3a7713b1edbc 4867
AnnaBridge 171:3a7713b1edbc 4868 /******************* Bit definition for TIM_BDTR register ******************/
AnnaBridge 171:3a7713b1edbc 4869 #define TIM_BDTR_DTG_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4870 #define TIM_BDTR_DTG_Msk (0xFFU << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 4871 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
AnnaBridge 171:3a7713b1edbc 4872 #define TIM_BDTR_DTG_0 (0x01U << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4873 #define TIM_BDTR_DTG_1 (0x02U << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4874 #define TIM_BDTR_DTG_2 (0x04U << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4875 #define TIM_BDTR_DTG_3 (0x08U << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4876 #define TIM_BDTR_DTG_4 (0x10U << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4877 #define TIM_BDTR_DTG_5 (0x20U << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4878 #define TIM_BDTR_DTG_6 (0x40U << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4879 #define TIM_BDTR_DTG_7 (0x80U << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4880
AnnaBridge 171:3a7713b1edbc 4881 #define TIM_BDTR_LOCK_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4882 #define TIM_BDTR_LOCK_Msk (0x3U << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
AnnaBridge 171:3a7713b1edbc 4883 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
AnnaBridge 171:3a7713b1edbc 4884 #define TIM_BDTR_LOCK_0 (0x1U << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4885 #define TIM_BDTR_LOCK_1 (0x2U << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4886
AnnaBridge 171:3a7713b1edbc 4887 #define TIM_BDTR_OSSI_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4888 #define TIM_BDTR_OSSI_Msk (0x1U << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4889 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
AnnaBridge 171:3a7713b1edbc 4890 #define TIM_BDTR_OSSR_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4891 #define TIM_BDTR_OSSR_Msk (0x1U << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4892 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
AnnaBridge 171:3a7713b1edbc 4893 #define TIM_BDTR_BKE_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4894 #define TIM_BDTR_BKE_Msk (0x1U << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4895 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable */
AnnaBridge 171:3a7713b1edbc 4896 #define TIM_BDTR_BKP_Pos (13U)
AnnaBridge 171:3a7713b1edbc 4897 #define TIM_BDTR_BKP_Msk (0x1U << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 4898 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity */
AnnaBridge 171:3a7713b1edbc 4899 #define TIM_BDTR_AOE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 4900 #define TIM_BDTR_AOE_Msk (0x1U << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 4901 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
AnnaBridge 171:3a7713b1edbc 4902 #define TIM_BDTR_MOE_Pos (15U)
AnnaBridge 171:3a7713b1edbc 4903 #define TIM_BDTR_MOE_Msk (0x1U << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 4904 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
AnnaBridge 171:3a7713b1edbc 4905
AnnaBridge 171:3a7713b1edbc 4906 /******************* Bit definition for TIM_DCR register *******************/
AnnaBridge 171:3a7713b1edbc 4907 #define TIM_DCR_DBA_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4908 #define TIM_DCR_DBA_Msk (0x1FU << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
AnnaBridge 171:3a7713b1edbc 4909 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
AnnaBridge 171:3a7713b1edbc 4910 #define TIM_DCR_DBA_0 (0x01U << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4911 #define TIM_DCR_DBA_1 (0x02U << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4912 #define TIM_DCR_DBA_2 (0x04U << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4913 #define TIM_DCR_DBA_3 (0x08U << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4914 #define TIM_DCR_DBA_4 (0x10U << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4915
AnnaBridge 171:3a7713b1edbc 4916 #define TIM_DCR_DBL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4917 #define TIM_DCR_DBL_Msk (0x1FU << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
AnnaBridge 171:3a7713b1edbc 4918 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
AnnaBridge 171:3a7713b1edbc 4919 #define TIM_DCR_DBL_0 (0x01U << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4920 #define TIM_DCR_DBL_1 (0x02U << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4921 #define TIM_DCR_DBL_2 (0x04U << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4922 #define TIM_DCR_DBL_3 (0x08U << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4923 #define TIM_DCR_DBL_4 (0x10U << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4924
AnnaBridge 171:3a7713b1edbc 4925 /******************* Bit definition for TIM_DMAR register ******************/
AnnaBridge 171:3a7713b1edbc 4926 #define TIM_DMAR_DMAB_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4927 #define TIM_DMAR_DMAB_Msk (0xFFFFU << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
AnnaBridge 171:3a7713b1edbc 4928 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
AnnaBridge 171:3a7713b1edbc 4929
AnnaBridge 171:3a7713b1edbc 4930 /******************* Bit definition for TIM14_OR register ********************/
AnnaBridge 171:3a7713b1edbc 4931 #define TIM14_OR_TI1_RMP_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4932 #define TIM14_OR_TI1_RMP_Msk (0x3U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000003 */
AnnaBridge 171:3a7713b1edbc 4933 #define TIM14_OR_TI1_RMP TIM14_OR_TI1_RMP_Msk /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
AnnaBridge 171:3a7713b1edbc 4934 #define TIM14_OR_TI1_RMP_0 (0x1U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4935 #define TIM14_OR_TI1_RMP_1 (0x2U << TIM14_OR_TI1_RMP_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4936
AnnaBridge 171:3a7713b1edbc 4937 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4938 /* */
AnnaBridge 171:3a7713b1edbc 4939 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
AnnaBridge 171:3a7713b1edbc 4940 /* */
AnnaBridge 171:3a7713b1edbc 4941 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 4942
AnnaBridge 171:3a7713b1edbc 4943 /*
AnnaBridge 171:3a7713b1edbc 4944 * @brief Specific device feature definitions (not present on all devices in the STM32F0 serie)
AnnaBridge 171:3a7713b1edbc 4945 */
AnnaBridge 171:3a7713b1edbc 4946
AnnaBridge 171:3a7713b1edbc 4947 /* Support of LIN feature */
AnnaBridge 171:3a7713b1edbc 4948 #define USART_LIN_SUPPORT
AnnaBridge 171:3a7713b1edbc 4949
AnnaBridge 171:3a7713b1edbc 4950 /* Support of Smartcard feature */
AnnaBridge 171:3a7713b1edbc 4951 #define USART_SMARTCARD_SUPPORT
AnnaBridge 171:3a7713b1edbc 4952
AnnaBridge 171:3a7713b1edbc 4953 /* Support of Irda feature */
AnnaBridge 171:3a7713b1edbc 4954 #define USART_IRDA_SUPPORT
AnnaBridge 171:3a7713b1edbc 4955
AnnaBridge 171:3a7713b1edbc 4956 /* Support of Wake Up from Stop Mode feature */
AnnaBridge 171:3a7713b1edbc 4957 #define USART_WUSM_SUPPORT
AnnaBridge 171:3a7713b1edbc 4958
AnnaBridge 171:3a7713b1edbc 4959 /****************** Bit definition for USART_CR1 register *******************/
AnnaBridge 171:3a7713b1edbc 4960 #define USART_CR1_UE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 4961 #define USART_CR1_UE_Msk (0x1U << USART_CR1_UE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 4962 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
AnnaBridge 171:3a7713b1edbc 4963 #define USART_CR1_UESM_Pos (1U)
AnnaBridge 171:3a7713b1edbc 4964 #define USART_CR1_UESM_Msk (0x1U << USART_CR1_UESM_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 4965 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
AnnaBridge 171:3a7713b1edbc 4966 #define USART_CR1_RE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 4967 #define USART_CR1_RE_Msk (0x1U << USART_CR1_RE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 4968 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
AnnaBridge 171:3a7713b1edbc 4969 #define USART_CR1_TE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 4970 #define USART_CR1_TE_Msk (0x1U << USART_CR1_TE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 4971 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
AnnaBridge 171:3a7713b1edbc 4972 #define USART_CR1_IDLEIE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 4973 #define USART_CR1_IDLEIE_Msk (0x1U << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 4974 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4975 #define USART_CR1_RXNEIE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 4976 #define USART_CR1_RXNEIE_Msk (0x1U << USART_CR1_RXNEIE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 4977 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk /*!< RXNE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4978 #define USART_CR1_TCIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 4979 #define USART_CR1_TCIE_Msk (0x1U << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 4980 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4981 #define USART_CR1_TXEIE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 4982 #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 4983 #define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!< TXE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4984 #define USART_CR1_PEIE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 4985 #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 4986 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 4987 #define USART_CR1_PS_Pos (9U)
AnnaBridge 171:3a7713b1edbc 4988 #define USART_CR1_PS_Msk (0x1U << USART_CR1_PS_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 4989 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
AnnaBridge 171:3a7713b1edbc 4990 #define USART_CR1_PCE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 4991 #define USART_CR1_PCE_Msk (0x1U << USART_CR1_PCE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 4992 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
AnnaBridge 171:3a7713b1edbc 4993 #define USART_CR1_WAKE_Pos (11U)
AnnaBridge 171:3a7713b1edbc 4994 #define USART_CR1_WAKE_Msk (0x1U << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 4995 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
AnnaBridge 171:3a7713b1edbc 4996 #define USART_CR1_M_Pos (12U)
AnnaBridge 171:3a7713b1edbc 4997 #define USART_CR1_M_Msk (0x1U << USART_CR1_M_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 4998 #define USART_CR1_M USART_CR1_M_Msk /*!< Word Length */
AnnaBridge 171:3a7713b1edbc 4999 #define USART_CR1_MME_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5000 #define USART_CR1_MME_Msk (0x1U << USART_CR1_MME_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5001 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
AnnaBridge 171:3a7713b1edbc 5002 #define USART_CR1_CMIE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5003 #define USART_CR1_CMIE_Msk (0x1U << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5004 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
AnnaBridge 171:3a7713b1edbc 5005 #define USART_CR1_OVER8_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5006 #define USART_CR1_OVER8_Msk (0x1U << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5007 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
AnnaBridge 171:3a7713b1edbc 5008 #define USART_CR1_DEDT_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5009 #define USART_CR1_DEDT_Msk (0x1FU << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
AnnaBridge 171:3a7713b1edbc 5010 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
AnnaBridge 171:3a7713b1edbc 5011 #define USART_CR1_DEDT_0 (0x01U << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5012 #define USART_CR1_DEDT_1 (0x02U << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5013 #define USART_CR1_DEDT_2 (0x04U << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5014 #define USART_CR1_DEDT_3 (0x08U << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5015 #define USART_CR1_DEDT_4 (0x10U << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5016 #define USART_CR1_DEAT_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5017 #define USART_CR1_DEAT_Msk (0x1FU << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
AnnaBridge 171:3a7713b1edbc 5018 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
AnnaBridge 171:3a7713b1edbc 5019 #define USART_CR1_DEAT_0 (0x01U << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5020 #define USART_CR1_DEAT_1 (0x02U << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5021 #define USART_CR1_DEAT_2 (0x04U << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5022 #define USART_CR1_DEAT_3 (0x08U << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
AnnaBridge 171:3a7713b1edbc 5023 #define USART_CR1_DEAT_4 (0x10U << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
AnnaBridge 171:3a7713b1edbc 5024 #define USART_CR1_RTOIE_Pos (26U)
AnnaBridge 171:3a7713b1edbc 5025 #define USART_CR1_RTOIE_Msk (0x1U << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
AnnaBridge 171:3a7713b1edbc 5026 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
AnnaBridge 171:3a7713b1edbc 5027 #define USART_CR1_EOBIE_Pos (27U)
AnnaBridge 171:3a7713b1edbc 5028 #define USART_CR1_EOBIE_Msk (0x1U << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
AnnaBridge 171:3a7713b1edbc 5029 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
AnnaBridge 171:3a7713b1edbc 5030
AnnaBridge 171:3a7713b1edbc 5031 /****************** Bit definition for USART_CR2 register *******************/
AnnaBridge 171:3a7713b1edbc 5032 #define USART_CR2_ADDM7_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5033 #define USART_CR2_ADDM7_Msk (0x1U << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5034 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
AnnaBridge 171:3a7713b1edbc 5035 #define USART_CR2_LBDL_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5036 #define USART_CR2_LBDL_Msk (0x1U << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5037 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
AnnaBridge 171:3a7713b1edbc 5038 #define USART_CR2_LBDIE_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5039 #define USART_CR2_LBDIE_Msk (0x1U << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5040 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5041 #define USART_CR2_LBCL_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5042 #define USART_CR2_LBCL_Msk (0x1U << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5043 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
AnnaBridge 171:3a7713b1edbc 5044 #define USART_CR2_CPHA_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5045 #define USART_CR2_CPHA_Msk (0x1U << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5046 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
AnnaBridge 171:3a7713b1edbc 5047 #define USART_CR2_CPOL_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5048 #define USART_CR2_CPOL_Msk (0x1U << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5049 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
AnnaBridge 171:3a7713b1edbc 5050 #define USART_CR2_CLKEN_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5051 #define USART_CR2_CLKEN_Msk (0x1U << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5052 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
AnnaBridge 171:3a7713b1edbc 5053 #define USART_CR2_STOP_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5054 #define USART_CR2_STOP_Msk (0x3U << USART_CR2_STOP_Pos) /*!< 0x00003000 */
AnnaBridge 171:3a7713b1edbc 5055 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
AnnaBridge 171:3a7713b1edbc 5056 #define USART_CR2_STOP_0 (0x1U << USART_CR2_STOP_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5057 #define USART_CR2_STOP_1 (0x2U << USART_CR2_STOP_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5058 #define USART_CR2_LINEN_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5059 #define USART_CR2_LINEN_Msk (0x1U << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5060 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
AnnaBridge 171:3a7713b1edbc 5061 #define USART_CR2_SWAP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5062 #define USART_CR2_SWAP_Msk (0x1U << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5063 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
AnnaBridge 171:3a7713b1edbc 5064 #define USART_CR2_RXINV_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5065 #define USART_CR2_RXINV_Msk (0x1U << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5066 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 5067 #define USART_CR2_TXINV_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5068 #define USART_CR2_TXINV_Msk (0x1U << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5069 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
AnnaBridge 171:3a7713b1edbc 5070 #define USART_CR2_DATAINV_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5071 #define USART_CR2_DATAINV_Msk (0x1U << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5072 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
AnnaBridge 171:3a7713b1edbc 5073 #define USART_CR2_MSBFIRST_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5074 #define USART_CR2_MSBFIRST_Msk (0x1U << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5075 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
AnnaBridge 171:3a7713b1edbc 5076 #define USART_CR2_ABREN_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5077 #define USART_CR2_ABREN_Msk (0x1U << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5078 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
AnnaBridge 171:3a7713b1edbc 5079 #define USART_CR2_ABRMODE_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5080 #define USART_CR2_ABRMODE_Msk (0x3U << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
AnnaBridge 171:3a7713b1edbc 5081 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
AnnaBridge 171:3a7713b1edbc 5082 #define USART_CR2_ABRMODE_0 (0x1U << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5083 #define USART_CR2_ABRMODE_1 (0x2U << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5084 #define USART_CR2_RTOEN_Pos (23U)
AnnaBridge 171:3a7713b1edbc 5085 #define USART_CR2_RTOEN_Msk (0x1U << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
AnnaBridge 171:3a7713b1edbc 5086 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
AnnaBridge 171:3a7713b1edbc 5087 #define USART_CR2_ADD_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5088 #define USART_CR2_ADD_Msk (0xFFU << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 5089 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
AnnaBridge 171:3a7713b1edbc 5090
AnnaBridge 171:3a7713b1edbc 5091 /****************** Bit definition for USART_CR3 register *******************/
AnnaBridge 171:3a7713b1edbc 5092 #define USART_CR3_EIE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5093 #define USART_CR3_EIE_Msk (0x1U << USART_CR3_EIE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5094 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5095 #define USART_CR3_IREN_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5096 #define USART_CR3_IREN_Msk (0x1U << USART_CR3_IREN_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5097 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
AnnaBridge 171:3a7713b1edbc 5098 #define USART_CR3_IRLP_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5099 #define USART_CR3_IRLP_Msk (0x1U << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5100 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
AnnaBridge 171:3a7713b1edbc 5101 #define USART_CR3_HDSEL_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5102 #define USART_CR3_HDSEL_Msk (0x1U << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5103 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
AnnaBridge 171:3a7713b1edbc 5104 #define USART_CR3_NACK_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5105 #define USART_CR3_NACK_Msk (0x1U << USART_CR3_NACK_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5106 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
AnnaBridge 171:3a7713b1edbc 5107 #define USART_CR3_SCEN_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5108 #define USART_CR3_SCEN_Msk (0x1U << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5109 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
AnnaBridge 171:3a7713b1edbc 5110 #define USART_CR3_DMAR_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5111 #define USART_CR3_DMAR_Msk (0x1U << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5112 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
AnnaBridge 171:3a7713b1edbc 5113 #define USART_CR3_DMAT_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5114 #define USART_CR3_DMAT_Msk (0x1U << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5115 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
AnnaBridge 171:3a7713b1edbc 5116 #define USART_CR3_RTSE_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5117 #define USART_CR3_RTSE_Msk (0x1U << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5118 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
AnnaBridge 171:3a7713b1edbc 5119 #define USART_CR3_CTSE_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5120 #define USART_CR3_CTSE_Msk (0x1U << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5121 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
AnnaBridge 171:3a7713b1edbc 5122 #define USART_CR3_CTSIE_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5123 #define USART_CR3_CTSIE_Msk (0x1U << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5124 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5125 #define USART_CR3_ONEBIT_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5126 #define USART_CR3_ONEBIT_Msk (0x1U << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5127 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
AnnaBridge 171:3a7713b1edbc 5128 #define USART_CR3_OVRDIS_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5129 #define USART_CR3_OVRDIS_Msk (0x1U << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5130 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
AnnaBridge 171:3a7713b1edbc 5131 #define USART_CR3_DDRE_Pos (13U)
AnnaBridge 171:3a7713b1edbc 5132 #define USART_CR3_DDRE_Msk (0x1U << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
AnnaBridge 171:3a7713b1edbc 5133 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
AnnaBridge 171:3a7713b1edbc 5134 #define USART_CR3_DEM_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5135 #define USART_CR3_DEM_Msk (0x1U << USART_CR3_DEM_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5136 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
AnnaBridge 171:3a7713b1edbc 5137 #define USART_CR3_DEP_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5138 #define USART_CR3_DEP_Msk (0x1U << USART_CR3_DEP_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5139 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
AnnaBridge 171:3a7713b1edbc 5140 #define USART_CR3_SCARCNT_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5141 #define USART_CR3_SCARCNT_Msk (0x7U << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
AnnaBridge 171:3a7713b1edbc 5142 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
AnnaBridge 171:3a7713b1edbc 5143 #define USART_CR3_SCARCNT_0 (0x1U << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5144 #define USART_CR3_SCARCNT_1 (0x2U << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5145 #define USART_CR3_SCARCNT_2 (0x4U << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5146 #define USART_CR3_WUS_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5147 #define USART_CR3_WUS_Msk (0x3U << USART_CR3_WUS_Pos) /*!< 0x00300000 */
AnnaBridge 171:3a7713b1edbc 5148 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
AnnaBridge 171:3a7713b1edbc 5149 #define USART_CR3_WUS_0 (0x1U << USART_CR3_WUS_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5150 #define USART_CR3_WUS_1 (0x2U << USART_CR3_WUS_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5151 #define USART_CR3_WUFIE_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5152 #define USART_CR3_WUFIE_Msk (0x1U << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5153 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 5154
AnnaBridge 171:3a7713b1edbc 5155 /****************** Bit definition for USART_BRR register *******************/
AnnaBridge 171:3a7713b1edbc 5156 #define USART_BRR_DIV_FRACTION_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5157 #define USART_BRR_DIV_FRACTION_Msk (0xFU << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
AnnaBridge 171:3a7713b1edbc 5158 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
AnnaBridge 171:3a7713b1edbc 5159 #define USART_BRR_DIV_MANTISSA_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5160 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFU << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
AnnaBridge 171:3a7713b1edbc 5161 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
AnnaBridge 171:3a7713b1edbc 5162
AnnaBridge 171:3a7713b1edbc 5163 /****************** Bit definition for USART_GTPR register ******************/
AnnaBridge 171:3a7713b1edbc 5164 #define USART_GTPR_PSC_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5165 #define USART_GTPR_PSC_Msk (0xFFU << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
AnnaBridge 171:3a7713b1edbc 5166 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
AnnaBridge 171:3a7713b1edbc 5167 #define USART_GTPR_GT_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5168 #define USART_GTPR_GT_Msk (0xFFU << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
AnnaBridge 171:3a7713b1edbc 5169 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
AnnaBridge 171:3a7713b1edbc 5170
AnnaBridge 171:3a7713b1edbc 5171
AnnaBridge 171:3a7713b1edbc 5172 /******************* Bit definition for USART_RTOR register *****************/
AnnaBridge 171:3a7713b1edbc 5173 #define USART_RTOR_RTO_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5174 #define USART_RTOR_RTO_Msk (0xFFFFFFU << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
AnnaBridge 171:3a7713b1edbc 5175 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
AnnaBridge 171:3a7713b1edbc 5176 #define USART_RTOR_BLEN_Pos (24U)
AnnaBridge 171:3a7713b1edbc 5177 #define USART_RTOR_BLEN_Msk (0xFFU << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
AnnaBridge 171:3a7713b1edbc 5178 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
AnnaBridge 171:3a7713b1edbc 5179
AnnaBridge 171:3a7713b1edbc 5180 /******************* Bit definition for USART_RQR register ******************/
AnnaBridge 171:3a7713b1edbc 5181 #define USART_RQR_ABRRQ_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5182 #define USART_RQR_ABRRQ_Msk (0x1U << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5183 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
AnnaBridge 171:3a7713b1edbc 5184 #define USART_RQR_SBKRQ_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5185 #define USART_RQR_SBKRQ_Msk (0x1U << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5186 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
AnnaBridge 171:3a7713b1edbc 5187 #define USART_RQR_MMRQ_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5188 #define USART_RQR_MMRQ_Msk (0x1U << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5189 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
AnnaBridge 171:3a7713b1edbc 5190 #define USART_RQR_RXFRQ_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5191 #define USART_RQR_RXFRQ_Msk (0x1U << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5192 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
AnnaBridge 171:3a7713b1edbc 5193 #define USART_RQR_TXFRQ_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5194 #define USART_RQR_TXFRQ_Msk (0x1U << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5195 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
AnnaBridge 171:3a7713b1edbc 5196
AnnaBridge 171:3a7713b1edbc 5197 /******************* Bit definition for USART_ISR register ******************/
AnnaBridge 171:3a7713b1edbc 5198 #define USART_ISR_PE_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5199 #define USART_ISR_PE_Msk (0x1U << USART_ISR_PE_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5200 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
AnnaBridge 171:3a7713b1edbc 5201 #define USART_ISR_FE_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5202 #define USART_ISR_FE_Msk (0x1U << USART_ISR_FE_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5203 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
AnnaBridge 171:3a7713b1edbc 5204 #define USART_ISR_NE_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5205 #define USART_ISR_NE_Msk (0x1U << USART_ISR_NE_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5206 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
AnnaBridge 171:3a7713b1edbc 5207 #define USART_ISR_ORE_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5208 #define USART_ISR_ORE_Msk (0x1U << USART_ISR_ORE_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5209 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
AnnaBridge 171:3a7713b1edbc 5210 #define USART_ISR_IDLE_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5211 #define USART_ISR_IDLE_Msk (0x1U << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5212 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
AnnaBridge 171:3a7713b1edbc 5213 #define USART_ISR_RXNE_Pos (5U)
AnnaBridge 171:3a7713b1edbc 5214 #define USART_ISR_RXNE_Msk (0x1U << USART_ISR_RXNE_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5215 #define USART_ISR_RXNE USART_ISR_RXNE_Msk /*!< Read Data Register Not Empty */
AnnaBridge 171:3a7713b1edbc 5216 #define USART_ISR_TC_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5217 #define USART_ISR_TC_Msk (0x1U << USART_ISR_TC_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5218 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
AnnaBridge 171:3a7713b1edbc 5219 #define USART_ISR_TXE_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5220 #define USART_ISR_TXE_Msk (0x1U << USART_ISR_TXE_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5221 #define USART_ISR_TXE USART_ISR_TXE_Msk /*!< Transmit Data Register Empty */
AnnaBridge 171:3a7713b1edbc 5222 #define USART_ISR_LBDF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5223 #define USART_ISR_LBDF_Msk (0x1U << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5224 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
AnnaBridge 171:3a7713b1edbc 5225 #define USART_ISR_CTSIF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5226 #define USART_ISR_CTSIF_Msk (0x1U << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5227 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
AnnaBridge 171:3a7713b1edbc 5228 #define USART_ISR_CTS_Pos (10U)
AnnaBridge 171:3a7713b1edbc 5229 #define USART_ISR_CTS_Msk (0x1U << USART_ISR_CTS_Pos) /*!< 0x00000400 */
AnnaBridge 171:3a7713b1edbc 5230 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
AnnaBridge 171:3a7713b1edbc 5231 #define USART_ISR_RTOF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5232 #define USART_ISR_RTOF_Msk (0x1U << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5233 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
AnnaBridge 171:3a7713b1edbc 5234 #define USART_ISR_EOBF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5235 #define USART_ISR_EOBF_Msk (0x1U << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5236 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
AnnaBridge 171:3a7713b1edbc 5237 #define USART_ISR_ABRE_Pos (14U)
AnnaBridge 171:3a7713b1edbc 5238 #define USART_ISR_ABRE_Msk (0x1U << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
AnnaBridge 171:3a7713b1edbc 5239 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
AnnaBridge 171:3a7713b1edbc 5240 #define USART_ISR_ABRF_Pos (15U)
AnnaBridge 171:3a7713b1edbc 5241 #define USART_ISR_ABRF_Msk (0x1U << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
AnnaBridge 171:3a7713b1edbc 5242 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
AnnaBridge 171:3a7713b1edbc 5243 #define USART_ISR_BUSY_Pos (16U)
AnnaBridge 171:3a7713b1edbc 5244 #define USART_ISR_BUSY_Msk (0x1U << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
AnnaBridge 171:3a7713b1edbc 5245 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
AnnaBridge 171:3a7713b1edbc 5246 #define USART_ISR_CMF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5247 #define USART_ISR_CMF_Msk (0x1U << USART_ISR_CMF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5248 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
AnnaBridge 171:3a7713b1edbc 5249 #define USART_ISR_SBKF_Pos (18U)
AnnaBridge 171:3a7713b1edbc 5250 #define USART_ISR_SBKF_Msk (0x1U << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
AnnaBridge 171:3a7713b1edbc 5251 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
AnnaBridge 171:3a7713b1edbc 5252 #define USART_ISR_RWU_Pos (19U)
AnnaBridge 171:3a7713b1edbc 5253 #define USART_ISR_RWU_Msk (0x1U << USART_ISR_RWU_Pos) /*!< 0x00080000 */
AnnaBridge 171:3a7713b1edbc 5254 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
AnnaBridge 171:3a7713b1edbc 5255 #define USART_ISR_WUF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5256 #define USART_ISR_WUF_Msk (0x1U << USART_ISR_WUF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5257 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
AnnaBridge 171:3a7713b1edbc 5258 #define USART_ISR_TEACK_Pos (21U)
AnnaBridge 171:3a7713b1edbc 5259 #define USART_ISR_TEACK_Msk (0x1U << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
AnnaBridge 171:3a7713b1edbc 5260 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 5261 #define USART_ISR_REACK_Pos (22U)
AnnaBridge 171:3a7713b1edbc 5262 #define USART_ISR_REACK_Msk (0x1U << USART_ISR_REACK_Pos) /*!< 0x00400000 */
AnnaBridge 171:3a7713b1edbc 5263 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
AnnaBridge 171:3a7713b1edbc 5264
AnnaBridge 171:3a7713b1edbc 5265 /******************* Bit definition for USART_ICR register ******************/
AnnaBridge 171:3a7713b1edbc 5266 #define USART_ICR_PECF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5267 #define USART_ICR_PECF_Msk (0x1U << USART_ICR_PECF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5268 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 5269 #define USART_ICR_FECF_Pos (1U)
AnnaBridge 171:3a7713b1edbc 5270 #define USART_ICR_FECF_Msk (0x1U << USART_ICR_FECF_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5271 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 5272 #define USART_ICR_NCF_Pos (2U)
AnnaBridge 171:3a7713b1edbc 5273 #define USART_ICR_NCF_Msk (0x1U << USART_ICR_NCF_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5274 #define USART_ICR_NCF USART_ICR_NCF_Msk /*!< Noise detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 5275 #define USART_ICR_ORECF_Pos (3U)
AnnaBridge 171:3a7713b1edbc 5276 #define USART_ICR_ORECF_Msk (0x1U << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5277 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
AnnaBridge 171:3a7713b1edbc 5278 #define USART_ICR_IDLECF_Pos (4U)
AnnaBridge 171:3a7713b1edbc 5279 #define USART_ICR_IDLECF_Msk (0x1U << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5280 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
AnnaBridge 171:3a7713b1edbc 5281 #define USART_ICR_TCCF_Pos (6U)
AnnaBridge 171:3a7713b1edbc 5282 #define USART_ICR_TCCF_Msk (0x1U << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5283 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
AnnaBridge 171:3a7713b1edbc 5284 #define USART_ICR_LBDCF_Pos (8U)
AnnaBridge 171:3a7713b1edbc 5285 #define USART_ICR_LBDCF_Msk (0x1U << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5286 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
AnnaBridge 171:3a7713b1edbc 5287 #define USART_ICR_CTSCF_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5288 #define USART_ICR_CTSCF_Msk (0x1U << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5289 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
AnnaBridge 171:3a7713b1edbc 5290 #define USART_ICR_RTOCF_Pos (11U)
AnnaBridge 171:3a7713b1edbc 5291 #define USART_ICR_RTOCF_Msk (0x1U << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
AnnaBridge 171:3a7713b1edbc 5292 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
AnnaBridge 171:3a7713b1edbc 5293 #define USART_ICR_EOBCF_Pos (12U)
AnnaBridge 171:3a7713b1edbc 5294 #define USART_ICR_EOBCF_Msk (0x1U << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
AnnaBridge 171:3a7713b1edbc 5295 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
AnnaBridge 171:3a7713b1edbc 5296 #define USART_ICR_CMCF_Pos (17U)
AnnaBridge 171:3a7713b1edbc 5297 #define USART_ICR_CMCF_Msk (0x1U << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
AnnaBridge 171:3a7713b1edbc 5298 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
AnnaBridge 171:3a7713b1edbc 5299 #define USART_ICR_WUCF_Pos (20U)
AnnaBridge 171:3a7713b1edbc 5300 #define USART_ICR_WUCF_Msk (0x1U << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
AnnaBridge 171:3a7713b1edbc 5301 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
AnnaBridge 171:3a7713b1edbc 5302
AnnaBridge 171:3a7713b1edbc 5303 /******************* Bit definition for USART_RDR register ******************/
AnnaBridge 171:3a7713b1edbc 5304 #define USART_RDR_RDR ((uint16_t)0x01FFU) /*!< RDR[8:0] bits (Receive Data value) */
AnnaBridge 171:3a7713b1edbc 5305
AnnaBridge 171:3a7713b1edbc 5306 /******************* Bit definition for USART_TDR register ******************/
AnnaBridge 171:3a7713b1edbc 5307 #define USART_TDR_TDR ((uint16_t)0x01FFU) /*!< TDR[8:0] bits (Transmit Data value) */
AnnaBridge 171:3a7713b1edbc 5308
AnnaBridge 171:3a7713b1edbc 5309 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5310 /* */
AnnaBridge 171:3a7713b1edbc 5311 /* Window WATCHDOG (WWDG) */
AnnaBridge 171:3a7713b1edbc 5312 /* */
AnnaBridge 171:3a7713b1edbc 5313 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5314
AnnaBridge 171:3a7713b1edbc 5315 /******************* Bit definition for WWDG_CR register ********************/
AnnaBridge 171:3a7713b1edbc 5316 #define WWDG_CR_T_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5317 #define WWDG_CR_T_Msk (0x7FU << WWDG_CR_T_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 5318 #define WWDG_CR_T WWDG_CR_T_Msk /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
AnnaBridge 171:3a7713b1edbc 5319 #define WWDG_CR_T_0 (0x01U << WWDG_CR_T_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5320 #define WWDG_CR_T_1 (0x02U << WWDG_CR_T_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5321 #define WWDG_CR_T_2 (0x04U << WWDG_CR_T_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5322 #define WWDG_CR_T_3 (0x08U << WWDG_CR_T_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5323 #define WWDG_CR_T_4 (0x10U << WWDG_CR_T_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5324 #define WWDG_CR_T_5 (0x20U << WWDG_CR_T_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5325 #define WWDG_CR_T_6 (0x40U << WWDG_CR_T_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5326
AnnaBridge 171:3a7713b1edbc 5327 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5328 #define WWDG_CR_T0 WWDG_CR_T_0
AnnaBridge 171:3a7713b1edbc 5329 #define WWDG_CR_T1 WWDG_CR_T_1
AnnaBridge 171:3a7713b1edbc 5330 #define WWDG_CR_T2 WWDG_CR_T_2
AnnaBridge 171:3a7713b1edbc 5331 #define WWDG_CR_T3 WWDG_CR_T_3
AnnaBridge 171:3a7713b1edbc 5332 #define WWDG_CR_T4 WWDG_CR_T_4
AnnaBridge 171:3a7713b1edbc 5333 #define WWDG_CR_T5 WWDG_CR_T_5
AnnaBridge 171:3a7713b1edbc 5334 #define WWDG_CR_T6 WWDG_CR_T_6
AnnaBridge 171:3a7713b1edbc 5335
AnnaBridge 171:3a7713b1edbc 5336 #define WWDG_CR_WDGA_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5337 #define WWDG_CR_WDGA_Msk (0x1U << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5338 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!< Activation bit */
AnnaBridge 171:3a7713b1edbc 5339
AnnaBridge 171:3a7713b1edbc 5340 /******************* Bit definition for WWDG_CFR register *******************/
AnnaBridge 171:3a7713b1edbc 5341 #define WWDG_CFR_W_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5342 #define WWDG_CFR_W_Msk (0x7FU << WWDG_CFR_W_Pos) /*!< 0x0000007F */
AnnaBridge 171:3a7713b1edbc 5343 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!< W[6:0] bits (7-bit window value) */
AnnaBridge 171:3a7713b1edbc 5344 #define WWDG_CFR_W_0 (0x01U << WWDG_CFR_W_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5345 #define WWDG_CFR_W_1 (0x02U << WWDG_CFR_W_Pos) /*!< 0x00000002 */
AnnaBridge 171:3a7713b1edbc 5346 #define WWDG_CFR_W_2 (0x04U << WWDG_CFR_W_Pos) /*!< 0x00000004 */
AnnaBridge 171:3a7713b1edbc 5347 #define WWDG_CFR_W_3 (0x08U << WWDG_CFR_W_Pos) /*!< 0x00000008 */
AnnaBridge 171:3a7713b1edbc 5348 #define WWDG_CFR_W_4 (0x10U << WWDG_CFR_W_Pos) /*!< 0x00000010 */
AnnaBridge 171:3a7713b1edbc 5349 #define WWDG_CFR_W_5 (0x20U << WWDG_CFR_W_Pos) /*!< 0x00000020 */
AnnaBridge 171:3a7713b1edbc 5350 #define WWDG_CFR_W_6 (0x40U << WWDG_CFR_W_Pos) /*!< 0x00000040 */
AnnaBridge 171:3a7713b1edbc 5351
AnnaBridge 171:3a7713b1edbc 5352 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5353 #define WWDG_CFR_W0 WWDG_CFR_W_0
AnnaBridge 171:3a7713b1edbc 5354 #define WWDG_CFR_W1 WWDG_CFR_W_1
AnnaBridge 171:3a7713b1edbc 5355 #define WWDG_CFR_W2 WWDG_CFR_W_2
AnnaBridge 171:3a7713b1edbc 5356 #define WWDG_CFR_W3 WWDG_CFR_W_3
AnnaBridge 171:3a7713b1edbc 5357 #define WWDG_CFR_W4 WWDG_CFR_W_4
AnnaBridge 171:3a7713b1edbc 5358 #define WWDG_CFR_W5 WWDG_CFR_W_5
AnnaBridge 171:3a7713b1edbc 5359 #define WWDG_CFR_W6 WWDG_CFR_W_6
AnnaBridge 171:3a7713b1edbc 5360
AnnaBridge 171:3a7713b1edbc 5361 #define WWDG_CFR_WDGTB_Pos (7U)
AnnaBridge 171:3a7713b1edbc 5362 #define WWDG_CFR_WDGTB_Msk (0x3U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000180 */
AnnaBridge 171:3a7713b1edbc 5363 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!< WDGTB[1:0] bits (Timer Base) */
AnnaBridge 171:3a7713b1edbc 5364 #define WWDG_CFR_WDGTB_0 (0x1U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000080 */
AnnaBridge 171:3a7713b1edbc 5365 #define WWDG_CFR_WDGTB_1 (0x2U << WWDG_CFR_WDGTB_Pos) /*!< 0x00000100 */
AnnaBridge 171:3a7713b1edbc 5366
AnnaBridge 171:3a7713b1edbc 5367 /* Legacy defines */
AnnaBridge 171:3a7713b1edbc 5368 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
AnnaBridge 171:3a7713b1edbc 5369 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
AnnaBridge 171:3a7713b1edbc 5370
AnnaBridge 171:3a7713b1edbc 5371 #define WWDG_CFR_EWI_Pos (9U)
AnnaBridge 171:3a7713b1edbc 5372 #define WWDG_CFR_EWI_Msk (0x1U << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
AnnaBridge 171:3a7713b1edbc 5373 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!< Early Wakeup Interrupt */
AnnaBridge 171:3a7713b1edbc 5374
AnnaBridge 171:3a7713b1edbc 5375 /******************* Bit definition for WWDG_SR register ********************/
AnnaBridge 171:3a7713b1edbc 5376 #define WWDG_SR_EWIF_Pos (0U)
AnnaBridge 171:3a7713b1edbc 5377 #define WWDG_SR_EWIF_Msk (0x1U << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
AnnaBridge 171:3a7713b1edbc 5378 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!< Early Wakeup Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 5379
AnnaBridge 171:3a7713b1edbc 5380 /**
AnnaBridge 171:3a7713b1edbc 5381 * @}
AnnaBridge 171:3a7713b1edbc 5382 */
AnnaBridge 171:3a7713b1edbc 5383
AnnaBridge 171:3a7713b1edbc 5384 /**
AnnaBridge 171:3a7713b1edbc 5385 * @}
AnnaBridge 171:3a7713b1edbc 5386 */
AnnaBridge 171:3a7713b1edbc 5387
AnnaBridge 171:3a7713b1edbc 5388
AnnaBridge 171:3a7713b1edbc 5389 /** @addtogroup Exported_macro
AnnaBridge 171:3a7713b1edbc 5390 * @{
AnnaBridge 171:3a7713b1edbc 5391 */
AnnaBridge 171:3a7713b1edbc 5392
AnnaBridge 171:3a7713b1edbc 5393 /****************************** ADC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5394 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
AnnaBridge 171:3a7713b1edbc 5395
AnnaBridge 171:3a7713b1edbc 5396 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
AnnaBridge 171:3a7713b1edbc 5397
AnnaBridge 171:3a7713b1edbc 5398 /****************************** CRC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5399 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
AnnaBridge 171:3a7713b1edbc 5400
AnnaBridge 171:3a7713b1edbc 5401 /******************************* DMA Instances ********************************/
AnnaBridge 171:3a7713b1edbc 5402 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
AnnaBridge 171:3a7713b1edbc 5403 ((INSTANCE) == DMA1_Channel2) || \
AnnaBridge 171:3a7713b1edbc 5404 ((INSTANCE) == DMA1_Channel3) || \
AnnaBridge 171:3a7713b1edbc 5405 ((INSTANCE) == DMA1_Channel4) || \
AnnaBridge 171:3a7713b1edbc 5406 ((INSTANCE) == DMA1_Channel5))
AnnaBridge 171:3a7713b1edbc 5407
AnnaBridge 171:3a7713b1edbc 5408 /****************************** GPIO Instances ********************************/
AnnaBridge 171:3a7713b1edbc 5409 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 5410 ((INSTANCE) == GPIOB) || \
AnnaBridge 171:3a7713b1edbc 5411 ((INSTANCE) == GPIOC) || \
AnnaBridge 171:3a7713b1edbc 5412 ((INSTANCE) == GPIOF))
AnnaBridge 171:3a7713b1edbc 5413
AnnaBridge 171:3a7713b1edbc 5414 /**************************** GPIO Alternate Function Instances ***************/
AnnaBridge 171:3a7713b1edbc 5415 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 5416 ((INSTANCE) == GPIOB))
AnnaBridge 171:3a7713b1edbc 5417
AnnaBridge 171:3a7713b1edbc 5418 /****************************** GPIO Lock Instances ***************************/
AnnaBridge 171:3a7713b1edbc 5419 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
AnnaBridge 171:3a7713b1edbc 5420 ((INSTANCE) == GPIOB))
AnnaBridge 171:3a7713b1edbc 5421
AnnaBridge 171:3a7713b1edbc 5422 /****************************** I2C Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5423 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
AnnaBridge 171:3a7713b1edbc 5424
AnnaBridge 171:3a7713b1edbc 5425 /****************** I2C Instances : wakeup capability from stop modes *********/
AnnaBridge 171:3a7713b1edbc 5426 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
AnnaBridge 171:3a7713b1edbc 5427
AnnaBridge 171:3a7713b1edbc 5428 /****************************** I2S Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5429 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
AnnaBridge 171:3a7713b1edbc 5430
AnnaBridge 171:3a7713b1edbc 5431 /****************************** IWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 5432 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
AnnaBridge 171:3a7713b1edbc 5433
AnnaBridge 171:3a7713b1edbc 5434 /****************************** RTC Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5435 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
AnnaBridge 171:3a7713b1edbc 5436
AnnaBridge 171:3a7713b1edbc 5437 /****************************** SMBUS Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5438 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
AnnaBridge 171:3a7713b1edbc 5439
AnnaBridge 171:3a7713b1edbc 5440 /****************************** SPI Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5441 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
AnnaBridge 171:3a7713b1edbc 5442
AnnaBridge 171:3a7713b1edbc 5443 /****************************** TIM Instances *********************************/
AnnaBridge 171:3a7713b1edbc 5444 #define IS_TIM_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5445 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5446 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5447 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 5448 ((INSTANCE) == TIM14) || \
AnnaBridge 171:3a7713b1edbc 5449 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5450 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5451
AnnaBridge 171:3a7713b1edbc 5452 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5453 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5454 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5455 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 5456 ((INSTANCE) == TIM14) || \
AnnaBridge 171:3a7713b1edbc 5457 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5458 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5459
AnnaBridge 171:3a7713b1edbc 5460 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5461 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5462 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5463 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5464
AnnaBridge 171:3a7713b1edbc 5465 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5466 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5467 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5468 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5469
AnnaBridge 171:3a7713b1edbc 5470 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5471 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5472 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5473 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5474
AnnaBridge 171:3a7713b1edbc 5475
AnnaBridge 171:3a7713b1edbc 5476 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5477 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5478 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5479 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5480
AnnaBridge 171:3a7713b1edbc 5481 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5482 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5483 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5484 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5485
AnnaBridge 171:3a7713b1edbc 5486 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5487 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5488 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5489 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5490
AnnaBridge 171:3a7713b1edbc 5491 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5492 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5493 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5494 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5495
AnnaBridge 171:3a7713b1edbc 5496 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5497 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5498 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5499 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5500
AnnaBridge 171:3a7713b1edbc 5501 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5502 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5503 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5504 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5505
AnnaBridge 171:3a7713b1edbc 5506 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5507 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 5508
AnnaBridge 171:3a7713b1edbc 5509 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5510 (((INSTANCE) == TIM1))
AnnaBridge 171:3a7713b1edbc 5511
AnnaBridge 171:3a7713b1edbc 5512 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5513 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5514 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5515 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5516
AnnaBridge 171:3a7713b1edbc 5517 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5518 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5519 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5520 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5521
AnnaBridge 171:3a7713b1edbc 5522 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5523 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5524 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5525 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5526
AnnaBridge 171:3a7713b1edbc 5527 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5528 ((INSTANCE) == TIM2)
AnnaBridge 171:3a7713b1edbc 5529
AnnaBridge 171:3a7713b1edbc 5530 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5531 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5532 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5533 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 5534 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5535 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5536
AnnaBridge 171:3a7713b1edbc 5537 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5538 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5539 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5540 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5541
AnnaBridge 171:3a7713b1edbc 5542 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 5543 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 5544 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 5545 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 5546 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 5547 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 5548 || \
AnnaBridge 171:3a7713b1edbc 5549 (((INSTANCE) == TIM2) && \
AnnaBridge 171:3a7713b1edbc 5550 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 5551 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 5552 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 5553 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 5554 || \
AnnaBridge 171:3a7713b1edbc 5555 (((INSTANCE) == TIM3) && \
AnnaBridge 171:3a7713b1edbc 5556 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 5557 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 5558 ((CHANNEL) == TIM_CHANNEL_3) || \
AnnaBridge 171:3a7713b1edbc 5559 ((CHANNEL) == TIM_CHANNEL_4))) \
AnnaBridge 171:3a7713b1edbc 5560 || \
AnnaBridge 171:3a7713b1edbc 5561 (((INSTANCE) == TIM14) && \
AnnaBridge 171:3a7713b1edbc 5562 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 5563 || \
AnnaBridge 171:3a7713b1edbc 5564 (((INSTANCE) == TIM16) && \
AnnaBridge 171:3a7713b1edbc 5565 (((CHANNEL) == TIM_CHANNEL_1))) \
AnnaBridge 171:3a7713b1edbc 5566 || \
AnnaBridge 171:3a7713b1edbc 5567 (((INSTANCE) == TIM17) && \
AnnaBridge 171:3a7713b1edbc 5568 (((CHANNEL) == TIM_CHANNEL_1))))
AnnaBridge 171:3a7713b1edbc 5569
AnnaBridge 171:3a7713b1edbc 5570 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
AnnaBridge 171:3a7713b1edbc 5571 ((((INSTANCE) == TIM1) && \
AnnaBridge 171:3a7713b1edbc 5572 (((CHANNEL) == TIM_CHANNEL_1) || \
AnnaBridge 171:3a7713b1edbc 5573 ((CHANNEL) == TIM_CHANNEL_2) || \
AnnaBridge 171:3a7713b1edbc 5574 ((CHANNEL) == TIM_CHANNEL_3))) \
AnnaBridge 171:3a7713b1edbc 5575 || \
AnnaBridge 171:3a7713b1edbc 5576 (((INSTANCE) == TIM16) && \
AnnaBridge 171:3a7713b1edbc 5577 ((CHANNEL) == TIM_CHANNEL_1)) \
AnnaBridge 171:3a7713b1edbc 5578 || \
AnnaBridge 171:3a7713b1edbc 5579 (((INSTANCE) == TIM17) && \
AnnaBridge 171:3a7713b1edbc 5580 ((CHANNEL) == TIM_CHANNEL_1)))
AnnaBridge 171:3a7713b1edbc 5581
AnnaBridge 171:3a7713b1edbc 5582 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5583 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5584 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5585 ((INSTANCE) == TIM3))
AnnaBridge 171:3a7713b1edbc 5586
AnnaBridge 171:3a7713b1edbc 5587 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5588 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5589 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5590 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5591
AnnaBridge 171:3a7713b1edbc 5592 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5593 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5594 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5595 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 5596 ((INSTANCE) == TIM14) || \
AnnaBridge 171:3a7713b1edbc 5597 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5598 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5599
AnnaBridge 171:3a7713b1edbc 5600 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5601 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5602 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5603 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 5604 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5605 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5606
AnnaBridge 171:3a7713b1edbc 5607 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5608 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5609 ((INSTANCE) == TIM2) || \
AnnaBridge 171:3a7713b1edbc 5610 ((INSTANCE) == TIM3) || \
AnnaBridge 171:3a7713b1edbc 5611 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5612 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5613
AnnaBridge 171:3a7713b1edbc 5614 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5615 (((INSTANCE) == TIM1) || \
AnnaBridge 171:3a7713b1edbc 5616 ((INSTANCE) == TIM16) || \
AnnaBridge 171:3a7713b1edbc 5617 ((INSTANCE) == TIM17))
AnnaBridge 171:3a7713b1edbc 5618
AnnaBridge 171:3a7713b1edbc 5619 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5620 ((INSTANCE) == TIM14)
AnnaBridge 171:3a7713b1edbc 5621
AnnaBridge 171:3a7713b1edbc 5622 #define IS_TIM_ADVANCED_INSTANCE(INSTANCE)\
AnnaBridge 171:3a7713b1edbc 5623 ((INSTANCE) == TIM1)
AnnaBridge 171:3a7713b1edbc 5624
AnnaBridge 171:3a7713b1edbc 5625 /*********************** UART Instances : IRDA mode ***************************/
AnnaBridge 171:3a7713b1edbc 5626 #define IS_IRDA_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5627
AnnaBridge 171:3a7713b1edbc 5628 /********************* UART Instances : Smard card mode ***********************/
AnnaBridge 171:3a7713b1edbc 5629 #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5630
AnnaBridge 171:3a7713b1edbc 5631 /******************** USART Instances : Synchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 5632 #define IS_USART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5633
AnnaBridge 171:3a7713b1edbc 5634 /******************** USART Instances : auto Baud rate detection **************/
AnnaBridge 171:3a7713b1edbc 5635 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5636
AnnaBridge 171:3a7713b1edbc 5637 /******************** UART Instances : Asynchronous mode **********************/
AnnaBridge 171:3a7713b1edbc 5638 #define IS_UART_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5639
AnnaBridge 171:3a7713b1edbc 5640 /******************** UART Instances : Half-Duplex mode **********************/
AnnaBridge 171:3a7713b1edbc 5641 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5642
AnnaBridge 171:3a7713b1edbc 5643 /****************** UART Instances : Hardware Flow control ********************/
AnnaBridge 171:3a7713b1edbc 5644 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5645
AnnaBridge 171:3a7713b1edbc 5646 /****************** UART Instances : LIN mode ********************/
AnnaBridge 171:3a7713b1edbc 5647 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5648
AnnaBridge 171:3a7713b1edbc 5649 /****************** UART Instances : wakeup from stop mode ********************/
AnnaBridge 171:3a7713b1edbc 5650 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5651 /* Old macro definition maintained for legacy purpose */
AnnaBridge 171:3a7713b1edbc 5652 #define IS_UART_WAKEUP_INSTANCE IS_UART_WAKEUP_FROMSTOP_INSTANCE
AnnaBridge 171:3a7713b1edbc 5653
AnnaBridge 171:3a7713b1edbc 5654 /****************** UART Instances : Driver enable detection ********************/
AnnaBridge 171:3a7713b1edbc 5655 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
AnnaBridge 171:3a7713b1edbc 5656
AnnaBridge 171:3a7713b1edbc 5657 /****************************** WWDG Instances ********************************/
AnnaBridge 171:3a7713b1edbc 5658 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
AnnaBridge 171:3a7713b1edbc 5659
AnnaBridge 171:3a7713b1edbc 5660 /**
AnnaBridge 171:3a7713b1edbc 5661 * @}
AnnaBridge 171:3a7713b1edbc 5662 */
AnnaBridge 171:3a7713b1edbc 5663
AnnaBridge 171:3a7713b1edbc 5664
AnnaBridge 171:3a7713b1edbc 5665 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5666 /* For a painless codes migration between the STM32F0xx device product */
AnnaBridge 171:3a7713b1edbc 5667 /* lines, the aliases defined below are put in place to overcome the */
AnnaBridge 171:3a7713b1edbc 5668 /* differences in the interrupt handlers and IRQn definitions. */
AnnaBridge 171:3a7713b1edbc 5669 /* No need to update developed interrupt code when moving across */
AnnaBridge 171:3a7713b1edbc 5670 /* product lines within the same STM32F0 Family */
AnnaBridge 171:3a7713b1edbc 5671 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 5672
AnnaBridge 171:3a7713b1edbc 5673 /* Aliases for __IRQn */
AnnaBridge 171:3a7713b1edbc 5674 #define ADC1_COMP_IRQn ADC1_IRQn
AnnaBridge 171:3a7713b1edbc 5675 #define DMA1_Ch1_IRQn DMA1_Channel1_IRQn
AnnaBridge 171:3a7713b1edbc 5676 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQn DMA1_Channel2_3_IRQn
AnnaBridge 171:3a7713b1edbc 5677 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
AnnaBridge 171:3a7713b1edbc 5678 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQn DMA1_Channel4_5_IRQn
AnnaBridge 171:3a7713b1edbc 5679 #define VDDIO2_IRQn PVD_IRQn
AnnaBridge 171:3a7713b1edbc 5680 #define PVD_VDDIO2_IRQn PVD_IRQn
AnnaBridge 171:3a7713b1edbc 5681 #define RCC_CRS_IRQn RCC_IRQn
AnnaBridge 171:3a7713b1edbc 5682
AnnaBridge 171:3a7713b1edbc 5683
AnnaBridge 171:3a7713b1edbc 5684 /* Aliases for __IRQHandler */
AnnaBridge 171:3a7713b1edbc 5685 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
AnnaBridge 171:3a7713b1edbc 5686 #define DMA1_Ch1_IRQHandler DMA1_Channel1_IRQHandler
AnnaBridge 171:3a7713b1edbc 5687 #define DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler DMA1_Channel2_3_IRQHandler
AnnaBridge 171:3a7713b1edbc 5688 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
AnnaBridge 171:3a7713b1edbc 5689 #define DMA1_Ch4_7_DMA2_Ch3_5_IRQHandler DMA1_Channel4_5_IRQHandler
AnnaBridge 171:3a7713b1edbc 5690 #define VDDIO2_IRQHandler PVD_IRQHandler
AnnaBridge 171:3a7713b1edbc 5691 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler
AnnaBridge 171:3a7713b1edbc 5692 #define RCC_CRS_IRQHandler RCC_IRQHandler
AnnaBridge 171:3a7713b1edbc 5693
AnnaBridge 171:3a7713b1edbc 5694
AnnaBridge 171:3a7713b1edbc 5695 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 5696 }
AnnaBridge 171:3a7713b1edbc 5697 #endif /* __cplusplus */
AnnaBridge 171:3a7713b1edbc 5698
AnnaBridge 171:3a7713b1edbc 5699 #endif /* __STM32F031x6_H */
AnnaBridge 171:3a7713b1edbc 5700
AnnaBridge 171:3a7713b1edbc 5701 /**
AnnaBridge 171:3a7713b1edbc 5702 * @}
AnnaBridge 171:3a7713b1edbc 5703 */
AnnaBridge 171:3a7713b1edbc 5704
AnnaBridge 171:3a7713b1edbc 5705 /**
AnnaBridge 171:3a7713b1edbc 5706 * @}
AnnaBridge 171:3a7713b1edbc 5707 */
AnnaBridge 171:3a7713b1edbc 5708
AnnaBridge 171:3a7713b1edbc 5709 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/