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Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc
mbed library release version 165

Who changed what in which revision?

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AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 3 * @file gpio_map.h
AnnaBridge 171:3a7713b1edbc 4 * @brief GPIO HW register map
AnnaBridge 171:3a7713b1edbc 5 * @internal
AnnaBridge 171:3a7713b1edbc 6 * @author ON Semiconductor
AnnaBridge 171:3a7713b1edbc 7 * $Rev: 2115 $
AnnaBridge 171:3a7713b1edbc 8 * $Date: 2013-07-17 18:08:17 +0530 (Wed, 17 Jul 2013) $
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
AnnaBridge 171:3a7713b1edbc 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
AnnaBridge 171:3a7713b1edbc 12 * under limited terms and conditions. The terms and conditions pertaining to the software
AnnaBridge 171:3a7713b1edbc 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
AnnaBridge 171:3a7713b1edbc 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
AnnaBridge 171:3a7713b1edbc 15 * if applicable the software license agreement. Do not use this software and/or
AnnaBridge 171:3a7713b1edbc 16 * documentation unless you have carefully read and you agree to the limited terms and
AnnaBridge 171:3a7713b1edbc 17 * conditions. By using this software and/or documentation, you agree to the limited
AnnaBridge 171:3a7713b1edbc 18 * terms and conditions.
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
AnnaBridge 171:3a7713b1edbc 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 25 * @endinternal
AnnaBridge 171:3a7713b1edbc 26 *
AnnaBridge 171:3a7713b1edbc 27 * @ingroup gpio
AnnaBridge 171:3a7713b1edbc 28 *
AnnaBridge 171:3a7713b1edbc 29 * @details
AnnaBridge 171:3a7713b1edbc 30 * <p>
AnnaBridge 171:3a7713b1edbc 31 * GPIO HW register map description
AnnaBridge 171:3a7713b1edbc 32 * </p>
AnnaBridge 171:3a7713b1edbc 33 *
AnnaBridge 171:3a7713b1edbc 34 * <h1> Reference document(s) </h1>
AnnaBridge 171:3a7713b1edbc 35 * <p>
AnnaBridge 171:3a7713b1edbc 36 * <a href="../pdf/IPC7203_GPIO_APB_DS_v1P1.pdf" target="_blank">
AnnaBridge 171:3a7713b1edbc 37 * Reference document: IPC7203 APB GPIO Design Specification v1.2</a>
AnnaBridge 171:3a7713b1edbc 38 * </p>
AnnaBridge 171:3a7713b1edbc 39 */
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #ifndef GPIO_MAP_H_
AnnaBridge 171:3a7713b1edbc 42 #define GPIO_MAP_H_
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #include "architecture.h"
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /** Structure overlay for GPIO control registers, see memory_map.h
AnnaBridge 171:3a7713b1edbc 47 * For most registers, bit lockations match GPIO numbers.*/
AnnaBridge 171:3a7713b1edbc 48 typedef struct {
AnnaBridge 171:3a7713b1edbc 49 __IO uint32_t R_STATE_W_SET; /**< Read synchronized input / Write ones to bits to set corresponding output IO's*/
AnnaBridge 171:3a7713b1edbc 50 __IO uint32_t R_IRQ_W_CLEAR; /**< Read state of irq / Write ones to bits to clear corresponging output IO's */
AnnaBridge 171:3a7713b1edbc 51 __IO uint32_t W_OUT; /**< Write ones to set direction to output */
AnnaBridge 171:3a7713b1edbc 52 __IO uint32_t W_IN; /**< Write ones to set direction to input */
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t IRQ_ENABLE_SET; /**< Read active high irq enable / Write ones to enable irq */
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t IRQ_ENABLE_CLEAR; /**< Read active high irq enable / Write ones to disable irq */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t IRQ_EDGE; /**< Read irq configuration (edge or level) / Write ones to set irq to edge-sensitive */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t IRQ_LEVEL; /**< Read irq configuration (edge or level) / Write ones to set irq to level-sensitive */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t IRQ_POLARITY_SET; /**< Read irq polarity / Write ones to set irq to active high or rising edge */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t IRQ_POLARITY_CLEAR; /**< Read irq polarity / Write ones to set interrupts to active low or falling edge */
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t ANYEDGE_SET; /**< Read irq anyedge configuration / Write ones to override irq edge selection & irq on any edge */
AnnaBridge 171:3a7713b1edbc 60 __IO uint32_t ANYEDGE_CLEAR; /**< Read irq anyedge configuration / Write ones to clear edge selection override */
AnnaBridge 171:3a7713b1edbc 61 __IO uint32_t IRQ_CLEAR; /**< Write ones to clear edge-sensitive irq */
AnnaBridge 171:3a7713b1edbc 62 __IO uint32_t CONTROL; /**< Controls loopback/normal mode selection */
AnnaBridge 171:3a7713b1edbc 63 } GpioReg_t, *GpioReg_pt;
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 #endif /* GPIO_MAP_H_ */