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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/i2cs_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * @file
AnnaBridge 171:3a7713b1edbc 3 * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
AnnaBridge 171:3a7713b1edbc 4 */
AnnaBridge 171:3a7713b1edbc 5 /* ****************************************************************************
AnnaBridge 171:3a7713b1edbc 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 9 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 10 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 12 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 13 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 16 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 24 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 28 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 29 *
AnnaBridge 171:3a7713b1edbc 30 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 31 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 32 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 34 * ownership rights.
AnnaBridge 171:3a7713b1edbc 35 *
AnnaBridge 171:3a7713b1edbc 36 * $Date: 2016-10-10 18:59:48 -0500 (Mon, 10 Oct 2016) $
AnnaBridge 171:3a7713b1edbc 37 * $Revision: 24661 $
AnnaBridge 171:3a7713b1edbc 38 *
AnnaBridge 171:3a7713b1edbc 39 *************************************************************************** */
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /* Define to prevent redundant inclusion */
AnnaBridge 171:3a7713b1edbc 42 #ifndef _MXC_I2CS_REGS_H_
AnnaBridge 171:3a7713b1edbc 43 #define _MXC_I2CS_REGS_H_
AnnaBridge 171:3a7713b1edbc 44
AnnaBridge 171:3a7713b1edbc 45 /* **** Includes **** */
AnnaBridge 171:3a7713b1edbc 46 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 49 extern "C" {
AnnaBridge 171:3a7713b1edbc 50 #endif
AnnaBridge 171:3a7713b1edbc 51
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 ///@cond
AnnaBridge 171:3a7713b1edbc 54 /*
AnnaBridge 171:3a7713b1edbc 55 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 171:3a7713b1edbc 56 */
AnnaBridge 171:3a7713b1edbc 57 #ifndef __IO
AnnaBridge 171:3a7713b1edbc 58 #define __IO volatile
AnnaBridge 171:3a7713b1edbc 59 #endif
AnnaBridge 171:3a7713b1edbc 60 #ifndef __I
AnnaBridge 171:3a7713b1edbc 61 #define __I volatile const
AnnaBridge 171:3a7713b1edbc 62 #endif
AnnaBridge 171:3a7713b1edbc 63 #ifndef __O
AnnaBridge 171:3a7713b1edbc 64 #define __O volatile
AnnaBridge 171:3a7713b1edbc 65 #endif
AnnaBridge 171:3a7713b1edbc 66 #ifndef __RO
AnnaBridge 171:3a7713b1edbc 67 #define __RO volatile const
AnnaBridge 171:3a7713b1edbc 68 #endif
AnnaBridge 171:3a7713b1edbc 69 ///@endcond
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @ingroup i2cs
AnnaBridge 171:3a7713b1edbc 73 * @defgroup i2cs_registers Registers
AnnaBridge 171:3a7713b1edbc 74 * @brief Registers, Bit Masks and Bit Positions for the I2CS Peripheral Module.
AnnaBridge 171:3a7713b1edbc 75 * @{
AnnaBridge 171:3a7713b1edbc 76 */
AnnaBridge 171:3a7713b1edbc 77
AnnaBridge 171:3a7713b1edbc 78 /**
AnnaBridge 171:3a7713b1edbc 79 * Structure type to access the I2CS Peripheral Module Registers
AnnaBridge 171:3a7713b1edbc 80 */
AnnaBridge 171:3a7713b1edbc 81 typedef struct {
AnnaBridge 171:3a7713b1edbc 82 __IO uint32_t clk_div; /**< <tt>\b 0x0000:</tt> I2CS_CLK_DIV Register - Clock Divisor Control */
AnnaBridge 171:3a7713b1edbc 83 __IO uint32_t dev_id; /**< <tt>\b 0x0004:</tt> I2CS_DEV_ID Register - Device ID Register */
AnnaBridge 171:3a7713b1edbc 84 __IO uint32_t intfl; /**< <tt>\b 0x0008:</tt> I2CS_INTFL Register - Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 85 __IO uint32_t inten; /**< <tt>\b 0x000C:</tt> I2CS_INTEN Register - Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 86 __IO uint32_t data_byte[32]; /**< <tt>\b 0x0010-0x008C:</tt> I2CS_DATA_BYTE - Data Byte */
AnnaBridge 171:3a7713b1edbc 87 } mxc_i2cs_regs_t;
AnnaBridge 171:3a7713b1edbc 88 /**@} end of i2cs_registers */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /*
AnnaBridge 171:3a7713b1edbc 92 Register offsets for module I2CS.
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94 /**
AnnaBridge 171:3a7713b1edbc 95 * @ingroup i2cs_registers
AnnaBridge 171:3a7713b1edbc 96 * @defgroup I2CS_Register_Offsets Register Offsets
AnnaBridge 171:3a7713b1edbc 97 * @brief I2C Slave Register Offsets from the I2CS Base Peripheral Address.
AnnaBridge 171:3a7713b1edbc 98 * @{
AnnaBridge 171:3a7713b1edbc 99 */
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0000</tt> */
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0004</tt> */
AnnaBridge 171:3a7713b1edbc 102 #define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0008</tt> */
AnnaBridge 171:3a7713b1edbc 103 #define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x000C</tt> */
AnnaBridge 171:3a7713b1edbc 104 #define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) /**< Offset from I2CS Base Peripheral Address: <tt>\b 0x0010-0x008C</tt> */
AnnaBridge 171:3a7713b1edbc 105 /**@} I2CS_Register_Offsets */
AnnaBridge 171:3a7713b1edbc 106 /*
AnnaBridge 171:3a7713b1edbc 107 Field positions and masks for module I2CS.
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109 /**
AnnaBridge 171:3a7713b1edbc 110 * @ingroup i2cs_registers
AnnaBridge 171:3a7713b1edbc 111 * @defgroup I2CS_CLK_DIV_Register I2CS_CLK_DIV
AnnaBridge 171:3a7713b1edbc 112 * @brief Field Positions and Bit Masks for the I2CS_CLK_DIV register
AnnaBridge 171:3a7713b1edbc 113 * @{
AnnaBridge 171:3a7713b1edbc 114 */
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 /**< FS_FILTER_CLOCK_DIV Position */
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) /**< FS_FILTER_CLOCK_DIV Mask */
AnnaBridge 171:3a7713b1edbc 117 /**@} end group I2CS_CLK_DIV */
AnnaBridge 171:3a7713b1edbc 118 /**
AnnaBridge 171:3a7713b1edbc 119 * @ingroup i2cs_registers
AnnaBridge 171:3a7713b1edbc 120 * @defgroup I2CS_DEV_ID_Register I2CS_DEV_ID
AnnaBridge 171:3a7713b1edbc 121 * @brief Field Positions and Bit Masks for the I2CS_DEV_ID register
AnnaBridge 171:3a7713b1edbc 122 * @{
AnnaBridge 171:3a7713b1edbc 123 */
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 /**< SLAVE_DEV_ID Position */
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) /**< SLAVE_DEV_ID Mask */
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 /**< TEN_BIT_ID_MODE Position */
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) /**< TEN_BIT_ID_MODE Mask */
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 /**< SLAVE_RESET Position */
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) /**< SLAVE_RESET Mask */
AnnaBridge 171:3a7713b1edbc 130 /**@} end group I2CS_DEV_ID */
AnnaBridge 171:3a7713b1edbc 131 /**
AnnaBridge 171:3a7713b1edbc 132 * @ingroup i2cs_registers
AnnaBridge 171:3a7713b1edbc 133 * @defgroup I2CS_INTFL_Register I2CS_INTFL
AnnaBridge 171:3a7713b1edbc 134 * @brief Field Positions and Bit Masks for the I2CS_INTFL register
AnnaBridge 171:3a7713b1edbc 135 * @{
AnnaBridge 171:3a7713b1edbc 136 */
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_I2CS_INTFL_BYTE0_POS 0 /**< BYTE0 Position */
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) /**< BYTE0 Mask */
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_I2CS_INTFL_BYTE1_POS 1 /**< BYTE1 Position */
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) /**< BYTE1 Mask */
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_I2CS_INTFL_BYTE2_POS 2 /**< BYTE2 Position */
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) /**< BYTE2 Mask */
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_I2CS_INTFL_BYTE3_POS 3 /**< BYTE3 Position */
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) /**< BYTE3 Mask */
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_I2CS_INTFL_BYTE4_POS 4 /**< BYTE4 Position */
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) /**< BYTE4 Mask */
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_I2CS_INTFL_BYTE5_POS 5 /**< BYTE5 Position */
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) /**< BYTE5 Mask */
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_I2CS_INTFL_BYTE6_POS 6 /**< BYTE6 Position */
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) /**< BYTE6 Mask */
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_I2CS_INTFL_BYTE7_POS 7 /**< BYTE7 Position */
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) /**< BYTE7 Mask */
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_I2CS_INTFL_BYTE8_POS 8 /**< BYTE8 Position */
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) /**< BYTE8 Mask */
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_I2CS_INTFL_BYTE9_POS 9 /**< BYTE9 Position */
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) /**< BYTE9 Mask */
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_I2CS_INTFL_BYTE10_POS 10 /**< BYTE10 Position */
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) /**< BYTE10 Mask */
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_I2CS_INTFL_BYTE11_POS 11 /**< BYTE11 Position */
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) /**< BYTE11 Mask */
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_I2CS_INTFL_BYTE12_POS 12 /**< BYTE12 Position */
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) /**< BYTE12 Mask */
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_I2CS_INTFL_BYTE13_POS 13 /**< BYTE13 Position */
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) /**< BYTE13 Mask */
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_I2CS_INTFL_BYTE14_POS 14 /**< BYTE14 Position */
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) /**< BYTE14 Mask */
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_I2CS_INTFL_BYTE15_POS 15 /**< BYTE15 Position */
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) /**< BYTE15 Mask */
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_I2CS_INTFL_BYTE16_POS 16 /**< BYTE16 Position */
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) /**< BYTE16 Mask */
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_I2CS_INTFL_BYTE17_POS 17 /**< BYTE17 Position */
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) /**< BYTE17 Mask */
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_I2CS_INTFL_BYTE18_POS 18 /**< BYTE18 Position */
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) /**< BYTE18 Mask */
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_I2CS_INTFL_BYTE19_POS 19 /**< BYTE19 Position */
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) /**< BYTE19 Mask */
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_I2CS_INTFL_BYTE20_POS 20 /**< BYTE20 Position */
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) /**< BYTE20 Mask */
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_I2CS_INTFL_BYTE21_POS 21 /**< BYTE21 Position */
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) /**< BYTE21 Mask */
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_I2CS_INTFL_BYTE22_POS 22 /**< BYTE22 Position */
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) /**< BYTE22 Mask */
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_I2CS_INTFL_BYTE23_POS 23 /**< BYTE23 Position */
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) /**< BYTE23 Mask */
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_I2CS_INTFL_BYTE24_POS 24 /**< BYTE24 Position */
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) /**< BYTE24 Mask */
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_I2CS_INTFL_BYTE25_POS 25 /**< BYTE25 Position */
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) /**< BYTE25 Mask */
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_I2CS_INTFL_BYTE26_POS 26 /**< BYTE26 Position */
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) /**< BYTE26 Mask */
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_I2CS_INTFL_BYTE27_POS 27 /**< BYTE27 Position */
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) /**< BYTE27 Mask */
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_I2CS_INTFL_BYTE28_POS 28 /**< BYTE28 Position */
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) /**< BYTE28 Mask */
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_I2CS_INTFL_BYTE29_POS 29 /**< BYTE29 Position */
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) /**< BYTE29 Mask */
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_I2CS_INTFL_BYTE30_POS 30 /**< BYTE30 Position */
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) /**< BYTE30 Mask */
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_I2CS_INTFL_BYTE31_POS 31 /**< BYTE31 Position */
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) /**< BYTE31 Mask */
AnnaBridge 171:3a7713b1edbc 201 /**@} end group I2CS_INTFL */
AnnaBridge 171:3a7713b1edbc 202 /**
AnnaBridge 171:3a7713b1edbc 203 * @ingroup i2cs_registers
AnnaBridge 171:3a7713b1edbc 204 * @defgroup I2CS_INTEN_Register I2CS_INTEN
AnnaBridge 171:3a7713b1edbc 205 * @brief Field Positions and Bit Masks for the I2CS_INTEN register
AnnaBridge 171:3a7713b1edbc 206 * @{
AnnaBridge 171:3a7713b1edbc 207 */
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_I2CS_INTEN_BYTE0_POS 0 /**< BYTE0 Position */
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) /**< BYTE0 Mask */
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_I2CS_INTEN_BYTE1_POS 1 /**< BYTE1 Position */
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) /**< BYTE1 Mask */
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_I2CS_INTEN_BYTE2_POS 2 /**< BYTE2 Position */
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) /**< BYTE2 Mask */
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_I2CS_INTEN_BYTE3_POS 3 /**< BYTE3 Position */
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) /**< BYTE3 Mask */
AnnaBridge 171:3a7713b1edbc 216 #define MXC_F_I2CS_INTEN_BYTE4_POS 4 /**< BYTE4 Position */
AnnaBridge 171:3a7713b1edbc 217 #define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) /**< BYTE4 Mask */
AnnaBridge 171:3a7713b1edbc 218 #define MXC_F_I2CS_INTEN_BYTE5_POS 5 /**< BYTE5 Position */
AnnaBridge 171:3a7713b1edbc 219 #define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) /**< BYTE5 Mask */
AnnaBridge 171:3a7713b1edbc 220 #define MXC_F_I2CS_INTEN_BYTE6_POS 6 /**< BYTE6 Position */
AnnaBridge 171:3a7713b1edbc 221 #define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) /**< BYTE6 Mask */
AnnaBridge 171:3a7713b1edbc 222 #define MXC_F_I2CS_INTEN_BYTE7_POS 7 /**< BYTE7 Position */
AnnaBridge 171:3a7713b1edbc 223 #define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) /**< BYTE7 Mask */
AnnaBridge 171:3a7713b1edbc 224 #define MXC_F_I2CS_INTEN_BYTE8_POS 8 /**< BYTE8 Position */
AnnaBridge 171:3a7713b1edbc 225 #define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) /**< BYTE8 Mask */
AnnaBridge 171:3a7713b1edbc 226 #define MXC_F_I2CS_INTEN_BYTE9_POS 9 /**< BYTE9 Position */
AnnaBridge 171:3a7713b1edbc 227 #define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) /**< BYTE9 Mask */
AnnaBridge 171:3a7713b1edbc 228 #define MXC_F_I2CS_INTEN_BYTE10_POS 10 /**< BYTE10 Position */
AnnaBridge 171:3a7713b1edbc 229 #define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) /**< BYTE10 Mask */
AnnaBridge 171:3a7713b1edbc 230 #define MXC_F_I2CS_INTEN_BYTE11_POS 11 /**< BYTE11 Position */
AnnaBridge 171:3a7713b1edbc 231 #define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) /**< BYTE11 Mask */
AnnaBridge 171:3a7713b1edbc 232 #define MXC_F_I2CS_INTEN_BYTE12_POS 12 /**< BYTE12 Position */
AnnaBridge 171:3a7713b1edbc 233 #define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) /**< BYTE12 Mask */
AnnaBridge 171:3a7713b1edbc 234 #define MXC_F_I2CS_INTEN_BYTE13_POS 13 /**< BYTE13 Position */
AnnaBridge 171:3a7713b1edbc 235 #define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) /**< BYTE13 Mask */
AnnaBridge 171:3a7713b1edbc 236 #define MXC_F_I2CS_INTEN_BYTE14_POS 14 /**< BYTE14 Position */
AnnaBridge 171:3a7713b1edbc 237 #define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) /**< BYTE14 Mask */
AnnaBridge 171:3a7713b1edbc 238 #define MXC_F_I2CS_INTEN_BYTE15_POS 15 /**< BYTE15 Position */
AnnaBridge 171:3a7713b1edbc 239 #define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) /**< BYTE15 Mask */
AnnaBridge 171:3a7713b1edbc 240 #define MXC_F_I2CS_INTEN_BYTE16_POS 16 /**< BYTE16 Position */
AnnaBridge 171:3a7713b1edbc 241 #define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) /**< BYTE16 Mask */
AnnaBridge 171:3a7713b1edbc 242 #define MXC_F_I2CS_INTEN_BYTE17_POS 17 /**< BYTE17 Position */
AnnaBridge 171:3a7713b1edbc 243 #define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) /**< BYTE17 Mask */
AnnaBridge 171:3a7713b1edbc 244 #define MXC_F_I2CS_INTEN_BYTE18_POS 18 /**< BYTE18 Position */
AnnaBridge 171:3a7713b1edbc 245 #define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) /**< BYTE18 Mask */
AnnaBridge 171:3a7713b1edbc 246 #define MXC_F_I2CS_INTEN_BYTE19_POS 19 /**< BYTE19 Position */
AnnaBridge 171:3a7713b1edbc 247 #define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) /**< BYTE19 Mask */
AnnaBridge 171:3a7713b1edbc 248 #define MXC_F_I2CS_INTEN_BYTE20_POS 20 /**< BYTE20 Position */
AnnaBridge 171:3a7713b1edbc 249 #define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) /**< BYTE20 Mask */
AnnaBridge 171:3a7713b1edbc 250 #define MXC_F_I2CS_INTEN_BYTE21_POS 21 /**< BYTE21 Position */
AnnaBridge 171:3a7713b1edbc 251 #define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) /**< BYTE21 Mask */
AnnaBridge 171:3a7713b1edbc 252 #define MXC_F_I2CS_INTEN_BYTE22_POS 22 /**< BYTE22 Position */
AnnaBridge 171:3a7713b1edbc 253 #define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) /**< BYTE22 Mask */
AnnaBridge 171:3a7713b1edbc 254 #define MXC_F_I2CS_INTEN_BYTE23_POS 23 /**< BYTE23 Position */
AnnaBridge 171:3a7713b1edbc 255 #define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) /**< BYTE23 Mask */
AnnaBridge 171:3a7713b1edbc 256 #define MXC_F_I2CS_INTEN_BYTE24_POS 24 /**< BYTE24 Position */
AnnaBridge 171:3a7713b1edbc 257 #define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) /**< BYTE24 Mask */
AnnaBridge 171:3a7713b1edbc 258 #define MXC_F_I2CS_INTEN_BYTE25_POS 25 /**< BYTE25 Position */
AnnaBridge 171:3a7713b1edbc 259 #define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) /**< BYTE25 Mask */
AnnaBridge 171:3a7713b1edbc 260 #define MXC_F_I2CS_INTEN_BYTE26_POS 26 /**< BYTE26 Position */
AnnaBridge 171:3a7713b1edbc 261 #define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) /**< BYTE26 Mask */
AnnaBridge 171:3a7713b1edbc 262 #define MXC_F_I2CS_INTEN_BYTE27_POS 27 /**< BYTE27 Position */
AnnaBridge 171:3a7713b1edbc 263 #define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) /**< BYTE27 Mask */
AnnaBridge 171:3a7713b1edbc 264 #define MXC_F_I2CS_INTEN_BYTE28_POS 28 /**< BYTE28 Position */
AnnaBridge 171:3a7713b1edbc 265 #define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) /**< BYTE28 Mask */
AnnaBridge 171:3a7713b1edbc 266 #define MXC_F_I2CS_INTEN_BYTE29_POS 29 /**< BYTE29 Position */
AnnaBridge 171:3a7713b1edbc 267 #define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) /**< BYTE29 Mask */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_F_I2CS_INTEN_BYTE30_POS 30 /**< BYTE30 Position */
AnnaBridge 171:3a7713b1edbc 269 #define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) /**< BYTE30 Mask */
AnnaBridge 171:3a7713b1edbc 270 #define MXC_F_I2CS_INTEN_BYTE31_POS 31 /**< BYTE31 Position */
AnnaBridge 171:3a7713b1edbc 271 #define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) /**< BYTE31 Mask */
AnnaBridge 171:3a7713b1edbc 272 /**@} end group I2CS_INTEN */
AnnaBridge 171:3a7713b1edbc 273 /**
AnnaBridge 171:3a7713b1edbc 274 * @ingroup i2cs_registers
AnnaBridge 171:3a7713b1edbc 275 * @defgroup I2CS_DATA_BYTE_Register I2CS_DATA_BYTE
AnnaBridge 171:3a7713b1edbc 276 * @brief Field Positions and Bit Masks for the I2CS_DATA_BYTE register
AnnaBridge 171:3a7713b1edbc 277 * @{
AnnaBridge 171:3a7713b1edbc 278 */
AnnaBridge 171:3a7713b1edbc 279 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 /**< DATA_FIELD Position */
AnnaBridge 171:3a7713b1edbc 280 #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) /**< DATA_FIELD */
AnnaBridge 171:3a7713b1edbc 281 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 /**< READ_ONLY_FL Position */
AnnaBridge 171:3a7713b1edbc 282 #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) /**< READ_ONLY_FL */
AnnaBridge 171:3a7713b1edbc 283 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 /**< DATA_UPDATED_FL Position */
AnnaBridge 171:3a7713b1edbc 284 #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) /**< DATA_UPDATED_FL */
AnnaBridge 171:3a7713b1edbc 285 /**@} end group I2CS_DATA_BYTE */
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 288 }
AnnaBridge 171:3a7713b1edbc 289 #endif
AnnaBridge 171:3a7713b1edbc 290
AnnaBridge 171:3a7713b1edbc 291 #endif /* _MXC_I2CS_REGS_H_ */