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TARGET_MAX32630FTHR/TOOLCHAIN_IAR/i2cm_regs.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * @file |
AnnaBridge | 171:3a7713b1edbc | 3 | * @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module. |
AnnaBridge | 171:3a7713b1edbc | 4 | */ |
AnnaBridge | 171:3a7713b1edbc | 5 | |
AnnaBridge | 171:3a7713b1edbc | 6 | /* **************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 7 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
AnnaBridge | 171:3a7713b1edbc | 8 | * |
AnnaBridge | 171:3a7713b1edbc | 9 | * Permission is hereby granted, free of charge, to any person obtaining a |
AnnaBridge | 171:3a7713b1edbc | 10 | * copy of this software and associated documentation files (the "Software"), |
AnnaBridge | 171:3a7713b1edbc | 11 | * to deal in the Software without restriction, including without limitation |
AnnaBridge | 171:3a7713b1edbc | 12 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
AnnaBridge | 171:3a7713b1edbc | 13 | * and/or sell copies of the Software, and to permit persons to whom the |
AnnaBridge | 171:3a7713b1edbc | 14 | * Software is furnished to do so, subject to the following conditions: |
AnnaBridge | 171:3a7713b1edbc | 15 | * |
AnnaBridge | 171:3a7713b1edbc | 16 | * The above copyright notice and this permission notice shall be included |
AnnaBridge | 171:3a7713b1edbc | 17 | * in all copies or substantial portions of the Software. |
AnnaBridge | 171:3a7713b1edbc | 18 | * |
AnnaBridge | 171:3a7713b1edbc | 19 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
AnnaBridge | 171:3a7713b1edbc | 20 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 21 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
AnnaBridge | 171:3a7713b1edbc | 22 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 23 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
AnnaBridge | 171:3a7713b1edbc | 24 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
AnnaBridge | 171:3a7713b1edbc | 25 | * OTHER DEALINGS IN THE SOFTWARE. |
AnnaBridge | 171:3a7713b1edbc | 26 | * |
AnnaBridge | 171:3a7713b1edbc | 27 | * Except as contained in this notice, the name of Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 28 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
AnnaBridge | 171:3a7713b1edbc | 29 | * Products, Inc. Branding Policy. |
AnnaBridge | 171:3a7713b1edbc | 30 | * |
AnnaBridge | 171:3a7713b1edbc | 31 | * The mere transfer of this software does not imply any licenses |
AnnaBridge | 171:3a7713b1edbc | 32 | * of trade secrets, proprietary technology, copyrights, patents, |
AnnaBridge | 171:3a7713b1edbc | 33 | * trademarks, maskwork rights, or any other form of intellectual |
AnnaBridge | 171:3a7713b1edbc | 34 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
AnnaBridge | 171:3a7713b1edbc | 35 | * ownership rights. |
AnnaBridge | 171:3a7713b1edbc | 36 | * |
AnnaBridge | 171:3a7713b1edbc | 37 | * $Date: 2016-10-10 18:58:15 -0500 (Mon, 10 Oct 2016) $ |
AnnaBridge | 171:3a7713b1edbc | 38 | * $Revision: 24660 $ |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | *************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 41 | |
AnnaBridge | 171:3a7713b1edbc | 42 | /* Define to prevent redundant inclusion */ |
AnnaBridge | 171:3a7713b1edbc | 43 | #ifndef _MXC_I2CM_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 44 | #define _MXC_I2CM_REGS_H_ |
AnnaBridge | 171:3a7713b1edbc | 45 | |
AnnaBridge | 171:3a7713b1edbc | 46 | /* **** Includes **** */ |
AnnaBridge | 171:3a7713b1edbc | 47 | #include <stdint.h> |
AnnaBridge | 171:3a7713b1edbc | 48 | |
AnnaBridge | 171:3a7713b1edbc | 49 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 50 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 51 | #endif |
AnnaBridge | 171:3a7713b1edbc | 52 | |
AnnaBridge | 171:3a7713b1edbc | 53 | ///@cond |
AnnaBridge | 171:3a7713b1edbc | 54 | /* |
AnnaBridge | 171:3a7713b1edbc | 55 | If types are not defined elsewhere (CMSIS) define them here |
AnnaBridge | 171:3a7713b1edbc | 56 | */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #ifndef __IO |
AnnaBridge | 171:3a7713b1edbc | 58 | #define __IO volatile |
AnnaBridge | 171:3a7713b1edbc | 59 | #endif |
AnnaBridge | 171:3a7713b1edbc | 60 | #ifndef __I |
AnnaBridge | 171:3a7713b1edbc | 61 | #define __I volatile const |
AnnaBridge | 171:3a7713b1edbc | 62 | #endif |
AnnaBridge | 171:3a7713b1edbc | 63 | #ifndef __O |
AnnaBridge | 171:3a7713b1edbc | 64 | #define __O volatile |
AnnaBridge | 171:3a7713b1edbc | 65 | #endif |
AnnaBridge | 171:3a7713b1edbc | 66 | #ifndef __RO |
AnnaBridge | 171:3a7713b1edbc | 67 | #define __RO volatile const |
AnnaBridge | 171:3a7713b1edbc | 68 | #endif |
AnnaBridge | 171:3a7713b1edbc | 69 | |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | #define MXC_S_I2CM_TRANS_TAG_START 0x000 |
AnnaBridge | 171:3a7713b1edbc | 72 | #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100 |
AnnaBridge | 171:3a7713b1edbc | 73 | #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200 |
AnnaBridge | 171:3a7713b1edbc | 74 | #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400 |
AnnaBridge | 171:3a7713b1edbc | 75 | #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500 |
AnnaBridge | 171:3a7713b1edbc | 76 | #define MXC_S_I2CM_TRANS_TAG_STOP 0x700 |
AnnaBridge | 171:3a7713b1edbc | 77 | #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100 |
AnnaBridge | 171:3a7713b1edbc | 78 | #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200 |
AnnaBridge | 171:3a7713b1edbc | 79 | ///@endcond |
AnnaBridge | 171:3a7713b1edbc | 80 | |
AnnaBridge | 171:3a7713b1edbc | 81 | /** |
AnnaBridge | 171:3a7713b1edbc | 82 | * @ingroup i2cm |
AnnaBridge | 171:3a7713b1edbc | 83 | * @defgroup i2cm_registers Registers |
AnnaBridge | 171:3a7713b1edbc | 84 | * @brief Registers, Bit Masks and Bit Positions for the I2CM Peripheral Module. |
AnnaBridge | 171:3a7713b1edbc | 85 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 86 | */ |
AnnaBridge | 171:3a7713b1edbc | 87 | |
AnnaBridge | 171:3a7713b1edbc | 88 | /** |
AnnaBridge | 171:3a7713b1edbc | 89 | * Structure type to access the I2CM Peripheral Module Registers |
AnnaBridge | 171:3a7713b1edbc | 90 | */ |
AnnaBridge | 171:3a7713b1edbc | 91 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 92 | __IO uint32_t fs_clk_div; /**< <tt>\b 0x0000 </tt> \b I2CM_FS_CLK_DIV Register - Full Speed SCL Clock Settings */ |
AnnaBridge | 171:3a7713b1edbc | 93 | __RO uint32_t rsv004[2]; /**< <tt>\b 0x0004-0x0008 </tt> \b RESERVED \warning Do Not Modify, Read Only */ |
AnnaBridge | 171:3a7713b1edbc | 94 | __IO uint32_t timeout; /**< <tt>\b 0x000C </tt> \b I2CM_TIMEOUT Register - Timeout and Auto-Stop Settings */ |
AnnaBridge | 171:3a7713b1edbc | 95 | __IO uint32_t ctrl; /**< <tt>\b 0x0010 </tt> \b I2CM_CTRL Register - Master Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 96 | __IO uint32_t trans; /**< <tt>\b 0x0014 </tt> \b I2CM_TRANS Register - Master Transaction Start and Status Flags */ |
AnnaBridge | 171:3a7713b1edbc | 97 | __IO uint32_t intfl; /**< <tt>\b 0x0018 </tt> \b I2CM_INTFL Register - Master Interrupt Flags */ |
AnnaBridge | 171:3a7713b1edbc | 98 | __IO uint32_t inten; /**< <tt>\b 0x001C </tt> \b I2CM_INTEN Register - Master Interrupt Enable/Disable Controls */ |
AnnaBridge | 171:3a7713b1edbc | 99 | __RO uint32_t rsv020[2]; /**< <tt>\b 0x0020-0x0024 </tt> \b RESERVED \warning Do Not Modify, Read Only */ |
AnnaBridge | 171:3a7713b1edbc | 100 | __IO uint32_t bb; /**< <tt>\b 0x0028 </tt> \b I2CM_BB Register - Master Bit-Bang Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 101 | } mxc_i2cm_regs_t; |
AnnaBridge | 171:3a7713b1edbc | 102 | |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | /** |
AnnaBridge | 171:3a7713b1edbc | 105 | * Structure type for the I2CM Transmit and Receive FIFOs. |
AnnaBridge | 171:3a7713b1edbc | 106 | * The @c tx member is the write location for transmitting data and @c rx member is the read point for reading data. |
AnnaBridge | 171:3a7713b1edbc | 107 | * |
AnnaBridge | 171:3a7713b1edbc | 108 | */ |
AnnaBridge | 171:3a7713b1edbc | 109 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 110 | union { |
AnnaBridge | 171:3a7713b1edbc | 111 | __IO uint16_t tx; /**< tx FIFO address */ |
AnnaBridge | 171:3a7713b1edbc | 112 | __IO uint8_t tx_8[2048]; /**< 8-bit access to TX FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 113 | __IO uint16_t tx_16[1024]; /**< 16-bit access to TX FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 114 | __IO uint32_t tx_32[512]; /**< 32-bit access to TX FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 115 | }; |
AnnaBridge | 171:3a7713b1edbc | 116 | union { |
AnnaBridge | 171:3a7713b1edbc | 117 | __IO uint16_t rx; /**< RX FIFO address */ |
AnnaBridge | 171:3a7713b1edbc | 118 | __IO uint8_t rx_8[2048]; /**< 8-bit access to RX FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 119 | __IO uint16_t rx_16[1024]; /**< 16-bit access to RX FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 120 | __IO uint32_t rx_32[512]; /**< 32-bit access to RX FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 121 | }; |
AnnaBridge | 171:3a7713b1edbc | 122 | } mxc_i2cm_fifo_regs_t; |
AnnaBridge | 171:3a7713b1edbc | 123 | /**@} end of group i2cm_registers */ |
AnnaBridge | 171:3a7713b1edbc | 124 | |
AnnaBridge | 171:3a7713b1edbc | 125 | /* |
AnnaBridge | 171:3a7713b1edbc | 126 | Register offsets for module I2CM. |
AnnaBridge | 171:3a7713b1edbc | 127 | */ |
AnnaBridge | 171:3a7713b1edbc | 128 | /** |
AnnaBridge | 171:3a7713b1edbc | 129 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 130 | * @defgroup I2CM_Register_Offsets Register Offsets |
AnnaBridge | 171:3a7713b1edbc | 131 | * @brief I2C Master Register Offsets from the I2CM[n] Base Peripheral Address. |
AnnaBridge | 171:3a7713b1edbc | 132 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 133 | */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL) /**< Offset from I2CM Base Address: <tt>\b 0x0000</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL) /**< Offset from I2CM Base Address: <tt>\b 0x000C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL) /**< Offset from I2CM Base Address: <tt>\b 0x0010</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL) /**< Offset from I2CM Base Address: <tt>\b 0x0014</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL) /**< Offset from I2CM Base Address: <tt>\b 0x0018</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL) /**< Offset from I2CM Base Address: <tt>\b 0x001C</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL) /**< Offset from I2CM Base Address: <tt>\b 0x0028</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL) /**< Offset from I2CM FIFO Base Address: <tt>\b 0x0000</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL) /**< Offset from I2CM FIFO Base Address: <tt>\b 0x8000</tt> */ |
AnnaBridge | 171:3a7713b1edbc | 143 | /**@} end of group i2cm_registers */ |
AnnaBridge | 171:3a7713b1edbc | 144 | |
AnnaBridge | 171:3a7713b1edbc | 145 | /* |
AnnaBridge | 171:3a7713b1edbc | 146 | Field positions and masks for module I2CM. |
AnnaBridge | 171:3a7713b1edbc | 147 | */ |
AnnaBridge | 171:3a7713b1edbc | 148 | /** |
AnnaBridge | 171:3a7713b1edbc | 149 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 150 | * @defgroup I2CM_FS_CLK_DIV_Register I2CM_FS_CLK_DIV |
AnnaBridge | 171:3a7713b1edbc | 151 | * @brief Field Positions and Bit Masks for the I2CM_FS_CLK_DIV register |
AnnaBridge | 171:3a7713b1edbc | 152 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 153 | */ |
AnnaBridge | 171:3a7713b1edbc | 154 | #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS 0 /**< FS_FILTER_CLK_DIV Position */ |
AnnaBridge | 171:3a7713b1edbc | 155 | #define MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_FS_CLK_DIV_FS_FILTER_CLK_DIV_POS)) /**< FS_FILTER_CLK_DIV Mask */ |
AnnaBridge | 171:3a7713b1edbc | 156 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS 8 /**< FS_SCL_LO_CNT Position */ |
AnnaBridge | 171:3a7713b1edbc | 157 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_LO_CNT_POS)) /**< FS_SCL_LO_CNT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS 20 /**< FS_SCL_HI_CNT Position */ |
AnnaBridge | 171:3a7713b1edbc | 159 | #define MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_FS_CLK_DIV_FS_SCL_HI_CNT_POS)) /**< FS_SCL_HI_CNT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 160 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 161 | /** |
AnnaBridge | 171:3a7713b1edbc | 162 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 163 | * @defgroup I2CM_TIMEOUT_Register I2CM_TIMEOUT |
AnnaBridge | 171:3a7713b1edbc | 164 | * @brief Field Positions and Bit Masks for the I2CM_TIMEOUT register |
AnnaBridge | 171:3a7713b1edbc | 165 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 166 | */ |
AnnaBridge | 171:3a7713b1edbc | 167 | #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16 /**< TX_TIMEOUT Position */ |
AnnaBridge | 171:3a7713b1edbc | 168 | #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24 /**< AUTO_STOP_EN Position */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS)) /**< AUTO_STOP_EN Mask */ |
AnnaBridge | 171:3a7713b1edbc | 171 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 172 | /** |
AnnaBridge | 171:3a7713b1edbc | 173 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 174 | * @defgroup I2CM_CTRL_Register I2CM_CTRL |
AnnaBridge | 171:3a7713b1edbc | 175 | * @brief Field Positions and Bit Masks for the I2CM_CTRL register |
AnnaBridge | 171:3a7713b1edbc | 176 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 177 | */ |
AnnaBridge | 171:3a7713b1edbc | 178 | #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2 /**< TX_FIFO_EN Position */ |
AnnaBridge | 171:3a7713b1edbc | 179 | #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS)) /**< TX_FIFO_EN Mask */ |
AnnaBridge | 171:3a7713b1edbc | 180 | #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3 /**< RX_FIFO_EN Position */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS)) /**< RX_FIFO_EN Mask */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7 /**< MSTR_RESET_EN Position */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS)) /**< MSTR_RESET_EN Mask */ |
AnnaBridge | 171:3a7713b1edbc | 184 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 185 | /** |
AnnaBridge | 171:3a7713b1edbc | 186 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 187 | * @defgroup I2CM_TRANS_Register I2CM_TRANS |
AnnaBridge | 171:3a7713b1edbc | 188 | * @brief Field Positions and Bit Masks for the I2CM_TRANS register |
AnnaBridge | 171:3a7713b1edbc | 189 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define MXC_F_I2CM_TRANS_TX_START_POS 0 /**< TX_START Position */ |
AnnaBridge | 171:3a7713b1edbc | 192 | #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS)) /**< TX_START Mask */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1 /**< TX_IN_PROGRESS Position */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS)) /**< TX_IN_PROGRESS Mask */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define MXC_F_I2CM_TRANS_TX_DONE_POS 2 /**< TX_DONE Position */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS)) /**< TX_DONE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3 /**< TX_NACKED Position */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS)) /**< TX_NACKED Mask */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4 /**< TX_LOST_ARBITR Position */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5 /**< TX_TIMEOUT Position */ |
AnnaBridge | 171:3a7713b1edbc | 202 | #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 203 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 204 | /** |
AnnaBridge | 171:3a7713b1edbc | 205 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 206 | * @defgroup I2CM_INTFL_Register I2CM_INTFL |
AnnaBridge | 171:3a7713b1edbc | 207 | * @brief Field Positions and Bit Masks for the I2CM_INTFL register |
AnnaBridge | 171:3a7713b1edbc | 208 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 209 | */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define MXC_F_I2CM_INTFL_TX_DONE_POS 0 /**< TX_DONE Position */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS)) /**< TX_DONE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1 /**< TX_NACKED Position */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS)) /**< TX_NACKED Mask */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */ |
AnnaBridge | 171:3a7713b1edbc | 215 | #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */ |
AnnaBridge | 171:3a7713b1edbc | 217 | #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 218 | #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */ |
AnnaBridge | 171:3a7713b1edbc | 219 | #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */ |
AnnaBridge | 171:3a7713b1edbc | 221 | #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */ |
AnnaBridge | 171:3a7713b1edbc | 222 | #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */ |
AnnaBridge | 171:3a7713b1edbc | 224 | #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 226 | #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */ |
AnnaBridge | 171:3a7713b1edbc | 227 | #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */ |
AnnaBridge | 171:3a7713b1edbc | 229 | #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 230 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 231 | /** |
AnnaBridge | 171:3a7713b1edbc | 232 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 233 | * @defgroup I2CM_INTEN_Register I2CM_INTEN |
AnnaBridge | 171:3a7713b1edbc | 234 | * @brief Field Positions and Bit Masks for the I2CM_INTEN register |
AnnaBridge | 171:3a7713b1edbc | 235 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 236 | */ |
AnnaBridge | 171:3a7713b1edbc | 237 | #define MXC_F_I2CM_INTEN_TX_DONE_POS 0 /**< TX_DONE Position */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS)) /**< TX_DONE Mask */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1 /**< TX_NACKED Position */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS)) /**< TX_NACKED Mask */ |
AnnaBridge | 171:3a7713b1edbc | 241 | #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2 /**< TX_LOST_ARBITR Position */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS)) /**< TX_LOST_ARBITR Mask */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3 /**< TX_TIMEOUT Position */ |
AnnaBridge | 171:3a7713b1edbc | 244 | #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS)) /**< TX_TIMEOUT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4 /**< TX_FIFO_EMPTY Position */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS)) /**< TX_FIFO_EMPTY Mask */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5 /**< TX_FIFO_3Q_EMPTY Position */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS)) /**< TX_FIFO_3Q_EMPTY Mask */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS 6 /**< RX_FIFO_NOT_EMPTY Position */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_NOT_EMPTY_POS)) /**< RX_FIFO_NOT_EMPTY Mask */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7 /**< RX_FIFO_2Q_FULL Position */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS)) /**< RX_FIFO_2Q_FULL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8 /**< RX_FIFO_3Q_FULL Position */ |
AnnaBridge | 171:3a7713b1edbc | 254 | #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS)) /**< RX_FIFO_3Q_FULL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9 /**< RX_FIFO_FULL Position */ |
AnnaBridge | 171:3a7713b1edbc | 256 | #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS)) /**< RX_FIFO_FULL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 257 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 258 | /** |
AnnaBridge | 171:3a7713b1edbc | 259 | * @ingroup i2cm_registers |
AnnaBridge | 171:3a7713b1edbc | 260 | * @defgroup I2CM_BB_Register I2CM_BB |
AnnaBridge | 171:3a7713b1edbc | 261 | * @brief Field Positions and Bit Masks for the I2CM_BB register |
AnnaBridge | 171:3a7713b1edbc | 262 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 263 | */ |
AnnaBridge | 171:3a7713b1edbc | 264 | #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0 /**< BB_SCL_OUT Position */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS)) /**< BB_SCL_OUT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1 /**< BB_SDA_OUT Position */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS)) /**< BB_SDA_OUT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 268 | #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2 /**< BB_SCL_IN_VAL Position */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS)) /**< BB_SCL_IN_VAL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3 /**< BB_SDA_IN_VAL Position */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS)) /**< BB_SDA_IN_VAL Mask */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16 /**< RX_FIFO_CNT Position */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS)) /**< RX_FIFO_CNT Mask */ |
AnnaBridge | 171:3a7713b1edbc | 274 | /**@}*/ |
AnnaBridge | 171:3a7713b1edbc | 275 | |
AnnaBridge | 171:3a7713b1edbc | 276 | |
AnnaBridge | 171:3a7713b1edbc | 277 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 278 | } |
AnnaBridge | 171:3a7713b1edbc | 279 | #endif |
AnnaBridge | 171:3a7713b1edbc | 280 | |
AnnaBridge | 171:3a7713b1edbc | 281 | #endif /* _MXC_I2CM_REGS_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 282 |