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TARGET_MAX32600MBED/TOOLCHAIN_IAR/spi_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_SPI_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_SPI_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file spi_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup spi SPI
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 50 ====== ============================================ */
AnnaBridge 171:3a7713b1edbc 51 typedef struct {
AnnaBridge 171:3a7713b1edbc 52 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t ss_sr_polarity; /* 0x0004 Polarity Control for SS and SR Signals */
AnnaBridge 171:3a7713b1edbc 54 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
AnnaBridge 171:3a7713b1edbc 59 __I uint32_t rsv001C; /* 0x001C Deprecated - was SPI_AHB_RETRY */
AnnaBridge 171:3a7713b1edbc 60 } mxc_spi_regs_t;
AnnaBridge 171:3a7713b1edbc 61
AnnaBridge 171:3a7713b1edbc 62 /**
AnnaBridge 171:3a7713b1edbc 63 * @brief TX FIFO register. Can do 8, 16, or 32 bit access.
AnnaBridge 171:3a7713b1edbc 64 */
AnnaBridge 171:3a7713b1edbc 65 typedef struct {
AnnaBridge 171:3a7713b1edbc 66 union {
AnnaBridge 171:3a7713b1edbc 67 __O uint8_t txfifo_8;
AnnaBridge 171:3a7713b1edbc 68 __O uint16_t txfifo_16;
AnnaBridge 171:3a7713b1edbc 69 __O uint32_t txfifo_32;
AnnaBridge 171:3a7713b1edbc 70 };
AnnaBridge 171:3a7713b1edbc 71 } mxc_spi_txfifo_regs_t;
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 /**
AnnaBridge 171:3a7713b1edbc 74 * @brief RX FIFO register. Can do 8, 16, or 32 bit access.
AnnaBridge 171:3a7713b1edbc 75 */
AnnaBridge 171:3a7713b1edbc 76 typedef struct {
AnnaBridge 171:3a7713b1edbc 77 union {
AnnaBridge 171:3a7713b1edbc 78 __I uint8_t rxfifo_8;
AnnaBridge 171:3a7713b1edbc 79 __I uint16_t rxfifo_16;
AnnaBridge 171:3a7713b1edbc 80 __I uint32_t rxfifo_32;
AnnaBridge 171:3a7713b1edbc 81 };
AnnaBridge 171:3a7713b1edbc 82 } mxc_spi_rxfifo_regs_t;
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 /*
AnnaBridge 171:3a7713b1edbc 85 Register offsets for module SPI.
AnnaBridge 171:3a7713b1edbc 86 */
AnnaBridge 171:3a7713b1edbc 87 #define MXC_R_SPI_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 88 #define MXC_R_SPI_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 89 #define MXC_R_SPI_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 90 #define MXC_R_SPI_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 91 #define MXC_R_SPI_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 92 #define MXC_R_SPI_OFFS_INTFL ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 93 #define MXC_R_SPI_OFFS_INTEN ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 #define MXC_R_SPI_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 96 #define MXC_R_SPI_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98 /*
AnnaBridge 171:3a7713b1edbc 99 Field positions and masks for module SPI.
AnnaBridge 171:3a7713b1edbc 100 */
AnnaBridge 171:3a7713b1edbc 101 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS 0
AnnaBridge 171:3a7713b1edbc 102 #define MXC_F_SPI_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPI_MSTR_CFG_SLAVE_SEL_POS))
AnnaBridge 171:3a7713b1edbc 103 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS 3
AnnaBridge 171:3a7713b1edbc 104 #define MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_MSTR_CFG_THREE_WIRE_MODE_POS))
AnnaBridge 171:3a7713b1edbc 105 #define MXC_F_SPI_MSTR_CFG_SPI_MODE_POS 4
AnnaBridge 171:3a7713b1edbc 106 #define MXC_F_SPI_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_SPI_MODE_POS))
AnnaBridge 171:3a7713b1edbc 107 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS 6
AnnaBridge 171:3a7713b1edbc 108 #define MXC_F_SPI_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS))
AnnaBridge 171:3a7713b1edbc 109 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS 8
AnnaBridge 171:3a7713b1edbc 110 #define MXC_F_SPI_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_HI_CLK_POS))
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS 12
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_SPI_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_SCK_LO_CLK_POS))
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS 16
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_SPI_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_ACT_DELAY_POS))
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS 18
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_SPI_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPI_MSTR_CFG_INACT_DELAY_POS))
AnnaBridge 171:3a7713b1edbc 117 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS 20
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_HI_CLK_POS))
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS 24
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPI_MSTR_CFG_ALT_SCK_LO_CLK_POS))
AnnaBridge 171:3a7713b1edbc 121
AnnaBridge 171:3a7713b1edbc 122 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 123 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
AnnaBridge 171:3a7713b1edbc 124 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
AnnaBridge 171:3a7713b1edbc 125 #define MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 #define MXC_S_SPI_MSTR_CFG_PAGE_4B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 171:3a7713b1edbc 128 #define MXC_S_SPI_MSTR_CFG_PAGE_8B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 171:3a7713b1edbc 129 #define MXC_S_SPI_MSTR_CFG_PAGE_16B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 171:3a7713b1edbc 130 #define MXC_S_SPI_MSTR_CFG_PAGE_32B (MXC_V_SPI_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPI_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS 0
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_SS_POLARITY_POS))
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS 8
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPI_SS_SR_POLARITY_FC_POLARITY_POS))
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS 0
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_SPI_MSTR_EN_POS))
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS 1
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_SPI_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_TX_FIFO_EN_POS))
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS 2
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_SPI_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_RX_FIFO_EN_POS))
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS 3
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BIT_BANG_MODE_POS))
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS 4
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SS_IN_OUT_POS))
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS 5
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_SPI_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SR_IN_POS))
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS 6
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPI_GEN_CTRL_BB_SCK_IN_OUT_POS))
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS 8
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_IN_POS))
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS 12
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_OUT_POS))
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS 16
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_GEN_CTRL_BB_SDIO_DR_EN_POS))
AnnaBridge 171:3a7713b1edbc 157
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS 8
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_TX_FIFO_USED_POS))
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS 24
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPI_FIFO_CTRL_RX_FIFO_USED_POS))
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_SS_SAMPLE_MODE_POS))
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS 1
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_SPI_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPI_SPCL_CTRL_MISO_FC_EN_POS))
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPI_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_SPI_INTFL_TX_STALLED_POS 0
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_SPI_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_STALLED_POS))
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_SPI_INTFL_RX_STALLED_POS 1
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_SPI_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_STALLED_POS))
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_SPI_INTFL_TX_READY_POS 2
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_SPI_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_READY_POS))
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_SPI_INTFL_RX_DONE_POS 3
AnnaBridge 171:3a7713b1edbc 183 #define MXC_F_SPI_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_DONE_POS))
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_SPI_INTFL_TX_FIFO_AE_POS 4
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_SPI_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_TX_FIFO_AE_POS))
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_SPI_INTFL_RX_FIFO_AF_POS 5
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_SPI_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTFL_RX_FIFO_AF_POS))
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_SPI_INTEN_TX_STALLED_POS 0
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_SPI_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_STALLED_POS))
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_SPI_INTEN_RX_STALLED_POS 1
AnnaBridge 171:3a7713b1edbc 192 #define MXC_F_SPI_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_STALLED_POS))
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_SPI_INTEN_TX_READY_POS 2
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_SPI_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_READY_POS))
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_SPI_INTEN_RX_DONE_POS 3
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_SPI_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_DONE_POS))
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_SPI_INTEN_TX_FIFO_AE_POS 4
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_SPI_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_TX_FIFO_AE_POS))
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_SPI_INTEN_RX_FIFO_AF_POS 5
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_SPI_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPI_INTEN_RX_FIFO_AF_POS))
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 #define MXC_F_SPI_FIFO_DIR_POS 0
AnnaBridge 171:3a7713b1edbc 203 #define MXC_F_SPI_FIFO_DIR ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_DIR_POS))
AnnaBridge 171:3a7713b1edbc 204 #define MXC_F_SPI_FIFO_UNIT_POS 2
AnnaBridge 171:3a7713b1edbc 205 #define MXC_F_SPI_FIFO_UNIT ((uint32_t)(0x00000003UL << MXC_F_SPI_FIFO_UNIT_POS))
AnnaBridge 171:3a7713b1edbc 206 #define MXC_F_SPI_FIFO_SIZE_POS 4
AnnaBridge 171:3a7713b1edbc 207 #define MXC_F_SPI_FIFO_SIZE ((uint32_t)(0x0000000FUL << MXC_F_SPI_FIFO_SIZE_POS))
AnnaBridge 171:3a7713b1edbc 208 #define MXC_F_SPI_FIFO_WIDTH_POS 9
AnnaBridge 171:3a7713b1edbc 209 #define MXC_F_SPI_FIFO_WIDTH ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_WIDTH_POS))
AnnaBridge 171:3a7713b1edbc 210 #define MXC_F_SPI_FIFO_ALT_POS 11
AnnaBridge 171:3a7713b1edbc 211 #define MXC_F_SPI_FIFO_ALT ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_ALT_POS))
AnnaBridge 171:3a7713b1edbc 212 #define MXC_F_SPI_FIFO_FLOW_POS 12
AnnaBridge 171:3a7713b1edbc 213 #define MXC_F_SPI_FIFO_FLOW ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_FLOW_POS))
AnnaBridge 171:3a7713b1edbc 214 #define MXC_F_SPI_FIFO_DASS_POS 13
AnnaBridge 171:3a7713b1edbc 215 #define MXC_F_SPI_FIFO_DASS ((uint32_t)(0x00000001UL << MXC_F_SPI_FIFO_DASS_POS))
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 218 }
AnnaBridge 171:3a7713b1edbc 219 #endif
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 /**
AnnaBridge 171:3a7713b1edbc 222 * @}
AnnaBridge 171:3a7713b1edbc 223 */
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 #endif /* _MXC_SPI_REGS_H */