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TARGET_MAX32600MBED/TOOLCHAIN_IAR/max32600.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MAX32600_H_
AnnaBridge 171:3a7713b1edbc 35 #define _MAX32600_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 38
AnnaBridge 171:3a7713b1edbc 39 typedef enum IRQn_Type {
AnnaBridge 171:3a7713b1edbc 40 NonMaskableInt_IRQn = -14,
AnnaBridge 171:3a7713b1edbc 41 HardFault_IRQn = -13,
AnnaBridge 171:3a7713b1edbc 42 MemoryManagement_IRQn = -12,
AnnaBridge 171:3a7713b1edbc 43 BusFault_IRQn = -11,
AnnaBridge 171:3a7713b1edbc 44 UsageFault_IRQn = -10,
AnnaBridge 171:3a7713b1edbc 45 SVCall_IRQn = -5,
AnnaBridge 171:3a7713b1edbc 46 DebugMonitor_IRQn = -4,
AnnaBridge 171:3a7713b1edbc 47 PendSV_IRQn = -2,
AnnaBridge 171:3a7713b1edbc 48 SysTick_IRQn = -1,
AnnaBridge 171:3a7713b1edbc 49
AnnaBridge 171:3a7713b1edbc 50 /* Externals interrupts */
AnnaBridge 171:3a7713b1edbc 51 UART0_IRQn = 0, /* 16:01 UART0 */
AnnaBridge 171:3a7713b1edbc 52 UART1_IRQn, /* 17: 2 UART1 */
AnnaBridge 171:3a7713b1edbc 53 I2CM0_IRQn, /* 18: 3 I2C Master 0 */
AnnaBridge 171:3a7713b1edbc 54 I2CS_IRQn, /* 19: 4 I2C Slave */
AnnaBridge 171:3a7713b1edbc 55 USB_IRQn, /* 20: 5 USB */
AnnaBridge 171:3a7713b1edbc 56 PMU_IRQn, /* 21: 6 DMA */
AnnaBridge 171:3a7713b1edbc 57 AFE_IRQn, /* 22: 7 AFE */
AnnaBridge 171:3a7713b1edbc 58 MAA_IRQn, /* 23: 8 MAA */
AnnaBridge 171:3a7713b1edbc 59 AES_IRQn, /* 24: 9 AES */
AnnaBridge 171:3a7713b1edbc 60 SPI0_IRQn, /* 25:10 SPI0 */
AnnaBridge 171:3a7713b1edbc 61 SPI1_IRQn, /* 26:11 SPI1 */
AnnaBridge 171:3a7713b1edbc 62 SPI2_IRQn, /* 27:12 SPI2 */
AnnaBridge 171:3a7713b1edbc 63 TMR0_IRQn, /* 28:13 Timer32-0 */
AnnaBridge 171:3a7713b1edbc 64 TMR1_IRQn, /* 29:14 Timer32-1 */
AnnaBridge 171:3a7713b1edbc 65 TMR2_IRQn, /* 30:15 Timer32-1 */
AnnaBridge 171:3a7713b1edbc 66 TMR3_IRQn, /* 31:16 Timer32-2 */
AnnaBridge 171:3a7713b1edbc 67 RSVD0_IRQn, /* 32:17 RSVD */
AnnaBridge 171:3a7713b1edbc 68 RSVD1_IRQn, /* 33:18 RSVD */
AnnaBridge 171:3a7713b1edbc 69 DAC0_IRQn, /* 34:19 DAC0 (12-bit DAC) */
AnnaBridge 171:3a7713b1edbc 70 DAC1_IRQn, /* 35:20 DAC1 (12-bit DAC) */
AnnaBridge 171:3a7713b1edbc 71 DAC2_IRQn, /* 36:21 DAC2 (8-bit DAC) */
AnnaBridge 171:3a7713b1edbc 72 DAC3_IRQn, /* 37:22 DAC3 (8-bit DAC) */
AnnaBridge 171:3a7713b1edbc 73 ADC_IRQn, /* 38:23 ADC */
AnnaBridge 171:3a7713b1edbc 74 FLC_IRQn, /* 39:24 Flash Controller */
AnnaBridge 171:3a7713b1edbc 75 PWRMAN_IRQn, /* 40:25 PWRMAN */
AnnaBridge 171:3a7713b1edbc 76 CLKMAN_IRQn, /* 41:26 CLKMAN */
AnnaBridge 171:3a7713b1edbc 77 RTC0_IRQn, /* 42:27 RTC INT0 */
AnnaBridge 171:3a7713b1edbc 78 RTC1_IRQn, /* 43:28 RTC INT1 */
AnnaBridge 171:3a7713b1edbc 79 RTC2_IRQn, /* 44:29 RTC INT2 */
AnnaBridge 171:3a7713b1edbc 80 RTC3_IRQn, /* 45:30 RTC INT3 */
AnnaBridge 171:3a7713b1edbc 81 WDT0_IRQn, /* 46:31 WATCHDOG0 */
AnnaBridge 171:3a7713b1edbc 82 WDT0_P_IRQn, /* 47:32 WATCHDOG0 PRE-WINDOW */
AnnaBridge 171:3a7713b1edbc 83 WDT1_IRQn, /* 48:33 WATCHDOG1 */
AnnaBridge 171:3a7713b1edbc 84 WDT1_P_IRQn, /* 49:34 WATCHDOG1 PRE-WINDOW */
AnnaBridge 171:3a7713b1edbc 85 GPIO_P0_IRQn, /* 50:35 GPIO Port 0 */
AnnaBridge 171:3a7713b1edbc 86 GPIO_P1_IRQn, /* 51:36 GPIO Port 1 */
AnnaBridge 171:3a7713b1edbc 87 GPIO_P2_IRQn, /* 52:37 GPIO Port 2 */
AnnaBridge 171:3a7713b1edbc 88 GPIO_P3_IRQn, /* 53:38 GPIO Port 3 */
AnnaBridge 171:3a7713b1edbc 89 GPIO_P4_IRQn, /* 54:39 GPIO Port 4 */
AnnaBridge 171:3a7713b1edbc 90 GPIO_P5_IRQn, /* 55:40 GPIO Port 5 */
AnnaBridge 171:3a7713b1edbc 91 GPIO_P6_IRQn, /* 56:41 GPIO Port 6 */
AnnaBridge 171:3a7713b1edbc 92 GPIO_P7_IRQn, /* 57:42 GPIO Port 7 */
AnnaBridge 171:3a7713b1edbc 93 TMR16_0_IRQn, /* 58:43 Timer16-s0 */
AnnaBridge 171:3a7713b1edbc 94 TMR16_1_IRQn, /* 59:44 Timer16-s1 */
AnnaBridge 171:3a7713b1edbc 95 TMR16_2_IRQn, /* 60:45 Timer16-s2 */
AnnaBridge 171:3a7713b1edbc 96 TMR16_3_IRQn, /* 61:46 Timer16-s3 */
AnnaBridge 171:3a7713b1edbc 97 I2CM1_IRQn, /* 62:47 I2C Master 1 */
AnnaBridge 171:3a7713b1edbc 98 MXC_IRQ_EXT_COUNT,
AnnaBridge 171:3a7713b1edbc 99 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 104 /* ================ Processor and Core Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 105 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 108
AnnaBridge 171:3a7713b1edbc 109 #include <core_cm3.h> /* Processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 110 #include "system_max32600.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 113 /* ================== Device Specific Memory Section ================== */
AnnaBridge 171:3a7713b1edbc 114 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 #define MXC_FLASH_MEM_BASE 0x00000000UL
AnnaBridge 171:3a7713b1edbc 117 #define MXC_FLASH_PAGE_SIZE 0x1000 // 256 x 128b = 4KB
AnnaBridge 171:3a7713b1edbc 118 #define MXC_FLASH_MEM_SIZE 0x00040000UL
AnnaBridge 171:3a7713b1edbc 119 #define MXC_SYS_MEM_BASE 0x20000000UL
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 122 /* ================ Device Specific Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 123 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 124
AnnaBridge 171:3a7713b1edbc 125 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 126 /* General Purpose I/O Ports (GPIO) */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 #define MXC_BASE_GPIO ((uint32_t)0x40000000UL)
AnnaBridge 171:3a7713b1edbc 129 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
AnnaBridge 171:3a7713b1edbc 130 #define MXC_BASE_GPIO_BITBAND ((uint32_t)0x42000000UL)
AnnaBridge 171:3a7713b1edbc 131
AnnaBridge 171:3a7713b1edbc 132 #define MXC_GPIO_GET_IRQ(i) (((unsigned int)i) + GPIO_P0_IRQn)
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134
AnnaBridge 171:3a7713b1edbc 135 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 136 /* Pulse Train Generation */
AnnaBridge 171:3a7713b1edbc 137
AnnaBridge 171:3a7713b1edbc 138 #define MXC_CFG_PT_INSTANCES (13)
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 #define MXC_BASE_PTG ((uint32_t)0x40001000UL)
AnnaBridge 171:3a7713b1edbc 141 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
AnnaBridge 171:3a7713b1edbc 142 #define MXC_BASE_PT ((uint32_t)0x40001008UL)
AnnaBridge 171:3a7713b1edbc 143 #define MXC_PT ((mxc_pt_regs_t *)MXC_BASE_PT)
AnnaBridge 171:3a7713b1edbc 144 #define MXC_BASE_PT0 ((uint32_t)0x40001008UL)
AnnaBridge 171:3a7713b1edbc 145 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
AnnaBridge 171:3a7713b1edbc 146 #define MXC_BASE_PT1 ((uint32_t)0x40001010UL)
AnnaBridge 171:3a7713b1edbc 147 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
AnnaBridge 171:3a7713b1edbc 148 #define MXC_BASE_PT2 ((uint32_t)0x40001018UL)
AnnaBridge 171:3a7713b1edbc 149 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
AnnaBridge 171:3a7713b1edbc 150 #define MXC_BASE_PT3 ((uint32_t)0x40001020UL)
AnnaBridge 171:3a7713b1edbc 151 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
AnnaBridge 171:3a7713b1edbc 152 #define MXC_BASE_PT4 ((uint32_t)0x40001028UL)
AnnaBridge 171:3a7713b1edbc 153 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
AnnaBridge 171:3a7713b1edbc 154 #define MXC_BASE_PT5 ((uint32_t)0x40001030UL)
AnnaBridge 171:3a7713b1edbc 155 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
AnnaBridge 171:3a7713b1edbc 156 #define MXC_BASE_PT6 ((uint32_t)0x40001038UL)
AnnaBridge 171:3a7713b1edbc 157 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
AnnaBridge 171:3a7713b1edbc 158 #define MXC_BASE_PT7 ((uint32_t)0x40001040UL)
AnnaBridge 171:3a7713b1edbc 159 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
AnnaBridge 171:3a7713b1edbc 160 #define MXC_BASE_PT8 ((uint32_t)0x40001048UL)
AnnaBridge 171:3a7713b1edbc 161 #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
AnnaBridge 171:3a7713b1edbc 162 #define MXC_BASE_PT9 ((uint32_t)0x40001050UL)
AnnaBridge 171:3a7713b1edbc 163 #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
AnnaBridge 171:3a7713b1edbc 164 #define MXC_BASE_PT10 ((uint32_t)0x40001058UL)
AnnaBridge 171:3a7713b1edbc 165 #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
AnnaBridge 171:3a7713b1edbc 166 #define MXC_BASE_PT11 ((uint32_t)0x40001060UL)
AnnaBridge 171:3a7713b1edbc 167 #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /* PT12, PT13, PT14 are not used */
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 172 /* CRC-16/CRC-32 Engine */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 #define MXC_BASE_CRC ((uint32_t)0x40010000UL)
AnnaBridge 171:3a7713b1edbc 175 #define MXC_CRC_REGS ((mxc_crc_regs_t *)MXC_BASE_CRC)
AnnaBridge 171:3a7713b1edbc 176
AnnaBridge 171:3a7713b1edbc 177 #define MXC_BASE_CRC_DATA ((uint32_t)0x4010B000UL)
AnnaBridge 171:3a7713b1edbc 178 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 181 /* Trust Protection Unit (TPU) */
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 #define MXC_BASE_TPU ((uint32_t)0x40011000UL)
AnnaBridge 171:3a7713b1edbc 184 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 #define MXC_BASE_TPU_TSR ((uint32_t)0x40011C00UL)
AnnaBridge 171:3a7713b1edbc 187 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 190 /* AES Cryptographic Engine */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 #define MXC_BASE_AES ((uint32_t)0x40011400UL)
AnnaBridge 171:3a7713b1edbc 193 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
AnnaBridge 171:3a7713b1edbc 194
AnnaBridge 171:3a7713b1edbc 195 #define MXC_BASE_AES_MEM ((uint32_t)0x4010A000UL)
AnnaBridge 171:3a7713b1edbc 196 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
AnnaBridge 171:3a7713b1edbc 197
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 200 /* MAA Cryptographic Engine */
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 #define MXC_BASE_MAA ((uint32_t)0x40011800UL)
AnnaBridge 171:3a7713b1edbc 203 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 #define MXC_BASE_MAA_MEM ((uint32_t)0x4010A800UL)
AnnaBridge 171:3a7713b1edbc 206 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 209 /* 32-Bit PWM Timer/Counter */
AnnaBridge 171:3a7713b1edbc 210
AnnaBridge 171:3a7713b1edbc 211 #define MXC_CFG_TMR_INSTANCES (4)
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213 #define MXC_BASE_TMR0 ((uint32_t)0x40012000UL)
AnnaBridge 171:3a7713b1edbc 214 #define MXC_BASE_TMR0_BITBAND ((uint32_t)0x42240000UL)
AnnaBridge 171:3a7713b1edbc 215 #define MXC_TMR0 ((mxc_tmr_regs_t *) MXC_BASE_TMR0)
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 #define MXC_BASE_TMR1 ((uint32_t)0x40013000UL)
AnnaBridge 171:3a7713b1edbc 218 #define MXC_BASE_TMR1_BITBAND ((uint32_t)0x42260000UL)
AnnaBridge 171:3a7713b1edbc 219 #define MXC_TMR1 ((mxc_tmr_regs_t *) MXC_BASE_TMR1)
AnnaBridge 171:3a7713b1edbc 220
AnnaBridge 171:3a7713b1edbc 221 #define MXC_BASE_TMR2 ((uint32_t)0x40014000UL)
AnnaBridge 171:3a7713b1edbc 222 #define MXC_BASE_TMR2_BITBAND ((uint32_t)0x42280000UL)
AnnaBridge 171:3a7713b1edbc 223 #define MXC_TMR2 ((mxc_tmr_regs_t *) MXC_BASE_TMR2)
AnnaBridge 171:3a7713b1edbc 224
AnnaBridge 171:3a7713b1edbc 225 #define MXC_BASE_TMR3 ((uint32_t)0x40015000UL)
AnnaBridge 171:3a7713b1edbc 226 #define MXC_BASE_TMR3_BITBAND ((uint32_t)0x422A0000UL)
AnnaBridge 171:3a7713b1edbc 227 #define MXC_TMR3 ((mxc_tmr_regs_t *) MXC_BASE_TMR3)
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 #define MXC_TMR_GET_IRQ_32(i) ((i) == 0 ? TMR0_IRQn : \
AnnaBridge 171:3a7713b1edbc 231 (i) == 1 ? TMR1_IRQn : \
AnnaBridge 171:3a7713b1edbc 232 (i) == 2 ? TMR2_IRQn : \
AnnaBridge 171:3a7713b1edbc 233 (i) == 3 ? TMR3_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 234
AnnaBridge 171:3a7713b1edbc 235 #define MXC_TMR_GET_IRQ_16(i) ((i) == 0 ? TMR0_IRQn : \
AnnaBridge 171:3a7713b1edbc 236 (i) == 1 ? TMR1_IRQn : \
AnnaBridge 171:3a7713b1edbc 237 (i) == 2 ? TMR2_IRQn : \
AnnaBridge 171:3a7713b1edbc 238 (i) == 3 ? TMR3_IRQn : \
AnnaBridge 171:3a7713b1edbc 239 (i) == 4 ? TMR16_0_IRQn : \
AnnaBridge 171:3a7713b1edbc 240 (i) == 5 ? TMR16_1_IRQn : \
AnnaBridge 171:3a7713b1edbc 241 (i) == 6 ? TMR16_2_IRQn : \
AnnaBridge 171:3a7713b1edbc 242 (i) == 7 ? TMR16_3_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
AnnaBridge 171:3a7713b1edbc 245 (i) == 1 ? MXC_BASE_TMR1 : \
AnnaBridge 171:3a7713b1edbc 246 (i) == 2 ? MXC_BASE_TMR2 : \
AnnaBridge 171:3a7713b1edbc 247 (i) == 3 ? MXC_BASE_TMR3 : 0)
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
AnnaBridge 171:3a7713b1edbc 250 (i) == 1 ? MXC_TMR1 : \
AnnaBridge 171:3a7713b1edbc 251 (i) == 2 ? MXC_TMR2 : \
AnnaBridge 171:3a7713b1edbc 252 (i) == 3 ? MXC_TMR3 : 0)
AnnaBridge 171:3a7713b1edbc 253 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 254 /* Watchdog Timer */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 #define MXC_CFG_WDT_INSTANCES (2)
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 #define MXC_BASE_WDT0 ((uint32_t)0x40021000UL)
AnnaBridge 171:3a7713b1edbc 259 #define MXC_BASE_WDT0_BITBAND ((uint32_t)0x42420000UL)
AnnaBridge 171:3a7713b1edbc 260 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 #define MXC_BASE_WDT1 ((uint32_t)0x40022000UL)
AnnaBridge 171:3a7713b1edbc 263 #define MXC_BASE_WDT1_BITBAND ((uint32_t)0x42440000UL)
AnnaBridge 171:3a7713b1edbc 264 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 #define MXC_WDT_GET_IRQ(i) ((i) == 0 ? WDT0_IRQn : \
AnnaBridge 171:3a7713b1edbc 267 (i) == 1 ? WDT1_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 #define MXC_WDT_GET_IRQ_P(i) ((i) == 0 ? WDT0_P_IRQn : \
AnnaBridge 171:3a7713b1edbc 270 (i) == 1 ? WDT1_P_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
AnnaBridge 171:3a7713b1edbc 273 (i) == 1 ? MXC_BASE_WDT1 : 0)
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
AnnaBridge 171:3a7713b1edbc 276 (i) == 1 ? MXC_WDT1 : 0)
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 279 /* SPI Interface */
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 #define MXC_CFG_SPI_INSTANCES (3)
AnnaBridge 171:3a7713b1edbc 282 #define MXC_CFG_SPI_FIFO_DEPTH (16)
AnnaBridge 171:3a7713b1edbc 283
AnnaBridge 171:3a7713b1edbc 284 #define MXC_BASE_SPI0 ((uint32_t)0x40030000UL)
AnnaBridge 171:3a7713b1edbc 285 #define MXC_SPI0 ((mxc_spi_regs_t *)MXC_BASE_SPI0)
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287 #define MXC_BASE_SPI0_TXFIFO ((uint32_t)0x40100000UL)
AnnaBridge 171:3a7713b1edbc 288 #define MXC_SPI0_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI0_TXFIFO)
AnnaBridge 171:3a7713b1edbc 289 #define MXC_BASE_SPI0_RXFIFO ((uint32_t)0x40100800UL)
AnnaBridge 171:3a7713b1edbc 290 #define MXC_SPI0_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI0_RXFIFO)
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292 #define MXC_BASE_SPI1 ((uint32_t)0x40031000UL)
AnnaBridge 171:3a7713b1edbc 293 #define MXC_SPI1 ((mxc_spi_regs_t *)MXC_BASE_SPI1)
AnnaBridge 171:3a7713b1edbc 294
AnnaBridge 171:3a7713b1edbc 295 #define MXC_BASE_SPI1_TXFIFO ((uint32_t)0x40101000UL)
AnnaBridge 171:3a7713b1edbc 296 #define MXC_SPI1_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI1_TXFIFO)
AnnaBridge 171:3a7713b1edbc 297 #define MXC_BASE_SPI1_RXFIFO ((uint32_t)0x40101800UL)
AnnaBridge 171:3a7713b1edbc 298 #define MXC_SPI1_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI1_RXFIFO)
AnnaBridge 171:3a7713b1edbc 299
AnnaBridge 171:3a7713b1edbc 300 #define MXC_BASE_SPI2 ((uint32_t)0x40032000UL)
AnnaBridge 171:3a7713b1edbc 301 #define MXC_SPI2 ((mxc_spi_regs_t *)MXC_BASE_SPI2)
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 #define MXC_BASE_SPI2_TXFIFO ((uint32_t)0x40102000UL)
AnnaBridge 171:3a7713b1edbc 304 #define MXC_SPI2_TXFIFO ((mxc_spi_txfifo_regs_t *)MXC_BASE_SPI2_TXFIFO)
AnnaBridge 171:3a7713b1edbc 305 #define MXC_BASE_SPI2_RXFIFO ((uint32_t)0x40102800UL)
AnnaBridge 171:3a7713b1edbc 306 #define MXC_SPI2_RXFIFO ((mxc_spi_rxfifo_regs_t *)MXC_BASE_SPI2_RXFIFO)
AnnaBridge 171:3a7713b1edbc 307
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 #define MXC_SPI_GET_IRQ(i) ((i) == 0 ? SPI0_IRQn : \
AnnaBridge 171:3a7713b1edbc 310 (i) == 1 ? SPI1_IRQn : \
AnnaBridge 171:3a7713b1edbc 311 (i) == 2 ? SPI2_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 #define MXC_SPI_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPI0 : \
AnnaBridge 171:3a7713b1edbc 314 (i) == 1 ? MXC_BASE_SPI1 : \
AnnaBridge 171:3a7713b1edbc 315 (i) == 2 ? MXC_BASE_SPI2 : 0)
AnnaBridge 171:3a7713b1edbc 316
AnnaBridge 171:3a7713b1edbc 317 #define MXC_SPI_GET_SPI(i) ((i) == 0 ? MXC_SPI0 : \
AnnaBridge 171:3a7713b1edbc 318 (i) == 1 ? MXC_SPI1 : \
AnnaBridge 171:3a7713b1edbc 319 (i) == 2 ? MXC_SPI2 : 0)
AnnaBridge 171:3a7713b1edbc 320
AnnaBridge 171:3a7713b1edbc 321 #define MXC_SPI_GET_RXFIFO(i) ((i) == 0 ? MXC_SPI0_RXFIFO : \
AnnaBridge 171:3a7713b1edbc 322 (i) == 1 ? MXC_SPI1_RXFIFO : \
AnnaBridge 171:3a7713b1edbc 323 (i) == 2 ? MXC_SPI2_RXFIFO : 0)
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 #define MXC_SPI_GET_TXFIFO(i) ((i) == 0 ? MXC_SPI0_TXFIFO : \
AnnaBridge 171:3a7713b1edbc 326 (i) == 1 ? MXC_SPI1_TXFIFO : \
AnnaBridge 171:3a7713b1edbc 327 (i) == 2 ? MXC_SPI2_TXFIFO : 0)
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329 #define MXC_SPI_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_SPI0)
AnnaBridge 171:3a7713b1edbc 330 #define MXC_SPI_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00003000) >> 12)
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332
AnnaBridge 171:3a7713b1edbc 333 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 334 /* UART Interface */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 #define MXC_CFG_UART_INSTANCES (2)
AnnaBridge 171:3a7713b1edbc 337
AnnaBridge 171:3a7713b1edbc 338 #define MXC_BASE_UART0 ((uint32_t)0x40038000UL)
AnnaBridge 171:3a7713b1edbc 339 #define MXC_BASE_UART0_BITBAND ((uint32_t)0x42700000UL)
AnnaBridge 171:3a7713b1edbc 340 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
AnnaBridge 171:3a7713b1edbc 341
AnnaBridge 171:3a7713b1edbc 342 #define MXC_BASE_UART1 ((uint32_t)0x40039000UL)
AnnaBridge 171:3a7713b1edbc 343 #define MXC_BASE_UART1_BITBAND ((uint32_t)0x42720000UL)
AnnaBridge 171:3a7713b1edbc 344 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346
AnnaBridge 171:3a7713b1edbc 347 #define MXC_UART_GET_IRQ(i) ((i) == 0 ? UART0_IRQn : \
AnnaBridge 171:3a7713b1edbc 348 (i) == 1 ? UART1_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 349
AnnaBridge 171:3a7713b1edbc 350 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
AnnaBridge 171:3a7713b1edbc 351 (i) == 1 ? MXC_BASE_UART1 : 0)
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
AnnaBridge 171:3a7713b1edbc 354 (i) == 1 ? MXC_UART1 : 0)
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 #define MXC_UART_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 12) + MXC_BASE_UART0)
AnnaBridge 171:3a7713b1edbc 357 #define MXC_UART_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00001000) >> 12)
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359
AnnaBridge 171:3a7713b1edbc 360 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 361 /* I2C Master Interface */
AnnaBridge 171:3a7713b1edbc 362
AnnaBridge 171:3a7713b1edbc 363 #define MXC_CFG_I2CM_INSTANCES (2)
AnnaBridge 171:3a7713b1edbc 364
AnnaBridge 171:3a7713b1edbc 365 #define MXC_BASE_I2CM0 ((uint32_t)0x40040000UL)
AnnaBridge 171:3a7713b1edbc 366 #define MXC_BASE_I2CM0_BITBAND ((uint32_t)0x42800000UL)
AnnaBridge 171:3a7713b1edbc 367 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
AnnaBridge 171:3a7713b1edbc 368 #define MXC_BASE_I2CM0_TX_FIFO ((uint32_t)0x40103000UL)
AnnaBridge 171:3a7713b1edbc 369 #define MXC_BASE_I2CM0_RX_FIFO ((uint32_t)0x40103800UL)
AnnaBridge 171:3a7713b1edbc 370
AnnaBridge 171:3a7713b1edbc 371 #define MXC_BASE_I2CM1 ((uint32_t)0x40042000UL)
AnnaBridge 171:3a7713b1edbc 372 #define MXC_BASE_I2CM1_BITBAND ((uint32_t)0x42840000UL)
AnnaBridge 171:3a7713b1edbc 373 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
AnnaBridge 171:3a7713b1edbc 374 #define MXC_BASE_I2CM1_TX_FIFO ((uint32_t)0x4010D000UL)
AnnaBridge 171:3a7713b1edbc 375 #define MXC_BASE_I2CM1_RX_FIFO ((uint32_t)0x4010D800UL)
AnnaBridge 171:3a7713b1edbc 376
AnnaBridge 171:3a7713b1edbc 377 #define MXC_I2CM_GET_IRQ(i) ((i) == 0 ? I2CM0_IRQn : \
AnnaBridge 171:3a7713b1edbc 378 (i) == 1 ? I2CM1_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 379
AnnaBridge 171:3a7713b1edbc 380 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
AnnaBridge 171:3a7713b1edbc 381 (i) == 1 ? MXC_BASE_I2CM1 : 0)
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
AnnaBridge 171:3a7713b1edbc 384 (i) == 1 ? MXC_I2CM1 : 0)
AnnaBridge 171:3a7713b1edbc 385
AnnaBridge 171:3a7713b1edbc 386 #define MXC_I2CM_GET_BASE_TX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_TX_FIFO : \
AnnaBridge 171:3a7713b1edbc 387 (i) == 1 ? MXC_BASE_I2CM1_TX_FIFO : 0)
AnnaBridge 171:3a7713b1edbc 388
AnnaBridge 171:3a7713b1edbc 389 #define MXC_I2CM_GET_BASE_RX_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_RX_FIFO : \
AnnaBridge 171:3a7713b1edbc 390 (i) == 1 ? MXC_BASE_I2CM1_RX_FIFO : 0)
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392 #define MXC_I2CM_INSTANCE_TO_BASE(instance) (((uint32_t)(instance) << 13) + MXC_BASE_I2CM0)
AnnaBridge 171:3a7713b1edbc 393 #define MXC_I2CM_BASE_TO_INSTANCE(base) (((uint32_t)(base) & 0x00002000) >> 13)
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 397 /* I2C Slave Interface */
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 #define MXC_CFG_I2CS_INSTANCES (1)
AnnaBridge 171:3a7713b1edbc 400
AnnaBridge 171:3a7713b1edbc 401 #define MXC_BASE_I2CS0 ((uint32_t)0x40041000UL)
AnnaBridge 171:3a7713b1edbc 402 #define MXC_BASE_I2CS0_BITBAND ((uint32_t)0x42820000UL)
AnnaBridge 171:3a7713b1edbc 403 #define MXC_I2CS0 ((mxc_i2cs_regs_t *)MXC_BASE_I2CS0)
AnnaBridge 171:3a7713b1edbc 404
AnnaBridge 171:3a7713b1edbc 405 #define MXC_BASE_I2CS0_FIFO ((uint32_t)0x40104000UL)
AnnaBridge 171:3a7713b1edbc 406 #define MXC_I2CS0_FIFO ((mxc_i2cs_fifo_regs_t *)MXC_BASE_I2CS0)
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408
AnnaBridge 171:3a7713b1edbc 409
AnnaBridge 171:3a7713b1edbc 410 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 411 /* DACs */
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 #define MXC_CFG_DAC_INSTANCES (4)
AnnaBridge 171:3a7713b1edbc 414 #define MXC_CFG_DAC_FIFO_DEPTH (32)
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 #define MXC_BASE_DAC0 ((uint32_t)0x40050000UL)
AnnaBridge 171:3a7713b1edbc 417 #define MXC_DAC0 ((mxc_dac_regs_t *)MXC_BASE_DAC0)
AnnaBridge 171:3a7713b1edbc 418 #define MXC_BASE_DAC0_FIFO ((uint32_t)0x40105000UL)
AnnaBridge 171:3a7713b1edbc 419 #define MXC_DAC0_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC0_FIFO)
AnnaBridge 171:3a7713b1edbc 420 #define MXC_DAC0_WIDTH ((uint8_t)(2))
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 #define MXC_BASE_DAC1 ((uint32_t)0x40051000UL)
AnnaBridge 171:3a7713b1edbc 423 #define MXC_DAC1 ((mxc_dac_regs_t *)MXC_BASE_DAC1)
AnnaBridge 171:3a7713b1edbc 424 #define MXC_BASE_DAC1_FIFO ((uint32_t)0x40106000UL)
AnnaBridge 171:3a7713b1edbc 425 #define MXC_DAC1_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC1_FIFO)
AnnaBridge 171:3a7713b1edbc 426 #define MXC_DAC1_WIDTH ((uint8_t)(2))
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 #define MXC_BASE_DAC2 ((uint32_t)0x40052000UL)
AnnaBridge 171:3a7713b1edbc 429 #define MXC_DAC2 ((mxc_dac_regs_t *)MXC_BASE_DAC2)
AnnaBridge 171:3a7713b1edbc 430 #define MXC_BASE_DAC2_FIFO ((uint32_t)0x40107000UL)
AnnaBridge 171:3a7713b1edbc 431 #define MXC_DAC2_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC2_FIFO)
AnnaBridge 171:3a7713b1edbc 432 #define MXC_DAC2_WIDTH ((uint8_t)(1))
AnnaBridge 171:3a7713b1edbc 433
AnnaBridge 171:3a7713b1edbc 434 #define MXC_BASE_DAC3 ((uint32_t)0x40053000UL)
AnnaBridge 171:3a7713b1edbc 435 #define MXC_DAC3 ((mxc_dac_regs_t *)MXC_BASE_DAC3)
AnnaBridge 171:3a7713b1edbc 436 #define MXC_BASE_DAC3_FIFO ((uint32_t)0x40108000UL)
AnnaBridge 171:3a7713b1edbc 437 #define MXC_DAC3_FIFO ((mxc_dac_fifo_regs_t *)MXC_BASE_DAC3_FIFO)
AnnaBridge 171:3a7713b1edbc 438 #define MXC_DAC3_WIDTH ((uint8_t)(1))
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440
AnnaBridge 171:3a7713b1edbc 441 #define MXC_DAC_GET_IRQ(i) ((i) == 0 ? DAC0_IRQn : \
AnnaBridge 171:3a7713b1edbc 442 (i) == 1 ? DAC1_IRQn : \
AnnaBridge 171:3a7713b1edbc 443 (i) == 2 ? DAC2_IRQn : \
AnnaBridge 171:3a7713b1edbc 444 (i) == 3 ? DAC3_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 445
AnnaBridge 171:3a7713b1edbc 446
AnnaBridge 171:3a7713b1edbc 447 #define MXC_DAC_GET_BASE(i) (i == 0 ? MXC_BASE_DAC0 : \
AnnaBridge 171:3a7713b1edbc 448 i == 1 ? MXC_BASE_DAC1 : \
AnnaBridge 171:3a7713b1edbc 449 i == 2 ? MXC_BASE_DAC2 : \
AnnaBridge 171:3a7713b1edbc 450 i == 3 ? MXC_BASE_DAC3 : 0)
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 #define MXC_DAC_GET_FIFO(i) (i == 0 ? MXC_BASE_DAC0_FIFO : \
AnnaBridge 171:3a7713b1edbc 453 i == 1 ? MXC_BASE_DAC1_FIFO : \
AnnaBridge 171:3a7713b1edbc 454 i == 2 ? MXC_BASE_DAC2_FIFO : \
AnnaBridge 171:3a7713b1edbc 455 i == 3 ? MXC_BASE_DAC3_FIFO : 0)
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #define MXC_DAC_GET_PMU_FIFO_IRQ(i) (i == 0 ? PMU_IRQ_DAC0_FIFO_AE : \
AnnaBridge 171:3a7713b1edbc 458 i == 1 ? PMU_IRQ_DAC1_FIFO_AE : \
AnnaBridge 171:3a7713b1edbc 459 i == 2 ? PMU_IRQ_DAC2_FIFO_AE : \
AnnaBridge 171:3a7713b1edbc 460 i == 3 ? PMU_IRQ_DAC3_FIFO_AE : 0)
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 #define MXC_DAC_GET_DAC(i) (i == 0 ? MXC_DAC0 : \
AnnaBridge 171:3a7713b1edbc 463 i == 1 ? MXC_DAC1 : \
AnnaBridge 171:3a7713b1edbc 464 i == 2 ? MXC_DAC2 : \
AnnaBridge 171:3a7713b1edbc 465 i == 3 ? MXC_DAC3 : 0)
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 #define MXC_DAC_GET_WIDTH(i) (i == 0 ? MXC_DAC0_WIDTH : \
AnnaBridge 171:3a7713b1edbc 468 i == 1 ? MXC_DAC1_WIDTH : \
AnnaBridge 171:3a7713b1edbc 469 i == 2 ? MXC_DAC2_WIDTH : \
AnnaBridge 171:3a7713b1edbc 470 i == 3 ? MXC_DAC3_WIDTH : 0)
AnnaBridge 171:3a7713b1edbc 471
AnnaBridge 171:3a7713b1edbc 472
AnnaBridge 171:3a7713b1edbc 473 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 474 /* Analog Front End */
AnnaBridge 171:3a7713b1edbc 475
AnnaBridge 171:3a7713b1edbc 476 #define MXC_BASE_AFE ((uint32_t)0x4005401CUL)
AnnaBridge 171:3a7713b1edbc 477 #define MXC_AFE ((mxc_afe_regs_t *)MXC_BASE_AFE)
AnnaBridge 171:3a7713b1edbc 478
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480
AnnaBridge 171:3a7713b1edbc 481 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 482 /* ADC */
AnnaBridge 171:3a7713b1edbc 483
AnnaBridge 171:3a7713b1edbc 484 #define MXC_CFG_ADC_FIFO_DEPTH ((uint32_t)(32))
AnnaBridge 171:3a7713b1edbc 485
AnnaBridge 171:3a7713b1edbc 486 #define MXC_BASE_ADC ((uint32_t)0x40054000UL)
AnnaBridge 171:3a7713b1edbc 487 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
AnnaBridge 171:3a7713b1edbc 488
AnnaBridge 171:3a7713b1edbc 489 #define MXC_BASE_ADCCFG ((uint32_t)0x40054038UL)
AnnaBridge 171:3a7713b1edbc 490 #define MXC_ADCCFG ((mxc_adccfg_regs_t *)MXC_BASE_ADCCFG)
AnnaBridge 171:3a7713b1edbc 491
AnnaBridge 171:3a7713b1edbc 492 #define MXC_BASE_ADC_FIFO ((uint32_t)0x40109000UL)
AnnaBridge 171:3a7713b1edbc 493 #define MXC_ADC_FIFO ((mxc_adc_fifo_regs_t *)MXC_BASE_ADC_FIFO)
AnnaBridge 171:3a7713b1edbc 494
AnnaBridge 171:3a7713b1edbc 495
AnnaBridge 171:3a7713b1edbc 496
AnnaBridge 171:3a7713b1edbc 497 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 498 /* LCD */
AnnaBridge 171:3a7713b1edbc 499 #define MXC_BASE_LCD ((uint32_t)0x40060000)
AnnaBridge 171:3a7713b1edbc 500 #define MXC_LCD ((mxc_lcd_regs_t *)MXC_BASE_LCD)
AnnaBridge 171:3a7713b1edbc 501
AnnaBridge 171:3a7713b1edbc 502 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 503 /* Peripheral Management Unit (PMU) - formerly DMA Controller */
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 #define MXC_CFG_PMU_CHANNELS (6)
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 #define MXC_BASE_PMU0 ((uint32_t)0x40070000UL)
AnnaBridge 171:3a7713b1edbc 508 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
AnnaBridge 171:3a7713b1edbc 509 #define MXC_BASE_PMU1 ((uint32_t)0x40070020UL)
AnnaBridge 171:3a7713b1edbc 510 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
AnnaBridge 171:3a7713b1edbc 511 #define MXC_BASE_PMU2 ((uint32_t)0x40070040UL)
AnnaBridge 171:3a7713b1edbc 512 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
AnnaBridge 171:3a7713b1edbc 513 #define MXC_BASE_PMU3 ((uint32_t)0x40070060UL)
AnnaBridge 171:3a7713b1edbc 514 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
AnnaBridge 171:3a7713b1edbc 515 #define MXC_BASE_PMU4 ((uint32_t)0x40070080UL)
AnnaBridge 171:3a7713b1edbc 516 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
AnnaBridge 171:3a7713b1edbc 517 #define MXC_BASE_PMU5 ((uint32_t)0x400700A0UL)
AnnaBridge 171:3a7713b1edbc 518 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
AnnaBridge 171:3a7713b1edbc 519
AnnaBridge 171:3a7713b1edbc 520 #define MXC_BASE_PMU_BITBAND ((uint32_t)0x42E00000UL)
AnnaBridge 171:3a7713b1edbc 521 #define MXC_BASE_PMU_BITBAND_CHOFFSET ((uint32_t)0x00000400UL)
AnnaBridge 171:3a7713b1edbc 522 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 523
AnnaBridge 171:3a7713b1edbc 524 typedef enum {
AnnaBridge 171:3a7713b1edbc 525 PMU_IRQ_DAC0_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 526 PMU_IRQ_DAC1_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 527 PMU_IRQ_DAC2_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 528 PMU_IRQ_DAC3_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 529 PMU_IRQ_DAC0_DONE,
AnnaBridge 171:3a7713b1edbc 530 PMU_IRQ_DAC1_DONE,
AnnaBridge 171:3a7713b1edbc 531 PMU_IRQ_DAC2_DONE,
AnnaBridge 171:3a7713b1edbc 532 PMU_IRQ_DAC3_DONE,
AnnaBridge 171:3a7713b1edbc 533 PMU_IRQ_ADC_FIFO_AF,
AnnaBridge 171:3a7713b1edbc 534 PMU_IRQ_ADC_DONE,
AnnaBridge 171:3a7713b1edbc 535 PMU_IRQ_I2C_MST0_DONE,
AnnaBridge 171:3a7713b1edbc 536 PMU_IRQ_I2C_MST1_DONE,
AnnaBridge 171:3a7713b1edbc 537 PMU_IRQ_SPI0_RSLTS_DONE,
AnnaBridge 171:3a7713b1edbc 538 PMU_IRQ_SPI1_RSLTS_DONE,
AnnaBridge 171:3a7713b1edbc 539 PMU_IRQ_SPI2_RSLTS_DONE,
AnnaBridge 171:3a7713b1edbc 540 PMU_IRQ_MAA_DONE,
AnnaBridge 171:3a7713b1edbc 541 PMU_IRQ_SPI0_TX_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 542 PMU_IRQ_SPI0_RSLTS_FIFO_AF,
AnnaBridge 171:3a7713b1edbc 543 PMU_IRQ_SPI1_TX_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 544 PMU_IRQ_SPI1_RSLTS_FIFO_AF,
AnnaBridge 171:3a7713b1edbc 545 PMU_IRQ_SPI2_TX_FIFO_AE,
AnnaBridge 171:3a7713b1edbc 546 PMU_IRQ_SPI3_RSLTS_FIFO_AF,
AnnaBridge 171:3a7713b1edbc 547 PMU_IRQ_I2C_MST0_TRANS_FIFO,
AnnaBridge 171:3a7713b1edbc 548 PMU_IRQ_I2C_MST0_RSLT_FIFO,
AnnaBridge 171:3a7713b1edbc 549 PMU_IRQ_I2C_MST1_TRANS_FIFO,
AnnaBridge 171:3a7713b1edbc 550 PMU_IRQ_I2C_MST2_RSLT_FIFO,
AnnaBridge 171:3a7713b1edbc 551 PMU_IRQ_I2C_SLV_TRANS_FIFO,
AnnaBridge 171:3a7713b1edbc 552 PMU_IRQ_I2C_SLV_RSLT_FIFO,
AnnaBridge 171:3a7713b1edbc 553 PMU_IRQ_UART0_TX_FIFO,
AnnaBridge 171:3a7713b1edbc 554 PMU_IRQ_UART0_RX_FIFO,
AnnaBridge 171:3a7713b1edbc 555 PMU_IRQ_UART1_TX_FIFO,
AnnaBridge 171:3a7713b1edbc 556 PMU_IRQ_UART1_RX_FIFO,
AnnaBridge 171:3a7713b1edbc 557 PMU_IRQ_SPI0_EXCP,
AnnaBridge 171:3a7713b1edbc 558 PMU_IRQ_SPI1_EXCP,
AnnaBridge 171:3a7713b1edbc 559 PMU_IRQ_SPI2_EXCP,
AnnaBridge 171:3a7713b1edbc 560 PMU_IRQ_RSVD0,
AnnaBridge 171:3a7713b1edbc 561 PMU_IRQ_I2C_MST0_EXCP,
AnnaBridge 171:3a7713b1edbc 562 PMU_IRQ_I2C_MST1_EXCP,
AnnaBridge 171:3a7713b1edbc 563 PMU_IRQ_I2C_SLV_EXCP,
AnnaBridge 171:3a7713b1edbc 564 PMU_IRQ_RSVD1,
AnnaBridge 171:3a7713b1edbc 565 PMU_IRQ_GPIO0,
AnnaBridge 171:3a7713b1edbc 566 PMU_IRQ_GPIO1,
AnnaBridge 171:3a7713b1edbc 567 PMU_IRQ_GPIO2,
AnnaBridge 171:3a7713b1edbc 568 PMU_IRQ_GPIO3,
AnnaBridge 171:3a7713b1edbc 569 PMU_IRQ_GPIO4,
AnnaBridge 171:3a7713b1edbc 570 PMU_IRQ_GPIO5,
AnnaBridge 171:3a7713b1edbc 571 PMU_IRQ_GPIO6,
AnnaBridge 171:3a7713b1edbc 572 PMU_IRQ_GPIO7,
AnnaBridge 171:3a7713b1edbc 573 PMU_IRQ_GPIO8,
AnnaBridge 171:3a7713b1edbc 574 PMU_IRQ_AFE_COMP_NMI,
AnnaBridge 171:3a7713b1edbc 575 PMU_IRQ_AES_ENGINE,
AnnaBridge 171:3a7713b1edbc 576 } pmu_int_mask_t;
AnnaBridge 171:3a7713b1edbc 577
AnnaBridge 171:3a7713b1edbc 578 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 579 /* USB */
AnnaBridge 171:3a7713b1edbc 580
AnnaBridge 171:3a7713b1edbc 581 #define MXC_BASE_USB ((uint32_t)0x4010C000UL)
AnnaBridge 171:3a7713b1edbc 582 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
AnnaBridge 171:3a7713b1edbc 583
AnnaBridge 171:3a7713b1edbc 584 #define MXC_USB_MAX_PACKET (64)
AnnaBridge 171:3a7713b1edbc 585 #define MXC_USB_NUM_EP (8)
AnnaBridge 171:3a7713b1edbc 586
AnnaBridge 171:3a7713b1edbc 587
AnnaBridge 171:3a7713b1edbc 588 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 589 /* Instruction Cache Controller */
AnnaBridge 171:3a7713b1edbc 590
AnnaBridge 171:3a7713b1edbc 591 #define MXC_BASE_ICC ((uint32_t)0x40080000UL)
AnnaBridge 171:3a7713b1edbc 592 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /* System Manager */
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 #define MXC_BASE_SYSMAN ((uint32_t)0x40090000UL)
AnnaBridge 171:3a7713b1edbc 597
AnnaBridge 171:3a7713b1edbc 598 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 599 /* Clock Manager */
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 #define MXC_BASE_CLKMAN ((uint32_t)0x40090400UL)
AnnaBridge 171:3a7713b1edbc 602 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 606 /* Power Manager */
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 #define MXC_BASE_PWRMAN ((uint32_t)0x40090800UL)
AnnaBridge 171:3a7713b1edbc 609 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
AnnaBridge 171:3a7713b1edbc 610
AnnaBridge 171:3a7713b1edbc 611 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 612 /* I/O Manager */
AnnaBridge 171:3a7713b1edbc 613
AnnaBridge 171:3a7713b1edbc 614 #define MXC_BASE_IOMAN ((uint32_t)0x40090C00UL)
AnnaBridge 171:3a7713b1edbc 615 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
AnnaBridge 171:3a7713b1edbc 616
AnnaBridge 171:3a7713b1edbc 617
AnnaBridge 171:3a7713b1edbc 618 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 619 /* RTC: Timer/Alarms */
AnnaBridge 171:3a7713b1edbc 620
AnnaBridge 171:3a7713b1edbc 621 #define MXC_BASE_RTCTMR ((uint32_t)0x40090A00UL)
AnnaBridge 171:3a7713b1edbc 622 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
AnnaBridge 171:3a7713b1edbc 623
AnnaBridge 171:3a7713b1edbc 624 #define MXC_RTCTMR_GET_IRQ(i) (i == 0 ? RTC0_IRQn : \
AnnaBridge 171:3a7713b1edbc 625 i == 1 ? RTC1_IRQn : \
AnnaBridge 171:3a7713b1edbc 626 i == 2 ? RTC2_IRQn : \
AnnaBridge 171:3a7713b1edbc 627 i == 3 ? RTC3_IRQn : 0)
AnnaBridge 171:3a7713b1edbc 628
AnnaBridge 171:3a7713b1edbc 629 #define MXC_BASE_RTCCFG ((uint32_t)0x40090A70UL)
AnnaBridge 171:3a7713b1edbc 630 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
AnnaBridge 171:3a7713b1edbc 631 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 632 /* RTC: Power Sequencer */
AnnaBridge 171:3a7713b1edbc 633
AnnaBridge 171:3a7713b1edbc 634 #define MXC_BASE_PWRSEQ ((uint32_t)0x40090A30UL)
AnnaBridge 171:3a7713b1edbc 635 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 638 /* Trim Shadow Registers */
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 #define MXC_BASE_TRIM ((uint32_t)0x400E0000UL)
AnnaBridge 171:3a7713b1edbc 641 #define MXC_TRIM ((mxc_ftr_regs_t *)MXC_BASE_TRIM)
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 644 /* Flash Memory Controller / Security */
AnnaBridge 171:3a7713b1edbc 645
AnnaBridge 171:3a7713b1edbc 646 #define MXC_BASE_FLC ((uint32_t)0x400F0000UL)
AnnaBridge 171:3a7713b1edbc 647 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
AnnaBridge 171:3a7713b1edbc 648 #define MXC_BASE_FLC_BITBAND ((uint32_t)0x43E00000UL)
AnnaBridge 171:3a7713b1edbc 649 #define MXC_FLC_PAGE_SIZE_SHIFT 11
AnnaBridge 171:3a7713b1edbc 650 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
AnnaBridge 171:3a7713b1edbc 651 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
AnnaBridge 171:3a7713b1edbc 652
AnnaBridge 171:3a7713b1edbc 653 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 658
AnnaBridge 171:3a7713b1edbc 659 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
AnnaBridge 171:3a7713b1edbc 660 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
AnnaBridge 171:3a7713b1edbc 661 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
AnnaBridge 171:3a7713b1edbc 662 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
AnnaBridge 171:3a7713b1edbc 663
AnnaBridge 171:3a7713b1edbc 664 /*******************************************************************************/
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 #endif /* _MAX32600_H_ */