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TARGET_MAX32600MBED/TOOLCHAIN_IAR/i2cm_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_I2CM_REGS_H_
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_I2CM_REGS_H_
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file i2cm_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup i2cm I2CM
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 50 ====== ================================================ */
AnnaBridge 171:3a7713b1edbc 51 typedef struct {
AnnaBridge 171:3a7713b1edbc 52 __IO uint32_t fs_clk_div; /* 0x0000 Full Speed SCL Clock Settings */
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t hs_clk_div; /* 0x0004 High Speed SCL Clock Settings */
AnnaBridge 171:3a7713b1edbc 54 __I uint32_t rsv0008; /* 0x0008 */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t timeout; /* 0x000C [TO_CNTL] Timeout and Auto-Stop Settings */
AnnaBridge 171:3a7713b1edbc 56 __IO uint32_t ctrl; /* 0x0010 [EN_CNTL] I2C Master Control Register */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t trans; /* 0x0014 [MSTR_CNTL] I2C Master Tx Start and Status Flags */
AnnaBridge 171:3a7713b1edbc 58 __IO uint32_t intfl; /* 0x0018 Interrupt Flags */
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t inten; /* 0x001C Interrupt Enable/Disable Controls */
AnnaBridge 171:3a7713b1edbc 60 __I uint32_t rsv0020[2]; /* 0x0020 */
AnnaBridge 171:3a7713b1edbc 61 __IO uint32_t bb; /* 0x0028 Bit-Bang Control Register */
AnnaBridge 171:3a7713b1edbc 62 } mxc_i2cm_regs_t;
AnnaBridge 171:3a7713b1edbc 63
AnnaBridge 171:3a7713b1edbc 64 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 65 ====== ================================================ */
AnnaBridge 171:3a7713b1edbc 66 typedef struct {
AnnaBridge 171:3a7713b1edbc 67 __IO uint32_t trans[512]; /* 0x0000 I2C Master Transaction FIFO */
AnnaBridge 171:3a7713b1edbc 68 __IO uint32_t rslts[512]; /* 0x0800 I2C Master Results FIFO */
AnnaBridge 171:3a7713b1edbc 69 } mxc_i2cm_fifo_regs_t;
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /*
AnnaBridge 171:3a7713b1edbc 72 Register offsets for module I2CM.
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74 #define MXC_R_I2CM_OFFS_FS_CLK_DIV ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 75 #define MXC_R_I2CM_OFFS_HS_CLK_DIV ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 76 #define MXC_R_I2CM_OFFS_TIMEOUT ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 77 #define MXC_R_I2CM_OFFS_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 78 #define MXC_R_I2CM_OFFS_TRANS ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 79 #define MXC_R_I2CM_OFFS_INTFL ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 80 #define MXC_R_I2CM_OFFS_INTEN ((uint32_t)0x0000001CUL)
AnnaBridge 171:3a7713b1edbc 81 #define MXC_R_I2CM_OFFS_BB ((uint32_t)0x00000028UL)
AnnaBridge 171:3a7713b1edbc 82 #define MXC_R_I2CM_OFFS_AHB_RETRY ((uint32_t)0x00000030UL)
AnnaBridge 171:3a7713b1edbc 83
AnnaBridge 171:3a7713b1edbc 84 #define MXC_R_I2CM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 85 #define MXC_R_I2CM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /*
AnnaBridge 171:3a7713b1edbc 88 Field positions and masks for module I2CM.
AnnaBridge 171:3a7713b1edbc 89 */
AnnaBridge 171:3a7713b1edbc 90 #define MXC_S_I2CM_TRANS_TAG_START 0x000
AnnaBridge 171:3a7713b1edbc 91 #define MXC_S_I2CM_TRANS_TAG_TXDATA_ACK 0x100
AnnaBridge 171:3a7713b1edbc 92 #define MXC_S_I2CM_TRANS_TAG_TXDATA_NACK 0x200
AnnaBridge 171:3a7713b1edbc 93 #define MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT 0x400
AnnaBridge 171:3a7713b1edbc 94 #define MXC_S_I2CM_TRANS_TAG_RXDATA_NACK 0x500
AnnaBridge 171:3a7713b1edbc 95 #define MXC_S_I2CM_TRANS_TAG_STOP 0x700
AnnaBridge 171:3a7713b1edbc 96 #define MXC_S_I2CM_RSTLS_TAG_DATA 0x100
AnnaBridge 171:3a7713b1edbc 97 #define MXC_S_I2CM_RSTLS_TAG_EMPTY 0x200
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS 0
AnnaBridge 171:3a7713b1edbc 100 #define MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CM_CLK_DIV_FILTER_CLK_DIV_POS))
AnnaBridge 171:3a7713b1edbc 101 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS 8
AnnaBridge 171:3a7713b1edbc 102 #define MXC_F_I2CM_CLK_DIV_SCL_LO_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_LO_CNT_POS))
AnnaBridge 171:3a7713b1edbc 103 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS 20
AnnaBridge 171:3a7713b1edbc 104 #define MXC_F_I2CM_CLK_DIV_SCL_HI_CNT ((uint32_t)(0x00000FFFUL << MXC_F_I2CM_CLK_DIV_SCL_HI_CNT_POS))
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS 16
AnnaBridge 171:3a7713b1edbc 107 #define MXC_F_I2CM_TIMEOUT_TX_TIMEOUT ((uint32_t)(0x000000FFUL << MXC_F_I2CM_TIMEOUT_TX_TIMEOUT_POS))
AnnaBridge 171:3a7713b1edbc 108 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS 24
AnnaBridge 171:3a7713b1edbc 109 #define MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_TIMEOUT_AUTO_STOP_EN_POS))
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 #define MXC_F_I2CM_CTRL_TX_FIFO_EN_POS 2
AnnaBridge 171:3a7713b1edbc 112 #define MXC_F_I2CM_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_TX_FIFO_EN_POS))
AnnaBridge 171:3a7713b1edbc 113 #define MXC_F_I2CM_CTRL_RX_FIFO_EN_POS 3
AnnaBridge 171:3a7713b1edbc 114 #define MXC_F_I2CM_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_RX_FIFO_EN_POS))
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS 7
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_I2CM_CTRL_MSTR_RESET_EN ((uint32_t)(0x00000001UL << MXC_F_I2CM_CTRL_MSTR_RESET_EN_POS))
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_I2CM_TRANS_TX_START_POS 0
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_I2CM_TRANS_TX_START ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_START_POS))
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS 1
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_I2CM_TRANS_TX_IN_PROGRESS ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_IN_PROGRESS_POS))
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_I2CM_TRANS_TX_DONE_POS 2
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_I2CM_TRANS_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_DONE_POS))
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_I2CM_TRANS_TX_NACKED_POS 3
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_I2CM_TRANS_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_NACKED_POS))
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS 4
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_I2CM_TRANS_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_LOST_ARBITR_POS))
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_I2CM_TRANS_TX_TIMEOUT_POS 5
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_I2CM_TRANS_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_TRANS_TX_TIMEOUT_POS))
AnnaBridge 171:3a7713b1edbc 130
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_I2CM_INTFL_TX_DONE_POS 0
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_I2CM_INTFL_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_DONE_POS))
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_I2CM_INTFL_TX_NACKED_POS 1
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_I2CM_INTFL_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_NACKED_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS 2
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_I2CM_INTFL_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_LOST_ARBITR_POS))
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_I2CM_INTFL_TX_TIMEOUT_POS 3
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_I2CM_INTFL_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_TIMEOUT_POS))
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS 4
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_I2CM_INTFL_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS 5
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_TX_FIFO_3Q_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS 6
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_NOT_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS 7
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_2Q_FULL_POS))
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS 8
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_3Q_FULL_POS))
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS 9
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_I2CM_INTFL_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTFL_RX_FIFO_FULL_POS))
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_I2CM_INTEN_TX_DONE_POS 0
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_I2CM_INTEN_TX_DONE ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_DONE_POS))
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_I2CM_INTEN_TX_NACKED_POS 1
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_I2CM_INTEN_TX_NACKED ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_NACKED_POS))
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS 2
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_I2CM_INTEN_TX_LOST_ARBITR ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_LOST_ARBITR_POS))
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_I2CM_INTEN_TX_TIMEOUT_POS 3
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_I2CM_INTEN_TX_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_TIMEOUT_POS))
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS 4
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_I2CM_INTEN_TX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS 5
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_TX_FIFO_3Q_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS 6
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_I2CM_INTEN_RX_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS 7
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_2Q_FULL_POS))
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS 8
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_3Q_FULL_POS))
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS 9
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_I2CM_INTEN_RX_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_I2CM_INTEN_RX_FIFO_FULL_POS))
AnnaBridge 171:3a7713b1edbc 172
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_I2CM_BB_BB_SCL_OUT_POS 0
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_I2CM_BB_BB_SCL_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_OUT_POS))
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_I2CM_BB_BB_SDA_OUT_POS 1
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_I2CM_BB_BB_SDA_OUT ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_OUT_POS))
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS 2
AnnaBridge 171:3a7713b1edbc 178 #define MXC_F_I2CM_BB_BB_SCL_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SCL_IN_VAL_POS))
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS 3
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_I2CM_BB_BB_SDA_IN_VAL ((uint32_t)(0x00000001UL << MXC_F_I2CM_BB_BB_SDA_IN_VAL_POS))
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_I2CM_BB_RX_FIFO_CNT_POS 16
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_I2CM_BB_RX_FIFO_CNT ((uint32_t)(0x0000001FUL << MXC_F_I2CM_BB_RX_FIFO_CNT_POS))
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 185 }
AnnaBridge 171:3a7713b1edbc 186 #endif
AnnaBridge 171:3a7713b1edbc 187
AnnaBridge 171:3a7713b1edbc 188 /**
AnnaBridge 171:3a7713b1edbc 189 * @}
AnnaBridge 171:3a7713b1edbc 190 */
AnnaBridge 171:3a7713b1edbc 191
AnnaBridge 171:3a7713b1edbc 192 #endif