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TARGET_MAX32600MBED/TOOLCHAIN_IAR/flc_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_FLC_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_FLC_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file flc_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup flc FLC
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 49 ====== ======================================================= */
AnnaBridge 171:3a7713b1edbc 50 typedef struct {
AnnaBridge 171:3a7713b1edbc 51 __IO uint32_t faddr; /* 0x0000 Flash Operation Address */
AnnaBridge 171:3a7713b1edbc 52 __IO uint32_t fckdiv; /* 0x0004 Flash Clock Rate Divisor */
AnnaBridge 171:3a7713b1edbc 53 __IO uint32_t ctrl; /* 0x0008 Flash Control Register */
AnnaBridge 171:3a7713b1edbc 54 __I uint32_t rsv000C[6]; /* 0x000C */
AnnaBridge 171:3a7713b1edbc 55 __IO uint32_t intr; /* 0x0024 Flash Controller Interrupt Flags and Enable/Disable 0 */
AnnaBridge 171:3a7713b1edbc 56 __I uint32_t rsv0028[2]; /* 0x0028 */
AnnaBridge 171:3a7713b1edbc 57 __IO uint32_t fdata; /* 0x0030 Flash Operation Data Register */
AnnaBridge 171:3a7713b1edbc 58 __I uint32_t rsv0034[7]; /* 0x0034 */
AnnaBridge 171:3a7713b1edbc 59 __IO uint32_t perform; /* 0x0050 Flash Performance Settings */
AnnaBridge 171:3a7713b1edbc 60 __I uint32_t rsv0054[11]; /* 0x0054 */
AnnaBridge 171:3a7713b1edbc 61 __IO uint32_t status; /* 0x0080 Security Status Flags */
AnnaBridge 171:3a7713b1edbc 62 __I uint32_t rsv0084; /* 0x0084 */
AnnaBridge 171:3a7713b1edbc 63 __IO uint32_t security; /* 0x0088 Flash Controller Security Settings */
AnnaBridge 171:3a7713b1edbc 64 __I uint32_t rsv008C[4]; /* 0x008C */
AnnaBridge 171:3a7713b1edbc 65 __IO uint32_t bypass; /* 0x009C Status Flags for DSB Operations */
AnnaBridge 171:3a7713b1edbc 66 __IO uint32_t user_option; /* 0x0100 Used to set DSB Access code and Auto-Lock in info block */
AnnaBridge 171:3a7713b1edbc 67 __I uint32_t rsv0104[15]; /* 0x0104 */
AnnaBridge 171:3a7713b1edbc 68 __IO uint32_t ctrl2; /* 0x0140 Flash Control Register 2 */
AnnaBridge 171:3a7713b1edbc 69 __IO uint32_t intfl1; /* 0x0144 Interrupt Flags Register 1 */
AnnaBridge 171:3a7713b1edbc 70 __IO uint32_t inten1; /* 0x0148 Interrupt Enable/Disable Register 1 */
AnnaBridge 171:3a7713b1edbc 71 __I uint32_t rsv014C; /* 0x014C */
AnnaBridge 171:3a7713b1edbc 72 __IO uint32_t disable_xr0; /* 0x0150 Disable Flash Page Exec/Read Register 0 */
AnnaBridge 171:3a7713b1edbc 73 __IO uint32_t disable_xr1; /* 0x0154 Disable Flash Page Exec/Read Register 1 */
AnnaBridge 171:3a7713b1edbc 74 __IO uint32_t disable_xr2; /* 0x0158 Disable Flash Page Exec/Read Register 2 */
AnnaBridge 171:3a7713b1edbc 75 __IO uint32_t disable_xr3; /* 0x015C Disable Flash Page Exec/Read Register 3 */
AnnaBridge 171:3a7713b1edbc 76 __IO uint32_t disable_we0; /* 0x0160 Disable Flash Page Write/Erase Register 0 */
AnnaBridge 171:3a7713b1edbc 77 __IO uint32_t disable_we1; /* 0x0164 Disable Flash Page Write/Erase Register 1 */
AnnaBridge 171:3a7713b1edbc 78 __IO uint32_t disable_we2; /* 0x0168 Disable Flash Page Write/Erase Register 2 */
AnnaBridge 171:3a7713b1edbc 79 __IO uint32_t disable_we3; /* 0x016C Disable Flash Page Write/Erase Register 3 */
AnnaBridge 171:3a7713b1edbc 80 } mxc_flc_regs_t;
AnnaBridge 171:3a7713b1edbc 81
AnnaBridge 171:3a7713b1edbc 82 /*
AnnaBridge 171:3a7713b1edbc 83 Register offsets for module FLC.
AnnaBridge 171:3a7713b1edbc 84 */
AnnaBridge 171:3a7713b1edbc 85 #define MXC_R_FLC_OFFS_FADDR ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 86 #define MXC_R_FLC_OFFS_FCKDIV ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 87 #define MXC_R_FLC_OFFS_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 88 #define MXC_R_FLC_OFFS_INTR ((uint32_t)0x00000024UL)
AnnaBridge 171:3a7713b1edbc 89 #define MXC_R_FLC_OFFS_FDATA ((uint32_t)0x00000030UL)
AnnaBridge 171:3a7713b1edbc 90 #define MXC_R_FLC_OFFS_PERFORM ((uint32_t)0x00000050UL)
AnnaBridge 171:3a7713b1edbc 91 #define MXC_R_FLC_OFFS_STATUS ((uint32_t)0x00000080UL)
AnnaBridge 171:3a7713b1edbc 92 #define MXC_R_FLC_OFFS_SECURITY ((uint32_t)0x00000088UL)
AnnaBridge 171:3a7713b1edbc 93 #define MXC_R_FLC_OFFS_BYPASS ((uint32_t)0x0000009CUL)
AnnaBridge 171:3a7713b1edbc 94 #define MXC_R_FLC_OFFS_USER_OPTION ((uint32_t)0x00000100UL)
AnnaBridge 171:3a7713b1edbc 95 #define MXC_R_FLC_OFFS_CTRL2 ((uint32_t)0x00000140UL)
AnnaBridge 171:3a7713b1edbc 96 #define MXC_R_FLC_OFFS_INTFL1 ((uint32_t)0x00000144UL)
AnnaBridge 171:3a7713b1edbc 97 #define MXC_R_FLC_OFFS_INTEN1 ((uint32_t)0x00000148UL)
AnnaBridge 171:3a7713b1edbc 98 #define MXC_R_FLC_OFFS_DISABLE_XR0 ((uint32_t)0x00000150UL)
AnnaBridge 171:3a7713b1edbc 99 #define MXC_R_FLC_OFFS_DISABLE_XR1 ((uint32_t)0x00000154UL)
AnnaBridge 171:3a7713b1edbc 100 #define MXC_R_FLC_OFFS_DISABLE_XR2 ((uint32_t)0x00000158UL)
AnnaBridge 171:3a7713b1edbc 101 #define MXC_R_FLC_OFFS_DISABLE_XR3 ((uint32_t)0x0000015CUL)
AnnaBridge 171:3a7713b1edbc 102 #define MXC_R_FLC_OFFS_DISABLE_WE0 ((uint32_t)0x00000160UL)
AnnaBridge 171:3a7713b1edbc 103 #define MXC_R_FLC_OFFS_DISABLE_WE1 ((uint32_t)0x00000164UL)
AnnaBridge 171:3a7713b1edbc 104 #define MXC_R_FLC_OFFS_DISABLE_WE2 ((uint32_t)0x00000168UL)
AnnaBridge 171:3a7713b1edbc 105 #define MXC_R_FLC_OFFS_DISABLE_WE3 ((uint32_t)0x0000016CUL)
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 #define MXC_V_FLC_ERASE_CODE_PAGE_ERASE ((uint8_t)0x55)
AnnaBridge 171:3a7713b1edbc 108 #define MXC_V_FLC_ERASE_CODE_MASS_ERASE ((uint8_t)0xAA)
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110 #define MXC_V_FLC_FLSH_UNLOCK_KEY ((uint8_t)0x2)
AnnaBridge 171:3a7713b1edbc 111
AnnaBridge 171:3a7713b1edbc 112 /*
AnnaBridge 171:3a7713b1edbc 113 Field positions and masks for module FLC.
AnnaBridge 171:3a7713b1edbc 114 */
AnnaBridge 171:3a7713b1edbc 115 #define MXC_F_FLC_FADDR_FADDR_POS 0
AnnaBridge 171:3a7713b1edbc 116 #define MXC_F_FLC_FADDR_FADDR ((uint32_t)(0x0003FFFFUL << MXC_F_FLC_FADDR_FADDR_POS))
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 #define MXC_F_FLC_FCKDIV_FCKDIV_POS 0
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_FLC_FCKDIV_FCKDIV ((uint32_t)(0x0000001FUL << MXC_F_FLC_FCKDIV_FCKDIV_POS))
AnnaBridge 171:3a7713b1edbc 120
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_FLC_CTRL_WRITE_POS 0
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_FLC_CTRL_WRITE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_POS))
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_FLC_CTRL_MASS_ERASE_POS 1
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_FLC_CTRL_MASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_MASS_ERASE_POS))
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_FLC_CTRL_PAGE_ERASE_POS 2
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_FLC_CTRL_PAGE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PAGE_ERASE_POS))
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_FLC_CTRL_ERASE_CODE_POS 8
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_FLC_CTRL_ERASE_CODE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL_ERASE_CODE_POS))
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS 16
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_UNLOCK_POS))
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_FLC_CTRL_WRITE_ENABLE_POS 17
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_FLC_CTRL_WRITE_ENABLE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_WRITE_ENABLE_POS))
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_FLC_CTRL_PENDING_POS 24
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_FLC_CTRL_PENDING ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_PENDING_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS 25
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_FLC_CTRL_INFO_BLOCK_VALID ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_INFO_BLOCK_VALID_POS))
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS 27
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_FLC_CTRL_AUTO_INCRE_MODE ((uint32_t)(0x00000001UL << MXC_F_FLC_CTRL_AUTO_INCRE_MODE_POS))
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_FLC_CTRL_FLSH_UNLOCK_POS 28
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_FLC_CTRL_FLSH_UNLOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_CTRL_FLSH_UNLOCK_POS))
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS 0
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IF_POS))
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS 1
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IF ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IF_POS))
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS 9
AnnaBridge 171:3a7713b1edbc 147 #define MXC_F_FLC_INTR_FLASH_OP_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_DONE_IE_POS))
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS 10
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_FLC_INTR_FLASH_OP_FAILED_IE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTR_FLASH_OP_FAILED_IE_POS))
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS 8
AnnaBridge 171:3a7713b1edbc 152 #define MXC_F_FLC_PERFORM_FAST_READ_MODE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_FAST_READ_MODE_EN_POS))
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_FLC_PERFORM_DELAY_SE_EN_POS 0
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_FLC_PERFORM_DELAY_SE_EN ((uint32_t)(0x00000001UL << MXC_F_FLC_PERFORM_DELAY_SE_EN_POS))
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS 0
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_WINDOW_POS))
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS 1
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_DEBUG_LOCK_STATIC_POS))
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_FLC_STATUS_AUTO_LOCK_POS 3
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_FLC_STATUS_AUTO_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_STATUS_AUTO_LOCK_POS))
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS 0
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_FLC_SECURITY_DEBUG_DISABLE ((uint32_t)(0x000000FFUL << MXC_F_FLC_SECURITY_DEBUG_DISABLE_POS))
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS 8
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_FLC_SECURITY_MASS_ERASE_LOCK ((uint32_t)(0x0000000FUL << MXC_F_FLC_SECURITY_MASS_ERASE_LOCK_POS))
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_FLC_SECURITY_SECURITY_LOCK_POS 31
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_FLC_SECURITY_SECURITY_LOCK ((uint32_t)(0x00000001UL << MXC_F_FLC_SECURITY_SECURITY_LOCK_POS))
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS 0
AnnaBridge 171:3a7713b1edbc 171 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_ERASE_POS))
AnnaBridge 171:3a7713b1edbc 172 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS 1
AnnaBridge 171:3a7713b1edbc 173 #define MXC_F_FLC_BYPASS_SUPERWIPE_ERASE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_ERASE_POS))
AnnaBridge 171:3a7713b1edbc 174 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS 2
AnnaBridge 171:3a7713b1edbc 175 #define MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_DESTRUCT_BYPASS_COMPLETE_POS))
AnnaBridge 171:3a7713b1edbc 176 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS 3
AnnaBridge 171:3a7713b1edbc 177 #define MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE ((uint32_t)(0x00000001UL << MXC_F_FLC_BYPASS_SUPERWIPE_COMPLETE_POS))
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 #define MXC_F_FLC_CTRL2_FLASH_LVE_POS 0
AnnaBridge 171:3a7713b1edbc 180 #define MXC_F_FLC_CTRL2_FLASH_LVE ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_FLASH_LVE_POS))
AnnaBridge 171:3a7713b1edbc 181 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS 8
AnnaBridge 171:3a7713b1edbc 182 #define MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL ((uint32_t)(0x000000FFUL << MXC_F_FLC_CTRL2_BYPASS_AHB_FAIL_POS))
AnnaBridge 171:3a7713b1edbc 183
AnnaBridge 171:3a7713b1edbc 184 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS 0
AnnaBridge 171:3a7713b1edbc 185 #define MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_SRAM_ADDR_WRAPPED_POS))
AnnaBridge 171:3a7713b1edbc 186 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS 1
AnnaBridge 171:3a7713b1edbc 187 #define MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_INVALID_FLASH_ADDR_POS))
AnnaBridge 171:3a7713b1edbc 188 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS 2
AnnaBridge 171:3a7713b1edbc 189 #define MXC_F_FLC_INTFL1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_FLASH_READ_LOCKED_POS))
AnnaBridge 171:3a7713b1edbc 190 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS 3
AnnaBridge 171:3a7713b1edbc 191 #define MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTFL1_TRIM_UPDATE_DONE_POS))
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS 0
AnnaBridge 171:3a7713b1edbc 194 #define MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_SRAM_ADDR_WRAPPED_POS))
AnnaBridge 171:3a7713b1edbc 195 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS 1
AnnaBridge 171:3a7713b1edbc 196 #define MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_INVALID_FLASH_ADDR_POS))
AnnaBridge 171:3a7713b1edbc 197 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS 2
AnnaBridge 171:3a7713b1edbc 198 #define MXC_F_FLC_INTEN1_FLASH_READ_LOCKED ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_FLASH_READ_LOCKED_POS))
AnnaBridge 171:3a7713b1edbc 199 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS 3
AnnaBridge 171:3a7713b1edbc 200 #define MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE ((uint32_t)(0x00000001UL << MXC_F_FLC_INTEN1_TRIM_UPDATE_DONE_POS))
AnnaBridge 171:3a7713b1edbc 201
AnnaBridge 171:3a7713b1edbc 202 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 203 }
AnnaBridge 171:3a7713b1edbc 204 #endif
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 /**
AnnaBridge 171:3a7713b1edbc 207 * @}
AnnaBridge 171:3a7713b1edbc 208 */
AnnaBridge 171:3a7713b1edbc 209
AnnaBridge 171:3a7713b1edbc 210 #endif /* _MXC_FLC_REGS_H_ */