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TARGET_MAX32600MBED/TOOLCHAIN_IAR/dac_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_DAC_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_DAC_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file dac_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup dac DAC
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**
AnnaBridge 171:3a7713b1edbc 50 * @brief Defines the DAC Operational Modes.
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef enum {
AnnaBridge 171:3a7713b1edbc 53 /** DAC OpMode FIFO */
AnnaBridge 171:3a7713b1edbc 54 MXC_E_DAC_OP_MODE_FIFO = 0,
AnnaBridge 171:3a7713b1edbc 55 /** DAC OpMode Sample Count */
AnnaBridge 171:3a7713b1edbc 56 MXC_E_DAC_OP_MODE_DACSMPLCNT,
AnnaBridge 171:3a7713b1edbc 57 /** DAC OpMode DAC_REG Control */
AnnaBridge 171:3a7713b1edbc 58 MXC_E_DAC_OP_MODE_DAC_REG,
AnnaBridge 171:3a7713b1edbc 59 /** DAC OpMode Continuous */
AnnaBridge 171:3a7713b1edbc 60 MXC_E_DAC_OP_MODE_CONTINUOUS
AnnaBridge 171:3a7713b1edbc 61 } mxc_dac_op_mode_t;
AnnaBridge 171:3a7713b1edbc 62
AnnaBridge 171:3a7713b1edbc 63 /**
AnnaBridge 171:3a7713b1edbc 64 * @brief Defines the DAC Interpolation Options.
AnnaBridge 171:3a7713b1edbc 65 */
AnnaBridge 171:3a7713b1edbc 66 typedef enum {
AnnaBridge 171:3a7713b1edbc 67 /** DAC Interpolation is Disabled */
AnnaBridge 171:3a7713b1edbc 68 MXC_E_DAC_INTERP_MODE_DISABLED = 0,
AnnaBridge 171:3a7713b1edbc 69 /** DAC Interpolation 2:1 */
AnnaBridge 171:3a7713b1edbc 70 MXC_E_DAC_INTERP_MODE_2_TO_1,
AnnaBridge 171:3a7713b1edbc 71 /** DAC Interpolation 4:1 */
AnnaBridge 171:3a7713b1edbc 72 MXC_E_DAC_INTERP_MODE_4_TO_1,
AnnaBridge 171:3a7713b1edbc 73 /** DAC Interpolation 8:1 */
AnnaBridge 171:3a7713b1edbc 74 MXC_E_DAC_INTERP_MODE_8_TO_1
AnnaBridge 171:3a7713b1edbc 75 } mxc_dac_interp_mode_t;
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /**
AnnaBridge 171:3a7713b1edbc 78 * @brief Defines the DAC Start Modes.
AnnaBridge 171:3a7713b1edbc 79 */
AnnaBridge 171:3a7713b1edbc 80 typedef enum {
AnnaBridge 171:3a7713b1edbc 81 /** Start on FIFO Not Empty */
AnnaBridge 171:3a7713b1edbc 82 MXC_E_DAC_START_MODE_FIFO_NOT_EMPTY = 0,
AnnaBridge 171:3a7713b1edbc 83 /** Start on ADC generated Start Strobe */
AnnaBridge 171:3a7713b1edbc 84 MXC_E_DAC_START_MODE_ADC_STROBE,
AnnaBridge 171:3a7713b1edbc 85 /** Start on DAC generated Start Strobe */
AnnaBridge 171:3a7713b1edbc 86 MXC_E_DAC_START_MODE_DAC_STROBE
AnnaBridge 171:3a7713b1edbc 87 } mxc_dac_start_mode_t;
AnnaBridge 171:3a7713b1edbc 88
AnnaBridge 171:3a7713b1edbc 89 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 90 ====== ================================================== */
AnnaBridge 171:3a7713b1edbc 91 typedef struct {
AnnaBridge 171:3a7713b1edbc 92 __IO uint32_t ctrl0; /* 0x0000 DAC Control Register 0 */
AnnaBridge 171:3a7713b1edbc 93 __IO uint32_t rate; /* 0x0004 DAC Output Rate Control */
AnnaBridge 171:3a7713b1edbc 94 __IO uint32_t ctrl1_int; /* 0x0008 DAC Control Register 1, Interrupt Flags and Enable */
AnnaBridge 171:3a7713b1edbc 95 __IO uint32_t reg; /* 0x000C DAC Data Register */
AnnaBridge 171:3a7713b1edbc 96 __IO uint32_t trm; /* 0x0010 DAC Trim Register */
AnnaBridge 171:3a7713b1edbc 97 } mxc_dac_regs_t;
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 100 ====== ================================================== */
AnnaBridge 171:3a7713b1edbc 101 typedef struct {
AnnaBridge 171:3a7713b1edbc 102 union {
AnnaBridge 171:3a7713b1edbc 103 __IO uint8_t output_8; /* 0x0000 Write to push values to DAC output FIFO */
AnnaBridge 171:3a7713b1edbc 104 __IO uint16_t output_16; /* 0x0000 Write to push values to DAC output FIFO */
AnnaBridge 171:3a7713b1edbc 105 };
AnnaBridge 171:3a7713b1edbc 106 } mxc_dac_fifo_regs_t;
AnnaBridge 171:3a7713b1edbc 107
AnnaBridge 171:3a7713b1edbc 108 /*
AnnaBridge 171:3a7713b1edbc 109 Register offsets for module DAC12.
AnnaBridge 171:3a7713b1edbc 110 */
AnnaBridge 171:3a7713b1edbc 111 #define MXC_R_DAC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 112 #define MXC_R_DAC_OFFS_RATE ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 113 #define MXC_R_DAC_OFFS_CTRL1_INT ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 114 #define MXC_R_DAC_FIFO_OFFS_OUTPUT ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 115
AnnaBridge 171:3a7713b1edbc 116 /*
AnnaBridge 171:3a7713b1edbc 117 Field positions and masks for module DAC.
AnnaBridge 171:3a7713b1edbc 118 */
AnnaBridge 171:3a7713b1edbc 119 #define MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS 0
AnnaBridge 171:3a7713b1edbc 120 #define MXC_F_DAC_CTRL0_FIFO_AE_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AE_CNT_POS))
AnnaBridge 171:3a7713b1edbc 121 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS 5
AnnaBridge 171:3a7713b1edbc 122 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_FULL_POS))
AnnaBridge 171:3a7713b1edbc 123 #define MXC_F_DAC_CTRL0_FIFO_EMPTY_POS 6
AnnaBridge 171:3a7713b1edbc 124 #define MXC_F_DAC_CTRL0_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 125 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS 7
AnnaBridge 171:3a7713b1edbc 126 #define MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_FIFO_ALMOST_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 127 #define MXC_F_DAC_CTRL0_INTERP_MODE_POS 8
AnnaBridge 171:3a7713b1edbc 128 #define MXC_F_DAC_CTRL0_INTERP_MODE ((uint32_t)(0x00000007UL << MXC_F_DAC_CTRL0_INTERP_MODE_POS))
AnnaBridge 171:3a7713b1edbc 129 #define MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS 12
AnnaBridge 171:3a7713b1edbc 130 #define MXC_F_DAC_CTRL0_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_DAC_CTRL0_FIFO_AF_CNT_POS))
AnnaBridge 171:3a7713b1edbc 131 #define MXC_F_DAC_CTRL0_START_MODE_POS 16
AnnaBridge 171:3a7713b1edbc 132 #define MXC_F_DAC_CTRL0_START_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_START_MODE_POS))
AnnaBridge 171:3a7713b1edbc 133 #define MXC_F_DAC_CTRL0_CPU_START_POS 20
AnnaBridge 171:3a7713b1edbc 134 #define MXC_F_DAC_CTRL0_CPU_START ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CPU_START_POS))
AnnaBridge 171:3a7713b1edbc 135 #define MXC_F_DAC_CTRL0_OP_MODE_POS 24
AnnaBridge 171:3a7713b1edbc 136 #define MXC_F_DAC_CTRL0_OP_MODE ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_OP_MODE_POS))
AnnaBridge 171:3a7713b1edbc 137 #define MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS 26
AnnaBridge 171:3a7713b1edbc 138 #define MXC_F_DAC_CTRL0_POWER_MODE_1_0 ((uint32_t)(0x00000003UL << MXC_F_DAC_CTRL0_POWER_MODE_1_0_POS))
AnnaBridge 171:3a7713b1edbc 139 #define MXC_F_DAC_CTRL0_POWER_ON_POS 28
AnnaBridge 171:3a7713b1edbc 140 #define MXC_F_DAC_CTRL0_POWER_ON ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_ON_POS))
AnnaBridge 171:3a7713b1edbc 141 #define MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS 29
AnnaBridge 171:3a7713b1edbc 142 #define MXC_F_DAC_CTRL0_CLOCK_GATE_EN ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_CLOCK_GATE_EN_POS))
AnnaBridge 171:3a7713b1edbc 143 #define MXC_F_DAC_CTRL0_POWER_MODE_2_POS 30
AnnaBridge 171:3a7713b1edbc 144 #define MXC_F_DAC_CTRL0_POWER_MODE_2 ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_POWER_MODE_2_POS))
AnnaBridge 171:3a7713b1edbc 145 #define MXC_F_DAC_CTRL0_RESET_POS 31
AnnaBridge 171:3a7713b1edbc 146 #define MXC_F_DAC_CTRL0_RESET ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL0_RESET_POS))
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 #define MXC_F_DAC_RATE_RATE_CNT_POS 0
AnnaBridge 171:3a7713b1edbc 149 #define MXC_F_DAC_RATE_RATE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_RATE_CNT_POS))
AnnaBridge 171:3a7713b1edbc 150 #define MXC_F_DAC_RATE_SAMPLE_CNT_POS 16
AnnaBridge 171:3a7713b1edbc 151 #define MXC_F_DAC_RATE_SAMPLE_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_DAC_RATE_SAMPLE_CNT_POS))
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS 0
AnnaBridge 171:3a7713b1edbc 154 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IF_POS))
AnnaBridge 171:3a7713b1edbc 155 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS 1
AnnaBridge 171:3a7713b1edbc 156 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IF_POS))
AnnaBridge 171:3a7713b1edbc 157 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS 2
AnnaBridge 171:3a7713b1edbc 158 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IF_POS))
AnnaBridge 171:3a7713b1edbc 159 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS 3
AnnaBridge 171:3a7713b1edbc 160 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_POS))
AnnaBridge 171:3a7713b1edbc 161 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS 16
AnnaBridge 171:3a7713b1edbc 162 #define MXC_F_DAC_CTRL1_INT_OUT_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_OUT_DONE_IE_POS))
AnnaBridge 171:3a7713b1edbc 163 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS 17
AnnaBridge 171:3a7713b1edbc 164 #define MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_UNDERFLOW_IE_POS))
AnnaBridge 171:3a7713b1edbc 165 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS 18
AnnaBridge 171:3a7713b1edbc 166 #define MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_ALMOST_EMPTY_IE_POS))
AnnaBridge 171:3a7713b1edbc 167 #define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS 28
AnnaBridge 171:3a7713b1edbc 168 #define MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_AHB_CG_DISABLE_POS))
AnnaBridge 171:3a7713b1edbc 169 #define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS 29
AnnaBridge 171:3a7713b1edbc 170 #define MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE ((uint32_t)(0x00000001UL << MXC_F_DAC_CTRL1_INT_APB_CG_DISABLE_POS))
AnnaBridge 171:3a7713b1edbc 171
AnnaBridge 171:3a7713b1edbc 172 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 173 }
AnnaBridge 171:3a7713b1edbc 174 #endif
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /**
AnnaBridge 171:3a7713b1edbc 177 * @}
AnnaBridge 171:3a7713b1edbc 178 */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 #endif /* _DAC12_REGS_H */