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TARGET_MAX32600MBED/TOOLCHAIN_IAR/adc_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 171:3a7713b1edbc 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 171:3a7713b1edbc 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 171:3a7713b1edbc 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 171:3a7713b1edbc 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 171:3a7713b1edbc 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 171:3a7713b1edbc 12 * in all copies or substantial portions of the Software.
AnnaBridge 171:3a7713b1edbc 13 *
AnnaBridge 171:3a7713b1edbc 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 171:3a7713b1edbc 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 171:3a7713b1edbc 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 171:3a7713b1edbc 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 171:3a7713b1edbc 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 171:3a7713b1edbc 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 171:3a7713b1edbc 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 171:3a7713b1edbc 24 * Products, Inc. Branding Policy.
AnnaBridge 171:3a7713b1edbc 25 *
AnnaBridge 171:3a7713b1edbc 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 171:3a7713b1edbc 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 171:3a7713b1edbc 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 171:3a7713b1edbc 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 171:3a7713b1edbc 30 * ownership rights.
AnnaBridge 171:3a7713b1edbc 31 *******************************************************************************
AnnaBridge 171:3a7713b1edbc 32 */
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef _MXC_ADC_REGS_H
AnnaBridge 171:3a7713b1edbc 35 #define _MXC_ADC_REGS_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 #include <stdint.h>
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 /**
AnnaBridge 171:3a7713b1edbc 44 * @file adc_regs.h
AnnaBridge 171:3a7713b1edbc 45 * @addtogroup adc ADC
AnnaBridge 171:3a7713b1edbc 46 * @{
AnnaBridge 171:3a7713b1edbc 47 */
AnnaBridge 171:3a7713b1edbc 48
AnnaBridge 171:3a7713b1edbc 49 /**
AnnaBridge 171:3a7713b1edbc 50 * @brief Defines ADC Modes.
AnnaBridge 171:3a7713b1edbc 51 */
AnnaBridge 171:3a7713b1edbc 52 typedef enum {
AnnaBridge 171:3a7713b1edbc 53 /** Single Mode Full Rate */
AnnaBridge 171:3a7713b1edbc 54 MXC_E_ADC_MODE_SMPLCNT_FULL_RATE = 0,
AnnaBridge 171:3a7713b1edbc 55 /** Single Mode Low Power */
AnnaBridge 171:3a7713b1edbc 56 MXC_E_ADC_MODE_SMPLCNT_LOW_POWER = 1,
AnnaBridge 171:3a7713b1edbc 57 /** Continuous Mode Full Rate */
AnnaBridge 171:3a7713b1edbc 58 MXC_E_ADC_MODE_CONTINUOUS_FULL_RATE = 2,
AnnaBridge 171:3a7713b1edbc 59 /** Continuous Mode Low Power */
AnnaBridge 171:3a7713b1edbc 60 MXC_E_ADC_MODE_CONTINUOUS_LOW_POWER = 3,
AnnaBridge 171:3a7713b1edbc 61 /** Single Mode Full Rate with Scan Enabled */
AnnaBridge 171:3a7713b1edbc 62 MXC_E_ADC_MODE_SMPLCNT_SCAN_FULL_RATE = 8,
AnnaBridge 171:3a7713b1edbc 63 /** Single Mode Low Power with Scan Enabled */
AnnaBridge 171:3a7713b1edbc 64 MXC_E_ADC_MODE_SMPLCNT_SCAN_LOW_POWER = 9,
AnnaBridge 171:3a7713b1edbc 65 /** Continuous Mode Full Rate with Scan Enabled */
AnnaBridge 171:3a7713b1edbc 66 MXC_E_ADC_MODE_CONTINUOUS_SCAN_FULL_RATE = 10,
AnnaBridge 171:3a7713b1edbc 67 /** Continuous Mode Low Power with Scan Enabled */
AnnaBridge 171:3a7713b1edbc 68 MXC_E_ADC_MODE_CONTINUOUS_SCAN_LOW_POWER = 11
AnnaBridge 171:3a7713b1edbc 69 } mxc_adc_mode_t;
AnnaBridge 171:3a7713b1edbc 70
AnnaBridge 171:3a7713b1edbc 71 /**
AnnaBridge 171:3a7713b1edbc 72 * @brief Defines ADC Range Control.
AnnaBridge 171:3a7713b1edbc 73 */
AnnaBridge 171:3a7713b1edbc 74 typedef enum {
AnnaBridge 171:3a7713b1edbc 75 /** Bi-polar Operation (-Vref/2 -> Vref/2) */
AnnaBridge 171:3a7713b1edbc 76 MXC_E_ADC_RANGE_HALF = 0,
AnnaBridge 171:3a7713b1edbc 77 /** Bi-polar Operation (-Vref -> Vref) */
AnnaBridge 171:3a7713b1edbc 78 MXC_E_ADC_RANGE_FULL
AnnaBridge 171:3a7713b1edbc 79 } mxc_adc_range_t;
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /**
AnnaBridge 171:3a7713b1edbc 82 * @brief Defines ADC Bipolar operation.
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84 typedef enum {
AnnaBridge 171:3a7713b1edbc 85 /** Uni-polar operation (0 -> Vref) */
AnnaBridge 171:3a7713b1edbc 86 MXC_E_ADC_BI_POL_UNIPOLAR = 0,
AnnaBridge 171:3a7713b1edbc 87 /** Bi-polar operation see ADC Range Control */
AnnaBridge 171:3a7713b1edbc 88 MXC_E_ADC_BI_POL_BIPOLAR
AnnaBridge 171:3a7713b1edbc 89 } mxc_adc_bi_pol_t;
AnnaBridge 171:3a7713b1edbc 90
AnnaBridge 171:3a7713b1edbc 91 /**
AnnaBridge 171:3a7713b1edbc 92 * @brief Defines Decimation Filter Modes.
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94 typedef enum {
AnnaBridge 171:3a7713b1edbc 95 /** Decimation Filter ByPassed */
AnnaBridge 171:3a7713b1edbc 96 MXC_E_ADC_AVG_MODE_FILTER_BYPASS = 0,
AnnaBridge 171:3a7713b1edbc 97 /** Output Average Only*/
AnnaBridge 171:3a7713b1edbc 98 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT,
AnnaBridge 171:3a7713b1edbc 99 /** Output Average and Raw Data (Test Mode Only) */
AnnaBridge 171:3a7713b1edbc 100 MXC_E_ADC_AVG_MODE_FILTER_OUTPUT_RAW
AnnaBridge 171:3a7713b1edbc 101 } mxc_adc_avg_mode_t;
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /**
AnnaBridge 171:3a7713b1edbc 104 * @brief Defines ADC StartMode Modes.
AnnaBridge 171:3a7713b1edbc 105 */
AnnaBridge 171:3a7713b1edbc 106 typedef enum {
AnnaBridge 171:3a7713b1edbc 107 /** StarMode via Software */
AnnaBridge 171:3a7713b1edbc 108 MXC_E_ADC_STRT_MODE_SOFTWARE = 0,
AnnaBridge 171:3a7713b1edbc 109 /** StarMode via PulseTrain */
AnnaBridge 171:3a7713b1edbc 110 MXC_E_ADC_STRT_MODE_PULSETRAIN
AnnaBridge 171:3a7713b1edbc 111 } mxc_adc_strt_mode_t;
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /**
AnnaBridge 171:3a7713b1edbc 114 * @brief Defines Mux Channel Select for the Positive Input to the ADC.
AnnaBridge 171:3a7713b1edbc 115 */
AnnaBridge 171:3a7713b1edbc 116 typedef enum {
AnnaBridge 171:3a7713b1edbc 117 /** Single Mode Input AIN0+; Diff Mode AIN0+/AIN8- */
AnnaBridge 171:3a7713b1edbc 118 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0 = 0,
AnnaBridge 171:3a7713b1edbc 119 /** Single Mode Input AIN1+; Diff Mode AIN1+/AIN9- */
AnnaBridge 171:3a7713b1edbc 120 MXC_E_ADC_PGA_MUX_CH_SEL_AIN1 = 1,
AnnaBridge 171:3a7713b1edbc 121 /** Single Mode Input AIN2+; Diff Mode AIN2+/AIN10- */
AnnaBridge 171:3a7713b1edbc 122 MXC_E_ADC_PGA_MUX_CH_SEL_AIN2 = 2,
AnnaBridge 171:3a7713b1edbc 123 /** Single Mode Input AIN3+; Diff Mode AIN3+/AIN11- */
AnnaBridge 171:3a7713b1edbc 124 MXC_E_ADC_PGA_MUX_CH_SEL_AIN3 = 3,
AnnaBridge 171:3a7713b1edbc 125 /** Single Mode Input AIN4+; Diff Mode AIN4+/AIN12- */
AnnaBridge 171:3a7713b1edbc 126 MXC_E_ADC_PGA_MUX_CH_SEL_AIN4 = 4,
AnnaBridge 171:3a7713b1edbc 127 /** Single Mode Input AIN5+; Diff Mode AIN5+/AIN13- */
AnnaBridge 171:3a7713b1edbc 128 MXC_E_ADC_PGA_MUX_CH_SEL_AIN5 = 5,
AnnaBridge 171:3a7713b1edbc 129 /** Single Mode Input AIN6+; Diff Mode AIN6+/AIN14- */
AnnaBridge 171:3a7713b1edbc 130 MXC_E_ADC_PGA_MUX_CH_SEL_AIN6 = 6,
AnnaBridge 171:3a7713b1edbc 131 /** Single Mode Input AIN7+; Diff Mode AIN7+/AIN15- */
AnnaBridge 171:3a7713b1edbc 132 MXC_E_ADC_PGA_MUX_CH_SEL_AIN7 = 7,
AnnaBridge 171:3a7713b1edbc 133 /** Single Mode Input AIN8+ */
AnnaBridge 171:3a7713b1edbc 134 MXC_E_ADC_PGA_MUX_CH_SEL_AIN8 = 8,
AnnaBridge 171:3a7713b1edbc 135 /** Single Mode Input AIN9+ */
AnnaBridge 171:3a7713b1edbc 136 MXC_E_ADC_PGA_MUX_CH_SEL_AIN9 = 9,
AnnaBridge 171:3a7713b1edbc 137 /** Single Mode Input AIN10+ */
AnnaBridge 171:3a7713b1edbc 138 MXC_E_ADC_PGA_MUX_CH_SEL_AIN10 = 10,
AnnaBridge 171:3a7713b1edbc 139 /** Single Mode Input AIN11+ */
AnnaBridge 171:3a7713b1edbc 140 MXC_E_ADC_PGA_MUX_CH_SEL_AIN11 = 11,
AnnaBridge 171:3a7713b1edbc 141 /** Single Mode Input AIN12+ */
AnnaBridge 171:3a7713b1edbc 142 MXC_E_ADC_PGA_MUX_CH_SEL_AIN12 = 12,
AnnaBridge 171:3a7713b1edbc 143 /** Single Mode Input AIN13+ */
AnnaBridge 171:3a7713b1edbc 144 MXC_E_ADC_PGA_MUX_CH_SEL_AIN13 = 13,
AnnaBridge 171:3a7713b1edbc 145 /** Single Mode Input AIN14+ */
AnnaBridge 171:3a7713b1edbc 146 MXC_E_ADC_PGA_MUX_CH_SEL_AIN14 = 14,
AnnaBridge 171:3a7713b1edbc 147 /** Single Mode Input AIN15+ */
AnnaBridge 171:3a7713b1edbc 148 MXC_E_ADC_PGA_MUX_CH_SEL_AIN15 = 15,
AnnaBridge 171:3a7713b1edbc 149 /** Positive Input VSSADC */
AnnaBridge 171:3a7713b1edbc 150 MXC_E_ADC_PGA_MUX_CH_SEL_VSSADC = 16,
AnnaBridge 171:3a7713b1edbc 151 /** Positive Input TMON_R */
AnnaBridge 171:3a7713b1edbc 152 MXC_E_ADC_PGA_MUX_CH_SEL_TMON_R = 17,
AnnaBridge 171:3a7713b1edbc 153 /** Positive Input VDDA/4 */
AnnaBridge 171:3a7713b1edbc 154 MXC_E_ADC_PGA_MUX_CH_SEL_VDDA4 = 18,
AnnaBridge 171:3a7713b1edbc 155 /** Positive Input PWRMAN_TST */
AnnaBridge 171:3a7713b1edbc 156 MXC_E_ADC_PGA_MUX_CH_SEL_PWRMON_TST = 19,
AnnaBridge 171:3a7713b1edbc 157 /** Positive Input Ain0Div */
AnnaBridge 171:3a7713b1edbc 158 MXC_E_ADC_PGA_MUX_CH_SEL_AIN0DIV = 20,
AnnaBridge 171:3a7713b1edbc 159 /** Positive Input OpAmp OUTA */
AnnaBridge 171:3a7713b1edbc 160 MXC_E_ADC_PGA_MUX_CH_SEL_OUTA = 32,
AnnaBridge 171:3a7713b1edbc 161 /** Positive Input OpAmp OUTB */
AnnaBridge 171:3a7713b1edbc 162 MXC_E_ADC_PGA_MUX_CH_SEL_OUTB = 33,
AnnaBridge 171:3a7713b1edbc 163 /** Positive Input OpAmp OUTC */
AnnaBridge 171:3a7713b1edbc 164 MXC_E_ADC_PGA_MUX_CH_SEL_OUTC = 34,
AnnaBridge 171:3a7713b1edbc 165 /** Positive Input OpAmp OUTD */
AnnaBridge 171:3a7713b1edbc 166 MXC_E_ADC_PGA_MUX_CH_SEL_OUTD = 35,
AnnaBridge 171:3a7713b1edbc 167 /** Positive INA+ */
AnnaBridge 171:3a7713b1edbc 168 MXC_E_ADC_PGA_MUX_CH_SEL_INAPLUS = 36,
AnnaBridge 171:3a7713b1edbc 169 /** Positive SNO_or */
AnnaBridge 171:3a7713b1edbc 170 MXC_E_ADC_PGA_MUX_CH_SEL_SNO_OR = 37,
AnnaBridge 171:3a7713b1edbc 171 /** Positive SCM_or */
AnnaBridge 171:3a7713b1edbc 172 MXC_E_ADC_PGA_MUX_CH_SEL_SCM_OR = 38,
AnnaBridge 171:3a7713b1edbc 173 /** Positive TPROBE_sense */
AnnaBridge 171:3a7713b1edbc 174 MXC_E_ADC_PGA_MUX_CH_SEL_TPROBE_SENSE = 48,
AnnaBridge 171:3a7713b1edbc 175 /** Positive VREFDAC */
AnnaBridge 171:3a7713b1edbc 176 MXC_E_ADC_PGA_MUX_CH_SEL_VREFDAC = 49,
AnnaBridge 171:3a7713b1edbc 177 /** Positive VREFADJ */
AnnaBridge 171:3a7713b1edbc 178 MXC_E_ADC_PGA_MUX_CH_SEL_VREFADJ = 50,
AnnaBridge 171:3a7713b1edbc 179 /** Positive Vdd3xtal */
AnnaBridge 171:3a7713b1edbc 180 MXC_E_ADC_PGA_MUX_CH_SEL_VDD3XTAL = 51
AnnaBridge 171:3a7713b1edbc 181 } mxc_adc_pga_mux_ch_sel_t;
AnnaBridge 171:3a7713b1edbc 182
AnnaBridge 171:3a7713b1edbc 183 /**
AnnaBridge 171:3a7713b1edbc 184 * @brief Decoded with the MUX Channel Select to enable Differential Mode Input to the ADC.
AnnaBridge 171:3a7713b1edbc 185 */
AnnaBridge 171:3a7713b1edbc 186 typedef enum {
AnnaBridge 171:3a7713b1edbc 187 /** Differential Mode Disabled */
AnnaBridge 171:3a7713b1edbc 188 MXC_E_ADC_PGA_MUX_DIFF_DISABLE = 0,
AnnaBridge 171:3a7713b1edbc 189 /** Differential Mode Enabled */
AnnaBridge 171:3a7713b1edbc 190 MXC_E_ADC_PGA_MUX_DIFF_ENABLE
AnnaBridge 171:3a7713b1edbc 191 } mxc_adc_pga_mux_diff_t;
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 /**
AnnaBridge 171:3a7713b1edbc 194 * @brief Defines the PGA Gain Options.
AnnaBridge 171:3a7713b1edbc 195 */
AnnaBridge 171:3a7713b1edbc 196 typedef enum {
AnnaBridge 171:3a7713b1edbc 197 /** PGA Gain = 1 */
AnnaBridge 171:3a7713b1edbc 198 MXC_E_ADC_PGA_GAIN_1 = 0,
AnnaBridge 171:3a7713b1edbc 199 /** PGA Gain = 2 */
AnnaBridge 171:3a7713b1edbc 200 MXC_E_ADC_PGA_GAIN_2,
AnnaBridge 171:3a7713b1edbc 201 /** PGA Gain = 4 */
AnnaBridge 171:3a7713b1edbc 202 MXC_E_ADC_PGA_GAIN_4,
AnnaBridge 171:3a7713b1edbc 203 /** PGA Gain = 8 */
AnnaBridge 171:3a7713b1edbc 204 MXC_E_ADC_PGA_GAIN_8,
AnnaBridge 171:3a7713b1edbc 205 } mxc_adc_pga_gain_t;
AnnaBridge 171:3a7713b1edbc 206
AnnaBridge 171:3a7713b1edbc 207 /**
AnnaBridge 171:3a7713b1edbc 208 * @brief Defines the Switch Control Mode.
AnnaBridge 171:3a7713b1edbc 209 */
AnnaBridge 171:3a7713b1edbc 210 typedef enum {
AnnaBridge 171:3a7713b1edbc 211 /** Switch Control Mode = Software */
AnnaBridge 171:3a7713b1edbc 212 MXC_E_ADC_SPST_SW_CTRL_SOFTWARE = 0,
AnnaBridge 171:3a7713b1edbc 213 /** Switch Control Mode = Pulse Train */
AnnaBridge 171:3a7713b1edbc 214 MXC_E_ADC_SPST_SW_CTRL_PULSETRAIN
AnnaBridge 171:3a7713b1edbc 215 } mxc_adc_spst_sw_ctrl_t;
AnnaBridge 171:3a7713b1edbc 216
AnnaBridge 171:3a7713b1edbc 217 /**
AnnaBridge 171:3a7713b1edbc 218 * @brief Defines the number of channels to scan when Scan Mode is enabled.
AnnaBridge 171:3a7713b1edbc 219 */
AnnaBridge 171:3a7713b1edbc 220 typedef enum {
AnnaBridge 171:3a7713b1edbc 221 /** Number of Channels to Scan = 1 */
AnnaBridge 171:3a7713b1edbc 222 MXC_E_ADC_SCAN_CNT_1 = 0,
AnnaBridge 171:3a7713b1edbc 223 /** Number of Channels to Scan = 2 */
AnnaBridge 171:3a7713b1edbc 224 MXC_E_ADC_SCAN_CNT_2,
AnnaBridge 171:3a7713b1edbc 225 /** Number of Channels to Scan = 3 */
AnnaBridge 171:3a7713b1edbc 226 MXC_E_ADC_SCAN_CNT_3,
AnnaBridge 171:3a7713b1edbc 227 /** Number of Channels to Scan = 4 */
AnnaBridge 171:3a7713b1edbc 228 MXC_E_ADC_SCAN_CNT_4,
AnnaBridge 171:3a7713b1edbc 229 /** Number of Channels to Scan = 5 */
AnnaBridge 171:3a7713b1edbc 230 MXC_E_ADC_SCAN_CNT_5,
AnnaBridge 171:3a7713b1edbc 231 /** Number of Channels to Scan = 6 */
AnnaBridge 171:3a7713b1edbc 232 MXC_E_ADC_SCAN_CNT_6,
AnnaBridge 171:3a7713b1edbc 233 /** Number of Channels to Scan = 7 */
AnnaBridge 171:3a7713b1edbc 234 MXC_E_ADC_SCAN_CNT_7,
AnnaBridge 171:3a7713b1edbc 235 /** Number of Channels to Scan = 8 */
AnnaBridge 171:3a7713b1edbc 236 MXC_E_ADC_SCAN_CNT_8,
AnnaBridge 171:3a7713b1edbc 237 } mxc_adc_scan_cnt_t;
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 240 ====== =================================================== */
AnnaBridge 171:3a7713b1edbc 241 typedef struct {
AnnaBridge 171:3a7713b1edbc 242 __IO uint32_t ctrl0; /* 0x0000 ADC Control Register 0 */
AnnaBridge 171:3a7713b1edbc 243 __IO uint32_t pga_ctrl; /* 0x0004 PGA Control Register */
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t tg_ctrl0; /* 0x0008 ADC Timing Generator Control 0 */
AnnaBridge 171:3a7713b1edbc 245 __IO uint32_t tg_ctrl1; /* 0x000C ADC Timing Generator Control 1 */
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t limit; /* 0x0010 ADC Limit Settings */
AnnaBridge 171:3a7713b1edbc 247 __IO uint32_t intr; /* 0x0014 ADC Interrupt Flags and Enable/Disable Controls */
AnnaBridge 171:3a7713b1edbc 248 __IO uint32_t out; /* 0x0018 ADC Output Register */
AnnaBridge 171:3a7713b1edbc 249 } mxc_adc_regs_t;
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /* Offset Register Description
AnnaBridge 171:3a7713b1edbc 252 ====== =================================================== */
AnnaBridge 171:3a7713b1edbc 253 typedef struct {
AnnaBridge 171:3a7713b1edbc 254 __IO uint32_t ctrl1; /* 0x0000 ADC Control Register 1 */
AnnaBridge 171:3a7713b1edbc 255 __IO uint32_t scan1; /* 0x0004 ADC Auto-Scan Settings 1 */
AnnaBridge 171:3a7713b1edbc 256 __IO uint32_t scan2; /* 0x0008 ADC Auto-Scan Settings 2 */
AnnaBridge 171:3a7713b1edbc 257 __IO uint32_t ro_cal0; /* 0x000C ADC Ring Osc Calibration 0 */
AnnaBridge 171:3a7713b1edbc 258 __IO uint32_t ro_cal1; /* 0x0010 ADC Ring Osc Calibration 1 */
AnnaBridge 171:3a7713b1edbc 259 } mxc_adccfg_regs_t;
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 typedef struct {
AnnaBridge 171:3a7713b1edbc 262 __IO uint16_t data; /* 0x0000 Read to pull sample data from ADC FIFO */
AnnaBridge 171:3a7713b1edbc 263 } mxc_adc_fifo_regs_t;
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /*
AnnaBridge 171:3a7713b1edbc 266 Register offsets for module ADC, ADCCFG, ADC_FIFO
AnnaBridge 171:3a7713b1edbc 267 */
AnnaBridge 171:3a7713b1edbc 268 #define MXC_R_ADC_OFFS_CTRL0 ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 269 #define MXC_R_ADC_OFFS_PGA_CTRL ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 270 #define MXC_R_ADC_OFFS_TG_CTRL0 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 271 #define MXC_R_ADC_OFFS_TG_CTRL1 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 272 #define MXC_R_ADC_OFFS_LIMIT ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 273 #define MXC_R_ADC_OFFS_INTR ((uint32_t)0x00000014UL)
AnnaBridge 171:3a7713b1edbc 274 #define MXC_R_ADC_OFFS_OUT ((uint32_t)0x00000018UL)
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #define MXC_R_ADCCFG_OFFS_CTRL1 ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 277 #define MXC_R_ADCCFG_OFFS_SCAN1 ((uint32_t)0x00000004UL)
AnnaBridge 171:3a7713b1edbc 278 #define MXC_R_ADCCFG_OFFS_SCAN2 ((uint32_t)0x00000008UL)
AnnaBridge 171:3a7713b1edbc 279 #define MXC_R_ADCCFG_OFFS_RO_CAL0 ((uint32_t)0x0000000CUL)
AnnaBridge 171:3a7713b1edbc 280 #define MXC_R_ADCCFG_OFFS_RO_CAL1 ((uint32_t)0x00000010UL)
AnnaBridge 171:3a7713b1edbc 281 #define MXC_R_ADC_FIFO_OFFS_DATA ((uint32_t)0x00000000UL)
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 /*
AnnaBridge 171:3a7713b1edbc 284 Field positions and masks for module ADC.
AnnaBridge 171:3a7713b1edbc 285 */
AnnaBridge 171:3a7713b1edbc 286 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS 0
AnnaBridge 171:3a7713b1edbc 287 #define MXC_F_ADC_CTRL0_ADC_WAKE_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_WAKE_CNT_POS))
AnnaBridge 171:3a7713b1edbc 288 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS 5
AnnaBridge 171:3a7713b1edbc 289 #define MXC_F_ADC_CTRL0_ADC_STRT_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_STRT_MODE_POS))
AnnaBridge 171:3a7713b1edbc 290 #define MXC_F_ADC_CTRL0_ADC_RANGE_POS 6
AnnaBridge 171:3a7713b1edbc 291 #define MXC_F_ADC_CTRL0_ADC_RANGE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_RANGE_POS))
AnnaBridge 171:3a7713b1edbc 292 #define MXC_F_ADC_CTRL0_ADC_BI_POL_POS 7
AnnaBridge 171:3a7713b1edbc 293 #define MXC_F_ADC_CTRL0_ADC_BI_POL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_BI_POL_POS))
AnnaBridge 171:3a7713b1edbc 294 #define MXC_F_ADC_CTRL0_ADC_DV_REG_POS 8
AnnaBridge 171:3a7713b1edbc 295 #define MXC_F_ADC_CTRL0_ADC_DV_REG ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_REG_POS))
AnnaBridge 171:3a7713b1edbc 296 #define MXC_F_ADC_CTRL0_ADC_DV_POS 9
AnnaBridge 171:3a7713b1edbc 297 #define MXC_F_ADC_CTRL0_ADC_DV ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_DV_POS))
AnnaBridge 171:3a7713b1edbc 298 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS 10
AnnaBridge 171:3a7713b1edbc 299 #define MXC_F_ADC_CTRL0_ADC_LMT_DMODE ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_LMT_DMODE_POS))
AnnaBridge 171:3a7713b1edbc 300 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS 11
AnnaBridge 171:3a7713b1edbc 301 #define MXC_F_ADC_CTRL0_ADC_SMP_EXT ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_SMP_EXT_POS))
AnnaBridge 171:3a7713b1edbc 302 #define MXC_F_ADC_CTRL0_ADC_CLK_EN_POS 12
AnnaBridge 171:3a7713b1edbc 303 #define MXC_F_ADC_CTRL0_ADC_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_CLK_EN_POS))
AnnaBridge 171:3a7713b1edbc 304 #define MXC_F_ADC_CTRL0_CPU_ADC_RST_POS 13
AnnaBridge 171:3a7713b1edbc 305 #define MXC_F_ADC_CTRL0_CPU_ADC_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_RST_POS))
AnnaBridge 171:3a7713b1edbc 306 #define MXC_F_ADC_CTRL0_CPU_ADC_START_POS 14
AnnaBridge 171:3a7713b1edbc 307 #define MXC_F_ADC_CTRL0_CPU_ADC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_START_POS))
AnnaBridge 171:3a7713b1edbc 308 #define MXC_F_ADC_CTRL0_CPU_ADC_EN_POS 15
AnnaBridge 171:3a7713b1edbc 309 #define MXC_F_ADC_CTRL0_CPU_ADC_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_ADC_EN_POS))
AnnaBridge 171:3a7713b1edbc 310 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS 18
AnnaBridge 171:3a7713b1edbc 311 #define MXC_F_ADC_CTRL0_ADC_FIFO_FULL ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_FULL_POS))
AnnaBridge 171:3a7713b1edbc 312 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS 19
AnnaBridge 171:3a7713b1edbc 313 #define MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_ADC_FIFO_EMPTY_POS))
AnnaBridge 171:3a7713b1edbc 314 #define MXC_F_ADC_CTRL0_AVG_MODE_POS 20
AnnaBridge 171:3a7713b1edbc 315 #define MXC_F_ADC_CTRL0_AVG_MODE ((uint32_t)(0x00000003UL << MXC_F_ADC_CTRL0_AVG_MODE_POS))
AnnaBridge 171:3a7713b1edbc 316 #define MXC_F_ADC_CTRL0_CPU_DAC_START_POS 22
AnnaBridge 171:3a7713b1edbc 317 #define MXC_F_ADC_CTRL0_CPU_DAC_START ((uint32_t)(0x00000001UL << MXC_F_ADC_CTRL0_CPU_DAC_START_POS))
AnnaBridge 171:3a7713b1edbc 318 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS 24
AnnaBridge 171:3a7713b1edbc 319 #define MXC_F_ADC_CTRL0_ADC_CLK_MODE ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS))
AnnaBridge 171:3a7713b1edbc 320 #define MXC_F_ADC_CTRL0_ADC_MODE_POS 28
AnnaBridge 171:3a7713b1edbc 321 #define MXC_F_ADC_CTRL0_ADC_MODE ((uint32_t)(0x0000000FUL << MXC_F_ADC_CTRL0_ADC_MODE_POS))
AnnaBridge 171:3a7713b1edbc 322
AnnaBridge 171:3a7713b1edbc 323 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS 0
AnnaBridge 171:3a7713b1edbc 324 #define MXC_F_ADC_PGA_CTRL_PGA_GAIN ((uint32_t)(0x00000003UL << MXC_F_ADC_PGA_CTRL_PGA_GAIN_POS))
AnnaBridge 171:3a7713b1edbc 325 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS 2
AnnaBridge 171:3a7713b1edbc 326 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_CLK_EN_POS))
AnnaBridge 171:3a7713b1edbc 327 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS 3
AnnaBridge 171:3a7713b1edbc 328 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_RST ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_RST_POS))
AnnaBridge 171:3a7713b1edbc 329 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS 4
AnnaBridge 171:3a7713b1edbc 330 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_DELAY_POS))
AnnaBridge 171:3a7713b1edbc 331 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS 5
AnnaBridge 171:3a7713b1edbc 332 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_TRK_POS))
AnnaBridge 171:3a7713b1edbc 333 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS 6
AnnaBridge 171:3a7713b1edbc 334 #define MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_CPU_PGA_BYPASS_POS))
AnnaBridge 171:3a7713b1edbc 335 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS 8
AnnaBridge 171:3a7713b1edbc 336 #define MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT ((uint32_t)(0x0000001FUL << MXC_F_ADC_PGA_CTRL_PGA_WAKE_CNT_POS))
AnnaBridge 171:3a7713b1edbc 337 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS 13
AnnaBridge 171:3a7713b1edbc 338 #define MXC_F_ADC_PGA_CTRL_MUX_SW_AIN ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_SW_AIN_POS))
AnnaBridge 171:3a7713b1edbc 339 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS 14
AnnaBridge 171:3a7713b1edbc 340 #define MXC_F_ADC_PGA_CTRL_MUX_DIFF ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS))
AnnaBridge 171:3a7713b1edbc 341 #define MXC_F_ADC_PGA_CTRL_MUX_MODE_POS 15
AnnaBridge 171:3a7713b1edbc 342 #define MXC_F_ADC_PGA_CTRL_MUX_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_PGA_CTRL_MUX_MODE_POS))
AnnaBridge 171:3a7713b1edbc 343 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS 20
AnnaBridge 171:3a7713b1edbc 344 #define MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_PGA_CTRL_PGA_RST_CLK_CNT_POS))
AnnaBridge 171:3a7713b1edbc 345 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS 24
AnnaBridge 171:3a7713b1edbc 346 #define MXC_F_ADC_PGA_CTRL_MUX_CH_SEL ((uint32_t)(0x0000003FUL << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS))
AnnaBridge 171:3a7713b1edbc 347
AnnaBridge 171:3a7713b1edbc 348 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS 0
AnnaBridge 171:3a7713b1edbc 349 #define MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT_POS))
AnnaBridge 171:3a7713b1edbc 350 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS 16
AnnaBridge 171:3a7713b1edbc 351 #define MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS))
AnnaBridge 171:3a7713b1edbc 352
AnnaBridge 171:3a7713b1edbc 353 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS 0
AnnaBridge 171:3a7713b1edbc 354 #define MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS))
AnnaBridge 171:3a7713b1edbc 355 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS 4
AnnaBridge 171:3a7713b1edbc 356 #define MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_FIFO_AF_CNT_POS))
AnnaBridge 171:3a7713b1edbc 357 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS 8
AnnaBridge 171:3a7713b1edbc 358 #define MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT_POS))
AnnaBridge 171:3a7713b1edbc 359 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS 12
AnnaBridge 171:3a7713b1edbc 360 #define MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT ((uint32_t)(0x0000000FUL << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS))
AnnaBridge 171:3a7713b1edbc 361 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS 16
AnnaBridge 171:3a7713b1edbc 362 #define MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS))
AnnaBridge 171:3a7713b1edbc 363
AnnaBridge 171:3a7713b1edbc 364 #define MXC_F_ADC_LIMIT_LO_LIMIT_POS 0
AnnaBridge 171:3a7713b1edbc 365 #define MXC_F_ADC_LIMIT_LO_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_LO_LIMIT_POS))
AnnaBridge 171:3a7713b1edbc 366 #define MXC_F_ADC_LIMIT_HI_LIMIT_POS 16
AnnaBridge 171:3a7713b1edbc 367 #define MXC_F_ADC_LIMIT_HI_LIMIT ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_LIMIT_HI_LIMIT_POS))
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 #define MXC_F_ADC_INTR_FIFO_AF_POS 6
AnnaBridge 171:3a7713b1edbc 370 #define MXC_F_ADC_INTR_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_AF_POS))
AnnaBridge 171:3a7713b1edbc 371 #define MXC_F_ADC_INTR_OUT_RNG_IF_POS 7
AnnaBridge 171:3a7713b1edbc 372 #define MXC_F_ADC_INTR_OUT_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IF_POS))
AnnaBridge 171:3a7713b1edbc 373 #define MXC_F_ADC_INTR_HI_RNG_IF_POS 8
AnnaBridge 171:3a7713b1edbc 374 #define MXC_F_ADC_INTR_HI_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IF_POS))
AnnaBridge 171:3a7713b1edbc 375 #define MXC_F_ADC_INTR_LO_RNG_IF_POS 9
AnnaBridge 171:3a7713b1edbc 376 #define MXC_F_ADC_INTR_LO_RNG_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IF_POS))
AnnaBridge 171:3a7713b1edbc 377 #define MXC_F_ADC_INTR_DONE_IF_POS 10
AnnaBridge 171:3a7713b1edbc 378 #define MXC_F_ADC_INTR_DONE_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IF_POS))
AnnaBridge 171:3a7713b1edbc 379 #define MXC_F_ADC_INTR_FIFO_UF_IF_POS 11
AnnaBridge 171:3a7713b1edbc 380 #define MXC_F_ADC_INTR_FIFO_UF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IF_POS))
AnnaBridge 171:3a7713b1edbc 381 #define MXC_F_ADC_INTR_FIFO_OF_IF_POS 12
AnnaBridge 171:3a7713b1edbc 382 #define MXC_F_ADC_INTR_FIFO_OF_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IF_POS))
AnnaBridge 171:3a7713b1edbc 383 #define MXC_F_ADC_INTR_FIFO_3Q_IF_POS 13
AnnaBridge 171:3a7713b1edbc 384 #define MXC_F_ADC_INTR_FIFO_3Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IF_POS))
AnnaBridge 171:3a7713b1edbc 385 #define MXC_F_ADC_INTR_FIFO_2Q_IF_POS 14
AnnaBridge 171:3a7713b1edbc 386 #define MXC_F_ADC_INTR_FIFO_2Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IF_POS))
AnnaBridge 171:3a7713b1edbc 387 #define MXC_F_ADC_INTR_FIFO_1Q_IF_POS 15
AnnaBridge 171:3a7713b1edbc 388 #define MXC_F_ADC_INTR_FIFO_1Q_IF ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IF_POS))
AnnaBridge 171:3a7713b1edbc 389 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS 16
AnnaBridge 171:3a7713b1edbc 390 #define MXC_F_ADC_INTR_SPST0_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST0_CTRL_MODE_POS))
AnnaBridge 171:3a7713b1edbc 391 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS 17
AnnaBridge 171:3a7713b1edbc 392 #define MXC_F_ADC_INTR_SPST1_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST1_CTRL_MODE_POS))
AnnaBridge 171:3a7713b1edbc 393 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS 18
AnnaBridge 171:3a7713b1edbc 394 #define MXC_F_ADC_INTR_SPST2_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST2_CTRL_MODE_POS))
AnnaBridge 171:3a7713b1edbc 395 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS 19
AnnaBridge 171:3a7713b1edbc 396 #define MXC_F_ADC_INTR_SPST3_CTRL_MODE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_SPST3_CTRL_MODE_POS))
AnnaBridge 171:3a7713b1edbc 397 #define MXC_F_ADC_INTR_OUT_RNG_IE_POS 23
AnnaBridge 171:3a7713b1edbc 398 #define MXC_F_ADC_INTR_OUT_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_OUT_RNG_IE_POS))
AnnaBridge 171:3a7713b1edbc 399 #define MXC_F_ADC_INTR_HI_RNG_IE_POS 24
AnnaBridge 171:3a7713b1edbc 400 #define MXC_F_ADC_INTR_HI_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_HI_RNG_IE_POS))
AnnaBridge 171:3a7713b1edbc 401 #define MXC_F_ADC_INTR_LO_RNG_IE_POS 25
AnnaBridge 171:3a7713b1edbc 402 #define MXC_F_ADC_INTR_LO_RNG_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_LO_RNG_IE_POS))
AnnaBridge 171:3a7713b1edbc 403 #define MXC_F_ADC_INTR_DONE_IE_POS 26
AnnaBridge 171:3a7713b1edbc 404 #define MXC_F_ADC_INTR_DONE_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_DONE_IE_POS))
AnnaBridge 171:3a7713b1edbc 405 #define MXC_F_ADC_INTR_FIFO_UF_IE_POS 27
AnnaBridge 171:3a7713b1edbc 406 #define MXC_F_ADC_INTR_FIFO_UF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_UF_IE_POS))
AnnaBridge 171:3a7713b1edbc 407 #define MXC_F_ADC_INTR_FIFO_OF_IE_POS 28
AnnaBridge 171:3a7713b1edbc 408 #define MXC_F_ADC_INTR_FIFO_OF_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_OF_IE_POS))
AnnaBridge 171:3a7713b1edbc 409 #define MXC_F_ADC_INTR_FIFO_3Q_IE_POS 29
AnnaBridge 171:3a7713b1edbc 410 #define MXC_F_ADC_INTR_FIFO_3Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_3Q_IE_POS))
AnnaBridge 171:3a7713b1edbc 411 #define MXC_F_ADC_INTR_FIFO_2Q_IE_POS 30
AnnaBridge 171:3a7713b1edbc 412 #define MXC_F_ADC_INTR_FIFO_2Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_2Q_IE_POS))
AnnaBridge 171:3a7713b1edbc 413 #define MXC_F_ADC_INTR_FIFO_1Q_IE_POS 31
AnnaBridge 171:3a7713b1edbc 414 #define MXC_F_ADC_INTR_FIFO_1Q_IE ((uint32_t)(0x00000001UL << MXC_F_ADC_INTR_FIFO_1Q_IE_POS))
AnnaBridge 171:3a7713b1edbc 415
AnnaBridge 171:3a7713b1edbc 416 #define MXC_F_ADC_OUT_DATA_REG_POS 0
AnnaBridge 171:3a7713b1edbc 417 #define MXC_F_ADC_OUT_DATA_REG ((uint32_t)(0x0000FFFFUL << MXC_F_ADC_OUT_DATA_REG_POS))
AnnaBridge 171:3a7713b1edbc 418
AnnaBridge 171:3a7713b1edbc 419 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS 16
AnnaBridge 171:3a7713b1edbc 420 #define MXC_F_ADC_CTRL1_ADC_SCAN_CNT ((uint32_t)(0x00000007UL << MXC_F_ADC_CTRL1_ADC_SCAN_CNT_POS))
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 #define MXC_F_ADC_SCAN1_ADC_SCAN0_POS 0
AnnaBridge 171:3a7713b1edbc 423 #define MXC_F_ADC_SCAN1_ADC_SCAN0 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN0_POS))
AnnaBridge 171:3a7713b1edbc 424 #define MXC_F_ADC_SCAN1_ADC_SCAN1_POS 8
AnnaBridge 171:3a7713b1edbc 425 #define MXC_F_ADC_SCAN1_ADC_SCAN1 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN1_POS))
AnnaBridge 171:3a7713b1edbc 426 #define MXC_F_ADC_SCAN1_ADC_SCAN2_POS 16
AnnaBridge 171:3a7713b1edbc 427 #define MXC_F_ADC_SCAN1_ADC_SCAN2 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN2_POS))
AnnaBridge 171:3a7713b1edbc 428 #define MXC_F_ADC_SCAN1_ADC_SCAN3_POS 24
AnnaBridge 171:3a7713b1edbc 429 #define MXC_F_ADC_SCAN1_ADC_SCAN3 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN1_ADC_SCAN3_POS))
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 #define MXC_F_ADC_SCAN2_ADC_SCAN4_POS 0
AnnaBridge 171:3a7713b1edbc 432 #define MXC_F_ADC_SCAN2_ADC_SCAN4 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN4_POS))
AnnaBridge 171:3a7713b1edbc 433 #define MXC_F_ADC_SCAN2_ADC_SCAN5_POS 8
AnnaBridge 171:3a7713b1edbc 434 #define MXC_F_ADC_SCAN2_ADC_SCAN5 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN5_POS))
AnnaBridge 171:3a7713b1edbc 435 #define MXC_F_ADC_SCAN2_ADC_SCAN6_POS 16
AnnaBridge 171:3a7713b1edbc 436 #define MXC_F_ADC_SCAN2_ADC_SCAN6 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN6_POS))
AnnaBridge 171:3a7713b1edbc 437 #define MXC_F_ADC_SCAN2_ADC_SCAN7_POS 24
AnnaBridge 171:3a7713b1edbc 438 #define MXC_F_ADC_SCAN2_ADC_SCAN7 ((uint32_t)(0x000000FFUL << MXC_F_ADC_SCAN2_ADC_SCAN7_POS))
AnnaBridge 171:3a7713b1edbc 439
AnnaBridge 171:3a7713b1edbc 440 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS 0
AnnaBridge 171:3a7713b1edbc 441 #define MXC_F_ADC_RO_CAL0_RO_CAL_EN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_EN_POS))
AnnaBridge 171:3a7713b1edbc 442 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS 1
AnnaBridge 171:3a7713b1edbc 443 #define MXC_F_ADC_RO_CAL0_RO_CAL_RUN ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_RUN_POS))
AnnaBridge 171:3a7713b1edbc 444 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS 2
AnnaBridge 171:3a7713b1edbc 445 #define MXC_F_ADC_RO_CAL0_RO_CAL_LOAD ((uint32_t)(0x00000001UL << MXC_F_ADC_RO_CAL0_RO_CAL_LOAD_POS))
AnnaBridge 171:3a7713b1edbc 446 #define MXC_F_ADC_RO_CAL0_TRM_MU_POS 8
AnnaBridge 171:3a7713b1edbc 447 #define MXC_F_ADC_RO_CAL0_TRM_MU ((uint32_t)(0x00000FFFUL << MXC_F_ADC_RO_CAL0_TRM_MU_POS))
AnnaBridge 171:3a7713b1edbc 448 #define MXC_F_ADC_RO_CAL0_RO_TRM_POS 23
AnnaBridge 171:3a7713b1edbc 449 #define MXC_F_ADC_RO_CAL0_RO_TRM ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL0_RO_TRM_POS))
AnnaBridge 171:3a7713b1edbc 450
AnnaBridge 171:3a7713b1edbc 451 #define MXC_F_ADC_RO_CAL1_TRM_INIT_POS 0
AnnaBridge 171:3a7713b1edbc 452 #define MXC_F_ADC_RO_CAL1_TRM_INIT ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_INIT_POS))
AnnaBridge 171:3a7713b1edbc 453 #define MXC_F_ADC_RO_CAL1_TRM_MIN_POS 10
AnnaBridge 171:3a7713b1edbc 454 #define MXC_F_ADC_RO_CAL1_TRM_MIN ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MIN_POS))
AnnaBridge 171:3a7713b1edbc 455 #define MXC_F_ADC_RO_CAL1_TRM_MAX_POS 20
AnnaBridge 171:3a7713b1edbc 456 #define MXC_F_ADC_RO_CAL1_TRM_MAX ((uint32_t)(0x000001FFUL << MXC_F_ADC_RO_CAL1_TRM_MAX_POS))
AnnaBridge 171:3a7713b1edbc 457
AnnaBridge 171:3a7713b1edbc 458 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 459 }
AnnaBridge 171:3a7713b1edbc 460 #endif
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 /**
AnnaBridge 171:3a7713b1edbc 463 * @}
AnnaBridge 171:3a7713b1edbc 464 */
AnnaBridge 171:3a7713b1edbc 465
AnnaBridge 171:3a7713b1edbc 466 #endif /* _MXC_ADC_REGS_H */