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TARGET_LPC546XX/TOOLCHAIN_GCC_ARM/fsl_sdif.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | * The Clear BSD License |
AnnaBridge | 171:3a7713b1edbc | 3 | * Copyright (c) 2016, Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 4 | * Copyright 2016-2017 NXP |
AnnaBridge | 171:3a7713b1edbc | 5 | * All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 6 | * |
AnnaBridge | 171:3a7713b1edbc | 7 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 8 | * are permitted (subject to the limitations in the disclaimer below) provided |
AnnaBridge | 171:3a7713b1edbc | 9 | * that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 12 | * of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 13 | * |
AnnaBridge | 171:3a7713b1edbc | 14 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 15 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 16 | * other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * o Neither the name of the copyright holder nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 19 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 20 | * software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. |
AnnaBridge | 171:3a7713b1edbc | 23 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 24 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 25 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 26 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 27 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 28 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 29 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 30 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 31 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 32 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 33 | */ |
AnnaBridge | 171:3a7713b1edbc | 34 | #ifndef _FSL_SDIF_H_ |
AnnaBridge | 171:3a7713b1edbc | 35 | #define _FSL_SDIF_H_ |
AnnaBridge | 171:3a7713b1edbc | 36 | |
AnnaBridge | 171:3a7713b1edbc | 37 | #include "fsl_common.h" |
AnnaBridge | 171:3a7713b1edbc | 38 | |
AnnaBridge | 171:3a7713b1edbc | 39 | /*! |
AnnaBridge | 171:3a7713b1edbc | 40 | * @addtogroup sdif |
AnnaBridge | 171:3a7713b1edbc | 41 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /********************************** |
AnnaBridge | 171:3a7713b1edbc | 45 | * Definitions. |
AnnaBridge | 171:3a7713b1edbc | 46 | *****************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 47 | |
AnnaBridge | 171:3a7713b1edbc | 48 | /*! @name Driver version */ |
AnnaBridge | 171:3a7713b1edbc | 49 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 50 | /*! @brief Driver version 2.0.4. */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U)) |
AnnaBridge | 171:3a7713b1edbc | 52 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 53 | |
AnnaBridge | 171:3a7713b1edbc | 54 | /*! @brief SDIOCLKCTRL setting |
AnnaBridge | 171:3a7713b1edbc | 55 | * Below clock delay setting should depend on specific platform, so |
AnnaBridge | 171:3a7713b1edbc | 56 | * it can be redefined when timing mismatch issue occur. |
AnnaBridge | 171:3a7713b1edbc | 57 | * Such as: response error/CRC error and so on |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | /*! @brief clock range value which need to add delay to avoid timing issue */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #ifndef SDIF_CLOCK_RANGE_NEED_DELAY |
AnnaBridge | 171:3a7713b1edbc | 61 | #define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U) |
AnnaBridge | 171:3a7713b1edbc | 62 | #endif |
AnnaBridge | 171:3a7713b1edbc | 63 | |
AnnaBridge | 171:3a7713b1edbc | 64 | /* |
AnnaBridge | 171:3a7713b1edbc | 65 | * Fixed delay configuration |
AnnaBridge | 171:3a7713b1edbc | 66 | * min hold time:2ns |
AnnaBridge | 171:3a7713b1edbc | 67 | * min setup time: 6ns |
AnnaBridge | 171:3a7713b1edbc | 68 | * delay = (x+1)*250ps |
AnnaBridge | 171:3a7713b1edbc | 69 | */ |
AnnaBridge | 171:3a7713b1edbc | 70 | /*! @brief High speed mode clk_sample fixed delay*/ |
AnnaBridge | 171:3a7713b1edbc | 71 | #ifndef SDIF_HIGHSPEED_SAMPLE_DELAY |
AnnaBridge | 171:3a7713b1edbc | 72 | #define SDIF_HIGHSPEED_SAMPLE_DELAY (0U) |
AnnaBridge | 171:3a7713b1edbc | 73 | #endif |
AnnaBridge | 171:3a7713b1edbc | 74 | /*! @brief High speed mode clk_drv fixed delay */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #ifndef SDIF_HIGHSPEED_DRV_DELAY |
AnnaBridge | 171:3a7713b1edbc | 76 | #define SDIF_HIGHSPEED_DRV_DELAY (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 77 | #endif |
AnnaBridge | 171:3a7713b1edbc | 78 | |
AnnaBridge | 171:3a7713b1edbc | 79 | /* |
AnnaBridge | 171:3a7713b1edbc | 80 | * Pharse shift delay configuration |
AnnaBridge | 171:3a7713b1edbc | 81 | * 0 degree: no delay |
AnnaBridge | 171:3a7713b1edbc | 82 | * 90 degree: 0.25/source clk value |
AnnaBridge | 171:3a7713b1edbc | 83 | * 180 degree: 0.50/source clk value |
AnnaBridge | 171:3a7713b1edbc | 84 | * 270 degree: 0.75/source clk value |
AnnaBridge | 171:3a7713b1edbc | 85 | */ |
AnnaBridge | 171:3a7713b1edbc | 86 | /*! @brief High speed mode clk_sample pharse shift */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT |
AnnaBridge | 171:3a7713b1edbc | 88 | #define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 89 | #endif |
AnnaBridge | 171:3a7713b1edbc | 90 | /*! @brief High speed mode clk_drv pharse shift */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT |
AnnaBridge | 171:3a7713b1edbc | 92 | #define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv pharse delay */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #endif |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | /*! @brief SDIF status */ |
AnnaBridge | 171:3a7713b1edbc | 96 | enum _sdif_status |
AnnaBridge | 171:3a7713b1edbc | 97 | { |
AnnaBridge | 171:3a7713b1edbc | 98 | kStatus_SDIF_DescriptorBufferLenError = MAKE_STATUS(kStatusGroup_SDIF, 0U), /*!< Set DMA descriptor failed */ |
AnnaBridge | 171:3a7713b1edbc | 99 | kStatue_SDIF_InvalidArgument = MAKE_STATUS(kStatusGroup_SDIF, 1U), /*!< invalid argument status */ |
AnnaBridge | 171:3a7713b1edbc | 100 | kStatus_SDIF_SyncCmdTimeout = MAKE_STATUS(kStatusGroup_SDIF, 2U), /*!< sync command to CIU timeout status */ |
AnnaBridge | 171:3a7713b1edbc | 101 | kStatus_SDIF_SendCmdFail = MAKE_STATUS(kStatusGroup_SDIF, 3U), /* send command to card fail */ |
AnnaBridge | 171:3a7713b1edbc | 102 | kStatus_SDIF_SendCmdErrorBufferFull = |
AnnaBridge | 171:3a7713b1edbc | 103 | MAKE_STATUS(kStatusGroup_SDIF, 4U), /* send command to card fail, due to command buffer full |
AnnaBridge | 171:3a7713b1edbc | 104 | user need to resend this command */ |
AnnaBridge | 171:3a7713b1edbc | 105 | kStatus_SDIF_DMATransferFailWithFBE = |
AnnaBridge | 171:3a7713b1edbc | 106 | MAKE_STATUS(kStatusGroup_SDIF, 5U), /* DMA transfer data fail with fatal bus error , |
AnnaBridge | 171:3a7713b1edbc | 107 | to do with this error :issue a hard reset/controller reset*/ |
AnnaBridge | 171:3a7713b1edbc | 108 | kStatus_SDIF_DMATransferDescriptorUnavaliable = MAKE_STATUS(kStatusGroup_SDIF, 6U), /* DMA descriptor unavalible */ |
AnnaBridge | 171:3a7713b1edbc | 109 | kStatus_SDIF_DataTransferFail = MAKE_STATUS(kStatusGroup_SDIF, 6U), /* transfer data fail */ |
AnnaBridge | 171:3a7713b1edbc | 110 | kStatus_SDIF_ResponseError = MAKE_STATUS(kStatusGroup_SDIF, 7U), |
AnnaBridge | 171:3a7713b1edbc | 111 | }; |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | /*! @brief Host controller capabilities flag mask */ |
AnnaBridge | 171:3a7713b1edbc | 114 | enum _sdif_capability_flag |
AnnaBridge | 171:3a7713b1edbc | 115 | { |
AnnaBridge | 171:3a7713b1edbc | 116 | kSDIF_SupportHighSpeedFlag = 0x1U, /*!< Support high-speed */ |
AnnaBridge | 171:3a7713b1edbc | 117 | kSDIF_SupportDmaFlag = 0x2U, /*!< Support DMA */ |
AnnaBridge | 171:3a7713b1edbc | 118 | kSDIF_SupportSuspendResumeFlag = 0x4U, /*!< Support suspend/resume */ |
AnnaBridge | 171:3a7713b1edbc | 119 | kSDIF_SupportV330Flag = 0x8U, /*!< Support voltage 3.3V */ |
AnnaBridge | 171:3a7713b1edbc | 120 | kSDIF_Support4BitFlag = 0x10U, /*!< Support 4 bit mode */ |
AnnaBridge | 171:3a7713b1edbc | 121 | kSDIF_Support8BitFlag = 0x20U, /*!< Support 8 bit mode */ |
AnnaBridge | 171:3a7713b1edbc | 122 | }; |
AnnaBridge | 171:3a7713b1edbc | 123 | |
AnnaBridge | 171:3a7713b1edbc | 124 | /*! @brief define the reset type */ |
AnnaBridge | 171:3a7713b1edbc | 125 | enum _sdif_reset_type |
AnnaBridge | 171:3a7713b1edbc | 126 | { |
AnnaBridge | 171:3a7713b1edbc | 127 | kSDIF_ResetController = |
AnnaBridge | 171:3a7713b1edbc | 128 | SDIF_CTRL_CONTROLLER_RESET_MASK, /*!< reset controller,will reset: BIU/CIU interface |
AnnaBridge | 171:3a7713b1edbc | 129 | CIU and state machine,ABORT_READ_DATA,SEND_IRQ_RESPONSE |
AnnaBridge | 171:3a7713b1edbc | 130 | and READ_WAIT bits of control register,START_CMD bit of the |
AnnaBridge | 171:3a7713b1edbc | 131 | command register*/ |
AnnaBridge | 171:3a7713b1edbc | 132 | kSDIF_ResetFIFO = SDIF_CTRL_FIFO_RESET_MASK, /*!< reset data FIFO*/ |
AnnaBridge | 171:3a7713b1edbc | 133 | kSDIF_ResetDMAInterface = SDIF_CTRL_DMA_RESET_MASK, /*!< reset DMA interface */ |
AnnaBridge | 171:3a7713b1edbc | 134 | |
AnnaBridge | 171:3a7713b1edbc | 135 | kSDIF_ResetAll = kSDIF_ResetController | kSDIF_ResetFIFO | /*!< reset all*/ |
AnnaBridge | 171:3a7713b1edbc | 136 | kSDIF_ResetDMAInterface, |
AnnaBridge | 171:3a7713b1edbc | 137 | }; |
AnnaBridge | 171:3a7713b1edbc | 138 | |
AnnaBridge | 171:3a7713b1edbc | 139 | /*! @brief define the card bus width type */ |
AnnaBridge | 171:3a7713b1edbc | 140 | typedef enum _sdif_bus_width |
AnnaBridge | 171:3a7713b1edbc | 141 | { |
AnnaBridge | 171:3a7713b1edbc | 142 | kSDIF_Bus1BitWidth = 0U, /*!< 1bit bus width, 1bit mode and 4bit mode |
AnnaBridge | 171:3a7713b1edbc | 143 | share one register bit */ |
AnnaBridge | 171:3a7713b1edbc | 144 | kSDIF_Bus4BitWidth = SDIF_CTYPE_CARD_WIDTH0_MASK, /*!< 4bit mode mask */ |
AnnaBridge | 171:3a7713b1edbc | 145 | kSDIF_Bus8BitWidth = SDIF_CTYPE_CARD_WIDTH1_MASK, /*!< support 8 bit mode */ |
AnnaBridge | 171:3a7713b1edbc | 146 | } sdif_bus_width_t; |
AnnaBridge | 171:3a7713b1edbc | 147 | |
AnnaBridge | 171:3a7713b1edbc | 148 | /*! @brief define the command flags */ |
AnnaBridge | 171:3a7713b1edbc | 149 | enum _sdif_command_flags |
AnnaBridge | 171:3a7713b1edbc | 150 | { |
AnnaBridge | 171:3a7713b1edbc | 151 | kSDIF_CmdResponseExpect = SDIF_CMD_RESPONSE_EXPECT_MASK, /*!< command request response*/ |
AnnaBridge | 171:3a7713b1edbc | 152 | kSDIF_CmdResponseLengthLong = SDIF_CMD_RESPONSE_LENGTH_MASK, /*!< command response length long */ |
AnnaBridge | 171:3a7713b1edbc | 153 | kSDIF_CmdCheckResponseCRC = SDIF_CMD_CHECK_RESPONSE_CRC_MASK, /*!< request check command response CRC*/ |
AnnaBridge | 171:3a7713b1edbc | 154 | kSDIF_DataExpect = SDIF_CMD_DATA_EXPECTED_MASK, /*!< request data transfer,ethier read/write*/ |
AnnaBridge | 171:3a7713b1edbc | 155 | kSDIF_DataWriteToCard = SDIF_CMD_READ_WRITE_MASK, /*!< data transfer direction */ |
AnnaBridge | 171:3a7713b1edbc | 156 | kSDIF_DataStreamTransfer = SDIF_CMD_TRANSFER_MODE_MASK, /*!< data transfer mode :stream/block transfer command */ |
AnnaBridge | 171:3a7713b1edbc | 157 | kSDIF_DataTransferAutoStop = SDIF_CMD_SEND_AUTO_STOP_MASK, /*!< data transfer with auto stop at the end of */ |
AnnaBridge | 171:3a7713b1edbc | 158 | kSDIF_WaitPreTransferComplete = |
AnnaBridge | 171:3a7713b1edbc | 159 | SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK, /*!< wait pre transfer complete before sending this cmd */ |
AnnaBridge | 171:3a7713b1edbc | 160 | kSDIF_TransferStopAbort = |
AnnaBridge | 171:3a7713b1edbc | 161 | SDIF_CMD_STOP_ABORT_CMD_MASK, /*!< when host issue stop or abort cmd to stop data transfer |
AnnaBridge | 171:3a7713b1edbc | 162 | ,this bit should set so that cmd/data state-machines of CIU can return |
AnnaBridge | 171:3a7713b1edbc | 163 | to idle correctly*/ |
AnnaBridge | 171:3a7713b1edbc | 164 | kSDIF_SendInitialization = |
AnnaBridge | 171:3a7713b1edbc | 165 | SDIF_CMD_SEND_INITIALIZATION_MASK, /*!< send initaliztion 80 clocks for SD card after power on */ |
AnnaBridge | 171:3a7713b1edbc | 166 | kSDIF_CmdUpdateClockRegisterOnly = |
AnnaBridge | 171:3a7713b1edbc | 167 | SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK, /*!< send cmd update the CIU clock register only */ |
AnnaBridge | 171:3a7713b1edbc | 168 | kSDIF_CmdtoReadCEATADevice = SDIF_CMD_READ_CEATA_DEVICE_MASK, /*!< host is perform read access to CE-ATA device */ |
AnnaBridge | 171:3a7713b1edbc | 169 | kSDIF_CmdExpectCCS = SDIF_CMD_CCS_EXPECTED_MASK, /*!< command expect command completion signal signal */ |
AnnaBridge | 171:3a7713b1edbc | 170 | kSDIF_BootModeEnable = SDIF_CMD_ENABLE_BOOT_MASK, /*!< this bit should only be set for mandatory boot mode */ |
AnnaBridge | 171:3a7713b1edbc | 171 | kSDIF_BootModeExpectAck = SDIF_CMD_EXPECT_BOOT_ACK_MASK, /*!< boot mode expect ack */ |
AnnaBridge | 171:3a7713b1edbc | 172 | kSDIF_BootModeDisable = SDIF_CMD_DISABLE_BOOT_MASK, /*!< when software set this bit along with START_CMD, CIU |
AnnaBridge | 171:3a7713b1edbc | 173 | terminates the boot operation*/ |
AnnaBridge | 171:3a7713b1edbc | 174 | kSDIF_BootModeAlternate = SDIF_CMD_BOOT_MODE_MASK, /*!< select boot mode ,alternate or mandatory*/ |
AnnaBridge | 171:3a7713b1edbc | 175 | kSDIF_CmdVoltageSwitch = SDIF_CMD_VOLT_SWITCH_MASK, /*!< this bit set for CMD11 only */ |
AnnaBridge | 171:3a7713b1edbc | 176 | kSDIF_CmdDataUseHoldReg = SDIF_CMD_USE_HOLD_REG_MASK, /*!< cmd and data send to card through the HOLD register*/ |
AnnaBridge | 171:3a7713b1edbc | 177 | }; |
AnnaBridge | 171:3a7713b1edbc | 178 | |
AnnaBridge | 171:3a7713b1edbc | 179 | /*! @brief The command type */ |
AnnaBridge | 171:3a7713b1edbc | 180 | enum _sdif_command_type |
AnnaBridge | 171:3a7713b1edbc | 181 | { |
AnnaBridge | 171:3a7713b1edbc | 182 | kCARD_CommandTypeNormal = 0U, /*!< Normal command */ |
AnnaBridge | 171:3a7713b1edbc | 183 | kCARD_CommandTypeSuspend = 1U, /*!< Suspend command */ |
AnnaBridge | 171:3a7713b1edbc | 184 | kCARD_CommandTypeResume = 2U, /*!< Resume command */ |
AnnaBridge | 171:3a7713b1edbc | 185 | kCARD_CommandTypeAbort = 3U, /*!< Abort command */ |
AnnaBridge | 171:3a7713b1edbc | 186 | }; |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | /*! |
AnnaBridge | 171:3a7713b1edbc | 189 | * @brief The command response type. |
AnnaBridge | 171:3a7713b1edbc | 190 | * |
AnnaBridge | 171:3a7713b1edbc | 191 | * Define the command response type from card to host controller. |
AnnaBridge | 171:3a7713b1edbc | 192 | */ |
AnnaBridge | 171:3a7713b1edbc | 193 | enum _sdif_response_type |
AnnaBridge | 171:3a7713b1edbc | 194 | { |
AnnaBridge | 171:3a7713b1edbc | 195 | kCARD_ResponseTypeNone = 0U, /*!< Response type: none */ |
AnnaBridge | 171:3a7713b1edbc | 196 | kCARD_ResponseTypeR1 = 1U, /*!< Response type: R1 */ |
AnnaBridge | 171:3a7713b1edbc | 197 | kCARD_ResponseTypeR1b = 2U, /*!< Response type: R1b */ |
AnnaBridge | 171:3a7713b1edbc | 198 | kCARD_ResponseTypeR2 = 3U, /*!< Response type: R2 */ |
AnnaBridge | 171:3a7713b1edbc | 199 | kCARD_ResponseTypeR3 = 4U, /*!< Response type: R3 */ |
AnnaBridge | 171:3a7713b1edbc | 200 | kCARD_ResponseTypeR4 = 5U, /*!< Response type: R4 */ |
AnnaBridge | 171:3a7713b1edbc | 201 | kCARD_ResponseTypeR5 = 6U, /*!< Response type: R5 */ |
AnnaBridge | 171:3a7713b1edbc | 202 | kCARD_ResponseTypeR5b = 7U, /*!< Response type: R5b */ |
AnnaBridge | 171:3a7713b1edbc | 203 | kCARD_ResponseTypeR6 = 8U, /*!< Response type: R6 */ |
AnnaBridge | 171:3a7713b1edbc | 204 | kCARD_ResponseTypeR7 = 9U, /*!< Response type: R7 */ |
AnnaBridge | 171:3a7713b1edbc | 205 | }; |
AnnaBridge | 171:3a7713b1edbc | 206 | |
AnnaBridge | 171:3a7713b1edbc | 207 | /*! @brief define the interrupt mask flags */ |
AnnaBridge | 171:3a7713b1edbc | 208 | enum _sdif_interrupt_mask |
AnnaBridge | 171:3a7713b1edbc | 209 | { |
AnnaBridge | 171:3a7713b1edbc | 210 | kSDIF_CardDetect = SDIF_INTMASK_CDET_MASK, /*!< mask for card detect */ |
AnnaBridge | 171:3a7713b1edbc | 211 | kSDIF_ResponseError = SDIF_INTMASK_RE_MASK, /*!< command response error */ |
AnnaBridge | 171:3a7713b1edbc | 212 | kSDIF_CommandDone = SDIF_INTMASK_CDONE_MASK, /*!< command transfer over*/ |
AnnaBridge | 171:3a7713b1edbc | 213 | kSDIF_DataTransferOver = SDIF_INTMASK_DTO_MASK, /*!< data transfer over flag*/ |
AnnaBridge | 171:3a7713b1edbc | 214 | kSDIF_WriteFIFORequest = SDIF_INTMASK_TXDR_MASK, /*!< write FIFO request */ |
AnnaBridge | 171:3a7713b1edbc | 215 | kSDIF_ReadFIFORequest = SDIF_INTMASK_RXDR_MASK, /*!< read FIFO request */ |
AnnaBridge | 171:3a7713b1edbc | 216 | kSDIF_ResponseCRCError = SDIF_INTMASK_RCRC_MASK, /*!< reponse CRC error */ |
AnnaBridge | 171:3a7713b1edbc | 217 | kSDIF_DataCRCError = SDIF_INTMASK_DCRC_MASK, /*!< data CRC error */ |
AnnaBridge | 171:3a7713b1edbc | 218 | kSDIF_ResponseTimeout = SDIF_INTMASK_RTO_MASK, /*!< response timeout */ |
AnnaBridge | 171:3a7713b1edbc | 219 | kSDIF_DataReadTimeout = SDIF_INTMASK_DRTO_MASK, /*!< read data timeout */ |
AnnaBridge | 171:3a7713b1edbc | 220 | kSDIF_DataStarvationByHostTimeout = SDIF_INTMASK_HTO_MASK, /*!< data starvation by host time out */ |
AnnaBridge | 171:3a7713b1edbc | 221 | kSDIF_FIFOError = SDIF_INTMASK_FRUN_MASK, /*!< indicate the FIFO underrun or overrun error */ |
AnnaBridge | 171:3a7713b1edbc | 222 | kSDIF_HardwareLockError = SDIF_INTMASK_HLE_MASK, /*!< hardware lock write error */ |
AnnaBridge | 171:3a7713b1edbc | 223 | kSDIF_DataStartBitError = SDIF_INTMASK_SBE_MASK, /*!< start bit error */ |
AnnaBridge | 171:3a7713b1edbc | 224 | kSDIF_AutoCmdDone = SDIF_INTMASK_ACD_MASK, /*!< indicate the auto command done */ |
AnnaBridge | 171:3a7713b1edbc | 225 | kSDIF_DataEndBitError = SDIF_INTMASK_EBE_MASK, /*!< end bit error */ |
AnnaBridge | 171:3a7713b1edbc | 226 | kSDIF_SDIOInterrupt = SDIF_INTMASK_SDIO_INT_MASK_MASK, /*!< interrupt from the SDIO card */ |
AnnaBridge | 171:3a7713b1edbc | 227 | |
AnnaBridge | 171:3a7713b1edbc | 228 | kSDIF_CommandTransferStatus = kSDIF_ResponseError | kSDIF_CommandDone | kSDIF_ResponseCRCError | |
AnnaBridge | 171:3a7713b1edbc | 229 | kSDIF_ResponseTimeout | |
AnnaBridge | 171:3a7713b1edbc | 230 | kSDIF_HardwareLockError, /*!< command transfer status collection*/ |
AnnaBridge | 171:3a7713b1edbc | 231 | kSDIF_DataTransferStatus = kSDIF_DataTransferOver | kSDIF_WriteFIFORequest | kSDIF_ReadFIFORequest | |
AnnaBridge | 171:3a7713b1edbc | 232 | kSDIF_DataCRCError | kSDIF_DataReadTimeout | kSDIF_DataStarvationByHostTimeout | |
AnnaBridge | 171:3a7713b1edbc | 233 | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | |
AnnaBridge | 171:3a7713b1edbc | 234 | kSDIF_AutoCmdDone, /*!< data transfer status collection */ |
AnnaBridge | 171:3a7713b1edbc | 235 | kSDIF_DataTransferError = |
AnnaBridge | 171:3a7713b1edbc | 236 | kSDIF_DataCRCError | kSDIF_FIFOError | kSDIF_DataStartBitError | kSDIF_DataEndBitError | kSDIF_DataReadTimeout, |
AnnaBridge | 171:3a7713b1edbc | 237 | kSDIF_AllInterruptStatus = 0x1FFFFU, /*!< all interrupt mask */ |
AnnaBridge | 171:3a7713b1edbc | 238 | |
AnnaBridge | 171:3a7713b1edbc | 239 | }; |
AnnaBridge | 171:3a7713b1edbc | 240 | |
AnnaBridge | 171:3a7713b1edbc | 241 | /*! @brief define the internal DMA status flags */ |
AnnaBridge | 171:3a7713b1edbc | 242 | enum _sdif_dma_status |
AnnaBridge | 171:3a7713b1edbc | 243 | { |
AnnaBridge | 171:3a7713b1edbc | 244 | kSDIF_DMATransFinishOneDescriptor = SDIF_IDSTS_TI_MASK, /*!< DMA transfer finished for one DMA descriptor */ |
AnnaBridge | 171:3a7713b1edbc | 245 | kSDIF_DMARecvFinishOneDescriptor = SDIF_IDSTS_RI_MASK, /*!< DMA revieve finished for one DMA descriptor */ |
AnnaBridge | 171:3a7713b1edbc | 246 | kSDIF_DMAFatalBusError = SDIF_IDSTS_FBE_MASK, /*!< DMA fatal bus error */ |
AnnaBridge | 171:3a7713b1edbc | 247 | kSDIF_DMADescriptorUnavailable = SDIF_IDSTS_DU_MASK, /*!< DMA descriptor unavailable */ |
AnnaBridge | 171:3a7713b1edbc | 248 | kSDIF_DMACardErrorSummary = SDIF_IDSTS_CES_MASK, /*!< card error summary */ |
AnnaBridge | 171:3a7713b1edbc | 249 | kSDIF_NormalInterruptSummary = SDIF_IDSTS_NIS_MASK, /*!< normal interrupt summary */ |
AnnaBridge | 171:3a7713b1edbc | 250 | kSDIF_AbnormalInterruptSummary = SDIF_IDSTS_AIS_MASK, /*!< abnormal interrupt summary*/ |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | kSDIF_DMAAllStatus = kSDIF_DMATransFinishOneDescriptor | kSDIF_DMARecvFinishOneDescriptor | kSDIF_DMAFatalBusError | |
AnnaBridge | 171:3a7713b1edbc | 253 | kSDIF_DMADescriptorUnavailable | kSDIF_DMACardErrorSummary | kSDIF_NormalInterruptSummary | |
AnnaBridge | 171:3a7713b1edbc | 254 | kSDIF_AbnormalInterruptSummary, |
AnnaBridge | 171:3a7713b1edbc | 255 | |
AnnaBridge | 171:3a7713b1edbc | 256 | }; |
AnnaBridge | 171:3a7713b1edbc | 257 | |
AnnaBridge | 171:3a7713b1edbc | 258 | /*! @brief define the internal DMA descriptor flag */ |
AnnaBridge | 171:3a7713b1edbc | 259 | enum _sdif_dma_descriptor_flag |
AnnaBridge | 171:3a7713b1edbc | 260 | { |
AnnaBridge | 171:3a7713b1edbc | 261 | kSDIF_DisableCompleteInterrupt = 0x2U, /*!< disable the complete interrupt flag for the ends |
AnnaBridge | 171:3a7713b1edbc | 262 | in the buffer pointed to by this descriptor*/ |
AnnaBridge | 171:3a7713b1edbc | 263 | kSDIF_DMADescriptorDataBufferEnd = 0x4U, /*!< indicate this descriptor contain the last data buffer of data */ |
AnnaBridge | 171:3a7713b1edbc | 264 | kSDIF_DMADescriptorDataBufferStart = 0x8U, /*!< indicate this descriptor contain the first data buffer |
AnnaBridge | 171:3a7713b1edbc | 265 | of data,if first buffer size is 0,next descriptor contain |
AnnaBridge | 171:3a7713b1edbc | 266 | the begaining of the data*/ |
AnnaBridge | 171:3a7713b1edbc | 267 | kSDIF_DMASecondAddrChained = 0x10U, /*!< indicate that the second addr in the descriptor is the |
AnnaBridge | 171:3a7713b1edbc | 268 | next descriptor addr not the data buffer */ |
AnnaBridge | 171:3a7713b1edbc | 269 | kSDIF_DMADescriptorEnd = 0x20U, /*!< indicate that the descriptor list reached its final descriptor*/ |
AnnaBridge | 171:3a7713b1edbc | 270 | kSDIF_DMADescriptorOwnByDMA = 0x80000000U, /*!< indicate the descriptor is own by SD/MMC DMA */ |
AnnaBridge | 171:3a7713b1edbc | 271 | }; |
AnnaBridge | 171:3a7713b1edbc | 272 | |
AnnaBridge | 171:3a7713b1edbc | 273 | /*! @brief define the internal DMA mode */ |
AnnaBridge | 171:3a7713b1edbc | 274 | typedef enum _sdif_dma_mode |
AnnaBridge | 171:3a7713b1edbc | 275 | { |
AnnaBridge | 171:3a7713b1edbc | 276 | kSDIF_ChainDMAMode = 0x01U, /* one descriptor with one buffer,but one descriptor point to another */ |
AnnaBridge | 171:3a7713b1edbc | 277 | kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */ |
AnnaBridge | 171:3a7713b1edbc | 278 | } sdif_dma_mode_t; |
AnnaBridge | 171:3a7713b1edbc | 279 | |
AnnaBridge | 171:3a7713b1edbc | 280 | /*! @brief define the internal DMA descriptor */ |
AnnaBridge | 171:3a7713b1edbc | 281 | typedef struct _sdif_dma_descriptor |
AnnaBridge | 171:3a7713b1edbc | 282 | { |
AnnaBridge | 171:3a7713b1edbc | 283 | uint32_t dmaDesAttribute; /*!< internal DMA attribute control and status */ |
AnnaBridge | 171:3a7713b1edbc | 284 | uint32_t dmaDataBufferSize; /*!< internal DMA transfer buffer size control */ |
AnnaBridge | 171:3a7713b1edbc | 285 | const uint32_t *dmaDataBufferAddr0; /*!< internal DMA buffer 0 addr ,the buffer size must be 32bit aligned */ |
AnnaBridge | 171:3a7713b1edbc | 286 | const uint32_t *dmaDataBufferAddr1; /*!< internal DMA buffer 1 addr ,the buffer size must be 32bit aligned */ |
AnnaBridge | 171:3a7713b1edbc | 287 | |
AnnaBridge | 171:3a7713b1edbc | 288 | } sdif_dma_descriptor_t; |
AnnaBridge | 171:3a7713b1edbc | 289 | |
AnnaBridge | 171:3a7713b1edbc | 290 | /*! @brief Defines the internal DMA config structure. */ |
AnnaBridge | 171:3a7713b1edbc | 291 | typedef struct _sdif_dma_config |
AnnaBridge | 171:3a7713b1edbc | 292 | { |
AnnaBridge | 171:3a7713b1edbc | 293 | bool enableFixBurstLen; /*!< fix burst len enable/disable flag,When set, the AHB will |
AnnaBridge | 171:3a7713b1edbc | 294 | use only SINGLE, INCR4, INCR8 or INCR16 during start of |
AnnaBridge | 171:3a7713b1edbc | 295 | normal burst transfers. When reset, the AHB will use SINGLE |
AnnaBridge | 171:3a7713b1edbc | 296 | and INCR burst transfer operations */ |
AnnaBridge | 171:3a7713b1edbc | 297 | |
AnnaBridge | 171:3a7713b1edbc | 298 | sdif_dma_mode_t mode; /*!< define the DMA mode */ |
AnnaBridge | 171:3a7713b1edbc | 299 | |
AnnaBridge | 171:3a7713b1edbc | 300 | uint8_t dmaDesSkipLen; /*!< define the descriptor skip length ,the length between two descriptor |
AnnaBridge | 171:3a7713b1edbc | 301 | this field is special for dual DMA mode */ |
AnnaBridge | 171:3a7713b1edbc | 302 | |
AnnaBridge | 171:3a7713b1edbc | 303 | uint32_t *dmaDesBufferStartAddr; /*!< internal DMA descriptor start address*/ |
AnnaBridge | 171:3a7713b1edbc | 304 | uint32_t dmaDesBufferLen; /*!< internal DMA buffer descriptor buffer len ,user need to pay attention to the |
AnnaBridge | 171:3a7713b1edbc | 305 | dma descriptor buffer length if it is bigger enough for your transfer */ |
AnnaBridge | 171:3a7713b1edbc | 306 | |
AnnaBridge | 171:3a7713b1edbc | 307 | } sdif_dma_config_t; |
AnnaBridge | 171:3a7713b1edbc | 308 | |
AnnaBridge | 171:3a7713b1edbc | 309 | /*! |
AnnaBridge | 171:3a7713b1edbc | 310 | * @brief Card data descriptor |
AnnaBridge | 171:3a7713b1edbc | 311 | */ |
AnnaBridge | 171:3a7713b1edbc | 312 | typedef struct _sdif_data |
AnnaBridge | 171:3a7713b1edbc | 313 | { |
AnnaBridge | 171:3a7713b1edbc | 314 | bool streamTransfer; /*!< indicate this is a stream data transfer command */ |
AnnaBridge | 171:3a7713b1edbc | 315 | bool enableAutoCommand12; /*!< indicate if auto stop will send when data transfer over */ |
AnnaBridge | 171:3a7713b1edbc | 316 | bool enableIgnoreError; /*!< indicate if enable ignore error when transfer data */ |
AnnaBridge | 171:3a7713b1edbc | 317 | |
AnnaBridge | 171:3a7713b1edbc | 318 | size_t blockSize; /*!< Block size, take care when config this parameter */ |
AnnaBridge | 171:3a7713b1edbc | 319 | uint32_t blockCount; /*!< Block count */ |
AnnaBridge | 171:3a7713b1edbc | 320 | uint32_t *rxData; /*!< data buffer to recieve */ |
AnnaBridge | 171:3a7713b1edbc | 321 | const uint32_t *txData; /*!< data buffer to transfer */ |
AnnaBridge | 171:3a7713b1edbc | 322 | } sdif_data_t; |
AnnaBridge | 171:3a7713b1edbc | 323 | |
AnnaBridge | 171:3a7713b1edbc | 324 | /*! |
AnnaBridge | 171:3a7713b1edbc | 325 | * @brief Card command descriptor |
AnnaBridge | 171:3a7713b1edbc | 326 | * |
AnnaBridge | 171:3a7713b1edbc | 327 | * Define card command-related attribute. |
AnnaBridge | 171:3a7713b1edbc | 328 | */ |
AnnaBridge | 171:3a7713b1edbc | 329 | typedef struct _sdif_command |
AnnaBridge | 171:3a7713b1edbc | 330 | { |
AnnaBridge | 171:3a7713b1edbc | 331 | uint32_t index; /*!< Command index */ |
AnnaBridge | 171:3a7713b1edbc | 332 | uint32_t argument; /*!< Command argument */ |
AnnaBridge | 171:3a7713b1edbc | 333 | uint32_t response[4U]; /*!< Response for this command */ |
AnnaBridge | 171:3a7713b1edbc | 334 | uint32_t type; /*!< define the command type */ |
AnnaBridge | 171:3a7713b1edbc | 335 | uint32_t responseType; /*!< Command response type */ |
AnnaBridge | 171:3a7713b1edbc | 336 | uint32_t flags; /*!< Cmd flags */ |
AnnaBridge | 171:3a7713b1edbc | 337 | uint32_t responseErrorFlags; /*!< response error flags, need to check the flags when |
AnnaBridge | 171:3a7713b1edbc | 338 | recieve the cmd response */ |
AnnaBridge | 171:3a7713b1edbc | 339 | } sdif_command_t; |
AnnaBridge | 171:3a7713b1edbc | 340 | |
AnnaBridge | 171:3a7713b1edbc | 341 | /*! @brief Transfer state */ |
AnnaBridge | 171:3a7713b1edbc | 342 | typedef struct _sdif_transfer |
AnnaBridge | 171:3a7713b1edbc | 343 | { |
AnnaBridge | 171:3a7713b1edbc | 344 | sdif_data_t *data; /*!< Data to transfer */ |
AnnaBridge | 171:3a7713b1edbc | 345 | sdif_command_t *command; /*!< Command to send */ |
AnnaBridge | 171:3a7713b1edbc | 346 | } sdif_transfer_t; |
AnnaBridge | 171:3a7713b1edbc | 347 | |
AnnaBridge | 171:3a7713b1edbc | 348 | /*! @brief Data structure to initialize the sdif */ |
AnnaBridge | 171:3a7713b1edbc | 349 | typedef struct _sdif_config |
AnnaBridge | 171:3a7713b1edbc | 350 | { |
AnnaBridge | 171:3a7713b1edbc | 351 | uint8_t responseTimeout; /*!< command reponse timeout value */ |
AnnaBridge | 171:3a7713b1edbc | 352 | uint32_t cardDetDebounce_Clock; /*!< define the debounce clock count which will used in |
AnnaBridge | 171:3a7713b1edbc | 353 | card detect logic,typical value is 5-25ms */ |
AnnaBridge | 171:3a7713b1edbc | 354 | uint32_t endianMode; /*!< define endian mode ,this field is not used in this |
AnnaBridge | 171:3a7713b1edbc | 355 | module actually, keep for compatible with middleware*/ |
AnnaBridge | 171:3a7713b1edbc | 356 | uint32_t dataTimeout; /*!< data timeout value */ |
AnnaBridge | 171:3a7713b1edbc | 357 | } sdif_config_t; |
AnnaBridge | 171:3a7713b1edbc | 358 | |
AnnaBridge | 171:3a7713b1edbc | 359 | /*! |
AnnaBridge | 171:3a7713b1edbc | 360 | * @brief SDIF capability information. |
AnnaBridge | 171:3a7713b1edbc | 361 | * Defines a structure to get the capability information of SDIF. |
AnnaBridge | 171:3a7713b1edbc | 362 | */ |
AnnaBridge | 171:3a7713b1edbc | 363 | typedef struct _sdif_capability |
AnnaBridge | 171:3a7713b1edbc | 364 | { |
AnnaBridge | 171:3a7713b1edbc | 365 | uint32_t sdVersion; /*!< support SD card/sdio version */ |
AnnaBridge | 171:3a7713b1edbc | 366 | uint32_t mmcVersion; /*!< support emmc card version */ |
AnnaBridge | 171:3a7713b1edbc | 367 | uint32_t maxBlockLength; /*!< Maximum block length united as byte */ |
AnnaBridge | 171:3a7713b1edbc | 368 | uint32_t maxBlockCount; /*!< Maximum byte count can be transfered */ |
AnnaBridge | 171:3a7713b1edbc | 369 | uint32_t flags; /*!< Capability flags to indicate the support information */ |
AnnaBridge | 171:3a7713b1edbc | 370 | } sdif_capability_t; |
AnnaBridge | 171:3a7713b1edbc | 371 | |
AnnaBridge | 171:3a7713b1edbc | 372 | /*! @brief sdif callback functions. */ |
AnnaBridge | 171:3a7713b1edbc | 373 | typedef struct _sdif_transfer_callback |
AnnaBridge | 171:3a7713b1edbc | 374 | { |
AnnaBridge | 171:3a7713b1edbc | 375 | void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */ |
AnnaBridge | 171:3a7713b1edbc | 376 | void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */ |
AnnaBridge | 171:3a7713b1edbc | 377 | void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */ |
AnnaBridge | 171:3a7713b1edbc | 378 | void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */ |
AnnaBridge | 171:3a7713b1edbc | 379 | void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */ |
AnnaBridge | 171:3a7713b1edbc | 380 | void (*TransferComplete)(SDIF_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 381 | void *handle, |
AnnaBridge | 171:3a7713b1edbc | 382 | status_t status, |
AnnaBridge | 171:3a7713b1edbc | 383 | void *userData); /*!< Transfer complete callback */ |
AnnaBridge | 171:3a7713b1edbc | 384 | } sdif_transfer_callback_t; |
AnnaBridge | 171:3a7713b1edbc | 385 | |
AnnaBridge | 171:3a7713b1edbc | 386 | /*! |
AnnaBridge | 171:3a7713b1edbc | 387 | * @brief sdif handle |
AnnaBridge | 171:3a7713b1edbc | 388 | * |
AnnaBridge | 171:3a7713b1edbc | 389 | * Defines the structure to save the sdif state information and callback function. The detail interrupt status when |
AnnaBridge | 171:3a7713b1edbc | 390 | * send command or transfer data can be obtained from interruptFlags field by using mask defined in |
AnnaBridge | 171:3a7713b1edbc | 391 | * sdif_interrupt_flag_t; |
AnnaBridge | 171:3a7713b1edbc | 392 | * @note All the fields except interruptFlags and transferredWords must be allocated by the user. |
AnnaBridge | 171:3a7713b1edbc | 393 | */ |
AnnaBridge | 171:3a7713b1edbc | 394 | typedef struct _sdif_handle |
AnnaBridge | 171:3a7713b1edbc | 395 | { |
AnnaBridge | 171:3a7713b1edbc | 396 | /* Transfer parameter */ |
AnnaBridge | 171:3a7713b1edbc | 397 | sdif_data_t *volatile data; /*!< Data to transfer */ |
AnnaBridge | 171:3a7713b1edbc | 398 | sdif_command_t *volatile command; /*!< Command to send */ |
AnnaBridge | 171:3a7713b1edbc | 399 | |
AnnaBridge | 171:3a7713b1edbc | 400 | /* Transfer status */ |
AnnaBridge | 171:3a7713b1edbc | 401 | volatile uint32_t interruptFlags; /*!< Interrupt flags of last transaction */ |
AnnaBridge | 171:3a7713b1edbc | 402 | volatile uint32_t dmaInterruptFlags; /*!< DMA interrupt flags of last transaction*/ |
AnnaBridge | 171:3a7713b1edbc | 403 | volatile uint32_t transferredWords; /*!< Words transferred by polling way */ |
AnnaBridge | 171:3a7713b1edbc | 404 | |
AnnaBridge | 171:3a7713b1edbc | 405 | /* Callback functions */ |
AnnaBridge | 171:3a7713b1edbc | 406 | sdif_transfer_callback_t callback; /*!< Callback function */ |
AnnaBridge | 171:3a7713b1edbc | 407 | void *userData; /*!< Parameter for transfer complete callback */ |
AnnaBridge | 171:3a7713b1edbc | 408 | } sdif_handle_t; |
AnnaBridge | 171:3a7713b1edbc | 409 | |
AnnaBridge | 171:3a7713b1edbc | 410 | /*! @brief sdif transfer function. */ |
AnnaBridge | 171:3a7713b1edbc | 411 | typedef status_t (*sdif_transfer_function_t)(SDIF_Type *base, sdif_transfer_t *content); |
AnnaBridge | 171:3a7713b1edbc | 412 | |
AnnaBridge | 171:3a7713b1edbc | 413 | /*! @brief sdif host descriptor */ |
AnnaBridge | 171:3a7713b1edbc | 414 | typedef struct _sdif_host |
AnnaBridge | 171:3a7713b1edbc | 415 | { |
AnnaBridge | 171:3a7713b1edbc | 416 | SDIF_Type *base; /*!< sdif peripheral base address */ |
AnnaBridge | 171:3a7713b1edbc | 417 | uint32_t sourceClock_Hz; /*!< sdif source clock frequency united in Hz */ |
AnnaBridge | 171:3a7713b1edbc | 418 | sdif_config_t config; /*!< sdif configuration */ |
AnnaBridge | 171:3a7713b1edbc | 419 | sdif_transfer_function_t transfer; /*!< sdif transfer function */ |
AnnaBridge | 171:3a7713b1edbc | 420 | sdif_capability_t capability; /*!< sdif capability information */ |
AnnaBridge | 171:3a7713b1edbc | 421 | } sdif_host_t; |
AnnaBridge | 171:3a7713b1edbc | 422 | |
AnnaBridge | 171:3a7713b1edbc | 423 | /************************************************************************************************* |
AnnaBridge | 171:3a7713b1edbc | 424 | * API |
AnnaBridge | 171:3a7713b1edbc | 425 | ************************************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 426 | #if defined(__cplusplus) |
AnnaBridge | 171:3a7713b1edbc | 427 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 428 | #endif |
AnnaBridge | 171:3a7713b1edbc | 429 | |
AnnaBridge | 171:3a7713b1edbc | 430 | /*! |
AnnaBridge | 171:3a7713b1edbc | 431 | * @brief SDIF module initialization function. |
AnnaBridge | 171:3a7713b1edbc | 432 | * |
AnnaBridge | 171:3a7713b1edbc | 433 | * Configures the SDIF according to the user configuration. |
AnnaBridge | 171:3a7713b1edbc | 434 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 435 | * @param config SDIF configuration information. |
AnnaBridge | 171:3a7713b1edbc | 436 | */ |
AnnaBridge | 171:3a7713b1edbc | 437 | void SDIF_Init(SDIF_Type *base, sdif_config_t *config); |
AnnaBridge | 171:3a7713b1edbc | 438 | |
AnnaBridge | 171:3a7713b1edbc | 439 | /*! |
AnnaBridge | 171:3a7713b1edbc | 440 | * @brief SDIF module deinit function. |
AnnaBridge | 171:3a7713b1edbc | 441 | * user should call this function follow with IP reset |
AnnaBridge | 171:3a7713b1edbc | 442 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 443 | */ |
AnnaBridge | 171:3a7713b1edbc | 444 | void SDIF_Deinit(SDIF_Type *base); |
AnnaBridge | 171:3a7713b1edbc | 445 | |
AnnaBridge | 171:3a7713b1edbc | 446 | /*! |
AnnaBridge | 171:3a7713b1edbc | 447 | * @brief SDIF send initialize 80 clocks for SD card after initilize |
AnnaBridge | 171:3a7713b1edbc | 448 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 449 | * @param timeout value |
AnnaBridge | 171:3a7713b1edbc | 450 | */ |
AnnaBridge | 171:3a7713b1edbc | 451 | bool SDIF_SendCardActive(SDIF_Type *base, uint32_t timeout); |
AnnaBridge | 171:3a7713b1edbc | 452 | |
AnnaBridge | 171:3a7713b1edbc | 453 | /*! |
AnnaBridge | 171:3a7713b1edbc | 454 | * @brief SDIF module detect card insert status function. |
AnnaBridge | 171:3a7713b1edbc | 455 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 456 | * @param data3 indicate use data3 as card insert detect pin |
AnnaBridge | 171:3a7713b1edbc | 457 | * @retval 1 card is inserted |
AnnaBridge | 171:3a7713b1edbc | 458 | * 0 card is removed |
AnnaBridge | 171:3a7713b1edbc | 459 | */ |
AnnaBridge | 171:3a7713b1edbc | 460 | static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3) |
AnnaBridge | 171:3a7713b1edbc | 461 | { |
AnnaBridge | 171:3a7713b1edbc | 462 | if (data3) |
AnnaBridge | 171:3a7713b1edbc | 463 | { |
AnnaBridge | 171:3a7713b1edbc | 464 | return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U; |
AnnaBridge | 171:3a7713b1edbc | 465 | } |
AnnaBridge | 171:3a7713b1edbc | 466 | else |
AnnaBridge | 171:3a7713b1edbc | 467 | { |
AnnaBridge | 171:3a7713b1edbc | 468 | return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U; |
AnnaBridge | 171:3a7713b1edbc | 469 | } |
AnnaBridge | 171:3a7713b1edbc | 470 | } |
AnnaBridge | 171:3a7713b1edbc | 471 | |
AnnaBridge | 171:3a7713b1edbc | 472 | /*! |
AnnaBridge | 171:3a7713b1edbc | 473 | * @brief SDIF module enable/disable card clock. |
AnnaBridge | 171:3a7713b1edbc | 474 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 475 | * @param enable/disable flag |
AnnaBridge | 171:3a7713b1edbc | 476 | */ |
AnnaBridge | 171:3a7713b1edbc | 477 | static inline void SDIF_EnableCardClock(SDIF_Type *base, bool enable) |
AnnaBridge | 171:3a7713b1edbc | 478 | { |
AnnaBridge | 171:3a7713b1edbc | 479 | if (enable) |
AnnaBridge | 171:3a7713b1edbc | 480 | { |
AnnaBridge | 171:3a7713b1edbc | 481 | base->CLKENA |= SDIF_CLKENA_CCLK_ENABLE_MASK; |
AnnaBridge | 171:3a7713b1edbc | 482 | } |
AnnaBridge | 171:3a7713b1edbc | 483 | else |
AnnaBridge | 171:3a7713b1edbc | 484 | { |
AnnaBridge | 171:3a7713b1edbc | 485 | base->CLKENA &= ~SDIF_CLKENA_CCLK_ENABLE_MASK; |
AnnaBridge | 171:3a7713b1edbc | 486 | } |
AnnaBridge | 171:3a7713b1edbc | 487 | } |
AnnaBridge | 171:3a7713b1edbc | 488 | |
AnnaBridge | 171:3a7713b1edbc | 489 | /*! |
AnnaBridge | 171:3a7713b1edbc | 490 | * @brief SDIF module enable/disable module disable the card clock |
AnnaBridge | 171:3a7713b1edbc | 491 | * to enter low power mode when card is idle,for SDIF cards, if |
AnnaBridge | 171:3a7713b1edbc | 492 | * interrupts must be detected, clock should not be stopped |
AnnaBridge | 171:3a7713b1edbc | 493 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 494 | * @param enable/disable flag |
AnnaBridge | 171:3a7713b1edbc | 495 | */ |
AnnaBridge | 171:3a7713b1edbc | 496 | static inline void SDIF_EnableLowPowerMode(SDIF_Type *base, bool enable) |
AnnaBridge | 171:3a7713b1edbc | 497 | { |
AnnaBridge | 171:3a7713b1edbc | 498 | if (enable) |
AnnaBridge | 171:3a7713b1edbc | 499 | { |
AnnaBridge | 171:3a7713b1edbc | 500 | base->CLKENA |= SDIF_CLKENA_CCLK_LOW_POWER_MASK; |
AnnaBridge | 171:3a7713b1edbc | 501 | } |
AnnaBridge | 171:3a7713b1edbc | 502 | else |
AnnaBridge | 171:3a7713b1edbc | 503 | { |
AnnaBridge | 171:3a7713b1edbc | 504 | base->CLKENA &= ~SDIF_CLKENA_CCLK_LOW_POWER_MASK; |
AnnaBridge | 171:3a7713b1edbc | 505 | } |
AnnaBridge | 171:3a7713b1edbc | 506 | } |
AnnaBridge | 171:3a7713b1edbc | 507 | |
AnnaBridge | 171:3a7713b1edbc | 508 | /*! |
AnnaBridge | 171:3a7713b1edbc | 509 | * @brief Sets the card bus clock frequency. |
AnnaBridge | 171:3a7713b1edbc | 510 | * |
AnnaBridge | 171:3a7713b1edbc | 511 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 512 | * @param srcClock_Hz SDIF source clock frequency united in Hz. |
AnnaBridge | 171:3a7713b1edbc | 513 | * @param target_HZ card bus clock frequency united in Hz. |
AnnaBridge | 171:3a7713b1edbc | 514 | * @return The nearest frequency of busClock_Hz configured to SD bus. |
AnnaBridge | 171:3a7713b1edbc | 515 | */ |
AnnaBridge | 171:3a7713b1edbc | 516 | uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ); |
AnnaBridge | 171:3a7713b1edbc | 517 | |
AnnaBridge | 171:3a7713b1edbc | 518 | /*! |
AnnaBridge | 171:3a7713b1edbc | 519 | * @brief reset the different block of the interface. |
AnnaBridge | 171:3a7713b1edbc | 520 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 521 | * @param mask indicate which block to reset. |
AnnaBridge | 171:3a7713b1edbc | 522 | * @param timeout value,set to wait the bit self clear |
AnnaBridge | 171:3a7713b1edbc | 523 | * @return reset result. |
AnnaBridge | 171:3a7713b1edbc | 524 | */ |
AnnaBridge | 171:3a7713b1edbc | 525 | bool SDIF_Reset(SDIF_Type *base, uint32_t mask, uint32_t timeout); |
AnnaBridge | 171:3a7713b1edbc | 526 | |
AnnaBridge | 171:3a7713b1edbc | 527 | /*! |
AnnaBridge | 171:3a7713b1edbc | 528 | * @brief enable/disable the card power. |
AnnaBridge | 171:3a7713b1edbc | 529 | * once turn power on, software should wait for regulator/switch |
AnnaBridge | 171:3a7713b1edbc | 530 | * ramp-up time before trying to initialize card. |
AnnaBridge | 171:3a7713b1edbc | 531 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 532 | * @param enable/disable flag. |
AnnaBridge | 171:3a7713b1edbc | 533 | */ |
AnnaBridge | 171:3a7713b1edbc | 534 | static inline void SDIF_EnableCardPower(SDIF_Type *base, bool enable) |
AnnaBridge | 171:3a7713b1edbc | 535 | { |
AnnaBridge | 171:3a7713b1edbc | 536 | if (enable) |
AnnaBridge | 171:3a7713b1edbc | 537 | { |
AnnaBridge | 171:3a7713b1edbc | 538 | base->PWREN |= SDIF_PWREN_POWER_ENABLE_MASK; |
AnnaBridge | 171:3a7713b1edbc | 539 | } |
AnnaBridge | 171:3a7713b1edbc | 540 | else |
AnnaBridge | 171:3a7713b1edbc | 541 | { |
AnnaBridge | 171:3a7713b1edbc | 542 | base->PWREN &= ~SDIF_PWREN_POWER_ENABLE_MASK; |
AnnaBridge | 171:3a7713b1edbc | 543 | } |
AnnaBridge | 171:3a7713b1edbc | 544 | } |
AnnaBridge | 171:3a7713b1edbc | 545 | |
AnnaBridge | 171:3a7713b1edbc | 546 | /*! |
AnnaBridge | 171:3a7713b1edbc | 547 | * @brief get the card write protect status |
AnnaBridge | 171:3a7713b1edbc | 548 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 549 | */ |
AnnaBridge | 171:3a7713b1edbc | 550 | static inline uint32_t SDIF_GetCardWriteProtect(SDIF_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 551 | { |
AnnaBridge | 171:3a7713b1edbc | 552 | return base->WRTPRT & SDIF_WRTPRT_WRITE_PROTECT_MASK; |
AnnaBridge | 171:3a7713b1edbc | 553 | } |
AnnaBridge | 171:3a7713b1edbc | 554 | |
AnnaBridge | 171:3a7713b1edbc | 555 | /*! |
AnnaBridge | 171:3a7713b1edbc | 556 | * @brief set card data bus width |
AnnaBridge | 171:3a7713b1edbc | 557 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 558 | * @param data bus width type |
AnnaBridge | 171:3a7713b1edbc | 559 | */ |
AnnaBridge | 171:3a7713b1edbc | 560 | static inline void SDIF_SetCardBusWidth(SDIF_Type *base, sdif_bus_width_t type) |
AnnaBridge | 171:3a7713b1edbc | 561 | { |
AnnaBridge | 171:3a7713b1edbc | 562 | base->CTYPE = type; |
AnnaBridge | 171:3a7713b1edbc | 563 | } |
AnnaBridge | 171:3a7713b1edbc | 564 | |
AnnaBridge | 171:3a7713b1edbc | 565 | /*! |
AnnaBridge | 171:3a7713b1edbc | 566 | * @brief toggle state on hardware reset PIN |
AnnaBridge | 171:3a7713b1edbc | 567 | * This is used which card has a reset PIN typically. |
AnnaBridge | 171:3a7713b1edbc | 568 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 569 | */ |
AnnaBridge | 171:3a7713b1edbc | 570 | static inline void SDIF_AssertHardwareReset(SDIF_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 571 | { |
AnnaBridge | 171:3a7713b1edbc | 572 | base->RST_N &= ~SDIF_RST_N_CARD_RESET_MASK; |
AnnaBridge | 171:3a7713b1edbc | 573 | } |
AnnaBridge | 171:3a7713b1edbc | 574 | |
AnnaBridge | 171:3a7713b1edbc | 575 | /*! |
AnnaBridge | 171:3a7713b1edbc | 576 | * @brief send command to the card |
AnnaBridge | 171:3a7713b1edbc | 577 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 578 | * @param command configuration collection |
AnnaBridge | 171:3a7713b1edbc | 579 | * @param timeout value |
AnnaBridge | 171:3a7713b1edbc | 580 | * @return command excute status |
AnnaBridge | 171:3a7713b1edbc | 581 | */ |
AnnaBridge | 171:3a7713b1edbc | 582 | status_t SDIF_SendCommand(SDIF_Type *base, sdif_command_t *cmd, uint32_t timeout); |
AnnaBridge | 171:3a7713b1edbc | 583 | |
AnnaBridge | 171:3a7713b1edbc | 584 | /*! |
AnnaBridge | 171:3a7713b1edbc | 585 | * @brief SDIF enable/disable global interrupt |
AnnaBridge | 171:3a7713b1edbc | 586 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 587 | * @param enable/disable flag |
AnnaBridge | 171:3a7713b1edbc | 588 | */ |
AnnaBridge | 171:3a7713b1edbc | 589 | static inline void SDIF_EnableGlobalInterrupt(SDIF_Type *base, bool enable) |
AnnaBridge | 171:3a7713b1edbc | 590 | { |
AnnaBridge | 171:3a7713b1edbc | 591 | if (enable) |
AnnaBridge | 171:3a7713b1edbc | 592 | { |
AnnaBridge | 171:3a7713b1edbc | 593 | base->CTRL |= SDIF_CTRL_INT_ENABLE_MASK; |
AnnaBridge | 171:3a7713b1edbc | 594 | } |
AnnaBridge | 171:3a7713b1edbc | 595 | else |
AnnaBridge | 171:3a7713b1edbc | 596 | { |
AnnaBridge | 171:3a7713b1edbc | 597 | base->CTRL &= ~SDIF_CTRL_INT_ENABLE_MASK; |
AnnaBridge | 171:3a7713b1edbc | 598 | } |
AnnaBridge | 171:3a7713b1edbc | 599 | } |
AnnaBridge | 171:3a7713b1edbc | 600 | |
AnnaBridge | 171:3a7713b1edbc | 601 | /*! |
AnnaBridge | 171:3a7713b1edbc | 602 | * @brief SDIF enable interrupt |
AnnaBridge | 171:3a7713b1edbc | 603 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 604 | * @param interrupt mask |
AnnaBridge | 171:3a7713b1edbc | 605 | */ |
AnnaBridge | 171:3a7713b1edbc | 606 | static inline void SDIF_EnableInterrupt(SDIF_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 607 | { |
AnnaBridge | 171:3a7713b1edbc | 608 | base->INTMASK |= mask; |
AnnaBridge | 171:3a7713b1edbc | 609 | } |
AnnaBridge | 171:3a7713b1edbc | 610 | |
AnnaBridge | 171:3a7713b1edbc | 611 | /*! |
AnnaBridge | 171:3a7713b1edbc | 612 | * @brief SDIF disable interrupt |
AnnaBridge | 171:3a7713b1edbc | 613 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 614 | * @param interrupt mask |
AnnaBridge | 171:3a7713b1edbc | 615 | */ |
AnnaBridge | 171:3a7713b1edbc | 616 | static inline void SDIF_DisableInterrupt(SDIF_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 617 | { |
AnnaBridge | 171:3a7713b1edbc | 618 | base->INTMASK &= ~mask; |
AnnaBridge | 171:3a7713b1edbc | 619 | } |
AnnaBridge | 171:3a7713b1edbc | 620 | |
AnnaBridge | 171:3a7713b1edbc | 621 | /*! |
AnnaBridge | 171:3a7713b1edbc | 622 | * @brief SDIF get interrupt status |
AnnaBridge | 171:3a7713b1edbc | 623 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 624 | */ |
AnnaBridge | 171:3a7713b1edbc | 625 | static inline uint32_t SDIF_GetInterruptStatus(SDIF_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 626 | { |
AnnaBridge | 171:3a7713b1edbc | 627 | return base->MINTSTS; |
AnnaBridge | 171:3a7713b1edbc | 628 | } |
AnnaBridge | 171:3a7713b1edbc | 629 | |
AnnaBridge | 171:3a7713b1edbc | 630 | /*! |
AnnaBridge | 171:3a7713b1edbc | 631 | * @brief SDIF clear interrupt status |
AnnaBridge | 171:3a7713b1edbc | 632 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 633 | * @param status mask to clear |
AnnaBridge | 171:3a7713b1edbc | 634 | */ |
AnnaBridge | 171:3a7713b1edbc | 635 | static inline void SDIF_ClearInterruptStatus(SDIF_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 636 | { |
AnnaBridge | 171:3a7713b1edbc | 637 | base->RINTSTS &= mask; |
AnnaBridge | 171:3a7713b1edbc | 638 | } |
AnnaBridge | 171:3a7713b1edbc | 639 | |
AnnaBridge | 171:3a7713b1edbc | 640 | /*! |
AnnaBridge | 171:3a7713b1edbc | 641 | * @brief Creates the SDIF handle. |
AnnaBridge | 171:3a7713b1edbc | 642 | * register call back function for interrupt and enable the interrupt |
AnnaBridge | 171:3a7713b1edbc | 643 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 644 | * @param handle SDIF handle pointer. |
AnnaBridge | 171:3a7713b1edbc | 645 | * @param callback Structure pointer to contain all callback functions. |
AnnaBridge | 171:3a7713b1edbc | 646 | * @param userData Callback function parameter. |
AnnaBridge | 171:3a7713b1edbc | 647 | */ |
AnnaBridge | 171:3a7713b1edbc | 648 | void SDIF_TransferCreateHandle(SDIF_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 649 | sdif_handle_t *handle, |
AnnaBridge | 171:3a7713b1edbc | 650 | sdif_transfer_callback_t *callback, |
AnnaBridge | 171:3a7713b1edbc | 651 | void *userData); |
AnnaBridge | 171:3a7713b1edbc | 652 | |
AnnaBridge | 171:3a7713b1edbc | 653 | /*! |
AnnaBridge | 171:3a7713b1edbc | 654 | * @brief SDIF enable DMA interrupt |
AnnaBridge | 171:3a7713b1edbc | 655 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 656 | * @param interrupt mask to set |
AnnaBridge | 171:3a7713b1edbc | 657 | */ |
AnnaBridge | 171:3a7713b1edbc | 658 | static inline void SDIF_EnableDmaInterrupt(SDIF_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 659 | { |
AnnaBridge | 171:3a7713b1edbc | 660 | base->IDINTEN |= mask; |
AnnaBridge | 171:3a7713b1edbc | 661 | } |
AnnaBridge | 171:3a7713b1edbc | 662 | |
AnnaBridge | 171:3a7713b1edbc | 663 | /*! |
AnnaBridge | 171:3a7713b1edbc | 664 | * @brief SDIF disable DMA interrupt |
AnnaBridge | 171:3a7713b1edbc | 665 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 666 | * @param interrupt mask to clear |
AnnaBridge | 171:3a7713b1edbc | 667 | */ |
AnnaBridge | 171:3a7713b1edbc | 668 | static inline void SDIF_DisableDmaInterrupt(SDIF_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 669 | { |
AnnaBridge | 171:3a7713b1edbc | 670 | base->IDINTEN &= ~mask; |
AnnaBridge | 171:3a7713b1edbc | 671 | } |
AnnaBridge | 171:3a7713b1edbc | 672 | |
AnnaBridge | 171:3a7713b1edbc | 673 | /*! |
AnnaBridge | 171:3a7713b1edbc | 674 | * @brief SDIF get internal DMA status |
AnnaBridge | 171:3a7713b1edbc | 675 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 676 | * @return the internal DMA status register |
AnnaBridge | 171:3a7713b1edbc | 677 | */ |
AnnaBridge | 171:3a7713b1edbc | 678 | static inline uint32_t SDIF_GetInternalDMAStatus(SDIF_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 679 | { |
AnnaBridge | 171:3a7713b1edbc | 680 | return base->IDSTS; |
AnnaBridge | 171:3a7713b1edbc | 681 | } |
AnnaBridge | 171:3a7713b1edbc | 682 | |
AnnaBridge | 171:3a7713b1edbc | 683 | /*! |
AnnaBridge | 171:3a7713b1edbc | 684 | * @brief SDIF clear internal DMA status |
AnnaBridge | 171:3a7713b1edbc | 685 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 686 | * @param status mask to clear |
AnnaBridge | 171:3a7713b1edbc | 687 | */ |
AnnaBridge | 171:3a7713b1edbc | 688 | static inline void SDIF_ClearInternalDMAStatus(SDIF_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 689 | { |
AnnaBridge | 171:3a7713b1edbc | 690 | base->IDSTS &= mask; |
AnnaBridge | 171:3a7713b1edbc | 691 | } |
AnnaBridge | 171:3a7713b1edbc | 692 | |
AnnaBridge | 171:3a7713b1edbc | 693 | /*! |
AnnaBridge | 171:3a7713b1edbc | 694 | * @brief SDIF internal DMA config function |
AnnaBridge | 171:3a7713b1edbc | 695 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 696 | * @param internal DMA configuration collection |
AnnaBridge | 171:3a7713b1edbc | 697 | * @param data buffer pointer |
AnnaBridge | 171:3a7713b1edbc | 698 | * @param data buffer size |
AnnaBridge | 171:3a7713b1edbc | 699 | */ |
AnnaBridge | 171:3a7713b1edbc | 700 | status_t SDIF_InternalDMAConfig(SDIF_Type *base, sdif_dma_config_t *config, const uint32_t *data, uint32_t dataSize); |
AnnaBridge | 171:3a7713b1edbc | 701 | |
AnnaBridge | 171:3a7713b1edbc | 702 | /*! |
AnnaBridge | 171:3a7713b1edbc | 703 | * @brief SDIF send read wait to SDIF card function |
AnnaBridge | 171:3a7713b1edbc | 704 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 705 | */ |
AnnaBridge | 171:3a7713b1edbc | 706 | static inline void SDIF_SendReadWait(SDIF_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 707 | { |
AnnaBridge | 171:3a7713b1edbc | 708 | base->CTRL |= SDIF_CTRL_READ_WAIT_MASK; |
AnnaBridge | 171:3a7713b1edbc | 709 | } |
AnnaBridge | 171:3a7713b1edbc | 710 | |
AnnaBridge | 171:3a7713b1edbc | 711 | /*! |
AnnaBridge | 171:3a7713b1edbc | 712 | * @brief SDIF abort the read data when SDIF card is in suspend state |
AnnaBridge | 171:3a7713b1edbc | 713 | * Once assert this bit,data state machine will be reset which is waiting for the |
AnnaBridge | 171:3a7713b1edbc | 714 | * next blocking data,used in SDIO card suspend sequence,should call after suspend |
AnnaBridge | 171:3a7713b1edbc | 715 | * cmd send |
AnnaBridge | 171:3a7713b1edbc | 716 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 717 | * @param timeout value to wait this bit self clear which indicate the data machine |
AnnaBridge | 171:3a7713b1edbc | 718 | * reset to idle |
AnnaBridge | 171:3a7713b1edbc | 719 | */ |
AnnaBridge | 171:3a7713b1edbc | 720 | bool SDIF_AbortReadData(SDIF_Type *base, uint32_t timeout); |
AnnaBridge | 171:3a7713b1edbc | 721 | |
AnnaBridge | 171:3a7713b1edbc | 722 | /*! |
AnnaBridge | 171:3a7713b1edbc | 723 | * @brief SDIF enable/disable CE-ATA card interrupt |
AnnaBridge | 171:3a7713b1edbc | 724 | * this bit should set together with the card register |
AnnaBridge | 171:3a7713b1edbc | 725 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 726 | * @param enable/disable flag |
AnnaBridge | 171:3a7713b1edbc | 727 | */ |
AnnaBridge | 171:3a7713b1edbc | 728 | static inline void SDIF_EnableCEATAInterrupt(SDIF_Type *base, bool enable) |
AnnaBridge | 171:3a7713b1edbc | 729 | { |
AnnaBridge | 171:3a7713b1edbc | 730 | if (enable) |
AnnaBridge | 171:3a7713b1edbc | 731 | { |
AnnaBridge | 171:3a7713b1edbc | 732 | base->CTRL |= SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; |
AnnaBridge | 171:3a7713b1edbc | 733 | } |
AnnaBridge | 171:3a7713b1edbc | 734 | else |
AnnaBridge | 171:3a7713b1edbc | 735 | { |
AnnaBridge | 171:3a7713b1edbc | 736 | base->CTRL &= ~SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK; |
AnnaBridge | 171:3a7713b1edbc | 737 | } |
AnnaBridge | 171:3a7713b1edbc | 738 | } |
AnnaBridge | 171:3a7713b1edbc | 739 | |
AnnaBridge | 171:3a7713b1edbc | 740 | /*! |
AnnaBridge | 171:3a7713b1edbc | 741 | * @brief SDIF transfer function data/cmd in a non-blocking way |
AnnaBridge | 171:3a7713b1edbc | 742 | * this API should be use in interrupt mode, when use this API user |
AnnaBridge | 171:3a7713b1edbc | 743 | * must call SDIF_TransferCreateHandle first, all status check through |
AnnaBridge | 171:3a7713b1edbc | 744 | * interrupt |
AnnaBridge | 171:3a7713b1edbc | 745 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 746 | * @param sdif handle |
AnnaBridge | 171:3a7713b1edbc | 747 | * @param DMA config structure |
AnnaBridge | 171:3a7713b1edbc | 748 | * This parameter can be config as: |
AnnaBridge | 171:3a7713b1edbc | 749 | * 1. NULL |
AnnaBridge | 171:3a7713b1edbc | 750 | In this condition, polling transfer mode is selected |
AnnaBridge | 171:3a7713b1edbc | 751 | 2. avaliable DMA config |
AnnaBridge | 171:3a7713b1edbc | 752 | In this condition, DMA transfer mode is selected |
AnnaBridge | 171:3a7713b1edbc | 753 | * @param sdif transfer configuration collection |
AnnaBridge | 171:3a7713b1edbc | 754 | */ |
AnnaBridge | 171:3a7713b1edbc | 755 | status_t SDIF_TransferNonBlocking(SDIF_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 756 | sdif_handle_t *handle, |
AnnaBridge | 171:3a7713b1edbc | 757 | sdif_dma_config_t *dmaConfig, |
AnnaBridge | 171:3a7713b1edbc | 758 | sdif_transfer_t *transfer); |
AnnaBridge | 171:3a7713b1edbc | 759 | |
AnnaBridge | 171:3a7713b1edbc | 760 | /*! |
AnnaBridge | 171:3a7713b1edbc | 761 | * @brief SDIF transfer function data/cmd in a blocking way |
AnnaBridge | 171:3a7713b1edbc | 762 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 763 | * @param DMA config structure |
AnnaBridge | 171:3a7713b1edbc | 764 | * 1. NULL |
AnnaBridge | 171:3a7713b1edbc | 765 | * In this condition, polling transfer mode is selected |
AnnaBridge | 171:3a7713b1edbc | 766 | * 2. avaliable DMA config |
AnnaBridge | 171:3a7713b1edbc | 767 | * In this condition, DMA transfer mode is selected |
AnnaBridge | 171:3a7713b1edbc | 768 | * @param sdif transfer configuration collection |
AnnaBridge | 171:3a7713b1edbc | 769 | */ |
AnnaBridge | 171:3a7713b1edbc | 770 | status_t SDIF_TransferBlocking(SDIF_Type *base, sdif_dma_config_t *dmaConfig, sdif_transfer_t *transfer); |
AnnaBridge | 171:3a7713b1edbc | 771 | |
AnnaBridge | 171:3a7713b1edbc | 772 | /*! |
AnnaBridge | 171:3a7713b1edbc | 773 | * @brief SDIF release the DMA descriptor to DMA engine |
AnnaBridge | 171:3a7713b1edbc | 774 | * this function should be called when DMA descriptor unavailable status occurs |
AnnaBridge | 171:3a7713b1edbc | 775 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 776 | * @param sdif DMA config pointer |
AnnaBridge | 171:3a7713b1edbc | 777 | */ |
AnnaBridge | 171:3a7713b1edbc | 778 | status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig); |
AnnaBridge | 171:3a7713b1edbc | 779 | |
AnnaBridge | 171:3a7713b1edbc | 780 | /*! |
AnnaBridge | 171:3a7713b1edbc | 781 | * @brief SDIF return the controller capability |
AnnaBridge | 171:3a7713b1edbc | 782 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 783 | * @param sdif capability pointer |
AnnaBridge | 171:3a7713b1edbc | 784 | */ |
AnnaBridge | 171:3a7713b1edbc | 785 | void SDIF_GetCapability(SDIF_Type *base, sdif_capability_t *capability); |
AnnaBridge | 171:3a7713b1edbc | 786 | |
AnnaBridge | 171:3a7713b1edbc | 787 | /*! |
AnnaBridge | 171:3a7713b1edbc | 788 | * @brief SDIF return the controller status |
AnnaBridge | 171:3a7713b1edbc | 789 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 790 | */ |
AnnaBridge | 171:3a7713b1edbc | 791 | static inline uint32_t SDIF_GetControllerStatus(SDIF_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 792 | { |
AnnaBridge | 171:3a7713b1edbc | 793 | return base->STATUS; |
AnnaBridge | 171:3a7713b1edbc | 794 | } |
AnnaBridge | 171:3a7713b1edbc | 795 | |
AnnaBridge | 171:3a7713b1edbc | 796 | /*! |
AnnaBridge | 171:3a7713b1edbc | 797 | * @brief SDIF send command complete signal disable to CE-ATA card |
AnnaBridge | 171:3a7713b1edbc | 798 | * @param base SDIF peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 799 | * @param send auto stop flag |
AnnaBridge | 171:3a7713b1edbc | 800 | */ |
AnnaBridge | 171:3a7713b1edbc | 801 | static inline void SDIF_SendCCSD(SDIF_Type *base, bool withAutoStop) |
AnnaBridge | 171:3a7713b1edbc | 802 | { |
AnnaBridge | 171:3a7713b1edbc | 803 | if (withAutoStop) |
AnnaBridge | 171:3a7713b1edbc | 804 | { |
AnnaBridge | 171:3a7713b1edbc | 805 | base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK | SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK; |
AnnaBridge | 171:3a7713b1edbc | 806 | } |
AnnaBridge | 171:3a7713b1edbc | 807 | else |
AnnaBridge | 171:3a7713b1edbc | 808 | { |
AnnaBridge | 171:3a7713b1edbc | 809 | base->CTRL |= SDIF_CTRL_SEND_CCSD_MASK; |
AnnaBridge | 171:3a7713b1edbc | 810 | } |
AnnaBridge | 171:3a7713b1edbc | 811 | } |
AnnaBridge | 171:3a7713b1edbc | 812 | |
AnnaBridge | 171:3a7713b1edbc | 813 | /*! |
AnnaBridge | 171:3a7713b1edbc | 814 | * @brief SDIF config the clock delay |
AnnaBridge | 171:3a7713b1edbc | 815 | * This function is used to config the cclk_in delay to |
AnnaBridge | 171:3a7713b1edbc | 816 | * sample and drvive the data ,should meet the min setup |
AnnaBridge | 171:3a7713b1edbc | 817 | * time and hold time, and user need to config this paramter |
AnnaBridge | 171:3a7713b1edbc | 818 | * according to your board setting |
AnnaBridge | 171:3a7713b1edbc | 819 | * @param target freq work mode |
AnnaBridge | 171:3a7713b1edbc | 820 | * @param clock divider which is used to decide if use pharse shift for delay |
AnnaBridge | 171:3a7713b1edbc | 821 | */ |
AnnaBridge | 171:3a7713b1edbc | 822 | void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider); |
AnnaBridge | 171:3a7713b1edbc | 823 | |
AnnaBridge | 171:3a7713b1edbc | 824 | /* @} */ |
AnnaBridge | 171:3a7713b1edbc | 825 | |
AnnaBridge | 171:3a7713b1edbc | 826 | #if defined(__cplusplus) |
AnnaBridge | 171:3a7713b1edbc | 827 | } |
AnnaBridge | 171:3a7713b1edbc | 828 | #endif |
AnnaBridge | 171:3a7713b1edbc | 829 | /*! @} */ |
AnnaBridge | 171:3a7713b1edbc | 830 | |
AnnaBridge | 171:3a7713b1edbc | 831 | #endif /* _FSL_sdif_H_*/ |