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TARGET_LPC54114/TOOLCHAIN_GCC_ARM/fsl_clock.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 148:fd96258d940d 1 /*
Kojto 148:fd96258d940d 2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
Kojto 148:fd96258d940d 3 * All rights reserved.
Kojto 148:fd96258d940d 4 *
Kojto 148:fd96258d940d 5 * Redistribution and use in source and binary forms, with or without modification,
Kojto 148:fd96258d940d 6 * are permitted provided that the following conditions are met:
Kojto 148:fd96258d940d 7 *
Kojto 148:fd96258d940d 8 * o Redistributions of source code must retain the above copyright notice, this list
Kojto 148:fd96258d940d 9 * of conditions and the following disclaimer.
Kojto 148:fd96258d940d 10 *
Kojto 148:fd96258d940d 11 * o Redistributions in binary form must reproduce the above copyright notice, this
Kojto 148:fd96258d940d 12 * list of conditions and the following disclaimer in the documentation and/or
Kojto 148:fd96258d940d 13 * other materials provided with the distribution.
Kojto 148:fd96258d940d 14 *
Kojto 148:fd96258d940d 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
Kojto 148:fd96258d940d 16 * contributors may be used to endorse or promote products derived from this
Kojto 148:fd96258d940d 17 * software without specific prior written permission.
Kojto 148:fd96258d940d 18 *
Kojto 148:fd96258d940d 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 148:fd96258d940d 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 148:fd96258d940d 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 148:fd96258d940d 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 148:fd96258d940d 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 148:fd96258d940d 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 148:fd96258d940d 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 148:fd96258d940d 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 148:fd96258d940d 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 148:fd96258d940d 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 148:fd96258d940d 29 */
Kojto 148:fd96258d940d 30
Kojto 148:fd96258d940d 31 #ifndef _FSL_CLOCK_H_
Kojto 148:fd96258d940d 32 #define _FSL_CLOCK_H_
Kojto 148:fd96258d940d 33
Kojto 148:fd96258d940d 34 #include "fsl_device_registers.h"
Kojto 148:fd96258d940d 35 #include <stdint.h>
Kojto 148:fd96258d940d 36 #include <stdbool.h>
Kojto 148:fd96258d940d 37 #include <assert.h>
Kojto 148:fd96258d940d 38
Kojto 148:fd96258d940d 39 /*! @addtogroup clock */
Kojto 148:fd96258d940d 40 /*! @{ */
Kojto 148:fd96258d940d 41
Kojto 148:fd96258d940d 42 /*! @file */
Kojto 148:fd96258d940d 43
Kojto 148:fd96258d940d 44 /*******************************************************************************
Kojto 148:fd96258d940d 45 * Definitions
Kojto 148:fd96258d940d 46 *****************************************************************************/
Kojto 148:fd96258d940d 47 /*! @brief Clock ip name array for FLEXCOMM. */
Kojto 148:fd96258d940d 48 #define FLEXCOMM_CLOCKS \
Kojto 148:fd96258d940d 49 { \
Kojto 148:fd96258d940d 50 kCLOCK_FlexComm0, kCLOCK_FlexComm1, kCLOCK_FlexComm2, kCLOCK_FlexComm3, \
Kojto 148:fd96258d940d 51 kCLOCK_FlexComm4, kCLOCK_FlexComm5, kCLOCK_FlexComm6, kCLOCK_FlexComm7 \
Kojto 148:fd96258d940d 52 }
Kojto 148:fd96258d940d 53 /*! @brief Clock ip name array for LPUART. */
Kojto 148:fd96258d940d 54 #define LPUART_CLOCKS \
Kojto 148:fd96258d940d 55 { \
Kojto 148:fd96258d940d 56 kCLOCK_MinUart0, kCLOCK_MinUart1, kCLOCK_MinUart2, kCLOCK_MinUart3, kCLOCK_MinUart4, kCLOCK_MinUart5, \
Kojto 148:fd96258d940d 57 kCLOCK_MinUart6, kCLOCK_MinUart7 \
Kojto 148:fd96258d940d 58 }
Kojto 148:fd96258d940d 59
Kojto 148:fd96258d940d 60 /*! @brief Clock ip name array for BI2C. */
Kojto 148:fd96258d940d 61 #define BI2C_CLOCKS \
Kojto 148:fd96258d940d 62 { \
Kojto 148:fd96258d940d 63 kCLOCK_BI2c0, kCLOCK_BI2c1, kCLOCK_BI2c2, kCLOCK_BI2c3, kCLOCK_BI2c4, kCLOCK_BI2c5, kCLOCK_BI2c6, kCLOCK_BI2c7 \
Kojto 148:fd96258d940d 64 }
Kojto 148:fd96258d940d 65 /*! @brief Clock ip name array for LSPI. */
Kojto 148:fd96258d940d 66 #define LPSI_CLOCKS \
Kojto 148:fd96258d940d 67 { \
Kojto 148:fd96258d940d 68 kCLOCK_LSpi0, kCLOCK_LSpi1, kCLOCK_LSpi2, kCLOCK_LSpi3, kCLOCK_LSpi4, kCLOCK_LSpi5, kCLOCK_LSpi6, kCLOCK_LSpi7 \
Kojto 148:fd96258d940d 69 }
Kojto 148:fd96258d940d 70 /*! @brief Clock ip name array for FLEXI2S. */
Kojto 148:fd96258d940d 71 #define FLEXI2S_CLOCKS \
Kojto 148:fd96258d940d 72 { \
Kojto 148:fd96258d940d 73 kCLOCK_FlexI2s0, kCLOCK_FlexI2s1, kCLOCK_FlexI2s2, kCLOCK_FlexI2s3, kCLOCK_FlexI2s4, kCLOCK_FlexI2s5, \
Kojto 148:fd96258d940d 74 kCLOCK_FlexI2s6, kCLOCK_FlexI2s7 \
Kojto 148:fd96258d940d 75 }
Kojto 148:fd96258d940d 76 /*! @brief Clock ip name array for UTICK. */
Kojto 148:fd96258d940d 77 #define UTICK_CLOCKS \
Kojto 148:fd96258d940d 78 { \
Kojto 148:fd96258d940d 79 kCLOCK_Utick \
Kojto 148:fd96258d940d 80 }
Kojto 148:fd96258d940d 81 /*! @brief Clock ip name array for DMIC. */
Kojto 148:fd96258d940d 82 #define DMIC_CLOCKS \
Kojto 148:fd96258d940d 83 { \
Kojto 148:fd96258d940d 84 kCLOCK_DMic \
Kojto 148:fd96258d940d 85 }
Kojto 148:fd96258d940d 86 /*! @brief Clock ip name array for DMA. */
Kojto 148:fd96258d940d 87 #define DMA_CLOCKS \
Kojto 148:fd96258d940d 88 { \
Kojto 148:fd96258d940d 89 kCLOCK_Dma \
Kojto 148:fd96258d940d 90 }
Kojto 148:fd96258d940d 91 /*! @brief Clock ip name array for CT32B. */
Kojto 148:fd96258d940d 92 #define CTIMER_CLOCKS \
Kojto 148:fd96258d940d 93 { \
Kojto 148:fd96258d940d 94 kCLOCK_Ct32b0, kCLOCK_Ct32b1, kCLOCK_Ct32b2, kCLOCK_Ct32b3, kCLOCK_Ct32b4 \
Kojto 148:fd96258d940d 95 }
Kojto 148:fd96258d940d 96
Kojto 148:fd96258d940d 97 /*! @brief Clock ip name array for GPIO. */
Kojto 148:fd96258d940d 98 #define GPIO_CLOCKS \
Kojto 148:fd96258d940d 99 { \
Kojto 148:fd96258d940d 100 kCLOCK_Gpio0, kCLOCK_Gpio1 \
Kojto 148:fd96258d940d 101 }
Kojto 148:fd96258d940d 102 /*! @brief Clock ip name array for ADC. */
Kojto 148:fd96258d940d 103 #define ADC_CLOCKS \
Kojto 148:fd96258d940d 104 { \
Kojto 148:fd96258d940d 105 kCLOCK_Adc0 \
Kojto 148:fd96258d940d 106 }
Kojto 148:fd96258d940d 107 /*! @brief Clock ip name array for MRT. */
Kojto 148:fd96258d940d 108 #define MRT_CLOCKS \
Kojto 148:fd96258d940d 109 { \
Kojto 148:fd96258d940d 110 kCLOCK_Mrt \
Kojto 148:fd96258d940d 111 }
Kojto 148:fd96258d940d 112 /*! @brief Clock ip name array for MRT. */
Kojto 148:fd96258d940d 113 #define SCT_CLOCKS \
Kojto 148:fd96258d940d 114 { \
Kojto 148:fd96258d940d 115 kCLOCK_Sct0 \
Kojto 148:fd96258d940d 116 }
Kojto 148:fd96258d940d 117 /*! @brief Clock ip name array for RTC. */
Kojto 148:fd96258d940d 118 #define RTC_CLOCKS \
Kojto 148:fd96258d940d 119 { \
Kojto 148:fd96258d940d 120 kCLOCK_Rtc \
Kojto 148:fd96258d940d 121 }
Kojto 148:fd96258d940d 122 /*! @brief Clock ip name array for WWDT. */
Kojto 148:fd96258d940d 123 #define WWDT_CLOCKS \
Kojto 148:fd96258d940d 124 { \
Kojto 148:fd96258d940d 125 kCLOCK_Wwdt \
Kojto 148:fd96258d940d 126 }
Kojto 148:fd96258d940d 127 /*! @brief Clock ip name array for CRC. */
Kojto 148:fd96258d940d 128 #define CRC_CLOCKS \
Kojto 148:fd96258d940d 129 { \
Kojto 148:fd96258d940d 130 kCLOCK_Crc \
Kojto 148:fd96258d940d 131 }
Kojto 148:fd96258d940d 132 /*! @brief Clock ip name array for USBD. */
Kojto 148:fd96258d940d 133 #define USBD_CLOCKS \
Kojto 148:fd96258d940d 134 { \
Kojto 148:fd96258d940d 135 kCLOCK_Usbd0 \
Kojto 148:fd96258d940d 136 }
Kojto 148:fd96258d940d 137
Kojto 148:fd96258d940d 138 /*! @brief Clock ip name array for GINT. GINT0 & GINT1 share same slot */
Kojto 148:fd96258d940d 139 #define GINT_CLOCKS \
Kojto 148:fd96258d940d 140 { \
Kojto 148:fd96258d940d 141 kCLOCK_Gint, kCLOCK_Gint \
Kojto 148:fd96258d940d 142 }
Kojto 148:fd96258d940d 143
Kojto 148:fd96258d940d 144 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
Kojto 148:fd96258d940d 145 /*------------------------------------------------------------------------------
Kojto 148:fd96258d940d 146 clock_ip_name_t definition:
Kojto 148:fd96258d940d 147 ------------------------------------------------------------------------------*/
Kojto 148:fd96258d940d 148
Kojto 148:fd96258d940d 149 #define CLK_GATE_REG_OFFSET_SHIFT 8U
Kojto 148:fd96258d940d 150 #define CLK_GATE_REG_OFFSET_MASK 0xFFFFFF00U
Kojto 148:fd96258d940d 151 #define CLK_GATE_BIT_SHIFT_SHIFT 0U
Kojto 148:fd96258d940d 152 #define CLK_GATE_BIT_SHIFT_MASK 0x000000FFU
Kojto 148:fd96258d940d 153
Kojto 148:fd96258d940d 154 #define CLK_GATE_DEFINE(reg_offset, bit_shift) \
Kojto 148:fd96258d940d 155 ((((reg_offset) << CLK_GATE_REG_OFFSET_SHIFT) & CLK_GATE_REG_OFFSET_MASK) | \
Kojto 148:fd96258d940d 156 (((bit_shift) << CLK_GATE_BIT_SHIFT_SHIFT) & CLK_GATE_BIT_SHIFT_MASK))
Kojto 148:fd96258d940d 157
Kojto 148:fd96258d940d 158 #define CLK_GATE_ABSTRACT_REG_OFFSET(x) (((uint32_t)(x)&CLK_GATE_REG_OFFSET_MASK) >> CLK_GATE_REG_OFFSET_SHIFT)
Kojto 148:fd96258d940d 159 #define CLK_GATE_ABSTRACT_BITS_SHIFT(x) (((uint32_t)(x)&CLK_GATE_BIT_SHIFT_MASK) >> CLK_GATE_BIT_SHIFT_SHIFT)
Kojto 148:fd96258d940d 160
Kojto 148:fd96258d940d 161 #define AHB_CLK_CTRL0 0
Kojto 148:fd96258d940d 162 #define AHB_CLK_CTRL1 1
Kojto 148:fd96258d940d 163 #define ASYNC_CLK_CTRL0 2
Kojto 148:fd96258d940d 164
Kojto 148:fd96258d940d 165 /*! @brief Clock gate name used for CLOCK_EnableClock/CLOCK_DisableClock. */
Kojto 148:fd96258d940d 166 typedef enum _clock_ip_name
Kojto 148:fd96258d940d 167 {
Kojto 148:fd96258d940d 168 kCLOCK_IpInvalid = 0U,
Kojto 148:fd96258d940d 169 kCLOCK_Rom = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 1),
Kojto 148:fd96258d940d 170 kCLOCK_Sram1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 3),
Kojto 148:fd96258d940d 171 kCLOCK_Sram2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 4),
Kojto 148:fd96258d940d 172 kCLOCK_Regfile = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 6),
Kojto 148:fd96258d940d 173 kCLOCK_Flash = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 7),
Kojto 148:fd96258d940d 174 kCLOCK_Fmc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 8),
Kojto 148:fd96258d940d 175 kCLOCK_InputMux = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 11),
Kojto 148:fd96258d940d 176 kCLOCK_Iocon = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 13),
Kojto 148:fd96258d940d 177 kCLOCK_Gpio0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 14),
Kojto 148:fd96258d940d 178 kCLOCK_Gpio1 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 15),
Kojto 148:fd96258d940d 179 kCLOCK_Gpio2 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 16),
Kojto 148:fd96258d940d 180 kCLOCK_Gpio3 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 17),
Kojto 148:fd96258d940d 181 kCLOCK_Pint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 18),
Kojto 148:fd96258d940d 182 kCLOCK_Gint = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 19), /* GPIO_GLOBALINT0 and GPIO_GLOBALINT1 share the same slot */
Kojto 148:fd96258d940d 183 kCLOCK_Dma = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 20),
Kojto 148:fd96258d940d 184 kCLOCK_Crc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 21),
Kojto 148:fd96258d940d 185 kCLOCK_Wwdt = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 22),
Kojto 148:fd96258d940d 186 kCLOCK_Rtc = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 23),
Kojto 148:fd96258d940d 187 kCLOCK_Mailbox = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 26),
Kojto 148:fd96258d940d 188 kCLOCK_Adc0 = CLK_GATE_DEFINE(AHB_CLK_CTRL0, 27),
Kojto 148:fd96258d940d 189 kCLOCK_Mrt = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 0),
Kojto 148:fd96258d940d 190 kCLOCK_Sct0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 2),
Kojto 148:fd96258d940d 191 kCLOCK_SctIpu0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 6),
Kojto 148:fd96258d940d 192 kCLOCK_Utick = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 10),
Kojto 148:fd96258d940d 193 kCLOCK_FlexComm0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
Kojto 148:fd96258d940d 194 kCLOCK_FlexComm1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
Kojto 148:fd96258d940d 195 kCLOCK_FlexComm2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
Kojto 148:fd96258d940d 196 kCLOCK_FlexComm3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
Kojto 148:fd96258d940d 197 kCLOCK_FlexComm4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
Kojto 148:fd96258d940d 198 kCLOCK_FlexComm5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
Kojto 148:fd96258d940d 199 kCLOCK_FlexComm6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
Kojto 148:fd96258d940d 200 kCLOCK_FlexComm7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
Kojto 148:fd96258d940d 201 kCLOCK_MinUart0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
Kojto 148:fd96258d940d 202 kCLOCK_MinUart1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
Kojto 148:fd96258d940d 203 kCLOCK_MinUart2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
Kojto 148:fd96258d940d 204 kCLOCK_MinUart3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
Kojto 148:fd96258d940d 205 kCLOCK_MinUart4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
Kojto 148:fd96258d940d 206 kCLOCK_MinUart5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
Kojto 148:fd96258d940d 207 kCLOCK_MinUart6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
Kojto 148:fd96258d940d 208 kCLOCK_MinUart7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
Kojto 148:fd96258d940d 209 kCLOCK_LSpi0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
Kojto 148:fd96258d940d 210 kCLOCK_LSpi1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
Kojto 148:fd96258d940d 211 kCLOCK_LSpi2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
Kojto 148:fd96258d940d 212 kCLOCK_LSpi3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
Kojto 148:fd96258d940d 213 kCLOCK_LSpi4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
Kojto 148:fd96258d940d 214 kCLOCK_LSpi5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
Kojto 148:fd96258d940d 215 kCLOCK_LSpi6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
Kojto 148:fd96258d940d 216 kCLOCK_LSpi7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
Kojto 148:fd96258d940d 217 kCLOCK_BI2c0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
Kojto 148:fd96258d940d 218 kCLOCK_BI2c1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
Kojto 148:fd96258d940d 219 kCLOCK_BI2c2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
Kojto 148:fd96258d940d 220 kCLOCK_BI2c3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
Kojto 148:fd96258d940d 221 kCLOCK_BI2c4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
Kojto 148:fd96258d940d 222 kCLOCK_BI2c5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
Kojto 148:fd96258d940d 223 kCLOCK_BI2c6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
Kojto 148:fd96258d940d 224 kCLOCK_BI2c7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
Kojto 148:fd96258d940d 225 kCLOCK_FlexI2s0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 11),
Kojto 148:fd96258d940d 226 kCLOCK_FlexI2s1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 12),
Kojto 148:fd96258d940d 227 kCLOCK_FlexI2s2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 13),
Kojto 148:fd96258d940d 228 kCLOCK_FlexI2s3 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 14),
Kojto 148:fd96258d940d 229 kCLOCK_FlexI2s4 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 15),
Kojto 148:fd96258d940d 230 kCLOCK_FlexI2s5 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 16),
Kojto 148:fd96258d940d 231 kCLOCK_FlexI2s6 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 17),
Kojto 148:fd96258d940d 232 kCLOCK_FlexI2s7 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 18),
Kojto 148:fd96258d940d 233 kCLOCK_DMic = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 19),
Kojto 148:fd96258d940d 234 kCLOCK_Ct32b2 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 22),
Kojto 148:fd96258d940d 235 kCLOCK_Usbd0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 25),
Kojto 148:fd96258d940d 236 kCLOCK_Ct32b0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 26),
Kojto 148:fd96258d940d 237 kCLOCK_Ct32b1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 27),
Kojto 148:fd96258d940d 238 kCLOCK_Pvtvf0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
Kojto 148:fd96258d940d 239 kCLOCK_Pvtvf1 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 28),
Kojto 148:fd96258d940d 240 kCLOCK_BodyBias0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 29),
Kojto 148:fd96258d940d 241 kCLOCK_EzhArchB0 = CLK_GATE_DEFINE(AHB_CLK_CTRL1, 31),
Kojto 148:fd96258d940d 242
Kojto 148:fd96258d940d 243 kCLOCK_Ct32b3 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 13),
Kojto 148:fd96258d940d 244 kCLOCK_Ct32b4 = CLK_GATE_DEFINE(ASYNC_CLK_CTRL0, 14)
Kojto 148:fd96258d940d 245 } clock_ip_name_t;
Kojto 148:fd96258d940d 246
Kojto 148:fd96258d940d 247 /*! @brief Clock name used to get clock frequency. */
Kojto 148:fd96258d940d 248 typedef enum _clock_name
Kojto 148:fd96258d940d 249 {
Kojto 148:fd96258d940d 250 kCLOCK_CoreSysClk, /*!< Core/system clock (aka MAIN_CLK) */
Kojto 148:fd96258d940d 251 kCLOCK_BusClk, /*!< Bus clock (AHB clock) */
Kojto 148:fd96258d940d 252 kCLOCK_FroHf, /*!< FRO48/96 */
Kojto 148:fd96258d940d 253 kCLOCK_Fro12M, /*!< FRO12M */
Kojto 148:fd96258d940d 254 kCLOCK_ExtClk, /*!< External Clock */
Kojto 148:fd96258d940d 255 kCLOCK_PllOut, /*!< PLL Output */
Kojto 148:fd96258d940d 256 kCLOCK_UsbClk, /*!< USB input */
Kojto 148:fd96258d940d 257 kClock_WdtOsc, /*!< Watchdog Oscillator */
Kojto 148:fd96258d940d 258 kCLOCK_Frg, /*!< Frg Clock */
Kojto 148:fd96258d940d 259 kCLOCK_Dmic, /*!< Digital Mic clock */
Kojto 148:fd96258d940d 260 kCLOCK_AsyncApbClk, /*!< Async APB clock */
Kojto 148:fd96258d940d 261 kCLOCK_FlexI2S, /*!< FlexI2S clock */
Kojto 148:fd96258d940d 262 kCLOCK_Flexcomm0, /*!< Flexcomm0Clock */
Kojto 148:fd96258d940d 263 kCLOCK_Flexcomm1, /*!< Flexcomm1Clock */
Kojto 148:fd96258d940d 264 kCLOCK_Flexcomm2, /*!< Flexcomm2Clock */
Kojto 148:fd96258d940d 265 kCLOCK_Flexcomm3, /*!< Flexcomm3Clock */
Kojto 148:fd96258d940d 266 kCLOCK_Flexcomm4, /*!< Flexcomm4Clock */
Kojto 148:fd96258d940d 267 kCLOCK_Flexcomm5, /*!< Flexcomm5Clock */
Kojto 148:fd96258d940d 268 kCLOCK_Flexcomm6, /*!< Flexcomm6Clock */
Kojto 148:fd96258d940d 269 kCLOCK_Flexcomm7, /*!< Flexcomm7Clock */
Kojto 148:fd96258d940d 270 } clock_name_t;
Kojto 148:fd96258d940d 271
Kojto 148:fd96258d940d 272 /**
Kojto 148:fd96258d940d 273 * Clock source selections for the asynchronous APB clock
Kojto 148:fd96258d940d 274 */
Kojto 148:fd96258d940d 275 typedef enum _async_clock_src
Kojto 148:fd96258d940d 276 {
Kojto 148:fd96258d940d 277 kCLOCK_AsyncMainClk = 0, /*!< Main System clock */
Kojto 148:fd96258d940d 278 kCLOCK_AsyncFro12Mhz, /*!< 12MHz FRO */
Kojto 148:fd96258d940d 279 } async_clock_src_t;
Kojto 148:fd96258d940d 280
Kojto 148:fd96258d940d 281 /*! @brief Clock Mux Switches
Kojto 148:fd96258d940d 282 * The encoding is as follows each connection identified is 64bits wide
Kojto 148:fd96258d940d 283 * starting from LSB upwards
Kojto 148:fd96258d940d 284 *
Kojto 148:fd96258d940d 285 * [4 bits for choice, where 1 is A, 2 is B, 3 is C and 4 is D, 0 means end of descriptor] [8 bits mux ID]*
Kojto 148:fd96258d940d 286 *
Kojto 148:fd96258d940d 287 */
Kojto 148:fd96258d940d 288
Kojto 148:fd96258d940d 289 #define MUX_A(m, choice) (((m) << 0) | ((choice + 1) << 8))
Kojto 148:fd96258d940d 290 #define MUX_B(m, choice) (((m) << 12) | ((choice + 1) << 20))
Kojto 148:fd96258d940d 291 #define MUX_C(m, choice) (((m) << 24) | ((choice + 1) << 32))
Kojto 148:fd96258d940d 292 #define MUX_D(m, choice) (((m) << 36) | ((choice + 1) << 44))
Kojto 148:fd96258d940d 293 #define MUX_E(m, choice) (((m) << 48) | ((choice + 1) << 56))
Kojto 148:fd96258d940d 294
Kojto 148:fd96258d940d 295 #define CM_MAINCLKSELA 0
Kojto 148:fd96258d940d 296 #define CM_MAINCLKSELB 1
Kojto 148:fd96258d940d 297 #define CM_CLKOUTCLKSELA 2
Kojto 148:fd96258d940d 298 #define CM_CLKOUTCLKSELB 3
Kojto 148:fd96258d940d 299 #define CM_SYSPLLCLKSEL 4
Kojto 148:fd96258d940d 300 #define CM_USBPLLCLKSEL 5
Kojto 148:fd96258d940d 301 #define CM_AUDPLLCLKSEL 6
Kojto 148:fd96258d940d 302 #define CM_SCTPLLCLKSEL 7
Kojto 148:fd96258d940d 303 #define CM_SPIFICLKSEL 8
Kojto 148:fd96258d940d 304 #define CM_ADCASYNCCLKSEL 9
Kojto 148:fd96258d940d 305 #define CM_USBCLKSEL 10
Kojto 148:fd96258d940d 306 #define CM_USB1CLKSEL 11
Kojto 148:fd96258d940d 307 #define CM_FXCOMCLKSEL0 12
Kojto 148:fd96258d940d 308 #define CM_FXCOMCLKSEL1 13
Kojto 148:fd96258d940d 309 #define CM_FXCOMCLKSEL2 14
Kojto 148:fd96258d940d 310 #define CM_FXCOMCLKSEL3 15
Kojto 148:fd96258d940d 311 #define CM_FXCOMCLKSEL4 16
Kojto 148:fd96258d940d 312 #define CM_FXCOMCLKSEL5 17
Kojto 148:fd96258d940d 313 #define CM_FXCOMCLKSEL6 18
Kojto 148:fd96258d940d 314 #define CM_FXCOMCLKSEL7 19
Kojto 148:fd96258d940d 315 #define CM_FXCOMCLKSEL8 20
Kojto 148:fd96258d940d 316 #define CM_FXCOMCLKSEL9 21
Kojto 148:fd96258d940d 317 #define CM_FXCOMCLKSEL10 22
Kojto 148:fd96258d940d 318 #define CM_FXCOMCLKSEL11 23
Kojto 148:fd96258d940d 319 #define CM_FXI2S0MCLKCLKSEL 24
Kojto 148:fd96258d940d 320 #define CM_FXI2S1MCLKCLKSEL 25
Kojto 148:fd96258d940d 321 #define CM_FRGCLKSEL 26
Kojto 148:fd96258d940d 322 #define CM_DMICCLKSEL 27
Kojto 148:fd96258d940d 323
Kojto 148:fd96258d940d 324 #define CM_ASYNCAPB 28
Kojto 148:fd96258d940d 325
Kojto 148:fd96258d940d 326 typedef enum _clock_attach_id
Kojto 148:fd96258d940d 327 {
Kojto 148:fd96258d940d 328
Kojto 148:fd96258d940d 329 kFRO12M_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 0) | MUX_B(CM_MAINCLKSELB, 0),
Kojto 148:fd96258d940d 330 kEXT_CLK_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 1) | MUX_B(CM_MAINCLKSELB, 0),
Kojto 148:fd96258d940d 331 kWDT_OSC_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 2) | MUX_B(CM_MAINCLKSELB, 0),
Kojto 148:fd96258d940d 332 kFRO_HF_to_MAIN_CLK = MUX_A(CM_MAINCLKSELA, 3) | MUX_B(CM_MAINCLKSELB, 0),
Kojto 148:fd96258d940d 333 kSYS_PLL_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 2),
Kojto 148:fd96258d940d 334 kOSC32K_to_MAIN_CLK = MUX_A(CM_MAINCLKSELB, 3),
Kojto 148:fd96258d940d 335
Kojto 148:fd96258d940d 336 kFRO12M_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 0),
Kojto 148:fd96258d940d 337 kEXT_CLK_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 1),
Kojto 148:fd96258d940d 338 kWDT_OSC_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 2),
Kojto 148:fd96258d940d 339 kOSC32K_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 3),
Kojto 148:fd96258d940d 340 kNONE_to_SYS_PLL = MUX_A(CM_SYSPLLCLKSEL, 7),
Kojto 148:fd96258d940d 341
Kojto 148:fd96258d940d 342 kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
Kojto 148:fd96258d940d 343 kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
Kojto 148:fd96258d940d 344
Kojto 148:fd96258d940d 345 kMAIN_CLK_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 0),
Kojto 148:fd96258d940d 346 kSYS_PLL_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 1),
Kojto 148:fd96258d940d 347 kFRO_HF_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 2),
Kojto 148:fd96258d940d 348 kNONE_to_ADC_CLK = MUX_A(CM_ADCASYNCCLKSEL, 7),
Kojto 148:fd96258d940d 349
Kojto 148:fd96258d940d 350 kMAIN_CLK_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 0),
Kojto 148:fd96258d940d 351 kSYS_PLL_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 1),
Kojto 148:fd96258d940d 352 kFRO_HF_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 3),
Kojto 148:fd96258d940d 353 kNONE_to_SPIFI_CLK = MUX_A(CM_SPIFICLKSEL, 7),
Kojto 148:fd96258d940d 354
Kojto 148:fd96258d940d 355 kFRO12M_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 0),
Kojto 148:fd96258d940d 356 kFRO_HF_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 1),
Kojto 148:fd96258d940d 357 kSYS_PLL_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 2),
Kojto 148:fd96258d940d 358 kMCLK_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 3),
Kojto 148:fd96258d940d 359 kFRG_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 4),
Kojto 148:fd96258d940d 360 kNONE_to_FLEXCOMM0 = MUX_A(CM_FXCOMCLKSEL0, 7),
Kojto 148:fd96258d940d 361
Kojto 148:fd96258d940d 362 kFRO12M_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 0),
Kojto 148:fd96258d940d 363 kFRO_HF_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 1),
Kojto 148:fd96258d940d 364 kSYS_PLL_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 2),
Kojto 148:fd96258d940d 365 kMCLK_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 3),
Kojto 148:fd96258d940d 366 kFRG_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 4),
Kojto 148:fd96258d940d 367 kNONE_to_FLEXCOMM1 = MUX_A(CM_FXCOMCLKSEL1, 7),
Kojto 148:fd96258d940d 368
Kojto 148:fd96258d940d 369 kFRO12M_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 0),
Kojto 148:fd96258d940d 370 kFRO_HF_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 1),
Kojto 148:fd96258d940d 371 kSYS_PLL_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 2),
Kojto 148:fd96258d940d 372 kMCLK_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 3),
Kojto 148:fd96258d940d 373 kFRG_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 4),
Kojto 148:fd96258d940d 374 kNONE_to_FLEXCOMM2 = MUX_A(CM_FXCOMCLKSEL2, 7),
Kojto 148:fd96258d940d 375
Kojto 148:fd96258d940d 376 kFRO12M_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 0),
Kojto 148:fd96258d940d 377 kFRO_HF_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 1),
Kojto 148:fd96258d940d 378 kSYS_PLL_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 2),
Kojto 148:fd96258d940d 379 kMCLK_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 3),
Kojto 148:fd96258d940d 380 kFRG_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 4),
Kojto 148:fd96258d940d 381 kNONE_to_FLEXCOMM3 = MUX_A(CM_FXCOMCLKSEL3, 7),
Kojto 148:fd96258d940d 382
Kojto 148:fd96258d940d 383 kFRO12M_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 0),
Kojto 148:fd96258d940d 384 kFRO_HF_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 1),
Kojto 148:fd96258d940d 385 kSYS_PLL_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 2),
Kojto 148:fd96258d940d 386 kMCLK_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 3),
Kojto 148:fd96258d940d 387 kFRG_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 4),
Kojto 148:fd96258d940d 388 kNONE_to_FLEXCOMM4 = MUX_A(CM_FXCOMCLKSEL4, 7),
Kojto 148:fd96258d940d 389
Kojto 148:fd96258d940d 390 kFRO12M_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 0),
Kojto 148:fd96258d940d 391 kFRO_HF_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 1),
Kojto 148:fd96258d940d 392 kSYS_PLL_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 2),
Kojto 148:fd96258d940d 393 kMCLK_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 3),
Kojto 148:fd96258d940d 394 kFRG_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 4),
Kojto 148:fd96258d940d 395 kNONE_to_FLEXCOMM5 = MUX_A(CM_FXCOMCLKSEL5, 7),
Kojto 148:fd96258d940d 396
Kojto 148:fd96258d940d 397 kFRO12M_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 0),
Kojto 148:fd96258d940d 398 kFRO_HF_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 1),
Kojto 148:fd96258d940d 399 kSYS_PLL_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 2),
Kojto 148:fd96258d940d 400 kMCLK_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 3),
Kojto 148:fd96258d940d 401 kFRG_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 4),
Kojto 148:fd96258d940d 402 kNONE_to_FLEXCOMM6 = MUX_A(CM_FXCOMCLKSEL6, 7),
Kojto 148:fd96258d940d 403
Kojto 148:fd96258d940d 404 kFRO12M_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 0),
Kojto 148:fd96258d940d 405 kFRO_HF_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 1),
Kojto 148:fd96258d940d 406 kSYS_PLL_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 2),
Kojto 148:fd96258d940d 407 kMCLK_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 3),
Kojto 148:fd96258d940d 408 kFRG_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 4),
Kojto 148:fd96258d940d 409 kNONE_to_FLEXCOMM7 = MUX_A(CM_FXCOMCLKSEL7, 7),
Kojto 148:fd96258d940d 410
Kojto 148:fd96258d940d 411 kMAIN_CLK_to_FRG = MUX_A(CM_FRGCLKSEL, 0),
Kojto 148:fd96258d940d 412 kSYS_PLL_to_FRG = MUX_A(CM_FRGCLKSEL, 1),
Kojto 148:fd96258d940d 413 kFRO12M_to_FRG = MUX_A(CM_FRGCLKSEL, 2),
Kojto 148:fd96258d940d 414 kFRO_HF_to_FRG = MUX_A(CM_FRGCLKSEL, 3),
Kojto 148:fd96258d940d 415 kNONE_to_FRG = MUX_A(CM_FRGCLKSEL, 7),
Kojto 148:fd96258d940d 416
Kojto 148:fd96258d940d 417 kFRO_HF_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 0),
Kojto 148:fd96258d940d 418 kSYS_PLL_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 1),
Kojto 148:fd96258d940d 419 kNONE_to_MCLK = MUX_A(CM_FXI2S0MCLKCLKSEL, 7),
Kojto 148:fd96258d940d 420
Kojto 148:fd96258d940d 421 kFRO12M_to_DMIC = MUX_A(CM_DMICCLKSEL, 0),
Kojto 148:fd96258d940d 422 kFRO_HF_to_DMIC = MUX_A(CM_DMICCLKSEL, 1),
Kojto 148:fd96258d940d 423 kSYS_PLL_to_DMIC = MUX_A(CM_DMICCLKSEL, 2),
Kojto 148:fd96258d940d 424 kMCLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 3),
Kojto 148:fd96258d940d 425 kMAIN_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 4),
Kojto 148:fd96258d940d 426 kWDT_CLK_to_DMIC = MUX_A(CM_DMICCLKSEL, 5),
Kojto 148:fd96258d940d 427 kNONE_to_DMIC = MUX_A(CM_DMICCLKSEL, 7),
Kojto 148:fd96258d940d 428
Kojto 148:fd96258d940d 429 kFRO_HF_to_USB_CLK = MUX_A(CM_USBCLKSEL, 0),
Kojto 148:fd96258d940d 430 kSYS_PLL_to_USB_CLK = MUX_A(CM_USBCLKSEL, 1),
Kojto 148:fd96258d940d 431 kNONE_to_USB_CLK = MUX_A(CM_USBCLKSEL, 7),
Kojto 148:fd96258d940d 432
Kojto 148:fd96258d940d 433 kMAIN_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 0),
Kojto 148:fd96258d940d 434 kEXT_CLK_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 1),
Kojto 148:fd96258d940d 435 kWDT_OSC_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 2),
Kojto 148:fd96258d940d 436 kFRO_HF_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 3),
Kojto 148:fd96258d940d 437 kSYS_PLL_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 4),
Kojto 148:fd96258d940d 438 kFRO12M_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 5),
Kojto 148:fd96258d940d 439 kOSC32K_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 6),
Kojto 148:fd96258d940d 440 kNONE_to_CLKOUT = MUX_A(CM_CLKOUTCLKSELA, 7),
Kojto 148:fd96258d940d 441 kNONE_to_NONE = 0x80000000U,
Kojto 148:fd96258d940d 442 } clock_attach_id_t;
Kojto 148:fd96258d940d 443
Kojto 148:fd96258d940d 444 /* Clock dividers */
Kojto 148:fd96258d940d 445 typedef enum _clock_div_name
Kojto 148:fd96258d940d 446 {
Kojto 148:fd96258d940d 447 kCLOCK_DivSystickClk = 0,
Kojto 148:fd96258d940d 448 kCLOCK_DivTraceClk = 1,
Kojto 148:fd96258d940d 449 kCLOCK_DivAhbClk = 32,
Kojto 148:fd96258d940d 450 kCLOCK_DivClkOut = 33,
Kojto 148:fd96258d940d 451 kCLOCK_DivSpifiClk = 36,
Kojto 148:fd96258d940d 452 kCLOCK_DivAdcAsyncClk = 37,
Kojto 148:fd96258d940d 453 kCLOCK_DivUsbClk = 38,
Kojto 148:fd96258d940d 454 kCLOCK_DivFrg = 40,
Kojto 148:fd96258d940d 455 kCLOCK_DivDmicClk = 42,
Kojto 148:fd96258d940d 456 kCLOCK_DivFxI2s0MClk = 43
Kojto 148:fd96258d940d 457 } clock_div_name_t;
Kojto 148:fd96258d940d 458
Kojto 148:fd96258d940d 459 /*******************************************************************************
Kojto 148:fd96258d940d 460 * API
Kojto 148:fd96258d940d 461 ******************************************************************************/
Kojto 148:fd96258d940d 462
Kojto 148:fd96258d940d 463 #if defined(__cplusplus)
Kojto 148:fd96258d940d 464 extern "C" {
Kojto 148:fd96258d940d 465 #endif /* __cplusplus */
Kojto 148:fd96258d940d 466
Kojto 148:fd96258d940d 467 static inline void CLOCK_EnableClock(clock_ip_name_t clk)
Kojto 148:fd96258d940d 468 {
Kojto 148:fd96258d940d 469 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
Kojto 148:fd96258d940d 470 if (index < 2)
Kojto 148:fd96258d940d 471 {
Kojto 148:fd96258d940d 472 SYSCON->AHBCLKCTRLSET[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
Kojto 148:fd96258d940d 473 }
Kojto 148:fd96258d940d 474 else
Kojto 148:fd96258d940d 475 {
Kojto 148:fd96258d940d 476 ASYNC_SYSCON->ASYNCAPBCLKCTRLSET = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
Kojto 148:fd96258d940d 477 }
Kojto 148:fd96258d940d 478 }
Kojto 148:fd96258d940d 479
Kojto 148:fd96258d940d 480 static inline void CLOCK_DisableClock(clock_ip_name_t clk)
Kojto 148:fd96258d940d 481 {
Kojto 148:fd96258d940d 482 uint32_t index = CLK_GATE_ABSTRACT_REG_OFFSET(clk);
Kojto 148:fd96258d940d 483 if (index < 2)
Kojto 148:fd96258d940d 484 {
Kojto 148:fd96258d940d 485 SYSCON->AHBCLKCTRLCLR[index] = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
Kojto 148:fd96258d940d 486 }
Kojto 148:fd96258d940d 487 else
Kojto 148:fd96258d940d 488 {
Kojto 148:fd96258d940d 489 ASYNC_SYSCON->ASYNCAPBCLKCTRLCLR = (1U << CLK_GATE_ABSTRACT_BITS_SHIFT(clk));
Kojto 148:fd96258d940d 490 }
Kojto 148:fd96258d940d 491 }
Kojto 148:fd96258d940d 492 /**
Kojto 148:fd96258d940d 493 * @brief FLASH Access time definitions
Kojto 148:fd96258d940d 494 */
Kojto 148:fd96258d940d 495 typedef enum _clock_flashtim
Kojto 148:fd96258d940d 496 {
Kojto 148:fd96258d940d 497 kCLOCK_Flash1Cycle = 0, /*!< Flash accesses use 1 CPU clock */
Kojto 148:fd96258d940d 498 kCLOCK_Flash2Cycle, /*!< Flash accesses use 2 CPU clocks */
Kojto 148:fd96258d940d 499 kCLOCK_Flash3Cycle, /*!< Flash accesses use 3 CPU clocks */
Kojto 148:fd96258d940d 500 kCLOCK_Flash4Cycle, /*!< Flash accesses use 4 CPU clocks */
Kojto 148:fd96258d940d 501 kCLOCK_Flash5Cycle, /*!< Flash accesses use 5 CPU clocks */
Kojto 148:fd96258d940d 502 kCLOCK_Flash6Cycle, /*!< Flash accesses use 6 CPU clocks */
Kojto 148:fd96258d940d 503 kCLOCK_Flash7Cycle, /*!< Flash accesses use 7 CPU clocks */
Kojto 148:fd96258d940d 504 kCLOCK_Flash8Cycle /*!< Flash accesses use 8 CPU clocks */
Kojto 148:fd96258d940d 505 } clock_flashtim_t;
Kojto 148:fd96258d940d 506
Kojto 148:fd96258d940d 507 /**
Kojto 148:fd96258d940d 508 * @brief Set FLASH memory access time in clocks
Kojto 148:fd96258d940d 509 * @param clks : Clock cycles for FLASH access
Kojto 148:fd96258d940d 510 * @return Nothing
Kojto 148:fd96258d940d 511 */
Kojto 148:fd96258d940d 512 static inline void CLOCK_SetFLASHAccessCycles(clock_flashtim_t clks)
Kojto 148:fd96258d940d 513 {
Kojto 148:fd96258d940d 514 uint32_t tmp;
Kojto 148:fd96258d940d 515
Kojto 148:fd96258d940d 516 tmp = SYSCON->FLASHCFG & ~(SYSCON_FLASHCFG_FLASHTIM_MASK);
Kojto 148:fd96258d940d 517
Kojto 148:fd96258d940d 518 /* Don't alter lower bits */
Kojto 148:fd96258d940d 519 SYSCON->FLASHCFG = tmp | ((uint32_t)clks << SYSCON_FLASHCFG_FLASHTIM_SHIFT);
Kojto 148:fd96258d940d 520 }
Kojto 148:fd96258d940d 521
Kojto 148:fd96258d940d 522 /**
Kojto 148:fd96258d940d 523 * @brief Initialize the Core clock to given frequency (12, 48 or 96 MHz).
Kojto 148:fd96258d940d 524 * Turns on FRO and uses default CCO, if freq is 12000000, then high speed output is off, else high speed output is
Kojto 148:fd96258d940d 525 * enabled.
Kojto 148:fd96258d940d 526 * @param iFreq : Desired frequency (must be one of CLK_FRO_12MHZ or CLK_FRO_48MHZ or CLK_FRO_96MHZ)
Kojto 148:fd96258d940d 527 * @return returns success or fail status.
Kojto 148:fd96258d940d 528 */
Kojto 148:fd96258d940d 529 status_t CLOCK_SetupFROClocking(uint32_t iFreq);
Kojto 148:fd96258d940d 530 /**
Kojto 148:fd96258d940d 531 * @brief Configure the clock selection muxes.
Kojto 148:fd96258d940d 532 * @param connection : Clock to be configured.
Kojto 148:fd96258d940d 533 * @return Nothing
Kojto 148:fd96258d940d 534 */
Kojto 148:fd96258d940d 535 void CLOCK_AttachClk(clock_attach_id_t connection);
Kojto 148:fd96258d940d 536 /**
Kojto 148:fd96258d940d 537 * @brief Setup peripheral clock dividers.
Kojto 148:fd96258d940d 538 * @param div_name : Clock divider name
Kojto 148:fd96258d940d 539 * @param divided_by_value: Value to be divided
Kojto 148:fd96258d940d 540 * @param reset : Whether to reset the divider counter.
Kojto 148:fd96258d940d 541 * @return Nothing
Kojto 148:fd96258d940d 542 */
Kojto 148:fd96258d940d 543 void CLOCK_SetClkDiv(clock_div_name_t div_name, uint32_t divided_by_value, bool reset);
Kojto 148:fd96258d940d 544 /**
Kojto 148:fd96258d940d 545 * @brief Set the flash wait states for the input freuqency.
Kojto 148:fd96258d940d 546 * @param iFreq : Input frequency
Kojto 148:fd96258d940d 547 * @return Nothing
Kojto 148:fd96258d940d 548 */
Kojto 148:fd96258d940d 549 void CLOCK_SetFLASHAccessCyclesForFreq(uint32_t iFreq);
Kojto 148:fd96258d940d 550 /*! @brief Return Frequency of selected clock
Kojto 148:fd96258d940d 551 * @return Frequency of selected clock
Kojto 148:fd96258d940d 552 */
Kojto 148:fd96258d940d 553 uint32_t CLOCK_GetFreq(clock_name_t clockName);
Kojto 148:fd96258d940d 554
Kojto 148:fd96258d940d 555 /*! @brief Return Input frequency for the Fractional baud rate generator
Kojto 148:fd96258d940d 556 * @return Input Frequency for FRG
Kojto 148:fd96258d940d 557 */
Kojto 148:fd96258d940d 558 uint32_t CLOCK_GetFRGInputClock(void);
Kojto 148:fd96258d940d 559
Kojto 148:fd96258d940d 560 /*! @brief Set output of the Fractional baud rate generator
Kojto 148:fd96258d940d 561 * @param freq : Desired output frequency
Kojto 148:fd96258d940d 562 * @return Error Code 0 - fail 1 - success
Kojto 148:fd96258d940d 563 */
Kojto 148:fd96258d940d 564 uint32_t CLOCK_SetFRGClock(uint32_t freq);
Kojto 148:fd96258d940d 565
Kojto 148:fd96258d940d 566 /*! @brief Return Frequency of FRO 12MHz
Kojto 148:fd96258d940d 567 * @return Frequency of FRO 12MHz
Kojto 148:fd96258d940d 568 */
Kojto 148:fd96258d940d 569 uint32_t CLOCK_GetFro12MFreq(void);
Kojto 148:fd96258d940d 570 /*! @brief Return Frequency of External Clock
Kojto 148:fd96258d940d 571 * @return Frequency of External Clock. If no external clock is used returns 0.
Kojto 148:fd96258d940d 572 */
Kojto 148:fd96258d940d 573 uint32_t CLOCK_GetExtClkFreq(void);
Kojto 148:fd96258d940d 574 /*! @brief Return Frequency of Watchdog Oscillator
Kojto 148:fd96258d940d 575 * @return Frequency of Watchdog Oscillator
Kojto 148:fd96258d940d 576 */
Kojto 148:fd96258d940d 577 uint32_t CLOCK_GetWdtOscFreq(void);
Kojto 148:fd96258d940d 578 /*! @brief Return Frequency of High-Freq output of FRO
Kojto 148:fd96258d940d 579 * @return Frequency of High-Freq output of FRO
Kojto 148:fd96258d940d 580 */
Kojto 148:fd96258d940d 581 uint32_t CLOCK_GetFroHfFreq(void);
Kojto 148:fd96258d940d 582 /*! @brief Return Frequency of PLL
Kojto 148:fd96258d940d 583 * @return Frequency of PLL
Kojto 148:fd96258d940d 584 */
Kojto 148:fd96258d940d 585 uint32_t CLOCK_GetPllOutFreq(void);
Kojto 148:fd96258d940d 586 /*! @brief Return Frequency of 32kHz osc
Kojto 148:fd96258d940d 587 * @return Frequency of 32kHz osc
Kojto 148:fd96258d940d 588 */
Kojto 148:fd96258d940d 589 uint32_t CLOCK_GetOsc32KFreq(void);
Kojto 148:fd96258d940d 590 /*! @brief Return Frequency of Core System
Kojto 148:fd96258d940d 591 * @return Frequency of Core System
Kojto 148:fd96258d940d 592 */
Kojto 148:fd96258d940d 593 uint32_t CLOCK_GetCoreSysClkFreq(void);
Kojto 148:fd96258d940d 594 /*! @brief Return Frequency of I2S MCLK Clock
Kojto 148:fd96258d940d 595 * @return Frequency of I2S MCLK Clock
Kojto 148:fd96258d940d 596 */
Kojto 148:fd96258d940d 597 uint32_t CLOCK_GetI2SMClkFreq(void);
Kojto 148:fd96258d940d 598 /*! @brief Return Frequency of Flexcomm functional Clock
Kojto 148:fd96258d940d 599 * @return Frequency of Flexcomm functional Clock
Kojto 148:fd96258d940d 600 */
Kojto 148:fd96258d940d 601 uint32_t CLOCK_GetFlexCommClkFreq(uint32_t id);
Kojto 148:fd96258d940d 602 /*! @brief Return Asynchronous APB Clock source
Kojto 148:fd96258d940d 603 * @return Asynchronous APB CLock source
Kojto 148:fd96258d940d 604 */
Kojto 148:fd96258d940d 605 __STATIC_INLINE async_clock_src_t CLOCK_GetAsyncApbClkSrc(void)
Kojto 148:fd96258d940d 606 {
Kojto 148:fd96258d940d 607 return (async_clock_src_t)(ASYNC_SYSCON->ASYNCAPBCLKSELA & 0x3);
Kojto 148:fd96258d940d 608 }
Kojto 148:fd96258d940d 609 /*! @brief Return Frequency of Asynchronous APB Clock
Kojto 148:fd96258d940d 610 * @return Frequency of Asynchronous APB Clock Clock
Kojto 148:fd96258d940d 611 */
Kojto 148:fd96258d940d 612 uint32_t CLOCK_GetAsyncApbClkFreq(void);
Kojto 148:fd96258d940d 613 /*! @brief Return System PLL input clock rate
Kojto 148:fd96258d940d 614 * @return System PLL input clock rate
Kojto 148:fd96258d940d 615 */
Kojto 148:fd96258d940d 616 uint32_t CLOCK_GetSystemPLLInClockRate(void);
Kojto 148:fd96258d940d 617
Kojto 148:fd96258d940d 618 /*! @brief Return System PLL output clock rate
Kojto 148:fd96258d940d 619 * @param recompute : Forces a PLL rate recomputation if true
Kojto 148:fd96258d940d 620 * @return System PLL output clock rate
Kojto 148:fd96258d940d 621 * @note The PLL rate is cached in the driver in a variable as
Kojto 148:fd96258d940d 622 * the rate computation function can take some time to perform. It
Kojto 148:fd96258d940d 623 * is recommended to use 'false' with the 'recompute' parameter.
Kojto 148:fd96258d940d 624 */
Kojto 148:fd96258d940d 625 uint32_t CLOCK_GetSystemPLLOutClockRate(bool recompute);
Kojto 148:fd96258d940d 626
Kojto 148:fd96258d940d 627 /*! @brief Enables and disables PLL bypass mode
Kojto 148:fd96258d940d 628 * @brief bypass : true to bypass PLL (PLL output = PLL input, false to disable bypass
Kojto 148:fd96258d940d 629 * @return System PLL output clock rate
Kojto 148:fd96258d940d 630 */
Kojto 148:fd96258d940d 631 __STATIC_INLINE void CLOCK_SetBypassPLL(bool bypass)
Kojto 148:fd96258d940d 632 {
Kojto 148:fd96258d940d 633 if (bypass)
Kojto 148:fd96258d940d 634 {
Kojto 148:fd96258d940d 635 SYSCON->SYSPLLCTRL |= (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
Kojto 148:fd96258d940d 636 }
Kojto 148:fd96258d940d 637 else
Kojto 148:fd96258d940d 638 {
Kojto 148:fd96258d940d 639 SYSCON->SYSPLLCTRL &= ~(1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT);
Kojto 148:fd96258d940d 640 }
Kojto 148:fd96258d940d 641 }
Kojto 148:fd96258d940d 642
Kojto 148:fd96258d940d 643 /*! @brief Check if PLL is locked or not
Kojto 148:fd96258d940d 644 * @return true if the PLL is locked, false if not locked
Kojto 148:fd96258d940d 645 */
Kojto 148:fd96258d940d 646 __STATIC_INLINE bool CLOCK_IsSystemPLLLocked(void)
Kojto 148:fd96258d940d 647 {
Kojto 148:fd96258d940d 648 return (bool)((SYSCON->SYSPLLSTAT & SYSCON_SYSPLLSTAT_LOCK_MASK) != 0);
Kojto 148:fd96258d940d 649 }
Kojto 148:fd96258d940d 650
Kojto 148:fd96258d940d 651 /*! @brief Store the current PLL rate
Kojto 148:fd96258d940d 652 * @param rate: Current rate of the PLL
Kojto 148:fd96258d940d 653 * @return Nothing
Kojto 148:fd96258d940d 654 **/
Kojto 148:fd96258d940d 655 void CLOCK_SetStoredPLLClockRate(uint32_t rate);
Kojto 148:fd96258d940d 656
Kojto 148:fd96258d940d 657 /*! @brief PLL configuration structure flags for 'flags' field
Kojto 148:fd96258d940d 658 * These flags control how the PLL configuration function sets up the PLL setup structure.<br>
Kojto 148:fd96258d940d 659 *
Kojto 148:fd96258d940d 660 * When the PLL_CONFIGFLAG_USEINRATE flag is selected, the 'InputRate' field in the
Kojto 148:fd96258d940d 661 * configuration structure must be assigned with the expected PLL frequency. If the
Kojto 148:fd96258d940d 662 * PLL_CONFIGFLAG_USEINRATE is not used, 'InputRate' is ignored in the configuration
Kojto 148:fd96258d940d 663 * function and the driver will determine the PLL rate from the currently selected
Kojto 148:fd96258d940d 664 * PLL source. This flag might be used to configure the PLL input clock more accurately
Kojto 148:fd96258d940d 665 * when using the WDT oscillator or a more dyanmic CLKIN source.<br>
Kojto 148:fd96258d940d 666 *
Kojto 148:fd96258d940d 667 * When the PLL_CONFIGFLAG_FORCENOFRACT flag is selected, the PLL hardware for the
Kojto 148:fd96258d940d 668 * automatic bandwidth selection, Spread Spectrum (SS) support, and fractional M-divider
Kojto 148:fd96258d940d 669 * are not used.<br>
Kojto 148:fd96258d940d 670 */
Kojto 148:fd96258d940d 671 #define PLL_CONFIGFLAG_USEINRATE (1 << 0) /*!< Flag to use InputRate in PLL configuration structure for setup */
Kojto 148:fd96258d940d 672 #define PLL_CONFIGFLAG_FORCENOFRACT \
Kojto 148:fd96258d940d 673 (1 \
Kojto 148:fd96258d940d 674 << 2) /*!< Force non-fractional output mode, PLL output will not use the fractional, automatic bandwidth, or SS \ \
Kojto 148:fd96258d940d 675 \ \ \ \
Kojto 148:fd96258d940d 676 \ \ \ \ \ \
Kojto 148:fd96258d940d 677 \ \ \ \ \ \ \ \
Kojto 148:fd96258d940d 678 hardware */
Kojto 148:fd96258d940d 679
Kojto 148:fd96258d940d 680 /*! @brief PLL Spread Spectrum (SS) Programmable modulation frequency
Kojto 148:fd96258d940d 681 * See (MF) field in the SYSPLLSSCTRL1 register in the UM.
Kojto 148:fd96258d940d 682 */
Kojto 148:fd96258d940d 683 typedef enum _ss_progmodfm
Kojto 148:fd96258d940d 684 {
Kojto 148:fd96258d940d 685 kSS_MF_512 = (0 << 20), /*!< Nss = 512 (fm ? 3.9 - 7.8 kHz) */
Kojto 148:fd96258d940d 686 kSS_MF_384 = (1 << 20), /*!< Nss ?= 384 (fm ? 5.2 - 10.4 kHz) */
Kojto 148:fd96258d940d 687 kSS_MF_256 = (2 << 20), /*!< Nss = 256 (fm ? 7.8 - 15.6 kHz) */
Kojto 148:fd96258d940d 688 kSS_MF_128 = (3 << 20), /*!< Nss = 128 (fm ? 15.6 - 31.3 kHz) */
Kojto 148:fd96258d940d 689 kSS_MF_64 = (4 << 20), /*!< Nss = 64 (fm ? 32.3 - 64.5 kHz) */
Kojto 148:fd96258d940d 690 kSS_MF_32 = (5 << 20), /*!< Nss = 32 (fm ? 62.5- 125 kHz) */
Kojto 148:fd96258d940d 691 kSS_MF_24 = (6 << 20), /*!< Nss ?= 24 (fm ? 83.3- 166.6 kHz) */
Kojto 148:fd96258d940d 692 kSS_MF_16 = (7 << 20) /*!< Nss = 16 (fm ? 125- 250 kHz) */
Kojto 148:fd96258d940d 693 } ss_progmodfm_t;
Kojto 148:fd96258d940d 694
Kojto 148:fd96258d940d 695 /*! @brief PLL Spread Spectrum (SS) Programmable frequency modulation depth
Kojto 148:fd96258d940d 696 * See (MR) field in the SYSPLLSSCTRL1 register in the UM.
Kojto 148:fd96258d940d 697 */
Kojto 148:fd96258d940d 698 typedef enum _ss_progmoddp
Kojto 148:fd96258d940d 699 {
Kojto 148:fd96258d940d 700 kSS_MR_K0 = (0 << 23), /*!< k = 0 (no spread spectrum) */
Kojto 148:fd96258d940d 701 kSS_MR_K1 = (1 << 23), /*!< k = 1 */
Kojto 148:fd96258d940d 702 kSS_MR_K1_5 = (2 << 23), /*!< k = 1.5 */
Kojto 148:fd96258d940d 703 kSS_MR_K2 = (3 << 23), /*!< k = 2 */
Kojto 148:fd96258d940d 704 kSS_MR_K3 = (4 << 23), /*!< k = 3 */
Kojto 148:fd96258d940d 705 kSS_MR_K4 = (5 << 23), /*!< k = 4 */
Kojto 148:fd96258d940d 706 kSS_MR_K6 = (6 << 23), /*!< k = 6 */
Kojto 148:fd96258d940d 707 kSS_MR_K8 = (7 << 23) /*!< k = 8 */
Kojto 148:fd96258d940d 708 } ss_progmoddp_t;
Kojto 148:fd96258d940d 709
Kojto 148:fd96258d940d 710 /*! @brief PLL Spread Spectrum (SS) Modulation waveform control
Kojto 148:fd96258d940d 711 * See (MC) field in the SYSPLLSSCTRL1 register in the UM.<br>
Kojto 148:fd96258d940d 712 * Compensation for low pass filtering of the PLL to get a triangular
Kojto 148:fd96258d940d 713 * modulation at the output of the PLL, giving a flat frequency spectrum.
Kojto 148:fd96258d940d 714 */
Kojto 148:fd96258d940d 715 typedef enum _ss_modwvctrl
Kojto 148:fd96258d940d 716 {
Kojto 148:fd96258d940d 717 kSS_MC_NOC = (0 << 26), /*!< no compensation */
Kojto 148:fd96258d940d 718 kSS_MC_RECC = (2 << 26), /*!< recommended setting */
Kojto 148:fd96258d940d 719 kSS_MC_MAXC = (3 << 26), /*!< max. compensation */
Kojto 148:fd96258d940d 720 } ss_modwvctrl_t;
Kojto 148:fd96258d940d 721
Kojto 148:fd96258d940d 722 /*! @brief PLL configuration structure
Kojto 148:fd96258d940d 723 *
Kojto 148:fd96258d940d 724 * This structure can be used to configure the settings for a PLL
Kojto 148:fd96258d940d 725 * setup structure. Fill in the desired configuration for the PLL
Kojto 148:fd96258d940d 726 * and call the PLL setup function to fill in a PLL setup structure.
Kojto 148:fd96258d940d 727 */
Kojto 148:fd96258d940d 728 typedef struct _pll_config
Kojto 148:fd96258d940d 729 {
Kojto 148:fd96258d940d 730 uint32_t desiredRate; /*!< Desired PLL rate in Hz */
Kojto 148:fd96258d940d 731 uint32_t inputRate; /*!< PLL input clock in Hz, only used if PLL_CONFIGFLAG_USEINRATE flag is set */
Kojto 148:fd96258d940d 732 uint32_t flags; /*!< PLL configuration flags, Or'ed value of PLL_CONFIGFLAG_* definitions */
Kojto 148:fd96258d940d 733 ss_progmodfm_t ss_mf; /*!< SS Programmable modulation frequency, only applicable when not using
Kojto 148:fd96258d940d 734 PLL_CONFIGFLAG_FORCENOFRACT flag */
Kojto 148:fd96258d940d 735 ss_progmoddp_t ss_mr; /*!< SS Programmable frequency modulation depth, only applicable when not using
Kojto 148:fd96258d940d 736 PLL_CONFIGFLAG_FORCENOFRACT flag */
Kojto 148:fd96258d940d 737 ss_modwvctrl_t
Kojto 148:fd96258d940d 738 ss_mc; /*!< SS Modulation waveform control, only applicable when not using PLL_CONFIGFLAG_FORCENOFRACT flag */
Kojto 148:fd96258d940d 739 bool mfDither; /*!< false for fixed modulation frequency or true for dithering, only applicable when not using
Kojto 148:fd96258d940d 740 PLL_CONFIGFLAG_FORCENOFRACT flag */
Kojto 148:fd96258d940d 741
Kojto 148:fd96258d940d 742 } pll_config_t;
Kojto 148:fd96258d940d 743
Kojto 148:fd96258d940d 744 /*! @brief PLL setup structure flags for 'flags' field
Kojto 148:fd96258d940d 745 * These flags control how the PLL setup function sets up the PLL
Kojto 148:fd96258d940d 746 */
Kojto 148:fd96258d940d 747 #define PLL_SETUPFLAG_POWERUP (1 << 0) /*!< Setup will power on the PLL after setup */
Kojto 148:fd96258d940d 748 #define PLL_SETUPFLAG_WAITLOCK (1 << 1) /*!< Setup will wait for PLL lock, implies the PLL will be pwoered on */
Kojto 148:fd96258d940d 749 #define PLL_SETUPFLAG_ADGVOLT (1 << 2) /*!< Optimize system voltage for the new PLL rate */
Kojto 148:fd96258d940d 750
Kojto 148:fd96258d940d 751 /*! @brief PLL setup structure
Kojto 148:fd96258d940d 752 * This structure can be used to pre-build a PLL setup configuration
Kojto 148:fd96258d940d 753 * at run-time and quickly set the PLL to the configuration. It can be
Kojto 148:fd96258d940d 754 * populated with the PLL setup function. If powering up or waiting
Kojto 148:fd96258d940d 755 * for PLL lock, the PLL input clock source should be configured prior
Kojto 148:fd96258d940d 756 * to PLL setup.
Kojto 148:fd96258d940d 757 */
Kojto 148:fd96258d940d 758 typedef struct _pll_setup
Kojto 148:fd96258d940d 759 {
Kojto 148:fd96258d940d 760 uint32_t syspllctrl; /*!< PLL control register SYSPLLCTRL */
Kojto 148:fd96258d940d 761 uint32_t syspllndec; /*!< PLL NDEC register SYSPLLNDEC */
Kojto 148:fd96258d940d 762 uint32_t syspllpdec; /*!< PLL PDEC register SYSPLLPDEC */
Kojto 148:fd96258d940d 763 uint32_t syspllssctrl[2]; /*!< PLL SSCTL registers SYSPLLSSCTRL */
Kojto 148:fd96258d940d 764 uint32_t pllRate; /*!< Acutal PLL rate */
Kojto 148:fd96258d940d 765 uint32_t flags; /*!< PLL setup flags, Or'ed value of PLL_SETUPFLAG_* definitions */
Kojto 148:fd96258d940d 766 } pll_setup_t;
Kojto 148:fd96258d940d 767
Kojto 148:fd96258d940d 768 /*! @brief PLL status definitions
Kojto 148:fd96258d940d 769 */
Kojto 148:fd96258d940d 770 typedef enum _pll_error
Kojto 148:fd96258d940d 771 {
Kojto 148:fd96258d940d 772 kStatus_PLL_Success = MAKE_STATUS(kStatusGroup_Generic, 0), /*!< PLL operation was successful */
Kojto 148:fd96258d940d 773 kStatus_PLL_OutputTooLow = MAKE_STATUS(kStatusGroup_Generic, 1), /*!< PLL output rate request was too low */
Kojto 148:fd96258d940d 774 kStatus_PLL_OutputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 2), /*!< PLL output rate request was too high */
Kojto 148:fd96258d940d 775 kStatus_PLL_InputTooLow = MAKE_STATUS(kStatusGroup_Generic, 3), /*!< PLL input rate is too low */
Kojto 148:fd96258d940d 776 kStatus_PLL_InputTooHigh = MAKE_STATUS(kStatusGroup_Generic, 4), /*!< PLL input rate is too high */
Kojto 148:fd96258d940d 777 kStatus_PLL_OutsideIntLimit = MAKE_STATUS(kStatusGroup_Generic, 5) /*!< Requested output rate isn't possible */
Kojto 148:fd96258d940d 778 } pll_error_t;
Kojto 148:fd96258d940d 779
Kojto 148:fd96258d940d 780 /*! @brief USB clock source definition. */
Kojto 148:fd96258d940d 781 typedef enum _clock_usb_src
Kojto 148:fd96258d940d 782 {
Kojto 148:fd96258d940d 783 kCLOCK_UsbSrcFro = (uint32_t)kCLOCK_FroHf, /*!< Use FRO 96 or 48 MHz. */
Kojto 148:fd96258d940d 784 kCLOCK_UsbSrcSystemPll = (uint32_t)kCLOCK_PllOut, /*!< Use System PLL output. */
Kojto 148:fd96258d940d 785 kCLOCK_UsbSrcMainClock = (uint32_t)kCLOCK_CoreSysClk, /*!< Use Main clock. */
Kojto 148:fd96258d940d 786 kCLOCK_UsbSrcNone = SYSCON_USBCLKSEL_SEL(
Kojto 148:fd96258d940d 787 7) /*!< Use None, this may be selected in order to reduce power when no output is needed. */
Kojto 148:fd96258d940d 788 } clock_usb_src_t;
Kojto 148:fd96258d940d 789
Kojto 148:fd96258d940d 790 /*! @brief Return System PLL output clock rate from setup structure
Kojto 148:fd96258d940d 791 * @param pSetup : Pointer to a PLL setup structure
Kojto 148:fd96258d940d 792 * @return System PLL output clock rate calculated from the setup structure
Kojto 148:fd96258d940d 793 */
Kojto 148:fd96258d940d 794 uint32_t CLOCK_GetSystemPLLOutFromSetup(pll_setup_t *pSetup);
Kojto 148:fd96258d940d 795
Kojto 148:fd96258d940d 796 /*! @brief Set PLL output based on the passed PLL setup data
Kojto 148:fd96258d940d 797 * @param pControl : Pointer to populated PLL control structure to generate setup with
Kojto 148:fd96258d940d 798 * @param pSetup : Pointer to PLL setup structure to be filled
Kojto 148:fd96258d940d 799 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
Kojto 148:fd96258d940d 800 * @note Actual frequency for setup may vary from the desired frequency based on the
Kojto 148:fd96258d940d 801 * accuracy of input clocks, rounding, non-fractional PLL mode, etc.
Kojto 148:fd96258d940d 802 */
Kojto 148:fd96258d940d 803 pll_error_t CLOCK_SetupPLLData(pll_config_t *pControl, pll_setup_t *pSetup);
Kojto 148:fd96258d940d 804
Kojto 148:fd96258d940d 805 /*! @brief Set PLL output from PLL setup structure (precise frequency)
Kojto 148:fd96258d940d 806 * @param pSetup : Pointer to populated PLL setup structure
Kojto 148:fd96258d940d 807 * @param flagcfg : Flag configuration for PLL config structure
Kojto 148:fd96258d940d 808 * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
Kojto 148:fd96258d940d 809 * @note This function will power off the PLL, setup the PLL with the
Kojto 148:fd96258d940d 810 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
Kojto 148:fd96258d940d 811 * and adjust system voltages to the new PLL rate. The function will not
Kojto 148:fd96258d940d 812 * alter any source clocks (ie, main systen clock) that may use the PLL,
Kojto 148:fd96258d940d 813 * so these should be setup prior to and after exiting the function.
Kojto 148:fd96258d940d 814 */
Kojto 148:fd96258d940d 815 pll_error_t CLOCK_SetupSystemPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
Kojto 148:fd96258d940d 816
Kojto 148:fd96258d940d 817 /**
Kojto 148:fd96258d940d 818 * @brief Set PLL output from PLL setup structure (precise frequency)
Kojto 148:fd96258d940d 819 * @param pSetup : Pointer to populated PLL setup structure
Kojto 148:fd96258d940d 820 * @return kStatus_PLL_Success on success, or PLL setup error code
Kojto 148:fd96258d940d 821 * @note This function will power off the PLL, setup the PLL with the
Kojto 148:fd96258d940d 822 * new setup data, and then optionally powerup the PLL, wait for PLL lock,
Kojto 148:fd96258d940d 823 * and adjust system voltages to the new PLL rate. The function will not
Kojto 148:fd96258d940d 824 * alter any source clocks (ie, main systen clock) that may use the PLL,
Kojto 148:fd96258d940d 825 * so these should be setup prior to and after exiting the function.
Kojto 148:fd96258d940d 826 */
Kojto 148:fd96258d940d 827 pll_error_t CLOCK_SetPLLFreq(const pll_setup_t *pSetup);
Kojto 148:fd96258d940d 828
Kojto 148:fd96258d940d 829 /*! @brief Set PLL output based on the multiplier and input frequency
Kojto 148:fd96258d940d 830 * @param multiply_by : multiplier
Kojto 148:fd96258d940d 831 * @param input_freq : Clock input frequency of the PLL
Kojto 148:fd96258d940d 832 * @return Nothing
Kojto 148:fd96258d940d 833 * @note Unlike the Chip_Clock_SetupSystemPLLPrec() function, this
Kojto 148:fd96258d940d 834 * function does not disable or enable PLL power, wait for PLL lock,
Kojto 148:fd96258d940d 835 * or adjust system voltages. These must be done in the application.
Kojto 148:fd96258d940d 836 * The function will not alter any source clocks (ie, main systen clock)
Kojto 148:fd96258d940d 837 * that may use the PLL, so these should be setup prior to and after
Kojto 148:fd96258d940d 838 * exiting the function.
Kojto 148:fd96258d940d 839 */
Kojto 148:fd96258d940d 840 void CLOCK_SetupSystemPLLMult(uint32_t multiply_by, uint32_t input_freq);
Kojto 148:fd96258d940d 841
Kojto 148:fd96258d940d 842 /*! @brief Disable USB FS clock.
Kojto 148:fd96258d940d 843 *
Kojto 148:fd96258d940d 844 * Disable USB FS clock.
Kojto 148:fd96258d940d 845 */
Kojto 148:fd96258d940d 846 static inline void CLOCK_DisableUsbfs0Clock(void)
Kojto 148:fd96258d940d 847 {
Kojto 148:fd96258d940d 848 CLOCK_DisableClock(kCLOCK_Usbd0);
Kojto 148:fd96258d940d 849 }
Kojto 148:fd96258d940d 850 bool CLOCK_EnableUsbfs0Clock(clock_usb_src_t src, uint32_t freq);
Kojto 148:fd96258d940d 851 #if defined(__cplusplus)
Kojto 148:fd96258d940d 852 }
Kojto 148:fd96258d940d 853 #endif /* __cplusplus */
Kojto 148:fd96258d940d 854
Kojto 148:fd96258d940d 855 /*! @} */
Kojto 148:fd96258d940d 856
Kojto 148:fd96258d940d 857 #endif /* _FSL_CLOCK_H_ */