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TARGET_LPC1768/TOOLCHAIN_ARM_STD/LPC17xx.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file LPC17xx.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
AnnaBridge 171:3a7713b1edbc 4 * NXP LPC17xx Device Series
AnnaBridge 171:3a7713b1edbc 5 * @version: V1.09
AnnaBridge 171:3a7713b1edbc 6 * @date: 17. March 2010
AnnaBridge 171:3a7713b1edbc 7
AnnaBridge 171:3a7713b1edbc 8 *
AnnaBridge 171:3a7713b1edbc 9 * @note
AnnaBridge 171:3a7713b1edbc 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * @par
AnnaBridge 171:3a7713b1edbc 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
AnnaBridge 171:3a7713b1edbc 14 * processor based microcontrollers. This file can be freely distributed
AnnaBridge 171:3a7713b1edbc 15 * within development tools that are supporting such ARM based processors.
AnnaBridge 171:3a7713b1edbc 16 *
AnnaBridge 171:3a7713b1edbc 17 * @par
AnnaBridge 171:3a7713b1edbc 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
AnnaBridge 171:3a7713b1edbc 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
AnnaBridge 171:3a7713b1edbc 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
AnnaBridge 171:3a7713b1edbc 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
AnnaBridge 171:3a7713b1edbc 23 *
AnnaBridge 171:3a7713b1edbc 24 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 25
AnnaBridge 171:3a7713b1edbc 26
AnnaBridge 171:3a7713b1edbc 27 #ifndef __LPC17xx_H__
AnnaBridge 171:3a7713b1edbc 28 #define __LPC17xx_H__
AnnaBridge 171:3a7713b1edbc 29
AnnaBridge 171:3a7713b1edbc 30 /*
AnnaBridge 171:3a7713b1edbc 31 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 32 * ---------- Interrupt Number Definition -----------------------------------
AnnaBridge 171:3a7713b1edbc 33 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 34 */
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 37 {
AnnaBridge 171:3a7713b1edbc 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
AnnaBridge 171:3a7713b1edbc 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 47
AnnaBridge 171:3a7713b1edbc 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
AnnaBridge 171:3a7713b1edbc 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
AnnaBridge 171:3a7713b1edbc 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
AnnaBridge 171:3a7713b1edbc 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
AnnaBridge 171:3a7713b1edbc 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
AnnaBridge 171:3a7713b1edbc 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
AnnaBridge 171:3a7713b1edbc 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
AnnaBridge 171:3a7713b1edbc 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
AnnaBridge 171:3a7713b1edbc 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
AnnaBridge 171:3a7713b1edbc 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
AnnaBridge 171:3a7713b1edbc 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
AnnaBridge 171:3a7713b1edbc 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
AnnaBridge 171:3a7713b1edbc 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
AnnaBridge 171:3a7713b1edbc 62 SPI_IRQn = 13, /*!< SPI Interrupt */
AnnaBridge 171:3a7713b1edbc 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
AnnaBridge 171:3a7713b1edbc 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
AnnaBridge 171:3a7713b1edbc 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
AnnaBridge 171:3a7713b1edbc 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
AnnaBridge 171:3a7713b1edbc 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
AnnaBridge 171:3a7713b1edbc 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
AnnaBridge 171:3a7713b1edbc 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
AnnaBridge 171:3a7713b1edbc 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
AnnaBridge 171:3a7713b1edbc 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
AnnaBridge 171:3a7713b1edbc 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
AnnaBridge 171:3a7713b1edbc 73 USB_IRQn = 24, /*!< USB Interrupt */
AnnaBridge 171:3a7713b1edbc 74 CAN_IRQn = 25, /*!< CAN Interrupt */
AnnaBridge 171:3a7713b1edbc 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
AnnaBridge 171:3a7713b1edbc 76 I2S_IRQn = 27, /*!< I2S Interrupt */
AnnaBridge 171:3a7713b1edbc 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
AnnaBridge 171:3a7713b1edbc 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
AnnaBridge 171:3a7713b1edbc 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
AnnaBridge 171:3a7713b1edbc 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
AnnaBridge 171:3a7713b1edbc 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
AnnaBridge 171:3a7713b1edbc 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
AnnaBridge 171:3a7713b1edbc 84 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86
AnnaBridge 171:3a7713b1edbc 87 /*
AnnaBridge 171:3a7713b1edbc 88 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 89 * ----------- Processor and Core Peripheral Section ------------------------
AnnaBridge 171:3a7713b1edbc 90 * ==========================================================================
AnnaBridge 171:3a7713b1edbc 91 */
AnnaBridge 171:3a7713b1edbc 92
AnnaBridge 171:3a7713b1edbc 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
AnnaBridge 171:3a7713b1edbc 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 97
AnnaBridge 171:3a7713b1edbc 98
AnnaBridge 171:3a7713b1edbc 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 100 #include "system_LPC17xx.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 101
AnnaBridge 171:3a7713b1edbc 102
AnnaBridge 171:3a7713b1edbc 103 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 104 /* Device Specific Peripheral registers structures */
AnnaBridge 171:3a7713b1edbc 105 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 108 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 109 #endif
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /*------------- System Control (SC) ------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 112 typedef struct
AnnaBridge 171:3a7713b1edbc 113 {
AnnaBridge 171:3a7713b1edbc 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
AnnaBridge 171:3a7713b1edbc 115 uint32_t RESERVED0[31];
AnnaBridge 171:3a7713b1edbc 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
AnnaBridge 171:3a7713b1edbc 117 __IO uint32_t PLL0CFG;
AnnaBridge 171:3a7713b1edbc 118 __I uint32_t PLL0STAT;
AnnaBridge 171:3a7713b1edbc 119 __O uint32_t PLL0FEED;
AnnaBridge 171:3a7713b1edbc 120 uint32_t RESERVED1[4];
AnnaBridge 171:3a7713b1edbc 121 __IO uint32_t PLL1CON;
AnnaBridge 171:3a7713b1edbc 122 __IO uint32_t PLL1CFG;
AnnaBridge 171:3a7713b1edbc 123 __I uint32_t PLL1STAT;
AnnaBridge 171:3a7713b1edbc 124 __O uint32_t PLL1FEED;
AnnaBridge 171:3a7713b1edbc 125 uint32_t RESERVED2[4];
AnnaBridge 171:3a7713b1edbc 126 __IO uint32_t PCON;
AnnaBridge 171:3a7713b1edbc 127 __IO uint32_t PCONP;
AnnaBridge 171:3a7713b1edbc 128 uint32_t RESERVED3[15];
AnnaBridge 171:3a7713b1edbc 129 __IO uint32_t CCLKCFG;
AnnaBridge 171:3a7713b1edbc 130 __IO uint32_t USBCLKCFG;
AnnaBridge 171:3a7713b1edbc 131 __IO uint32_t CLKSRCSEL;
AnnaBridge 171:3a7713b1edbc 132 __IO uint32_t CANSLEEPCLR;
AnnaBridge 171:3a7713b1edbc 133 __IO uint32_t CANWAKEFLAGS;
AnnaBridge 171:3a7713b1edbc 134 uint32_t RESERVED4[10];
AnnaBridge 171:3a7713b1edbc 135 __IO uint32_t EXTINT; /* External Interrupts */
AnnaBridge 171:3a7713b1edbc 136 uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 137 __IO uint32_t EXTMODE;
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t EXTPOLAR;
AnnaBridge 171:3a7713b1edbc 139 uint32_t RESERVED6[12];
AnnaBridge 171:3a7713b1edbc 140 __IO uint32_t RSID; /* Reset */
AnnaBridge 171:3a7713b1edbc 141 uint32_t RESERVED7[7];
AnnaBridge 171:3a7713b1edbc 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
AnnaBridge 171:3a7713b1edbc 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t PCLKSEL0;
AnnaBridge 171:3a7713b1edbc 145 __IO uint32_t PCLKSEL1;
AnnaBridge 171:3a7713b1edbc 146 uint32_t RESERVED8[4];
AnnaBridge 171:3a7713b1edbc 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
AnnaBridge 171:3a7713b1edbc 148 __IO uint32_t DMAREQSEL;
AnnaBridge 171:3a7713b1edbc 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
AnnaBridge 171:3a7713b1edbc 150 } LPC_SC_TypeDef;
AnnaBridge 171:3a7713b1edbc 151
AnnaBridge 171:3a7713b1edbc 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 153 typedef struct
AnnaBridge 171:3a7713b1edbc 154 {
AnnaBridge 171:3a7713b1edbc 155 __IO uint32_t PINSEL0;
AnnaBridge 171:3a7713b1edbc 156 __IO uint32_t PINSEL1;
AnnaBridge 171:3a7713b1edbc 157 __IO uint32_t PINSEL2;
AnnaBridge 171:3a7713b1edbc 158 __IO uint32_t PINSEL3;
AnnaBridge 171:3a7713b1edbc 159 __IO uint32_t PINSEL4;
AnnaBridge 171:3a7713b1edbc 160 __IO uint32_t PINSEL5;
AnnaBridge 171:3a7713b1edbc 161 __IO uint32_t PINSEL6;
AnnaBridge 171:3a7713b1edbc 162 __IO uint32_t PINSEL7;
AnnaBridge 171:3a7713b1edbc 163 __IO uint32_t PINSEL8;
AnnaBridge 171:3a7713b1edbc 164 __IO uint32_t PINSEL9;
AnnaBridge 171:3a7713b1edbc 165 __IO uint32_t PINSEL10;
AnnaBridge 171:3a7713b1edbc 166 uint32_t RESERVED0[5];
AnnaBridge 171:3a7713b1edbc 167 __IO uint32_t PINMODE0;
AnnaBridge 171:3a7713b1edbc 168 __IO uint32_t PINMODE1;
AnnaBridge 171:3a7713b1edbc 169 __IO uint32_t PINMODE2;
AnnaBridge 171:3a7713b1edbc 170 __IO uint32_t PINMODE3;
AnnaBridge 171:3a7713b1edbc 171 __IO uint32_t PINMODE4;
AnnaBridge 171:3a7713b1edbc 172 __IO uint32_t PINMODE5;
AnnaBridge 171:3a7713b1edbc 173 __IO uint32_t PINMODE6;
AnnaBridge 171:3a7713b1edbc 174 __IO uint32_t PINMODE7;
AnnaBridge 171:3a7713b1edbc 175 __IO uint32_t PINMODE8;
AnnaBridge 171:3a7713b1edbc 176 __IO uint32_t PINMODE9;
AnnaBridge 171:3a7713b1edbc 177 __IO uint32_t PINMODE_OD0;
AnnaBridge 171:3a7713b1edbc 178 __IO uint32_t PINMODE_OD1;
AnnaBridge 171:3a7713b1edbc 179 __IO uint32_t PINMODE_OD2;
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t PINMODE_OD3;
AnnaBridge 171:3a7713b1edbc 181 __IO uint32_t PINMODE_OD4;
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t I2CPADCFG;
AnnaBridge 171:3a7713b1edbc 183 } LPC_PINCON_TypeDef;
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
AnnaBridge 171:3a7713b1edbc 186 typedef struct
AnnaBridge 171:3a7713b1edbc 187 {
AnnaBridge 171:3a7713b1edbc 188 union {
AnnaBridge 171:3a7713b1edbc 189 __IO uint32_t FIODIR;
AnnaBridge 171:3a7713b1edbc 190 struct {
AnnaBridge 171:3a7713b1edbc 191 __IO uint16_t FIODIRL;
AnnaBridge 171:3a7713b1edbc 192 __IO uint16_t FIODIRH;
AnnaBridge 171:3a7713b1edbc 193 };
AnnaBridge 171:3a7713b1edbc 194 struct {
AnnaBridge 171:3a7713b1edbc 195 __IO uint8_t FIODIR0;
AnnaBridge 171:3a7713b1edbc 196 __IO uint8_t FIODIR1;
AnnaBridge 171:3a7713b1edbc 197 __IO uint8_t FIODIR2;
AnnaBridge 171:3a7713b1edbc 198 __IO uint8_t FIODIR3;
AnnaBridge 171:3a7713b1edbc 199 };
AnnaBridge 171:3a7713b1edbc 200 };
AnnaBridge 171:3a7713b1edbc 201 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 202 union {
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t FIOMASK;
AnnaBridge 171:3a7713b1edbc 204 struct {
AnnaBridge 171:3a7713b1edbc 205 __IO uint16_t FIOMASKL;
AnnaBridge 171:3a7713b1edbc 206 __IO uint16_t FIOMASKH;
AnnaBridge 171:3a7713b1edbc 207 };
AnnaBridge 171:3a7713b1edbc 208 struct {
AnnaBridge 171:3a7713b1edbc 209 __IO uint8_t FIOMASK0;
AnnaBridge 171:3a7713b1edbc 210 __IO uint8_t FIOMASK1;
AnnaBridge 171:3a7713b1edbc 211 __IO uint8_t FIOMASK2;
AnnaBridge 171:3a7713b1edbc 212 __IO uint8_t FIOMASK3;
AnnaBridge 171:3a7713b1edbc 213 };
AnnaBridge 171:3a7713b1edbc 214 };
AnnaBridge 171:3a7713b1edbc 215 union {
AnnaBridge 171:3a7713b1edbc 216 __IO uint32_t FIOPIN;
AnnaBridge 171:3a7713b1edbc 217 struct {
AnnaBridge 171:3a7713b1edbc 218 __IO uint16_t FIOPINL;
AnnaBridge 171:3a7713b1edbc 219 __IO uint16_t FIOPINH;
AnnaBridge 171:3a7713b1edbc 220 };
AnnaBridge 171:3a7713b1edbc 221 struct {
AnnaBridge 171:3a7713b1edbc 222 __IO uint8_t FIOPIN0;
AnnaBridge 171:3a7713b1edbc 223 __IO uint8_t FIOPIN1;
AnnaBridge 171:3a7713b1edbc 224 __IO uint8_t FIOPIN2;
AnnaBridge 171:3a7713b1edbc 225 __IO uint8_t FIOPIN3;
AnnaBridge 171:3a7713b1edbc 226 };
AnnaBridge 171:3a7713b1edbc 227 };
AnnaBridge 171:3a7713b1edbc 228 union {
AnnaBridge 171:3a7713b1edbc 229 __IO uint32_t FIOSET;
AnnaBridge 171:3a7713b1edbc 230 struct {
AnnaBridge 171:3a7713b1edbc 231 __IO uint16_t FIOSETL;
AnnaBridge 171:3a7713b1edbc 232 __IO uint16_t FIOSETH;
AnnaBridge 171:3a7713b1edbc 233 };
AnnaBridge 171:3a7713b1edbc 234 struct {
AnnaBridge 171:3a7713b1edbc 235 __IO uint8_t FIOSET0;
AnnaBridge 171:3a7713b1edbc 236 __IO uint8_t FIOSET1;
AnnaBridge 171:3a7713b1edbc 237 __IO uint8_t FIOSET2;
AnnaBridge 171:3a7713b1edbc 238 __IO uint8_t FIOSET3;
AnnaBridge 171:3a7713b1edbc 239 };
AnnaBridge 171:3a7713b1edbc 240 };
AnnaBridge 171:3a7713b1edbc 241 union {
AnnaBridge 171:3a7713b1edbc 242 __O uint32_t FIOCLR;
AnnaBridge 171:3a7713b1edbc 243 struct {
AnnaBridge 171:3a7713b1edbc 244 __O uint16_t FIOCLRL;
AnnaBridge 171:3a7713b1edbc 245 __O uint16_t FIOCLRH;
AnnaBridge 171:3a7713b1edbc 246 };
AnnaBridge 171:3a7713b1edbc 247 struct {
AnnaBridge 171:3a7713b1edbc 248 __O uint8_t FIOCLR0;
AnnaBridge 171:3a7713b1edbc 249 __O uint8_t FIOCLR1;
AnnaBridge 171:3a7713b1edbc 250 __O uint8_t FIOCLR2;
AnnaBridge 171:3a7713b1edbc 251 __O uint8_t FIOCLR3;
AnnaBridge 171:3a7713b1edbc 252 };
AnnaBridge 171:3a7713b1edbc 253 };
AnnaBridge 171:3a7713b1edbc 254 } LPC_GPIO_TypeDef;
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 typedef struct
AnnaBridge 171:3a7713b1edbc 257 {
AnnaBridge 171:3a7713b1edbc 258 __I uint32_t IntStatus;
AnnaBridge 171:3a7713b1edbc 259 __I uint32_t IO0IntStatR;
AnnaBridge 171:3a7713b1edbc 260 __I uint32_t IO0IntStatF;
AnnaBridge 171:3a7713b1edbc 261 __O uint32_t IO0IntClr;
AnnaBridge 171:3a7713b1edbc 262 __IO uint32_t IO0IntEnR;
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t IO0IntEnF;
AnnaBridge 171:3a7713b1edbc 264 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 265 __I uint32_t IO2IntStatR;
AnnaBridge 171:3a7713b1edbc 266 __I uint32_t IO2IntStatF;
AnnaBridge 171:3a7713b1edbc 267 __O uint32_t IO2IntClr;
AnnaBridge 171:3a7713b1edbc 268 __IO uint32_t IO2IntEnR;
AnnaBridge 171:3a7713b1edbc 269 __IO uint32_t IO2IntEnF;
AnnaBridge 171:3a7713b1edbc 270 } LPC_GPIOINT_TypeDef;
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /*------------- Timer (TIM) --------------------------------------------------*/
AnnaBridge 171:3a7713b1edbc 273 typedef struct
AnnaBridge 171:3a7713b1edbc 274 {
AnnaBridge 171:3a7713b1edbc 275 __IO uint32_t IR;
AnnaBridge 171:3a7713b1edbc 276 __IO uint32_t TCR;
AnnaBridge 171:3a7713b1edbc 277 __IO uint32_t TC;
AnnaBridge 171:3a7713b1edbc 278 __IO uint32_t PR;
AnnaBridge 171:3a7713b1edbc 279 __IO uint32_t PC;
AnnaBridge 171:3a7713b1edbc 280 __IO uint32_t MCR;
AnnaBridge 171:3a7713b1edbc 281 __IO uint32_t MR0;
AnnaBridge 171:3a7713b1edbc 282 __IO uint32_t MR1;
AnnaBridge 171:3a7713b1edbc 283 __IO uint32_t MR2;
AnnaBridge 171:3a7713b1edbc 284 __IO uint32_t MR3;
AnnaBridge 171:3a7713b1edbc 285 __IO uint32_t CCR;
AnnaBridge 171:3a7713b1edbc 286 __I uint32_t CR0;
AnnaBridge 171:3a7713b1edbc 287 __I uint32_t CR1;
AnnaBridge 171:3a7713b1edbc 288 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 289 __IO uint32_t EMR;
AnnaBridge 171:3a7713b1edbc 290 uint32_t RESERVED1[12];
AnnaBridge 171:3a7713b1edbc 291 __IO uint32_t CTCR;
AnnaBridge 171:3a7713b1edbc 292 } LPC_TIM_TypeDef;
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
AnnaBridge 171:3a7713b1edbc 295 typedef struct
AnnaBridge 171:3a7713b1edbc 296 {
AnnaBridge 171:3a7713b1edbc 297 __IO uint32_t IR;
AnnaBridge 171:3a7713b1edbc 298 __IO uint32_t TCR;
AnnaBridge 171:3a7713b1edbc 299 __IO uint32_t TC;
AnnaBridge 171:3a7713b1edbc 300 __IO uint32_t PR;
AnnaBridge 171:3a7713b1edbc 301 __IO uint32_t PC;
AnnaBridge 171:3a7713b1edbc 302 __IO uint32_t MCR;
AnnaBridge 171:3a7713b1edbc 303 __IO uint32_t MR0;
AnnaBridge 171:3a7713b1edbc 304 __IO uint32_t MR1;
AnnaBridge 171:3a7713b1edbc 305 __IO uint32_t MR2;
AnnaBridge 171:3a7713b1edbc 306 __IO uint32_t MR3;
AnnaBridge 171:3a7713b1edbc 307 __IO uint32_t CCR;
AnnaBridge 171:3a7713b1edbc 308 __I uint32_t CR0;
AnnaBridge 171:3a7713b1edbc 309 __I uint32_t CR1;
AnnaBridge 171:3a7713b1edbc 310 __I uint32_t CR2;
AnnaBridge 171:3a7713b1edbc 311 __I uint32_t CR3;
AnnaBridge 171:3a7713b1edbc 312 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t MR4;
AnnaBridge 171:3a7713b1edbc 314 __IO uint32_t MR5;
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t MR6;
AnnaBridge 171:3a7713b1edbc 316 __IO uint32_t PCR;
AnnaBridge 171:3a7713b1edbc 317 __IO uint32_t LER;
AnnaBridge 171:3a7713b1edbc 318 uint32_t RESERVED1[7];
AnnaBridge 171:3a7713b1edbc 319 __IO uint32_t CTCR;
AnnaBridge 171:3a7713b1edbc 320 } LPC_PWM_TypeDef;
AnnaBridge 171:3a7713b1edbc 321
AnnaBridge 171:3a7713b1edbc 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
AnnaBridge 171:3a7713b1edbc 323 typedef struct
AnnaBridge 171:3a7713b1edbc 324 {
AnnaBridge 171:3a7713b1edbc 325 union {
AnnaBridge 171:3a7713b1edbc 326 __I uint8_t RBR;
AnnaBridge 171:3a7713b1edbc 327 __O uint8_t THR;
AnnaBridge 171:3a7713b1edbc 328 __IO uint8_t DLL;
AnnaBridge 171:3a7713b1edbc 329 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 330 };
AnnaBridge 171:3a7713b1edbc 331 union {
AnnaBridge 171:3a7713b1edbc 332 __IO uint8_t DLM;
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 334 };
AnnaBridge 171:3a7713b1edbc 335 union {
AnnaBridge 171:3a7713b1edbc 336 __I uint32_t IIR;
AnnaBridge 171:3a7713b1edbc 337 __O uint8_t FCR;
AnnaBridge 171:3a7713b1edbc 338 };
AnnaBridge 171:3a7713b1edbc 339 __IO uint8_t LCR;
AnnaBridge 171:3a7713b1edbc 340 uint8_t RESERVED1[7];
AnnaBridge 171:3a7713b1edbc 341 __I uint8_t LSR;
AnnaBridge 171:3a7713b1edbc 342 uint8_t RESERVED2[7];
AnnaBridge 171:3a7713b1edbc 343 __IO uint8_t SCR;
AnnaBridge 171:3a7713b1edbc 344 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t ACR;
AnnaBridge 171:3a7713b1edbc 346 __IO uint8_t ICR;
AnnaBridge 171:3a7713b1edbc 347 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 348 __IO uint8_t FDR;
AnnaBridge 171:3a7713b1edbc 349 uint8_t RESERVED5[7];
AnnaBridge 171:3a7713b1edbc 350 __IO uint8_t TER;
AnnaBridge 171:3a7713b1edbc 351 uint8_t RESERVED6[39];
AnnaBridge 171:3a7713b1edbc 352 __IO uint32_t FIFOLVL;
AnnaBridge 171:3a7713b1edbc 353 } LPC_UART_TypeDef;
AnnaBridge 171:3a7713b1edbc 354
AnnaBridge 171:3a7713b1edbc 355 typedef struct
AnnaBridge 171:3a7713b1edbc 356 {
AnnaBridge 171:3a7713b1edbc 357 union {
AnnaBridge 171:3a7713b1edbc 358 __I uint8_t RBR;
AnnaBridge 171:3a7713b1edbc 359 __O uint8_t THR;
AnnaBridge 171:3a7713b1edbc 360 __IO uint8_t DLL;
AnnaBridge 171:3a7713b1edbc 361 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 362 };
AnnaBridge 171:3a7713b1edbc 363 union {
AnnaBridge 171:3a7713b1edbc 364 __IO uint8_t DLM;
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 366 };
AnnaBridge 171:3a7713b1edbc 367 union {
AnnaBridge 171:3a7713b1edbc 368 __I uint32_t IIR;
AnnaBridge 171:3a7713b1edbc 369 __O uint8_t FCR;
AnnaBridge 171:3a7713b1edbc 370 };
AnnaBridge 171:3a7713b1edbc 371 __IO uint8_t LCR;
AnnaBridge 171:3a7713b1edbc 372 uint8_t RESERVED1[7];
AnnaBridge 171:3a7713b1edbc 373 __I uint8_t LSR;
AnnaBridge 171:3a7713b1edbc 374 uint8_t RESERVED2[7];
AnnaBridge 171:3a7713b1edbc 375 __IO uint8_t SCR;
AnnaBridge 171:3a7713b1edbc 376 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 377 __IO uint32_t ACR;
AnnaBridge 171:3a7713b1edbc 378 __IO uint8_t ICR;
AnnaBridge 171:3a7713b1edbc 379 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 380 __IO uint8_t FDR;
AnnaBridge 171:3a7713b1edbc 381 uint8_t RESERVED5[7];
AnnaBridge 171:3a7713b1edbc 382 __IO uint8_t TER;
AnnaBridge 171:3a7713b1edbc 383 uint8_t RESERVED6[39];
AnnaBridge 171:3a7713b1edbc 384 __IO uint32_t FIFOLVL;
AnnaBridge 171:3a7713b1edbc 385 } LPC_UART0_TypeDef;
AnnaBridge 171:3a7713b1edbc 386
AnnaBridge 171:3a7713b1edbc 387 typedef struct
AnnaBridge 171:3a7713b1edbc 388 {
AnnaBridge 171:3a7713b1edbc 389 union {
AnnaBridge 171:3a7713b1edbc 390 __I uint8_t RBR;
AnnaBridge 171:3a7713b1edbc 391 __O uint8_t THR;
AnnaBridge 171:3a7713b1edbc 392 __IO uint8_t DLL;
AnnaBridge 171:3a7713b1edbc 393 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 394 };
AnnaBridge 171:3a7713b1edbc 395 union {
AnnaBridge 171:3a7713b1edbc 396 __IO uint8_t DLM;
AnnaBridge 171:3a7713b1edbc 397 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 398 };
AnnaBridge 171:3a7713b1edbc 399 union {
AnnaBridge 171:3a7713b1edbc 400 __I uint32_t IIR;
AnnaBridge 171:3a7713b1edbc 401 __O uint8_t FCR;
AnnaBridge 171:3a7713b1edbc 402 };
AnnaBridge 171:3a7713b1edbc 403 __IO uint8_t LCR;
AnnaBridge 171:3a7713b1edbc 404 uint8_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 405 __IO uint8_t MCR;
AnnaBridge 171:3a7713b1edbc 406 uint8_t RESERVED2[3];
AnnaBridge 171:3a7713b1edbc 407 __I uint8_t LSR;
AnnaBridge 171:3a7713b1edbc 408 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 409 __I uint8_t MSR;
AnnaBridge 171:3a7713b1edbc 410 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 411 __IO uint8_t SCR;
AnnaBridge 171:3a7713b1edbc 412 uint8_t RESERVED5[3];
AnnaBridge 171:3a7713b1edbc 413 __IO uint32_t ACR;
AnnaBridge 171:3a7713b1edbc 414 uint32_t RESERVED6;
AnnaBridge 171:3a7713b1edbc 415 __IO uint32_t FDR;
AnnaBridge 171:3a7713b1edbc 416 uint32_t RESERVED7;
AnnaBridge 171:3a7713b1edbc 417 __IO uint8_t TER;
AnnaBridge 171:3a7713b1edbc 418 uint8_t RESERVED8[27];
AnnaBridge 171:3a7713b1edbc 419 __IO uint8_t RS485CTRL;
AnnaBridge 171:3a7713b1edbc 420 uint8_t RESERVED9[3];
AnnaBridge 171:3a7713b1edbc 421 __IO uint8_t ADRMATCH;
AnnaBridge 171:3a7713b1edbc 422 uint8_t RESERVED10[3];
AnnaBridge 171:3a7713b1edbc 423 __IO uint8_t RS485DLY;
AnnaBridge 171:3a7713b1edbc 424 uint8_t RESERVED11[3];
AnnaBridge 171:3a7713b1edbc 425 __IO uint32_t FIFOLVL;
AnnaBridge 171:3a7713b1edbc 426 } LPC_UART1_TypeDef;
AnnaBridge 171:3a7713b1edbc 427
AnnaBridge 171:3a7713b1edbc 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
AnnaBridge 171:3a7713b1edbc 429 typedef struct
AnnaBridge 171:3a7713b1edbc 430 {
AnnaBridge 171:3a7713b1edbc 431 __IO uint32_t SPCR;
AnnaBridge 171:3a7713b1edbc 432 __I uint32_t SPSR;
AnnaBridge 171:3a7713b1edbc 433 __IO uint32_t SPDR;
AnnaBridge 171:3a7713b1edbc 434 __IO uint32_t SPCCR;
AnnaBridge 171:3a7713b1edbc 435 uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 436 __IO uint32_t SPINT;
AnnaBridge 171:3a7713b1edbc 437 } LPC_SPI_TypeDef;
AnnaBridge 171:3a7713b1edbc 438
AnnaBridge 171:3a7713b1edbc 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
AnnaBridge 171:3a7713b1edbc 440 typedef struct
AnnaBridge 171:3a7713b1edbc 441 {
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t CR0;
AnnaBridge 171:3a7713b1edbc 443 __IO uint32_t CR1;
AnnaBridge 171:3a7713b1edbc 444 __IO uint32_t DR;
AnnaBridge 171:3a7713b1edbc 445 __I uint32_t SR;
AnnaBridge 171:3a7713b1edbc 446 __IO uint32_t CPSR;
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t IMSC;
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t RIS;
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t MIS;
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t ICR;
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t DMACR;
AnnaBridge 171:3a7713b1edbc 452 } LPC_SSP_TypeDef;
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
AnnaBridge 171:3a7713b1edbc 455 typedef struct
AnnaBridge 171:3a7713b1edbc 456 {
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t I2CONSET;
AnnaBridge 171:3a7713b1edbc 458 __I uint32_t I2STAT;
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t I2DAT;
AnnaBridge 171:3a7713b1edbc 460 __IO uint32_t I2ADR0;
AnnaBridge 171:3a7713b1edbc 461 __IO uint32_t I2SCLH;
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t I2SCLL;
AnnaBridge 171:3a7713b1edbc 463 __O uint32_t I2CONCLR;
AnnaBridge 171:3a7713b1edbc 464 __IO uint32_t MMCTRL;
AnnaBridge 171:3a7713b1edbc 465 __IO uint32_t I2ADR1;
AnnaBridge 171:3a7713b1edbc 466 __IO uint32_t I2ADR2;
AnnaBridge 171:3a7713b1edbc 467 __IO uint32_t I2ADR3;
AnnaBridge 171:3a7713b1edbc 468 __I uint32_t I2DATA_BUFFER;
AnnaBridge 171:3a7713b1edbc 469 __IO uint32_t I2MASK0;
AnnaBridge 171:3a7713b1edbc 470 __IO uint32_t I2MASK1;
AnnaBridge 171:3a7713b1edbc 471 __IO uint32_t I2MASK2;
AnnaBridge 171:3a7713b1edbc 472 __IO uint32_t I2MASK3;
AnnaBridge 171:3a7713b1edbc 473 } LPC_I2C_TypeDef;
AnnaBridge 171:3a7713b1edbc 474
AnnaBridge 171:3a7713b1edbc 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 476 typedef struct
AnnaBridge 171:3a7713b1edbc 477 {
AnnaBridge 171:3a7713b1edbc 478 __IO uint32_t I2SDAO;
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t I2SDAI;
AnnaBridge 171:3a7713b1edbc 480 __O uint32_t I2STXFIFO;
AnnaBridge 171:3a7713b1edbc 481 __I uint32_t I2SRXFIFO;
AnnaBridge 171:3a7713b1edbc 482 __I uint32_t I2SSTATE;
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t I2SDMA1;
AnnaBridge 171:3a7713b1edbc 484 __IO uint32_t I2SDMA2;
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t I2SIRQ;
AnnaBridge 171:3a7713b1edbc 486 __IO uint32_t I2STXRATE;
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t I2SRXRATE;
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t I2STXBITRATE;
AnnaBridge 171:3a7713b1edbc 489 __IO uint32_t I2SRXBITRATE;
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t I2STXMODE;
AnnaBridge 171:3a7713b1edbc 491 __IO uint32_t I2SRXMODE;
AnnaBridge 171:3a7713b1edbc 492 } LPC_I2S_TypeDef;
AnnaBridge 171:3a7713b1edbc 493
AnnaBridge 171:3a7713b1edbc 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
AnnaBridge 171:3a7713b1edbc 495 typedef struct
AnnaBridge 171:3a7713b1edbc 496 {
AnnaBridge 171:3a7713b1edbc 497 __IO uint32_t RICOMPVAL;
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t RIMASK;
AnnaBridge 171:3a7713b1edbc 499 __IO uint8_t RICTRL;
AnnaBridge 171:3a7713b1edbc 500 uint8_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 501 __IO uint32_t RICOUNTER;
AnnaBridge 171:3a7713b1edbc 502 } LPC_RIT_TypeDef;
AnnaBridge 171:3a7713b1edbc 503
AnnaBridge 171:3a7713b1edbc 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 505 typedef struct
AnnaBridge 171:3a7713b1edbc 506 {
AnnaBridge 171:3a7713b1edbc 507 __IO uint8_t ILR;
AnnaBridge 171:3a7713b1edbc 508 uint8_t RESERVED0[7];
AnnaBridge 171:3a7713b1edbc 509 __IO uint8_t CCR;
AnnaBridge 171:3a7713b1edbc 510 uint8_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 511 __IO uint8_t CIIR;
AnnaBridge 171:3a7713b1edbc 512 uint8_t RESERVED2[3];
AnnaBridge 171:3a7713b1edbc 513 __IO uint8_t AMR;
AnnaBridge 171:3a7713b1edbc 514 uint8_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 515 __I uint32_t CTIME0;
AnnaBridge 171:3a7713b1edbc 516 __I uint32_t CTIME1;
AnnaBridge 171:3a7713b1edbc 517 __I uint32_t CTIME2;
AnnaBridge 171:3a7713b1edbc 518 __IO uint8_t SEC;
AnnaBridge 171:3a7713b1edbc 519 uint8_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 520 __IO uint8_t MIN;
AnnaBridge 171:3a7713b1edbc 521 uint8_t RESERVED5[3];
AnnaBridge 171:3a7713b1edbc 522 __IO uint8_t HOUR;
AnnaBridge 171:3a7713b1edbc 523 uint8_t RESERVED6[3];
AnnaBridge 171:3a7713b1edbc 524 __IO uint8_t DOM;
AnnaBridge 171:3a7713b1edbc 525 uint8_t RESERVED7[3];
AnnaBridge 171:3a7713b1edbc 526 __IO uint8_t DOW;
AnnaBridge 171:3a7713b1edbc 527 uint8_t RESERVED8[3];
AnnaBridge 171:3a7713b1edbc 528 __IO uint16_t DOY;
AnnaBridge 171:3a7713b1edbc 529 uint16_t RESERVED9;
AnnaBridge 171:3a7713b1edbc 530 __IO uint8_t MONTH;
AnnaBridge 171:3a7713b1edbc 531 uint8_t RESERVED10[3];
AnnaBridge 171:3a7713b1edbc 532 __IO uint16_t YEAR;
AnnaBridge 171:3a7713b1edbc 533 uint16_t RESERVED11;
AnnaBridge 171:3a7713b1edbc 534 __IO uint32_t CALIBRATION;
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t GPREG0;
AnnaBridge 171:3a7713b1edbc 536 __IO uint32_t GPREG1;
AnnaBridge 171:3a7713b1edbc 537 __IO uint32_t GPREG2;
AnnaBridge 171:3a7713b1edbc 538 __IO uint32_t GPREG3;
AnnaBridge 171:3a7713b1edbc 539 __IO uint32_t GPREG4;
AnnaBridge 171:3a7713b1edbc 540 __IO uint8_t RTC_AUXEN;
AnnaBridge 171:3a7713b1edbc 541 uint8_t RESERVED12[3];
AnnaBridge 171:3a7713b1edbc 542 __IO uint8_t RTC_AUX;
AnnaBridge 171:3a7713b1edbc 543 uint8_t RESERVED13[3];
AnnaBridge 171:3a7713b1edbc 544 __IO uint8_t ALSEC;
AnnaBridge 171:3a7713b1edbc 545 uint8_t RESERVED14[3];
AnnaBridge 171:3a7713b1edbc 546 __IO uint8_t ALMIN;
AnnaBridge 171:3a7713b1edbc 547 uint8_t RESERVED15[3];
AnnaBridge 171:3a7713b1edbc 548 __IO uint8_t ALHOUR;
AnnaBridge 171:3a7713b1edbc 549 uint8_t RESERVED16[3];
AnnaBridge 171:3a7713b1edbc 550 __IO uint8_t ALDOM;
AnnaBridge 171:3a7713b1edbc 551 uint8_t RESERVED17[3];
AnnaBridge 171:3a7713b1edbc 552 __IO uint8_t ALDOW;
AnnaBridge 171:3a7713b1edbc 553 uint8_t RESERVED18[3];
AnnaBridge 171:3a7713b1edbc 554 __IO uint16_t ALDOY;
AnnaBridge 171:3a7713b1edbc 555 uint16_t RESERVED19;
AnnaBridge 171:3a7713b1edbc 556 __IO uint8_t ALMON;
AnnaBridge 171:3a7713b1edbc 557 uint8_t RESERVED20[3];
AnnaBridge 171:3a7713b1edbc 558 __IO uint16_t ALYEAR;
AnnaBridge 171:3a7713b1edbc 559 uint16_t RESERVED21;
AnnaBridge 171:3a7713b1edbc 560 } LPC_RTC_TypeDef;
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
AnnaBridge 171:3a7713b1edbc 563 typedef struct
AnnaBridge 171:3a7713b1edbc 564 {
AnnaBridge 171:3a7713b1edbc 565 __IO uint8_t WDMOD;
AnnaBridge 171:3a7713b1edbc 566 uint8_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 567 __IO uint32_t WDTC;
AnnaBridge 171:3a7713b1edbc 568 __O uint8_t WDFEED;
AnnaBridge 171:3a7713b1edbc 569 uint8_t RESERVED1[3];
AnnaBridge 171:3a7713b1edbc 570 __I uint32_t WDTV;
AnnaBridge 171:3a7713b1edbc 571 __IO uint32_t WDCLKSEL;
AnnaBridge 171:3a7713b1edbc 572 } LPC_WDT_TypeDef;
AnnaBridge 171:3a7713b1edbc 573
AnnaBridge 171:3a7713b1edbc 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
AnnaBridge 171:3a7713b1edbc 575 typedef struct
AnnaBridge 171:3a7713b1edbc 576 {
AnnaBridge 171:3a7713b1edbc 577 __IO uint32_t ADCR;
AnnaBridge 171:3a7713b1edbc 578 __IO uint32_t ADGDR;
AnnaBridge 171:3a7713b1edbc 579 uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 580 __IO uint32_t ADINTEN;
AnnaBridge 171:3a7713b1edbc 581 __I uint32_t ADDR0;
AnnaBridge 171:3a7713b1edbc 582 __I uint32_t ADDR1;
AnnaBridge 171:3a7713b1edbc 583 __I uint32_t ADDR2;
AnnaBridge 171:3a7713b1edbc 584 __I uint32_t ADDR3;
AnnaBridge 171:3a7713b1edbc 585 __I uint32_t ADDR4;
AnnaBridge 171:3a7713b1edbc 586 __I uint32_t ADDR5;
AnnaBridge 171:3a7713b1edbc 587 __I uint32_t ADDR6;
AnnaBridge 171:3a7713b1edbc 588 __I uint32_t ADDR7;
AnnaBridge 171:3a7713b1edbc 589 __I uint32_t ADSTAT;
AnnaBridge 171:3a7713b1edbc 590 __IO uint32_t ADTRM;
AnnaBridge 171:3a7713b1edbc 591 } LPC_ADC_TypeDef;
AnnaBridge 171:3a7713b1edbc 592
AnnaBridge 171:3a7713b1edbc 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
AnnaBridge 171:3a7713b1edbc 594 typedef struct
AnnaBridge 171:3a7713b1edbc 595 {
AnnaBridge 171:3a7713b1edbc 596 __IO uint32_t DACR;
AnnaBridge 171:3a7713b1edbc 597 __IO uint32_t DACCTRL;
AnnaBridge 171:3a7713b1edbc 598 __IO uint16_t DACCNTVAL;
AnnaBridge 171:3a7713b1edbc 599 } LPC_DAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 600
AnnaBridge 171:3a7713b1edbc 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
AnnaBridge 171:3a7713b1edbc 602 typedef struct
AnnaBridge 171:3a7713b1edbc 603 {
AnnaBridge 171:3a7713b1edbc 604 __I uint32_t MCCON;
AnnaBridge 171:3a7713b1edbc 605 __O uint32_t MCCON_SET;
AnnaBridge 171:3a7713b1edbc 606 __O uint32_t MCCON_CLR;
AnnaBridge 171:3a7713b1edbc 607 __I uint32_t MCCAPCON;
AnnaBridge 171:3a7713b1edbc 608 __O uint32_t MCCAPCON_SET;
AnnaBridge 171:3a7713b1edbc 609 __O uint32_t MCCAPCON_CLR;
AnnaBridge 171:3a7713b1edbc 610 __IO uint32_t MCTIM0;
AnnaBridge 171:3a7713b1edbc 611 __IO uint32_t MCTIM1;
AnnaBridge 171:3a7713b1edbc 612 __IO uint32_t MCTIM2;
AnnaBridge 171:3a7713b1edbc 613 __IO uint32_t MCPER0;
AnnaBridge 171:3a7713b1edbc 614 __IO uint32_t MCPER1;
AnnaBridge 171:3a7713b1edbc 615 __IO uint32_t MCPER2;
AnnaBridge 171:3a7713b1edbc 616 __IO uint32_t MCPW0;
AnnaBridge 171:3a7713b1edbc 617 __IO uint32_t MCPW1;
AnnaBridge 171:3a7713b1edbc 618 __IO uint32_t MCPW2;
AnnaBridge 171:3a7713b1edbc 619 __IO uint32_t MCDEADTIME;
AnnaBridge 171:3a7713b1edbc 620 __IO uint32_t MCCCP;
AnnaBridge 171:3a7713b1edbc 621 __IO uint32_t MCCR0;
AnnaBridge 171:3a7713b1edbc 622 __IO uint32_t MCCR1;
AnnaBridge 171:3a7713b1edbc 623 __IO uint32_t MCCR2;
AnnaBridge 171:3a7713b1edbc 624 __I uint32_t MCINTEN;
AnnaBridge 171:3a7713b1edbc 625 __O uint32_t MCINTEN_SET;
AnnaBridge 171:3a7713b1edbc 626 __O uint32_t MCINTEN_CLR;
AnnaBridge 171:3a7713b1edbc 627 __I uint32_t MCCNTCON;
AnnaBridge 171:3a7713b1edbc 628 __O uint32_t MCCNTCON_SET;
AnnaBridge 171:3a7713b1edbc 629 __O uint32_t MCCNTCON_CLR;
AnnaBridge 171:3a7713b1edbc 630 __I uint32_t MCINTFLAG;
AnnaBridge 171:3a7713b1edbc 631 __O uint32_t MCINTFLAG_SET;
AnnaBridge 171:3a7713b1edbc 632 __O uint32_t MCINTFLAG_CLR;
AnnaBridge 171:3a7713b1edbc 633 __O uint32_t MCCAP_CLR;
AnnaBridge 171:3a7713b1edbc 634 } LPC_MCPWM_TypeDef;
AnnaBridge 171:3a7713b1edbc 635
AnnaBridge 171:3a7713b1edbc 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
AnnaBridge 171:3a7713b1edbc 637 typedef struct
AnnaBridge 171:3a7713b1edbc 638 {
AnnaBridge 171:3a7713b1edbc 639 __O uint32_t QEICON;
AnnaBridge 171:3a7713b1edbc 640 __I uint32_t QEISTAT;
AnnaBridge 171:3a7713b1edbc 641 __IO uint32_t QEICONF;
AnnaBridge 171:3a7713b1edbc 642 __I uint32_t QEIPOS;
AnnaBridge 171:3a7713b1edbc 643 __IO uint32_t QEIMAXPOS;
AnnaBridge 171:3a7713b1edbc 644 __IO uint32_t CMPOS0;
AnnaBridge 171:3a7713b1edbc 645 __IO uint32_t CMPOS1;
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t CMPOS2;
AnnaBridge 171:3a7713b1edbc 647 __I uint32_t INXCNT;
AnnaBridge 171:3a7713b1edbc 648 __IO uint32_t INXCMP;
AnnaBridge 171:3a7713b1edbc 649 __IO uint32_t QEILOAD;
AnnaBridge 171:3a7713b1edbc 650 __I uint32_t QEITIME;
AnnaBridge 171:3a7713b1edbc 651 __I uint32_t QEIVEL;
AnnaBridge 171:3a7713b1edbc 652 __I uint32_t QEICAP;
AnnaBridge 171:3a7713b1edbc 653 __IO uint32_t VELCOMP;
AnnaBridge 171:3a7713b1edbc 654 __IO uint32_t FILTER;
AnnaBridge 171:3a7713b1edbc 655 uint32_t RESERVED0[998];
AnnaBridge 171:3a7713b1edbc 656 __O uint32_t QEIIEC;
AnnaBridge 171:3a7713b1edbc 657 __O uint32_t QEIIES;
AnnaBridge 171:3a7713b1edbc 658 __I uint32_t QEIINTSTAT;
AnnaBridge 171:3a7713b1edbc 659 __I uint32_t QEIIE;
AnnaBridge 171:3a7713b1edbc 660 __O uint32_t QEICLR;
AnnaBridge 171:3a7713b1edbc 661 __O uint32_t QEISET;
AnnaBridge 171:3a7713b1edbc 662 } LPC_QEI_TypeDef;
AnnaBridge 171:3a7713b1edbc 663
AnnaBridge 171:3a7713b1edbc 664 /*------------- Controller Area Network (CAN) --------------------------------*/
AnnaBridge 171:3a7713b1edbc 665 typedef struct
AnnaBridge 171:3a7713b1edbc 666 {
AnnaBridge 171:3a7713b1edbc 667 __IO uint32_t mask[512]; /* ID Masks */
AnnaBridge 171:3a7713b1edbc 668 } LPC_CANAF_RAM_TypeDef;
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 typedef struct /* Acceptance Filter Registers */
AnnaBridge 171:3a7713b1edbc 671 {
AnnaBridge 171:3a7713b1edbc 672 __IO uint32_t AFMR;
AnnaBridge 171:3a7713b1edbc 673 __IO uint32_t SFF_sa;
AnnaBridge 171:3a7713b1edbc 674 __IO uint32_t SFF_GRP_sa;
AnnaBridge 171:3a7713b1edbc 675 __IO uint32_t EFF_sa;
AnnaBridge 171:3a7713b1edbc 676 __IO uint32_t EFF_GRP_sa;
AnnaBridge 171:3a7713b1edbc 677 __IO uint32_t ENDofTable;
AnnaBridge 171:3a7713b1edbc 678 __I uint32_t LUTerrAd;
AnnaBridge 171:3a7713b1edbc 679 __I uint32_t LUTerr;
AnnaBridge 171:3a7713b1edbc 680 __IO uint32_t FCANIE;
AnnaBridge 171:3a7713b1edbc 681 __IO uint32_t FCANIC0;
AnnaBridge 171:3a7713b1edbc 682 __IO uint32_t FCANIC1;
AnnaBridge 171:3a7713b1edbc 683 } LPC_CANAF_TypeDef;
AnnaBridge 171:3a7713b1edbc 684
AnnaBridge 171:3a7713b1edbc 685 typedef struct /* Central Registers */
AnnaBridge 171:3a7713b1edbc 686 {
AnnaBridge 171:3a7713b1edbc 687 __I uint32_t CANTxSR;
AnnaBridge 171:3a7713b1edbc 688 __I uint32_t CANRxSR;
AnnaBridge 171:3a7713b1edbc 689 __I uint32_t CANMSR;
AnnaBridge 171:3a7713b1edbc 690 } LPC_CANCR_TypeDef;
AnnaBridge 171:3a7713b1edbc 691
AnnaBridge 171:3a7713b1edbc 692 typedef struct /* Controller Registers */
AnnaBridge 171:3a7713b1edbc 693 {
AnnaBridge 171:3a7713b1edbc 694 __IO uint32_t MOD;
AnnaBridge 171:3a7713b1edbc 695 __O uint32_t CMR;
AnnaBridge 171:3a7713b1edbc 696 __IO uint32_t GSR;
AnnaBridge 171:3a7713b1edbc 697 __I uint32_t ICR;
AnnaBridge 171:3a7713b1edbc 698 __IO uint32_t IER;
AnnaBridge 171:3a7713b1edbc 699 __IO uint32_t BTR;
AnnaBridge 171:3a7713b1edbc 700 __IO uint32_t EWL;
AnnaBridge 171:3a7713b1edbc 701 __I uint32_t SR;
AnnaBridge 171:3a7713b1edbc 702 __IO uint32_t RFS;
AnnaBridge 171:3a7713b1edbc 703 __IO uint32_t RID;
AnnaBridge 171:3a7713b1edbc 704 __IO uint32_t RDA;
AnnaBridge 171:3a7713b1edbc 705 __IO uint32_t RDB;
AnnaBridge 171:3a7713b1edbc 706 __IO uint32_t TFI1;
AnnaBridge 171:3a7713b1edbc 707 __IO uint32_t TID1;
AnnaBridge 171:3a7713b1edbc 708 __IO uint32_t TDA1;
AnnaBridge 171:3a7713b1edbc 709 __IO uint32_t TDB1;
AnnaBridge 171:3a7713b1edbc 710 __IO uint32_t TFI2;
AnnaBridge 171:3a7713b1edbc 711 __IO uint32_t TID2;
AnnaBridge 171:3a7713b1edbc 712 __IO uint32_t TDA2;
AnnaBridge 171:3a7713b1edbc 713 __IO uint32_t TDB2;
AnnaBridge 171:3a7713b1edbc 714 __IO uint32_t TFI3;
AnnaBridge 171:3a7713b1edbc 715 __IO uint32_t TID3;
AnnaBridge 171:3a7713b1edbc 716 __IO uint32_t TDA3;
AnnaBridge 171:3a7713b1edbc 717 __IO uint32_t TDB3;
AnnaBridge 171:3a7713b1edbc 718 } LPC_CAN_TypeDef;
AnnaBridge 171:3a7713b1edbc 719
AnnaBridge 171:3a7713b1edbc 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
AnnaBridge 171:3a7713b1edbc 721 typedef struct /* Common Registers */
AnnaBridge 171:3a7713b1edbc 722 {
AnnaBridge 171:3a7713b1edbc 723 __I uint32_t DMACIntStat;
AnnaBridge 171:3a7713b1edbc 724 __I uint32_t DMACIntTCStat;
AnnaBridge 171:3a7713b1edbc 725 __O uint32_t DMACIntTCClear;
AnnaBridge 171:3a7713b1edbc 726 __I uint32_t DMACIntErrStat;
AnnaBridge 171:3a7713b1edbc 727 __O uint32_t DMACIntErrClr;
AnnaBridge 171:3a7713b1edbc 728 __I uint32_t DMACRawIntTCStat;
AnnaBridge 171:3a7713b1edbc 729 __I uint32_t DMACRawIntErrStat;
AnnaBridge 171:3a7713b1edbc 730 __I uint32_t DMACEnbldChns;
AnnaBridge 171:3a7713b1edbc 731 __IO uint32_t DMACSoftBReq;
AnnaBridge 171:3a7713b1edbc 732 __IO uint32_t DMACSoftSReq;
AnnaBridge 171:3a7713b1edbc 733 __IO uint32_t DMACSoftLBReq;
AnnaBridge 171:3a7713b1edbc 734 __IO uint32_t DMACSoftLSReq;
AnnaBridge 171:3a7713b1edbc 735 __IO uint32_t DMACConfig;
AnnaBridge 171:3a7713b1edbc 736 __IO uint32_t DMACSync;
AnnaBridge 171:3a7713b1edbc 737 } LPC_GPDMA_TypeDef;
AnnaBridge 171:3a7713b1edbc 738
AnnaBridge 171:3a7713b1edbc 739 typedef struct /* Channel Registers */
AnnaBridge 171:3a7713b1edbc 740 {
AnnaBridge 171:3a7713b1edbc 741 __IO uint32_t DMACCSrcAddr;
AnnaBridge 171:3a7713b1edbc 742 __IO uint32_t DMACCDestAddr;
AnnaBridge 171:3a7713b1edbc 743 __IO uint32_t DMACCLLI;
AnnaBridge 171:3a7713b1edbc 744 __IO uint32_t DMACCControl;
AnnaBridge 171:3a7713b1edbc 745 __IO uint32_t DMACCConfig;
AnnaBridge 171:3a7713b1edbc 746 } LPC_GPDMACH_TypeDef;
AnnaBridge 171:3a7713b1edbc 747
AnnaBridge 171:3a7713b1edbc 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
AnnaBridge 171:3a7713b1edbc 749 typedef struct
AnnaBridge 171:3a7713b1edbc 750 {
AnnaBridge 171:3a7713b1edbc 751 __I uint32_t HcRevision; /* USB Host Registers */
AnnaBridge 171:3a7713b1edbc 752 __IO uint32_t HcControl;
AnnaBridge 171:3a7713b1edbc 753 __IO uint32_t HcCommandStatus;
AnnaBridge 171:3a7713b1edbc 754 __IO uint32_t HcInterruptStatus;
AnnaBridge 171:3a7713b1edbc 755 __IO uint32_t HcInterruptEnable;
AnnaBridge 171:3a7713b1edbc 756 __IO uint32_t HcInterruptDisable;
AnnaBridge 171:3a7713b1edbc 757 __IO uint32_t HcHCCA;
AnnaBridge 171:3a7713b1edbc 758 __I uint32_t HcPeriodCurrentED;
AnnaBridge 171:3a7713b1edbc 759 __IO uint32_t HcControlHeadED;
AnnaBridge 171:3a7713b1edbc 760 __IO uint32_t HcControlCurrentED;
AnnaBridge 171:3a7713b1edbc 761 __IO uint32_t HcBulkHeadED;
AnnaBridge 171:3a7713b1edbc 762 __IO uint32_t HcBulkCurrentED;
AnnaBridge 171:3a7713b1edbc 763 __I uint32_t HcDoneHead;
AnnaBridge 171:3a7713b1edbc 764 __IO uint32_t HcFmInterval;
AnnaBridge 171:3a7713b1edbc 765 __I uint32_t HcFmRemaining;
AnnaBridge 171:3a7713b1edbc 766 __I uint32_t HcFmNumber;
AnnaBridge 171:3a7713b1edbc 767 __IO uint32_t HcPeriodicStart;
AnnaBridge 171:3a7713b1edbc 768 __IO uint32_t HcLSTreshold;
AnnaBridge 171:3a7713b1edbc 769 __IO uint32_t HcRhDescriptorA;
AnnaBridge 171:3a7713b1edbc 770 __IO uint32_t HcRhDescriptorB;
AnnaBridge 171:3a7713b1edbc 771 __IO uint32_t HcRhStatus;
AnnaBridge 171:3a7713b1edbc 772 __IO uint32_t HcRhPortStatus1;
AnnaBridge 171:3a7713b1edbc 773 __IO uint32_t HcRhPortStatus2;
AnnaBridge 171:3a7713b1edbc 774 uint32_t RESERVED0[40];
AnnaBridge 171:3a7713b1edbc 775 __I uint32_t Module_ID;
AnnaBridge 171:3a7713b1edbc 776
AnnaBridge 171:3a7713b1edbc 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
AnnaBridge 171:3a7713b1edbc 778 __IO uint32_t OTGIntEn;
AnnaBridge 171:3a7713b1edbc 779 __O uint32_t OTGIntSet;
AnnaBridge 171:3a7713b1edbc 780 __O uint32_t OTGIntClr;
AnnaBridge 171:3a7713b1edbc 781 __IO uint32_t OTGStCtrl;
AnnaBridge 171:3a7713b1edbc 782 __IO uint32_t OTGTmr;
AnnaBridge 171:3a7713b1edbc 783 uint32_t RESERVED1[58];
AnnaBridge 171:3a7713b1edbc 784
AnnaBridge 171:3a7713b1edbc 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
AnnaBridge 171:3a7713b1edbc 786 __IO uint32_t USBDevIntEn;
AnnaBridge 171:3a7713b1edbc 787 __O uint32_t USBDevIntClr;
AnnaBridge 171:3a7713b1edbc 788 __O uint32_t USBDevIntSet;
AnnaBridge 171:3a7713b1edbc 789
AnnaBridge 171:3a7713b1edbc 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
AnnaBridge 171:3a7713b1edbc 791 __I uint32_t USBCmdData;
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
AnnaBridge 171:3a7713b1edbc 794 __O uint32_t USBTxData;
AnnaBridge 171:3a7713b1edbc 795 __I uint32_t USBRxPLen;
AnnaBridge 171:3a7713b1edbc 796 __O uint32_t USBTxPLen;
AnnaBridge 171:3a7713b1edbc 797 __IO uint32_t USBCtrl;
AnnaBridge 171:3a7713b1edbc 798 __O uint32_t USBDevIntPri;
AnnaBridge 171:3a7713b1edbc 799
AnnaBridge 171:3a7713b1edbc 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
AnnaBridge 171:3a7713b1edbc 801 __IO uint32_t USBEpIntEn;
AnnaBridge 171:3a7713b1edbc 802 __O uint32_t USBEpIntClr;
AnnaBridge 171:3a7713b1edbc 803 __O uint32_t USBEpIntSet;
AnnaBridge 171:3a7713b1edbc 804 __O uint32_t USBEpIntPri;
AnnaBridge 171:3a7713b1edbc 805
AnnaBridge 171:3a7713b1edbc 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
AnnaBridge 171:3a7713b1edbc 807 __O uint32_t USBEpInd;
AnnaBridge 171:3a7713b1edbc 808 __IO uint32_t USBMaxPSize;
AnnaBridge 171:3a7713b1edbc 809
AnnaBridge 171:3a7713b1edbc 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
AnnaBridge 171:3a7713b1edbc 811 __O uint32_t USBDMARClr;
AnnaBridge 171:3a7713b1edbc 812 __O uint32_t USBDMARSet;
AnnaBridge 171:3a7713b1edbc 813 uint32_t RESERVED2[9];
AnnaBridge 171:3a7713b1edbc 814 __IO uint32_t USBUDCAH;
AnnaBridge 171:3a7713b1edbc 815 __I uint32_t USBEpDMASt;
AnnaBridge 171:3a7713b1edbc 816 __O uint32_t USBEpDMAEn;
AnnaBridge 171:3a7713b1edbc 817 __O uint32_t USBEpDMADis;
AnnaBridge 171:3a7713b1edbc 818 __I uint32_t USBDMAIntSt;
AnnaBridge 171:3a7713b1edbc 819 __IO uint32_t USBDMAIntEn;
AnnaBridge 171:3a7713b1edbc 820 uint32_t RESERVED3[2];
AnnaBridge 171:3a7713b1edbc 821 __I uint32_t USBEoTIntSt;
AnnaBridge 171:3a7713b1edbc 822 __O uint32_t USBEoTIntClr;
AnnaBridge 171:3a7713b1edbc 823 __O uint32_t USBEoTIntSet;
AnnaBridge 171:3a7713b1edbc 824 __I uint32_t USBNDDRIntSt;
AnnaBridge 171:3a7713b1edbc 825 __O uint32_t USBNDDRIntClr;
AnnaBridge 171:3a7713b1edbc 826 __O uint32_t USBNDDRIntSet;
AnnaBridge 171:3a7713b1edbc 827 __I uint32_t USBSysErrIntSt;
AnnaBridge 171:3a7713b1edbc 828 __O uint32_t USBSysErrIntClr;
AnnaBridge 171:3a7713b1edbc 829 __O uint32_t USBSysErrIntSet;
AnnaBridge 171:3a7713b1edbc 830 uint32_t RESERVED4[15];
AnnaBridge 171:3a7713b1edbc 831
AnnaBridge 171:3a7713b1edbc 832 union {
AnnaBridge 171:3a7713b1edbc 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
AnnaBridge 171:3a7713b1edbc 834 __O uint32_t I2C_TX;
AnnaBridge 171:3a7713b1edbc 835 };
AnnaBridge 171:3a7713b1edbc 836 __I uint32_t I2C_STS;
AnnaBridge 171:3a7713b1edbc 837 __IO uint32_t I2C_CTL;
AnnaBridge 171:3a7713b1edbc 838 __IO uint32_t I2C_CLKHI;
AnnaBridge 171:3a7713b1edbc 839 __O uint32_t I2C_CLKLO;
AnnaBridge 171:3a7713b1edbc 840 uint32_t RESERVED5[824];
AnnaBridge 171:3a7713b1edbc 841
AnnaBridge 171:3a7713b1edbc 842 union {
AnnaBridge 171:3a7713b1edbc 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
AnnaBridge 171:3a7713b1edbc 844 __IO uint32_t OTGClkCtrl;
AnnaBridge 171:3a7713b1edbc 845 };
AnnaBridge 171:3a7713b1edbc 846 union {
AnnaBridge 171:3a7713b1edbc 847 __I uint32_t USBClkSt;
AnnaBridge 171:3a7713b1edbc 848 __I uint32_t OTGClkSt;
AnnaBridge 171:3a7713b1edbc 849 };
AnnaBridge 171:3a7713b1edbc 850 } LPC_USB_TypeDef;
AnnaBridge 171:3a7713b1edbc 851
AnnaBridge 171:3a7713b1edbc 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
AnnaBridge 171:3a7713b1edbc 853 typedef struct
AnnaBridge 171:3a7713b1edbc 854 {
AnnaBridge 171:3a7713b1edbc 855 __IO uint32_t MAC1; /* MAC Registers */
AnnaBridge 171:3a7713b1edbc 856 __IO uint32_t MAC2;
AnnaBridge 171:3a7713b1edbc 857 __IO uint32_t IPGT;
AnnaBridge 171:3a7713b1edbc 858 __IO uint32_t IPGR;
AnnaBridge 171:3a7713b1edbc 859 __IO uint32_t CLRT;
AnnaBridge 171:3a7713b1edbc 860 __IO uint32_t MAXF;
AnnaBridge 171:3a7713b1edbc 861 __IO uint32_t SUPP;
AnnaBridge 171:3a7713b1edbc 862 __IO uint32_t TEST;
AnnaBridge 171:3a7713b1edbc 863 __IO uint32_t MCFG;
AnnaBridge 171:3a7713b1edbc 864 __IO uint32_t MCMD;
AnnaBridge 171:3a7713b1edbc 865 __IO uint32_t MADR;
AnnaBridge 171:3a7713b1edbc 866 __O uint32_t MWTD;
AnnaBridge 171:3a7713b1edbc 867 __I uint32_t MRDD;
AnnaBridge 171:3a7713b1edbc 868 __I uint32_t MIND;
AnnaBridge 171:3a7713b1edbc 869 uint32_t RESERVED0[2];
AnnaBridge 171:3a7713b1edbc 870 __IO uint32_t SA0;
AnnaBridge 171:3a7713b1edbc 871 __IO uint32_t SA1;
AnnaBridge 171:3a7713b1edbc 872 __IO uint32_t SA2;
AnnaBridge 171:3a7713b1edbc 873 uint32_t RESERVED1[45];
AnnaBridge 171:3a7713b1edbc 874 __IO uint32_t Command; /* Control Registers */
AnnaBridge 171:3a7713b1edbc 875 __I uint32_t Status;
AnnaBridge 171:3a7713b1edbc 876 __IO uint32_t RxDescriptor;
AnnaBridge 171:3a7713b1edbc 877 __IO uint32_t RxStatus;
AnnaBridge 171:3a7713b1edbc 878 __IO uint32_t RxDescriptorNumber;
AnnaBridge 171:3a7713b1edbc 879 __I uint32_t RxProduceIndex;
AnnaBridge 171:3a7713b1edbc 880 __IO uint32_t RxConsumeIndex;
AnnaBridge 171:3a7713b1edbc 881 __IO uint32_t TxDescriptor;
AnnaBridge 171:3a7713b1edbc 882 __IO uint32_t TxStatus;
AnnaBridge 171:3a7713b1edbc 883 __IO uint32_t TxDescriptorNumber;
AnnaBridge 171:3a7713b1edbc 884 __IO uint32_t TxProduceIndex;
AnnaBridge 171:3a7713b1edbc 885 __I uint32_t TxConsumeIndex;
AnnaBridge 171:3a7713b1edbc 886 uint32_t RESERVED2[10];
AnnaBridge 171:3a7713b1edbc 887 __I uint32_t TSV0;
AnnaBridge 171:3a7713b1edbc 888 __I uint32_t TSV1;
AnnaBridge 171:3a7713b1edbc 889 __I uint32_t RSV;
AnnaBridge 171:3a7713b1edbc 890 uint32_t RESERVED3[3];
AnnaBridge 171:3a7713b1edbc 891 __IO uint32_t FlowControlCounter;
AnnaBridge 171:3a7713b1edbc 892 __I uint32_t FlowControlStatus;
AnnaBridge 171:3a7713b1edbc 893 uint32_t RESERVED4[34];
AnnaBridge 171:3a7713b1edbc 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
AnnaBridge 171:3a7713b1edbc 895 __IO uint32_t RxFilterWoLStatus;
AnnaBridge 171:3a7713b1edbc 896 __IO uint32_t RxFilterWoLClear;
AnnaBridge 171:3a7713b1edbc 897 uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 898 __IO uint32_t HashFilterL;
AnnaBridge 171:3a7713b1edbc 899 __IO uint32_t HashFilterH;
AnnaBridge 171:3a7713b1edbc 900 uint32_t RESERVED6[882];
AnnaBridge 171:3a7713b1edbc 901 __I uint32_t IntStatus; /* Module Control Registers */
AnnaBridge 171:3a7713b1edbc 902 __IO uint32_t IntEnable;
AnnaBridge 171:3a7713b1edbc 903 __O uint32_t IntClear;
AnnaBridge 171:3a7713b1edbc 904 __O uint32_t IntSet;
AnnaBridge 171:3a7713b1edbc 905 uint32_t RESERVED7;
AnnaBridge 171:3a7713b1edbc 906 __IO uint32_t PowerDown;
AnnaBridge 171:3a7713b1edbc 907 uint32_t RESERVED8;
AnnaBridge 171:3a7713b1edbc 908 __IO uint32_t Module_ID;
AnnaBridge 171:3a7713b1edbc 909 } LPC_EMAC_TypeDef;
AnnaBridge 171:3a7713b1edbc 910
AnnaBridge 171:3a7713b1edbc 911 #if defined ( __CC_ARM )
AnnaBridge 171:3a7713b1edbc 912 #pragma no_anon_unions
AnnaBridge 171:3a7713b1edbc 913 #endif
AnnaBridge 171:3a7713b1edbc 914
AnnaBridge 171:3a7713b1edbc 915
AnnaBridge 171:3a7713b1edbc 916 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 917 /* Peripheral memory map */
AnnaBridge 171:3a7713b1edbc 918 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 919 /* Base addresses */
AnnaBridge 171:3a7713b1edbc 920 #define LPC_FLASH_BASE (0x00000000UL)
AnnaBridge 171:3a7713b1edbc 921 #define LPC_RAM_BASE (0x10000000UL)
AnnaBridge 171:3a7713b1edbc 922 #define LPC_GPIO_BASE (0x2009C000UL)
AnnaBridge 171:3a7713b1edbc 923 #define LPC_APB0_BASE (0x40000000UL)
AnnaBridge 171:3a7713b1edbc 924 #define LPC_APB1_BASE (0x40080000UL)
AnnaBridge 171:3a7713b1edbc 925 #define LPC_AHB_BASE (0x50000000UL)
AnnaBridge 171:3a7713b1edbc 926 #define LPC_CM3_BASE (0xE0000000UL)
AnnaBridge 171:3a7713b1edbc 927
AnnaBridge 171:3a7713b1edbc 928 /* APB0 peripherals */
AnnaBridge 171:3a7713b1edbc 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
AnnaBridge 171:3a7713b1edbc 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
AnnaBridge 171:3a7713b1edbc 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
AnnaBridge 171:3a7713b1edbc 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
AnnaBridge 171:3a7713b1edbc 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
AnnaBridge 171:3a7713b1edbc 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
AnnaBridge 171:3a7713b1edbc 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
AnnaBridge 171:3a7713b1edbc 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
AnnaBridge 171:3a7713b1edbc 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
AnnaBridge 171:3a7713b1edbc 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
AnnaBridge 171:3a7713b1edbc 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
AnnaBridge 171:3a7713b1edbc 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
AnnaBridge 171:3a7713b1edbc 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
AnnaBridge 171:3a7713b1edbc 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
AnnaBridge 171:3a7713b1edbc 948
AnnaBridge 171:3a7713b1edbc 949 /* APB1 peripherals */
AnnaBridge 171:3a7713b1edbc 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
AnnaBridge 171:3a7713b1edbc 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
AnnaBridge 171:3a7713b1edbc 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
AnnaBridge 171:3a7713b1edbc 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
AnnaBridge 171:3a7713b1edbc 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
AnnaBridge 171:3a7713b1edbc 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
AnnaBridge 171:3a7713b1edbc 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
AnnaBridge 171:3a7713b1edbc 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
AnnaBridge 171:3a7713b1edbc 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
AnnaBridge 171:3a7713b1edbc 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
AnnaBridge 171:3a7713b1edbc 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
AnnaBridge 171:3a7713b1edbc 962
AnnaBridge 171:3a7713b1edbc 963 /* AHB peripherals */
AnnaBridge 171:3a7713b1edbc 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
AnnaBridge 171:3a7713b1edbc 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
AnnaBridge 171:3a7713b1edbc 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
AnnaBridge 171:3a7713b1edbc 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
AnnaBridge 171:3a7713b1edbc 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
AnnaBridge 171:3a7713b1edbc 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
AnnaBridge 171:3a7713b1edbc 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
AnnaBridge 171:3a7713b1edbc 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
AnnaBridge 171:3a7713b1edbc 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
AnnaBridge 171:3a7713b1edbc 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
AnnaBridge 171:3a7713b1edbc 975
AnnaBridge 171:3a7713b1edbc 976 /* GPIOs */
AnnaBridge 171:3a7713b1edbc 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
AnnaBridge 171:3a7713b1edbc 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
AnnaBridge 171:3a7713b1edbc 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
AnnaBridge 171:3a7713b1edbc 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
AnnaBridge 171:3a7713b1edbc 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
AnnaBridge 171:3a7713b1edbc 982
AnnaBridge 171:3a7713b1edbc 983
AnnaBridge 171:3a7713b1edbc 984 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 985 /* Peripheral declaration */
AnnaBridge 171:3a7713b1edbc 986 /******************************************************************************/
AnnaBridge 171:3a7713b1edbc 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
AnnaBridge 171:3a7713b1edbc 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
AnnaBridge 171:3a7713b1edbc 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
AnnaBridge 171:3a7713b1edbc 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
AnnaBridge 171:3a7713b1edbc 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
AnnaBridge 171:3a7713b1edbc 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
AnnaBridge 171:3a7713b1edbc 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
AnnaBridge 171:3a7713b1edbc 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
AnnaBridge 171:3a7713b1edbc 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
AnnaBridge 171:3a7713b1edbc 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
AnnaBridge 171:3a7713b1edbc 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
AnnaBridge 171:3a7713b1edbc 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
AnnaBridge 171:3a7713b1edbc 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
AnnaBridge 171:3a7713b1edbc 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
AnnaBridge 171:3a7713b1edbc 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
AnnaBridge 171:3a7713b1edbc 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
AnnaBridge 171:3a7713b1edbc 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
AnnaBridge 171:3a7713b1edbc 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
AnnaBridge 171:3a7713b1edbc 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
AnnaBridge 171:3a7713b1edbc 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
AnnaBridge 171:3a7713b1edbc 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
AnnaBridge 171:3a7713b1edbc 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
AnnaBridge 171:3a7713b1edbc 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
AnnaBridge 171:3a7713b1edbc 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
AnnaBridge 171:3a7713b1edbc 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
AnnaBridge 171:3a7713b1edbc 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
AnnaBridge 171:3a7713b1edbc 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
AnnaBridge 171:3a7713b1edbc 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
AnnaBridge 171:3a7713b1edbc 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
AnnaBridge 171:3a7713b1edbc 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
AnnaBridge 171:3a7713b1edbc 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
AnnaBridge 171:3a7713b1edbc 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
AnnaBridge 171:3a7713b1edbc 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
AnnaBridge 171:3a7713b1edbc 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
AnnaBridge 171:3a7713b1edbc 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
AnnaBridge 171:3a7713b1edbc 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
AnnaBridge 171:3a7713b1edbc 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
AnnaBridge 171:3a7713b1edbc 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
AnnaBridge 171:3a7713b1edbc 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
AnnaBridge 171:3a7713b1edbc 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
AnnaBridge 171:3a7713b1edbc 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
AnnaBridge 171:3a7713b1edbc 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
AnnaBridge 171:3a7713b1edbc 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
AnnaBridge 171:3a7713b1edbc 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
AnnaBridge 171:3a7713b1edbc 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
AnnaBridge 171:3a7713b1edbc 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
AnnaBridge 171:3a7713b1edbc 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
AnnaBridge 171:3a7713b1edbc 1034
AnnaBridge 171:3a7713b1edbc 1035 #endif // __LPC17xx_H__