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TARGET_KL43Z/TOOLCHAIN_IAR/fsl_lptmr.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 9 * of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 16 * contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 17 * software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 29 */
AnnaBridge 171:3a7713b1edbc 30 #ifndef _FSL_LPTMR_H_
AnnaBridge 171:3a7713b1edbc 31 #define _FSL_LPTMR_H_
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 #include "fsl_common.h"
AnnaBridge 171:3a7713b1edbc 34
AnnaBridge 171:3a7713b1edbc 35 /*!
AnnaBridge 171:3a7713b1edbc 36 * @addtogroup lptmr_driver
AnnaBridge 171:3a7713b1edbc 37 * @{
AnnaBridge 171:3a7713b1edbc 38 */
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40 /*! @file */
AnnaBridge 171:3a7713b1edbc 41
AnnaBridge 171:3a7713b1edbc 42 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 43 * Definitions
AnnaBridge 171:3a7713b1edbc 44 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /*! @name Driver version */
AnnaBridge 171:3a7713b1edbc 47 /*@{*/
AnnaBridge 171:3a7713b1edbc 48 #define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0 */
AnnaBridge 171:3a7713b1edbc 49 /*@}*/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /*! @brief LPTMR pin selection, used in pulse counter mode.*/
AnnaBridge 171:3a7713b1edbc 52 typedef enum _lptmr_pin_select
AnnaBridge 171:3a7713b1edbc 53 {
AnnaBridge 171:3a7713b1edbc 54 kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
AnnaBridge 171:3a7713b1edbc 55 kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */
AnnaBridge 171:3a7713b1edbc 56 kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */
AnnaBridge 171:3a7713b1edbc 57 kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */
AnnaBridge 171:3a7713b1edbc 58 } lptmr_pin_select_t;
AnnaBridge 171:3a7713b1edbc 59
AnnaBridge 171:3a7713b1edbc 60 /*! @brief LPTMR pin polarity, used in pulse counter mode.*/
AnnaBridge 171:3a7713b1edbc 61 typedef enum _lptmr_pin_polarity
AnnaBridge 171:3a7713b1edbc 62 {
AnnaBridge 171:3a7713b1edbc 63 kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
AnnaBridge 171:3a7713b1edbc 64 kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */
AnnaBridge 171:3a7713b1edbc 65 } lptmr_pin_polarity_t;
AnnaBridge 171:3a7713b1edbc 66
AnnaBridge 171:3a7713b1edbc 67 /*! @brief LPTMR timer mode selection.*/
AnnaBridge 171:3a7713b1edbc 68 typedef enum _lptmr_timer_mode
AnnaBridge 171:3a7713b1edbc 69 {
AnnaBridge 171:3a7713b1edbc 70 kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */
AnnaBridge 171:3a7713b1edbc 71 kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */
AnnaBridge 171:3a7713b1edbc 72 } lptmr_timer_mode_t;
AnnaBridge 171:3a7713b1edbc 73
AnnaBridge 171:3a7713b1edbc 74 /*! @brief LPTMR prescaler/glitch filter values*/
AnnaBridge 171:3a7713b1edbc 75 typedef enum _lptmr_prescaler_glitch_value
AnnaBridge 171:3a7713b1edbc 76 {
AnnaBridge 171:3a7713b1edbc 77 kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */
AnnaBridge 171:3a7713b1edbc 78 kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */
AnnaBridge 171:3a7713b1edbc 79 kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */
AnnaBridge 171:3a7713b1edbc 80 kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */
AnnaBridge 171:3a7713b1edbc 81 kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */
AnnaBridge 171:3a7713b1edbc 82 kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */
AnnaBridge 171:3a7713b1edbc 83 kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */
AnnaBridge 171:3a7713b1edbc 84 kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */
AnnaBridge 171:3a7713b1edbc 85 kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */
AnnaBridge 171:3a7713b1edbc 86 kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/
AnnaBridge 171:3a7713b1edbc 87 kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */
AnnaBridge 171:3a7713b1edbc 88 kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */
AnnaBridge 171:3a7713b1edbc 89 kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */
AnnaBridge 171:3a7713b1edbc 90 kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */
AnnaBridge 171:3a7713b1edbc 91 kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */
AnnaBridge 171:3a7713b1edbc 92 kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */
AnnaBridge 171:3a7713b1edbc 93 } lptmr_prescaler_glitch_value_t;
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /*!
AnnaBridge 171:3a7713b1edbc 96 * @brief LPTMR prescaler/glitch filter clock select.
AnnaBridge 171:3a7713b1edbc 97 * @note Clock connections are SoC-specific
AnnaBridge 171:3a7713b1edbc 98 */
AnnaBridge 171:3a7713b1edbc 99 typedef enum _lptmr_prescaler_clock_select
AnnaBridge 171:3a7713b1edbc 100 {
AnnaBridge 171:3a7713b1edbc 101 kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
AnnaBridge 171:3a7713b1edbc 102 kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
AnnaBridge 171:3a7713b1edbc 103 kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
AnnaBridge 171:3a7713b1edbc 104 kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
AnnaBridge 171:3a7713b1edbc 105 } lptmr_prescaler_clock_select_t;
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /*! @brief List of LPTMR interrupts */
AnnaBridge 171:3a7713b1edbc 108 typedef enum _lptmr_interrupt_enable
AnnaBridge 171:3a7713b1edbc 109 {
AnnaBridge 171:3a7713b1edbc 110 kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
AnnaBridge 171:3a7713b1edbc 111 } lptmr_interrupt_enable_t;
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /*! @brief List of LPTMR status flags */
AnnaBridge 171:3a7713b1edbc 114 typedef enum _lptmr_status_flags
AnnaBridge 171:3a7713b1edbc 115 {
AnnaBridge 171:3a7713b1edbc 116 kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
AnnaBridge 171:3a7713b1edbc 117 } lptmr_status_flags_t;
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /*!
AnnaBridge 171:3a7713b1edbc 120 * @brief LPTMR config structure
AnnaBridge 171:3a7713b1edbc 121 *
AnnaBridge 171:3a7713b1edbc 122 * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
AnnaBridge 171:3a7713b1edbc 123 * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
AnnaBridge 171:3a7713b1edbc 124 * pointer to your config structure instance.
AnnaBridge 171:3a7713b1edbc 125 *
AnnaBridge 171:3a7713b1edbc 126 * The config struct can be made const so it resides in flash
AnnaBridge 171:3a7713b1edbc 127 */
AnnaBridge 171:3a7713b1edbc 128 typedef struct _lptmr_config
AnnaBridge 171:3a7713b1edbc 129 {
AnnaBridge 171:3a7713b1edbc 130 lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */
AnnaBridge 171:3a7713b1edbc 131 lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */
AnnaBridge 171:3a7713b1edbc 132 lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
AnnaBridge 171:3a7713b1edbc 133 bool enableFreeRunning; /*!< true: enable free running, counter is reset on overflow
AnnaBridge 171:3a7713b1edbc 134 false: counter is reset when the compare flag is set */
AnnaBridge 171:3a7713b1edbc 135 bool bypassPrescaler; /*!< true: bypass prescaler; false: use clock from prescaler */
AnnaBridge 171:3a7713b1edbc 136 lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
AnnaBridge 171:3a7713b1edbc 137 lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */
AnnaBridge 171:3a7713b1edbc 138 } lptmr_config_t;
AnnaBridge 171:3a7713b1edbc 139
AnnaBridge 171:3a7713b1edbc 140 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 141 * API
AnnaBridge 171:3a7713b1edbc 142 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 143
AnnaBridge 171:3a7713b1edbc 144 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 145 extern "C" {
AnnaBridge 171:3a7713b1edbc 146 #endif
AnnaBridge 171:3a7713b1edbc 147
AnnaBridge 171:3a7713b1edbc 148 /*!
AnnaBridge 171:3a7713b1edbc 149 * @name Initialization and deinitialization
AnnaBridge 171:3a7713b1edbc 150 * @{
AnnaBridge 171:3a7713b1edbc 151 */
AnnaBridge 171:3a7713b1edbc 152
AnnaBridge 171:3a7713b1edbc 153 /*!
AnnaBridge 171:3a7713b1edbc 154 * @brief Ungate the LPTMR clock and configures the peripheral for basic operation.
AnnaBridge 171:3a7713b1edbc 155 *
AnnaBridge 171:3a7713b1edbc 156 * @note This API should be called at the beginning of the application using the LPTMR driver.
AnnaBridge 171:3a7713b1edbc 157 *
AnnaBridge 171:3a7713b1edbc 158 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 159 * @param config Pointer to user's LPTMR config structure.
AnnaBridge 171:3a7713b1edbc 160 */
AnnaBridge 171:3a7713b1edbc 161 void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 /*!
AnnaBridge 171:3a7713b1edbc 164 * @brief Gate the LPTMR clock
AnnaBridge 171:3a7713b1edbc 165 *
AnnaBridge 171:3a7713b1edbc 166 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 167 */
AnnaBridge 171:3a7713b1edbc 168 void LPTMR_Deinit(LPTMR_Type *base);
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /*!
AnnaBridge 171:3a7713b1edbc 171 * @brief Fill in the LPTMR config struct with the default settings
AnnaBridge 171:3a7713b1edbc 172 *
AnnaBridge 171:3a7713b1edbc 173 * The default values are:
AnnaBridge 171:3a7713b1edbc 174 * @code
AnnaBridge 171:3a7713b1edbc 175 * config->timerMode = kLPTMR_TimerModeTimeCounter;
AnnaBridge 171:3a7713b1edbc 176 * config->pinSelect = kLPTMR_PinSelectInput_0;
AnnaBridge 171:3a7713b1edbc 177 * config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
AnnaBridge 171:3a7713b1edbc 178 * config->enableFreeRunning = false;
AnnaBridge 171:3a7713b1edbc 179 * config->bypassPrescaler = true;
AnnaBridge 171:3a7713b1edbc 180 * config->prescalerClockSource = kLPTMR_PrescalerClock_1;
AnnaBridge 171:3a7713b1edbc 181 * config->value = kLPTMR_Prescale_Glitch_0;
AnnaBridge 171:3a7713b1edbc 182 * @endcode
AnnaBridge 171:3a7713b1edbc 183 * @param config Pointer to user's LPTMR config structure.
AnnaBridge 171:3a7713b1edbc 184 */
AnnaBridge 171:3a7713b1edbc 185 void LPTMR_GetDefaultConfig(lptmr_config_t *config);
AnnaBridge 171:3a7713b1edbc 186
AnnaBridge 171:3a7713b1edbc 187 /*! @}*/
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /*!
AnnaBridge 171:3a7713b1edbc 190 * @name Interrupt Interface
AnnaBridge 171:3a7713b1edbc 191 * @{
AnnaBridge 171:3a7713b1edbc 192 */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /*!
AnnaBridge 171:3a7713b1edbc 195 * @brief Enables the selected LPTMR interrupts.
AnnaBridge 171:3a7713b1edbc 196 *
AnnaBridge 171:3a7713b1edbc 197 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 198 * @param mask The interrupts to enable. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 199 * enumeration ::lptmr_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 200 */
AnnaBridge 171:3a7713b1edbc 201 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 202 {
AnnaBridge 171:3a7713b1edbc 203 base->CSR |= mask;
AnnaBridge 171:3a7713b1edbc 204 }
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 /*!
AnnaBridge 171:3a7713b1edbc 207 * @brief Disables the selected LPTMR interrupts.
AnnaBridge 171:3a7713b1edbc 208 *
AnnaBridge 171:3a7713b1edbc 209 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 210 * @param mask The interrupts to disable. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 211 * enumeration ::lptmr_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 212 */
AnnaBridge 171:3a7713b1edbc 213 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 214 {
AnnaBridge 171:3a7713b1edbc 215 base->CSR &= ~mask;
AnnaBridge 171:3a7713b1edbc 216 }
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 /*!
AnnaBridge 171:3a7713b1edbc 219 * @brief Gets the enabled LPTMR interrupts.
AnnaBridge 171:3a7713b1edbc 220 *
AnnaBridge 171:3a7713b1edbc 221 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 222 *
AnnaBridge 171:3a7713b1edbc 223 * @return The enabled interrupts. This is the logical OR of members of the
AnnaBridge 171:3a7713b1edbc 224 * enumeration ::lptmr_interrupt_enable_t
AnnaBridge 171:3a7713b1edbc 225 */
AnnaBridge 171:3a7713b1edbc 226 static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
AnnaBridge 171:3a7713b1edbc 227 {
AnnaBridge 171:3a7713b1edbc 228 return (base->CSR & LPTMR_CSR_TIE_MASK);
AnnaBridge 171:3a7713b1edbc 229 }
AnnaBridge 171:3a7713b1edbc 230
AnnaBridge 171:3a7713b1edbc 231 /*! @}*/
AnnaBridge 171:3a7713b1edbc 232
AnnaBridge 171:3a7713b1edbc 233 /*!
AnnaBridge 171:3a7713b1edbc 234 * @name Status Interface
AnnaBridge 171:3a7713b1edbc 235 * @{
AnnaBridge 171:3a7713b1edbc 236 */
AnnaBridge 171:3a7713b1edbc 237
AnnaBridge 171:3a7713b1edbc 238 /*!
AnnaBridge 171:3a7713b1edbc 239 * @brief Gets the LPTMR status flags
AnnaBridge 171:3a7713b1edbc 240 *
AnnaBridge 171:3a7713b1edbc 241 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 242 *
AnnaBridge 171:3a7713b1edbc 243 * @return The status flags. This is the logical OR of members of the
AnnaBridge 171:3a7713b1edbc 244 * enumeration ::lptmr_status_flags_t
AnnaBridge 171:3a7713b1edbc 245 */
AnnaBridge 171:3a7713b1edbc 246 static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
AnnaBridge 171:3a7713b1edbc 247 {
AnnaBridge 171:3a7713b1edbc 248 return (base->CSR & LPTMR_CSR_TCF_MASK);
AnnaBridge 171:3a7713b1edbc 249 }
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251 /*!
AnnaBridge 171:3a7713b1edbc 252 * @brief Clears the LPTMR status flags
AnnaBridge 171:3a7713b1edbc 253 *
AnnaBridge 171:3a7713b1edbc 254 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 255 * @param mask The status flags to clear. This is a logical OR of members of the
AnnaBridge 171:3a7713b1edbc 256 * enumeration ::lptmr_status_flags_t
AnnaBridge 171:3a7713b1edbc 257 */
AnnaBridge 171:3a7713b1edbc 258 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
AnnaBridge 171:3a7713b1edbc 259 {
AnnaBridge 171:3a7713b1edbc 260 base->CSR |= mask;
AnnaBridge 171:3a7713b1edbc 261 }
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /*! @}*/
AnnaBridge 171:3a7713b1edbc 264
AnnaBridge 171:3a7713b1edbc 265 /*!
AnnaBridge 171:3a7713b1edbc 266 * @name Read and Write the timer period
AnnaBridge 171:3a7713b1edbc 267 * @{
AnnaBridge 171:3a7713b1edbc 268 */
AnnaBridge 171:3a7713b1edbc 269
AnnaBridge 171:3a7713b1edbc 270 /*!
AnnaBridge 171:3a7713b1edbc 271 * @brief Sets the timer period in units of count.
AnnaBridge 171:3a7713b1edbc 272 *
AnnaBridge 171:3a7713b1edbc 273 * Timers counts from 0 till it equals the count value set here. The count value is written to
AnnaBridge 171:3a7713b1edbc 274 * the CMR register.
AnnaBridge 171:3a7713b1edbc 275 *
AnnaBridge 171:3a7713b1edbc 276 * @note
AnnaBridge 171:3a7713b1edbc 277 * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
AnnaBridge 171:3a7713b1edbc 278 * 2. User can call the utility macros provided in fsl_common.h to convert to ticks
AnnaBridge 171:3a7713b1edbc 279 *
AnnaBridge 171:3a7713b1edbc 280 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 281 * @param ticks Timer period in units of ticks
AnnaBridge 171:3a7713b1edbc 282 */
AnnaBridge 171:3a7713b1edbc 283 static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint16_t ticks)
AnnaBridge 171:3a7713b1edbc 284 {
AnnaBridge 171:3a7713b1edbc 285 base->CMR = ticks;
AnnaBridge 171:3a7713b1edbc 286 }
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 /*!
AnnaBridge 171:3a7713b1edbc 289 * @brief Reads the current timer counting value.
AnnaBridge 171:3a7713b1edbc 290 *
AnnaBridge 171:3a7713b1edbc 291 * This function returns the real-time timer counting value, in a range from 0 to a
AnnaBridge 171:3a7713b1edbc 292 * timer period.
AnnaBridge 171:3a7713b1edbc 293 *
AnnaBridge 171:3a7713b1edbc 294 * @note User can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
AnnaBridge 171:3a7713b1edbc 295 *
AnnaBridge 171:3a7713b1edbc 296 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 297 *
AnnaBridge 171:3a7713b1edbc 298 * @return Current counter value in ticks
AnnaBridge 171:3a7713b1edbc 299 */
AnnaBridge 171:3a7713b1edbc 300 static inline uint16_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
AnnaBridge 171:3a7713b1edbc 301 {
AnnaBridge 171:3a7713b1edbc 302 /* Must first write any value to the CNR. This will synchronize and register the current value
AnnaBridge 171:3a7713b1edbc 303 * of the CNR into a temporary register which can then be read
AnnaBridge 171:3a7713b1edbc 304 */
AnnaBridge 171:3a7713b1edbc 305 base->CNR = 0U;
AnnaBridge 171:3a7713b1edbc 306 return (uint16_t)base->CNR;
AnnaBridge 171:3a7713b1edbc 307 }
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /*! @}*/
AnnaBridge 171:3a7713b1edbc 310
AnnaBridge 171:3a7713b1edbc 311 /*!
AnnaBridge 171:3a7713b1edbc 312 * @name Timer Start and Stop
AnnaBridge 171:3a7713b1edbc 313 * @{
AnnaBridge 171:3a7713b1edbc 314 */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 /*!
AnnaBridge 171:3a7713b1edbc 317 * @brief Starts the timer counting.
AnnaBridge 171:3a7713b1edbc 318 *
AnnaBridge 171:3a7713b1edbc 319 * After calling this function, the timer counts up to the CMR register value.
AnnaBridge 171:3a7713b1edbc 320 * Each time the timer reaches CMR value and then increments, it generates a
AnnaBridge 171:3a7713b1edbc 321 * trigger pulse and sets the timeout interrupt flag. An interrupt will also be
AnnaBridge 171:3a7713b1edbc 322 * triggered if the timer interrupt is enabled.
AnnaBridge 171:3a7713b1edbc 323 *
AnnaBridge 171:3a7713b1edbc 324 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 325 */
AnnaBridge 171:3a7713b1edbc 326 static inline void LPTMR_StartTimer(LPTMR_Type *base)
AnnaBridge 171:3a7713b1edbc 327 {
AnnaBridge 171:3a7713b1edbc 328 base->CSR |= LPTMR_CSR_TEN_MASK;
AnnaBridge 171:3a7713b1edbc 329 }
AnnaBridge 171:3a7713b1edbc 330
AnnaBridge 171:3a7713b1edbc 331 /*!
AnnaBridge 171:3a7713b1edbc 332 * @brief Stops the timer counting.
AnnaBridge 171:3a7713b1edbc 333 *
AnnaBridge 171:3a7713b1edbc 334 * This function stops the timer counting and resets the timer's counter register
AnnaBridge 171:3a7713b1edbc 335 *
AnnaBridge 171:3a7713b1edbc 336 * @param base LPTMR peripheral base address
AnnaBridge 171:3a7713b1edbc 337 */
AnnaBridge 171:3a7713b1edbc 338 static inline void LPTMR_StopTimer(LPTMR_Type *base)
AnnaBridge 171:3a7713b1edbc 339 {
AnnaBridge 171:3a7713b1edbc 340 base->CSR &= ~LPTMR_CSR_TEN_MASK;
AnnaBridge 171:3a7713b1edbc 341 }
AnnaBridge 171:3a7713b1edbc 342
AnnaBridge 171:3a7713b1edbc 343 /*! @}*/
AnnaBridge 171:3a7713b1edbc 344
AnnaBridge 171:3a7713b1edbc 345 #if defined(__cplusplus)
AnnaBridge 171:3a7713b1edbc 346 }
AnnaBridge 171:3a7713b1edbc 347 #endif
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /*! @}*/
AnnaBridge 171:3a7713b1edbc 350
AnnaBridge 171:3a7713b1edbc 351 #endif /* _FSL_LPTMR_H_ */