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TARGET_K64F/TOOLCHAIN_IAR/fsl_dspi.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 3 | * Copyright 2016-2017 NXP |
AnnaBridge | 171:3a7713b1edbc | 4 | * |
AnnaBridge | 171:3a7713b1edbc | 5 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 6 | * are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 9 | * of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 10 | * |
AnnaBridge | 171:3a7713b1edbc | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 12 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 13 | * other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * o Neither the name of the copyright holder nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 16 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 17 | * software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 18 | * |
AnnaBridge | 171:3a7713b1edbc | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 29 | */ |
AnnaBridge | 171:3a7713b1edbc | 30 | #ifndef _FSL_DSPI_H_ |
AnnaBridge | 171:3a7713b1edbc | 31 | #define _FSL_DSPI_H_ |
AnnaBridge | 171:3a7713b1edbc | 32 | |
AnnaBridge | 171:3a7713b1edbc | 33 | #include "fsl_common.h" |
AnnaBridge | 171:3a7713b1edbc | 34 | |
AnnaBridge | 171:3a7713b1edbc | 35 | /*! |
AnnaBridge | 171:3a7713b1edbc | 36 | * @addtogroup dspi_driver |
AnnaBridge | 171:3a7713b1edbc | 37 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 38 | */ |
AnnaBridge | 171:3a7713b1edbc | 39 | |
AnnaBridge | 171:3a7713b1edbc | 40 | /********************************************************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 41 | * Definitions |
AnnaBridge | 171:3a7713b1edbc | 42 | *********************************************************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 43 | |
AnnaBridge | 171:3a7713b1edbc | 44 | /*! @name Driver version */ |
AnnaBridge | 171:3a7713b1edbc | 45 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 46 | /*! @brief DSPI driver version 2.2.0. */ |
AnnaBridge | 171:3a7713b1edbc | 47 | #define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0)) |
AnnaBridge | 171:3a7713b1edbc | 48 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | #ifndef DSPI_DUMMY_DATA |
AnnaBridge | 171:3a7713b1edbc | 51 | /*! @brief DSPI dummy data if there is no Tx data.*/ |
AnnaBridge | 171:3a7713b1edbc | 52 | #define DSPI_DUMMY_DATA (0x00U) /*!< Dummy data used for Tx if there is no txData. */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #endif |
AnnaBridge | 171:3a7713b1edbc | 54 | |
AnnaBridge | 171:3a7713b1edbc | 55 | /*! @brief Status for the DSPI driver.*/ |
AnnaBridge | 171:3a7713b1edbc | 56 | enum _dspi_status |
AnnaBridge | 171:3a7713b1edbc | 57 | { |
AnnaBridge | 171:3a7713b1edbc | 58 | kStatus_DSPI_Busy = MAKE_STATUS(kStatusGroup_DSPI, 0), /*!< DSPI transfer is busy.*/ |
AnnaBridge | 171:3a7713b1edbc | 59 | kStatus_DSPI_Error = MAKE_STATUS(kStatusGroup_DSPI, 1), /*!< DSPI driver error. */ |
AnnaBridge | 171:3a7713b1edbc | 60 | kStatus_DSPI_Idle = MAKE_STATUS(kStatusGroup_DSPI, 2), /*!< DSPI is idle.*/ |
AnnaBridge | 171:3a7713b1edbc | 61 | kStatus_DSPI_OutOfRange = MAKE_STATUS(kStatusGroup_DSPI, 3) /*!< DSPI transfer out of range. */ |
AnnaBridge | 171:3a7713b1edbc | 62 | }; |
AnnaBridge | 171:3a7713b1edbc | 63 | |
AnnaBridge | 171:3a7713b1edbc | 64 | /*! @brief DSPI status flags in SPIx_SR register.*/ |
AnnaBridge | 171:3a7713b1edbc | 65 | enum _dspi_flags |
AnnaBridge | 171:3a7713b1edbc | 66 | { |
AnnaBridge | 171:3a7713b1edbc | 67 | kDSPI_TxCompleteFlag = SPI_SR_TCF_MASK, /*!< Transfer Complete Flag. */ |
AnnaBridge | 171:3a7713b1edbc | 68 | kDSPI_EndOfQueueFlag = SPI_SR_EOQF_MASK, /*!< End of Queue Flag.*/ |
AnnaBridge | 171:3a7713b1edbc | 69 | kDSPI_TxFifoUnderflowFlag = SPI_SR_TFUF_MASK, /*!< Transmit FIFO Underflow Flag.*/ |
AnnaBridge | 171:3a7713b1edbc | 70 | kDSPI_TxFifoFillRequestFlag = SPI_SR_TFFF_MASK, /*!< Transmit FIFO Fill Flag.*/ |
AnnaBridge | 171:3a7713b1edbc | 71 | kDSPI_RxFifoOverflowFlag = SPI_SR_RFOF_MASK, /*!< Receive FIFO Overflow Flag.*/ |
AnnaBridge | 171:3a7713b1edbc | 72 | kDSPI_RxFifoDrainRequestFlag = SPI_SR_RFDF_MASK, /*!< Receive FIFO Drain Flag.*/ |
AnnaBridge | 171:3a7713b1edbc | 73 | kDSPI_TxAndRxStatusFlag = SPI_SR_TXRXS_MASK, /*!< The module is in Stopped/Running state.*/ |
AnnaBridge | 171:3a7713b1edbc | 74 | kDSPI_AllStatusFlag = SPI_SR_TCF_MASK | SPI_SR_EOQF_MASK | SPI_SR_TFUF_MASK | SPI_SR_TFFF_MASK | SPI_SR_RFOF_MASK | |
AnnaBridge | 171:3a7713b1edbc | 75 | SPI_SR_RFDF_MASK | SPI_SR_TXRXS_MASK /*!< All statuses above.*/ |
AnnaBridge | 171:3a7713b1edbc | 76 | }; |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | /*! @brief DSPI interrupt source.*/ |
AnnaBridge | 171:3a7713b1edbc | 79 | enum _dspi_interrupt_enable |
AnnaBridge | 171:3a7713b1edbc | 80 | { |
AnnaBridge | 171:3a7713b1edbc | 81 | kDSPI_TxCompleteInterruptEnable = SPI_RSER_TCF_RE_MASK, /*!< TCF interrupt enable.*/ |
AnnaBridge | 171:3a7713b1edbc | 82 | kDSPI_EndOfQueueInterruptEnable = SPI_RSER_EOQF_RE_MASK, /*!< EOQF interrupt enable.*/ |
AnnaBridge | 171:3a7713b1edbc | 83 | kDSPI_TxFifoUnderflowInterruptEnable = SPI_RSER_TFUF_RE_MASK, /*!< TFUF interrupt enable.*/ |
AnnaBridge | 171:3a7713b1edbc | 84 | kDSPI_TxFifoFillRequestInterruptEnable = SPI_RSER_TFFF_RE_MASK, /*!< TFFF interrupt enable, DMA disable.*/ |
AnnaBridge | 171:3a7713b1edbc | 85 | kDSPI_RxFifoOverflowInterruptEnable = SPI_RSER_RFOF_RE_MASK, /*!< RFOF interrupt enable.*/ |
AnnaBridge | 171:3a7713b1edbc | 86 | kDSPI_RxFifoDrainRequestInterruptEnable = SPI_RSER_RFDF_RE_MASK, /*!< RFDF interrupt enable, DMA disable.*/ |
AnnaBridge | 171:3a7713b1edbc | 87 | kDSPI_AllInterruptEnable = SPI_RSER_TCF_RE_MASK | SPI_RSER_EOQF_RE_MASK | SPI_RSER_TFUF_RE_MASK | |
AnnaBridge | 171:3a7713b1edbc | 88 | SPI_RSER_TFFF_RE_MASK | SPI_RSER_RFOF_RE_MASK | SPI_RSER_RFDF_RE_MASK |
AnnaBridge | 171:3a7713b1edbc | 89 | /*!< All above interrupts enable.*/ |
AnnaBridge | 171:3a7713b1edbc | 90 | }; |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | /*! @brief DSPI DMA source.*/ |
AnnaBridge | 171:3a7713b1edbc | 93 | enum _dspi_dma_enable |
AnnaBridge | 171:3a7713b1edbc | 94 | { |
AnnaBridge | 171:3a7713b1edbc | 95 | kDSPI_TxDmaEnable = (SPI_RSER_TFFF_RE_MASK | SPI_RSER_TFFF_DIRS_MASK), /*!< TFFF flag generates DMA requests. |
AnnaBridge | 171:3a7713b1edbc | 96 | No Tx interrupt request. */ |
AnnaBridge | 171:3a7713b1edbc | 97 | kDSPI_RxDmaEnable = (SPI_RSER_RFDF_RE_MASK | SPI_RSER_RFDF_DIRS_MASK) /*!< RFDF flag generates DMA requests. |
AnnaBridge | 171:3a7713b1edbc | 98 | No Rx interrupt request. */ |
AnnaBridge | 171:3a7713b1edbc | 99 | }; |
AnnaBridge | 171:3a7713b1edbc | 100 | |
AnnaBridge | 171:3a7713b1edbc | 101 | /*! @brief DSPI master or slave mode configuration.*/ |
AnnaBridge | 171:3a7713b1edbc | 102 | typedef enum _dspi_master_slave_mode |
AnnaBridge | 171:3a7713b1edbc | 103 | { |
AnnaBridge | 171:3a7713b1edbc | 104 | kDSPI_Master = 1U, /*!< DSPI peripheral operates in master mode.*/ |
AnnaBridge | 171:3a7713b1edbc | 105 | kDSPI_Slave = 0U /*!< DSPI peripheral operates in slave mode.*/ |
AnnaBridge | 171:3a7713b1edbc | 106 | } dspi_master_slave_mode_t; |
AnnaBridge | 171:3a7713b1edbc | 107 | |
AnnaBridge | 171:3a7713b1edbc | 108 | /*! |
AnnaBridge | 171:3a7713b1edbc | 109 | * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is |
AnnaBridge | 171:3a7713b1edbc | 110 | * valid |
AnnaBridge | 171:3a7713b1edbc | 111 | * only when the CPHA bit in the CTAR register is 0. |
AnnaBridge | 171:3a7713b1edbc | 112 | */ |
AnnaBridge | 171:3a7713b1edbc | 113 | typedef enum _dspi_master_sample_point |
AnnaBridge | 171:3a7713b1edbc | 114 | { |
AnnaBridge | 171:3a7713b1edbc | 115 | kDSPI_SckToSin0Clock = 0U, /*!< 0 system clocks between SCK edge and SIN sample.*/ |
AnnaBridge | 171:3a7713b1edbc | 116 | kDSPI_SckToSin1Clock = 1U, /*!< 1 system clock between SCK edge and SIN sample.*/ |
AnnaBridge | 171:3a7713b1edbc | 117 | kDSPI_SckToSin2Clock = 2U /*!< 2 system clocks between SCK edge and SIN sample.*/ |
AnnaBridge | 171:3a7713b1edbc | 118 | } dspi_master_sample_point_t; |
AnnaBridge | 171:3a7713b1edbc | 119 | |
AnnaBridge | 171:3a7713b1edbc | 120 | /*! @brief DSPI Peripheral Chip Select (Pcs) configuration (which Pcs to configure).*/ |
AnnaBridge | 171:3a7713b1edbc | 121 | typedef enum _dspi_which_pcs_config |
AnnaBridge | 171:3a7713b1edbc | 122 | { |
AnnaBridge | 171:3a7713b1edbc | 123 | kDSPI_Pcs0 = 1U << 0, /*!< Pcs[0] */ |
AnnaBridge | 171:3a7713b1edbc | 124 | kDSPI_Pcs1 = 1U << 1, /*!< Pcs[1] */ |
AnnaBridge | 171:3a7713b1edbc | 125 | kDSPI_Pcs2 = 1U << 2, /*!< Pcs[2] */ |
AnnaBridge | 171:3a7713b1edbc | 126 | kDSPI_Pcs3 = 1U << 3, /*!< Pcs[3] */ |
AnnaBridge | 171:3a7713b1edbc | 127 | kDSPI_Pcs4 = 1U << 4, /*!< Pcs[4] */ |
AnnaBridge | 171:3a7713b1edbc | 128 | kDSPI_Pcs5 = 1U << 5 /*!< Pcs[5] */ |
AnnaBridge | 171:3a7713b1edbc | 129 | } dspi_which_pcs_t; |
AnnaBridge | 171:3a7713b1edbc | 130 | |
AnnaBridge | 171:3a7713b1edbc | 131 | /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity configuration.*/ |
AnnaBridge | 171:3a7713b1edbc | 132 | typedef enum _dspi_pcs_polarity_config |
AnnaBridge | 171:3a7713b1edbc | 133 | { |
AnnaBridge | 171:3a7713b1edbc | 134 | kDSPI_PcsActiveHigh = 0U, /*!< Pcs Active High (idles low). */ |
AnnaBridge | 171:3a7713b1edbc | 135 | kDSPI_PcsActiveLow = 1U /*!< Pcs Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 136 | } dspi_pcs_polarity_config_t; |
AnnaBridge | 171:3a7713b1edbc | 137 | |
AnnaBridge | 171:3a7713b1edbc | 138 | /*! @brief DSPI Peripheral Chip Select (Pcs) Polarity.*/ |
AnnaBridge | 171:3a7713b1edbc | 139 | enum _dspi_pcs_polarity |
AnnaBridge | 171:3a7713b1edbc | 140 | { |
AnnaBridge | 171:3a7713b1edbc | 141 | kDSPI_Pcs0ActiveLow = 1U << 0, /*!< Pcs0 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 142 | kDSPI_Pcs1ActiveLow = 1U << 1, /*!< Pcs1 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 143 | kDSPI_Pcs2ActiveLow = 1U << 2, /*!< Pcs2 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 144 | kDSPI_Pcs3ActiveLow = 1U << 3, /*!< Pcs3 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 145 | kDSPI_Pcs4ActiveLow = 1U << 4, /*!< Pcs4 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 146 | kDSPI_Pcs5ActiveLow = 1U << 5, /*!< Pcs5 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 147 | kDSPI_PcsAllActiveLow = 0xFFU /*!< Pcs0 to Pcs5 Active Low (idles high). */ |
AnnaBridge | 171:3a7713b1edbc | 148 | }; |
AnnaBridge | 171:3a7713b1edbc | 149 | |
AnnaBridge | 171:3a7713b1edbc | 150 | /*! @brief DSPI clock polarity configuration for a given CTAR.*/ |
AnnaBridge | 171:3a7713b1edbc | 151 | typedef enum _dspi_clock_polarity |
AnnaBridge | 171:3a7713b1edbc | 152 | { |
AnnaBridge | 171:3a7713b1edbc | 153 | kDSPI_ClockPolarityActiveHigh = 0U, /*!< CPOL=0. Active-high DSPI clock (idles low).*/ |
AnnaBridge | 171:3a7713b1edbc | 154 | kDSPI_ClockPolarityActiveLow = 1U /*!< CPOL=1. Active-low DSPI clock (idles high).*/ |
AnnaBridge | 171:3a7713b1edbc | 155 | } dspi_clock_polarity_t; |
AnnaBridge | 171:3a7713b1edbc | 156 | |
AnnaBridge | 171:3a7713b1edbc | 157 | /*! @brief DSPI clock phase configuration for a given CTAR.*/ |
AnnaBridge | 171:3a7713b1edbc | 158 | typedef enum _dspi_clock_phase |
AnnaBridge | 171:3a7713b1edbc | 159 | { |
AnnaBridge | 171:3a7713b1edbc | 160 | kDSPI_ClockPhaseFirstEdge = 0U, /*!< CPHA=0. Data is captured on the leading edge of the SCK and changed on the |
AnnaBridge | 171:3a7713b1edbc | 161 | following edge.*/ |
AnnaBridge | 171:3a7713b1edbc | 162 | kDSPI_ClockPhaseSecondEdge = 1U /*!< CPHA=1. Data is changed on the leading edge of the SCK and captured on the |
AnnaBridge | 171:3a7713b1edbc | 163 | following edge.*/ |
AnnaBridge | 171:3a7713b1edbc | 164 | } dspi_clock_phase_t; |
AnnaBridge | 171:3a7713b1edbc | 165 | |
AnnaBridge | 171:3a7713b1edbc | 166 | /*! @brief DSPI data shifter direction options for a given CTAR.*/ |
AnnaBridge | 171:3a7713b1edbc | 167 | typedef enum _dspi_shift_direction |
AnnaBridge | 171:3a7713b1edbc | 168 | { |
AnnaBridge | 171:3a7713b1edbc | 169 | kDSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit.*/ |
AnnaBridge | 171:3a7713b1edbc | 170 | kDSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. |
AnnaBridge | 171:3a7713b1edbc | 171 | Shifting out of LSB is not supported for slave */ |
AnnaBridge | 171:3a7713b1edbc | 172 | } dspi_shift_direction_t; |
AnnaBridge | 171:3a7713b1edbc | 173 | |
AnnaBridge | 171:3a7713b1edbc | 174 | /*! @brief DSPI delay type selection.*/ |
AnnaBridge | 171:3a7713b1edbc | 175 | typedef enum _dspi_delay_type |
AnnaBridge | 171:3a7713b1edbc | 176 | { |
AnnaBridge | 171:3a7713b1edbc | 177 | kDSPI_PcsToSck = 1U, /*!< Pcs-to-SCK delay. */ |
AnnaBridge | 171:3a7713b1edbc | 178 | kDSPI_LastSckToPcs, /*!< The last SCK edge to Pcs delay. */ |
AnnaBridge | 171:3a7713b1edbc | 179 | kDSPI_BetweenTransfer /*!< Delay between transfers. */ |
AnnaBridge | 171:3a7713b1edbc | 180 | } dspi_delay_type_t; |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | /*! @brief DSPI Clock and Transfer Attributes Register (CTAR) selection.*/ |
AnnaBridge | 171:3a7713b1edbc | 183 | typedef enum _dspi_ctar_selection |
AnnaBridge | 171:3a7713b1edbc | 184 | { |
AnnaBridge | 171:3a7713b1edbc | 185 | kDSPI_Ctar0 = 0U, /*!< CTAR0 selection option for master or slave mode; note that CTAR0 and CTAR0_SLAVE are the |
AnnaBridge | 171:3a7713b1edbc | 186 | same register address. */ |
AnnaBridge | 171:3a7713b1edbc | 187 | kDSPI_Ctar1 = 1U, /*!< CTAR1 selection option for master mode only. */ |
AnnaBridge | 171:3a7713b1edbc | 188 | kDSPI_Ctar2 = 2U, /*!< CTAR2 selection option for master mode only; note that some devices do not support CTAR2. */ |
AnnaBridge | 171:3a7713b1edbc | 189 | kDSPI_Ctar3 = 3U, /*!< CTAR3 selection option for master mode only; note that some devices do not support CTAR3. */ |
AnnaBridge | 171:3a7713b1edbc | 190 | kDSPI_Ctar4 = 4U, /*!< CTAR4 selection option for master mode only; note that some devices do not support CTAR4. */ |
AnnaBridge | 171:3a7713b1edbc | 191 | kDSPI_Ctar5 = 5U, /*!< CTAR5 selection option for master mode only; note that some devices do not support CTAR5. */ |
AnnaBridge | 171:3a7713b1edbc | 192 | kDSPI_Ctar6 = 6U, /*!< CTAR6 selection option for master mode only; note that some devices do not support CTAR6. */ |
AnnaBridge | 171:3a7713b1edbc | 193 | kDSPI_Ctar7 = 7U /*!< CTAR7 selection option for master mode only; note that some devices do not support CTAR7. */ |
AnnaBridge | 171:3a7713b1edbc | 194 | } dspi_ctar_selection_t; |
AnnaBridge | 171:3a7713b1edbc | 195 | |
AnnaBridge | 171:3a7713b1edbc | 196 | #define DSPI_MASTER_CTAR_SHIFT (0U) /*!< DSPI master CTAR shift macro; used internally. */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define DSPI_MASTER_CTAR_MASK (0x0FU) /*!< DSPI master CTAR mask macro; used internally. */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define DSPI_MASTER_PCS_SHIFT (4U) /*!< DSPI master PCS shift macro; used internally. */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define DSPI_MASTER_PCS_MASK (0xF0U) /*!< DSPI master PCS mask macro; used internally. */ |
AnnaBridge | 171:3a7713b1edbc | 200 | /*! @brief Use this enumeration for the DSPI master transfer configFlags. */ |
AnnaBridge | 171:3a7713b1edbc | 201 | enum _dspi_transfer_config_flag_for_master |
AnnaBridge | 171:3a7713b1edbc | 202 | { |
AnnaBridge | 171:3a7713b1edbc | 203 | kDSPI_MasterCtar0 = 0U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR0 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 204 | kDSPI_MasterCtar1 = 1U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR1 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 205 | kDSPI_MasterCtar2 = 2U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR2 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 206 | kDSPI_MasterCtar3 = 3U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR3 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 207 | kDSPI_MasterCtar4 = 4U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR4 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 208 | kDSPI_MasterCtar5 = 5U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR5 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 209 | kDSPI_MasterCtar6 = 6U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR6 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 210 | kDSPI_MasterCtar7 = 7U << DSPI_MASTER_CTAR_SHIFT, /*!< DSPI master transfer use CTAR7 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 211 | |
AnnaBridge | 171:3a7713b1edbc | 212 | kDSPI_MasterPcs0 = 0U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS0 signal. */ |
AnnaBridge | 171:3a7713b1edbc | 213 | kDSPI_MasterPcs1 = 1U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS1 signal. */ |
AnnaBridge | 171:3a7713b1edbc | 214 | kDSPI_MasterPcs2 = 2U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS2 signal.*/ |
AnnaBridge | 171:3a7713b1edbc | 215 | kDSPI_MasterPcs3 = 3U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS3 signal. */ |
AnnaBridge | 171:3a7713b1edbc | 216 | kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */ |
AnnaBridge | 171:3a7713b1edbc | 217 | kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */ |
AnnaBridge | 171:3a7713b1edbc | 220 | kDSPI_MasterActiveAfterTransfer = |
AnnaBridge | 171:3a7713b1edbc | 221 | 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ |
AnnaBridge | 171:3a7713b1edbc | 222 | }; |
AnnaBridge | 171:3a7713b1edbc | 223 | |
AnnaBridge | 171:3a7713b1edbc | 224 | #define DSPI_SLAVE_CTAR_SHIFT (0U) /*!< DSPI slave CTAR shift macro; used internally. */ |
AnnaBridge | 171:3a7713b1edbc | 225 | #define DSPI_SLAVE_CTAR_MASK (0x07U) /*!< DSPI slave CTAR mask macro; used internally. */ |
AnnaBridge | 171:3a7713b1edbc | 226 | /*! @brief Use this enumeration for the DSPI slave transfer configFlags. */ |
AnnaBridge | 171:3a7713b1edbc | 227 | enum _dspi_transfer_config_flag_for_slave |
AnnaBridge | 171:3a7713b1edbc | 228 | { |
AnnaBridge | 171:3a7713b1edbc | 229 | kDSPI_SlaveCtar0 = 0U << DSPI_SLAVE_CTAR_SHIFT, /*!< DSPI slave transfer use CTAR0 setting. */ |
AnnaBridge | 171:3a7713b1edbc | 230 | /*!< DSPI slave can only use PCS0. */ |
AnnaBridge | 171:3a7713b1edbc | 231 | }; |
AnnaBridge | 171:3a7713b1edbc | 232 | |
AnnaBridge | 171:3a7713b1edbc | 233 | /*! @brief DSPI transfer state, which is used for DSPI transactional API state machine. */ |
AnnaBridge | 171:3a7713b1edbc | 234 | enum _dspi_transfer_state |
AnnaBridge | 171:3a7713b1edbc | 235 | { |
AnnaBridge | 171:3a7713b1edbc | 236 | kDSPI_Idle = 0x0U, /*!< Nothing in the transmitter/receiver. */ |
AnnaBridge | 171:3a7713b1edbc | 237 | kDSPI_Busy, /*!< Transfer queue is not finished. */ |
AnnaBridge | 171:3a7713b1edbc | 238 | kDSPI_Error /*!< Transfer error. */ |
AnnaBridge | 171:3a7713b1edbc | 239 | }; |
AnnaBridge | 171:3a7713b1edbc | 240 | |
AnnaBridge | 171:3a7713b1edbc | 241 | /*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/ |
AnnaBridge | 171:3a7713b1edbc | 242 | typedef struct _dspi_command_data_config |
AnnaBridge | 171:3a7713b1edbc | 243 | { |
AnnaBridge | 171:3a7713b1edbc | 244 | bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/ |
AnnaBridge | 171:3a7713b1edbc | 245 | dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes |
AnnaBridge | 171:3a7713b1edbc | 246 | Register (CTAR) to use for CTAS.*/ |
AnnaBridge | 171:3a7713b1edbc | 247 | dspi_which_pcs_t whichPcs; /*!< The desired PCS signal to use for the data transfer.*/ |
AnnaBridge | 171:3a7713b1edbc | 248 | bool isEndOfQueue; /*!< Signals that the current transfer is the last in the queue.*/ |
AnnaBridge | 171:3a7713b1edbc | 249 | bool clearTransferCount; /*!< Clears the SPI Transfer Counter (SPI_TCNT) before transmission starts.*/ |
AnnaBridge | 171:3a7713b1edbc | 250 | } dspi_command_data_config_t; |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | /*! @brief DSPI master ctar configuration structure.*/ |
AnnaBridge | 171:3a7713b1edbc | 253 | typedef struct _dspi_master_ctar_config |
AnnaBridge | 171:3a7713b1edbc | 254 | { |
AnnaBridge | 171:3a7713b1edbc | 255 | uint32_t baudRate; /*!< Baud Rate for DSPI. */ |
AnnaBridge | 171:3a7713b1edbc | 256 | uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ |
AnnaBridge | 171:3a7713b1edbc | 257 | dspi_clock_polarity_t cpol; /*!< Clock polarity. */ |
AnnaBridge | 171:3a7713b1edbc | 258 | dspi_clock_phase_t cpha; /*!< Clock phase. */ |
AnnaBridge | 171:3a7713b1edbc | 259 | dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */ |
AnnaBridge | 171:3a7713b1edbc | 260 | |
AnnaBridge | 171:3a7713b1edbc | 261 | uint32_t pcsToSckDelayInNanoSec; /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum |
AnnaBridge | 171:3a7713b1edbc | 262 | delay. It also sets the boundary value if out of range.*/ |
AnnaBridge | 171:3a7713b1edbc | 263 | uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the |
AnnaBridge | 171:3a7713b1edbc | 264 | minimum delay. It also sets the boundary value if out of range.*/ |
AnnaBridge | 171:3a7713b1edbc | 265 | |
AnnaBridge | 171:3a7713b1edbc | 266 | uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum |
AnnaBridge | 171:3a7713b1edbc | 267 | delay. It also sets the boundary value if out of range.*/ |
AnnaBridge | 171:3a7713b1edbc | 268 | } dspi_master_ctar_config_t; |
AnnaBridge | 171:3a7713b1edbc | 269 | |
AnnaBridge | 171:3a7713b1edbc | 270 | /*! @brief DSPI master configuration structure.*/ |
AnnaBridge | 171:3a7713b1edbc | 271 | typedef struct _dspi_master_config |
AnnaBridge | 171:3a7713b1edbc | 272 | { |
AnnaBridge | 171:3a7713b1edbc | 273 | dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ |
AnnaBridge | 171:3a7713b1edbc | 274 | dspi_master_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ |
AnnaBridge | 171:3a7713b1edbc | 275 | |
AnnaBridge | 171:3a7713b1edbc | 276 | dspi_which_pcs_t whichPcs; /*!< The desired Peripheral Chip Select (pcs). */ |
AnnaBridge | 171:3a7713b1edbc | 277 | dspi_pcs_polarity_config_t pcsActiveHighOrLow; /*!< The desired PCS active high or low. */ |
AnnaBridge | 171:3a7713b1edbc | 278 | |
AnnaBridge | 171:3a7713b1edbc | 279 | bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only |
AnnaBridge | 171:3a7713b1edbc | 280 | supported for CPHA = 1.*/ |
AnnaBridge | 171:3a7713b1edbc | 281 | bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming |
AnnaBridge | 171:3a7713b1edbc | 282 | data is ignored and the data from the transfer that generated the overflow |
AnnaBridge | 171:3a7713b1edbc | 283 | is also ignored. If ROOE = 1, the incoming data is shifted to the |
AnnaBridge | 171:3a7713b1edbc | 284 | shift register. */ |
AnnaBridge | 171:3a7713b1edbc | 285 | |
AnnaBridge | 171:3a7713b1edbc | 286 | bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ |
AnnaBridge | 171:3a7713b1edbc | 287 | dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer |
AnnaBridge | 171:3a7713b1edbc | 288 | Format. It's valid only when CPHA=0. */ |
AnnaBridge | 171:3a7713b1edbc | 289 | } dspi_master_config_t; |
AnnaBridge | 171:3a7713b1edbc | 290 | |
AnnaBridge | 171:3a7713b1edbc | 291 | /*! @brief DSPI slave ctar configuration structure.*/ |
AnnaBridge | 171:3a7713b1edbc | 292 | typedef struct _dspi_slave_ctar_config |
AnnaBridge | 171:3a7713b1edbc | 293 | { |
AnnaBridge | 171:3a7713b1edbc | 294 | uint32_t bitsPerFrame; /*!< Bits per frame, minimum 4, maximum 16.*/ |
AnnaBridge | 171:3a7713b1edbc | 295 | dspi_clock_polarity_t cpol; /*!< Clock polarity. */ |
AnnaBridge | 171:3a7713b1edbc | 296 | dspi_clock_phase_t cpha; /*!< Clock phase. */ |
AnnaBridge | 171:3a7713b1edbc | 297 | /*!< Slave only supports MSB and does not support LSB.*/ |
AnnaBridge | 171:3a7713b1edbc | 298 | } dspi_slave_ctar_config_t; |
AnnaBridge | 171:3a7713b1edbc | 299 | |
AnnaBridge | 171:3a7713b1edbc | 300 | /*! @brief DSPI slave configuration structure.*/ |
AnnaBridge | 171:3a7713b1edbc | 301 | typedef struct _dspi_slave_config |
AnnaBridge | 171:3a7713b1edbc | 302 | { |
AnnaBridge | 171:3a7713b1edbc | 303 | dspi_ctar_selection_t whichCtar; /*!< The desired CTAR to use. */ |
AnnaBridge | 171:3a7713b1edbc | 304 | dspi_slave_ctar_config_t ctarConfig; /*!< Set the ctarConfig to the desired CTAR. */ |
AnnaBridge | 171:3a7713b1edbc | 305 | |
AnnaBridge | 171:3a7713b1edbc | 306 | bool enableContinuousSCK; /*!< CONT_SCKE, continuous SCK enable. Note that the continuous SCK is only |
AnnaBridge | 171:3a7713b1edbc | 307 | supported for CPHA = 1.*/ |
AnnaBridge | 171:3a7713b1edbc | 308 | bool enableRxFifoOverWrite; /*!< ROOE, receive FIFO overflow overwrite enable. If ROOE = 0, the incoming |
AnnaBridge | 171:3a7713b1edbc | 309 | data is ignored and the data from the transfer that generated the overflow |
AnnaBridge | 171:3a7713b1edbc | 310 | is also ignored. If ROOE = 1, the incoming data is shifted to the |
AnnaBridge | 171:3a7713b1edbc | 311 | shift register. */ |
AnnaBridge | 171:3a7713b1edbc | 312 | bool enableModifiedTimingFormat; /*!< Enables a modified transfer format to be used if true.*/ |
AnnaBridge | 171:3a7713b1edbc | 313 | dspi_master_sample_point_t samplePoint; /*!< Controls when the module master samples SIN in the Modified Transfer |
AnnaBridge | 171:3a7713b1edbc | 314 | Format. It's valid only when CPHA=0. */ |
AnnaBridge | 171:3a7713b1edbc | 315 | } dspi_slave_config_t; |
AnnaBridge | 171:3a7713b1edbc | 316 | |
AnnaBridge | 171:3a7713b1edbc | 317 | /*! |
AnnaBridge | 171:3a7713b1edbc | 318 | * @brief Forward declaration of the _dspi_master_handle typedefs. |
AnnaBridge | 171:3a7713b1edbc | 319 | */ |
AnnaBridge | 171:3a7713b1edbc | 320 | typedef struct _dspi_master_handle dspi_master_handle_t; |
AnnaBridge | 171:3a7713b1edbc | 321 | |
AnnaBridge | 171:3a7713b1edbc | 322 | /*! |
AnnaBridge | 171:3a7713b1edbc | 323 | * @brief Forward declaration of the _dspi_slave_handle typedefs. |
AnnaBridge | 171:3a7713b1edbc | 324 | */ |
AnnaBridge | 171:3a7713b1edbc | 325 | typedef struct _dspi_slave_handle dspi_slave_handle_t; |
AnnaBridge | 171:3a7713b1edbc | 326 | |
AnnaBridge | 171:3a7713b1edbc | 327 | /*! |
AnnaBridge | 171:3a7713b1edbc | 328 | * @brief Completion callback function pointer type. |
AnnaBridge | 171:3a7713b1edbc | 329 | * |
AnnaBridge | 171:3a7713b1edbc | 330 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 331 | * @param handle Pointer to the handle for the DSPI master. |
AnnaBridge | 171:3a7713b1edbc | 332 | * @param status Success or error code describing whether the transfer completed. |
AnnaBridge | 171:3a7713b1edbc | 333 | * @param userData Arbitrary pointer-dataSized value passed from the application. |
AnnaBridge | 171:3a7713b1edbc | 334 | */ |
AnnaBridge | 171:3a7713b1edbc | 335 | typedef void (*dspi_master_transfer_callback_t)(SPI_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 336 | dspi_master_handle_t *handle, |
AnnaBridge | 171:3a7713b1edbc | 337 | status_t status, |
AnnaBridge | 171:3a7713b1edbc | 338 | void *userData); |
AnnaBridge | 171:3a7713b1edbc | 339 | /*! |
AnnaBridge | 171:3a7713b1edbc | 340 | * @brief Completion callback function pointer type. |
AnnaBridge | 171:3a7713b1edbc | 341 | * |
AnnaBridge | 171:3a7713b1edbc | 342 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 343 | * @param handle Pointer to the handle for the DSPI slave. |
AnnaBridge | 171:3a7713b1edbc | 344 | * @param status Success or error code describing whether the transfer completed. |
AnnaBridge | 171:3a7713b1edbc | 345 | * @param userData Arbitrary pointer-dataSized value passed from the application. |
AnnaBridge | 171:3a7713b1edbc | 346 | */ |
AnnaBridge | 171:3a7713b1edbc | 347 | typedef void (*dspi_slave_transfer_callback_t)(SPI_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 348 | dspi_slave_handle_t *handle, |
AnnaBridge | 171:3a7713b1edbc | 349 | status_t status, |
AnnaBridge | 171:3a7713b1edbc | 350 | void *userData); |
AnnaBridge | 171:3a7713b1edbc | 351 | |
AnnaBridge | 171:3a7713b1edbc | 352 | /*! @brief DSPI master/slave transfer structure.*/ |
AnnaBridge | 171:3a7713b1edbc | 353 | typedef struct _dspi_transfer |
AnnaBridge | 171:3a7713b1edbc | 354 | { |
AnnaBridge | 171:3a7713b1edbc | 355 | uint8_t *txData; /*!< Send buffer. */ |
AnnaBridge | 171:3a7713b1edbc | 356 | uint8_t *rxData; /*!< Receive buffer. */ |
AnnaBridge | 171:3a7713b1edbc | 357 | volatile size_t dataSize; /*!< Transfer bytes. */ |
AnnaBridge | 171:3a7713b1edbc | 358 | |
AnnaBridge | 171:3a7713b1edbc | 359 | uint32_t |
AnnaBridge | 171:3a7713b1edbc | 360 | configFlags; /*!< Transfer transfer configuration flags; set from _dspi_transfer_config_flag_for_master if the |
AnnaBridge | 171:3a7713b1edbc | 361 | transfer is used for master or _dspi_transfer_config_flag_for_slave enumeration if the transfer |
AnnaBridge | 171:3a7713b1edbc | 362 | is used for slave.*/ |
AnnaBridge | 171:3a7713b1edbc | 363 | } dspi_transfer_t; |
AnnaBridge | 171:3a7713b1edbc | 364 | |
AnnaBridge | 171:3a7713b1edbc | 365 | /*! @brief DSPI master transfer handle structure used for transactional API. */ |
AnnaBridge | 171:3a7713b1edbc | 366 | struct _dspi_master_handle |
AnnaBridge | 171:3a7713b1edbc | 367 | { |
AnnaBridge | 171:3a7713b1edbc | 368 | uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ |
AnnaBridge | 171:3a7713b1edbc | 369 | volatile uint32_t command; /*!< The desired data command. */ |
AnnaBridge | 171:3a7713b1edbc | 370 | volatile uint32_t lastCommand; /*!< The desired last data command. */ |
AnnaBridge | 171:3a7713b1edbc | 371 | |
AnnaBridge | 171:3a7713b1edbc | 372 | uint8_t fifoSize; /*!< FIFO dataSize. */ |
AnnaBridge | 171:3a7713b1edbc | 373 | |
AnnaBridge | 171:3a7713b1edbc | 374 | volatile bool |
AnnaBridge | 171:3a7713b1edbc | 375 | isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/ |
AnnaBridge | 171:3a7713b1edbc | 376 | volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ |
AnnaBridge | 171:3a7713b1edbc | 377 | |
AnnaBridge | 171:3a7713b1edbc | 378 | uint8_t *volatile txData; /*!< Send buffer. */ |
AnnaBridge | 171:3a7713b1edbc | 379 | uint8_t *volatile rxData; /*!< Receive buffer. */ |
AnnaBridge | 171:3a7713b1edbc | 380 | volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ |
AnnaBridge | 171:3a7713b1edbc | 381 | volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ |
AnnaBridge | 171:3a7713b1edbc | 382 | size_t totalByteCount; /*!< A number of transfer bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 383 | |
AnnaBridge | 171:3a7713b1edbc | 384 | volatile uint8_t state; /*!< DSPI transfer state, see _dspi_transfer_state.*/ |
AnnaBridge | 171:3a7713b1edbc | 385 | |
AnnaBridge | 171:3a7713b1edbc | 386 | dspi_master_transfer_callback_t callback; /*!< Completion callback. */ |
AnnaBridge | 171:3a7713b1edbc | 387 | void *userData; /*!< Callback user data. */ |
AnnaBridge | 171:3a7713b1edbc | 388 | }; |
AnnaBridge | 171:3a7713b1edbc | 389 | |
AnnaBridge | 171:3a7713b1edbc | 390 | /*! @brief DSPI slave transfer handle structure used for the transactional API. */ |
AnnaBridge | 171:3a7713b1edbc | 391 | struct _dspi_slave_handle |
AnnaBridge | 171:3a7713b1edbc | 392 | { |
AnnaBridge | 171:3a7713b1edbc | 393 | uint32_t bitsPerFrame; /*!< The desired number of bits per frame. */ |
AnnaBridge | 171:3a7713b1edbc | 394 | volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/ |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | uint8_t *volatile txData; /*!< Send buffer. */ |
AnnaBridge | 171:3a7713b1edbc | 397 | uint8_t *volatile rxData; /*!< Receive buffer. */ |
AnnaBridge | 171:3a7713b1edbc | 398 | volatile size_t remainingSendByteCount; /*!< A number of bytes remaining to send.*/ |
AnnaBridge | 171:3a7713b1edbc | 399 | volatile size_t remainingReceiveByteCount; /*!< A number of bytes remaining to receive.*/ |
AnnaBridge | 171:3a7713b1edbc | 400 | size_t totalByteCount; /*!< A number of transfer bytes*/ |
AnnaBridge | 171:3a7713b1edbc | 401 | |
AnnaBridge | 171:3a7713b1edbc | 402 | volatile uint8_t state; /*!< DSPI transfer state.*/ |
AnnaBridge | 171:3a7713b1edbc | 403 | |
AnnaBridge | 171:3a7713b1edbc | 404 | volatile uint32_t errorCount; /*!< Error count for slave transfer.*/ |
AnnaBridge | 171:3a7713b1edbc | 405 | |
AnnaBridge | 171:3a7713b1edbc | 406 | dspi_slave_transfer_callback_t callback; /*!< Completion callback. */ |
AnnaBridge | 171:3a7713b1edbc | 407 | void *userData; /*!< Callback user data. */ |
AnnaBridge | 171:3a7713b1edbc | 408 | }; |
AnnaBridge | 171:3a7713b1edbc | 409 | |
AnnaBridge | 171:3a7713b1edbc | 410 | /********************************************************************************************************************** |
AnnaBridge | 171:3a7713b1edbc | 411 | * API |
AnnaBridge | 171:3a7713b1edbc | 412 | *********************************************************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 413 | #if defined(__cplusplus) |
AnnaBridge | 171:3a7713b1edbc | 414 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 415 | #endif /*_cplusplus*/ |
AnnaBridge | 171:3a7713b1edbc | 416 | |
AnnaBridge | 171:3a7713b1edbc | 417 | /*! |
AnnaBridge | 171:3a7713b1edbc | 418 | * @name Initialization and deinitialization |
AnnaBridge | 171:3a7713b1edbc | 419 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 420 | */ |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | /*! |
AnnaBridge | 171:3a7713b1edbc | 423 | * @brief Initializes the DSPI master. |
AnnaBridge | 171:3a7713b1edbc | 424 | * |
AnnaBridge | 171:3a7713b1edbc | 425 | * This function initializes the DSPI master configuration. This is an example use case. |
AnnaBridge | 171:3a7713b1edbc | 426 | * @code |
AnnaBridge | 171:3a7713b1edbc | 427 | * dspi_master_config_t masterConfig; |
AnnaBridge | 171:3a7713b1edbc | 428 | * masterConfig.whichCtar = kDSPI_Ctar0; |
AnnaBridge | 171:3a7713b1edbc | 429 | * masterConfig.ctarConfig.baudRate = 500000000U; |
AnnaBridge | 171:3a7713b1edbc | 430 | * masterConfig.ctarConfig.bitsPerFrame = 8; |
AnnaBridge | 171:3a7713b1edbc | 431 | * masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; |
AnnaBridge | 171:3a7713b1edbc | 432 | * masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; |
AnnaBridge | 171:3a7713b1edbc | 433 | * masterConfig.ctarConfig.direction = kDSPI_MsbFirst; |
AnnaBridge | 171:3a7713b1edbc | 434 | * masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; |
AnnaBridge | 171:3a7713b1edbc | 435 | * masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; |
AnnaBridge | 171:3a7713b1edbc | 436 | * masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / masterConfig.ctarConfig.baudRate ; |
AnnaBridge | 171:3a7713b1edbc | 437 | * masterConfig.whichPcs = kDSPI_Pcs0; |
AnnaBridge | 171:3a7713b1edbc | 438 | * masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveLow; |
AnnaBridge | 171:3a7713b1edbc | 439 | * masterConfig.enableContinuousSCK = false; |
AnnaBridge | 171:3a7713b1edbc | 440 | * masterConfig.enableRxFifoOverWrite = false; |
AnnaBridge | 171:3a7713b1edbc | 441 | * masterConfig.enableModifiedTimingFormat = false; |
AnnaBridge | 171:3a7713b1edbc | 442 | * masterConfig.samplePoint = kDSPI_SckToSin0Clock; |
AnnaBridge | 171:3a7713b1edbc | 443 | * DSPI_MasterInit(base, &masterConfig, srcClock_Hz); |
AnnaBridge | 171:3a7713b1edbc | 444 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 445 | * |
AnnaBridge | 171:3a7713b1edbc | 446 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 447 | * @param masterConfig Pointer to the structure dspi_master_config_t. |
AnnaBridge | 171:3a7713b1edbc | 448 | * @param srcClock_Hz Module source input clock in Hertz. |
AnnaBridge | 171:3a7713b1edbc | 449 | */ |
AnnaBridge | 171:3a7713b1edbc | 450 | void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz); |
AnnaBridge | 171:3a7713b1edbc | 451 | |
AnnaBridge | 171:3a7713b1edbc | 452 | /*! |
AnnaBridge | 171:3a7713b1edbc | 453 | * @brief Sets the dspi_master_config_t structure to default values. |
AnnaBridge | 171:3a7713b1edbc | 454 | * |
AnnaBridge | 171:3a7713b1edbc | 455 | * The purpose of this API is to get the configuration structure initialized for the DSPI_MasterInit(). |
AnnaBridge | 171:3a7713b1edbc | 456 | * Users may use the initialized structure unchanged in the DSPI_MasterInit() or modify the structure |
AnnaBridge | 171:3a7713b1edbc | 457 | * before calling the DSPI_MasterInit(). |
AnnaBridge | 171:3a7713b1edbc | 458 | * Example: |
AnnaBridge | 171:3a7713b1edbc | 459 | * @code |
AnnaBridge | 171:3a7713b1edbc | 460 | * dspi_master_config_t masterConfig; |
AnnaBridge | 171:3a7713b1edbc | 461 | * DSPI_MasterGetDefaultConfig(&masterConfig); |
AnnaBridge | 171:3a7713b1edbc | 462 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 463 | * @param masterConfig pointer to dspi_master_config_t structure |
AnnaBridge | 171:3a7713b1edbc | 464 | */ |
AnnaBridge | 171:3a7713b1edbc | 465 | void DSPI_MasterGetDefaultConfig(dspi_master_config_t *masterConfig); |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | /*! |
AnnaBridge | 171:3a7713b1edbc | 468 | * @brief DSPI slave configuration. |
AnnaBridge | 171:3a7713b1edbc | 469 | * |
AnnaBridge | 171:3a7713b1edbc | 470 | * This function initializes the DSPI slave configuration. This is an example use case. |
AnnaBridge | 171:3a7713b1edbc | 471 | * @code |
AnnaBridge | 171:3a7713b1edbc | 472 | * dspi_slave_config_t slaveConfig; |
AnnaBridge | 171:3a7713b1edbc | 473 | * slaveConfig->whichCtar = kDSPI_Ctar0; |
AnnaBridge | 171:3a7713b1edbc | 474 | * slaveConfig->ctarConfig.bitsPerFrame = 8; |
AnnaBridge | 171:3a7713b1edbc | 475 | * slaveConfig->ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh; |
AnnaBridge | 171:3a7713b1edbc | 476 | * slaveConfig->ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge; |
AnnaBridge | 171:3a7713b1edbc | 477 | * slaveConfig->enableContinuousSCK = false; |
AnnaBridge | 171:3a7713b1edbc | 478 | * slaveConfig->enableRxFifoOverWrite = false; |
AnnaBridge | 171:3a7713b1edbc | 479 | * slaveConfig->enableModifiedTimingFormat = false; |
AnnaBridge | 171:3a7713b1edbc | 480 | * slaveConfig->samplePoint = kDSPI_SckToSin0Clock; |
AnnaBridge | 171:3a7713b1edbc | 481 | * DSPI_SlaveInit(base, &slaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 482 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 483 | * |
AnnaBridge | 171:3a7713b1edbc | 484 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 485 | * @param slaveConfig Pointer to the structure dspi_master_config_t. |
AnnaBridge | 171:3a7713b1edbc | 486 | */ |
AnnaBridge | 171:3a7713b1edbc | 487 | void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 488 | |
AnnaBridge | 171:3a7713b1edbc | 489 | /*! |
AnnaBridge | 171:3a7713b1edbc | 490 | * @brief Sets the dspi_slave_config_t structure to a default value. |
AnnaBridge | 171:3a7713b1edbc | 491 | * |
AnnaBridge | 171:3a7713b1edbc | 492 | * The purpose of this API is to get the configuration structure initialized for the DSPI_SlaveInit(). |
AnnaBridge | 171:3a7713b1edbc | 493 | * Users may use the initialized structure unchanged in the DSPI_SlaveInit() or modify the structure |
AnnaBridge | 171:3a7713b1edbc | 494 | * before calling the DSPI_SlaveInit(). |
AnnaBridge | 171:3a7713b1edbc | 495 | * This is an example. |
AnnaBridge | 171:3a7713b1edbc | 496 | * @code |
AnnaBridge | 171:3a7713b1edbc | 497 | * dspi_slave_config_t slaveConfig; |
AnnaBridge | 171:3a7713b1edbc | 498 | * DSPI_SlaveGetDefaultConfig(&slaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 499 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 500 | * @param slaveConfig Pointer to the dspi_slave_config_t structure. |
AnnaBridge | 171:3a7713b1edbc | 501 | */ |
AnnaBridge | 171:3a7713b1edbc | 502 | void DSPI_SlaveGetDefaultConfig(dspi_slave_config_t *slaveConfig); |
AnnaBridge | 171:3a7713b1edbc | 503 | |
AnnaBridge | 171:3a7713b1edbc | 504 | /*! |
AnnaBridge | 171:3a7713b1edbc | 505 | * @brief De-initializes the DSPI peripheral. Call this API to disable the DSPI clock. |
AnnaBridge | 171:3a7713b1edbc | 506 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 507 | */ |
AnnaBridge | 171:3a7713b1edbc | 508 | void DSPI_Deinit(SPI_Type *base); |
AnnaBridge | 171:3a7713b1edbc | 509 | |
AnnaBridge | 171:3a7713b1edbc | 510 | /*! |
AnnaBridge | 171:3a7713b1edbc | 511 | * @brief Enables the DSPI peripheral and sets the MCR MDIS to 0. |
AnnaBridge | 171:3a7713b1edbc | 512 | * |
AnnaBridge | 171:3a7713b1edbc | 513 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 514 | * @param enable Pass true to enable module, false to disable module. |
AnnaBridge | 171:3a7713b1edbc | 515 | */ |
AnnaBridge | 171:3a7713b1edbc | 516 | static inline void DSPI_Enable(SPI_Type *base, bool enable) |
AnnaBridge | 171:3a7713b1edbc | 517 | { |
AnnaBridge | 171:3a7713b1edbc | 518 | if (enable) |
AnnaBridge | 171:3a7713b1edbc | 519 | { |
AnnaBridge | 171:3a7713b1edbc | 520 | base->MCR &= ~SPI_MCR_MDIS_MASK; |
AnnaBridge | 171:3a7713b1edbc | 521 | } |
AnnaBridge | 171:3a7713b1edbc | 522 | else |
AnnaBridge | 171:3a7713b1edbc | 523 | { |
AnnaBridge | 171:3a7713b1edbc | 524 | base->MCR |= SPI_MCR_MDIS_MASK; |
AnnaBridge | 171:3a7713b1edbc | 525 | } |
AnnaBridge | 171:3a7713b1edbc | 526 | } |
AnnaBridge | 171:3a7713b1edbc | 527 | |
AnnaBridge | 171:3a7713b1edbc | 528 | /*! |
AnnaBridge | 171:3a7713b1edbc | 529 | *@} |
AnnaBridge | 171:3a7713b1edbc | 530 | */ |
AnnaBridge | 171:3a7713b1edbc | 531 | |
AnnaBridge | 171:3a7713b1edbc | 532 | /*! |
AnnaBridge | 171:3a7713b1edbc | 533 | * @name Status |
AnnaBridge | 171:3a7713b1edbc | 534 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 535 | */ |
AnnaBridge | 171:3a7713b1edbc | 536 | |
AnnaBridge | 171:3a7713b1edbc | 537 | /*! |
AnnaBridge | 171:3a7713b1edbc | 538 | * @brief Gets the DSPI status flag state. |
AnnaBridge | 171:3a7713b1edbc | 539 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 540 | * @return DSPI status (in SR register). |
AnnaBridge | 171:3a7713b1edbc | 541 | */ |
AnnaBridge | 171:3a7713b1edbc | 542 | static inline uint32_t DSPI_GetStatusFlags(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 543 | { |
AnnaBridge | 171:3a7713b1edbc | 544 | return (base->SR); |
AnnaBridge | 171:3a7713b1edbc | 545 | } |
AnnaBridge | 171:3a7713b1edbc | 546 | |
AnnaBridge | 171:3a7713b1edbc | 547 | /*! |
AnnaBridge | 171:3a7713b1edbc | 548 | * @brief Clears the DSPI status flag. |
AnnaBridge | 171:3a7713b1edbc | 549 | * |
AnnaBridge | 171:3a7713b1edbc | 550 | * This function clears the desired status bit by using a write-1-to-clear. The user passes in the base and the |
AnnaBridge | 171:3a7713b1edbc | 551 | * desired status bit to clear. The list of status bits is defined in the dspi_status_and_interrupt_request_t. The |
AnnaBridge | 171:3a7713b1edbc | 552 | * function uses these bit positions in its algorithm to clear the desired flag state. |
AnnaBridge | 171:3a7713b1edbc | 553 | * This is an example. |
AnnaBridge | 171:3a7713b1edbc | 554 | * @code |
AnnaBridge | 171:3a7713b1edbc | 555 | * DSPI_ClearStatusFlags(base, kDSPI_TxCompleteFlag|kDSPI_EndOfQueueFlag); |
AnnaBridge | 171:3a7713b1edbc | 556 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 557 | * |
AnnaBridge | 171:3a7713b1edbc | 558 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 559 | * @param statusFlags The status flag used from the type dspi_flags. |
AnnaBridge | 171:3a7713b1edbc | 560 | */ |
AnnaBridge | 171:3a7713b1edbc | 561 | static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags) |
AnnaBridge | 171:3a7713b1edbc | 562 | { |
AnnaBridge | 171:3a7713b1edbc | 563 | base->SR = statusFlags; /*!< The status flags are cleared by writing 1 (w1c).*/ |
AnnaBridge | 171:3a7713b1edbc | 564 | } |
AnnaBridge | 171:3a7713b1edbc | 565 | |
AnnaBridge | 171:3a7713b1edbc | 566 | /*! |
AnnaBridge | 171:3a7713b1edbc | 567 | *@} |
AnnaBridge | 171:3a7713b1edbc | 568 | */ |
AnnaBridge | 171:3a7713b1edbc | 569 | |
AnnaBridge | 171:3a7713b1edbc | 570 | /*! |
AnnaBridge | 171:3a7713b1edbc | 571 | * @name Interrupts |
AnnaBridge | 171:3a7713b1edbc | 572 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 573 | */ |
AnnaBridge | 171:3a7713b1edbc | 574 | |
AnnaBridge | 171:3a7713b1edbc | 575 | /*! |
AnnaBridge | 171:3a7713b1edbc | 576 | * @brief Enables the DSPI interrupts. |
AnnaBridge | 171:3a7713b1edbc | 577 | * |
AnnaBridge | 171:3a7713b1edbc | 578 | * This function configures the various interrupt masks of the DSPI. The parameters are a base and an interrupt mask. |
AnnaBridge | 171:3a7713b1edbc | 579 | * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request. |
AnnaBridge | 171:3a7713b1edbc | 580 | * Do not use this API(write to RSER register) while DSPI is in running state. |
AnnaBridge | 171:3a7713b1edbc | 581 | * |
AnnaBridge | 171:3a7713b1edbc | 582 | * @code |
AnnaBridge | 171:3a7713b1edbc | 583 | * DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); |
AnnaBridge | 171:3a7713b1edbc | 584 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 585 | * |
AnnaBridge | 171:3a7713b1edbc | 586 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 587 | * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. |
AnnaBridge | 171:3a7713b1edbc | 588 | */ |
AnnaBridge | 171:3a7713b1edbc | 589 | void DSPI_EnableInterrupts(SPI_Type *base, uint32_t mask); |
AnnaBridge | 171:3a7713b1edbc | 590 | |
AnnaBridge | 171:3a7713b1edbc | 591 | /*! |
AnnaBridge | 171:3a7713b1edbc | 592 | * @brief Disables the DSPI interrupts. |
AnnaBridge | 171:3a7713b1edbc | 593 | * |
AnnaBridge | 171:3a7713b1edbc | 594 | * @code |
AnnaBridge | 171:3a7713b1edbc | 595 | * DSPI_DisableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable ); |
AnnaBridge | 171:3a7713b1edbc | 596 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 597 | * |
AnnaBridge | 171:3a7713b1edbc | 598 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 599 | * @param mask The interrupt mask; use the enum _dspi_interrupt_enable. |
AnnaBridge | 171:3a7713b1edbc | 600 | */ |
AnnaBridge | 171:3a7713b1edbc | 601 | static inline void DSPI_DisableInterrupts(SPI_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 602 | { |
AnnaBridge | 171:3a7713b1edbc | 603 | base->RSER &= ~mask; |
AnnaBridge | 171:3a7713b1edbc | 604 | } |
AnnaBridge | 171:3a7713b1edbc | 605 | |
AnnaBridge | 171:3a7713b1edbc | 606 | /*! |
AnnaBridge | 171:3a7713b1edbc | 607 | *@} |
AnnaBridge | 171:3a7713b1edbc | 608 | */ |
AnnaBridge | 171:3a7713b1edbc | 609 | |
AnnaBridge | 171:3a7713b1edbc | 610 | /*! |
AnnaBridge | 171:3a7713b1edbc | 611 | * @name DMA Control |
AnnaBridge | 171:3a7713b1edbc | 612 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 613 | */ |
AnnaBridge | 171:3a7713b1edbc | 614 | |
AnnaBridge | 171:3a7713b1edbc | 615 | /*! |
AnnaBridge | 171:3a7713b1edbc | 616 | * @brief Enables the DSPI DMA request. |
AnnaBridge | 171:3a7713b1edbc | 617 | * |
AnnaBridge | 171:3a7713b1edbc | 618 | * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. |
AnnaBridge | 171:3a7713b1edbc | 619 | * @code |
AnnaBridge | 171:3a7713b1edbc | 620 | * DSPI_EnableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); |
AnnaBridge | 171:3a7713b1edbc | 621 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 622 | * |
AnnaBridge | 171:3a7713b1edbc | 623 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 624 | * @param mask The interrupt mask; use the enum dspi_dma_enable. |
AnnaBridge | 171:3a7713b1edbc | 625 | */ |
AnnaBridge | 171:3a7713b1edbc | 626 | static inline void DSPI_EnableDMA(SPI_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 627 | { |
AnnaBridge | 171:3a7713b1edbc | 628 | base->RSER |= mask; |
AnnaBridge | 171:3a7713b1edbc | 629 | } |
AnnaBridge | 171:3a7713b1edbc | 630 | |
AnnaBridge | 171:3a7713b1edbc | 631 | /*! |
AnnaBridge | 171:3a7713b1edbc | 632 | * @brief Disables the DSPI DMA request. |
AnnaBridge | 171:3a7713b1edbc | 633 | * |
AnnaBridge | 171:3a7713b1edbc | 634 | * This function configures the Rx and Tx DMA mask of the DSPI. The parameters are a base and a DMA mask. |
AnnaBridge | 171:3a7713b1edbc | 635 | * @code |
AnnaBridge | 171:3a7713b1edbc | 636 | * SPI_DisableDMA(base, kDSPI_TxDmaEnable | kDSPI_RxDmaEnable); |
AnnaBridge | 171:3a7713b1edbc | 637 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 638 | * |
AnnaBridge | 171:3a7713b1edbc | 639 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 640 | * @param mask The interrupt mask; use the enum dspi_dma_enable. |
AnnaBridge | 171:3a7713b1edbc | 641 | */ |
AnnaBridge | 171:3a7713b1edbc | 642 | static inline void DSPI_DisableDMA(SPI_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 643 | { |
AnnaBridge | 171:3a7713b1edbc | 644 | base->RSER &= ~mask; |
AnnaBridge | 171:3a7713b1edbc | 645 | } |
AnnaBridge | 171:3a7713b1edbc | 646 | |
AnnaBridge | 171:3a7713b1edbc | 647 | /*! |
AnnaBridge | 171:3a7713b1edbc | 648 | * @brief Gets the DSPI master PUSHR data register address for the DMA operation. |
AnnaBridge | 171:3a7713b1edbc | 649 | * |
AnnaBridge | 171:3a7713b1edbc | 650 | * This function gets the DSPI master PUSHR data register address because this value is needed for the DMA operation. |
AnnaBridge | 171:3a7713b1edbc | 651 | * |
AnnaBridge | 171:3a7713b1edbc | 652 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 653 | * @return The DSPI master PUSHR data register address. |
AnnaBridge | 171:3a7713b1edbc | 654 | */ |
AnnaBridge | 171:3a7713b1edbc | 655 | static inline uint32_t DSPI_MasterGetTxRegisterAddress(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 656 | { |
AnnaBridge | 171:3a7713b1edbc | 657 | return (uint32_t) & (base->PUSHR); |
AnnaBridge | 171:3a7713b1edbc | 658 | } |
AnnaBridge | 171:3a7713b1edbc | 659 | |
AnnaBridge | 171:3a7713b1edbc | 660 | /*! |
AnnaBridge | 171:3a7713b1edbc | 661 | * @brief Gets the DSPI slave PUSHR data register address for the DMA operation. |
AnnaBridge | 171:3a7713b1edbc | 662 | * |
AnnaBridge | 171:3a7713b1edbc | 663 | * This function gets the DSPI slave PUSHR data register address as this value is needed for the DMA operation. |
AnnaBridge | 171:3a7713b1edbc | 664 | * |
AnnaBridge | 171:3a7713b1edbc | 665 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 666 | * @return The DSPI slave PUSHR data register address. |
AnnaBridge | 171:3a7713b1edbc | 667 | */ |
AnnaBridge | 171:3a7713b1edbc | 668 | static inline uint32_t DSPI_SlaveGetTxRegisterAddress(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 669 | { |
AnnaBridge | 171:3a7713b1edbc | 670 | return (uint32_t) & (base->PUSHR_SLAVE); |
AnnaBridge | 171:3a7713b1edbc | 671 | } |
AnnaBridge | 171:3a7713b1edbc | 672 | |
AnnaBridge | 171:3a7713b1edbc | 673 | /*! |
AnnaBridge | 171:3a7713b1edbc | 674 | * @brief Gets the DSPI POPR data register address for the DMA operation. |
AnnaBridge | 171:3a7713b1edbc | 675 | * |
AnnaBridge | 171:3a7713b1edbc | 676 | * This function gets the DSPI POPR data register address as this value is needed for the DMA operation. |
AnnaBridge | 171:3a7713b1edbc | 677 | * |
AnnaBridge | 171:3a7713b1edbc | 678 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 679 | * @return The DSPI POPR data register address. |
AnnaBridge | 171:3a7713b1edbc | 680 | */ |
AnnaBridge | 171:3a7713b1edbc | 681 | static inline uint32_t DSPI_GetRxRegisterAddress(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 682 | { |
AnnaBridge | 171:3a7713b1edbc | 683 | return (uint32_t) & (base->POPR); |
AnnaBridge | 171:3a7713b1edbc | 684 | } |
AnnaBridge | 171:3a7713b1edbc | 685 | |
AnnaBridge | 171:3a7713b1edbc | 686 | /*! |
AnnaBridge | 171:3a7713b1edbc | 687 | *@} |
AnnaBridge | 171:3a7713b1edbc | 688 | */ |
AnnaBridge | 171:3a7713b1edbc | 689 | |
AnnaBridge | 171:3a7713b1edbc | 690 | /*! |
AnnaBridge | 171:3a7713b1edbc | 691 | * @name Bus Operations |
AnnaBridge | 171:3a7713b1edbc | 692 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 693 | */ |
AnnaBridge | 171:3a7713b1edbc | 694 | |
AnnaBridge | 171:3a7713b1edbc | 695 | /*! |
AnnaBridge | 171:3a7713b1edbc | 696 | * @brief Configures the DSPI for master or slave. |
AnnaBridge | 171:3a7713b1edbc | 697 | * |
AnnaBridge | 171:3a7713b1edbc | 698 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 699 | * @param mode Mode setting (master or slave) of type dspi_master_slave_mode_t. |
AnnaBridge | 171:3a7713b1edbc | 700 | */ |
AnnaBridge | 171:3a7713b1edbc | 701 | static inline void DSPI_SetMasterSlaveMode(SPI_Type *base, dspi_master_slave_mode_t mode) |
AnnaBridge | 171:3a7713b1edbc | 702 | { |
AnnaBridge | 171:3a7713b1edbc | 703 | base->MCR = (base->MCR & (~SPI_MCR_MSTR_MASK)) | SPI_MCR_MSTR(mode); |
AnnaBridge | 171:3a7713b1edbc | 704 | } |
AnnaBridge | 171:3a7713b1edbc | 705 | |
AnnaBridge | 171:3a7713b1edbc | 706 | /*! |
AnnaBridge | 171:3a7713b1edbc | 707 | * @brief Returns whether the DSPI module is in master mode. |
AnnaBridge | 171:3a7713b1edbc | 708 | * |
AnnaBridge | 171:3a7713b1edbc | 709 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 710 | * @return Returns true if the module is in master mode or false if the module is in slave mode. |
AnnaBridge | 171:3a7713b1edbc | 711 | */ |
AnnaBridge | 171:3a7713b1edbc | 712 | static inline bool DSPI_IsMaster(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 713 | { |
AnnaBridge | 171:3a7713b1edbc | 714 | return (bool)((base->MCR) & SPI_MCR_MSTR_MASK); |
AnnaBridge | 171:3a7713b1edbc | 715 | } |
AnnaBridge | 171:3a7713b1edbc | 716 | /*! |
AnnaBridge | 171:3a7713b1edbc | 717 | * @brief Starts the DSPI transfers and clears HALT bit in MCR. |
AnnaBridge | 171:3a7713b1edbc | 718 | * |
AnnaBridge | 171:3a7713b1edbc | 719 | * This function sets the module to start data transfer in either master or slave mode. |
AnnaBridge | 171:3a7713b1edbc | 720 | * |
AnnaBridge | 171:3a7713b1edbc | 721 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 722 | */ |
AnnaBridge | 171:3a7713b1edbc | 723 | static inline void DSPI_StartTransfer(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 724 | { |
AnnaBridge | 171:3a7713b1edbc | 725 | base->MCR &= ~SPI_MCR_HALT_MASK; |
AnnaBridge | 171:3a7713b1edbc | 726 | } |
AnnaBridge | 171:3a7713b1edbc | 727 | /*! |
AnnaBridge | 171:3a7713b1edbc | 728 | * @brief Stops DSPI transfers and sets the HALT bit in MCR. |
AnnaBridge | 171:3a7713b1edbc | 729 | * |
AnnaBridge | 171:3a7713b1edbc | 730 | * This function stops data transfers in either master or slave modes. |
AnnaBridge | 171:3a7713b1edbc | 731 | * |
AnnaBridge | 171:3a7713b1edbc | 732 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 733 | */ |
AnnaBridge | 171:3a7713b1edbc | 734 | static inline void DSPI_StopTransfer(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 735 | { |
AnnaBridge | 171:3a7713b1edbc | 736 | base->MCR |= SPI_MCR_HALT_MASK; |
AnnaBridge | 171:3a7713b1edbc | 737 | } |
AnnaBridge | 171:3a7713b1edbc | 738 | |
AnnaBridge | 171:3a7713b1edbc | 739 | /*! |
AnnaBridge | 171:3a7713b1edbc | 740 | * @brief Enables or disables the DSPI FIFOs. |
AnnaBridge | 171:3a7713b1edbc | 741 | * |
AnnaBridge | 171:3a7713b1edbc | 742 | * This function allows the caller to disable/enable the Tx and Rx FIFOs independently. |
AnnaBridge | 171:3a7713b1edbc | 743 | * Note that to disable, pass in a logic 0 (false) for the particular FIFO configuration. To enable, |
AnnaBridge | 171:3a7713b1edbc | 744 | * pass in a logic 1 (true). |
AnnaBridge | 171:3a7713b1edbc | 745 | * |
AnnaBridge | 171:3a7713b1edbc | 746 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 747 | * @param enableTxFifo Disables (false) the TX FIFO; Otherwise, enables (true) the TX FIFO |
AnnaBridge | 171:3a7713b1edbc | 748 | * @param enableRxFifo Disables (false) the RX FIFO; Otherwise, enables (true) the RX FIFO |
AnnaBridge | 171:3a7713b1edbc | 749 | */ |
AnnaBridge | 171:3a7713b1edbc | 750 | static inline void DSPI_SetFifoEnable(SPI_Type *base, bool enableTxFifo, bool enableRxFifo) |
AnnaBridge | 171:3a7713b1edbc | 751 | { |
AnnaBridge | 171:3a7713b1edbc | 752 | base->MCR = (base->MCR & (~(SPI_MCR_DIS_RXF_MASK | SPI_MCR_DIS_TXF_MASK))) | SPI_MCR_DIS_TXF(!enableTxFifo) | |
AnnaBridge | 171:3a7713b1edbc | 753 | SPI_MCR_DIS_RXF(!enableRxFifo); |
AnnaBridge | 171:3a7713b1edbc | 754 | } |
AnnaBridge | 171:3a7713b1edbc | 755 | |
AnnaBridge | 171:3a7713b1edbc | 756 | /*! |
AnnaBridge | 171:3a7713b1edbc | 757 | * @brief Flushes the DSPI FIFOs. |
AnnaBridge | 171:3a7713b1edbc | 758 | * |
AnnaBridge | 171:3a7713b1edbc | 759 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 760 | * @param flushTxFifo Flushes (true) the Tx FIFO; Otherwise, does not flush (false) the Tx FIFO |
AnnaBridge | 171:3a7713b1edbc | 761 | * @param flushRxFifo Flushes (true) the Rx FIFO; Otherwise, does not flush (false) the Rx FIFO |
AnnaBridge | 171:3a7713b1edbc | 762 | */ |
AnnaBridge | 171:3a7713b1edbc | 763 | static inline void DSPI_FlushFifo(SPI_Type *base, bool flushTxFifo, bool flushRxFifo) |
AnnaBridge | 171:3a7713b1edbc | 764 | { |
AnnaBridge | 171:3a7713b1edbc | 765 | base->MCR = (base->MCR & (~(SPI_MCR_CLR_TXF_MASK | SPI_MCR_CLR_RXF_MASK))) | SPI_MCR_CLR_TXF(flushTxFifo) | |
AnnaBridge | 171:3a7713b1edbc | 766 | SPI_MCR_CLR_RXF(flushRxFifo); |
AnnaBridge | 171:3a7713b1edbc | 767 | } |
AnnaBridge | 171:3a7713b1edbc | 768 | |
AnnaBridge | 171:3a7713b1edbc | 769 | /*! |
AnnaBridge | 171:3a7713b1edbc | 770 | * @brief Configures the DSPI peripheral chip select polarity simultaneously. |
AnnaBridge | 171:3a7713b1edbc | 771 | * For example, PCS0 and PCS1 are set to active low and other PCS is set to active high. Note that the number of |
AnnaBridge | 171:3a7713b1edbc | 772 | * PCSs is specific to the device. |
AnnaBridge | 171:3a7713b1edbc | 773 | * @code |
AnnaBridge | 171:3a7713b1edbc | 774 | * DSPI_SetAllPcsPolarity(base, kDSPI_Pcs0ActiveLow | kDSPI_Pcs1ActiveLow); |
AnnaBridge | 171:3a7713b1edbc | 775 | @endcode |
AnnaBridge | 171:3a7713b1edbc | 776 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 777 | * @param mask The PCS polarity mask; use the enum _dspi_pcs_polarity. |
AnnaBridge | 171:3a7713b1edbc | 778 | */ |
AnnaBridge | 171:3a7713b1edbc | 779 | static inline void DSPI_SetAllPcsPolarity(SPI_Type *base, uint32_t mask) |
AnnaBridge | 171:3a7713b1edbc | 780 | { |
AnnaBridge | 171:3a7713b1edbc | 781 | base->MCR = (base->MCR & ~SPI_MCR_PCSIS_MASK) | SPI_MCR_PCSIS(mask); |
AnnaBridge | 171:3a7713b1edbc | 782 | } |
AnnaBridge | 171:3a7713b1edbc | 783 | |
AnnaBridge | 171:3a7713b1edbc | 784 | /*! |
AnnaBridge | 171:3a7713b1edbc | 785 | * @brief Sets the DSPI baud rate in bits per second. |
AnnaBridge | 171:3a7713b1edbc | 786 | * |
AnnaBridge | 171:3a7713b1edbc | 787 | * This function takes in the desired baudRate_Bps (baud rate) and calculates the nearest possible baud rate without |
AnnaBridge | 171:3a7713b1edbc | 788 | * exceeding the desired baud rate, and returns the calculated baud rate in bits-per-second. It requires that the |
AnnaBridge | 171:3a7713b1edbc | 789 | * caller also provide the frequency of the module source clock (in Hertz). |
AnnaBridge | 171:3a7713b1edbc | 790 | * |
AnnaBridge | 171:3a7713b1edbc | 791 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 792 | * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of the type dspi_ctar_selection_t |
AnnaBridge | 171:3a7713b1edbc | 793 | * @param baudRate_Bps The desired baud rate in bits per second |
AnnaBridge | 171:3a7713b1edbc | 794 | * @param srcClock_Hz Module source input clock in Hertz |
AnnaBridge | 171:3a7713b1edbc | 795 | * @return The actual calculated baud rate |
AnnaBridge | 171:3a7713b1edbc | 796 | */ |
AnnaBridge | 171:3a7713b1edbc | 797 | uint32_t DSPI_MasterSetBaudRate(SPI_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 798 | dspi_ctar_selection_t whichCtar, |
AnnaBridge | 171:3a7713b1edbc | 799 | uint32_t baudRate_Bps, |
AnnaBridge | 171:3a7713b1edbc | 800 | uint32_t srcClock_Hz); |
AnnaBridge | 171:3a7713b1edbc | 801 | |
AnnaBridge | 171:3a7713b1edbc | 802 | /*! |
AnnaBridge | 171:3a7713b1edbc | 803 | * @brief Manually configures the delay prescaler and scaler for a particular CTAR. |
AnnaBridge | 171:3a7713b1edbc | 804 | * |
AnnaBridge | 171:3a7713b1edbc | 805 | * This function configures the PCS to SCK delay pre-scalar (PcsSCK) and scalar (CSSCK), after SCK delay pre-scalar |
AnnaBridge | 171:3a7713b1edbc | 806 | * (PASC) and scalar (ASC), and the delay after transfer pre-scalar (PDT) and scalar (DT). |
AnnaBridge | 171:3a7713b1edbc | 807 | * |
AnnaBridge | 171:3a7713b1edbc | 808 | * These delay names are available in the type dspi_delay_type_t. |
AnnaBridge | 171:3a7713b1edbc | 809 | * |
AnnaBridge | 171:3a7713b1edbc | 810 | * The user passes the delay to the configuration along with the prescaler and scaler value. |
AnnaBridge | 171:3a7713b1edbc | 811 | * This allows the user to directly set the prescaler/scaler values if pre-calculated or |
AnnaBridge | 171:3a7713b1edbc | 812 | * to manually increment either value. |
AnnaBridge | 171:3a7713b1edbc | 813 | * |
AnnaBridge | 171:3a7713b1edbc | 814 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 815 | * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. |
AnnaBridge | 171:3a7713b1edbc | 816 | * @param prescaler The prescaler delay value (can be an integer 0, 1, 2, or 3). |
AnnaBridge | 171:3a7713b1edbc | 817 | * @param scaler The scaler delay value (can be any integer between 0 to 15). |
AnnaBridge | 171:3a7713b1edbc | 818 | * @param whichDelay The desired delay to configure; must be of type dspi_delay_type_t |
AnnaBridge | 171:3a7713b1edbc | 819 | */ |
AnnaBridge | 171:3a7713b1edbc | 820 | void DSPI_MasterSetDelayScaler( |
AnnaBridge | 171:3a7713b1edbc | 821 | SPI_Type *base, dspi_ctar_selection_t whichCtar, uint32_t prescaler, uint32_t scaler, dspi_delay_type_t whichDelay); |
AnnaBridge | 171:3a7713b1edbc | 822 | |
AnnaBridge | 171:3a7713b1edbc | 823 | /*! |
AnnaBridge | 171:3a7713b1edbc | 824 | * @brief Calculates the delay prescaler and scaler based on the desired delay input in nanoseconds. |
AnnaBridge | 171:3a7713b1edbc | 825 | * |
AnnaBridge | 171:3a7713b1edbc | 826 | * This function calculates the values for the following. |
AnnaBridge | 171:3a7713b1edbc | 827 | * PCS to SCK delay pre-scalar (PCSSCK) and scalar (CSSCK), or |
AnnaBridge | 171:3a7713b1edbc | 828 | * After SCK delay pre-scalar (PASC) and scalar (ASC), or |
AnnaBridge | 171:3a7713b1edbc | 829 | * Delay after transfer pre-scalar (PDT) and scalar (DT). |
AnnaBridge | 171:3a7713b1edbc | 830 | * |
AnnaBridge | 171:3a7713b1edbc | 831 | * These delay names are available in the type dspi_delay_type_t. |
AnnaBridge | 171:3a7713b1edbc | 832 | * |
AnnaBridge | 171:3a7713b1edbc | 833 | * The user passes which delay to configure along with the desired delay value in nanoseconds. The function |
AnnaBridge | 171:3a7713b1edbc | 834 | * calculates the values needed for the prescaler and scaler. Note that returning the calculated delay as an exact |
AnnaBridge | 171:3a7713b1edbc | 835 | * delay match may not be possible. In this case, the closest match is calculated without going below the desired |
AnnaBridge | 171:3a7713b1edbc | 836 | * delay value input. |
AnnaBridge | 171:3a7713b1edbc | 837 | * It is possible to input a very large delay value that exceeds the capability of the part, in which case the maximum |
AnnaBridge | 171:3a7713b1edbc | 838 | * supported delay is returned. The higher-level peripheral driver alerts the user of an out of range delay |
AnnaBridge | 171:3a7713b1edbc | 839 | * input. |
AnnaBridge | 171:3a7713b1edbc | 840 | * |
AnnaBridge | 171:3a7713b1edbc | 841 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 842 | * @param whichCtar The desired Clock and Transfer Attributes Register (CTAR) of type dspi_ctar_selection_t. |
AnnaBridge | 171:3a7713b1edbc | 843 | * @param whichDelay The desired delay to configure, must be of type dspi_delay_type_t |
AnnaBridge | 171:3a7713b1edbc | 844 | * @param srcClock_Hz Module source input clock in Hertz |
AnnaBridge | 171:3a7713b1edbc | 845 | * @param delayTimeInNanoSec The desired delay value in nanoseconds. |
AnnaBridge | 171:3a7713b1edbc | 846 | * @return The actual calculated delay value. |
AnnaBridge | 171:3a7713b1edbc | 847 | */ |
AnnaBridge | 171:3a7713b1edbc | 848 | uint32_t DSPI_MasterSetDelayTimes(SPI_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 849 | dspi_ctar_selection_t whichCtar, |
AnnaBridge | 171:3a7713b1edbc | 850 | dspi_delay_type_t whichDelay, |
AnnaBridge | 171:3a7713b1edbc | 851 | uint32_t srcClock_Hz, |
AnnaBridge | 171:3a7713b1edbc | 852 | uint32_t delayTimeInNanoSec); |
AnnaBridge | 171:3a7713b1edbc | 853 | |
AnnaBridge | 171:3a7713b1edbc | 854 | /*! |
AnnaBridge | 171:3a7713b1edbc | 855 | * @brief Writes data into the data buffer for master mode. |
AnnaBridge | 171:3a7713b1edbc | 856 | * |
AnnaBridge | 171:3a7713b1edbc | 857 | * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion |
AnnaBridge | 171:3a7713b1edbc | 858 | * provides characteristics of the data, such as the optional continuous chip select |
AnnaBridge | 171:3a7713b1edbc | 859 | * operation between transfers, the desired Clock and Transfer Attributes register to use for the |
AnnaBridge | 171:3a7713b1edbc | 860 | * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current |
AnnaBridge | 171:3a7713b1edbc | 861 | * transfer is the last in the queue, and whether to clear the transfer count (normally needed when |
AnnaBridge | 171:3a7713b1edbc | 862 | * sending the first frame of a data packet). This is an example. |
AnnaBridge | 171:3a7713b1edbc | 863 | * @code |
AnnaBridge | 171:3a7713b1edbc | 864 | * dspi_command_data_config_t commandConfig; |
AnnaBridge | 171:3a7713b1edbc | 865 | * commandConfig.isPcsContinuous = true; |
AnnaBridge | 171:3a7713b1edbc | 866 | * commandConfig.whichCtar = kDSPICtar0; |
AnnaBridge | 171:3a7713b1edbc | 867 | * commandConfig.whichPcs = kDSPIPcs0; |
AnnaBridge | 171:3a7713b1edbc | 868 | * commandConfig.clearTransferCount = false; |
AnnaBridge | 171:3a7713b1edbc | 869 | * commandConfig.isEndOfQueue = false; |
AnnaBridge | 171:3a7713b1edbc | 870 | * DSPI_MasterWriteData(base, &commandConfig, dataWord); |
AnnaBridge | 171:3a7713b1edbc | 871 | @endcode |
AnnaBridge | 171:3a7713b1edbc | 872 | * |
AnnaBridge | 171:3a7713b1edbc | 873 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 874 | * @param command Pointer to the command structure. |
AnnaBridge | 171:3a7713b1edbc | 875 | * @param data The data word to be sent. |
AnnaBridge | 171:3a7713b1edbc | 876 | */ |
AnnaBridge | 171:3a7713b1edbc | 877 | static inline void DSPI_MasterWriteData(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data) |
AnnaBridge | 171:3a7713b1edbc | 878 | { |
AnnaBridge | 171:3a7713b1edbc | 879 | base->PUSHR = SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | |
AnnaBridge | 171:3a7713b1edbc | 880 | SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | |
AnnaBridge | 171:3a7713b1edbc | 881 | SPI_PUSHR_CTCNT(command->clearTransferCount) | SPI_PUSHR_TXDATA(data); |
AnnaBridge | 171:3a7713b1edbc | 882 | } |
AnnaBridge | 171:3a7713b1edbc | 883 | |
AnnaBridge | 171:3a7713b1edbc | 884 | /*! |
AnnaBridge | 171:3a7713b1edbc | 885 | * @brief Sets the dspi_command_data_config_t structure to default values. |
AnnaBridge | 171:3a7713b1edbc | 886 | * |
AnnaBridge | 171:3a7713b1edbc | 887 | * The purpose of this API is to get the configuration structure initialized for use in the DSPI_MasterWrite_xx(). |
AnnaBridge | 171:3a7713b1edbc | 888 | * Users may use the initialized structure unchanged in the DSPI_MasterWrite_xx() or modify the structure |
AnnaBridge | 171:3a7713b1edbc | 889 | * before calling the DSPI_MasterWrite_xx(). |
AnnaBridge | 171:3a7713b1edbc | 890 | * This is an example. |
AnnaBridge | 171:3a7713b1edbc | 891 | * @code |
AnnaBridge | 171:3a7713b1edbc | 892 | * dspi_command_data_config_t command; |
AnnaBridge | 171:3a7713b1edbc | 893 | * DSPI_GetDefaultDataCommandConfig(&command); |
AnnaBridge | 171:3a7713b1edbc | 894 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 895 | * @param command Pointer to the dspi_command_data_config_t structure. |
AnnaBridge | 171:3a7713b1edbc | 896 | */ |
AnnaBridge | 171:3a7713b1edbc | 897 | void DSPI_GetDefaultDataCommandConfig(dspi_command_data_config_t *command); |
AnnaBridge | 171:3a7713b1edbc | 898 | |
AnnaBridge | 171:3a7713b1edbc | 899 | /*! |
AnnaBridge | 171:3a7713b1edbc | 900 | * @brief Writes data into the data buffer master mode and waits till complete to return. |
AnnaBridge | 171:3a7713b1edbc | 901 | * |
AnnaBridge | 171:3a7713b1edbc | 902 | * In master mode, the 16-bit data is appended to the 16-bit command info. The command portion |
AnnaBridge | 171:3a7713b1edbc | 903 | * provides characteristics of the data, such as the optional continuous chip select |
AnnaBridge | 171:3a7713b1edbc | 904 | * operation between transfers, the desired Clock and Transfer Attributes register to use for the |
AnnaBridge | 171:3a7713b1edbc | 905 | * associated SPI frame, the desired PCS signal to use for the data transfer, whether the current |
AnnaBridge | 171:3a7713b1edbc | 906 | * transfer is the last in the queue, and whether to clear the transfer count (normally needed when |
AnnaBridge | 171:3a7713b1edbc | 907 | * sending the first frame of a data packet). This is an example. |
AnnaBridge | 171:3a7713b1edbc | 908 | * @code |
AnnaBridge | 171:3a7713b1edbc | 909 | * dspi_command_config_t commandConfig; |
AnnaBridge | 171:3a7713b1edbc | 910 | * commandConfig.isPcsContinuous = true; |
AnnaBridge | 171:3a7713b1edbc | 911 | * commandConfig.whichCtar = kDSPICtar0; |
AnnaBridge | 171:3a7713b1edbc | 912 | * commandConfig.whichPcs = kDSPIPcs1; |
AnnaBridge | 171:3a7713b1edbc | 913 | * commandConfig.clearTransferCount = false; |
AnnaBridge | 171:3a7713b1edbc | 914 | * commandConfig.isEndOfQueue = false; |
AnnaBridge | 171:3a7713b1edbc | 915 | * DSPI_MasterWriteDataBlocking(base, &commandConfig, dataWord); |
AnnaBridge | 171:3a7713b1edbc | 916 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 917 | * |
AnnaBridge | 171:3a7713b1edbc | 918 | * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be |
AnnaBridge | 171:3a7713b1edbc | 919 | * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). Because the SPI is a synchronous protocol, |
AnnaBridge | 171:3a7713b1edbc | 920 | * the received data is available when the transmit completes. |
AnnaBridge | 171:3a7713b1edbc | 921 | * |
AnnaBridge | 171:3a7713b1edbc | 922 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 923 | * @param command Pointer to the command structure. |
AnnaBridge | 171:3a7713b1edbc | 924 | * @param data The data word to be sent. |
AnnaBridge | 171:3a7713b1edbc | 925 | */ |
AnnaBridge | 171:3a7713b1edbc | 926 | void DSPI_MasterWriteDataBlocking(SPI_Type *base, dspi_command_data_config_t *command, uint16_t data); |
AnnaBridge | 171:3a7713b1edbc | 927 | |
AnnaBridge | 171:3a7713b1edbc | 928 | /*! |
AnnaBridge | 171:3a7713b1edbc | 929 | * @brief Returns the DSPI command word formatted to the PUSHR data register bit field. |
AnnaBridge | 171:3a7713b1edbc | 930 | * |
AnnaBridge | 171:3a7713b1edbc | 931 | * This function allows the caller to pass in the data command structure and returns the command word formatted |
AnnaBridge | 171:3a7713b1edbc | 932 | * according to the DSPI PUSHR register bit field placement. The user can then "OR" the returned command word with the |
AnnaBridge | 171:3a7713b1edbc | 933 | * desired data to send and use the function DSPI_HAL_WriteCommandDataMastermode or |
AnnaBridge | 171:3a7713b1edbc | 934 | * DSPI_HAL_WriteCommandDataMastermodeBlocking to write the entire 32-bit command data word to the PUSHR. This helps |
AnnaBridge | 171:3a7713b1edbc | 935 | * improve performance in cases where the command structure is constant. For example, the user calls this function |
AnnaBridge | 171:3a7713b1edbc | 936 | * before starting a transfer to generate the command word. When they are ready to transmit the data, they OR |
AnnaBridge | 171:3a7713b1edbc | 937 | * this formatted command word with the desired data to transmit. This process increases transmit performance when |
AnnaBridge | 171:3a7713b1edbc | 938 | * compared to calling send functions, such as DSPI_HAL_WriteDataMastermode, which format the command word each time a |
AnnaBridge | 171:3a7713b1edbc | 939 | * data word is to be sent. |
AnnaBridge | 171:3a7713b1edbc | 940 | * |
AnnaBridge | 171:3a7713b1edbc | 941 | * @param command Pointer to the command structure. |
AnnaBridge | 171:3a7713b1edbc | 942 | * @return The command word formatted to the PUSHR data register bit field. |
AnnaBridge | 171:3a7713b1edbc | 943 | */ |
AnnaBridge | 171:3a7713b1edbc | 944 | static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t *command) |
AnnaBridge | 171:3a7713b1edbc | 945 | { |
AnnaBridge | 171:3a7713b1edbc | 946 | /* Format the 16-bit command word according to the PUSHR data register bit field*/ |
AnnaBridge | 171:3a7713b1edbc | 947 | return (uint32_t)(SPI_PUSHR_CONT(command->isPcsContinuous) | SPI_PUSHR_CTAS(command->whichCtar) | |
AnnaBridge | 171:3a7713b1edbc | 948 | SPI_PUSHR_PCS(command->whichPcs) | SPI_PUSHR_EOQ(command->isEndOfQueue) | |
AnnaBridge | 171:3a7713b1edbc | 949 | SPI_PUSHR_CTCNT(command->clearTransferCount)); |
AnnaBridge | 171:3a7713b1edbc | 950 | } |
AnnaBridge | 171:3a7713b1edbc | 951 | |
AnnaBridge | 171:3a7713b1edbc | 952 | /*! |
AnnaBridge | 171:3a7713b1edbc | 953 | * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data |
AnnaBridge | 171:3a7713b1edbc | 954 | * buffer master mode and waits till complete to return. |
AnnaBridge | 171:3a7713b1edbc | 955 | * |
AnnaBridge | 171:3a7713b1edbc | 956 | * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total |
AnnaBridge | 171:3a7713b1edbc | 957 | * 32-bit word |
AnnaBridge | 171:3a7713b1edbc | 958 | * as the data to send. |
AnnaBridge | 171:3a7713b1edbc | 959 | * The command portion provides characteristics of the data, such as the optional continuous chip select operation |
AnnaBridge | 171:3a7713b1edbc | 960 | * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the |
AnnaBridge | 171:3a7713b1edbc | 961 | * desired PCS |
AnnaBridge | 171:3a7713b1edbc | 962 | * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the |
AnnaBridge | 171:3a7713b1edbc | 963 | * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for |
AnnaBridge | 171:3a7713b1edbc | 964 | * appending this command with the data to send. This is an example: |
AnnaBridge | 171:3a7713b1edbc | 965 | * @code |
AnnaBridge | 171:3a7713b1edbc | 966 | * dataWord = <16-bit command> | <16-bit data>; |
AnnaBridge | 171:3a7713b1edbc | 967 | * DSPI_MasterWriteCommandDataBlocking(base, dataWord); |
AnnaBridge | 171:3a7713b1edbc | 968 | * @endcode |
AnnaBridge | 171:3a7713b1edbc | 969 | * |
AnnaBridge | 171:3a7713b1edbc | 970 | * Note that this function does not return until after the transmit is complete. Also note that the DSPI must be |
AnnaBridge | 171:3a7713b1edbc | 971 | * enabled and running to transmit data (MCR[MDIS] & [HALT] = 0). |
AnnaBridge | 171:3a7713b1edbc | 972 | * Because the SPI is a synchronous protocol, the received data is available when the transmit completes. |
AnnaBridge | 171:3a7713b1edbc | 973 | * |
AnnaBridge | 171:3a7713b1edbc | 974 | * For a blocking polling transfer, see methods below. |
AnnaBridge | 171:3a7713b1edbc | 975 | * Option 1: |
AnnaBridge | 171:3a7713b1edbc | 976 | * uint32_t command_to_send = DSPI_MasterGetFormattedCommand(&command); |
AnnaBridge | 171:3a7713b1edbc | 977 | * uint32_t data0 = command_to_send | data_need_to_send_0; |
AnnaBridge | 171:3a7713b1edbc | 978 | * uint32_t data1 = command_to_send | data_need_to_send_1; |
AnnaBridge | 171:3a7713b1edbc | 979 | * uint32_t data2 = command_to_send | data_need_to_send_2; |
AnnaBridge | 171:3a7713b1edbc | 980 | * |
AnnaBridge | 171:3a7713b1edbc | 981 | * DSPI_MasterWriteCommandDataBlocking(base,data0); |
AnnaBridge | 171:3a7713b1edbc | 982 | * DSPI_MasterWriteCommandDataBlocking(base,data1); |
AnnaBridge | 171:3a7713b1edbc | 983 | * DSPI_MasterWriteCommandDataBlocking(base,data2); |
AnnaBridge | 171:3a7713b1edbc | 984 | * |
AnnaBridge | 171:3a7713b1edbc | 985 | * Option 2: |
AnnaBridge | 171:3a7713b1edbc | 986 | * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_0); |
AnnaBridge | 171:3a7713b1edbc | 987 | * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_1); |
AnnaBridge | 171:3a7713b1edbc | 988 | * DSPI_MasterWriteDataBlocking(base,&command,data_need_to_send_2); |
AnnaBridge | 171:3a7713b1edbc | 989 | * |
AnnaBridge | 171:3a7713b1edbc | 990 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 991 | * @param data The data word (command and data combined) to be sent. |
AnnaBridge | 171:3a7713b1edbc | 992 | */ |
AnnaBridge | 171:3a7713b1edbc | 993 | void DSPI_MasterWriteCommandDataBlocking(SPI_Type *base, uint32_t data); |
AnnaBridge | 171:3a7713b1edbc | 994 | |
AnnaBridge | 171:3a7713b1edbc | 995 | /*! |
AnnaBridge | 171:3a7713b1edbc | 996 | * @brief Writes data into the data buffer in slave mode. |
AnnaBridge | 171:3a7713b1edbc | 997 | * |
AnnaBridge | 171:3a7713b1edbc | 998 | * In slave mode, up to 16-bit words may be written. |
AnnaBridge | 171:3a7713b1edbc | 999 | * |
AnnaBridge | 171:3a7713b1edbc | 1000 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1001 | * @param data The data to send. |
AnnaBridge | 171:3a7713b1edbc | 1002 | */ |
AnnaBridge | 171:3a7713b1edbc | 1003 | static inline void DSPI_SlaveWriteData(SPI_Type *base, uint32_t data) |
AnnaBridge | 171:3a7713b1edbc | 1004 | { |
AnnaBridge | 171:3a7713b1edbc | 1005 | base->PUSHR_SLAVE = data; |
AnnaBridge | 171:3a7713b1edbc | 1006 | } |
AnnaBridge | 171:3a7713b1edbc | 1007 | |
AnnaBridge | 171:3a7713b1edbc | 1008 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1009 | * @brief Writes data into the data buffer in slave mode, waits till data was transmitted, and returns. |
AnnaBridge | 171:3a7713b1edbc | 1010 | * |
AnnaBridge | 171:3a7713b1edbc | 1011 | * In slave mode, up to 16-bit words may be written. The function first clears the transmit complete flag, writes data |
AnnaBridge | 171:3a7713b1edbc | 1012 | * into data register, and finally waits until the data is transmitted. |
AnnaBridge | 171:3a7713b1edbc | 1013 | * |
AnnaBridge | 171:3a7713b1edbc | 1014 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1015 | * @param data The data to send. |
AnnaBridge | 171:3a7713b1edbc | 1016 | */ |
AnnaBridge | 171:3a7713b1edbc | 1017 | void DSPI_SlaveWriteDataBlocking(SPI_Type *base, uint32_t data); |
AnnaBridge | 171:3a7713b1edbc | 1018 | |
AnnaBridge | 171:3a7713b1edbc | 1019 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1020 | * @brief Reads data from the data buffer. |
AnnaBridge | 171:3a7713b1edbc | 1021 | * |
AnnaBridge | 171:3a7713b1edbc | 1022 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1023 | * @return The data from the read data buffer. |
AnnaBridge | 171:3a7713b1edbc | 1024 | */ |
AnnaBridge | 171:3a7713b1edbc | 1025 | static inline uint32_t DSPI_ReadData(SPI_Type *base) |
AnnaBridge | 171:3a7713b1edbc | 1026 | { |
AnnaBridge | 171:3a7713b1edbc | 1027 | return (base->POPR); |
AnnaBridge | 171:3a7713b1edbc | 1028 | } |
AnnaBridge | 171:3a7713b1edbc | 1029 | |
AnnaBridge | 171:3a7713b1edbc | 1030 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1031 | * @brief Set up the dummy data. |
AnnaBridge | 171:3a7713b1edbc | 1032 | * |
AnnaBridge | 171:3a7713b1edbc | 1033 | * @param base DSPI peripheral address. |
AnnaBridge | 171:3a7713b1edbc | 1034 | * @param dummyData Data to be transferred when tx buffer is NULL. |
AnnaBridge | 171:3a7713b1edbc | 1035 | */ |
AnnaBridge | 171:3a7713b1edbc | 1036 | void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData); |
AnnaBridge | 171:3a7713b1edbc | 1037 | |
AnnaBridge | 171:3a7713b1edbc | 1038 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1039 | *@} |
AnnaBridge | 171:3a7713b1edbc | 1040 | */ |
AnnaBridge | 171:3a7713b1edbc | 1041 | |
AnnaBridge | 171:3a7713b1edbc | 1042 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1043 | * @name Transactional |
AnnaBridge | 171:3a7713b1edbc | 1044 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1045 | */ |
AnnaBridge | 171:3a7713b1edbc | 1046 | /*Transactional APIs*/ |
AnnaBridge | 171:3a7713b1edbc | 1047 | |
AnnaBridge | 171:3a7713b1edbc | 1048 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1049 | * @brief Initializes the DSPI master handle. |
AnnaBridge | 171:3a7713b1edbc | 1050 | * |
AnnaBridge | 171:3a7713b1edbc | 1051 | * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a |
AnnaBridge | 171:3a7713b1edbc | 1052 | * specified DSPI instance, call this API once to get the initialized handle. |
AnnaBridge | 171:3a7713b1edbc | 1053 | * |
AnnaBridge | 171:3a7713b1edbc | 1054 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1055 | * @param handle DSPI handle pointer to dspi_master_handle_t. |
AnnaBridge | 171:3a7713b1edbc | 1056 | * @param callback DSPI callback. |
AnnaBridge | 171:3a7713b1edbc | 1057 | * @param userData Callback function parameter. |
AnnaBridge | 171:3a7713b1edbc | 1058 | */ |
AnnaBridge | 171:3a7713b1edbc | 1059 | void DSPI_MasterTransferCreateHandle(SPI_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 1060 | dspi_master_handle_t *handle, |
AnnaBridge | 171:3a7713b1edbc | 1061 | dspi_master_transfer_callback_t callback, |
AnnaBridge | 171:3a7713b1edbc | 1062 | void *userData); |
AnnaBridge | 171:3a7713b1edbc | 1063 | |
AnnaBridge | 171:3a7713b1edbc | 1064 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1065 | * @brief DSPI master transfer data using polling. |
AnnaBridge | 171:3a7713b1edbc | 1066 | * |
AnnaBridge | 171:3a7713b1edbc | 1067 | * This function transfers data using polling. This is a blocking function, which does not return until all transfers |
AnnaBridge | 171:3a7713b1edbc | 1068 | * have been completed. |
AnnaBridge | 171:3a7713b1edbc | 1069 | * |
AnnaBridge | 171:3a7713b1edbc | 1070 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1071 | * @param transfer Pointer to the dspi_transfer_t structure. |
AnnaBridge | 171:3a7713b1edbc | 1072 | * @return status of status_t. |
AnnaBridge | 171:3a7713b1edbc | 1073 | */ |
AnnaBridge | 171:3a7713b1edbc | 1074 | status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer); |
AnnaBridge | 171:3a7713b1edbc | 1075 | |
AnnaBridge | 171:3a7713b1edbc | 1076 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1077 | * @brief DSPI master transfer data using interrupts. |
AnnaBridge | 171:3a7713b1edbc | 1078 | * |
AnnaBridge | 171:3a7713b1edbc | 1079 | * This function transfers data using interrupts. This is a non-blocking function, which returns right away. When all |
AnnaBridge | 171:3a7713b1edbc | 1080 | * data is transferred, the callback function is called. |
AnnaBridge | 171:3a7713b1edbc | 1081 | |
AnnaBridge | 171:3a7713b1edbc | 1082 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1083 | * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1084 | * @param transfer Pointer to the dspi_transfer_t structure. |
AnnaBridge | 171:3a7713b1edbc | 1085 | * @return status of status_t. |
AnnaBridge | 171:3a7713b1edbc | 1086 | */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer); |
AnnaBridge | 171:3a7713b1edbc | 1088 | |
AnnaBridge | 171:3a7713b1edbc | 1089 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1090 | * @brief Gets the master transfer count. |
AnnaBridge | 171:3a7713b1edbc | 1091 | * |
AnnaBridge | 171:3a7713b1edbc | 1092 | * This function gets the master transfer count. |
AnnaBridge | 171:3a7713b1edbc | 1093 | * |
AnnaBridge | 171:3a7713b1edbc | 1094 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1095 | * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1096 | * @param count The number of bytes transferred by using the non-blocking transaction. |
AnnaBridge | 171:3a7713b1edbc | 1097 | * @return status of status_t. |
AnnaBridge | 171:3a7713b1edbc | 1098 | */ |
AnnaBridge | 171:3a7713b1edbc | 1099 | status_t DSPI_MasterTransferGetCount(SPI_Type *base, dspi_master_handle_t *handle, size_t *count); |
AnnaBridge | 171:3a7713b1edbc | 1100 | |
AnnaBridge | 171:3a7713b1edbc | 1101 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1102 | * @brief DSPI master aborts a transfer using an interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1103 | * |
AnnaBridge | 171:3a7713b1edbc | 1104 | * This function aborts a transfer using an interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1105 | * |
AnnaBridge | 171:3a7713b1edbc | 1106 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1107 | * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1108 | */ |
AnnaBridge | 171:3a7713b1edbc | 1109 | void DSPI_MasterTransferAbort(SPI_Type *base, dspi_master_handle_t *handle); |
AnnaBridge | 171:3a7713b1edbc | 1110 | |
AnnaBridge | 171:3a7713b1edbc | 1111 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1112 | * @brief DSPI Master IRQ handler function. |
AnnaBridge | 171:3a7713b1edbc | 1113 | * |
AnnaBridge | 171:3a7713b1edbc | 1114 | * This function processes the DSPI transmit and receive IRQ. |
AnnaBridge | 171:3a7713b1edbc | 1115 | |
AnnaBridge | 171:3a7713b1edbc | 1116 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1117 | * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1118 | */ |
AnnaBridge | 171:3a7713b1edbc | 1119 | void DSPI_MasterTransferHandleIRQ(SPI_Type *base, dspi_master_handle_t *handle); |
AnnaBridge | 171:3a7713b1edbc | 1120 | |
AnnaBridge | 171:3a7713b1edbc | 1121 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1122 | * @brief Initializes the DSPI slave handle. |
AnnaBridge | 171:3a7713b1edbc | 1123 | * |
AnnaBridge | 171:3a7713b1edbc | 1124 | * This function initializes the DSPI handle, which can be used for other DSPI transactional APIs. Usually, for a |
AnnaBridge | 171:3a7713b1edbc | 1125 | * specified DSPI instance, call this API once to get the initialized handle. |
AnnaBridge | 171:3a7713b1edbc | 1126 | * |
AnnaBridge | 171:3a7713b1edbc | 1127 | * @param handle DSPI handle pointer to the dspi_slave_handle_t. |
AnnaBridge | 171:3a7713b1edbc | 1128 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1129 | * @param callback DSPI callback. |
AnnaBridge | 171:3a7713b1edbc | 1130 | * @param userData Callback function parameter. |
AnnaBridge | 171:3a7713b1edbc | 1131 | */ |
AnnaBridge | 171:3a7713b1edbc | 1132 | void DSPI_SlaveTransferCreateHandle(SPI_Type *base, |
AnnaBridge | 171:3a7713b1edbc | 1133 | dspi_slave_handle_t *handle, |
AnnaBridge | 171:3a7713b1edbc | 1134 | dspi_slave_transfer_callback_t callback, |
AnnaBridge | 171:3a7713b1edbc | 1135 | void *userData); |
AnnaBridge | 171:3a7713b1edbc | 1136 | |
AnnaBridge | 171:3a7713b1edbc | 1137 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1138 | * @brief DSPI slave transfers data using an interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1139 | * |
AnnaBridge | 171:3a7713b1edbc | 1140 | * This function transfers data using an interrupt. This is a non-blocking function, which returns right away. When all |
AnnaBridge | 171:3a7713b1edbc | 1141 | * data is transferred, the callback function is called. |
AnnaBridge | 171:3a7713b1edbc | 1142 | * |
AnnaBridge | 171:3a7713b1edbc | 1143 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1144 | * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1145 | * @param transfer Pointer to the dspi_transfer_t structure. |
AnnaBridge | 171:3a7713b1edbc | 1146 | * @return status of status_t. |
AnnaBridge | 171:3a7713b1edbc | 1147 | */ |
AnnaBridge | 171:3a7713b1edbc | 1148 | status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *handle, dspi_transfer_t *transfer); |
AnnaBridge | 171:3a7713b1edbc | 1149 | |
AnnaBridge | 171:3a7713b1edbc | 1150 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1151 | * @brief Gets the slave transfer count. |
AnnaBridge | 171:3a7713b1edbc | 1152 | * |
AnnaBridge | 171:3a7713b1edbc | 1153 | * This function gets the slave transfer count. |
AnnaBridge | 171:3a7713b1edbc | 1154 | * |
AnnaBridge | 171:3a7713b1edbc | 1155 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1156 | * @param handle Pointer to the dspi_master_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1157 | * @param count The number of bytes transferred by using the non-blocking transaction. |
AnnaBridge | 171:3a7713b1edbc | 1158 | * @return status of status_t. |
AnnaBridge | 171:3a7713b1edbc | 1159 | */ |
AnnaBridge | 171:3a7713b1edbc | 1160 | status_t DSPI_SlaveTransferGetCount(SPI_Type *base, dspi_slave_handle_t *handle, size_t *count); |
AnnaBridge | 171:3a7713b1edbc | 1161 | |
AnnaBridge | 171:3a7713b1edbc | 1162 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1163 | * @brief DSPI slave aborts a transfer using an interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1164 | * |
AnnaBridge | 171:3a7713b1edbc | 1165 | * This function aborts a transfer using an interrupt. |
AnnaBridge | 171:3a7713b1edbc | 1166 | * |
AnnaBridge | 171:3a7713b1edbc | 1167 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1168 | * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1169 | */ |
AnnaBridge | 171:3a7713b1edbc | 1170 | void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle); |
AnnaBridge | 171:3a7713b1edbc | 1171 | |
AnnaBridge | 171:3a7713b1edbc | 1172 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1173 | * @brief DSPI Master IRQ handler function. |
AnnaBridge | 171:3a7713b1edbc | 1174 | * |
AnnaBridge | 171:3a7713b1edbc | 1175 | * This function processes the DSPI transmit and receive IRQ. |
AnnaBridge | 171:3a7713b1edbc | 1176 | * |
AnnaBridge | 171:3a7713b1edbc | 1177 | * @param base DSPI peripheral base address. |
AnnaBridge | 171:3a7713b1edbc | 1178 | * @param handle Pointer to the dspi_slave_handle_t structure which stores the transfer state. |
AnnaBridge | 171:3a7713b1edbc | 1179 | */ |
AnnaBridge | 171:3a7713b1edbc | 1180 | void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle); |
AnnaBridge | 171:3a7713b1edbc | 1181 | |
AnnaBridge | 171:3a7713b1edbc | 1182 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1183 | *@} |
AnnaBridge | 171:3a7713b1edbc | 1184 | */ |
AnnaBridge | 171:3a7713b1edbc | 1185 | |
AnnaBridge | 171:3a7713b1edbc | 1186 | #if defined(__cplusplus) |
AnnaBridge | 171:3a7713b1edbc | 1187 | } |
AnnaBridge | 171:3a7713b1edbc | 1188 | #endif /*_cplusplus*/ |
AnnaBridge | 171:3a7713b1edbc | 1189 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1190 | *@} |
AnnaBridge | 171:3a7713b1edbc | 1191 | */ |
AnnaBridge | 171:3a7713b1edbc | 1192 | |
AnnaBridge | 171:3a7713b1edbc | 1193 | #endif /*_FSL_DSPI_H_*/ |