mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_K64F/TOOLCHAIN_IAR/MK64F12.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 3 ** Processors: MK64FN1M0CAJ12
AnnaBridge 171:3a7713b1edbc 4 ** MK64FN1M0VDC12
AnnaBridge 171:3a7713b1edbc 5 ** MK64FN1M0VLL12
AnnaBridge 171:3a7713b1edbc 6 ** MK64FN1M0VLQ12
AnnaBridge 171:3a7713b1edbc 7 ** MK64FN1M0VMD12
AnnaBridge 171:3a7713b1edbc 8 ** MK64FX512VDC12
AnnaBridge 171:3a7713b1edbc 9 ** MK64FX512VLL12
AnnaBridge 171:3a7713b1edbc 10 ** MK64FX512VLQ12
AnnaBridge 171:3a7713b1edbc 11 ** MK64FX512VMD12
AnnaBridge 171:3a7713b1edbc 12 **
AnnaBridge 171:3a7713b1edbc 13 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 171:3a7713b1edbc 14 ** Freescale C/C++ for Embedded ARM
AnnaBridge 171:3a7713b1edbc 15 ** GNU C Compiler
AnnaBridge 171:3a7713b1edbc 16 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 171:3a7713b1edbc 17 **
AnnaBridge 171:3a7713b1edbc 18 ** Reference manual: K64P144M120SF5RM, Rev.2, January 2014
AnnaBridge 171:3a7713b1edbc 19 ** Version: rev. 2.9, 2016-03-21
AnnaBridge 171:3a7713b1edbc 20 ** Build: b160321
AnnaBridge 171:3a7713b1edbc 21 **
AnnaBridge 171:3a7713b1edbc 22 ** Abstract:
AnnaBridge 171:3a7713b1edbc 23 ** CMSIS Peripheral Access Layer for MK64F12
AnnaBridge 171:3a7713b1edbc 24 **
AnnaBridge 171:3a7713b1edbc 25 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
AnnaBridge 171:3a7713b1edbc 26 ** All rights reserved.
AnnaBridge 171:3a7713b1edbc 27 **
AnnaBridge 171:3a7713b1edbc 28 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 29 ** are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 30 **
AnnaBridge 171:3a7713b1edbc 31 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 171:3a7713b1edbc 32 ** of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 33 **
AnnaBridge 171:3a7713b1edbc 34 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 35 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 36 ** other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 37 **
AnnaBridge 171:3a7713b1edbc 38 ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its
AnnaBridge 171:3a7713b1edbc 39 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 171:3a7713b1edbc 40 ** software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 41 **
AnnaBridge 171:3a7713b1edbc 42 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 43 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 44 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 45 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 46 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 47 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 48 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 49 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 50 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 51 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 52 **
AnnaBridge 171:3a7713b1edbc 53 ** http: www.freescale.com
AnnaBridge 171:3a7713b1edbc 54 ** mail: support@freescale.com
AnnaBridge 171:3a7713b1edbc 55 **
AnnaBridge 171:3a7713b1edbc 56 ** Revisions:
AnnaBridge 171:3a7713b1edbc 57 ** - rev. 1.0 (2013-08-12)
AnnaBridge 171:3a7713b1edbc 58 ** Initial version.
AnnaBridge 171:3a7713b1edbc 59 ** - rev. 2.0 (2013-10-29)
AnnaBridge 171:3a7713b1edbc 60 ** Register accessor macros added to the memory map.
AnnaBridge 171:3a7713b1edbc 61 ** Symbols for Processor Expert memory map compatibility added to the memory map.
AnnaBridge 171:3a7713b1edbc 62 ** Startup file for gcc has been updated according to CMSIS 3.2.
AnnaBridge 171:3a7713b1edbc 63 ** System initialization updated.
AnnaBridge 171:3a7713b1edbc 64 ** MCG - registers updated.
AnnaBridge 171:3a7713b1edbc 65 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
AnnaBridge 171:3a7713b1edbc 66 ** - rev. 2.1 (2013-10-30)
AnnaBridge 171:3a7713b1edbc 67 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
AnnaBridge 171:3a7713b1edbc 68 ** - rev. 2.2 (2013-12-09)
AnnaBridge 171:3a7713b1edbc 69 ** DMA - EARS register removed.
AnnaBridge 171:3a7713b1edbc 70 ** AIPS0, AIPS1 - MPRA register updated.
AnnaBridge 171:3a7713b1edbc 71 ** - rev. 2.3 (2014-01-24)
AnnaBridge 171:3a7713b1edbc 72 ** Update according to reference manual rev. 2
AnnaBridge 171:3a7713b1edbc 73 ** ENET, MCG, MCM, SIM, USB - registers updated
AnnaBridge 171:3a7713b1edbc 74 ** - rev. 2.4 (2014-02-10)
AnnaBridge 171:3a7713b1edbc 75 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
AnnaBridge 171:3a7713b1edbc 76 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge 171:3a7713b1edbc 77 ** - rev. 2.5 (2014-02-10)
AnnaBridge 171:3a7713b1edbc 78 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h
AnnaBridge 171:3a7713b1edbc 79 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge 171:3a7713b1edbc 80 ** Module access macro module_BASES replaced by module_BASE_PTRS.
AnnaBridge 171:3a7713b1edbc 81 ** - rev. 2.6 (2014-08-28)
AnnaBridge 171:3a7713b1edbc 82 ** Update of system files - default clock configuration changed.
AnnaBridge 171:3a7713b1edbc 83 ** Update of startup files - possibility to override DefaultISR added.
AnnaBridge 171:3a7713b1edbc 84 ** - rev. 2.7 (2014-10-14)
AnnaBridge 171:3a7713b1edbc 85 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
AnnaBridge 171:3a7713b1edbc 86 ** - rev. 2.8 (2015-02-19)
AnnaBridge 171:3a7713b1edbc 87 ** Renamed interrupt vector LLW to LLWU.
AnnaBridge 171:3a7713b1edbc 88 ** - rev. 2.9 (2016-03-21)
AnnaBridge 171:3a7713b1edbc 89 ** Added MK64FN1M0CAJ12 part.
AnnaBridge 171:3a7713b1edbc 90 ** GPIO - renamed port instances: PTx -> GPIOx.
AnnaBridge 171:3a7713b1edbc 91 **
AnnaBridge 171:3a7713b1edbc 92 ** ###################################################################
AnnaBridge 171:3a7713b1edbc 93 */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 /*!
AnnaBridge 171:3a7713b1edbc 96 * @file MK64F12.h
AnnaBridge 171:3a7713b1edbc 97 * @version 2.9
AnnaBridge 171:3a7713b1edbc 98 * @date 2016-03-21
AnnaBridge 171:3a7713b1edbc 99 * @brief CMSIS Peripheral Access Layer for MK64F12
AnnaBridge 171:3a7713b1edbc 100 *
AnnaBridge 171:3a7713b1edbc 101 * CMSIS Peripheral Access Layer for MK64F12
AnnaBridge 171:3a7713b1edbc 102 */
AnnaBridge 171:3a7713b1edbc 103
AnnaBridge 171:3a7713b1edbc 104 #ifndef _MK64F12_H_
AnnaBridge 171:3a7713b1edbc 105 #define _MK64F12_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 171:3a7713b1edbc 108 * compatible) */
AnnaBridge 171:3a7713b1edbc 109 #define MCU_MEM_MAP_VERSION 0x0200U
AnnaBridge 171:3a7713b1edbc 110 /** Memory map minor version */
AnnaBridge 171:3a7713b1edbc 111 #define MCU_MEM_MAP_VERSION_MINOR 0x0009U
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /**
AnnaBridge 171:3a7713b1edbc 114 * @brief Macro to calculate address of an aliased word in the peripheral
AnnaBridge 171:3a7713b1edbc 115 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
AnnaBridge 171:3a7713b1edbc 116 * 0x400FFFFF).
AnnaBridge 171:3a7713b1edbc 117 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 118 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 119 * @return Address of the aliased word in the peripheral bitband area.
AnnaBridge 171:3a7713b1edbc 120 */
AnnaBridge 171:3a7713b1edbc 121 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
AnnaBridge 171:3a7713b1edbc 122 /**
AnnaBridge 171:3a7713b1edbc 123 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 124 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 125 * be used for peripherals with 32bit access allowed.
AnnaBridge 171:3a7713b1edbc 126 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 127 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 128 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 129 */
AnnaBridge 171:3a7713b1edbc 130 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 131 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
AnnaBridge 171:3a7713b1edbc 132 /**
AnnaBridge 171:3a7713b1edbc 133 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 134 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 135 * be used for peripherals with 16bit access allowed.
AnnaBridge 171:3a7713b1edbc 136 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 137 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 138 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 139 */
AnnaBridge 171:3a7713b1edbc 140 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 141 /**
AnnaBridge 171:3a7713b1edbc 142 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 171:3a7713b1edbc 143 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 171:3a7713b1edbc 144 * be used for peripherals with 8bit access allowed.
AnnaBridge 171:3a7713b1edbc 145 * @param Reg Register to access.
AnnaBridge 171:3a7713b1edbc 146 * @param Bit Bit number to access.
AnnaBridge 171:3a7713b1edbc 147 * @return Value of the targeted bit in the bit band region.
AnnaBridge 171:3a7713b1edbc 148 */
AnnaBridge 171:3a7713b1edbc 149 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 152 -- Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 153 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 /*!
AnnaBridge 171:3a7713b1edbc 156 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 171:3a7713b1edbc 157 * @{
AnnaBridge 171:3a7713b1edbc 158 */
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 /** Interrupt Number Definitions */
AnnaBridge 171:3a7713b1edbc 161 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
AnnaBridge 171:3a7713b1edbc 162
AnnaBridge 171:3a7713b1edbc 163 typedef enum IRQn {
AnnaBridge 171:3a7713b1edbc 164 /* Auxiliary constants */
AnnaBridge 171:3a7713b1edbc 165 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 171:3a7713b1edbc 166
AnnaBridge 171:3a7713b1edbc 167 /* Core interrupts */
AnnaBridge 171:3a7713b1edbc 168 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 169 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 170 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 171 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 172 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 173 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 174 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 175 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 176 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 177
AnnaBridge 171:3a7713b1edbc 178 /* Device specific interrupts */
AnnaBridge 171:3a7713b1edbc 179 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 180 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 181 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 182 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 183 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 184 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 185 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 186 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 187 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 188 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 189 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 190 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 191 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 192 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 193 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 194 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
AnnaBridge 171:3a7713b1edbc 195 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
AnnaBridge 171:3a7713b1edbc 196 MCM_IRQn = 17, /**< Normal Interrupt */
AnnaBridge 171:3a7713b1edbc 197 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
AnnaBridge 171:3a7713b1edbc 198 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
AnnaBridge 171:3a7713b1edbc 199 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
AnnaBridge 171:3a7713b1edbc 200 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
AnnaBridge 171:3a7713b1edbc 201 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
AnnaBridge 171:3a7713b1edbc 202 RNG_IRQn = 23, /**< RNG Interrupt */
AnnaBridge 171:3a7713b1edbc 203 I2C0_IRQn = 24, /**< I2C0 interrupt */
AnnaBridge 171:3a7713b1edbc 204 I2C1_IRQn = 25, /**< I2C1 interrupt */
AnnaBridge 171:3a7713b1edbc 205 SPI0_IRQn = 26, /**< SPI0 Interrupt */
AnnaBridge 171:3a7713b1edbc 206 SPI1_IRQn = 27, /**< SPI1 Interrupt */
AnnaBridge 171:3a7713b1edbc 207 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
AnnaBridge 171:3a7713b1edbc 208 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
AnnaBridge 171:3a7713b1edbc 209 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
AnnaBridge 171:3a7713b1edbc 210 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 211 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
AnnaBridge 171:3a7713b1edbc 212 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 213 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
AnnaBridge 171:3a7713b1edbc 214 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 215 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
AnnaBridge 171:3a7713b1edbc 216 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 217 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
AnnaBridge 171:3a7713b1edbc 218 ADC0_IRQn = 39, /**< ADC0 interrupt */
AnnaBridge 171:3a7713b1edbc 219 CMP0_IRQn = 40, /**< CMP0 interrupt */
AnnaBridge 171:3a7713b1edbc 220 CMP1_IRQn = 41, /**< CMP1 interrupt */
AnnaBridge 171:3a7713b1edbc 221 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 222 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 223 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 224 CMT_IRQn = 45, /**< CMT interrupt */
AnnaBridge 171:3a7713b1edbc 225 RTC_IRQn = 46, /**< RTC interrupt */
AnnaBridge 171:3a7713b1edbc 226 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
AnnaBridge 171:3a7713b1edbc 227 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
AnnaBridge 171:3a7713b1edbc 228 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
AnnaBridge 171:3a7713b1edbc 229 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
AnnaBridge 171:3a7713b1edbc 230 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
AnnaBridge 171:3a7713b1edbc 231 PDB0_IRQn = 52, /**< PDB0 Interrupt */
AnnaBridge 171:3a7713b1edbc 232 USB0_IRQn = 53, /**< USB0 interrupt */
AnnaBridge 171:3a7713b1edbc 233 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
AnnaBridge 171:3a7713b1edbc 234 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
AnnaBridge 171:3a7713b1edbc 235 DAC0_IRQn = 56, /**< DAC0 interrupt */
AnnaBridge 171:3a7713b1edbc 236 MCG_IRQn = 57, /**< MCG Interrupt */
AnnaBridge 171:3a7713b1edbc 237 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
AnnaBridge 171:3a7713b1edbc 238 PORTA_IRQn = 59, /**< Port A interrupt */
AnnaBridge 171:3a7713b1edbc 239 PORTB_IRQn = 60, /**< Port B interrupt */
AnnaBridge 171:3a7713b1edbc 240 PORTC_IRQn = 61, /**< Port C interrupt */
AnnaBridge 171:3a7713b1edbc 241 PORTD_IRQn = 62, /**< Port D interrupt */
AnnaBridge 171:3a7713b1edbc 242 PORTE_IRQn = 63, /**< Port E interrupt */
AnnaBridge 171:3a7713b1edbc 243 SWI_IRQn = 64, /**< Software interrupt */
AnnaBridge 171:3a7713b1edbc 244 SPI2_IRQn = 65, /**< SPI2 Interrupt */
AnnaBridge 171:3a7713b1edbc 245 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 246 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
AnnaBridge 171:3a7713b1edbc 247 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
AnnaBridge 171:3a7713b1edbc 248 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
AnnaBridge 171:3a7713b1edbc 249 CMP2_IRQn = 70, /**< CMP2 interrupt */
AnnaBridge 171:3a7713b1edbc 250 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
AnnaBridge 171:3a7713b1edbc 251 DAC1_IRQn = 72, /**< DAC1 interrupt */
AnnaBridge 171:3a7713b1edbc 252 ADC1_IRQn = 73, /**< ADC1 interrupt */
AnnaBridge 171:3a7713b1edbc 253 I2C2_IRQn = 74, /**< I2C2 interrupt */
AnnaBridge 171:3a7713b1edbc 254 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
AnnaBridge 171:3a7713b1edbc 255 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
AnnaBridge 171:3a7713b1edbc 256 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
AnnaBridge 171:3a7713b1edbc 257 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
AnnaBridge 171:3a7713b1edbc 258 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
AnnaBridge 171:3a7713b1edbc 259 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
AnnaBridge 171:3a7713b1edbc 260 SDHC_IRQn = 81, /**< SDHC interrupt */
AnnaBridge 171:3a7713b1edbc 261 ENET_1588_Timer_IRQn = 82, /**< Ethernet MAC IEEE 1588 Timer Interrupt */
AnnaBridge 171:3a7713b1edbc 262 ENET_Transmit_IRQn = 83, /**< Ethernet MAC Transmit Interrupt */
AnnaBridge 171:3a7713b1edbc 263 ENET_Receive_IRQn = 84, /**< Ethernet MAC Receive Interrupt */
AnnaBridge 171:3a7713b1edbc 264 ENET_Error_IRQn = 85 /**< Ethernet MAC Error and miscelaneous Interrupt */
AnnaBridge 171:3a7713b1edbc 265 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 266
AnnaBridge 171:3a7713b1edbc 267 /*!
AnnaBridge 171:3a7713b1edbc 268 * @}
AnnaBridge 171:3a7713b1edbc 269 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 273 -- Cortex M4 Core Configuration
AnnaBridge 171:3a7713b1edbc 274 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 /*!
AnnaBridge 171:3a7713b1edbc 277 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
AnnaBridge 171:3a7713b1edbc 278 * @{
AnnaBridge 171:3a7713b1edbc 279 */
AnnaBridge 171:3a7713b1edbc 280
AnnaBridge 171:3a7713b1edbc 281 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 171:3a7713b1edbc 282 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 171:3a7713b1edbc 283 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 171:3a7713b1edbc 284 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 #include "core_cm4.h" /* Core Peripheral Access Layer */
AnnaBridge 171:3a7713b1edbc 287 #include "system_MK64F12.h" /* Device specific configuration file */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /*!
AnnaBridge 171:3a7713b1edbc 290 * @}
AnnaBridge 171:3a7713b1edbc 291 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293
AnnaBridge 171:3a7713b1edbc 294 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 295 -- Mapping Information
AnnaBridge 171:3a7713b1edbc 296 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 297
AnnaBridge 171:3a7713b1edbc 298 /*!
AnnaBridge 171:3a7713b1edbc 299 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 171:3a7713b1edbc 300 * @{
AnnaBridge 171:3a7713b1edbc 301 */
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 /** Mapping Information */
AnnaBridge 171:3a7713b1edbc 304 /*!
AnnaBridge 171:3a7713b1edbc 305 * @addtogroup edma_request
AnnaBridge 171:3a7713b1edbc 306 * @{
AnnaBridge 171:3a7713b1edbc 307 */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /*******************************************************************************
AnnaBridge 171:3a7713b1edbc 310 * Definitions
AnnaBridge 171:3a7713b1edbc 311 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 312
AnnaBridge 171:3a7713b1edbc 313 /*!
AnnaBridge 171:3a7713b1edbc 314 * @brief Structure for the DMA hardware request
AnnaBridge 171:3a7713b1edbc 315 *
AnnaBridge 171:3a7713b1edbc 316 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 171:3a7713b1edbc 317 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 171:3a7713b1edbc 318 * of the hardware request varies according to the to SoC.
AnnaBridge 171:3a7713b1edbc 319 */
AnnaBridge 171:3a7713b1edbc 320 typedef enum _dma_request_source
AnnaBridge 171:3a7713b1edbc 321 {
AnnaBridge 171:3a7713b1edbc 322 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 171:3a7713b1edbc 323 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
AnnaBridge 171:3a7713b1edbc 324 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
AnnaBridge 171:3a7713b1edbc 325 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
AnnaBridge 171:3a7713b1edbc 326 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
AnnaBridge 171:3a7713b1edbc 327 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
AnnaBridge 171:3a7713b1edbc 328 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
AnnaBridge 171:3a7713b1edbc 329 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
AnnaBridge 171:3a7713b1edbc 330 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
AnnaBridge 171:3a7713b1edbc 331 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
AnnaBridge 171:3a7713b1edbc 332 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
AnnaBridge 171:3a7713b1edbc 333 kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */
AnnaBridge 171:3a7713b1edbc 334 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
AnnaBridge 171:3a7713b1edbc 335 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
AnnaBridge 171:3a7713b1edbc 336 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
AnnaBridge 171:3a7713b1edbc 337 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
AnnaBridge 171:3a7713b1edbc 338 kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
AnnaBridge 171:3a7713b1edbc 339 kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */
AnnaBridge 171:3a7713b1edbc 340 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
AnnaBridge 171:3a7713b1edbc 341 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 171:3a7713b1edbc 342 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 171:3a7713b1edbc 343 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 171:3a7713b1edbc 344 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
AnnaBridge 171:3a7713b1edbc 345 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
AnnaBridge 171:3a7713b1edbc 346 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
AnnaBridge 171:3a7713b1edbc 347 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
AnnaBridge 171:3a7713b1edbc 348 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
AnnaBridge 171:3a7713b1edbc 349 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
AnnaBridge 171:3a7713b1edbc 350 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
AnnaBridge 171:3a7713b1edbc 351 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
AnnaBridge 171:3a7713b1edbc 352 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
AnnaBridge 171:3a7713b1edbc 353 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
AnnaBridge 171:3a7713b1edbc 354 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
AnnaBridge 171:3a7713b1edbc 355 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
AnnaBridge 171:3a7713b1edbc 356 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
AnnaBridge 171:3a7713b1edbc 357 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
AnnaBridge 171:3a7713b1edbc 358 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
AnnaBridge 171:3a7713b1edbc 359 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
AnnaBridge 171:3a7713b1edbc 360 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
AnnaBridge 171:3a7713b1edbc 361 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
AnnaBridge 171:3a7713b1edbc 362 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
AnnaBridge 171:3a7713b1edbc 363 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
AnnaBridge 171:3a7713b1edbc 364 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 171:3a7713b1edbc 365 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
AnnaBridge 171:3a7713b1edbc 366 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 171:3a7713b1edbc 367 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
AnnaBridge 171:3a7713b1edbc 368 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */
AnnaBridge 171:3a7713b1edbc 369 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
AnnaBridge 171:3a7713b1edbc 370 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
AnnaBridge 171:3a7713b1edbc 371 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
AnnaBridge 171:3a7713b1edbc 372 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
AnnaBridge 171:3a7713b1edbc 373 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 171:3a7713b1edbc 374 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 171:3a7713b1edbc 375 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 171:3a7713b1edbc 376 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
AnnaBridge 171:3a7713b1edbc 377 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
AnnaBridge 171:3a7713b1edbc 378 kDmaRequestMux0IEEE1588Timer0 = 54|0x100U, /**< ENET IEEE 1588 timer 0. */
AnnaBridge 171:3a7713b1edbc 379 kDmaRequestMux0IEEE1588Timer1 = 55|0x100U, /**< ENET IEEE 1588 timer 1. */
AnnaBridge 171:3a7713b1edbc 380 kDmaRequestMux0IEEE1588Timer2 = 56|0x100U, /**< ENET IEEE 1588 timer 2. */
AnnaBridge 171:3a7713b1edbc 381 kDmaRequestMux0IEEE1588Timer3 = 57|0x100U, /**< ENET IEEE 1588 timer 3. */
AnnaBridge 171:3a7713b1edbc 382 kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 383 kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 384 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 385 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 386 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 387 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 171:3a7713b1edbc 388 } dma_request_source_t;
AnnaBridge 171:3a7713b1edbc 389
AnnaBridge 171:3a7713b1edbc 390 /* @} */
AnnaBridge 171:3a7713b1edbc 391
AnnaBridge 171:3a7713b1edbc 392
AnnaBridge 171:3a7713b1edbc 393 /*!
AnnaBridge 171:3a7713b1edbc 394 * @}
AnnaBridge 171:3a7713b1edbc 395 */ /* end of group Mapping_Information */
AnnaBridge 171:3a7713b1edbc 396
AnnaBridge 171:3a7713b1edbc 397
AnnaBridge 171:3a7713b1edbc 398 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 399 -- Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 400 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 401
AnnaBridge 171:3a7713b1edbc 402 /*!
AnnaBridge 171:3a7713b1edbc 403 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 404 * @{
AnnaBridge 171:3a7713b1edbc 405 */
AnnaBridge 171:3a7713b1edbc 406
AnnaBridge 171:3a7713b1edbc 407
AnnaBridge 171:3a7713b1edbc 408 /*
AnnaBridge 171:3a7713b1edbc 409 ** Start of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 410 */
AnnaBridge 171:3a7713b1edbc 411
AnnaBridge 171:3a7713b1edbc 412 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 413 #pragma push
AnnaBridge 171:3a7713b1edbc 414 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 415 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 416 #pragma push
AnnaBridge 171:3a7713b1edbc 417 #pragma cpp_extensions on
AnnaBridge 171:3a7713b1edbc 418 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 419 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 420 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 421 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 422 #else
AnnaBridge 171:3a7713b1edbc 423 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 424 #endif
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 427 -- ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 428 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 429
AnnaBridge 171:3a7713b1edbc 430 /*!
AnnaBridge 171:3a7713b1edbc 431 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 432 * @{
AnnaBridge 171:3a7713b1edbc 433 */
AnnaBridge 171:3a7713b1edbc 434
AnnaBridge 171:3a7713b1edbc 435 /** ADC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 436 typedef struct {
AnnaBridge 171:3a7713b1edbc 437 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 438 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 439 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 440 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 441 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 443 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 444 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 445 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 446 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 448 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 450 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 452 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 453 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 454 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 455 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 456 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 457 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 458 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 459 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 460 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 461 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 462 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 463 } ADC_Type;
AnnaBridge 171:3a7713b1edbc 464
AnnaBridge 171:3a7713b1edbc 465 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 466 -- ADC Register Masks
AnnaBridge 171:3a7713b1edbc 467 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 468
AnnaBridge 171:3a7713b1edbc 469 /*!
AnnaBridge 171:3a7713b1edbc 470 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 171:3a7713b1edbc 471 * @{
AnnaBridge 171:3a7713b1edbc 472 */
AnnaBridge 171:3a7713b1edbc 473
AnnaBridge 171:3a7713b1edbc 474 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 171:3a7713b1edbc 475 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 476 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 477 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 171:3a7713b1edbc 478 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 479 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 480 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 171:3a7713b1edbc 481 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 482 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 483 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 171:3a7713b1edbc 484 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 485 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 486 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 171:3a7713b1edbc 487
AnnaBridge 171:3a7713b1edbc 488 /* The count of ADC_SC1 */
AnnaBridge 171:3a7713b1edbc 489 #define ADC_SC1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 490
AnnaBridge 171:3a7713b1edbc 491 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 492 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 493 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 494 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 171:3a7713b1edbc 495 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 496 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 497 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 498 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 499 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 500 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 171:3a7713b1edbc 501 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 502 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 503 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 171:3a7713b1edbc 504 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 505 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 506 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 509 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 510 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 511 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 171:3a7713b1edbc 512 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 513 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 514 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 171:3a7713b1edbc 515 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 516 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 517 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 171:3a7713b1edbc 518 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 519 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 520 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 171:3a7713b1edbc 521
AnnaBridge 171:3a7713b1edbc 522 /*! @name R - ADC Data Result Register */
AnnaBridge 171:3a7713b1edbc 523 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 524 #define ADC_R_D_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 525 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 171:3a7713b1edbc 526
AnnaBridge 171:3a7713b1edbc 527 /* The count of ADC_R */
AnnaBridge 171:3a7713b1edbc 528 #define ADC_R_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 529
AnnaBridge 171:3a7713b1edbc 530 /*! @name CV1 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 531 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 532 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 533 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 171:3a7713b1edbc 534
AnnaBridge 171:3a7713b1edbc 535 /*! @name CV2 - Compare Value Registers */
AnnaBridge 171:3a7713b1edbc 536 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 537 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 538 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 171:3a7713b1edbc 539
AnnaBridge 171:3a7713b1edbc 540 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 171:3a7713b1edbc 541 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 542 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 543 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 171:3a7713b1edbc 544 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 545 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 546 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 547 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 548 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 549 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 171:3a7713b1edbc 550 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 551 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 552 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 171:3a7713b1edbc 553 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 554 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 555 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 171:3a7713b1edbc 556 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 557 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 558 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 171:3a7713b1edbc 559 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 560 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 561 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 171:3a7713b1edbc 562
AnnaBridge 171:3a7713b1edbc 563 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 171:3a7713b1edbc 564 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 565 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 566 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 171:3a7713b1edbc 567 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 568 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 569 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 171:3a7713b1edbc 570 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 571 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 572 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 171:3a7713b1edbc 573 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 574 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 575 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 171:3a7713b1edbc 576 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 577 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 578 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 171:3a7713b1edbc 579
AnnaBridge 171:3a7713b1edbc 580 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 171:3a7713b1edbc 581 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 582 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 583 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 171:3a7713b1edbc 584
AnnaBridge 171:3a7713b1edbc 585 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 586 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 587 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 588 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 171:3a7713b1edbc 589
AnnaBridge 171:3a7713b1edbc 590 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 171:3a7713b1edbc 591 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 592 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 593 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 171:3a7713b1edbc 594
AnnaBridge 171:3a7713b1edbc 595 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 596 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 597 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 598 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 171:3a7713b1edbc 599
AnnaBridge 171:3a7713b1edbc 600 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 601 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 602 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 603 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 171:3a7713b1edbc 604
AnnaBridge 171:3a7713b1edbc 605 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 606 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 607 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 608 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 171:3a7713b1edbc 609
AnnaBridge 171:3a7713b1edbc 610 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 611 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 612 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 613 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 171:3a7713b1edbc 614
AnnaBridge 171:3a7713b1edbc 615 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 616 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 617 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 618 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 171:3a7713b1edbc 619
AnnaBridge 171:3a7713b1edbc 620 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 621 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 622 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 623 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 171:3a7713b1edbc 624
AnnaBridge 171:3a7713b1edbc 625 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 626 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 627 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 628 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 171:3a7713b1edbc 629
AnnaBridge 171:3a7713b1edbc 630 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 631 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 632 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 633 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 171:3a7713b1edbc 634
AnnaBridge 171:3a7713b1edbc 635 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 636 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 637 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 638 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 171:3a7713b1edbc 639
AnnaBridge 171:3a7713b1edbc 640 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 641 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 642 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 643 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 171:3a7713b1edbc 644
AnnaBridge 171:3a7713b1edbc 645 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 646 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 647 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 648 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 171:3a7713b1edbc 649
AnnaBridge 171:3a7713b1edbc 650 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 651 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 652 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 653 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 171:3a7713b1edbc 654
AnnaBridge 171:3a7713b1edbc 655 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 656 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 657 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 658 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 171:3a7713b1edbc 661 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 662 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 663 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 /*!
AnnaBridge 171:3a7713b1edbc 667 * @}
AnnaBridge 171:3a7713b1edbc 668 */ /* end of group ADC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670
AnnaBridge 171:3a7713b1edbc 671 /* ADC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 672 /** Peripheral ADC0 base address */
AnnaBridge 171:3a7713b1edbc 673 #define ADC0_BASE (0x4003B000u)
AnnaBridge 171:3a7713b1edbc 674 /** Peripheral ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 675 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 171:3a7713b1edbc 676 /** Peripheral ADC1 base address */
AnnaBridge 171:3a7713b1edbc 677 #define ADC1_BASE (0x400BB000u)
AnnaBridge 171:3a7713b1edbc 678 /** Peripheral ADC1 base pointer */
AnnaBridge 171:3a7713b1edbc 679 #define ADC1 ((ADC_Type *)ADC1_BASE)
AnnaBridge 171:3a7713b1edbc 680 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 681 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
AnnaBridge 171:3a7713b1edbc 682 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 683 #define ADC_BASE_PTRS { ADC0, ADC1 }
AnnaBridge 171:3a7713b1edbc 684 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 171:3a7713b1edbc 685 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
AnnaBridge 171:3a7713b1edbc 686
AnnaBridge 171:3a7713b1edbc 687 /*!
AnnaBridge 171:3a7713b1edbc 688 * @}
AnnaBridge 171:3a7713b1edbc 689 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 690
AnnaBridge 171:3a7713b1edbc 691
AnnaBridge 171:3a7713b1edbc 692 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 693 -- AIPS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 694 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 695
AnnaBridge 171:3a7713b1edbc 696 /*!
AnnaBridge 171:3a7713b1edbc 697 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 698 * @{
AnnaBridge 171:3a7713b1edbc 699 */
AnnaBridge 171:3a7713b1edbc 700
AnnaBridge 171:3a7713b1edbc 701 /** AIPS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 702 typedef struct {
AnnaBridge 171:3a7713b1edbc 703 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 704 uint8_t RESERVED_0[28];
AnnaBridge 171:3a7713b1edbc 705 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 706 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 707 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 708 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 709 uint8_t RESERVED_1[16];
AnnaBridge 171:3a7713b1edbc 710 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 711 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 712 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 713 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 714 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 715 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 716 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 717 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 718 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 719 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 720 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 721 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 722 uint8_t RESERVED_2[16];
AnnaBridge 171:3a7713b1edbc 723 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 724 } AIPS_Type;
AnnaBridge 171:3a7713b1edbc 725
AnnaBridge 171:3a7713b1edbc 726 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 727 -- AIPS Register Masks
AnnaBridge 171:3a7713b1edbc 728 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 729
AnnaBridge 171:3a7713b1edbc 730 /*!
AnnaBridge 171:3a7713b1edbc 731 * @addtogroup AIPS_Register_Masks AIPS Register Masks
AnnaBridge 171:3a7713b1edbc 732 * @{
AnnaBridge 171:3a7713b1edbc 733 */
AnnaBridge 171:3a7713b1edbc 734
AnnaBridge 171:3a7713b1edbc 735 /*! @name MPRA - Master Privilege Register A */
AnnaBridge 171:3a7713b1edbc 736 #define AIPS_MPRA_MPL5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 737 #define AIPS_MPRA_MPL5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 738 #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
AnnaBridge 171:3a7713b1edbc 739 #define AIPS_MPRA_MTW5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 740 #define AIPS_MPRA_MTW5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 741 #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
AnnaBridge 171:3a7713b1edbc 742 #define AIPS_MPRA_MTR5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 743 #define AIPS_MPRA_MTR5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 744 #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
AnnaBridge 171:3a7713b1edbc 745 #define AIPS_MPRA_MPL4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 746 #define AIPS_MPRA_MPL4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 747 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
AnnaBridge 171:3a7713b1edbc 748 #define AIPS_MPRA_MTW4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 749 #define AIPS_MPRA_MTW4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 750 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
AnnaBridge 171:3a7713b1edbc 751 #define AIPS_MPRA_MTR4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 752 #define AIPS_MPRA_MTR4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 753 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
AnnaBridge 171:3a7713b1edbc 754 #define AIPS_MPRA_MPL3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 755 #define AIPS_MPRA_MPL3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 756 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
AnnaBridge 171:3a7713b1edbc 757 #define AIPS_MPRA_MTW3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 758 #define AIPS_MPRA_MTW3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 759 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
AnnaBridge 171:3a7713b1edbc 760 #define AIPS_MPRA_MTR3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 761 #define AIPS_MPRA_MTR3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 762 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
AnnaBridge 171:3a7713b1edbc 763 #define AIPS_MPRA_MPL2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 764 #define AIPS_MPRA_MPL2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 765 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
AnnaBridge 171:3a7713b1edbc 766 #define AIPS_MPRA_MTW2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 767 #define AIPS_MPRA_MTW2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 768 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
AnnaBridge 171:3a7713b1edbc 769 #define AIPS_MPRA_MTR2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 770 #define AIPS_MPRA_MTR2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 771 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
AnnaBridge 171:3a7713b1edbc 772 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 773 #define AIPS_MPRA_MPL1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 774 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
AnnaBridge 171:3a7713b1edbc 775 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 776 #define AIPS_MPRA_MTW1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 777 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
AnnaBridge 171:3a7713b1edbc 778 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 779 #define AIPS_MPRA_MTR1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 780 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
AnnaBridge 171:3a7713b1edbc 781 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 782 #define AIPS_MPRA_MPL0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 783 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
AnnaBridge 171:3a7713b1edbc 784 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 785 #define AIPS_MPRA_MTW0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 786 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
AnnaBridge 171:3a7713b1edbc 787 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 788 #define AIPS_MPRA_MTR0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 789 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
AnnaBridge 171:3a7713b1edbc 790
AnnaBridge 171:3a7713b1edbc 791 /*! @name PACRA - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 792 #define AIPS_PACRA_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 793 #define AIPS_PACRA_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 794 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 795 #define AIPS_PACRA_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 796 #define AIPS_PACRA_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 797 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 798 #define AIPS_PACRA_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 799 #define AIPS_PACRA_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 800 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 801 #define AIPS_PACRA_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 802 #define AIPS_PACRA_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 803 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 804 #define AIPS_PACRA_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 805 #define AIPS_PACRA_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 806 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 807 #define AIPS_PACRA_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 808 #define AIPS_PACRA_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 809 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 810 #define AIPS_PACRA_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 811 #define AIPS_PACRA_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 812 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 813 #define AIPS_PACRA_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 814 #define AIPS_PACRA_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 815 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 816 #define AIPS_PACRA_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 817 #define AIPS_PACRA_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 818 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 819 #define AIPS_PACRA_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 820 #define AIPS_PACRA_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 821 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 822 #define AIPS_PACRA_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 823 #define AIPS_PACRA_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 824 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 825 #define AIPS_PACRA_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 826 #define AIPS_PACRA_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 827 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 828 #define AIPS_PACRA_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 829 #define AIPS_PACRA_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 830 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 831 #define AIPS_PACRA_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 832 #define AIPS_PACRA_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 833 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 834 #define AIPS_PACRA_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 835 #define AIPS_PACRA_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 836 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 837 #define AIPS_PACRA_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 838 #define AIPS_PACRA_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 839 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 840 #define AIPS_PACRA_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 841 #define AIPS_PACRA_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 842 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 843 #define AIPS_PACRA_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 844 #define AIPS_PACRA_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 845 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 846 #define AIPS_PACRA_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 847 #define AIPS_PACRA_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 848 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 849 #define AIPS_PACRA_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 850 #define AIPS_PACRA_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 851 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 852 #define AIPS_PACRA_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 853 #define AIPS_PACRA_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 854 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 855 #define AIPS_PACRA_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 856 #define AIPS_PACRA_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 857 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 858 #define AIPS_PACRA_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 859 #define AIPS_PACRA_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 860 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 861 #define AIPS_PACRA_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 862 #define AIPS_PACRA_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 863 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 864
AnnaBridge 171:3a7713b1edbc 865 /*! @name PACRB - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 866 #define AIPS_PACRB_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 867 #define AIPS_PACRB_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 868 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 869 #define AIPS_PACRB_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 870 #define AIPS_PACRB_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 871 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 872 #define AIPS_PACRB_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 873 #define AIPS_PACRB_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 874 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 875 #define AIPS_PACRB_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 876 #define AIPS_PACRB_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 877 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 878 #define AIPS_PACRB_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 879 #define AIPS_PACRB_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 880 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 881 #define AIPS_PACRB_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 882 #define AIPS_PACRB_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 883 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 884 #define AIPS_PACRB_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 885 #define AIPS_PACRB_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 886 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 887 #define AIPS_PACRB_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 888 #define AIPS_PACRB_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 889 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 890 #define AIPS_PACRB_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 891 #define AIPS_PACRB_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 892 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 893 #define AIPS_PACRB_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 894 #define AIPS_PACRB_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 895 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 896 #define AIPS_PACRB_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 897 #define AIPS_PACRB_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 898 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 899 #define AIPS_PACRB_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 900 #define AIPS_PACRB_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 901 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 902 #define AIPS_PACRB_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 903 #define AIPS_PACRB_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 904 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 905 #define AIPS_PACRB_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 906 #define AIPS_PACRB_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 907 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 908 #define AIPS_PACRB_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 909 #define AIPS_PACRB_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 910 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 911 #define AIPS_PACRB_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 912 #define AIPS_PACRB_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 913 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 914 #define AIPS_PACRB_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 915 #define AIPS_PACRB_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 916 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 917 #define AIPS_PACRB_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 918 #define AIPS_PACRB_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 919 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 920 #define AIPS_PACRB_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 921 #define AIPS_PACRB_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 922 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 923 #define AIPS_PACRB_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 924 #define AIPS_PACRB_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 925 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 926 #define AIPS_PACRB_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 927 #define AIPS_PACRB_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 928 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 929 #define AIPS_PACRB_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 930 #define AIPS_PACRB_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 931 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 932 #define AIPS_PACRB_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 933 #define AIPS_PACRB_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 934 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 935 #define AIPS_PACRB_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 936 #define AIPS_PACRB_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 937 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 938
AnnaBridge 171:3a7713b1edbc 939 /*! @name PACRC - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 940 #define AIPS_PACRC_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 941 #define AIPS_PACRC_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 942 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 943 #define AIPS_PACRC_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 944 #define AIPS_PACRC_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 945 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 946 #define AIPS_PACRC_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 947 #define AIPS_PACRC_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 948 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 949 #define AIPS_PACRC_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 950 #define AIPS_PACRC_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 951 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 952 #define AIPS_PACRC_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 953 #define AIPS_PACRC_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 954 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 955 #define AIPS_PACRC_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 956 #define AIPS_PACRC_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 957 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 958 #define AIPS_PACRC_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 959 #define AIPS_PACRC_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 960 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 961 #define AIPS_PACRC_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 962 #define AIPS_PACRC_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 963 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 964 #define AIPS_PACRC_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 965 #define AIPS_PACRC_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 966 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 967 #define AIPS_PACRC_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 968 #define AIPS_PACRC_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 969 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 970 #define AIPS_PACRC_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 971 #define AIPS_PACRC_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 972 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 973 #define AIPS_PACRC_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 974 #define AIPS_PACRC_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 975 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 976 #define AIPS_PACRC_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 977 #define AIPS_PACRC_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 978 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 979 #define AIPS_PACRC_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 980 #define AIPS_PACRC_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 981 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 982 #define AIPS_PACRC_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 983 #define AIPS_PACRC_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 984 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 985 #define AIPS_PACRC_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 986 #define AIPS_PACRC_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 987 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 988 #define AIPS_PACRC_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 989 #define AIPS_PACRC_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 990 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 991 #define AIPS_PACRC_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 992 #define AIPS_PACRC_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 993 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 994 #define AIPS_PACRC_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 995 #define AIPS_PACRC_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 996 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 997 #define AIPS_PACRC_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 998 #define AIPS_PACRC_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 999 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1000 #define AIPS_PACRC_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1001 #define AIPS_PACRC_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1002 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1003 #define AIPS_PACRC_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1004 #define AIPS_PACRC_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1005 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1006 #define AIPS_PACRC_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1007 #define AIPS_PACRC_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1008 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1009 #define AIPS_PACRC_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1010 #define AIPS_PACRC_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1011 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1012
AnnaBridge 171:3a7713b1edbc 1013 /*! @name PACRD - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1014 #define AIPS_PACRD_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1015 #define AIPS_PACRD_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1016 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1017 #define AIPS_PACRD_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1018 #define AIPS_PACRD_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1019 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1020 #define AIPS_PACRD_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1021 #define AIPS_PACRD_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1022 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1023 #define AIPS_PACRD_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1024 #define AIPS_PACRD_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1025 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1026 #define AIPS_PACRD_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1027 #define AIPS_PACRD_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1028 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1029 #define AIPS_PACRD_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1030 #define AIPS_PACRD_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1031 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1032 #define AIPS_PACRD_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1033 #define AIPS_PACRD_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1034 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1035 #define AIPS_PACRD_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1036 #define AIPS_PACRD_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1037 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1038 #define AIPS_PACRD_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1039 #define AIPS_PACRD_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1040 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1041 #define AIPS_PACRD_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1042 #define AIPS_PACRD_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1043 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1044 #define AIPS_PACRD_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1045 #define AIPS_PACRD_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1046 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1047 #define AIPS_PACRD_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1048 #define AIPS_PACRD_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1049 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1050 #define AIPS_PACRD_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1051 #define AIPS_PACRD_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1052 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1053 #define AIPS_PACRD_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1054 #define AIPS_PACRD_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1055 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1056 #define AIPS_PACRD_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1057 #define AIPS_PACRD_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1058 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1059 #define AIPS_PACRD_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1060 #define AIPS_PACRD_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1061 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1062 #define AIPS_PACRD_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1063 #define AIPS_PACRD_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1064 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1065 #define AIPS_PACRD_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1066 #define AIPS_PACRD_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1067 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1068 #define AIPS_PACRD_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1069 #define AIPS_PACRD_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1070 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1071 #define AIPS_PACRD_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1072 #define AIPS_PACRD_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1073 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1074 #define AIPS_PACRD_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1075 #define AIPS_PACRD_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1076 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1077 #define AIPS_PACRD_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1078 #define AIPS_PACRD_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1079 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1080 #define AIPS_PACRD_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1081 #define AIPS_PACRD_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1082 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1083 #define AIPS_PACRD_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1084 #define AIPS_PACRD_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1085 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1086
AnnaBridge 171:3a7713b1edbc 1087 /*! @name PACRE - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1088 #define AIPS_PACRE_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1089 #define AIPS_PACRE_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1090 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1091 #define AIPS_PACRE_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1092 #define AIPS_PACRE_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1093 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1094 #define AIPS_PACRE_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1095 #define AIPS_PACRE_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1096 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1097 #define AIPS_PACRE_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1098 #define AIPS_PACRE_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1099 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1100 #define AIPS_PACRE_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1101 #define AIPS_PACRE_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1102 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1103 #define AIPS_PACRE_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1104 #define AIPS_PACRE_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1105 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1106 #define AIPS_PACRE_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1107 #define AIPS_PACRE_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1108 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1109 #define AIPS_PACRE_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1110 #define AIPS_PACRE_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1111 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1112 #define AIPS_PACRE_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1113 #define AIPS_PACRE_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1114 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1115 #define AIPS_PACRE_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1116 #define AIPS_PACRE_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1117 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1118 #define AIPS_PACRE_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1119 #define AIPS_PACRE_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1120 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1121 #define AIPS_PACRE_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1122 #define AIPS_PACRE_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1123 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1124 #define AIPS_PACRE_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1125 #define AIPS_PACRE_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1126 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1127 #define AIPS_PACRE_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1128 #define AIPS_PACRE_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1129 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1130 #define AIPS_PACRE_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1131 #define AIPS_PACRE_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1132 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1133 #define AIPS_PACRE_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1134 #define AIPS_PACRE_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1135 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1136 #define AIPS_PACRE_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1137 #define AIPS_PACRE_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1138 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1139 #define AIPS_PACRE_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1140 #define AIPS_PACRE_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1141 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1142 #define AIPS_PACRE_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1143 #define AIPS_PACRE_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1144 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1145 #define AIPS_PACRE_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1146 #define AIPS_PACRE_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1147 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1148 #define AIPS_PACRE_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1149 #define AIPS_PACRE_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1150 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1151 #define AIPS_PACRE_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1152 #define AIPS_PACRE_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1153 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1154 #define AIPS_PACRE_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1155 #define AIPS_PACRE_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1156 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1157 #define AIPS_PACRE_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1158 #define AIPS_PACRE_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1159 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1160
AnnaBridge 171:3a7713b1edbc 1161 /*! @name PACRF - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1162 #define AIPS_PACRF_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1163 #define AIPS_PACRF_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1164 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1165 #define AIPS_PACRF_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1166 #define AIPS_PACRF_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1167 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1168 #define AIPS_PACRF_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1169 #define AIPS_PACRF_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1170 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1171 #define AIPS_PACRF_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1172 #define AIPS_PACRF_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1173 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1174 #define AIPS_PACRF_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1175 #define AIPS_PACRF_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1176 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1177 #define AIPS_PACRF_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1178 #define AIPS_PACRF_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1179 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1180 #define AIPS_PACRF_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1181 #define AIPS_PACRF_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1182 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1183 #define AIPS_PACRF_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1184 #define AIPS_PACRF_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1185 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1186 #define AIPS_PACRF_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1187 #define AIPS_PACRF_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1188 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1189 #define AIPS_PACRF_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1190 #define AIPS_PACRF_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1191 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1192 #define AIPS_PACRF_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1193 #define AIPS_PACRF_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1194 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1195 #define AIPS_PACRF_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1196 #define AIPS_PACRF_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1197 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1198 #define AIPS_PACRF_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1199 #define AIPS_PACRF_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1200 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1201 #define AIPS_PACRF_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1202 #define AIPS_PACRF_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1203 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1204 #define AIPS_PACRF_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1205 #define AIPS_PACRF_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1206 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1207 #define AIPS_PACRF_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1208 #define AIPS_PACRF_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1209 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1210 #define AIPS_PACRF_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1211 #define AIPS_PACRF_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1212 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1213 #define AIPS_PACRF_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1214 #define AIPS_PACRF_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1215 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1216 #define AIPS_PACRF_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1217 #define AIPS_PACRF_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1218 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1219 #define AIPS_PACRF_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1220 #define AIPS_PACRF_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1221 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1222 #define AIPS_PACRF_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1223 #define AIPS_PACRF_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1224 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1225 #define AIPS_PACRF_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1226 #define AIPS_PACRF_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1227 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1228 #define AIPS_PACRF_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1229 #define AIPS_PACRF_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1230 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1231 #define AIPS_PACRF_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1232 #define AIPS_PACRF_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1233 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1234
AnnaBridge 171:3a7713b1edbc 1235 /*! @name PACRG - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1236 #define AIPS_PACRG_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1237 #define AIPS_PACRG_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1238 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1239 #define AIPS_PACRG_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1240 #define AIPS_PACRG_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1241 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1242 #define AIPS_PACRG_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1243 #define AIPS_PACRG_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1244 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1245 #define AIPS_PACRG_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1246 #define AIPS_PACRG_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1247 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1248 #define AIPS_PACRG_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1249 #define AIPS_PACRG_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1250 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1251 #define AIPS_PACRG_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1252 #define AIPS_PACRG_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1253 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1254 #define AIPS_PACRG_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1255 #define AIPS_PACRG_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1256 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1257 #define AIPS_PACRG_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1258 #define AIPS_PACRG_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1259 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1260 #define AIPS_PACRG_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1261 #define AIPS_PACRG_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1262 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1263 #define AIPS_PACRG_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1264 #define AIPS_PACRG_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1265 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1266 #define AIPS_PACRG_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1267 #define AIPS_PACRG_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1268 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1269 #define AIPS_PACRG_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1270 #define AIPS_PACRG_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1271 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1272 #define AIPS_PACRG_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1273 #define AIPS_PACRG_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1274 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1275 #define AIPS_PACRG_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1276 #define AIPS_PACRG_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1277 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1278 #define AIPS_PACRG_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1279 #define AIPS_PACRG_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1280 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1281 #define AIPS_PACRG_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1282 #define AIPS_PACRG_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1283 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1284 #define AIPS_PACRG_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1285 #define AIPS_PACRG_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1286 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1287 #define AIPS_PACRG_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1288 #define AIPS_PACRG_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1289 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1290 #define AIPS_PACRG_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1291 #define AIPS_PACRG_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1292 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1293 #define AIPS_PACRG_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1294 #define AIPS_PACRG_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1295 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1296 #define AIPS_PACRG_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1297 #define AIPS_PACRG_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1298 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1299 #define AIPS_PACRG_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1300 #define AIPS_PACRG_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1301 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1302 #define AIPS_PACRG_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1303 #define AIPS_PACRG_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1304 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1305 #define AIPS_PACRG_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1306 #define AIPS_PACRG_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1307 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1308
AnnaBridge 171:3a7713b1edbc 1309 /*! @name PACRH - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1310 #define AIPS_PACRH_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1311 #define AIPS_PACRH_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1312 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1313 #define AIPS_PACRH_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1314 #define AIPS_PACRH_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1315 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1316 #define AIPS_PACRH_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1317 #define AIPS_PACRH_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1318 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1319 #define AIPS_PACRH_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1320 #define AIPS_PACRH_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1321 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1322 #define AIPS_PACRH_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1323 #define AIPS_PACRH_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1324 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1325 #define AIPS_PACRH_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1326 #define AIPS_PACRH_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1327 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1328 #define AIPS_PACRH_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1329 #define AIPS_PACRH_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1330 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1331 #define AIPS_PACRH_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1332 #define AIPS_PACRH_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1333 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1334 #define AIPS_PACRH_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1335 #define AIPS_PACRH_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1336 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1337 #define AIPS_PACRH_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1338 #define AIPS_PACRH_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1339 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1340 #define AIPS_PACRH_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1341 #define AIPS_PACRH_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1342 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1343 #define AIPS_PACRH_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1344 #define AIPS_PACRH_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1345 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1346 #define AIPS_PACRH_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1347 #define AIPS_PACRH_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1348 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1349 #define AIPS_PACRH_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1350 #define AIPS_PACRH_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1351 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1352 #define AIPS_PACRH_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1353 #define AIPS_PACRH_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1354 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1355 #define AIPS_PACRH_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1356 #define AIPS_PACRH_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1357 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1358 #define AIPS_PACRH_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1359 #define AIPS_PACRH_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1360 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1361 #define AIPS_PACRH_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1362 #define AIPS_PACRH_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1363 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1364 #define AIPS_PACRH_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1365 #define AIPS_PACRH_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1366 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1367 #define AIPS_PACRH_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1368 #define AIPS_PACRH_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1369 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1370 #define AIPS_PACRH_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1371 #define AIPS_PACRH_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1372 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1373 #define AIPS_PACRH_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1374 #define AIPS_PACRH_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1375 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1376 #define AIPS_PACRH_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1377 #define AIPS_PACRH_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1378 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1379 #define AIPS_PACRH_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1380 #define AIPS_PACRH_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1381 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1382
AnnaBridge 171:3a7713b1edbc 1383 /*! @name PACRI - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1384 #define AIPS_PACRI_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1385 #define AIPS_PACRI_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1386 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1387 #define AIPS_PACRI_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1388 #define AIPS_PACRI_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1389 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1390 #define AIPS_PACRI_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1391 #define AIPS_PACRI_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1392 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1393 #define AIPS_PACRI_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1394 #define AIPS_PACRI_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1395 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1396 #define AIPS_PACRI_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1397 #define AIPS_PACRI_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1398 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1399 #define AIPS_PACRI_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1400 #define AIPS_PACRI_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1401 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1402 #define AIPS_PACRI_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1403 #define AIPS_PACRI_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1404 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1405 #define AIPS_PACRI_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1406 #define AIPS_PACRI_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1407 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1408 #define AIPS_PACRI_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1409 #define AIPS_PACRI_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1410 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1411 #define AIPS_PACRI_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1412 #define AIPS_PACRI_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1413 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1414 #define AIPS_PACRI_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1415 #define AIPS_PACRI_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1416 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1417 #define AIPS_PACRI_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1418 #define AIPS_PACRI_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1419 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1420 #define AIPS_PACRI_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1421 #define AIPS_PACRI_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1422 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1423 #define AIPS_PACRI_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1424 #define AIPS_PACRI_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1425 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1426 #define AIPS_PACRI_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1427 #define AIPS_PACRI_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1428 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1429 #define AIPS_PACRI_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1430 #define AIPS_PACRI_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1431 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1432 #define AIPS_PACRI_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1433 #define AIPS_PACRI_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1434 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1435 #define AIPS_PACRI_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1436 #define AIPS_PACRI_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1437 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1438 #define AIPS_PACRI_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1439 #define AIPS_PACRI_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1440 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1441 #define AIPS_PACRI_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1442 #define AIPS_PACRI_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1443 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1444 #define AIPS_PACRI_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1445 #define AIPS_PACRI_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1446 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1447 #define AIPS_PACRI_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1448 #define AIPS_PACRI_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1449 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1450 #define AIPS_PACRI_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1451 #define AIPS_PACRI_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1452 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1453 #define AIPS_PACRI_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1454 #define AIPS_PACRI_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1455 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1456
AnnaBridge 171:3a7713b1edbc 1457 /*! @name PACRJ - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1458 #define AIPS_PACRJ_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1459 #define AIPS_PACRJ_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1460 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1461 #define AIPS_PACRJ_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1462 #define AIPS_PACRJ_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1463 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1464 #define AIPS_PACRJ_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1465 #define AIPS_PACRJ_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1466 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1467 #define AIPS_PACRJ_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1468 #define AIPS_PACRJ_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1469 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1470 #define AIPS_PACRJ_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1471 #define AIPS_PACRJ_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1472 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1473 #define AIPS_PACRJ_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1474 #define AIPS_PACRJ_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1475 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1476 #define AIPS_PACRJ_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1477 #define AIPS_PACRJ_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1478 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1479 #define AIPS_PACRJ_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1480 #define AIPS_PACRJ_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1481 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1482 #define AIPS_PACRJ_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1483 #define AIPS_PACRJ_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1484 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1485 #define AIPS_PACRJ_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1486 #define AIPS_PACRJ_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1487 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1488 #define AIPS_PACRJ_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1489 #define AIPS_PACRJ_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1490 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1491 #define AIPS_PACRJ_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1492 #define AIPS_PACRJ_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1493 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1494 #define AIPS_PACRJ_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1495 #define AIPS_PACRJ_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1496 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1497 #define AIPS_PACRJ_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1498 #define AIPS_PACRJ_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1499 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1500 #define AIPS_PACRJ_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1501 #define AIPS_PACRJ_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1502 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1503 #define AIPS_PACRJ_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1504 #define AIPS_PACRJ_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1505 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1506 #define AIPS_PACRJ_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1507 #define AIPS_PACRJ_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1508 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1509 #define AIPS_PACRJ_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1510 #define AIPS_PACRJ_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1511 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1512 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1513 #define AIPS_PACRJ_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1514 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1515 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1516 #define AIPS_PACRJ_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1517 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1518 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1519 #define AIPS_PACRJ_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1520 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1521 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1522 #define AIPS_PACRJ_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1523 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1524 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1525 #define AIPS_PACRJ_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1526 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1527 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1528 #define AIPS_PACRJ_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1529 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1530
AnnaBridge 171:3a7713b1edbc 1531 /*! @name PACRK - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1532 #define AIPS_PACRK_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1533 #define AIPS_PACRK_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1534 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1535 #define AIPS_PACRK_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1536 #define AIPS_PACRK_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1537 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1538 #define AIPS_PACRK_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1539 #define AIPS_PACRK_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1540 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1541 #define AIPS_PACRK_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1542 #define AIPS_PACRK_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1543 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1544 #define AIPS_PACRK_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1545 #define AIPS_PACRK_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1546 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1547 #define AIPS_PACRK_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1548 #define AIPS_PACRK_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1549 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1550 #define AIPS_PACRK_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1551 #define AIPS_PACRK_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1552 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1553 #define AIPS_PACRK_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1554 #define AIPS_PACRK_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1555 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1556 #define AIPS_PACRK_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1557 #define AIPS_PACRK_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1558 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1559 #define AIPS_PACRK_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1560 #define AIPS_PACRK_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1561 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1562 #define AIPS_PACRK_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1563 #define AIPS_PACRK_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1564 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1565 #define AIPS_PACRK_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1566 #define AIPS_PACRK_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1567 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1568 #define AIPS_PACRK_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1569 #define AIPS_PACRK_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1570 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1571 #define AIPS_PACRK_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1572 #define AIPS_PACRK_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1573 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1574 #define AIPS_PACRK_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1575 #define AIPS_PACRK_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1576 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1577 #define AIPS_PACRK_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1578 #define AIPS_PACRK_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1579 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1580 #define AIPS_PACRK_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1581 #define AIPS_PACRK_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1582 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1583 #define AIPS_PACRK_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1584 #define AIPS_PACRK_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1585 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1586 #define AIPS_PACRK_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1587 #define AIPS_PACRK_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1588 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1589 #define AIPS_PACRK_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1590 #define AIPS_PACRK_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1591 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1592 #define AIPS_PACRK_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1593 #define AIPS_PACRK_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1594 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1595 #define AIPS_PACRK_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1596 #define AIPS_PACRK_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1597 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1598 #define AIPS_PACRK_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1599 #define AIPS_PACRK_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1600 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1601 #define AIPS_PACRK_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1602 #define AIPS_PACRK_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1603 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1604
AnnaBridge 171:3a7713b1edbc 1605 /*! @name PACRL - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1606 #define AIPS_PACRL_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1607 #define AIPS_PACRL_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1608 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1609 #define AIPS_PACRL_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1610 #define AIPS_PACRL_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1611 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1612 #define AIPS_PACRL_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1613 #define AIPS_PACRL_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1614 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1615 #define AIPS_PACRL_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1616 #define AIPS_PACRL_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1617 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1618 #define AIPS_PACRL_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1619 #define AIPS_PACRL_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1620 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1621 #define AIPS_PACRL_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1622 #define AIPS_PACRL_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1623 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1624 #define AIPS_PACRL_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1625 #define AIPS_PACRL_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1626 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1627 #define AIPS_PACRL_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1628 #define AIPS_PACRL_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1629 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1630 #define AIPS_PACRL_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1631 #define AIPS_PACRL_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1632 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1633 #define AIPS_PACRL_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1634 #define AIPS_PACRL_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1635 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1636 #define AIPS_PACRL_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1637 #define AIPS_PACRL_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1638 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1639 #define AIPS_PACRL_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1640 #define AIPS_PACRL_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1641 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1642 #define AIPS_PACRL_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1643 #define AIPS_PACRL_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1644 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1645 #define AIPS_PACRL_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1646 #define AIPS_PACRL_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1647 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1648 #define AIPS_PACRL_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1649 #define AIPS_PACRL_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1650 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1651 #define AIPS_PACRL_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1652 #define AIPS_PACRL_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1653 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1654 #define AIPS_PACRL_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1655 #define AIPS_PACRL_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1656 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1657 #define AIPS_PACRL_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1658 #define AIPS_PACRL_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1659 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1660 #define AIPS_PACRL_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1661 #define AIPS_PACRL_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1662 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1663 #define AIPS_PACRL_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1664 #define AIPS_PACRL_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1665 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1666 #define AIPS_PACRL_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1667 #define AIPS_PACRL_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1668 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1669 #define AIPS_PACRL_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1670 #define AIPS_PACRL_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1671 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1672 #define AIPS_PACRL_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1673 #define AIPS_PACRL_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1674 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1675 #define AIPS_PACRL_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1676 #define AIPS_PACRL_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1677 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1678
AnnaBridge 171:3a7713b1edbc 1679 /*! @name PACRM - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1680 #define AIPS_PACRM_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1681 #define AIPS_PACRM_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1682 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1683 #define AIPS_PACRM_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1684 #define AIPS_PACRM_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1685 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1686 #define AIPS_PACRM_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1687 #define AIPS_PACRM_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1688 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1689 #define AIPS_PACRM_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1690 #define AIPS_PACRM_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1691 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1692 #define AIPS_PACRM_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1693 #define AIPS_PACRM_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1694 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1695 #define AIPS_PACRM_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1696 #define AIPS_PACRM_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1697 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1698 #define AIPS_PACRM_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1699 #define AIPS_PACRM_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1700 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1701 #define AIPS_PACRM_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1702 #define AIPS_PACRM_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1703 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1704 #define AIPS_PACRM_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1705 #define AIPS_PACRM_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1706 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1707 #define AIPS_PACRM_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1708 #define AIPS_PACRM_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1709 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1710 #define AIPS_PACRM_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1711 #define AIPS_PACRM_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1712 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1713 #define AIPS_PACRM_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1714 #define AIPS_PACRM_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1715 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1716 #define AIPS_PACRM_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1717 #define AIPS_PACRM_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1718 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1719 #define AIPS_PACRM_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1720 #define AIPS_PACRM_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1721 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1722 #define AIPS_PACRM_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1723 #define AIPS_PACRM_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1724 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1725 #define AIPS_PACRM_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1726 #define AIPS_PACRM_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1727 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1728 #define AIPS_PACRM_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1729 #define AIPS_PACRM_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1730 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1731 #define AIPS_PACRM_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1732 #define AIPS_PACRM_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1733 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1734 #define AIPS_PACRM_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1735 #define AIPS_PACRM_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1736 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1737 #define AIPS_PACRM_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1738 #define AIPS_PACRM_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1739 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1740 #define AIPS_PACRM_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1741 #define AIPS_PACRM_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1742 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1743 #define AIPS_PACRM_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1744 #define AIPS_PACRM_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1745 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1746 #define AIPS_PACRM_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1747 #define AIPS_PACRM_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1748 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1749 #define AIPS_PACRM_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1750 #define AIPS_PACRM_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1751 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1752
AnnaBridge 171:3a7713b1edbc 1753 /*! @name PACRN - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1754 #define AIPS_PACRN_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1755 #define AIPS_PACRN_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1756 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1757 #define AIPS_PACRN_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1758 #define AIPS_PACRN_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1759 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1760 #define AIPS_PACRN_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1761 #define AIPS_PACRN_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1762 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1763 #define AIPS_PACRN_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1764 #define AIPS_PACRN_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1765 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1766 #define AIPS_PACRN_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1767 #define AIPS_PACRN_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1768 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1769 #define AIPS_PACRN_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1770 #define AIPS_PACRN_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1771 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1772 #define AIPS_PACRN_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1773 #define AIPS_PACRN_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1774 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1775 #define AIPS_PACRN_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1776 #define AIPS_PACRN_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1777 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1778 #define AIPS_PACRN_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1779 #define AIPS_PACRN_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1780 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1781 #define AIPS_PACRN_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1782 #define AIPS_PACRN_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1783 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1784 #define AIPS_PACRN_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1785 #define AIPS_PACRN_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1786 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1787 #define AIPS_PACRN_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1788 #define AIPS_PACRN_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1789 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1790 #define AIPS_PACRN_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1791 #define AIPS_PACRN_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1792 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1793 #define AIPS_PACRN_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1794 #define AIPS_PACRN_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1795 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1796 #define AIPS_PACRN_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1797 #define AIPS_PACRN_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1798 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1799 #define AIPS_PACRN_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1800 #define AIPS_PACRN_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1801 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1802 #define AIPS_PACRN_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1803 #define AIPS_PACRN_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1804 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1805 #define AIPS_PACRN_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1806 #define AIPS_PACRN_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1807 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1808 #define AIPS_PACRN_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1809 #define AIPS_PACRN_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1810 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1811 #define AIPS_PACRN_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1812 #define AIPS_PACRN_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1813 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1814 #define AIPS_PACRN_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1815 #define AIPS_PACRN_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1816 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1817 #define AIPS_PACRN_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1818 #define AIPS_PACRN_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1819 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1820 #define AIPS_PACRN_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1821 #define AIPS_PACRN_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1822 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1823 #define AIPS_PACRN_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1824 #define AIPS_PACRN_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1825 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1826
AnnaBridge 171:3a7713b1edbc 1827 /*! @name PACRO - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1828 #define AIPS_PACRO_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1829 #define AIPS_PACRO_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1830 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1831 #define AIPS_PACRO_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1832 #define AIPS_PACRO_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1833 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1834 #define AIPS_PACRO_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1835 #define AIPS_PACRO_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1836 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1837 #define AIPS_PACRO_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1838 #define AIPS_PACRO_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1839 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1840 #define AIPS_PACRO_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1841 #define AIPS_PACRO_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1842 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1843 #define AIPS_PACRO_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1844 #define AIPS_PACRO_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1845 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1846 #define AIPS_PACRO_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1847 #define AIPS_PACRO_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1848 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1849 #define AIPS_PACRO_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1850 #define AIPS_PACRO_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1851 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1852 #define AIPS_PACRO_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1853 #define AIPS_PACRO_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1854 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1855 #define AIPS_PACRO_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1856 #define AIPS_PACRO_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1857 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1858 #define AIPS_PACRO_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1859 #define AIPS_PACRO_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1860 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1861 #define AIPS_PACRO_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1862 #define AIPS_PACRO_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1863 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1864 #define AIPS_PACRO_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1865 #define AIPS_PACRO_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1866 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1867 #define AIPS_PACRO_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1868 #define AIPS_PACRO_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1869 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1870 #define AIPS_PACRO_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1871 #define AIPS_PACRO_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1872 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1873 #define AIPS_PACRO_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1874 #define AIPS_PACRO_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1875 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1876 #define AIPS_PACRO_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1877 #define AIPS_PACRO_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1878 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1879 #define AIPS_PACRO_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1880 #define AIPS_PACRO_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1881 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1882 #define AIPS_PACRO_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1883 #define AIPS_PACRO_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1884 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1885 #define AIPS_PACRO_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1886 #define AIPS_PACRO_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1887 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1888 #define AIPS_PACRO_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1889 #define AIPS_PACRO_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1890 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1891 #define AIPS_PACRO_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1892 #define AIPS_PACRO_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1893 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1894 #define AIPS_PACRO_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1895 #define AIPS_PACRO_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1896 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1897 #define AIPS_PACRO_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1898 #define AIPS_PACRO_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1899 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1900
AnnaBridge 171:3a7713b1edbc 1901 /*! @name PACRP - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1902 #define AIPS_PACRP_TP7_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 1903 #define AIPS_PACRP_TP7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 1904 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
AnnaBridge 171:3a7713b1edbc 1905 #define AIPS_PACRP_WP7_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 1906 #define AIPS_PACRP_WP7_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 1907 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
AnnaBridge 171:3a7713b1edbc 1908 #define AIPS_PACRP_SP7_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 1909 #define AIPS_PACRP_SP7_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 1910 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
AnnaBridge 171:3a7713b1edbc 1911 #define AIPS_PACRP_TP6_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 1912 #define AIPS_PACRP_TP6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 1913 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
AnnaBridge 171:3a7713b1edbc 1914 #define AIPS_PACRP_WP6_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 1915 #define AIPS_PACRP_WP6_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 1916 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
AnnaBridge 171:3a7713b1edbc 1917 #define AIPS_PACRP_SP6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 1918 #define AIPS_PACRP_SP6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 1919 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
AnnaBridge 171:3a7713b1edbc 1920 #define AIPS_PACRP_TP5_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 1921 #define AIPS_PACRP_TP5_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 1922 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
AnnaBridge 171:3a7713b1edbc 1923 #define AIPS_PACRP_WP5_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 1924 #define AIPS_PACRP_WP5_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 1925 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
AnnaBridge 171:3a7713b1edbc 1926 #define AIPS_PACRP_SP5_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 1927 #define AIPS_PACRP_SP5_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 1928 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
AnnaBridge 171:3a7713b1edbc 1929 #define AIPS_PACRP_TP4_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 1930 #define AIPS_PACRP_TP4_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 1931 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
AnnaBridge 171:3a7713b1edbc 1932 #define AIPS_PACRP_WP4_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 1933 #define AIPS_PACRP_WP4_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 1934 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
AnnaBridge 171:3a7713b1edbc 1935 #define AIPS_PACRP_SP4_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 1936 #define AIPS_PACRP_SP4_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 1937 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
AnnaBridge 171:3a7713b1edbc 1938 #define AIPS_PACRP_TP3_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 1939 #define AIPS_PACRP_TP3_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 1940 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
AnnaBridge 171:3a7713b1edbc 1941 #define AIPS_PACRP_WP3_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 1942 #define AIPS_PACRP_WP3_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 1943 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
AnnaBridge 171:3a7713b1edbc 1944 #define AIPS_PACRP_SP3_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 1945 #define AIPS_PACRP_SP3_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 1946 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
AnnaBridge 171:3a7713b1edbc 1947 #define AIPS_PACRP_TP2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 1948 #define AIPS_PACRP_TP2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 1949 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
AnnaBridge 171:3a7713b1edbc 1950 #define AIPS_PACRP_WP2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 1951 #define AIPS_PACRP_WP2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 1952 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
AnnaBridge 171:3a7713b1edbc 1953 #define AIPS_PACRP_SP2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 1954 #define AIPS_PACRP_SP2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 1955 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
AnnaBridge 171:3a7713b1edbc 1956 #define AIPS_PACRP_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1957 #define AIPS_PACRP_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1958 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1959 #define AIPS_PACRP_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1960 #define AIPS_PACRP_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1961 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1962 #define AIPS_PACRP_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1963 #define AIPS_PACRP_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1964 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1965 #define AIPS_PACRP_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1966 #define AIPS_PACRP_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1967 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1968 #define AIPS_PACRP_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1969 #define AIPS_PACRP_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1970 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1971 #define AIPS_PACRP_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1972 #define AIPS_PACRP_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1973 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1974
AnnaBridge 171:3a7713b1edbc 1975 /*! @name PACRU - Peripheral Access Control Register */
AnnaBridge 171:3a7713b1edbc 1976 #define AIPS_PACRU_TP1_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 1977 #define AIPS_PACRU_TP1_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 1978 #define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK)
AnnaBridge 171:3a7713b1edbc 1979 #define AIPS_PACRU_WP1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 1980 #define AIPS_PACRU_WP1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 1981 #define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK)
AnnaBridge 171:3a7713b1edbc 1982 #define AIPS_PACRU_SP1_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 1983 #define AIPS_PACRU_SP1_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 1984 #define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK)
AnnaBridge 171:3a7713b1edbc 1985 #define AIPS_PACRU_TP0_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 1986 #define AIPS_PACRU_TP0_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 1987 #define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK)
AnnaBridge 171:3a7713b1edbc 1988 #define AIPS_PACRU_WP0_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 1989 #define AIPS_PACRU_WP0_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 1990 #define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK)
AnnaBridge 171:3a7713b1edbc 1991 #define AIPS_PACRU_SP0_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 1992 #define AIPS_PACRU_SP0_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 1993 #define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK)
AnnaBridge 171:3a7713b1edbc 1994
AnnaBridge 171:3a7713b1edbc 1995
AnnaBridge 171:3a7713b1edbc 1996 /*!
AnnaBridge 171:3a7713b1edbc 1997 * @}
AnnaBridge 171:3a7713b1edbc 1998 */ /* end of group AIPS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 1999
AnnaBridge 171:3a7713b1edbc 2000
AnnaBridge 171:3a7713b1edbc 2001 /* AIPS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2002 /** Peripheral AIPS0 base address */
AnnaBridge 171:3a7713b1edbc 2003 #define AIPS0_BASE (0x40000000u)
AnnaBridge 171:3a7713b1edbc 2004 /** Peripheral AIPS0 base pointer */
AnnaBridge 171:3a7713b1edbc 2005 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
AnnaBridge 171:3a7713b1edbc 2006 /** Peripheral AIPS1 base address */
AnnaBridge 171:3a7713b1edbc 2007 #define AIPS1_BASE (0x40080000u)
AnnaBridge 171:3a7713b1edbc 2008 /** Peripheral AIPS1 base pointer */
AnnaBridge 171:3a7713b1edbc 2009 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
AnnaBridge 171:3a7713b1edbc 2010 /** Array initializer of AIPS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2011 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
AnnaBridge 171:3a7713b1edbc 2012 /** Array initializer of AIPS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2013 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
AnnaBridge 171:3a7713b1edbc 2014
AnnaBridge 171:3a7713b1edbc 2015 /*!
AnnaBridge 171:3a7713b1edbc 2016 * @}
AnnaBridge 171:3a7713b1edbc 2017 */ /* end of group AIPS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2018
AnnaBridge 171:3a7713b1edbc 2019
AnnaBridge 171:3a7713b1edbc 2020 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2021 -- AXBS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2022 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2023
AnnaBridge 171:3a7713b1edbc 2024 /*!
AnnaBridge 171:3a7713b1edbc 2025 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2026 * @{
AnnaBridge 171:3a7713b1edbc 2027 */
AnnaBridge 171:3a7713b1edbc 2028
AnnaBridge 171:3a7713b1edbc 2029 /** AXBS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2030 typedef struct {
AnnaBridge 171:3a7713b1edbc 2031 struct { /* offset: 0x0, array step: 0x100 */
AnnaBridge 171:3a7713b1edbc 2032 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
AnnaBridge 171:3a7713b1edbc 2033 uint8_t RESERVED_0[12];
AnnaBridge 171:3a7713b1edbc 2034 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
AnnaBridge 171:3a7713b1edbc 2035 uint8_t RESERVED_1[236];
AnnaBridge 171:3a7713b1edbc 2036 } SLAVE[5];
AnnaBridge 171:3a7713b1edbc 2037 uint8_t RESERVED_0[768];
AnnaBridge 171:3a7713b1edbc 2038 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
AnnaBridge 171:3a7713b1edbc 2039 uint8_t RESERVED_1[252];
AnnaBridge 171:3a7713b1edbc 2040 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
AnnaBridge 171:3a7713b1edbc 2041 uint8_t RESERVED_2[252];
AnnaBridge 171:3a7713b1edbc 2042 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
AnnaBridge 171:3a7713b1edbc 2043 uint8_t RESERVED_3[252];
AnnaBridge 171:3a7713b1edbc 2044 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */
AnnaBridge 171:3a7713b1edbc 2045 uint8_t RESERVED_4[252];
AnnaBridge 171:3a7713b1edbc 2046 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
AnnaBridge 171:3a7713b1edbc 2047 uint8_t RESERVED_5[252];
AnnaBridge 171:3a7713b1edbc 2048 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
AnnaBridge 171:3a7713b1edbc 2049 } AXBS_Type;
AnnaBridge 171:3a7713b1edbc 2050
AnnaBridge 171:3a7713b1edbc 2051 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2052 -- AXBS Register Masks
AnnaBridge 171:3a7713b1edbc 2053 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2054
AnnaBridge 171:3a7713b1edbc 2055 /*!
AnnaBridge 171:3a7713b1edbc 2056 * @addtogroup AXBS_Register_Masks AXBS Register Masks
AnnaBridge 171:3a7713b1edbc 2057 * @{
AnnaBridge 171:3a7713b1edbc 2058 */
AnnaBridge 171:3a7713b1edbc 2059
AnnaBridge 171:3a7713b1edbc 2060 /*! @name PRS - Priority Registers Slave */
AnnaBridge 171:3a7713b1edbc 2061 #define AXBS_PRS_M0_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2062 #define AXBS_PRS_M0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2063 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
AnnaBridge 171:3a7713b1edbc 2064 #define AXBS_PRS_M1_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 2065 #define AXBS_PRS_M1_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2066 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
AnnaBridge 171:3a7713b1edbc 2067 #define AXBS_PRS_M2_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 2068 #define AXBS_PRS_M2_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2069 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
AnnaBridge 171:3a7713b1edbc 2070 #define AXBS_PRS_M3_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 2071 #define AXBS_PRS_M3_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2072 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
AnnaBridge 171:3a7713b1edbc 2073 #define AXBS_PRS_M4_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 2074 #define AXBS_PRS_M4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2075 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
AnnaBridge 171:3a7713b1edbc 2076 #define AXBS_PRS_M5_MASK (0x700000U)
AnnaBridge 171:3a7713b1edbc 2077 #define AXBS_PRS_M5_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2078 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
AnnaBridge 171:3a7713b1edbc 2079
AnnaBridge 171:3a7713b1edbc 2080 /* The count of AXBS_PRS */
AnnaBridge 171:3a7713b1edbc 2081 #define AXBS_PRS_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 2082
AnnaBridge 171:3a7713b1edbc 2083 /*! @name CRS - Control Register */
AnnaBridge 171:3a7713b1edbc 2084 #define AXBS_CRS_PARK_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2085 #define AXBS_CRS_PARK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2086 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
AnnaBridge 171:3a7713b1edbc 2087 #define AXBS_CRS_PCTL_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2088 #define AXBS_CRS_PCTL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2089 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
AnnaBridge 171:3a7713b1edbc 2090 #define AXBS_CRS_ARB_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2091 #define AXBS_CRS_ARB_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2092 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
AnnaBridge 171:3a7713b1edbc 2093 #define AXBS_CRS_HLP_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2094 #define AXBS_CRS_HLP_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2095 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
AnnaBridge 171:3a7713b1edbc 2096 #define AXBS_CRS_RO_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2097 #define AXBS_CRS_RO_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2098 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
AnnaBridge 171:3a7713b1edbc 2099
AnnaBridge 171:3a7713b1edbc 2100 /* The count of AXBS_CRS */
AnnaBridge 171:3a7713b1edbc 2101 #define AXBS_CRS_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 2102
AnnaBridge 171:3a7713b1edbc 2103 /*! @name MGPCR0 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2104 #define AXBS_MGPCR0_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2105 #define AXBS_MGPCR0_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2106 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2107
AnnaBridge 171:3a7713b1edbc 2108 /*! @name MGPCR1 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2109 #define AXBS_MGPCR1_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2110 #define AXBS_MGPCR1_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2111 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2112
AnnaBridge 171:3a7713b1edbc 2113 /*! @name MGPCR2 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2114 #define AXBS_MGPCR2_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2115 #define AXBS_MGPCR2_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2116 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2117
AnnaBridge 171:3a7713b1edbc 2118 /*! @name MGPCR3 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2119 #define AXBS_MGPCR3_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2120 #define AXBS_MGPCR3_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2121 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2122
AnnaBridge 171:3a7713b1edbc 2123 /*! @name MGPCR4 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2124 #define AXBS_MGPCR4_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2125 #define AXBS_MGPCR4_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2126 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2127
AnnaBridge 171:3a7713b1edbc 2128 /*! @name MGPCR5 - Master General Purpose Control Register */
AnnaBridge 171:3a7713b1edbc 2129 #define AXBS_MGPCR5_AULB_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2130 #define AXBS_MGPCR5_AULB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2131 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
AnnaBridge 171:3a7713b1edbc 2132
AnnaBridge 171:3a7713b1edbc 2133
AnnaBridge 171:3a7713b1edbc 2134 /*!
AnnaBridge 171:3a7713b1edbc 2135 * @}
AnnaBridge 171:3a7713b1edbc 2136 */ /* end of group AXBS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2137
AnnaBridge 171:3a7713b1edbc 2138
AnnaBridge 171:3a7713b1edbc 2139 /* AXBS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2140 /** Peripheral AXBS base address */
AnnaBridge 171:3a7713b1edbc 2141 #define AXBS_BASE (0x40004000u)
AnnaBridge 171:3a7713b1edbc 2142 /** Peripheral AXBS base pointer */
AnnaBridge 171:3a7713b1edbc 2143 #define AXBS ((AXBS_Type *)AXBS_BASE)
AnnaBridge 171:3a7713b1edbc 2144 /** Array initializer of AXBS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2145 #define AXBS_BASE_ADDRS { AXBS_BASE }
AnnaBridge 171:3a7713b1edbc 2146 /** Array initializer of AXBS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2147 #define AXBS_BASE_PTRS { AXBS }
AnnaBridge 171:3a7713b1edbc 2148
AnnaBridge 171:3a7713b1edbc 2149 /*!
AnnaBridge 171:3a7713b1edbc 2150 * @}
AnnaBridge 171:3a7713b1edbc 2151 */ /* end of group AXBS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2152
AnnaBridge 171:3a7713b1edbc 2153
AnnaBridge 171:3a7713b1edbc 2154 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2155 -- CAN Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2156 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2157
AnnaBridge 171:3a7713b1edbc 2158 /*!
AnnaBridge 171:3a7713b1edbc 2159 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2160 * @{
AnnaBridge 171:3a7713b1edbc 2161 */
AnnaBridge 171:3a7713b1edbc 2162
AnnaBridge 171:3a7713b1edbc 2163 /** CAN - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2164 typedef struct {
AnnaBridge 171:3a7713b1edbc 2165 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 2166 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 2167 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 2168 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 2169 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 2170 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 2171 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 2172 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 2173 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 2174 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 2175 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 2176 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 2177 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 2178 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 2179 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 2180 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 2181 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 2182 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 2183 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 2184 uint8_t RESERVED_4[48];
AnnaBridge 171:3a7713b1edbc 2185 struct { /* offset: 0x80, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2186 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2187 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2188 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2189 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 2190 } MB[16];
AnnaBridge 171:3a7713b1edbc 2191 uint8_t RESERVED_5[1792];
AnnaBridge 171:3a7713b1edbc 2192 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2193 } CAN_Type;
AnnaBridge 171:3a7713b1edbc 2194
AnnaBridge 171:3a7713b1edbc 2195 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2196 -- CAN Register Masks
AnnaBridge 171:3a7713b1edbc 2197 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2198
AnnaBridge 171:3a7713b1edbc 2199 /*!
AnnaBridge 171:3a7713b1edbc 2200 * @addtogroup CAN_Register_Masks CAN Register Masks
AnnaBridge 171:3a7713b1edbc 2201 * @{
AnnaBridge 171:3a7713b1edbc 2202 */
AnnaBridge 171:3a7713b1edbc 2203
AnnaBridge 171:3a7713b1edbc 2204 /*! @name MCR - Module Configuration Register */
AnnaBridge 171:3a7713b1edbc 2205 #define CAN_MCR_MAXMB_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 2206 #define CAN_MCR_MAXMB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2207 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
AnnaBridge 171:3a7713b1edbc 2208 #define CAN_MCR_IDAM_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 2209 #define CAN_MCR_IDAM_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2210 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
AnnaBridge 171:3a7713b1edbc 2211 #define CAN_MCR_AEN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2212 #define CAN_MCR_AEN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2213 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
AnnaBridge 171:3a7713b1edbc 2214 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2215 #define CAN_MCR_LPRIOEN_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2216 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
AnnaBridge 171:3a7713b1edbc 2217 #define CAN_MCR_IRMQ_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2218 #define CAN_MCR_IRMQ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2219 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
AnnaBridge 171:3a7713b1edbc 2220 #define CAN_MCR_SRXDIS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2221 #define CAN_MCR_SRXDIS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2222 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
AnnaBridge 171:3a7713b1edbc 2223 #define CAN_MCR_WAKSRC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 2224 #define CAN_MCR_WAKSRC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2225 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2226 #define CAN_MCR_LPMACK_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2227 #define CAN_MCR_LPMACK_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2228 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
AnnaBridge 171:3a7713b1edbc 2229 #define CAN_MCR_WRNEN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2230 #define CAN_MCR_WRNEN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2231 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
AnnaBridge 171:3a7713b1edbc 2232 #define CAN_MCR_SLFWAK_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2233 #define CAN_MCR_SLFWAK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2234 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
AnnaBridge 171:3a7713b1edbc 2235 #define CAN_MCR_SUPV_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 2236 #define CAN_MCR_SUPV_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 2237 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
AnnaBridge 171:3a7713b1edbc 2238 #define CAN_MCR_FRZACK_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 2239 #define CAN_MCR_FRZACK_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2240 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
AnnaBridge 171:3a7713b1edbc 2241 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 2242 #define CAN_MCR_SOFTRST_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 2243 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
AnnaBridge 171:3a7713b1edbc 2244 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 2245 #define CAN_MCR_WAKMSK_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 2246 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2247 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 2248 #define CAN_MCR_NOTRDY_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 2249 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
AnnaBridge 171:3a7713b1edbc 2250 #define CAN_MCR_HALT_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2251 #define CAN_MCR_HALT_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2252 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 2253 #define CAN_MCR_RFEN_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 2254 #define CAN_MCR_RFEN_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2255 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
AnnaBridge 171:3a7713b1edbc 2256 #define CAN_MCR_FRZ_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 2257 #define CAN_MCR_FRZ_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 2258 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 2259 #define CAN_MCR_MDIS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 2260 #define CAN_MCR_MDIS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 2261 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 2262
AnnaBridge 171:3a7713b1edbc 2263 /*! @name CTRL1 - Control 1 register */
AnnaBridge 171:3a7713b1edbc 2264 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 2265 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2266 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
AnnaBridge 171:3a7713b1edbc 2267 #define CAN_CTRL1_LOM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2268 #define CAN_CTRL1_LOM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2269 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
AnnaBridge 171:3a7713b1edbc 2270 #define CAN_CTRL1_LBUF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 2271 #define CAN_CTRL1_LBUF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2272 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
AnnaBridge 171:3a7713b1edbc 2273 #define CAN_CTRL1_TSYN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2274 #define CAN_CTRL1_TSYN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2275 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
AnnaBridge 171:3a7713b1edbc 2276 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2277 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2278 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
AnnaBridge 171:3a7713b1edbc 2279 #define CAN_CTRL1_SMP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2280 #define CAN_CTRL1_SMP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2281 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
AnnaBridge 171:3a7713b1edbc 2282 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2283 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2284 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2285 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2286 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2287 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2288 #define CAN_CTRL1_LPB_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2289 #define CAN_CTRL1_LPB_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2290 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
AnnaBridge 171:3a7713b1edbc 2291 #define CAN_CTRL1_CLKSRC_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2292 #define CAN_CTRL1_CLKSRC_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2293 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 2294 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2295 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2296 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2297 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2298 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2299 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
AnnaBridge 171:3a7713b1edbc 2300 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 2301 #define CAN_CTRL1_PSEG2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2302 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
AnnaBridge 171:3a7713b1edbc 2303 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
AnnaBridge 171:3a7713b1edbc 2304 #define CAN_CTRL1_PSEG1_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2305 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
AnnaBridge 171:3a7713b1edbc 2306 #define CAN_CTRL1_RJW_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 2307 #define CAN_CTRL1_RJW_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2308 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
AnnaBridge 171:3a7713b1edbc 2309 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2310 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2311 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
AnnaBridge 171:3a7713b1edbc 2312
AnnaBridge 171:3a7713b1edbc 2313 /*! @name TIMER - Free Running Timer */
AnnaBridge 171:3a7713b1edbc 2314 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2315 #define CAN_TIMER_TIMER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2316 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 2317
AnnaBridge 171:3a7713b1edbc 2318 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
AnnaBridge 171:3a7713b1edbc 2319 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2320 #define CAN_RXMGMASK_MG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2321 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
AnnaBridge 171:3a7713b1edbc 2322
AnnaBridge 171:3a7713b1edbc 2323 /*! @name RX14MASK - Rx 14 Mask register */
AnnaBridge 171:3a7713b1edbc 2324 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2325 #define CAN_RX14MASK_RX14M_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2326 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
AnnaBridge 171:3a7713b1edbc 2327
AnnaBridge 171:3a7713b1edbc 2328 /*! @name RX15MASK - Rx 15 Mask register */
AnnaBridge 171:3a7713b1edbc 2329 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2330 #define CAN_RX15MASK_RX15M_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2331 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
AnnaBridge 171:3a7713b1edbc 2332
AnnaBridge 171:3a7713b1edbc 2333 /*! @name ECR - Error Counter */
AnnaBridge 171:3a7713b1edbc 2334 #define CAN_ECR_TXERRCNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2335 #define CAN_ECR_TXERRCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2336 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
AnnaBridge 171:3a7713b1edbc 2337 #define CAN_ECR_RXERRCNT_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2338 #define CAN_ECR_RXERRCNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2339 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
AnnaBridge 171:3a7713b1edbc 2340
AnnaBridge 171:3a7713b1edbc 2341 /*! @name ESR1 - Error and Status 1 register */
AnnaBridge 171:3a7713b1edbc 2342 #define CAN_ESR1_WAKINT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2343 #define CAN_ESR1_WAKINT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2344 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
AnnaBridge 171:3a7713b1edbc 2345 #define CAN_ESR1_ERRINT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2346 #define CAN_ESR1_ERRINT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2347 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
AnnaBridge 171:3a7713b1edbc 2348 #define CAN_ESR1_BOFFINT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 2349 #define CAN_ESR1_BOFFINT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 2350 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
AnnaBridge 171:3a7713b1edbc 2351 #define CAN_ESR1_RX_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 2352 #define CAN_ESR1_RX_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 2353 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
AnnaBridge 171:3a7713b1edbc 2354 #define CAN_ESR1_FLTCONF_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 2355 #define CAN_ESR1_FLTCONF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 2356 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
AnnaBridge 171:3a7713b1edbc 2357 #define CAN_ESR1_TX_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2358 #define CAN_ESR1_TX_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2359 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 2360 #define CAN_ESR1_IDLE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2361 #define CAN_ESR1_IDLE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2362 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 2363 #define CAN_ESR1_RXWRN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 2364 #define CAN_ESR1_RXWRN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2365 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
AnnaBridge 171:3a7713b1edbc 2366 #define CAN_ESR1_TXWRN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 2367 #define CAN_ESR1_TXWRN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 2368 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
AnnaBridge 171:3a7713b1edbc 2369 #define CAN_ESR1_STFERR_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 2370 #define CAN_ESR1_STFERR_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 2371 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
AnnaBridge 171:3a7713b1edbc 2372 #define CAN_ESR1_FRMERR_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 2373 #define CAN_ESR1_FRMERR_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 2374 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
AnnaBridge 171:3a7713b1edbc 2375 #define CAN_ESR1_CRCERR_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 2376 #define CAN_ESR1_CRCERR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 2377 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
AnnaBridge 171:3a7713b1edbc 2378 #define CAN_ESR1_ACKERR_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2379 #define CAN_ESR1_ACKERR_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2380 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 2381 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2382 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2383 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
AnnaBridge 171:3a7713b1edbc 2384 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 2385 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 2386 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
AnnaBridge 171:3a7713b1edbc 2387 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2388 #define CAN_ESR1_RWRNINT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2389 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
AnnaBridge 171:3a7713b1edbc 2390 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2391 #define CAN_ESR1_TWRNINT_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2392 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
AnnaBridge 171:3a7713b1edbc 2393 #define CAN_ESR1_SYNCH_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2394 #define CAN_ESR1_SYNCH_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2395 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
AnnaBridge 171:3a7713b1edbc 2396
AnnaBridge 171:3a7713b1edbc 2397 /*! @name IMASK1 - Interrupt Masks 1 register */
AnnaBridge 171:3a7713b1edbc 2398 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2399 #define CAN_IMASK1_BUFLM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2400 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
AnnaBridge 171:3a7713b1edbc 2401
AnnaBridge 171:3a7713b1edbc 2402 /*! @name IFLAG1 - Interrupt Flags 1 register */
AnnaBridge 171:3a7713b1edbc 2403 #define CAN_IFLAG1_BUF0I_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2404 #define CAN_IFLAG1_BUF0I_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2405 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
AnnaBridge 171:3a7713b1edbc 2406 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
AnnaBridge 171:3a7713b1edbc 2407 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2408 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
AnnaBridge 171:3a7713b1edbc 2409 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 2410 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 2411 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
AnnaBridge 171:3a7713b1edbc 2412 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 2413 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 2414 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
AnnaBridge 171:3a7713b1edbc 2415 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 2416 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 2417 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
AnnaBridge 171:3a7713b1edbc 2418 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
AnnaBridge 171:3a7713b1edbc 2419 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2420 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
AnnaBridge 171:3a7713b1edbc 2421
AnnaBridge 171:3a7713b1edbc 2422 /*! @name CTRL2 - Control 2 register */
AnnaBridge 171:3a7713b1edbc 2423 #define CAN_CTRL2_EACEN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 2424 #define CAN_CTRL2_EACEN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2425 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
AnnaBridge 171:3a7713b1edbc 2426 #define CAN_CTRL2_RRS_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 2427 #define CAN_CTRL2_RRS_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 2428 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
AnnaBridge 171:3a7713b1edbc 2429 #define CAN_CTRL2_MRP_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 2430 #define CAN_CTRL2_MRP_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2431 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
AnnaBridge 171:3a7713b1edbc 2432 #define CAN_CTRL2_TASD_MASK (0xF80000U)
AnnaBridge 171:3a7713b1edbc 2433 #define CAN_CTRL2_TASD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 2434 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
AnnaBridge 171:3a7713b1edbc 2435 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 2436 #define CAN_CTRL2_RFFN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2437 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
AnnaBridge 171:3a7713b1edbc 2438 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 2439 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2440 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
AnnaBridge 171:3a7713b1edbc 2441
AnnaBridge 171:3a7713b1edbc 2442 /*! @name ESR2 - Error and Status 2 register */
AnnaBridge 171:3a7713b1edbc 2443 #define CAN_ESR2_IMB_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 2444 #define CAN_ESR2_IMB_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 2445 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
AnnaBridge 171:3a7713b1edbc 2446 #define CAN_ESR2_VPS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 2447 #define CAN_ESR2_VPS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 2448 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
AnnaBridge 171:3a7713b1edbc 2449 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 2450 #define CAN_ESR2_LPTM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2451 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
AnnaBridge 171:3a7713b1edbc 2452
AnnaBridge 171:3a7713b1edbc 2453 /*! @name CRCR - CRC Register */
AnnaBridge 171:3a7713b1edbc 2454 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 2455 #define CAN_CRCR_TXCRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2456 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
AnnaBridge 171:3a7713b1edbc 2457 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 2458 #define CAN_CRCR_MBCRC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2459 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
AnnaBridge 171:3a7713b1edbc 2460
AnnaBridge 171:3a7713b1edbc 2461 /*! @name RXFGMASK - Rx FIFO Global Mask register */
AnnaBridge 171:3a7713b1edbc 2462 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2463 #define CAN_RXFGMASK_FGM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2464 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
AnnaBridge 171:3a7713b1edbc 2465
AnnaBridge 171:3a7713b1edbc 2466 /*! @name RXFIR - Rx FIFO Information Register */
AnnaBridge 171:3a7713b1edbc 2467 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 2468 #define CAN_RXFIR_IDHIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2469 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
AnnaBridge 171:3a7713b1edbc 2470
AnnaBridge 171:3a7713b1edbc 2471 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
AnnaBridge 171:3a7713b1edbc 2472 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 2473 #define CAN_CS_TIME_STAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2474 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
AnnaBridge 171:3a7713b1edbc 2475 #define CAN_CS_DLC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 2476 #define CAN_CS_DLC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2477 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
AnnaBridge 171:3a7713b1edbc 2478 #define CAN_CS_RTR_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 2479 #define CAN_CS_RTR_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 2480 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
AnnaBridge 171:3a7713b1edbc 2481 #define CAN_CS_IDE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 2482 #define CAN_CS_IDE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 2483 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
AnnaBridge 171:3a7713b1edbc 2484 #define CAN_CS_SRR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 2485 #define CAN_CS_SRR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 2486 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
AnnaBridge 171:3a7713b1edbc 2487 #define CAN_CS_CODE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 2488 #define CAN_CS_CODE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2489 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
AnnaBridge 171:3a7713b1edbc 2490
AnnaBridge 171:3a7713b1edbc 2491 /* The count of CAN_CS */
AnnaBridge 171:3a7713b1edbc 2492 #define CAN_CS_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2493
AnnaBridge 171:3a7713b1edbc 2494 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
AnnaBridge 171:3a7713b1edbc 2495 #define CAN_ID_EXT_MASK (0x3FFFFU)
AnnaBridge 171:3a7713b1edbc 2496 #define CAN_ID_EXT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2497 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
AnnaBridge 171:3a7713b1edbc 2498 #define CAN_ID_STD_MASK (0x1FFC0000U)
AnnaBridge 171:3a7713b1edbc 2499 #define CAN_ID_STD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 2500 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
AnnaBridge 171:3a7713b1edbc 2501 #define CAN_ID_PRIO_MASK (0xE0000000U)
AnnaBridge 171:3a7713b1edbc 2502 #define CAN_ID_PRIO_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 2503 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
AnnaBridge 171:3a7713b1edbc 2504
AnnaBridge 171:3a7713b1edbc 2505 /* The count of CAN_ID */
AnnaBridge 171:3a7713b1edbc 2506 #define CAN_ID_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2507
AnnaBridge 171:3a7713b1edbc 2508 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
AnnaBridge 171:3a7713b1edbc 2509 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2510 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2511 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
AnnaBridge 171:3a7713b1edbc 2512 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2513 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2514 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
AnnaBridge 171:3a7713b1edbc 2515 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 2516 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2517 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
AnnaBridge 171:3a7713b1edbc 2518 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2519 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2520 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
AnnaBridge 171:3a7713b1edbc 2521
AnnaBridge 171:3a7713b1edbc 2522 /* The count of CAN_WORD0 */
AnnaBridge 171:3a7713b1edbc 2523 #define CAN_WORD0_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2524
AnnaBridge 171:3a7713b1edbc 2525 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
AnnaBridge 171:3a7713b1edbc 2526 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 2527 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2528 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
AnnaBridge 171:3a7713b1edbc 2529 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 2530 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 2531 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
AnnaBridge 171:3a7713b1edbc 2532 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 2533 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 2534 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
AnnaBridge 171:3a7713b1edbc 2535 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 2536 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 2537 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
AnnaBridge 171:3a7713b1edbc 2538
AnnaBridge 171:3a7713b1edbc 2539 /* The count of CAN_WORD1 */
AnnaBridge 171:3a7713b1edbc 2540 #define CAN_WORD1_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2541
AnnaBridge 171:3a7713b1edbc 2542 /*! @name RXIMR - Rx Individual Mask Registers */
AnnaBridge 171:3a7713b1edbc 2543 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2544 #define CAN_RXIMR_MI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2545 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
AnnaBridge 171:3a7713b1edbc 2546
AnnaBridge 171:3a7713b1edbc 2547 /* The count of CAN_RXIMR */
AnnaBridge 171:3a7713b1edbc 2548 #define CAN_RXIMR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2549
AnnaBridge 171:3a7713b1edbc 2550
AnnaBridge 171:3a7713b1edbc 2551 /*!
AnnaBridge 171:3a7713b1edbc 2552 * @}
AnnaBridge 171:3a7713b1edbc 2553 */ /* end of group CAN_Register_Masks */
AnnaBridge 171:3a7713b1edbc 2554
AnnaBridge 171:3a7713b1edbc 2555
AnnaBridge 171:3a7713b1edbc 2556 /* CAN - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 2557 /** Peripheral CAN0 base address */
AnnaBridge 171:3a7713b1edbc 2558 #define CAN0_BASE (0x40024000u)
AnnaBridge 171:3a7713b1edbc 2559 /** Peripheral CAN0 base pointer */
AnnaBridge 171:3a7713b1edbc 2560 #define CAN0 ((CAN_Type *)CAN0_BASE)
AnnaBridge 171:3a7713b1edbc 2561 /** Array initializer of CAN peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 2562 #define CAN_BASE_ADDRS { CAN0_BASE }
AnnaBridge 171:3a7713b1edbc 2563 /** Array initializer of CAN peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 2564 #define CAN_BASE_PTRS { CAN0 }
AnnaBridge 171:3a7713b1edbc 2565 /** Interrupt vectors for the CAN peripheral type */
AnnaBridge 171:3a7713b1edbc 2566 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
AnnaBridge 171:3a7713b1edbc 2567 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
AnnaBridge 171:3a7713b1edbc 2568 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
AnnaBridge 171:3a7713b1edbc 2569 #define CAN_Error_IRQS { CAN0_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 2570 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
AnnaBridge 171:3a7713b1edbc 2571 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
AnnaBridge 171:3a7713b1edbc 2572
AnnaBridge 171:3a7713b1edbc 2573 /*!
AnnaBridge 171:3a7713b1edbc 2574 * @}
AnnaBridge 171:3a7713b1edbc 2575 */ /* end of group CAN_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 2576
AnnaBridge 171:3a7713b1edbc 2577
AnnaBridge 171:3a7713b1edbc 2578 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2579 -- CAU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2580 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2581
AnnaBridge 171:3a7713b1edbc 2582 /*!
AnnaBridge 171:3a7713b1edbc 2583 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 2584 * @{
AnnaBridge 171:3a7713b1edbc 2585 */
AnnaBridge 171:3a7713b1edbc 2586
AnnaBridge 171:3a7713b1edbc 2587 /** CAU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 2588 typedef struct {
AnnaBridge 171:3a7713b1edbc 2589 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2590 uint8_t RESERVED_0[2048];
AnnaBridge 171:3a7713b1edbc 2591 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
AnnaBridge 171:3a7713b1edbc 2592 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
AnnaBridge 171:3a7713b1edbc 2593 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2594 uint8_t RESERVED_1[20];
AnnaBridge 171:3a7713b1edbc 2595 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
AnnaBridge 171:3a7713b1edbc 2596 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
AnnaBridge 171:3a7713b1edbc 2597 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2598 uint8_t RESERVED_2[20];
AnnaBridge 171:3a7713b1edbc 2599 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
AnnaBridge 171:3a7713b1edbc 2600 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
AnnaBridge 171:3a7713b1edbc 2601 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2602 uint8_t RESERVED_3[20];
AnnaBridge 171:3a7713b1edbc 2603 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
AnnaBridge 171:3a7713b1edbc 2604 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
AnnaBridge 171:3a7713b1edbc 2605 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2606 uint8_t RESERVED_4[84];
AnnaBridge 171:3a7713b1edbc 2607 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
AnnaBridge 171:3a7713b1edbc 2608 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
AnnaBridge 171:3a7713b1edbc 2609 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2610 uint8_t RESERVED_5[20];
AnnaBridge 171:3a7713b1edbc 2611 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
AnnaBridge 171:3a7713b1edbc 2612 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
AnnaBridge 171:3a7713b1edbc 2613 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2614 uint8_t RESERVED_6[276];
AnnaBridge 171:3a7713b1edbc 2615 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
AnnaBridge 171:3a7713b1edbc 2616 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
AnnaBridge 171:3a7713b1edbc 2617 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2618 uint8_t RESERVED_7[20];
AnnaBridge 171:3a7713b1edbc 2619 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
AnnaBridge 171:3a7713b1edbc 2620 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
AnnaBridge 171:3a7713b1edbc 2621 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 2622 } CAU_Type;
AnnaBridge 171:3a7713b1edbc 2623
AnnaBridge 171:3a7713b1edbc 2624 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 2625 -- CAU Register Masks
AnnaBridge 171:3a7713b1edbc 2626 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 2627
AnnaBridge 171:3a7713b1edbc 2628 /*!
AnnaBridge 171:3a7713b1edbc 2629 * @addtogroup CAU_Register_Masks CAU Register Masks
AnnaBridge 171:3a7713b1edbc 2630 * @{
AnnaBridge 171:3a7713b1edbc 2631 */
AnnaBridge 171:3a7713b1edbc 2632
AnnaBridge 171:3a7713b1edbc 2633 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
AnnaBridge 171:3a7713b1edbc 2634 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2635 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2636 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
AnnaBridge 171:3a7713b1edbc 2637 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2638 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2639 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
AnnaBridge 171:3a7713b1edbc 2640 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2641 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2642 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
AnnaBridge 171:3a7713b1edbc 2643 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2644 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2645 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
AnnaBridge 171:3a7713b1edbc 2646 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2647 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2648 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
AnnaBridge 171:3a7713b1edbc 2649 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2650 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2651 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
AnnaBridge 171:3a7713b1edbc 2652 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2653 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2654 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
AnnaBridge 171:3a7713b1edbc 2655 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2656 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2657 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
AnnaBridge 171:3a7713b1edbc 2658 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2659 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2660 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
AnnaBridge 171:3a7713b1edbc 2661 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2662 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2663 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
AnnaBridge 171:3a7713b1edbc 2664 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2665 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2666 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
AnnaBridge 171:3a7713b1edbc 2667 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2668 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2669 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
AnnaBridge 171:3a7713b1edbc 2670 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2671 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2672 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
AnnaBridge 171:3a7713b1edbc 2673 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2674 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2675 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
AnnaBridge 171:3a7713b1edbc 2676 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2677 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2678 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
AnnaBridge 171:3a7713b1edbc 2679 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2680 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2681 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
AnnaBridge 171:3a7713b1edbc 2682
AnnaBridge 171:3a7713b1edbc 2683 /* The count of CAU_DIRECT */
AnnaBridge 171:3a7713b1edbc 2684 #define CAU_DIRECT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 2685
AnnaBridge 171:3a7713b1edbc 2686 /*! @name LDR_CASR - Status register - Load Register command */
AnnaBridge 171:3a7713b1edbc 2687 #define CAU_LDR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2688 #define CAU_LDR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2689 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2690 #define CAU_LDR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2691 #define CAU_LDR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2692 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2693 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2694 #define CAU_LDR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2695 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2696
AnnaBridge 171:3a7713b1edbc 2697 /*! @name LDR_CAA - Accumulator register - Load Register command */
AnnaBridge 171:3a7713b1edbc 2698 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2699 #define CAU_LDR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2700 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2701
AnnaBridge 171:3a7713b1edbc 2702 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
AnnaBridge 171:3a7713b1edbc 2703 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2704 #define CAU_LDR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2705 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2706 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2707 #define CAU_LDR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2708 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2709 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2710 #define CAU_LDR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2711 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2712 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2713 #define CAU_LDR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2714 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2715 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2716 #define CAU_LDR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2717 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2718 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2719 #define CAU_LDR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2720 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2721 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2722 #define CAU_LDR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2723 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2724 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2725 #define CAU_LDR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2726 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2727 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2728 #define CAU_LDR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2729 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2730
AnnaBridge 171:3a7713b1edbc 2731 /* The count of CAU_LDR_CA */
AnnaBridge 171:3a7713b1edbc 2732 #define CAU_LDR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2733
AnnaBridge 171:3a7713b1edbc 2734 /*! @name STR_CASR - Status register - Store Register command */
AnnaBridge 171:3a7713b1edbc 2735 #define CAU_STR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2736 #define CAU_STR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2737 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2738 #define CAU_STR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2739 #define CAU_STR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2740 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2741 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2742 #define CAU_STR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2743 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2744
AnnaBridge 171:3a7713b1edbc 2745 /*! @name STR_CAA - Accumulator register - Store Register command */
AnnaBridge 171:3a7713b1edbc 2746 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2747 #define CAU_STR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2748 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2749
AnnaBridge 171:3a7713b1edbc 2750 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
AnnaBridge 171:3a7713b1edbc 2751 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2752 #define CAU_STR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2753 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2754 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2755 #define CAU_STR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2756 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2757 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2758 #define CAU_STR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2759 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2760 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2761 #define CAU_STR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2762 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2763 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2764 #define CAU_STR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2765 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2766 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2767 #define CAU_STR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2768 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2769 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2770 #define CAU_STR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2771 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2772 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2773 #define CAU_STR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2774 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2775 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2776 #define CAU_STR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2777 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2778
AnnaBridge 171:3a7713b1edbc 2779 /* The count of CAU_STR_CA */
AnnaBridge 171:3a7713b1edbc 2780 #define CAU_STR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2781
AnnaBridge 171:3a7713b1edbc 2782 /*! @name ADR_CASR - Status register - Add Register command */
AnnaBridge 171:3a7713b1edbc 2783 #define CAU_ADR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2784 #define CAU_ADR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2785 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2786 #define CAU_ADR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2787 #define CAU_ADR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2788 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2789 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2790 #define CAU_ADR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2791 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2792
AnnaBridge 171:3a7713b1edbc 2793 /*! @name ADR_CAA - Accumulator register - Add to register command */
AnnaBridge 171:3a7713b1edbc 2794 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2795 #define CAU_ADR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2796 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2797
AnnaBridge 171:3a7713b1edbc 2798 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
AnnaBridge 171:3a7713b1edbc 2799 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2800 #define CAU_ADR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2801 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2802 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2803 #define CAU_ADR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2804 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2805 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2806 #define CAU_ADR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2807 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2808 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2809 #define CAU_ADR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2810 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2811 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2812 #define CAU_ADR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2813 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2814 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2815 #define CAU_ADR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2816 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2817 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2818 #define CAU_ADR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2819 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2820 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2821 #define CAU_ADR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2822 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2823 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2824 #define CAU_ADR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2825 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2826
AnnaBridge 171:3a7713b1edbc 2827 /* The count of CAU_ADR_CA */
AnnaBridge 171:3a7713b1edbc 2828 #define CAU_ADR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2829
AnnaBridge 171:3a7713b1edbc 2830 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 2831 #define CAU_RADR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2832 #define CAU_RADR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2833 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2834 #define CAU_RADR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2835 #define CAU_RADR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2836 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2837 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2838 #define CAU_RADR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2839 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2840
AnnaBridge 171:3a7713b1edbc 2841 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 2842 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2843 #define CAU_RADR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2844 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2845
AnnaBridge 171:3a7713b1edbc 2846 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
AnnaBridge 171:3a7713b1edbc 2847 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2848 #define CAU_RADR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2849 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2850 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2851 #define CAU_RADR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2852 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2853 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2854 #define CAU_RADR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2855 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2856 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2857 #define CAU_RADR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2858 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2859 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2860 #define CAU_RADR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2861 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2862 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2863 #define CAU_RADR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2864 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2865 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2866 #define CAU_RADR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2867 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2868 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2869 #define CAU_RADR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2870 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2871 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2872 #define CAU_RADR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2873 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2874
AnnaBridge 171:3a7713b1edbc 2875 /* The count of CAU_RADR_CA */
AnnaBridge 171:3a7713b1edbc 2876 #define CAU_RADR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2877
AnnaBridge 171:3a7713b1edbc 2878 /*! @name XOR_CASR - Status register - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 2879 #define CAU_XOR_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2880 #define CAU_XOR_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2881 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2882 #define CAU_XOR_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2883 #define CAU_XOR_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2884 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2885 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2886 #define CAU_XOR_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2887 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2888
AnnaBridge 171:3a7713b1edbc 2889 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 2890 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2891 #define CAU_XOR_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2892 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2893
AnnaBridge 171:3a7713b1edbc 2894 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
AnnaBridge 171:3a7713b1edbc 2895 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2896 #define CAU_XOR_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2897 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2898 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2899 #define CAU_XOR_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2900 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2901 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2902 #define CAU_XOR_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2903 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2904 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2905 #define CAU_XOR_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2906 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2907 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2908 #define CAU_XOR_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2909 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2910 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2911 #define CAU_XOR_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2912 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2913 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2914 #define CAU_XOR_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2915 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2916 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2917 #define CAU_XOR_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2918 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2919 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2920 #define CAU_XOR_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2921 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2922
AnnaBridge 171:3a7713b1edbc 2923 /* The count of CAU_XOR_CA */
AnnaBridge 171:3a7713b1edbc 2924 #define CAU_XOR_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2925
AnnaBridge 171:3a7713b1edbc 2926 /*! @name ROTL_CASR - Status register - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 2927 #define CAU_ROTL_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2928 #define CAU_ROTL_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2929 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2930 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2931 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2932 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2933 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2934 #define CAU_ROTL_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2935 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2936
AnnaBridge 171:3a7713b1edbc 2937 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 2938 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2939 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2940 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2941
AnnaBridge 171:3a7713b1edbc 2942 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
AnnaBridge 171:3a7713b1edbc 2943 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2944 #define CAU_ROTL_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2945 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2946 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2947 #define CAU_ROTL_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2948 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2949 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2950 #define CAU_ROTL_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2951 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 2952 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2953 #define CAU_ROTL_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2954 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 2955 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2956 #define CAU_ROTL_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2957 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 2958 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2959 #define CAU_ROTL_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2960 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 2961 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2962 #define CAU_ROTL_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2963 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 2964 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2965 #define CAU_ROTL_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2966 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 2967 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2968 #define CAU_ROTL_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2969 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 2970
AnnaBridge 171:3a7713b1edbc 2971 /* The count of CAU_ROTL_CA */
AnnaBridge 171:3a7713b1edbc 2972 #define CAU_ROTL_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 2973
AnnaBridge 171:3a7713b1edbc 2974 /*! @name AESC_CASR - Status register - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 2975 #define CAU_AESC_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 2976 #define CAU_AESC_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2977 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 2978 #define CAU_AESC_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 2979 #define CAU_AESC_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 2980 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 2981 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 2982 #define CAU_AESC_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 2983 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 2984
AnnaBridge 171:3a7713b1edbc 2985 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 2986 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2987 #define CAU_AESC_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2988 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 2989
AnnaBridge 171:3a7713b1edbc 2990 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
AnnaBridge 171:3a7713b1edbc 2991 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2992 #define CAU_AESC_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2993 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 2994 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2995 #define CAU_AESC_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2996 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 2997 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 2998 #define CAU_AESC_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 2999 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 3000 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3001 #define CAU_AESC_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3002 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 3003 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3004 #define CAU_AESC_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3005 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 3006 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3007 #define CAU_AESC_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3008 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 3009 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3010 #define CAU_AESC_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3011 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 3012 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3013 #define CAU_AESC_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3014 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 3015 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3016 #define CAU_AESC_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3017 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 3018
AnnaBridge 171:3a7713b1edbc 3019 /* The count of CAU_AESC_CA */
AnnaBridge 171:3a7713b1edbc 3020 #define CAU_AESC_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 3021
AnnaBridge 171:3a7713b1edbc 3022 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 3023 #define CAU_AESIC_CASR_IC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3024 #define CAU_AESIC_CASR_IC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3025 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
AnnaBridge 171:3a7713b1edbc 3026 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3027 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3028 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
AnnaBridge 171:3a7713b1edbc 3029 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 3030 #define CAU_AESIC_CASR_VER_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3031 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
AnnaBridge 171:3a7713b1edbc 3032
AnnaBridge 171:3a7713b1edbc 3033 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 3034 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3035 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3036 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
AnnaBridge 171:3a7713b1edbc 3037
AnnaBridge 171:3a7713b1edbc 3038 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
AnnaBridge 171:3a7713b1edbc 3039 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3040 #define CAU_AESIC_CA_CA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3041 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
AnnaBridge 171:3a7713b1edbc 3042 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3043 #define CAU_AESIC_CA_CA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3044 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
AnnaBridge 171:3a7713b1edbc 3045 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3046 #define CAU_AESIC_CA_CA2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3047 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
AnnaBridge 171:3a7713b1edbc 3048 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3049 #define CAU_AESIC_CA_CA3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3050 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
AnnaBridge 171:3a7713b1edbc 3051 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3052 #define CAU_AESIC_CA_CA4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3053 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
AnnaBridge 171:3a7713b1edbc 3054 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3055 #define CAU_AESIC_CA_CA5_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3056 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
AnnaBridge 171:3a7713b1edbc 3057 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3058 #define CAU_AESIC_CA_CA6_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3059 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
AnnaBridge 171:3a7713b1edbc 3060 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3061 #define CAU_AESIC_CA_CA7_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3062 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
AnnaBridge 171:3a7713b1edbc 3063 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 3064 #define CAU_AESIC_CA_CA8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3065 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
AnnaBridge 171:3a7713b1edbc 3066
AnnaBridge 171:3a7713b1edbc 3067 /* The count of CAU_AESIC_CA */
AnnaBridge 171:3a7713b1edbc 3068 #define CAU_AESIC_CA_COUNT (9U)
AnnaBridge 171:3a7713b1edbc 3069
AnnaBridge 171:3a7713b1edbc 3070
AnnaBridge 171:3a7713b1edbc 3071 /*!
AnnaBridge 171:3a7713b1edbc 3072 * @}
AnnaBridge 171:3a7713b1edbc 3073 */ /* end of group CAU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3074
AnnaBridge 171:3a7713b1edbc 3075
AnnaBridge 171:3a7713b1edbc 3076 /* CAU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3077 /** Peripheral CAU base address */
AnnaBridge 171:3a7713b1edbc 3078 #define CAU_BASE (0xE0081000u)
AnnaBridge 171:3a7713b1edbc 3079 /** Peripheral CAU base pointer */
AnnaBridge 171:3a7713b1edbc 3080 #define CAU ((CAU_Type *)CAU_BASE)
AnnaBridge 171:3a7713b1edbc 3081 /** Array initializer of CAU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3082 #define CAU_BASE_ADDRS { CAU_BASE }
AnnaBridge 171:3a7713b1edbc 3083 /** Array initializer of CAU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3084 #define CAU_BASE_PTRS { CAU }
AnnaBridge 171:3a7713b1edbc 3085
AnnaBridge 171:3a7713b1edbc 3086 /*!
AnnaBridge 171:3a7713b1edbc 3087 * @}
AnnaBridge 171:3a7713b1edbc 3088 */ /* end of group CAU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3089
AnnaBridge 171:3a7713b1edbc 3090
AnnaBridge 171:3a7713b1edbc 3091 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3092 -- CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3093 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3094
AnnaBridge 171:3a7713b1edbc 3095 /*!
AnnaBridge 171:3a7713b1edbc 3096 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3097 * @{
AnnaBridge 171:3a7713b1edbc 3098 */
AnnaBridge 171:3a7713b1edbc 3099
AnnaBridge 171:3a7713b1edbc 3100 /** CMP - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3101 typedef struct {
AnnaBridge 171:3a7713b1edbc 3102 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3103 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3104 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3105 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3106 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3107 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3108 } CMP_Type;
AnnaBridge 171:3a7713b1edbc 3109
AnnaBridge 171:3a7713b1edbc 3110 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3111 -- CMP Register Masks
AnnaBridge 171:3a7713b1edbc 3112 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3113
AnnaBridge 171:3a7713b1edbc 3114 /*!
AnnaBridge 171:3a7713b1edbc 3115 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 171:3a7713b1edbc 3116 * @{
AnnaBridge 171:3a7713b1edbc 3117 */
AnnaBridge 171:3a7713b1edbc 3118
AnnaBridge 171:3a7713b1edbc 3119 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 171:3a7713b1edbc 3120 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 3121 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3122 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 171:3a7713b1edbc 3123 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 3124 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3125 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 3126
AnnaBridge 171:3a7713b1edbc 3127 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 171:3a7713b1edbc 3128 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3129 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3130 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 3131 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3132 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3133 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 171:3a7713b1edbc 3134 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3135 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3136 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 171:3a7713b1edbc 3137 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3138 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3139 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 171:3a7713b1edbc 3140 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3141 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3142 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 171:3a7713b1edbc 3143 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3144 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3145 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 171:3a7713b1edbc 3146 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3147 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3148 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 171:3a7713b1edbc 3149
AnnaBridge 171:3a7713b1edbc 3150 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 171:3a7713b1edbc 3151 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3152 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3153 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 171:3a7713b1edbc 3154
AnnaBridge 171:3a7713b1edbc 3155 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 171:3a7713b1edbc 3156 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3157 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3158 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 171:3a7713b1edbc 3159 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3160 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3161 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 171:3a7713b1edbc 3162 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3163 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3164 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 171:3a7713b1edbc 3165 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3166 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3167 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 171:3a7713b1edbc 3168 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3169 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3170 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 171:3a7713b1edbc 3171 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3172 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3173 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3174
AnnaBridge 171:3a7713b1edbc 3175 /*! @name DACCR - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 3176 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 3177 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3178 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3179 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3180 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3181 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3182 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3183 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3184 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 3185
AnnaBridge 171:3a7713b1edbc 3186 /*! @name MUXCR - MUX Control Register */
AnnaBridge 171:3a7713b1edbc 3187 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 3188 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3189 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3190 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 3191 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3192 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3193 #define CMP_MUXCR_PSTM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3194 #define CMP_MUXCR_PSTM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3195 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
AnnaBridge 171:3a7713b1edbc 3196
AnnaBridge 171:3a7713b1edbc 3197
AnnaBridge 171:3a7713b1edbc 3198 /*!
AnnaBridge 171:3a7713b1edbc 3199 * @}
AnnaBridge 171:3a7713b1edbc 3200 */ /* end of group CMP_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3201
AnnaBridge 171:3a7713b1edbc 3202
AnnaBridge 171:3a7713b1edbc 3203 /* CMP - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3204 /** Peripheral CMP0 base address */
AnnaBridge 171:3a7713b1edbc 3205 #define CMP0_BASE (0x40073000u)
AnnaBridge 171:3a7713b1edbc 3206 /** Peripheral CMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 3207 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 171:3a7713b1edbc 3208 /** Peripheral CMP1 base address */
AnnaBridge 171:3a7713b1edbc 3209 #define CMP1_BASE (0x40073008u)
AnnaBridge 171:3a7713b1edbc 3210 /** Peripheral CMP1 base pointer */
AnnaBridge 171:3a7713b1edbc 3211 #define CMP1 ((CMP_Type *)CMP1_BASE)
AnnaBridge 171:3a7713b1edbc 3212 /** Peripheral CMP2 base address */
AnnaBridge 171:3a7713b1edbc 3213 #define CMP2_BASE (0x40073010u)
AnnaBridge 171:3a7713b1edbc 3214 /** Peripheral CMP2 base pointer */
AnnaBridge 171:3a7713b1edbc 3215 #define CMP2 ((CMP_Type *)CMP2_BASE)
AnnaBridge 171:3a7713b1edbc 3216 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3217 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
AnnaBridge 171:3a7713b1edbc 3218 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3219 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
AnnaBridge 171:3a7713b1edbc 3220 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 171:3a7713b1edbc 3221 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
AnnaBridge 171:3a7713b1edbc 3222
AnnaBridge 171:3a7713b1edbc 3223 /*!
AnnaBridge 171:3a7713b1edbc 3224 * @}
AnnaBridge 171:3a7713b1edbc 3225 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3226
AnnaBridge 171:3a7713b1edbc 3227
AnnaBridge 171:3a7713b1edbc 3228 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3229 -- CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3230 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3231
AnnaBridge 171:3a7713b1edbc 3232 /*!
AnnaBridge 171:3a7713b1edbc 3233 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3234 * @{
AnnaBridge 171:3a7713b1edbc 3235 */
AnnaBridge 171:3a7713b1edbc 3236
AnnaBridge 171:3a7713b1edbc 3237 /** CMT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3238 typedef struct {
AnnaBridge 171:3a7713b1edbc 3239 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3240 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3241 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3242 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3243 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3244 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3245 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3246 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3247 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3248 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 3249 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 3250 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3251 } CMT_Type;
AnnaBridge 171:3a7713b1edbc 3252
AnnaBridge 171:3a7713b1edbc 3253 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3254 -- CMT Register Masks
AnnaBridge 171:3a7713b1edbc 3255 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3256
AnnaBridge 171:3a7713b1edbc 3257 /*!
AnnaBridge 171:3a7713b1edbc 3258 * @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge 171:3a7713b1edbc 3259 * @{
AnnaBridge 171:3a7713b1edbc 3260 */
AnnaBridge 171:3a7713b1edbc 3261
AnnaBridge 171:3a7713b1edbc 3262 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
AnnaBridge 171:3a7713b1edbc 3263 #define CMT_CGH1_PH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3264 #define CMT_CGH1_PH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3265 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
AnnaBridge 171:3a7713b1edbc 3266
AnnaBridge 171:3a7713b1edbc 3267 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
AnnaBridge 171:3a7713b1edbc 3268 #define CMT_CGL1_PL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3269 #define CMT_CGL1_PL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3270 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
AnnaBridge 171:3a7713b1edbc 3271
AnnaBridge 171:3a7713b1edbc 3272 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
AnnaBridge 171:3a7713b1edbc 3273 #define CMT_CGH2_SH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3274 #define CMT_CGH2_SH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3275 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
AnnaBridge 171:3a7713b1edbc 3276
AnnaBridge 171:3a7713b1edbc 3277 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
AnnaBridge 171:3a7713b1edbc 3278 #define CMT_CGL2_SL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3279 #define CMT_CGL2_SL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3280 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
AnnaBridge 171:3a7713b1edbc 3281
AnnaBridge 171:3a7713b1edbc 3282 /*! @name OC - CMT Output Control Register */
AnnaBridge 171:3a7713b1edbc 3283 #define CMT_OC_IROPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3284 #define CMT_OC_IROPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3285 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
AnnaBridge 171:3a7713b1edbc 3286 #define CMT_OC_CMTPOL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3287 #define CMT_OC_CMTPOL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3288 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
AnnaBridge 171:3a7713b1edbc 3289 #define CMT_OC_IROL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3290 #define CMT_OC_IROL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3291 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
AnnaBridge 171:3a7713b1edbc 3292
AnnaBridge 171:3a7713b1edbc 3293 /*! @name MSC - CMT Modulator Status and Control Register */
AnnaBridge 171:3a7713b1edbc 3294 #define CMT_MSC_MCGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3295 #define CMT_MSC_MCGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3296 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
AnnaBridge 171:3a7713b1edbc 3297 #define CMT_MSC_EOCIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3298 #define CMT_MSC_EOCIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3299 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
AnnaBridge 171:3a7713b1edbc 3300 #define CMT_MSC_FSK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3301 #define CMT_MSC_FSK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3302 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
AnnaBridge 171:3a7713b1edbc 3303 #define CMT_MSC_BASE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3304 #define CMT_MSC_BASE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3305 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
AnnaBridge 171:3a7713b1edbc 3306 #define CMT_MSC_EXSPC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3307 #define CMT_MSC_EXSPC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3308 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
AnnaBridge 171:3a7713b1edbc 3309 #define CMT_MSC_CMTDIV_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 3310 #define CMT_MSC_CMTDIV_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3311 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
AnnaBridge 171:3a7713b1edbc 3312 #define CMT_MSC_EOCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3313 #define CMT_MSC_EOCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3314 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
AnnaBridge 171:3a7713b1edbc 3315
AnnaBridge 171:3a7713b1edbc 3316 /*! @name CMD1 - CMT Modulator Data Register Mark High */
AnnaBridge 171:3a7713b1edbc 3317 #define CMT_CMD1_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3318 #define CMT_CMD1_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3319 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
AnnaBridge 171:3a7713b1edbc 3320
AnnaBridge 171:3a7713b1edbc 3321 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
AnnaBridge 171:3a7713b1edbc 3322 #define CMT_CMD2_MB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3323 #define CMT_CMD2_MB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3324 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
AnnaBridge 171:3a7713b1edbc 3325
AnnaBridge 171:3a7713b1edbc 3326 /*! @name CMD3 - CMT Modulator Data Register Space High */
AnnaBridge 171:3a7713b1edbc 3327 #define CMT_CMD3_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3328 #define CMT_CMD3_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3329 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
AnnaBridge 171:3a7713b1edbc 3330
AnnaBridge 171:3a7713b1edbc 3331 /*! @name CMD4 - CMT Modulator Data Register Space Low */
AnnaBridge 171:3a7713b1edbc 3332 #define CMT_CMD4_SB_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3333 #define CMT_CMD4_SB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3334 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
AnnaBridge 171:3a7713b1edbc 3335
AnnaBridge 171:3a7713b1edbc 3336 /*! @name PPS - CMT Primary Prescaler Register */
AnnaBridge 171:3a7713b1edbc 3337 #define CMT_PPS_PPSDIV_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3338 #define CMT_PPS_PPSDIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3339 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
AnnaBridge 171:3a7713b1edbc 3340
AnnaBridge 171:3a7713b1edbc 3341 /*! @name DMA - CMT Direct Memory Access Register */
AnnaBridge 171:3a7713b1edbc 3342 #define CMT_DMA_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3343 #define CMT_DMA_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3344 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 3345
AnnaBridge 171:3a7713b1edbc 3346
AnnaBridge 171:3a7713b1edbc 3347 /*!
AnnaBridge 171:3a7713b1edbc 3348 * @}
AnnaBridge 171:3a7713b1edbc 3349 */ /* end of group CMT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3350
AnnaBridge 171:3a7713b1edbc 3351
AnnaBridge 171:3a7713b1edbc 3352 /* CMT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3353 /** Peripheral CMT base address */
AnnaBridge 171:3a7713b1edbc 3354 #define CMT_BASE (0x40062000u)
AnnaBridge 171:3a7713b1edbc 3355 /** Peripheral CMT base pointer */
AnnaBridge 171:3a7713b1edbc 3356 #define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge 171:3a7713b1edbc 3357 /** Array initializer of CMT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3358 #define CMT_BASE_ADDRS { CMT_BASE }
AnnaBridge 171:3a7713b1edbc 3359 /** Array initializer of CMT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3360 #define CMT_BASE_PTRS { CMT }
AnnaBridge 171:3a7713b1edbc 3361 /** Interrupt vectors for the CMT peripheral type */
AnnaBridge 171:3a7713b1edbc 3362 #define CMT_IRQS { CMT_IRQn }
AnnaBridge 171:3a7713b1edbc 3363
AnnaBridge 171:3a7713b1edbc 3364 /*!
AnnaBridge 171:3a7713b1edbc 3365 * @}
AnnaBridge 171:3a7713b1edbc 3366 */ /* end of group CMT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3367
AnnaBridge 171:3a7713b1edbc 3368
AnnaBridge 171:3a7713b1edbc 3369 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3370 -- CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3371 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3372
AnnaBridge 171:3a7713b1edbc 3373 /*!
AnnaBridge 171:3a7713b1edbc 3374 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3375 * @{
AnnaBridge 171:3a7713b1edbc 3376 */
AnnaBridge 171:3a7713b1edbc 3377
AnnaBridge 171:3a7713b1edbc 3378 /** CRC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3379 typedef struct {
AnnaBridge 171:3a7713b1edbc 3380 union { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3381 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3382 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3383 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3384 } ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 3385 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3386 struct { /* offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3387 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3388 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 3389 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 3390 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 3391 } ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 3392 };
AnnaBridge 171:3a7713b1edbc 3393 union { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3394 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3395 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3396 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3397 } GPOLY_ACCESS16BIT;
AnnaBridge 171:3a7713b1edbc 3398 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3399 struct { /* offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3400 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3401 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 3402 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 3403 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 3404 } GPOLY_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 3405 };
AnnaBridge 171:3a7713b1edbc 3406 union { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3407 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3408 struct { /* offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 3409 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 3410 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
AnnaBridge 171:3a7713b1edbc 3411 } CTRL_ACCESS8BIT;
AnnaBridge 171:3a7713b1edbc 3412 };
AnnaBridge 171:3a7713b1edbc 3413 } CRC_Type;
AnnaBridge 171:3a7713b1edbc 3414
AnnaBridge 171:3a7713b1edbc 3415 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3416 -- CRC Register Masks
AnnaBridge 171:3a7713b1edbc 3417 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3418
AnnaBridge 171:3a7713b1edbc 3419 /*!
AnnaBridge 171:3a7713b1edbc 3420 * @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge 171:3a7713b1edbc 3421 * @{
AnnaBridge 171:3a7713b1edbc 3422 */
AnnaBridge 171:3a7713b1edbc 3423
AnnaBridge 171:3a7713b1edbc 3424 /*! @name DATAL - CRC_DATAL register. */
AnnaBridge 171:3a7713b1edbc 3425 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3426 #define CRC_DATAL_DATAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3427 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
AnnaBridge 171:3a7713b1edbc 3428
AnnaBridge 171:3a7713b1edbc 3429 /*! @name DATAH - CRC_DATAH register. */
AnnaBridge 171:3a7713b1edbc 3430 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3431 #define CRC_DATAH_DATAH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3432 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
AnnaBridge 171:3a7713b1edbc 3433
AnnaBridge 171:3a7713b1edbc 3434 /*! @name DATA - CRC Data register */
AnnaBridge 171:3a7713b1edbc 3435 #define CRC_DATA_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3436 #define CRC_DATA_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3437 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
AnnaBridge 171:3a7713b1edbc 3438 #define CRC_DATA_LU_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 3439 #define CRC_DATA_LU_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3440 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
AnnaBridge 171:3a7713b1edbc 3441 #define CRC_DATA_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 3442 #define CRC_DATA_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3443 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
AnnaBridge 171:3a7713b1edbc 3444 #define CRC_DATA_HU_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 3445 #define CRC_DATA_HU_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3446 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
AnnaBridge 171:3a7713b1edbc 3447
AnnaBridge 171:3a7713b1edbc 3448 /*! @name DATALL - CRC_DATALL register. */
AnnaBridge 171:3a7713b1edbc 3449 #define CRC_DATALL_DATALL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3450 #define CRC_DATALL_DATALL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3451 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
AnnaBridge 171:3a7713b1edbc 3452
AnnaBridge 171:3a7713b1edbc 3453 /*! @name DATALU - CRC_DATALU register. */
AnnaBridge 171:3a7713b1edbc 3454 #define CRC_DATALU_DATALU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3455 #define CRC_DATALU_DATALU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3456 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
AnnaBridge 171:3a7713b1edbc 3457
AnnaBridge 171:3a7713b1edbc 3458 /*! @name DATAHL - CRC_DATAHL register. */
AnnaBridge 171:3a7713b1edbc 3459 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3460 #define CRC_DATAHL_DATAHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3461 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
AnnaBridge 171:3a7713b1edbc 3462
AnnaBridge 171:3a7713b1edbc 3463 /*! @name DATAHU - CRC_DATAHU register. */
AnnaBridge 171:3a7713b1edbc 3464 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3465 #define CRC_DATAHU_DATAHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3466 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
AnnaBridge 171:3a7713b1edbc 3467
AnnaBridge 171:3a7713b1edbc 3468 /*! @name GPOLYL - CRC_GPOLYL register. */
AnnaBridge 171:3a7713b1edbc 3469 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3470 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3471 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge 171:3a7713b1edbc 3472
AnnaBridge 171:3a7713b1edbc 3473 /*! @name GPOLYH - CRC_GPOLYH register. */
AnnaBridge 171:3a7713b1edbc 3474 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3475 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3476 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge 171:3a7713b1edbc 3477
AnnaBridge 171:3a7713b1edbc 3478 /*! @name GPOLY - CRC Polynomial register */
AnnaBridge 171:3a7713b1edbc 3479 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 3480 #define CRC_GPOLY_LOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3481 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
AnnaBridge 171:3a7713b1edbc 3482 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 3483 #define CRC_GPOLY_HIGH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3484 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
AnnaBridge 171:3a7713b1edbc 3485
AnnaBridge 171:3a7713b1edbc 3486 /*! @name GPOLYLL - CRC_GPOLYLL register. */
AnnaBridge 171:3a7713b1edbc 3487 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3488 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3489 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge 171:3a7713b1edbc 3490
AnnaBridge 171:3a7713b1edbc 3491 /*! @name GPOLYLU - CRC_GPOLYLU register. */
AnnaBridge 171:3a7713b1edbc 3492 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3493 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3494 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge 171:3a7713b1edbc 3495
AnnaBridge 171:3a7713b1edbc 3496 /*! @name GPOLYHL - CRC_GPOLYHL register. */
AnnaBridge 171:3a7713b1edbc 3497 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3498 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3499 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge 171:3a7713b1edbc 3500
AnnaBridge 171:3a7713b1edbc 3501 /*! @name GPOLYHU - CRC_GPOLYHU register. */
AnnaBridge 171:3a7713b1edbc 3502 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3503 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3504 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge 171:3a7713b1edbc 3505
AnnaBridge 171:3a7713b1edbc 3506 /*! @name CTRL - CRC Control register */
AnnaBridge 171:3a7713b1edbc 3507 #define CRC_CTRL_TCRC_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 3508 #define CRC_CTRL_TCRC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 3509 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 3510 #define CRC_CTRL_WAS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 3511 #define CRC_CTRL_WAS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 3512 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 3513 #define CRC_CTRL_FXOR_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 3514 #define CRC_CTRL_FXOR_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 3515 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 3516 #define CRC_CTRL_TOTR_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 3517 #define CRC_CTRL_TOTR_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 3518 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 3519 #define CRC_CTRL_TOT_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 3520 #define CRC_CTRL_TOT_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 3521 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 3522
AnnaBridge 171:3a7713b1edbc 3523 /*! @name CTRLHU - CRC_CTRLHU register. */
AnnaBridge 171:3a7713b1edbc 3524 #define CRC_CTRLHU_TCRC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3525 #define CRC_CTRLHU_TCRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3526 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
AnnaBridge 171:3a7713b1edbc 3527 #define CRC_CTRLHU_WAS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3528 #define CRC_CTRLHU_WAS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3529 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
AnnaBridge 171:3a7713b1edbc 3530 #define CRC_CTRLHU_FXOR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3531 #define CRC_CTRLHU_FXOR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3532 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
AnnaBridge 171:3a7713b1edbc 3533 #define CRC_CTRLHU_TOTR_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 3534 #define CRC_CTRLHU_TOTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3535 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
AnnaBridge 171:3a7713b1edbc 3536 #define CRC_CTRLHU_TOT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 3537 #define CRC_CTRLHU_TOT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3538 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
AnnaBridge 171:3a7713b1edbc 3539
AnnaBridge 171:3a7713b1edbc 3540
AnnaBridge 171:3a7713b1edbc 3541 /*!
AnnaBridge 171:3a7713b1edbc 3542 * @}
AnnaBridge 171:3a7713b1edbc 3543 */ /* end of group CRC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3544
AnnaBridge 171:3a7713b1edbc 3545
AnnaBridge 171:3a7713b1edbc 3546 /* CRC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3547 /** Peripheral CRC base address */
AnnaBridge 171:3a7713b1edbc 3548 #define CRC_BASE (0x40032000u)
AnnaBridge 171:3a7713b1edbc 3549 /** Peripheral CRC base pointer */
AnnaBridge 171:3a7713b1edbc 3550 #define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge 171:3a7713b1edbc 3551 /** Array initializer of CRC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3552 #define CRC_BASE_ADDRS { CRC_BASE }
AnnaBridge 171:3a7713b1edbc 3553 /** Array initializer of CRC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3554 #define CRC_BASE_PTRS { CRC0 }
AnnaBridge 171:3a7713b1edbc 3555
AnnaBridge 171:3a7713b1edbc 3556 /*!
AnnaBridge 171:3a7713b1edbc 3557 * @}
AnnaBridge 171:3a7713b1edbc 3558 */ /* end of group CRC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3559
AnnaBridge 171:3a7713b1edbc 3560
AnnaBridge 171:3a7713b1edbc 3561 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3562 -- DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3563 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3564
AnnaBridge 171:3a7713b1edbc 3565 /*!
AnnaBridge 171:3a7713b1edbc 3566 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3567 * @{
AnnaBridge 171:3a7713b1edbc 3568 */
AnnaBridge 171:3a7713b1edbc 3569
AnnaBridge 171:3a7713b1edbc 3570 /** DAC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3571 typedef struct {
AnnaBridge 171:3a7713b1edbc 3572 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 3573 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 3574 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 171:3a7713b1edbc 3575 } DAT[16];
AnnaBridge 171:3a7713b1edbc 3576 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 3577 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 171:3a7713b1edbc 3578 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 171:3a7713b1edbc 3579 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 171:3a7713b1edbc 3580 } DAC_Type;
AnnaBridge 171:3a7713b1edbc 3581
AnnaBridge 171:3a7713b1edbc 3582 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3583 -- DAC Register Masks
AnnaBridge 171:3a7713b1edbc 3584 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3585
AnnaBridge 171:3a7713b1edbc 3586 /*!
AnnaBridge 171:3a7713b1edbc 3587 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 171:3a7713b1edbc 3588 * @{
AnnaBridge 171:3a7713b1edbc 3589 */
AnnaBridge 171:3a7713b1edbc 3590
AnnaBridge 171:3a7713b1edbc 3591 /*! @name DATL - DAC Data Low Register */
AnnaBridge 171:3a7713b1edbc 3592 #define DAC_DATL_DATA0_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 3593 #define DAC_DATL_DATA0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3594 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
AnnaBridge 171:3a7713b1edbc 3595
AnnaBridge 171:3a7713b1edbc 3596 /* The count of DAC_DATL */
AnnaBridge 171:3a7713b1edbc 3597 #define DAC_DATL_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 3598
AnnaBridge 171:3a7713b1edbc 3599 /*! @name DATH - DAC Data High Register */
AnnaBridge 171:3a7713b1edbc 3600 #define DAC_DATH_DATA1_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3601 #define DAC_DATH_DATA1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3602 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
AnnaBridge 171:3a7713b1edbc 3603
AnnaBridge 171:3a7713b1edbc 3604 /* The count of DAC_DATH */
AnnaBridge 171:3a7713b1edbc 3605 #define DAC_DATH_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 3606
AnnaBridge 171:3a7713b1edbc 3607 /*! @name SR - DAC Status Register */
AnnaBridge 171:3a7713b1edbc 3608 #define DAC_SR_DACBFRPBF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3609 #define DAC_SR_DACBFRPBF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3610 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
AnnaBridge 171:3a7713b1edbc 3611 #define DAC_SR_DACBFRPTF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3612 #define DAC_SR_DACBFRPTF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3613 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
AnnaBridge 171:3a7713b1edbc 3614 #define DAC_SR_DACBFWMF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3615 #define DAC_SR_DACBFWMF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3616 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
AnnaBridge 171:3a7713b1edbc 3617
AnnaBridge 171:3a7713b1edbc 3618 /*! @name C0 - DAC Control Register */
AnnaBridge 171:3a7713b1edbc 3619 #define DAC_C0_DACBBIEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3620 #define DAC_C0_DACBBIEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3621 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
AnnaBridge 171:3a7713b1edbc 3622 #define DAC_C0_DACBTIEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3623 #define DAC_C0_DACBTIEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3624 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 3625 #define DAC_C0_DACBWIEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3626 #define DAC_C0_DACBWIEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3627 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
AnnaBridge 171:3a7713b1edbc 3628 #define DAC_C0_LPEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3629 #define DAC_C0_LPEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3630 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
AnnaBridge 171:3a7713b1edbc 3631 #define DAC_C0_DACSWTRG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3632 #define DAC_C0_DACSWTRG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3633 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
AnnaBridge 171:3a7713b1edbc 3634 #define DAC_C0_DACTRGSEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3635 #define DAC_C0_DACTRGSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3636 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 3637 #define DAC_C0_DACRFS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3638 #define DAC_C0_DACRFS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3639 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
AnnaBridge 171:3a7713b1edbc 3640 #define DAC_C0_DACEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3641 #define DAC_C0_DACEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3642 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
AnnaBridge 171:3a7713b1edbc 3643
AnnaBridge 171:3a7713b1edbc 3644 /*! @name C1 - DAC Control Register 1 */
AnnaBridge 171:3a7713b1edbc 3645 #define DAC_C1_DACBFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3646 #define DAC_C1_DACBFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3647 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
AnnaBridge 171:3a7713b1edbc 3648 #define DAC_C1_DACBFMD_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 3649 #define DAC_C1_DACBFMD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3650 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
AnnaBridge 171:3a7713b1edbc 3651 #define DAC_C1_DACBFWM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 3652 #define DAC_C1_DACBFWM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3653 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
AnnaBridge 171:3a7713b1edbc 3654 #define DAC_C1_DMAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3655 #define DAC_C1_DMAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3656 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 3657
AnnaBridge 171:3a7713b1edbc 3658 /*! @name C2 - DAC Control Register 2 */
AnnaBridge 171:3a7713b1edbc 3659 #define DAC_C2_DACBFUP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3660 #define DAC_C2_DACBFUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3661 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
AnnaBridge 171:3a7713b1edbc 3662 #define DAC_C2_DACBFRP_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 3663 #define DAC_C2_DACBFRP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3664 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
AnnaBridge 171:3a7713b1edbc 3665
AnnaBridge 171:3a7713b1edbc 3666
AnnaBridge 171:3a7713b1edbc 3667 /*!
AnnaBridge 171:3a7713b1edbc 3668 * @}
AnnaBridge 171:3a7713b1edbc 3669 */ /* end of group DAC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 3670
AnnaBridge 171:3a7713b1edbc 3671
AnnaBridge 171:3a7713b1edbc 3672 /* DAC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 3673 /** Peripheral DAC0 base address */
AnnaBridge 171:3a7713b1edbc 3674 #define DAC0_BASE (0x400CC000u)
AnnaBridge 171:3a7713b1edbc 3675 /** Peripheral DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 3676 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 171:3a7713b1edbc 3677 /** Peripheral DAC1 base address */
AnnaBridge 171:3a7713b1edbc 3678 #define DAC1_BASE (0x400CD000u)
AnnaBridge 171:3a7713b1edbc 3679 /** Peripheral DAC1 base pointer */
AnnaBridge 171:3a7713b1edbc 3680 #define DAC1 ((DAC_Type *)DAC1_BASE)
AnnaBridge 171:3a7713b1edbc 3681 /** Array initializer of DAC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 3682 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
AnnaBridge 171:3a7713b1edbc 3683 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 3684 #define DAC_BASE_PTRS { DAC0, DAC1 }
AnnaBridge 171:3a7713b1edbc 3685 /** Interrupt vectors for the DAC peripheral type */
AnnaBridge 171:3a7713b1edbc 3686 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
AnnaBridge 171:3a7713b1edbc 3687
AnnaBridge 171:3a7713b1edbc 3688 /*!
AnnaBridge 171:3a7713b1edbc 3689 * @}
AnnaBridge 171:3a7713b1edbc 3690 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 3691
AnnaBridge 171:3a7713b1edbc 3692
AnnaBridge 171:3a7713b1edbc 3693 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3694 -- DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3695 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3696
AnnaBridge 171:3a7713b1edbc 3697 /*!
AnnaBridge 171:3a7713b1edbc 3698 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 3699 * @{
AnnaBridge 171:3a7713b1edbc 3700 */
AnnaBridge 171:3a7713b1edbc 3701
AnnaBridge 171:3a7713b1edbc 3702 /** DMA - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 3703 typedef struct {
AnnaBridge 171:3a7713b1edbc 3704 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 3705 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 3706 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 3707 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 3708 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 3709 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 3710 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 3711 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 3712 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 3713 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 3714 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 3715 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 3716 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 3717 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 3718 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 3719 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 3720 uint8_t RESERVED_3[4];
AnnaBridge 171:3a7713b1edbc 3721 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 3722 uint8_t RESERVED_4[4];
AnnaBridge 171:3a7713b1edbc 3723 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 3724 uint8_t RESERVED_5[200];
AnnaBridge 171:3a7713b1edbc 3725 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 3726 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
AnnaBridge 171:3a7713b1edbc 3727 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
AnnaBridge 171:3a7713b1edbc 3728 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
AnnaBridge 171:3a7713b1edbc 3729 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 3730 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
AnnaBridge 171:3a7713b1edbc 3731 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
AnnaBridge 171:3a7713b1edbc 3732 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
AnnaBridge 171:3a7713b1edbc 3733 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 3734 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
AnnaBridge 171:3a7713b1edbc 3735 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
AnnaBridge 171:3a7713b1edbc 3736 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
AnnaBridge 171:3a7713b1edbc 3737 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 3738 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
AnnaBridge 171:3a7713b1edbc 3739 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
AnnaBridge 171:3a7713b1edbc 3740 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
AnnaBridge 171:3a7713b1edbc 3741 uint8_t RESERVED_6[3824];
AnnaBridge 171:3a7713b1edbc 3742 struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3743 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3744 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3745 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3746 union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3747 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3748 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3749 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3750 };
AnnaBridge 171:3a7713b1edbc 3751 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3752 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3753 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3754 union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3755 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3756 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3757 };
AnnaBridge 171:3a7713b1edbc 3758 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3759 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3760 union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3761 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3762 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 171:3a7713b1edbc 3763 };
AnnaBridge 171:3a7713b1edbc 3764 } TCD[16];
AnnaBridge 171:3a7713b1edbc 3765 } DMA_Type;
AnnaBridge 171:3a7713b1edbc 3766
AnnaBridge 171:3a7713b1edbc 3767 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 3768 -- DMA Register Masks
AnnaBridge 171:3a7713b1edbc 3769 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 3770
AnnaBridge 171:3a7713b1edbc 3771 /*!
AnnaBridge 171:3a7713b1edbc 3772 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 171:3a7713b1edbc 3773 * @{
AnnaBridge 171:3a7713b1edbc 3774 */
AnnaBridge 171:3a7713b1edbc 3775
AnnaBridge 171:3a7713b1edbc 3776 /*! @name CR - Control Register */
AnnaBridge 171:3a7713b1edbc 3777 #define DMA_CR_EDBG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3778 #define DMA_CR_EDBG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3779 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
AnnaBridge 171:3a7713b1edbc 3780 #define DMA_CR_ERCA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3781 #define DMA_CR_ERCA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3782 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
AnnaBridge 171:3a7713b1edbc 3783 #define DMA_CR_HOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3784 #define DMA_CR_HOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3785 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
AnnaBridge 171:3a7713b1edbc 3786 #define DMA_CR_HALT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3787 #define DMA_CR_HALT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3788 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 3789 #define DMA_CR_CLM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3790 #define DMA_CR_CLM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3791 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
AnnaBridge 171:3a7713b1edbc 3792 #define DMA_CR_EMLM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3793 #define DMA_CR_EMLM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3794 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
AnnaBridge 171:3a7713b1edbc 3795 #define DMA_CR_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3796 #define DMA_CR_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3797 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 3798 #define DMA_CR_CX_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 3799 #define DMA_CR_CX_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 3800 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
AnnaBridge 171:3a7713b1edbc 3801
AnnaBridge 171:3a7713b1edbc 3802 /*! @name ES - Error Status Register */
AnnaBridge 171:3a7713b1edbc 3803 #define DMA_ES_DBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3804 #define DMA_ES_DBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3805 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
AnnaBridge 171:3a7713b1edbc 3806 #define DMA_ES_SBE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3807 #define DMA_ES_SBE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3808 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
AnnaBridge 171:3a7713b1edbc 3809 #define DMA_ES_SGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3810 #define DMA_ES_SGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3811 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
AnnaBridge 171:3a7713b1edbc 3812 #define DMA_ES_NCE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3813 #define DMA_ES_NCE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3814 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
AnnaBridge 171:3a7713b1edbc 3815 #define DMA_ES_DOE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3816 #define DMA_ES_DOE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3817 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
AnnaBridge 171:3a7713b1edbc 3818 #define DMA_ES_DAE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3819 #define DMA_ES_DAE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3820 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
AnnaBridge 171:3a7713b1edbc 3821 #define DMA_ES_SOE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3822 #define DMA_ES_SOE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3823 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
AnnaBridge 171:3a7713b1edbc 3824 #define DMA_ES_SAE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3825 #define DMA_ES_SAE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3826 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
AnnaBridge 171:3a7713b1edbc 3827 #define DMA_ES_ERRCHN_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 3828 #define DMA_ES_ERRCHN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3829 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
AnnaBridge 171:3a7713b1edbc 3830 #define DMA_ES_CPE_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3831 #define DMA_ES_CPE_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3832 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
AnnaBridge 171:3a7713b1edbc 3833 #define DMA_ES_ECX_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 3834 #define DMA_ES_ECX_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 3835 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
AnnaBridge 171:3a7713b1edbc 3836 #define DMA_ES_VLD_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 3837 #define DMA_ES_VLD_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 3838 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 3839
AnnaBridge 171:3a7713b1edbc 3840 /*! @name ERQ - Enable Request Register */
AnnaBridge 171:3a7713b1edbc 3841 #define DMA_ERQ_ERQ0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3842 #define DMA_ERQ_ERQ0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3843 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
AnnaBridge 171:3a7713b1edbc 3844 #define DMA_ERQ_ERQ1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3845 #define DMA_ERQ_ERQ1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3846 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
AnnaBridge 171:3a7713b1edbc 3847 #define DMA_ERQ_ERQ2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3848 #define DMA_ERQ_ERQ2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3849 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
AnnaBridge 171:3a7713b1edbc 3850 #define DMA_ERQ_ERQ3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3851 #define DMA_ERQ_ERQ3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3852 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
AnnaBridge 171:3a7713b1edbc 3853 #define DMA_ERQ_ERQ4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3854 #define DMA_ERQ_ERQ4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3855 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
AnnaBridge 171:3a7713b1edbc 3856 #define DMA_ERQ_ERQ5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3857 #define DMA_ERQ_ERQ5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3858 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
AnnaBridge 171:3a7713b1edbc 3859 #define DMA_ERQ_ERQ6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3860 #define DMA_ERQ_ERQ6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3861 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
AnnaBridge 171:3a7713b1edbc 3862 #define DMA_ERQ_ERQ7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3863 #define DMA_ERQ_ERQ7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3864 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
AnnaBridge 171:3a7713b1edbc 3865 #define DMA_ERQ_ERQ8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3866 #define DMA_ERQ_ERQ8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3867 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
AnnaBridge 171:3a7713b1edbc 3868 #define DMA_ERQ_ERQ9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3869 #define DMA_ERQ_ERQ9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3870 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
AnnaBridge 171:3a7713b1edbc 3871 #define DMA_ERQ_ERQ10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3872 #define DMA_ERQ_ERQ10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3873 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
AnnaBridge 171:3a7713b1edbc 3874 #define DMA_ERQ_ERQ11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3875 #define DMA_ERQ_ERQ11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3876 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
AnnaBridge 171:3a7713b1edbc 3877 #define DMA_ERQ_ERQ12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3878 #define DMA_ERQ_ERQ12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3879 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
AnnaBridge 171:3a7713b1edbc 3880 #define DMA_ERQ_ERQ13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3881 #define DMA_ERQ_ERQ13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3882 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
AnnaBridge 171:3a7713b1edbc 3883 #define DMA_ERQ_ERQ14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3884 #define DMA_ERQ_ERQ14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3885 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
AnnaBridge 171:3a7713b1edbc 3886 #define DMA_ERQ_ERQ15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3887 #define DMA_ERQ_ERQ15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3888 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
AnnaBridge 171:3a7713b1edbc 3889
AnnaBridge 171:3a7713b1edbc 3890 /*! @name EEI - Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 3891 #define DMA_EEI_EEI0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 3892 #define DMA_EEI_EEI0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3893 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
AnnaBridge 171:3a7713b1edbc 3894 #define DMA_EEI_EEI1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 3895 #define DMA_EEI_EEI1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 3896 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
AnnaBridge 171:3a7713b1edbc 3897 #define DMA_EEI_EEI2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 3898 #define DMA_EEI_EEI2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 3899 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
AnnaBridge 171:3a7713b1edbc 3900 #define DMA_EEI_EEI3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 3901 #define DMA_EEI_EEI3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 3902 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
AnnaBridge 171:3a7713b1edbc 3903 #define DMA_EEI_EEI4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 3904 #define DMA_EEI_EEI4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 3905 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
AnnaBridge 171:3a7713b1edbc 3906 #define DMA_EEI_EEI5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 3907 #define DMA_EEI_EEI5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 3908 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
AnnaBridge 171:3a7713b1edbc 3909 #define DMA_EEI_EEI6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3910 #define DMA_EEI_EEI6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3911 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
AnnaBridge 171:3a7713b1edbc 3912 #define DMA_EEI_EEI7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3913 #define DMA_EEI_EEI7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3914 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
AnnaBridge 171:3a7713b1edbc 3915 #define DMA_EEI_EEI8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 3916 #define DMA_EEI_EEI8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 3917 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
AnnaBridge 171:3a7713b1edbc 3918 #define DMA_EEI_EEI9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 3919 #define DMA_EEI_EEI9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 3920 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
AnnaBridge 171:3a7713b1edbc 3921 #define DMA_EEI_EEI10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 3922 #define DMA_EEI_EEI10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 3923 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
AnnaBridge 171:3a7713b1edbc 3924 #define DMA_EEI_EEI11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 3925 #define DMA_EEI_EEI11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 3926 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
AnnaBridge 171:3a7713b1edbc 3927 #define DMA_EEI_EEI12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 3928 #define DMA_EEI_EEI12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 3929 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
AnnaBridge 171:3a7713b1edbc 3930 #define DMA_EEI_EEI13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 3931 #define DMA_EEI_EEI13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 3932 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
AnnaBridge 171:3a7713b1edbc 3933 #define DMA_EEI_EEI14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 3934 #define DMA_EEI_EEI14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 3935 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
AnnaBridge 171:3a7713b1edbc 3936 #define DMA_EEI_EEI15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 3937 #define DMA_EEI_EEI15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 3938 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
AnnaBridge 171:3a7713b1edbc 3939
AnnaBridge 171:3a7713b1edbc 3940 /*! @name CEEI - Clear Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 3941 #define DMA_CEEI_CEEI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3942 #define DMA_CEEI_CEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3943 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
AnnaBridge 171:3a7713b1edbc 3944 #define DMA_CEEI_CAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3945 #define DMA_CEEI_CAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3946 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
AnnaBridge 171:3a7713b1edbc 3947 #define DMA_CEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3948 #define DMA_CEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3949 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 3950
AnnaBridge 171:3a7713b1edbc 3951 /*! @name SEEI - Set Enable Error Interrupt Register */
AnnaBridge 171:3a7713b1edbc 3952 #define DMA_SEEI_SEEI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3953 #define DMA_SEEI_SEEI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3954 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
AnnaBridge 171:3a7713b1edbc 3955 #define DMA_SEEI_SAEE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3956 #define DMA_SEEI_SAEE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3957 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
AnnaBridge 171:3a7713b1edbc 3958 #define DMA_SEEI_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3959 #define DMA_SEEI_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3960 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 3961
AnnaBridge 171:3a7713b1edbc 3962 /*! @name CERQ - Clear Enable Request Register */
AnnaBridge 171:3a7713b1edbc 3963 #define DMA_CERQ_CERQ_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3964 #define DMA_CERQ_CERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3965 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
AnnaBridge 171:3a7713b1edbc 3966 #define DMA_CERQ_CAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3967 #define DMA_CERQ_CAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3968 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
AnnaBridge 171:3a7713b1edbc 3969 #define DMA_CERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3970 #define DMA_CERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3971 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 3972
AnnaBridge 171:3a7713b1edbc 3973 /*! @name SERQ - Set Enable Request Register */
AnnaBridge 171:3a7713b1edbc 3974 #define DMA_SERQ_SERQ_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3975 #define DMA_SERQ_SERQ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3976 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
AnnaBridge 171:3a7713b1edbc 3977 #define DMA_SERQ_SAER_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3978 #define DMA_SERQ_SAER_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3979 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
AnnaBridge 171:3a7713b1edbc 3980 #define DMA_SERQ_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3981 #define DMA_SERQ_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3982 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 3983
AnnaBridge 171:3a7713b1edbc 3984 /*! @name CDNE - Clear DONE Status Bit Register */
AnnaBridge 171:3a7713b1edbc 3985 #define DMA_CDNE_CDNE_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3986 #define DMA_CDNE_CDNE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3987 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
AnnaBridge 171:3a7713b1edbc 3988 #define DMA_CDNE_CADN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 3989 #define DMA_CDNE_CADN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 3990 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
AnnaBridge 171:3a7713b1edbc 3991 #define DMA_CDNE_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 3992 #define DMA_CDNE_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 3993 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 3994
AnnaBridge 171:3a7713b1edbc 3995 /*! @name SSRT - Set START Bit Register */
AnnaBridge 171:3a7713b1edbc 3996 #define DMA_SSRT_SSRT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 3997 #define DMA_SSRT_SSRT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 3998 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
AnnaBridge 171:3a7713b1edbc 3999 #define DMA_SSRT_SAST_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4000 #define DMA_SSRT_SAST_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4001 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
AnnaBridge 171:3a7713b1edbc 4002 #define DMA_SSRT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4003 #define DMA_SSRT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4004 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4005
AnnaBridge 171:3a7713b1edbc 4006 /*! @name CERR - Clear Error Register */
AnnaBridge 171:3a7713b1edbc 4007 #define DMA_CERR_CERR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4008 #define DMA_CERR_CERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4009 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
AnnaBridge 171:3a7713b1edbc 4010 #define DMA_CERR_CAEI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4011 #define DMA_CERR_CAEI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4012 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
AnnaBridge 171:3a7713b1edbc 4013 #define DMA_CERR_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4014 #define DMA_CERR_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4015 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4016
AnnaBridge 171:3a7713b1edbc 4017 /*! @name CINT - Clear Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 4018 #define DMA_CINT_CINT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4019 #define DMA_CINT_CINT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4020 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 4021 #define DMA_CINT_CAIR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4022 #define DMA_CINT_CAIR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4023 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
AnnaBridge 171:3a7713b1edbc 4024 #define DMA_CINT_NOP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4025 #define DMA_CINT_NOP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4026 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
AnnaBridge 171:3a7713b1edbc 4027
AnnaBridge 171:3a7713b1edbc 4028 /*! @name INT - Interrupt Request Register */
AnnaBridge 171:3a7713b1edbc 4029 #define DMA_INT_INT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4030 #define DMA_INT_INT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4031 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
AnnaBridge 171:3a7713b1edbc 4032 #define DMA_INT_INT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4033 #define DMA_INT_INT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4034 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
AnnaBridge 171:3a7713b1edbc 4035 #define DMA_INT_INT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4036 #define DMA_INT_INT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4037 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
AnnaBridge 171:3a7713b1edbc 4038 #define DMA_INT_INT3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4039 #define DMA_INT_INT3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4040 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
AnnaBridge 171:3a7713b1edbc 4041 #define DMA_INT_INT4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4042 #define DMA_INT_INT4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4043 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
AnnaBridge 171:3a7713b1edbc 4044 #define DMA_INT_INT5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4045 #define DMA_INT_INT5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4046 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
AnnaBridge 171:3a7713b1edbc 4047 #define DMA_INT_INT6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4048 #define DMA_INT_INT6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4049 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
AnnaBridge 171:3a7713b1edbc 4050 #define DMA_INT_INT7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4051 #define DMA_INT_INT7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4052 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
AnnaBridge 171:3a7713b1edbc 4053 #define DMA_INT_INT8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4054 #define DMA_INT_INT8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4055 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
AnnaBridge 171:3a7713b1edbc 4056 #define DMA_INT_INT9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4057 #define DMA_INT_INT9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4058 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
AnnaBridge 171:3a7713b1edbc 4059 #define DMA_INT_INT10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4060 #define DMA_INT_INT10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4061 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
AnnaBridge 171:3a7713b1edbc 4062 #define DMA_INT_INT11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4063 #define DMA_INT_INT11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4064 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
AnnaBridge 171:3a7713b1edbc 4065 #define DMA_INT_INT12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4066 #define DMA_INT_INT12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4067 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
AnnaBridge 171:3a7713b1edbc 4068 #define DMA_INT_INT13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4069 #define DMA_INT_INT13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4070 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
AnnaBridge 171:3a7713b1edbc 4071 #define DMA_INT_INT14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4072 #define DMA_INT_INT14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4073 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
AnnaBridge 171:3a7713b1edbc 4074 #define DMA_INT_INT15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4075 #define DMA_INT_INT15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4076 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
AnnaBridge 171:3a7713b1edbc 4077
AnnaBridge 171:3a7713b1edbc 4078 /*! @name ERR - Error Register */
AnnaBridge 171:3a7713b1edbc 4079 #define DMA_ERR_ERR0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4080 #define DMA_ERR_ERR0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4081 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
AnnaBridge 171:3a7713b1edbc 4082 #define DMA_ERR_ERR1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4083 #define DMA_ERR_ERR1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4084 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
AnnaBridge 171:3a7713b1edbc 4085 #define DMA_ERR_ERR2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4086 #define DMA_ERR_ERR2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4087 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
AnnaBridge 171:3a7713b1edbc 4088 #define DMA_ERR_ERR3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4089 #define DMA_ERR_ERR3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4090 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
AnnaBridge 171:3a7713b1edbc 4091 #define DMA_ERR_ERR4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4092 #define DMA_ERR_ERR4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4093 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
AnnaBridge 171:3a7713b1edbc 4094 #define DMA_ERR_ERR5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4095 #define DMA_ERR_ERR5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4096 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
AnnaBridge 171:3a7713b1edbc 4097 #define DMA_ERR_ERR6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4098 #define DMA_ERR_ERR6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4099 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
AnnaBridge 171:3a7713b1edbc 4100 #define DMA_ERR_ERR7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4101 #define DMA_ERR_ERR7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4102 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
AnnaBridge 171:3a7713b1edbc 4103 #define DMA_ERR_ERR8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4104 #define DMA_ERR_ERR8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4105 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
AnnaBridge 171:3a7713b1edbc 4106 #define DMA_ERR_ERR9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4107 #define DMA_ERR_ERR9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4108 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
AnnaBridge 171:3a7713b1edbc 4109 #define DMA_ERR_ERR10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4110 #define DMA_ERR_ERR10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4111 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
AnnaBridge 171:3a7713b1edbc 4112 #define DMA_ERR_ERR11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4113 #define DMA_ERR_ERR11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4114 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
AnnaBridge 171:3a7713b1edbc 4115 #define DMA_ERR_ERR12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4116 #define DMA_ERR_ERR12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4117 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
AnnaBridge 171:3a7713b1edbc 4118 #define DMA_ERR_ERR13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4119 #define DMA_ERR_ERR13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4120 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
AnnaBridge 171:3a7713b1edbc 4121 #define DMA_ERR_ERR14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4122 #define DMA_ERR_ERR14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4123 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
AnnaBridge 171:3a7713b1edbc 4124 #define DMA_ERR_ERR15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4125 #define DMA_ERR_ERR15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4126 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
AnnaBridge 171:3a7713b1edbc 4127
AnnaBridge 171:3a7713b1edbc 4128 /*! @name HRS - Hardware Request Status Register */
AnnaBridge 171:3a7713b1edbc 4129 #define DMA_HRS_HRS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4130 #define DMA_HRS_HRS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4131 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
AnnaBridge 171:3a7713b1edbc 4132 #define DMA_HRS_HRS1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4133 #define DMA_HRS_HRS1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4134 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
AnnaBridge 171:3a7713b1edbc 4135 #define DMA_HRS_HRS2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4136 #define DMA_HRS_HRS2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4137 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
AnnaBridge 171:3a7713b1edbc 4138 #define DMA_HRS_HRS3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4139 #define DMA_HRS_HRS3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4140 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
AnnaBridge 171:3a7713b1edbc 4141 #define DMA_HRS_HRS4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4142 #define DMA_HRS_HRS4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4143 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
AnnaBridge 171:3a7713b1edbc 4144 #define DMA_HRS_HRS5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4145 #define DMA_HRS_HRS5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4146 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
AnnaBridge 171:3a7713b1edbc 4147 #define DMA_HRS_HRS6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4148 #define DMA_HRS_HRS6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4149 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
AnnaBridge 171:3a7713b1edbc 4150 #define DMA_HRS_HRS7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4151 #define DMA_HRS_HRS7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4152 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
AnnaBridge 171:3a7713b1edbc 4153 #define DMA_HRS_HRS8_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4154 #define DMA_HRS_HRS8_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4155 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
AnnaBridge 171:3a7713b1edbc 4156 #define DMA_HRS_HRS9_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4157 #define DMA_HRS_HRS9_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4158 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
AnnaBridge 171:3a7713b1edbc 4159 #define DMA_HRS_HRS10_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 4160 #define DMA_HRS_HRS10_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4161 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
AnnaBridge 171:3a7713b1edbc 4162 #define DMA_HRS_HRS11_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 4163 #define DMA_HRS_HRS11_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4164 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
AnnaBridge 171:3a7713b1edbc 4165 #define DMA_HRS_HRS12_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4166 #define DMA_HRS_HRS12_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4167 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
AnnaBridge 171:3a7713b1edbc 4168 #define DMA_HRS_HRS13_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4169 #define DMA_HRS_HRS13_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4170 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
AnnaBridge 171:3a7713b1edbc 4171 #define DMA_HRS_HRS14_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4172 #define DMA_HRS_HRS14_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4173 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
AnnaBridge 171:3a7713b1edbc 4174 #define DMA_HRS_HRS15_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4175 #define DMA_HRS_HRS15_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4176 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
AnnaBridge 171:3a7713b1edbc 4177
AnnaBridge 171:3a7713b1edbc 4178 /*! @name DCHPRI3 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4179 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4180 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4181 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4182 #define DMA_DCHPRI3_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4183 #define DMA_DCHPRI3_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4184 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4185 #define DMA_DCHPRI3_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4186 #define DMA_DCHPRI3_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4187 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4188
AnnaBridge 171:3a7713b1edbc 4189 /*! @name DCHPRI2 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4190 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4191 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4192 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4193 #define DMA_DCHPRI2_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4194 #define DMA_DCHPRI2_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4195 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4196 #define DMA_DCHPRI2_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4197 #define DMA_DCHPRI2_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4198 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4199
AnnaBridge 171:3a7713b1edbc 4200 /*! @name DCHPRI1 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4201 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4202 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4203 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4204 #define DMA_DCHPRI1_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4205 #define DMA_DCHPRI1_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4206 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4207 #define DMA_DCHPRI1_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4208 #define DMA_DCHPRI1_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4209 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4210
AnnaBridge 171:3a7713b1edbc 4211 /*! @name DCHPRI0 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4212 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4213 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4214 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4215 #define DMA_DCHPRI0_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4216 #define DMA_DCHPRI0_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4217 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4218 #define DMA_DCHPRI0_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4219 #define DMA_DCHPRI0_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4220 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4221
AnnaBridge 171:3a7713b1edbc 4222 /*! @name DCHPRI7 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4223 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4224 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4225 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4226 #define DMA_DCHPRI7_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4227 #define DMA_DCHPRI7_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4228 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4229 #define DMA_DCHPRI7_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4230 #define DMA_DCHPRI7_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4231 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4232
AnnaBridge 171:3a7713b1edbc 4233 /*! @name DCHPRI6 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4234 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4235 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4236 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4237 #define DMA_DCHPRI6_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4238 #define DMA_DCHPRI6_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4239 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4240 #define DMA_DCHPRI6_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4241 #define DMA_DCHPRI6_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4242 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4243
AnnaBridge 171:3a7713b1edbc 4244 /*! @name DCHPRI5 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4245 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4246 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4247 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4248 #define DMA_DCHPRI5_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4249 #define DMA_DCHPRI5_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4250 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4251 #define DMA_DCHPRI5_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4252 #define DMA_DCHPRI5_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4253 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4254
AnnaBridge 171:3a7713b1edbc 4255 /*! @name DCHPRI4 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4256 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4257 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4258 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4259 #define DMA_DCHPRI4_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4260 #define DMA_DCHPRI4_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4261 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4262 #define DMA_DCHPRI4_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4263 #define DMA_DCHPRI4_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4264 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4265
AnnaBridge 171:3a7713b1edbc 4266 /*! @name DCHPRI11 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4267 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4268 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4269 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4270 #define DMA_DCHPRI11_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4271 #define DMA_DCHPRI11_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4272 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4273 #define DMA_DCHPRI11_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4274 #define DMA_DCHPRI11_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4275 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4276
AnnaBridge 171:3a7713b1edbc 4277 /*! @name DCHPRI10 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4278 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4279 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4280 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4281 #define DMA_DCHPRI10_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4282 #define DMA_DCHPRI10_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4283 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4284 #define DMA_DCHPRI10_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4285 #define DMA_DCHPRI10_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4286 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4287
AnnaBridge 171:3a7713b1edbc 4288 /*! @name DCHPRI9 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4289 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4290 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4291 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4292 #define DMA_DCHPRI9_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4293 #define DMA_DCHPRI9_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4294 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4295 #define DMA_DCHPRI9_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4296 #define DMA_DCHPRI9_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4297 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4298
AnnaBridge 171:3a7713b1edbc 4299 /*! @name DCHPRI8 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4300 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4301 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4302 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4303 #define DMA_DCHPRI8_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4304 #define DMA_DCHPRI8_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4305 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4306 #define DMA_DCHPRI8_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4307 #define DMA_DCHPRI8_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4308 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4309
AnnaBridge 171:3a7713b1edbc 4310 /*! @name DCHPRI15 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4311 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4312 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4313 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4314 #define DMA_DCHPRI15_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4315 #define DMA_DCHPRI15_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4316 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4317 #define DMA_DCHPRI15_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4318 #define DMA_DCHPRI15_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4319 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4320
AnnaBridge 171:3a7713b1edbc 4321 /*! @name DCHPRI14 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4322 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4323 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4324 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4325 #define DMA_DCHPRI14_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4326 #define DMA_DCHPRI14_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4327 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4328 #define DMA_DCHPRI14_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4329 #define DMA_DCHPRI14_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4330 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4331
AnnaBridge 171:3a7713b1edbc 4332 /*! @name DCHPRI13 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4333 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4334 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4335 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4336 #define DMA_DCHPRI13_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4337 #define DMA_DCHPRI13_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4338 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4339 #define DMA_DCHPRI13_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4340 #define DMA_DCHPRI13_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4341 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4342
AnnaBridge 171:3a7713b1edbc 4343 /*! @name DCHPRI12 - Channel n Priority Register */
AnnaBridge 171:3a7713b1edbc 4344 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 4345 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4346 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
AnnaBridge 171:3a7713b1edbc 4347 #define DMA_DCHPRI12_DPA_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4348 #define DMA_DCHPRI12_DPA_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4349 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
AnnaBridge 171:3a7713b1edbc 4350 #define DMA_DCHPRI12_ECP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4351 #define DMA_DCHPRI12_ECP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4352 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
AnnaBridge 171:3a7713b1edbc 4353
AnnaBridge 171:3a7713b1edbc 4354 /*! @name SADDR - TCD Source Address */
AnnaBridge 171:3a7713b1edbc 4355 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4356 #define DMA_SADDR_SADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4357 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
AnnaBridge 171:3a7713b1edbc 4358
AnnaBridge 171:3a7713b1edbc 4359 /* The count of DMA_SADDR */
AnnaBridge 171:3a7713b1edbc 4360 #define DMA_SADDR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4361
AnnaBridge 171:3a7713b1edbc 4362 /*! @name SOFF - TCD Signed Source Address Offset */
AnnaBridge 171:3a7713b1edbc 4363 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4364 #define DMA_SOFF_SOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4365 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
AnnaBridge 171:3a7713b1edbc 4366
AnnaBridge 171:3a7713b1edbc 4367 /* The count of DMA_SOFF */
AnnaBridge 171:3a7713b1edbc 4368 #define DMA_SOFF_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4369
AnnaBridge 171:3a7713b1edbc 4370 /*! @name ATTR - TCD Transfer Attributes */
AnnaBridge 171:3a7713b1edbc 4371 #define DMA_ATTR_DSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 4372 #define DMA_ATTR_DSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4373 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4374 #define DMA_ATTR_DMOD_MASK (0xF8U)
AnnaBridge 171:3a7713b1edbc 4375 #define DMA_ATTR_DMOD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4376 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
AnnaBridge 171:3a7713b1edbc 4377 #define DMA_ATTR_SSIZE_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 4378 #define DMA_ATTR_SSIZE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4379 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 4380 #define DMA_ATTR_SMOD_MASK (0xF800U)
AnnaBridge 171:3a7713b1edbc 4381 #define DMA_ATTR_SMOD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 4382 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
AnnaBridge 171:3a7713b1edbc 4383
AnnaBridge 171:3a7713b1edbc 4384 /* The count of DMA_ATTR */
AnnaBridge 171:3a7713b1edbc 4385 #define DMA_ATTR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4386
AnnaBridge 171:3a7713b1edbc 4387 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
AnnaBridge 171:3a7713b1edbc 4388 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4389 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4390 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 4391
AnnaBridge 171:3a7713b1edbc 4392 /* The count of DMA_NBYTES_MLNO */
AnnaBridge 171:3a7713b1edbc 4393 #define DMA_NBYTES_MLNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4394
AnnaBridge 171:3a7713b1edbc 4395 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
AnnaBridge 171:3a7713b1edbc 4396 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4397 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4398 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 4399 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4400 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4401 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 4402 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4403 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4404 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 4405
AnnaBridge 171:3a7713b1edbc 4406 /* The count of DMA_NBYTES_MLOFFNO */
AnnaBridge 171:3a7713b1edbc 4407 #define DMA_NBYTES_MLOFFNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4408
AnnaBridge 171:3a7713b1edbc 4409 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
AnnaBridge 171:3a7713b1edbc 4410 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 4411 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4412 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge 171:3a7713b1edbc 4413 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
AnnaBridge 171:3a7713b1edbc 4414 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 4415 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge 171:3a7713b1edbc 4416 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4417 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4418 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 4419 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4420 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4421 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
AnnaBridge 171:3a7713b1edbc 4422
AnnaBridge 171:3a7713b1edbc 4423 /* The count of DMA_NBYTES_MLOFFYES */
AnnaBridge 171:3a7713b1edbc 4424 #define DMA_NBYTES_MLOFFYES_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4425
AnnaBridge 171:3a7713b1edbc 4426 /*! @name SLAST - TCD Last Source Address Adjustment */
AnnaBridge 171:3a7713b1edbc 4427 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4428 #define DMA_SLAST_SLAST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4429 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
AnnaBridge 171:3a7713b1edbc 4430
AnnaBridge 171:3a7713b1edbc 4431 /* The count of DMA_SLAST */
AnnaBridge 171:3a7713b1edbc 4432 #define DMA_SLAST_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4433
AnnaBridge 171:3a7713b1edbc 4434 /*! @name DADDR - TCD Destination Address */
AnnaBridge 171:3a7713b1edbc 4435 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4436 #define DMA_DADDR_DADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4437 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
AnnaBridge 171:3a7713b1edbc 4438
AnnaBridge 171:3a7713b1edbc 4439 /* The count of DMA_DADDR */
AnnaBridge 171:3a7713b1edbc 4440 #define DMA_DADDR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4441
AnnaBridge 171:3a7713b1edbc 4442 /*! @name DOFF - TCD Signed Destination Address Offset */
AnnaBridge 171:3a7713b1edbc 4443 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4444 #define DMA_DOFF_DOFF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4445 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
AnnaBridge 171:3a7713b1edbc 4446
AnnaBridge 171:3a7713b1edbc 4447 /* The count of DMA_DOFF */
AnnaBridge 171:3a7713b1edbc 4448 #define DMA_DOFF_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4449
AnnaBridge 171:3a7713b1edbc 4450 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 4451 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 4452 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4453 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 4454 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4455 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4456 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 4457
AnnaBridge 171:3a7713b1edbc 4458 /* The count of DMA_CITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 4459 #define DMA_CITER_ELINKNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4460
AnnaBridge 171:3a7713b1edbc 4461 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 4462 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 4463 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4464 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge 171:3a7713b1edbc 4465 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
AnnaBridge 171:3a7713b1edbc 4466 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4467 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 4468 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4469 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4470 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 4471
AnnaBridge 171:3a7713b1edbc 4472 /* The count of DMA_CITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 4473 #define DMA_CITER_ELINKYES_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4474
AnnaBridge 171:3a7713b1edbc 4475 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
AnnaBridge 171:3a7713b1edbc 4476 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 4477 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4478 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge 171:3a7713b1edbc 4479
AnnaBridge 171:3a7713b1edbc 4480 /* The count of DMA_DLAST_SGA */
AnnaBridge 171:3a7713b1edbc 4481 #define DMA_DLAST_SGA_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4482
AnnaBridge 171:3a7713b1edbc 4483 /*! @name CSR - TCD Control and Status */
AnnaBridge 171:3a7713b1edbc 4484 #define DMA_CSR_START_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4485 #define DMA_CSR_START_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4486 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
AnnaBridge 171:3a7713b1edbc 4487 #define DMA_CSR_INTMAJOR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4488 #define DMA_CSR_INTMAJOR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4489 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
AnnaBridge 171:3a7713b1edbc 4490 #define DMA_CSR_INTHALF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4491 #define DMA_CSR_INTHALF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4492 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
AnnaBridge 171:3a7713b1edbc 4493 #define DMA_CSR_DREQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4494 #define DMA_CSR_DREQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4495 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
AnnaBridge 171:3a7713b1edbc 4496 #define DMA_CSR_ESG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4497 #define DMA_CSR_ESG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4498 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
AnnaBridge 171:3a7713b1edbc 4499 #define DMA_CSR_MAJORELINK_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4500 #define DMA_CSR_MAJORELINK_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4501 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
AnnaBridge 171:3a7713b1edbc 4502 #define DMA_CSR_ACTIVE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4503 #define DMA_CSR_ACTIVE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4504 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 4505 #define DMA_CSR_DONE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4506 #define DMA_CSR_DONE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4507 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
AnnaBridge 171:3a7713b1edbc 4508 #define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 4509 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4510 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 4511 #define DMA_CSR_BWC_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 4512 #define DMA_CSR_BWC_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4513 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
AnnaBridge 171:3a7713b1edbc 4514
AnnaBridge 171:3a7713b1edbc 4515 /* The count of DMA_CSR */
AnnaBridge 171:3a7713b1edbc 4516 #define DMA_CSR_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4517
AnnaBridge 171:3a7713b1edbc 4518 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 171:3a7713b1edbc 4519 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
AnnaBridge 171:3a7713b1edbc 4520 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4521 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 4522 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4523 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4524 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 4525
AnnaBridge 171:3a7713b1edbc 4526 /* The count of DMA_BITER_ELINKNO */
AnnaBridge 171:3a7713b1edbc 4527 #define DMA_BITER_ELINKNO_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4528
AnnaBridge 171:3a7713b1edbc 4529 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 171:3a7713b1edbc 4530 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
AnnaBridge 171:3a7713b1edbc 4531 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4532 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge 171:3a7713b1edbc 4533 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
AnnaBridge 171:3a7713b1edbc 4534 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4535 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge 171:3a7713b1edbc 4536 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4537 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4538 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
AnnaBridge 171:3a7713b1edbc 4539
AnnaBridge 171:3a7713b1edbc 4540 /* The count of DMA_BITER_ELINKYES */
AnnaBridge 171:3a7713b1edbc 4541 #define DMA_BITER_ELINKYES_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4542
AnnaBridge 171:3a7713b1edbc 4543
AnnaBridge 171:3a7713b1edbc 4544 /*!
AnnaBridge 171:3a7713b1edbc 4545 * @}
AnnaBridge 171:3a7713b1edbc 4546 */ /* end of group DMA_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4547
AnnaBridge 171:3a7713b1edbc 4548
AnnaBridge 171:3a7713b1edbc 4549 /* DMA - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4550 /** Peripheral DMA base address */
AnnaBridge 171:3a7713b1edbc 4551 #define DMA_BASE (0x40008000u)
AnnaBridge 171:3a7713b1edbc 4552 /** Peripheral DMA base pointer */
AnnaBridge 171:3a7713b1edbc 4553 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 171:3a7713b1edbc 4554 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4555 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 171:3a7713b1edbc 4556 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4557 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 171:3a7713b1edbc 4558 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 171:3a7713b1edbc 4559 #define DMA_CHN_IRQS { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
AnnaBridge 171:3a7713b1edbc 4560 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 4561
AnnaBridge 171:3a7713b1edbc 4562 /*!
AnnaBridge 171:3a7713b1edbc 4563 * @}
AnnaBridge 171:3a7713b1edbc 4564 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4565
AnnaBridge 171:3a7713b1edbc 4566
AnnaBridge 171:3a7713b1edbc 4567 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4568 -- DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4569 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4570
AnnaBridge 171:3a7713b1edbc 4571 /*!
AnnaBridge 171:3a7713b1edbc 4572 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4573 * @{
AnnaBridge 171:3a7713b1edbc 4574 */
AnnaBridge 171:3a7713b1edbc 4575
AnnaBridge 171:3a7713b1edbc 4576 /** DMAMUX - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4577 typedef struct {
AnnaBridge 171:3a7713b1edbc 4578 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 171:3a7713b1edbc 4579 } DMAMUX_Type;
AnnaBridge 171:3a7713b1edbc 4580
AnnaBridge 171:3a7713b1edbc 4581 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4582 -- DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 4583 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4584
AnnaBridge 171:3a7713b1edbc 4585 /*!
AnnaBridge 171:3a7713b1edbc 4586 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 171:3a7713b1edbc 4587 * @{
AnnaBridge 171:3a7713b1edbc 4588 */
AnnaBridge 171:3a7713b1edbc 4589
AnnaBridge 171:3a7713b1edbc 4590 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 171:3a7713b1edbc 4591 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 4592 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4593 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 171:3a7713b1edbc 4594 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4595 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4596 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 4597 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4598 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4599 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 171:3a7713b1edbc 4600
AnnaBridge 171:3a7713b1edbc 4601 /* The count of DMAMUX_CHCFG */
AnnaBridge 171:3a7713b1edbc 4602 #define DMAMUX_CHCFG_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 4603
AnnaBridge 171:3a7713b1edbc 4604
AnnaBridge 171:3a7713b1edbc 4605 /*!
AnnaBridge 171:3a7713b1edbc 4606 * @}
AnnaBridge 171:3a7713b1edbc 4607 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 171:3a7713b1edbc 4608
AnnaBridge 171:3a7713b1edbc 4609
AnnaBridge 171:3a7713b1edbc 4610 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 4611 /** Peripheral DMAMUX base address */
AnnaBridge 171:3a7713b1edbc 4612 #define DMAMUX_BASE (0x40021000u)
AnnaBridge 171:3a7713b1edbc 4613 /** Peripheral DMAMUX base pointer */
AnnaBridge 171:3a7713b1edbc 4614 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
AnnaBridge 171:3a7713b1edbc 4615 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 4616 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
AnnaBridge 171:3a7713b1edbc 4617 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 4618 #define DMAMUX_BASE_PTRS { DMAMUX }
AnnaBridge 171:3a7713b1edbc 4619
AnnaBridge 171:3a7713b1edbc 4620 /*!
AnnaBridge 171:3a7713b1edbc 4621 * @}
AnnaBridge 171:3a7713b1edbc 4622 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 4623
AnnaBridge 171:3a7713b1edbc 4624
AnnaBridge 171:3a7713b1edbc 4625 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4626 -- ENET Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4627 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4628
AnnaBridge 171:3a7713b1edbc 4629 /*!
AnnaBridge 171:3a7713b1edbc 4630 * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 4631 * @{
AnnaBridge 171:3a7713b1edbc 4632 */
AnnaBridge 171:3a7713b1edbc 4633
AnnaBridge 171:3a7713b1edbc 4634 /** ENET - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 4635 typedef struct {
AnnaBridge 171:3a7713b1edbc 4636 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 4637 __IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 4638 __IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 4639 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 4640 __IO uint32_t RDAR; /**< Receive Descriptor Active Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 4641 __IO uint32_t TDAR; /**< Transmit Descriptor Active Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 4642 uint8_t RESERVED_2[12];
AnnaBridge 171:3a7713b1edbc 4643 __IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 4644 uint8_t RESERVED_3[24];
AnnaBridge 171:3a7713b1edbc 4645 __IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 4646 __IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 4647 uint8_t RESERVED_4[28];
AnnaBridge 171:3a7713b1edbc 4648 __IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 4649 uint8_t RESERVED_5[28];
AnnaBridge 171:3a7713b1edbc 4650 __IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 4651 uint8_t RESERVED_6[60];
AnnaBridge 171:3a7713b1edbc 4652 __IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 4653 uint8_t RESERVED_7[28];
AnnaBridge 171:3a7713b1edbc 4654 __IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
AnnaBridge 171:3a7713b1edbc 4655 __IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
AnnaBridge 171:3a7713b1edbc 4656 __IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
AnnaBridge 171:3a7713b1edbc 4657 uint8_t RESERVED_8[40];
AnnaBridge 171:3a7713b1edbc 4658 __IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
AnnaBridge 171:3a7713b1edbc 4659 __IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
AnnaBridge 171:3a7713b1edbc 4660 __IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
AnnaBridge 171:3a7713b1edbc 4661 __IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
AnnaBridge 171:3a7713b1edbc 4662 uint8_t RESERVED_9[28];
AnnaBridge 171:3a7713b1edbc 4663 __IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 4664 uint8_t RESERVED_10[56];
AnnaBridge 171:3a7713b1edbc 4665 __IO uint32_t RDSR; /**< Receive Descriptor Ring Start Register, offset: 0x180 */
AnnaBridge 171:3a7713b1edbc 4666 __IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
AnnaBridge 171:3a7713b1edbc 4667 __IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register, offset: 0x188 */
AnnaBridge 171:3a7713b1edbc 4668 uint8_t RESERVED_11[4];
AnnaBridge 171:3a7713b1edbc 4669 __IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
AnnaBridge 171:3a7713b1edbc 4670 __IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
AnnaBridge 171:3a7713b1edbc 4671 __IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
AnnaBridge 171:3a7713b1edbc 4672 __IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
AnnaBridge 171:3a7713b1edbc 4673 __IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
AnnaBridge 171:3a7713b1edbc 4674 __IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
AnnaBridge 171:3a7713b1edbc 4675 __IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
AnnaBridge 171:3a7713b1edbc 4676 __IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
AnnaBridge 171:3a7713b1edbc 4677 __IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
AnnaBridge 171:3a7713b1edbc 4678 uint8_t RESERVED_12[12];
AnnaBridge 171:3a7713b1edbc 4679 __IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
AnnaBridge 171:3a7713b1edbc 4680 __IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
AnnaBridge 171:3a7713b1edbc 4681 uint8_t RESERVED_13[60];
AnnaBridge 171:3a7713b1edbc 4682 __I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
AnnaBridge 171:3a7713b1edbc 4683 __I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
AnnaBridge 171:3a7713b1edbc 4684 __I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
AnnaBridge 171:3a7713b1edbc 4685 __I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
AnnaBridge 171:3a7713b1edbc 4686 __I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
AnnaBridge 171:3a7713b1edbc 4687 __I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
AnnaBridge 171:3a7713b1edbc 4688 __I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
AnnaBridge 171:3a7713b1edbc 4689 __I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
AnnaBridge 171:3a7713b1edbc 4690 __I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
AnnaBridge 171:3a7713b1edbc 4691 __I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
AnnaBridge 171:3a7713b1edbc 4692 __I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
AnnaBridge 171:3a7713b1edbc 4693 __I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
AnnaBridge 171:3a7713b1edbc 4694 __I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
AnnaBridge 171:3a7713b1edbc 4695 __I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
AnnaBridge 171:3a7713b1edbc 4696 __I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
AnnaBridge 171:3a7713b1edbc 4697 __I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
AnnaBridge 171:3a7713b1edbc 4698 __I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
AnnaBridge 171:3a7713b1edbc 4699 uint8_t RESERVED_14[4];
AnnaBridge 171:3a7713b1edbc 4700 __I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
AnnaBridge 171:3a7713b1edbc 4701 __I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
AnnaBridge 171:3a7713b1edbc 4702 __I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
AnnaBridge 171:3a7713b1edbc 4703 __I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
AnnaBridge 171:3a7713b1edbc 4704 __I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
AnnaBridge 171:3a7713b1edbc 4705 __I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
AnnaBridge 171:3a7713b1edbc 4706 __I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
AnnaBridge 171:3a7713b1edbc 4707 __I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
AnnaBridge 171:3a7713b1edbc 4708 uint8_t RESERVED_15[4];
AnnaBridge 171:3a7713b1edbc 4709 __I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
AnnaBridge 171:3a7713b1edbc 4710 __I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
AnnaBridge 171:3a7713b1edbc 4711 uint8_t RESERVED_16[12];
AnnaBridge 171:3a7713b1edbc 4712 __I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
AnnaBridge 171:3a7713b1edbc 4713 __I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
AnnaBridge 171:3a7713b1edbc 4714 __I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
AnnaBridge 171:3a7713b1edbc 4715 __I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
AnnaBridge 171:3a7713b1edbc 4716 __I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
AnnaBridge 171:3a7713b1edbc 4717 __I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
AnnaBridge 171:3a7713b1edbc 4718 __I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
AnnaBridge 171:3a7713b1edbc 4719 __I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
AnnaBridge 171:3a7713b1edbc 4720 uint8_t RESERVED_17[4];
AnnaBridge 171:3a7713b1edbc 4721 __I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
AnnaBridge 171:3a7713b1edbc 4722 __I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
AnnaBridge 171:3a7713b1edbc 4723 __I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
AnnaBridge 171:3a7713b1edbc 4724 __I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
AnnaBridge 171:3a7713b1edbc 4725 __I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
AnnaBridge 171:3a7713b1edbc 4726 __I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
AnnaBridge 171:3a7713b1edbc 4727 __I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
AnnaBridge 171:3a7713b1edbc 4728 __I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
AnnaBridge 171:3a7713b1edbc 4729 __I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
AnnaBridge 171:3a7713b1edbc 4730 __I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
AnnaBridge 171:3a7713b1edbc 4731 __I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
AnnaBridge 171:3a7713b1edbc 4732 __I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
AnnaBridge 171:3a7713b1edbc 4733 __I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
AnnaBridge 171:3a7713b1edbc 4734 __I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
AnnaBridge 171:3a7713b1edbc 4735 __I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
AnnaBridge 171:3a7713b1edbc 4736 uint8_t RESERVED_18[284];
AnnaBridge 171:3a7713b1edbc 4737 __IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
AnnaBridge 171:3a7713b1edbc 4738 __IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
AnnaBridge 171:3a7713b1edbc 4739 __IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
AnnaBridge 171:3a7713b1edbc 4740 __IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
AnnaBridge 171:3a7713b1edbc 4741 __IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
AnnaBridge 171:3a7713b1edbc 4742 __IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
AnnaBridge 171:3a7713b1edbc 4743 __I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
AnnaBridge 171:3a7713b1edbc 4744 uint8_t RESERVED_19[488];
AnnaBridge 171:3a7713b1edbc 4745 __IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
AnnaBridge 171:3a7713b1edbc 4746 struct { /* offset: 0x608, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4747 __IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4748 __IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 4749 } CHANNEL[4];
AnnaBridge 171:3a7713b1edbc 4750 } ENET_Type;
AnnaBridge 171:3a7713b1edbc 4751
AnnaBridge 171:3a7713b1edbc 4752 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 4753 -- ENET Register Masks
AnnaBridge 171:3a7713b1edbc 4754 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 4755
AnnaBridge 171:3a7713b1edbc 4756 /*!
AnnaBridge 171:3a7713b1edbc 4757 * @addtogroup ENET_Register_Masks ENET Register Masks
AnnaBridge 171:3a7713b1edbc 4758 * @{
AnnaBridge 171:3a7713b1edbc 4759 */
AnnaBridge 171:3a7713b1edbc 4760
AnnaBridge 171:3a7713b1edbc 4761 /*! @name EIR - Interrupt Event Register */
AnnaBridge 171:3a7713b1edbc 4762 #define ENET_EIR_TS_TIMER_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4763 #define ENET_EIR_TS_TIMER_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4764 #define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 4765 #define ENET_EIR_TS_AVAIL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4766 #define ENET_EIR_TS_AVAIL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4767 #define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
AnnaBridge 171:3a7713b1edbc 4768 #define ENET_EIR_WAKEUP_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4769 #define ENET_EIR_WAKEUP_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4770 #define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 4771 #define ENET_EIR_PLR_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4772 #define ENET_EIR_PLR_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4773 #define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
AnnaBridge 171:3a7713b1edbc 4774 #define ENET_EIR_UN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4775 #define ENET_EIR_UN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4776 #define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
AnnaBridge 171:3a7713b1edbc 4777 #define ENET_EIR_RL_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4778 #define ENET_EIR_RL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4779 #define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
AnnaBridge 171:3a7713b1edbc 4780 #define ENET_EIR_LC_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4781 #define ENET_EIR_LC_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4782 #define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
AnnaBridge 171:3a7713b1edbc 4783 #define ENET_EIR_EBERR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4784 #define ENET_EIR_EBERR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4785 #define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
AnnaBridge 171:3a7713b1edbc 4786 #define ENET_EIR_MII_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4787 #define ENET_EIR_MII_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4788 #define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
AnnaBridge 171:3a7713b1edbc 4789 #define ENET_EIR_RXB_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4790 #define ENET_EIR_RXB_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4791 #define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
AnnaBridge 171:3a7713b1edbc 4792 #define ENET_EIR_RXF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4793 #define ENET_EIR_RXF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4794 #define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 4795 #define ENET_EIR_TXB_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4796 #define ENET_EIR_TXB_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4797 #define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
AnnaBridge 171:3a7713b1edbc 4798 #define ENET_EIR_TXF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4799 #define ENET_EIR_TXF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4800 #define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 4801 #define ENET_EIR_GRA_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4802 #define ENET_EIR_GRA_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4803 #define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
AnnaBridge 171:3a7713b1edbc 4804 #define ENET_EIR_BABT_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4805 #define ENET_EIR_BABT_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4806 #define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
AnnaBridge 171:3a7713b1edbc 4807 #define ENET_EIR_BABR_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4808 #define ENET_EIR_BABR_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4809 #define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
AnnaBridge 171:3a7713b1edbc 4810
AnnaBridge 171:3a7713b1edbc 4811 /*! @name EIMR - Interrupt Mask Register */
AnnaBridge 171:3a7713b1edbc 4812 #define ENET_EIMR_TS_TIMER_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4813 #define ENET_EIMR_TS_TIMER_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4814 #define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
AnnaBridge 171:3a7713b1edbc 4815 #define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 4816 #define ENET_EIMR_TS_AVAIL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4817 #define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
AnnaBridge 171:3a7713b1edbc 4818 #define ENET_EIMR_WAKEUP_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 4819 #define ENET_EIMR_WAKEUP_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 4820 #define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 4821 #define ENET_EIMR_PLR_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 4822 #define ENET_EIMR_PLR_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4823 #define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
AnnaBridge 171:3a7713b1edbc 4824 #define ENET_EIMR_UN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 4825 #define ENET_EIMR_UN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 4826 #define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
AnnaBridge 171:3a7713b1edbc 4827 #define ENET_EIMR_RL_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 4828 #define ENET_EIMR_RL_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 4829 #define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
AnnaBridge 171:3a7713b1edbc 4830 #define ENET_EIMR_LC_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 4831 #define ENET_EIMR_LC_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 4832 #define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
AnnaBridge 171:3a7713b1edbc 4833 #define ENET_EIMR_EBERR_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 4834 #define ENET_EIMR_EBERR_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 4835 #define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
AnnaBridge 171:3a7713b1edbc 4836 #define ENET_EIMR_MII_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 4837 #define ENET_EIMR_MII_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4838 #define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
AnnaBridge 171:3a7713b1edbc 4839 #define ENET_EIMR_RXB_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4840 #define ENET_EIMR_RXB_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4841 #define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
AnnaBridge 171:3a7713b1edbc 4842 #define ENET_EIMR_RXF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 4843 #define ENET_EIMR_RXF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 4844 #define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 4845 #define ENET_EIMR_TXB_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 4846 #define ENET_EIMR_TXB_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 4847 #define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
AnnaBridge 171:3a7713b1edbc 4848 #define ENET_EIMR_TXF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 4849 #define ENET_EIMR_TXF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 4850 #define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 4851 #define ENET_EIMR_GRA_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 4852 #define ENET_EIMR_GRA_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4853 #define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
AnnaBridge 171:3a7713b1edbc 4854 #define ENET_EIMR_BABT_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4855 #define ENET_EIMR_BABT_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4856 #define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
AnnaBridge 171:3a7713b1edbc 4857 #define ENET_EIMR_BABR_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4858 #define ENET_EIMR_BABR_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4859 #define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
AnnaBridge 171:3a7713b1edbc 4860
AnnaBridge 171:3a7713b1edbc 4861 /*! @name RDAR - Receive Descriptor Active Register */
AnnaBridge 171:3a7713b1edbc 4862 #define ENET_RDAR_RDAR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4863 #define ENET_RDAR_RDAR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4864 #define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
AnnaBridge 171:3a7713b1edbc 4865
AnnaBridge 171:3a7713b1edbc 4866 /*! @name TDAR - Transmit Descriptor Active Register */
AnnaBridge 171:3a7713b1edbc 4867 #define ENET_TDAR_TDAR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 4868 #define ENET_TDAR_TDAR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 4869 #define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
AnnaBridge 171:3a7713b1edbc 4870
AnnaBridge 171:3a7713b1edbc 4871 /*! @name ECR - Ethernet Control Register */
AnnaBridge 171:3a7713b1edbc 4872 #define ENET_ECR_RESET_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4873 #define ENET_ECR_RESET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4874 #define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 4875 #define ENET_ECR_ETHEREN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4876 #define ENET_ECR_ETHEREN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4877 #define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
AnnaBridge 171:3a7713b1edbc 4878 #define ENET_ECR_MAGICEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4879 #define ENET_ECR_MAGICEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4880 #define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
AnnaBridge 171:3a7713b1edbc 4881 #define ENET_ECR_SLEEP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4882 #define ENET_ECR_SLEEP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4883 #define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
AnnaBridge 171:3a7713b1edbc 4884 #define ENET_ECR_EN1588_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4885 #define ENET_ECR_EN1588_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4886 #define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
AnnaBridge 171:3a7713b1edbc 4887 #define ENET_ECR_DBGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 4888 #define ENET_ECR_DBGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 4889 #define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 4890 #define ENET_ECR_STOPEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4891 #define ENET_ECR_STOPEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4892 #define ENET_ECR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 4893 #define ENET_ECR_DBSWP_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4894 #define ENET_ECR_DBSWP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4895 #define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
AnnaBridge 171:3a7713b1edbc 4896
AnnaBridge 171:3a7713b1edbc 4897 /*! @name MMFR - MII Management Frame Register */
AnnaBridge 171:3a7713b1edbc 4898 #define ENET_MMFR_DATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 4899 #define ENET_MMFR_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4900 #define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 4901 #define ENET_MMFR_TA_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 4902 #define ENET_MMFR_TA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4903 #define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
AnnaBridge 171:3a7713b1edbc 4904 #define ENET_MMFR_RA_MASK (0x7C0000U)
AnnaBridge 171:3a7713b1edbc 4905 #define ENET_MMFR_RA_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 4906 #define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
AnnaBridge 171:3a7713b1edbc 4907 #define ENET_MMFR_PA_MASK (0xF800000U)
AnnaBridge 171:3a7713b1edbc 4908 #define ENET_MMFR_PA_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 4909 #define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
AnnaBridge 171:3a7713b1edbc 4910 #define ENET_MMFR_OP_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 4911 #define ENET_MMFR_OP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 4912 #define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
AnnaBridge 171:3a7713b1edbc 4913 #define ENET_MMFR_ST_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 4914 #define ENET_MMFR_ST_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4915 #define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
AnnaBridge 171:3a7713b1edbc 4916
AnnaBridge 171:3a7713b1edbc 4917 /*! @name MSCR - MII Speed Control Register */
AnnaBridge 171:3a7713b1edbc 4918 #define ENET_MSCR_MII_SPEED_MASK (0x7EU)
AnnaBridge 171:3a7713b1edbc 4919 #define ENET_MSCR_MII_SPEED_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4920 #define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
AnnaBridge 171:3a7713b1edbc 4921 #define ENET_MSCR_DIS_PRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 4922 #define ENET_MSCR_DIS_PRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 4923 #define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
AnnaBridge 171:3a7713b1edbc 4924 #define ENET_MSCR_HOLDTIME_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 4925 #define ENET_MSCR_HOLDTIME_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4926 #define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
AnnaBridge 171:3a7713b1edbc 4927
AnnaBridge 171:3a7713b1edbc 4928 /*! @name MIBC - MIB Control Register */
AnnaBridge 171:3a7713b1edbc 4929 #define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 4930 #define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 4931 #define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
AnnaBridge 171:3a7713b1edbc 4932 #define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4933 #define ENET_MIBC_MIB_IDLE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4934 #define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 4935 #define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4936 #define ENET_MIBC_MIB_DIS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4937 #define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 4938
AnnaBridge 171:3a7713b1edbc 4939 /*! @name RCR - Receive Control Register */
AnnaBridge 171:3a7713b1edbc 4940 #define ENET_RCR_LOOP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4941 #define ENET_RCR_LOOP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4942 #define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
AnnaBridge 171:3a7713b1edbc 4943 #define ENET_RCR_DRT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 4944 #define ENET_RCR_DRT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 4945 #define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
AnnaBridge 171:3a7713b1edbc 4946 #define ENET_RCR_MII_MODE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4947 #define ENET_RCR_MII_MODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4948 #define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 4949 #define ENET_RCR_PROM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4950 #define ENET_RCR_PROM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4951 #define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
AnnaBridge 171:3a7713b1edbc 4952 #define ENET_RCR_BC_REJ_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4953 #define ENET_RCR_BC_REJ_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4954 #define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
AnnaBridge 171:3a7713b1edbc 4955 #define ENET_RCR_FCE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 4956 #define ENET_RCR_FCE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 4957 #define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
AnnaBridge 171:3a7713b1edbc 4958 #define ENET_RCR_RMII_MODE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 4959 #define ENET_RCR_RMII_MODE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 4960 #define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
AnnaBridge 171:3a7713b1edbc 4961 #define ENET_RCR_RMII_10T_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 4962 #define ENET_RCR_RMII_10T_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 4963 #define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
AnnaBridge 171:3a7713b1edbc 4964 #define ENET_RCR_PADEN_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 4965 #define ENET_RCR_PADEN_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 4966 #define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
AnnaBridge 171:3a7713b1edbc 4967 #define ENET_RCR_PAUFWD_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 4968 #define ENET_RCR_PAUFWD_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 4969 #define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
AnnaBridge 171:3a7713b1edbc 4970 #define ENET_RCR_CRCFWD_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 4971 #define ENET_RCR_CRCFWD_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 4972 #define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
AnnaBridge 171:3a7713b1edbc 4973 #define ENET_RCR_CFEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 4974 #define ENET_RCR_CFEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 4975 #define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
AnnaBridge 171:3a7713b1edbc 4976 #define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
AnnaBridge 171:3a7713b1edbc 4977 #define ENET_RCR_MAX_FL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 4978 #define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
AnnaBridge 171:3a7713b1edbc 4979 #define ENET_RCR_NLC_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 4980 #define ENET_RCR_NLC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 4981 #define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
AnnaBridge 171:3a7713b1edbc 4982 #define ENET_RCR_GRS_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 4983 #define ENET_RCR_GRS_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 4984 #define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
AnnaBridge 171:3a7713b1edbc 4985
AnnaBridge 171:3a7713b1edbc 4986 /*! @name TCR - Transmit Control Register */
AnnaBridge 171:3a7713b1edbc 4987 #define ENET_TCR_GTS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 4988 #define ENET_TCR_GTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 4989 #define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
AnnaBridge 171:3a7713b1edbc 4990 #define ENET_TCR_FDEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 4991 #define ENET_TCR_FDEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 4992 #define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
AnnaBridge 171:3a7713b1edbc 4993 #define ENET_TCR_TFC_PAUSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 4994 #define ENET_TCR_TFC_PAUSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 4995 #define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
AnnaBridge 171:3a7713b1edbc 4996 #define ENET_TCR_RFC_PAUSE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 4997 #define ENET_TCR_RFC_PAUSE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 4998 #define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
AnnaBridge 171:3a7713b1edbc 4999 #define ENET_TCR_ADDSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 5000 #define ENET_TCR_ADDSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5001 #define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
AnnaBridge 171:3a7713b1edbc 5002 #define ENET_TCR_ADDINS_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5003 #define ENET_TCR_ADDINS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5004 #define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
AnnaBridge 171:3a7713b1edbc 5005 #define ENET_TCR_CRCFWD_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5006 #define ENET_TCR_CRCFWD_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5007 #define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
AnnaBridge 171:3a7713b1edbc 5008
AnnaBridge 171:3a7713b1edbc 5009 /*! @name PALR - Physical Address Lower Register */
AnnaBridge 171:3a7713b1edbc 5010 #define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5011 #define ENET_PALR_PADDR1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5012 #define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 5013
AnnaBridge 171:3a7713b1edbc 5014 /*! @name PAUR - Physical Address Upper Register */
AnnaBridge 171:3a7713b1edbc 5015 #define ENET_PAUR_TYPE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5016 #define ENET_PAUR_TYPE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5017 #define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
AnnaBridge 171:3a7713b1edbc 5018 #define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5019 #define ENET_PAUR_PADDR2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5020 #define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
AnnaBridge 171:3a7713b1edbc 5021
AnnaBridge 171:3a7713b1edbc 5022 /*! @name OPD - Opcode/Pause Duration Register */
AnnaBridge 171:3a7713b1edbc 5023 #define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5024 #define ENET_OPD_PAUSE_DUR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5025 #define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
AnnaBridge 171:3a7713b1edbc 5026 #define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5027 #define ENET_OPD_OPCODE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5028 #define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
AnnaBridge 171:3a7713b1edbc 5029
AnnaBridge 171:3a7713b1edbc 5030 /*! @name IAUR - Descriptor Individual Upper Address Register */
AnnaBridge 171:3a7713b1edbc 5031 #define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5032 #define ENET_IAUR_IADDR1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5033 #define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 5034
AnnaBridge 171:3a7713b1edbc 5035 /*! @name IALR - Descriptor Individual Lower Address Register */
AnnaBridge 171:3a7713b1edbc 5036 #define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5037 #define ENET_IALR_IADDR2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5038 #define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
AnnaBridge 171:3a7713b1edbc 5039
AnnaBridge 171:3a7713b1edbc 5040 /*! @name GAUR - Descriptor Group Upper Address Register */
AnnaBridge 171:3a7713b1edbc 5041 #define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5042 #define ENET_GAUR_GADDR1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5043 #define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 5044
AnnaBridge 171:3a7713b1edbc 5045 /*! @name GALR - Descriptor Group Lower Address Register */
AnnaBridge 171:3a7713b1edbc 5046 #define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5047 #define ENET_GALR_GADDR2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5048 #define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
AnnaBridge 171:3a7713b1edbc 5049
AnnaBridge 171:3a7713b1edbc 5050 /*! @name TFWR - Transmit FIFO Watermark Register */
AnnaBridge 171:3a7713b1edbc 5051 #define ENET_TFWR_TFWR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 5052 #define ENET_TFWR_TFWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5053 #define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
AnnaBridge 171:3a7713b1edbc 5054 #define ENET_TFWR_STRFWD_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5055 #define ENET_TFWR_STRFWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5056 #define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
AnnaBridge 171:3a7713b1edbc 5057
AnnaBridge 171:3a7713b1edbc 5058 /*! @name RDSR - Receive Descriptor Ring Start Register */
AnnaBridge 171:3a7713b1edbc 5059 #define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 5060 #define ENET_RDSR_R_DES_START_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5061 #define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
AnnaBridge 171:3a7713b1edbc 5062
AnnaBridge 171:3a7713b1edbc 5063 /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
AnnaBridge 171:3a7713b1edbc 5064 #define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
AnnaBridge 171:3a7713b1edbc 5065 #define ENET_TDSR_X_DES_START_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5066 #define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
AnnaBridge 171:3a7713b1edbc 5067
AnnaBridge 171:3a7713b1edbc 5068 /*! @name MRBR - Maximum Receive Buffer Size Register */
AnnaBridge 171:3a7713b1edbc 5069 #define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U)
AnnaBridge 171:3a7713b1edbc 5070 #define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5071 #define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 5072
AnnaBridge 171:3a7713b1edbc 5073 /*! @name RSFL - Receive FIFO Section Full Threshold */
AnnaBridge 171:3a7713b1edbc 5074 #define ENET_RSFL_RX_SECTION_FULL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5075 #define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5076 #define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 5077
AnnaBridge 171:3a7713b1edbc 5078 /*! @name RSEM - Receive FIFO Section Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5079 #define ENET_RSEM_RX_SECTION_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5080 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5081 #define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5082 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 5083 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5084 #define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5085
AnnaBridge 171:3a7713b1edbc 5086 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5087 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5088 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5089 #define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5090
AnnaBridge 171:3a7713b1edbc 5091 /*! @name RAFL - Receive FIFO Almost Full Threshold */
AnnaBridge 171:3a7713b1edbc 5092 #define ENET_RAFL_RX_ALMOST_FULL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5093 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5094 #define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 5095
AnnaBridge 171:3a7713b1edbc 5096 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5097 #define ENET_TSEM_TX_SECTION_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5098 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5099 #define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5100
AnnaBridge 171:3a7713b1edbc 5101 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
AnnaBridge 171:3a7713b1edbc 5102 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5103 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5104 #define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
AnnaBridge 171:3a7713b1edbc 5105
AnnaBridge 171:3a7713b1edbc 5106 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
AnnaBridge 171:3a7713b1edbc 5107 #define ENET_TAFL_TX_ALMOST_FULL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5108 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5109 #define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
AnnaBridge 171:3a7713b1edbc 5110
AnnaBridge 171:3a7713b1edbc 5111 /*! @name TIPG - Transmit Inter-Packet Gap */
AnnaBridge 171:3a7713b1edbc 5112 #define ENET_TIPG_IPG_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 5113 #define ENET_TIPG_IPG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5114 #define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
AnnaBridge 171:3a7713b1edbc 5115
AnnaBridge 171:3a7713b1edbc 5116 /*! @name FTRL - Frame Truncation Length */
AnnaBridge 171:3a7713b1edbc 5117 #define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
AnnaBridge 171:3a7713b1edbc 5118 #define ENET_FTRL_TRUNC_FL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5119 #define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
AnnaBridge 171:3a7713b1edbc 5120
AnnaBridge 171:3a7713b1edbc 5121 /*! @name TACC - Transmit Accelerator Function Configuration */
AnnaBridge 171:3a7713b1edbc 5122 #define ENET_TACC_SHIFT16_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5123 #define ENET_TACC_SHIFT16_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5124 #define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
AnnaBridge 171:3a7713b1edbc 5125 #define ENET_TACC_IPCHK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5126 #define ENET_TACC_IPCHK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5127 #define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
AnnaBridge 171:3a7713b1edbc 5128 #define ENET_TACC_PROCHK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5129 #define ENET_TACC_PROCHK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5130 #define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
AnnaBridge 171:3a7713b1edbc 5131
AnnaBridge 171:3a7713b1edbc 5132 /*! @name RACC - Receive Accelerator Function Configuration */
AnnaBridge 171:3a7713b1edbc 5133 #define ENET_RACC_PADREM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5134 #define ENET_RACC_PADREM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5135 #define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
AnnaBridge 171:3a7713b1edbc 5136 #define ENET_RACC_IPDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5137 #define ENET_RACC_IPDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5138 #define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5139 #define ENET_RACC_PRODIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5140 #define ENET_RACC_PRODIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5141 #define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
AnnaBridge 171:3a7713b1edbc 5142 #define ENET_RACC_LINEDIS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5143 #define ENET_RACC_LINEDIS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5144 #define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
AnnaBridge 171:3a7713b1edbc 5145 #define ENET_RACC_SHIFT16_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5146 #define ENET_RACC_SHIFT16_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5147 #define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
AnnaBridge 171:3a7713b1edbc 5148
AnnaBridge 171:3a7713b1edbc 5149 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5150 #define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5151 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5152 #define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5153
AnnaBridge 171:3a7713b1edbc 5154 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5155 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5156 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5157 #define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5158
AnnaBridge 171:3a7713b1edbc 5159 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5160 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5161 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5162 #define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5163
AnnaBridge 171:3a7713b1edbc 5164 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5165 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5166 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5167 #define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5168
AnnaBridge 171:3a7713b1edbc 5169 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5170 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5171 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5172 #define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5173
AnnaBridge 171:3a7713b1edbc 5174 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5175 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5176 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5177 #define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5178
AnnaBridge 171:3a7713b1edbc 5179 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5180 #define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5181 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5182 #define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5183
AnnaBridge 171:3a7713b1edbc 5184 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5185 #define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5186 #define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5187 #define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5188
AnnaBridge 171:3a7713b1edbc 5189 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5190 #define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5191 #define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5192 #define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5193
AnnaBridge 171:3a7713b1edbc 5194 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5195 #define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5196 #define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5197 #define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5198
AnnaBridge 171:3a7713b1edbc 5199 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5200 #define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5201 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5202 #define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5203
AnnaBridge 171:3a7713b1edbc 5204 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5205 #define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5206 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5207 #define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5208
AnnaBridge 171:3a7713b1edbc 5209 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5210 #define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5211 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5212 #define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5213
AnnaBridge 171:3a7713b1edbc 5214 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5215 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5216 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5217 #define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5218
AnnaBridge 171:3a7713b1edbc 5219 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5220 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5221 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5222 #define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5223
AnnaBridge 171:3a7713b1edbc 5224 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
AnnaBridge 171:3a7713b1edbc 5225 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5226 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5227 #define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
AnnaBridge 171:3a7713b1edbc 5228
AnnaBridge 171:3a7713b1edbc 5229 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5230 #define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5231 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5232 #define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
AnnaBridge 171:3a7713b1edbc 5233
AnnaBridge 171:3a7713b1edbc 5234 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
AnnaBridge 171:3a7713b1edbc 5235 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5236 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5237 #define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5238
AnnaBridge 171:3a7713b1edbc 5239 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
AnnaBridge 171:3a7713b1edbc 5240 #define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5241 #define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5242 #define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5243
AnnaBridge 171:3a7713b1edbc 5244 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
AnnaBridge 171:3a7713b1edbc 5245 #define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5246 #define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5247 #define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5248
AnnaBridge 171:3a7713b1edbc 5249 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
AnnaBridge 171:3a7713b1edbc 5250 #define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5251 #define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5252 #define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5253
AnnaBridge 171:3a7713b1edbc 5254 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
AnnaBridge 171:3a7713b1edbc 5255 #define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5256 #define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5257 #define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5258
AnnaBridge 171:3a7713b1edbc 5259 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
AnnaBridge 171:3a7713b1edbc 5260 #define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5261 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5262 #define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5263
AnnaBridge 171:3a7713b1edbc 5264 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
AnnaBridge 171:3a7713b1edbc 5265 #define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5266 #define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5267 #define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5268
AnnaBridge 171:3a7713b1edbc 5269 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5270 #define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5271 #define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5272 #define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5273
AnnaBridge 171:3a7713b1edbc 5274 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
AnnaBridge 171:3a7713b1edbc 5275 #define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5276 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5277 #define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5278
AnnaBridge 171:3a7713b1edbc 5279 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5280 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5281 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5282 #define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5283
AnnaBridge 171:3a7713b1edbc 5284 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5285 #define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5286 #define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5287 #define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5288
AnnaBridge 171:3a7713b1edbc 5289 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5290 #define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5291 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5292 #define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5293
AnnaBridge 171:3a7713b1edbc 5294 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5295 #define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5296 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5297 #define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5298
AnnaBridge 171:3a7713b1edbc 5299 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5300 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5301 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5302 #define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5303
AnnaBridge 171:3a7713b1edbc 5304 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5305 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5306 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5307 #define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5308
AnnaBridge 171:3a7713b1edbc 5309 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5310 #define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5311 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5312 #define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5313
AnnaBridge 171:3a7713b1edbc 5314 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5315 #define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5316 #define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5317 #define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5318
AnnaBridge 171:3a7713b1edbc 5319 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
AnnaBridge 171:3a7713b1edbc 5320 #define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5321 #define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5322 #define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5323
AnnaBridge 171:3a7713b1edbc 5324 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5325 #define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5326 #define ENET_RMON_R_P64_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5327 #define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5328
AnnaBridge 171:3a7713b1edbc 5329 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5330 #define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5331 #define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5332 #define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5333
AnnaBridge 171:3a7713b1edbc 5334 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5335 #define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5336 #define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5337 #define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5338
AnnaBridge 171:3a7713b1edbc 5339 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5340 #define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5341 #define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5342 #define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5343
AnnaBridge 171:3a7713b1edbc 5344 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5345 #define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5346 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5347 #define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5348
AnnaBridge 171:3a7713b1edbc 5349 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5350 #define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5351 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5352 #define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5353
AnnaBridge 171:3a7713b1edbc 5354 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
AnnaBridge 171:3a7713b1edbc 5355 #define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5356 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5357 #define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5358
AnnaBridge 171:3a7713b1edbc 5359 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
AnnaBridge 171:3a7713b1edbc 5360 #define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5361 #define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5362 #define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5363
AnnaBridge 171:3a7713b1edbc 5364 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
AnnaBridge 171:3a7713b1edbc 5365 #define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5366 #define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5367 #define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5368
AnnaBridge 171:3a7713b1edbc 5369 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
AnnaBridge 171:3a7713b1edbc 5370 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5371 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5372 #define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5373
AnnaBridge 171:3a7713b1edbc 5374 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5375 #define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5376 #define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5377 #define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5378
AnnaBridge 171:3a7713b1edbc 5379 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5380 #define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5381 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5382 #define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5383
AnnaBridge 171:3a7713b1edbc 5384 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
AnnaBridge 171:3a7713b1edbc 5385 #define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5386 #define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5387 #define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5388
AnnaBridge 171:3a7713b1edbc 5389 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
AnnaBridge 171:3a7713b1edbc 5390 #define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 5391 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5392 #define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5393
AnnaBridge 171:3a7713b1edbc 5394 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
AnnaBridge 171:3a7713b1edbc 5395 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5396 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5397 #define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 5398
AnnaBridge 171:3a7713b1edbc 5399 /*! @name ATCR - Adjustable Timer Control Register */
AnnaBridge 171:3a7713b1edbc 5400 #define ENET_ATCR_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5401 #define ENET_ATCR_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5402 #define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
AnnaBridge 171:3a7713b1edbc 5403 #define ENET_ATCR_OFFEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5404 #define ENET_ATCR_OFFEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5405 #define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
AnnaBridge 171:3a7713b1edbc 5406 #define ENET_ATCR_OFFRST_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5407 #define ENET_ATCR_OFFRST_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5408 #define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
AnnaBridge 171:3a7713b1edbc 5409 #define ENET_ATCR_PEREN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5410 #define ENET_ATCR_PEREN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5411 #define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
AnnaBridge 171:3a7713b1edbc 5412 #define ENET_ATCR_PINPER_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5413 #define ENET_ATCR_PINPER_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5414 #define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
AnnaBridge 171:3a7713b1edbc 5415 #define ENET_ATCR_RESTART_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5416 #define ENET_ATCR_RESTART_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5417 #define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
AnnaBridge 171:3a7713b1edbc 5418 #define ENET_ATCR_CAPTURE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 5419 #define ENET_ATCR_CAPTURE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 5420 #define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
AnnaBridge 171:3a7713b1edbc 5421 #define ENET_ATCR_SLAVE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 5422 #define ENET_ATCR_SLAVE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 5423 #define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
AnnaBridge 171:3a7713b1edbc 5424
AnnaBridge 171:3a7713b1edbc 5425 /*! @name ATVR - Timer Value Register */
AnnaBridge 171:3a7713b1edbc 5426 #define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5427 #define ENET_ATVR_ATIME_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5428 #define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
AnnaBridge 171:3a7713b1edbc 5429
AnnaBridge 171:3a7713b1edbc 5430 /*! @name ATOFF - Timer Offset Register */
AnnaBridge 171:3a7713b1edbc 5431 #define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5432 #define ENET_ATOFF_OFFSET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5433 #define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
AnnaBridge 171:3a7713b1edbc 5434
AnnaBridge 171:3a7713b1edbc 5435 /*! @name ATPER - Timer Period Register */
AnnaBridge 171:3a7713b1edbc 5436 #define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5437 #define ENET_ATPER_PERIOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5438 #define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
AnnaBridge 171:3a7713b1edbc 5439
AnnaBridge 171:3a7713b1edbc 5440 /*! @name ATCOR - Timer Correction Register */
AnnaBridge 171:3a7713b1edbc 5441 #define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5442 #define ENET_ATCOR_COR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5443 #define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
AnnaBridge 171:3a7713b1edbc 5444
AnnaBridge 171:3a7713b1edbc 5445 /*! @name ATINC - Time-Stamping Clock Period Register */
AnnaBridge 171:3a7713b1edbc 5446 #define ENET_ATINC_INC_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 5447 #define ENET_ATINC_INC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5448 #define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
AnnaBridge 171:3a7713b1edbc 5449 #define ENET_ATINC_INC_CORR_MASK (0x7F00U)
AnnaBridge 171:3a7713b1edbc 5450 #define ENET_ATINC_INC_CORR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5451 #define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
AnnaBridge 171:3a7713b1edbc 5452
AnnaBridge 171:3a7713b1edbc 5453 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
AnnaBridge 171:3a7713b1edbc 5454 #define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5455 #define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5456 #define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
AnnaBridge 171:3a7713b1edbc 5457
AnnaBridge 171:3a7713b1edbc 5458 /*! @name TGSR - Timer Global Status Register */
AnnaBridge 171:3a7713b1edbc 5459 #define ENET_TGSR_TF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5460 #define ENET_TGSR_TF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5461 #define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
AnnaBridge 171:3a7713b1edbc 5462 #define ENET_TGSR_TF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5463 #define ENET_TGSR_TF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5464 #define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
AnnaBridge 171:3a7713b1edbc 5465 #define ENET_TGSR_TF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5466 #define ENET_TGSR_TF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5467 #define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
AnnaBridge 171:3a7713b1edbc 5468 #define ENET_TGSR_TF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5469 #define ENET_TGSR_TF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5470 #define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
AnnaBridge 171:3a7713b1edbc 5471
AnnaBridge 171:3a7713b1edbc 5472 /*! @name TCSR - Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 5473 #define ENET_TCSR_TDRE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5474 #define ENET_TCSR_TDRE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5475 #define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 5476 #define ENET_TCSR_TMODE_MASK (0x3CU)
AnnaBridge 171:3a7713b1edbc 5477 #define ENET_TCSR_TMODE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5478 #define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
AnnaBridge 171:3a7713b1edbc 5479 #define ENET_TCSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 5480 #define ENET_TCSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5481 #define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 5482 #define ENET_TCSR_TF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 5483 #define ENET_TCSR_TF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 5484 #define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
AnnaBridge 171:3a7713b1edbc 5485
AnnaBridge 171:3a7713b1edbc 5486 /* The count of ENET_TCSR */
AnnaBridge 171:3a7713b1edbc 5487 #define ENET_TCSR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5488
AnnaBridge 171:3a7713b1edbc 5489 /*! @name TCCR - Timer Compare Capture Register */
AnnaBridge 171:3a7713b1edbc 5490 #define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5491 #define ENET_TCCR_TCC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5492 #define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
AnnaBridge 171:3a7713b1edbc 5493
AnnaBridge 171:3a7713b1edbc 5494 /* The count of ENET_TCCR */
AnnaBridge 171:3a7713b1edbc 5495 #define ENET_TCCR_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5496
AnnaBridge 171:3a7713b1edbc 5497
AnnaBridge 171:3a7713b1edbc 5498 /*!
AnnaBridge 171:3a7713b1edbc 5499 * @}
AnnaBridge 171:3a7713b1edbc 5500 */ /* end of group ENET_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5501
AnnaBridge 171:3a7713b1edbc 5502
AnnaBridge 171:3a7713b1edbc 5503 /* ENET - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5504 /** Peripheral ENET base address */
AnnaBridge 171:3a7713b1edbc 5505 #define ENET_BASE (0x400C0000u)
AnnaBridge 171:3a7713b1edbc 5506 /** Peripheral ENET base pointer */
AnnaBridge 171:3a7713b1edbc 5507 #define ENET ((ENET_Type *)ENET_BASE)
AnnaBridge 171:3a7713b1edbc 5508 /** Array initializer of ENET peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5509 #define ENET_BASE_ADDRS { ENET_BASE }
AnnaBridge 171:3a7713b1edbc 5510 /** Array initializer of ENET peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5511 #define ENET_BASE_PTRS { ENET }
AnnaBridge 171:3a7713b1edbc 5512 /** Interrupt vectors for the ENET peripheral type */
AnnaBridge 171:3a7713b1edbc 5513 #define ENET_Transmit_IRQS { ENET_Transmit_IRQn }
AnnaBridge 171:3a7713b1edbc 5514 #define ENET_Receive_IRQS { ENET_Receive_IRQn }
AnnaBridge 171:3a7713b1edbc 5515 #define ENET_Error_IRQS { ENET_Error_IRQn }
AnnaBridge 171:3a7713b1edbc 5516 #define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn }
AnnaBridge 171:3a7713b1edbc 5517
AnnaBridge 171:3a7713b1edbc 5518 /*!
AnnaBridge 171:3a7713b1edbc 5519 * @}
AnnaBridge 171:3a7713b1edbc 5520 */ /* end of group ENET_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5521
AnnaBridge 171:3a7713b1edbc 5522
AnnaBridge 171:3a7713b1edbc 5523 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5524 -- EWM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5525 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5526
AnnaBridge 171:3a7713b1edbc 5527 /*!
AnnaBridge 171:3a7713b1edbc 5528 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5529 * @{
AnnaBridge 171:3a7713b1edbc 5530 */
AnnaBridge 171:3a7713b1edbc 5531
AnnaBridge 171:3a7713b1edbc 5532 /** EWM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5533 typedef struct {
AnnaBridge 171:3a7713b1edbc 5534 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5535 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5536 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5537 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 5538 } EWM_Type;
AnnaBridge 171:3a7713b1edbc 5539
AnnaBridge 171:3a7713b1edbc 5540 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5541 -- EWM Register Masks
AnnaBridge 171:3a7713b1edbc 5542 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5543
AnnaBridge 171:3a7713b1edbc 5544 /*!
AnnaBridge 171:3a7713b1edbc 5545 * @addtogroup EWM_Register_Masks EWM Register Masks
AnnaBridge 171:3a7713b1edbc 5546 * @{
AnnaBridge 171:3a7713b1edbc 5547 */
AnnaBridge 171:3a7713b1edbc 5548
AnnaBridge 171:3a7713b1edbc 5549 /*! @name CTRL - Control Register */
AnnaBridge 171:3a7713b1edbc 5550 #define EWM_CTRL_EWMEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5551 #define EWM_CTRL_EWMEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5552 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
AnnaBridge 171:3a7713b1edbc 5553 #define EWM_CTRL_ASSIN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5554 #define EWM_CTRL_ASSIN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5555 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
AnnaBridge 171:3a7713b1edbc 5556 #define EWM_CTRL_INEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5557 #define EWM_CTRL_INEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5558 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
AnnaBridge 171:3a7713b1edbc 5559 #define EWM_CTRL_INTEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5560 #define EWM_CTRL_INTEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5561 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
AnnaBridge 171:3a7713b1edbc 5562
AnnaBridge 171:3a7713b1edbc 5563 /*! @name SERV - Service Register */
AnnaBridge 171:3a7713b1edbc 5564 #define EWM_SERV_SERVICE_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5565 #define EWM_SERV_SERVICE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5566 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
AnnaBridge 171:3a7713b1edbc 5567
AnnaBridge 171:3a7713b1edbc 5568 /*! @name CMPL - Compare Low Register */
AnnaBridge 171:3a7713b1edbc 5569 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5570 #define EWM_CMPL_COMPAREL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5571 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
AnnaBridge 171:3a7713b1edbc 5572
AnnaBridge 171:3a7713b1edbc 5573 /*! @name CMPH - Compare High Register */
AnnaBridge 171:3a7713b1edbc 5574 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 5575 #define EWM_CMPH_COMPAREH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5576 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
AnnaBridge 171:3a7713b1edbc 5577
AnnaBridge 171:3a7713b1edbc 5578
AnnaBridge 171:3a7713b1edbc 5579 /*!
AnnaBridge 171:3a7713b1edbc 5580 * @}
AnnaBridge 171:3a7713b1edbc 5581 */ /* end of group EWM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5582
AnnaBridge 171:3a7713b1edbc 5583
AnnaBridge 171:3a7713b1edbc 5584 /* EWM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5585 /** Peripheral EWM base address */
AnnaBridge 171:3a7713b1edbc 5586 #define EWM_BASE (0x40061000u)
AnnaBridge 171:3a7713b1edbc 5587 /** Peripheral EWM base pointer */
AnnaBridge 171:3a7713b1edbc 5588 #define EWM ((EWM_Type *)EWM_BASE)
AnnaBridge 171:3a7713b1edbc 5589 /** Array initializer of EWM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5590 #define EWM_BASE_ADDRS { EWM_BASE }
AnnaBridge 171:3a7713b1edbc 5591 /** Array initializer of EWM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5592 #define EWM_BASE_PTRS { EWM }
AnnaBridge 171:3a7713b1edbc 5593 /** Interrupt vectors for the EWM peripheral type */
AnnaBridge 171:3a7713b1edbc 5594 #define EWM_IRQS { WDOG_EWM_IRQn }
AnnaBridge 171:3a7713b1edbc 5595
AnnaBridge 171:3a7713b1edbc 5596 /*!
AnnaBridge 171:3a7713b1edbc 5597 * @}
AnnaBridge 171:3a7713b1edbc 5598 */ /* end of group EWM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5599
AnnaBridge 171:3a7713b1edbc 5600
AnnaBridge 171:3a7713b1edbc 5601 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5602 -- FB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5603 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5604
AnnaBridge 171:3a7713b1edbc 5605 /*!
AnnaBridge 171:3a7713b1edbc 5606 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5607 * @{
AnnaBridge 171:3a7713b1edbc 5608 */
AnnaBridge 171:3a7713b1edbc 5609
AnnaBridge 171:3a7713b1edbc 5610 /** FB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5611 typedef struct {
AnnaBridge 171:3a7713b1edbc 5612 struct { /* offset: 0x0, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 5613 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 5614 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 5615 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
AnnaBridge 171:3a7713b1edbc 5616 } CS[6];
AnnaBridge 171:3a7713b1edbc 5617 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 5618 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 5619 } FB_Type;
AnnaBridge 171:3a7713b1edbc 5620
AnnaBridge 171:3a7713b1edbc 5621 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5622 -- FB Register Masks
AnnaBridge 171:3a7713b1edbc 5623 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5624
AnnaBridge 171:3a7713b1edbc 5625 /*!
AnnaBridge 171:3a7713b1edbc 5626 * @addtogroup FB_Register_Masks FB Register Masks
AnnaBridge 171:3a7713b1edbc 5627 * @{
AnnaBridge 171:3a7713b1edbc 5628 */
AnnaBridge 171:3a7713b1edbc 5629
AnnaBridge 171:3a7713b1edbc 5630 /*! @name CSAR - Chip Select Address Register */
AnnaBridge 171:3a7713b1edbc 5631 #define FB_CSAR_BA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5632 #define FB_CSAR_BA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5633 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
AnnaBridge 171:3a7713b1edbc 5634
AnnaBridge 171:3a7713b1edbc 5635 /* The count of FB_CSAR */
AnnaBridge 171:3a7713b1edbc 5636 #define FB_CSAR_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 5637
AnnaBridge 171:3a7713b1edbc 5638 /*! @name CSMR - Chip Select Mask Register */
AnnaBridge 171:3a7713b1edbc 5639 #define FB_CSMR_V_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5640 #define FB_CSMR_V_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5641 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
AnnaBridge 171:3a7713b1edbc 5642 #define FB_CSMR_WP_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5643 #define FB_CSMR_WP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5644 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
AnnaBridge 171:3a7713b1edbc 5645 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 5646 #define FB_CSMR_BAM_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5647 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
AnnaBridge 171:3a7713b1edbc 5648
AnnaBridge 171:3a7713b1edbc 5649 /* The count of FB_CSMR */
AnnaBridge 171:3a7713b1edbc 5650 #define FB_CSMR_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 5651
AnnaBridge 171:3a7713b1edbc 5652 /*! @name CSCR - Chip Select Control Register */
AnnaBridge 171:3a7713b1edbc 5653 #define FB_CSCR_BSTW_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5654 #define FB_CSCR_BSTW_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5655 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
AnnaBridge 171:3a7713b1edbc 5656 #define FB_CSCR_BSTR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5657 #define FB_CSCR_BSTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5658 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
AnnaBridge 171:3a7713b1edbc 5659 #define FB_CSCR_BEM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 5660 #define FB_CSCR_BEM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5661 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
AnnaBridge 171:3a7713b1edbc 5662 #define FB_CSCR_PS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 5663 #define FB_CSCR_PS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5664 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 5665 #define FB_CSCR_AA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 5666 #define FB_CSCR_AA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5667 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
AnnaBridge 171:3a7713b1edbc 5668 #define FB_CSCR_BLS_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 5669 #define FB_CSCR_BLS_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 5670 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
AnnaBridge 171:3a7713b1edbc 5671 #define FB_CSCR_WS_MASK (0xFC00U)
AnnaBridge 171:3a7713b1edbc 5672 #define FB_CSCR_WS_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 5673 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
AnnaBridge 171:3a7713b1edbc 5674 #define FB_CSCR_WRAH_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 5675 #define FB_CSCR_WRAH_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5676 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
AnnaBridge 171:3a7713b1edbc 5677 #define FB_CSCR_RDAH_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 5678 #define FB_CSCR_RDAH_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5679 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
AnnaBridge 171:3a7713b1edbc 5680 #define FB_CSCR_ASET_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 5681 #define FB_CSCR_ASET_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5682 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
AnnaBridge 171:3a7713b1edbc 5683 #define FB_CSCR_EXTS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 5684 #define FB_CSCR_EXTS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 5685 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
AnnaBridge 171:3a7713b1edbc 5686 #define FB_CSCR_SWSEN_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 5687 #define FB_CSCR_SWSEN_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5688 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
AnnaBridge 171:3a7713b1edbc 5689 #define FB_CSCR_SWS_MASK (0xFC000000U)
AnnaBridge 171:3a7713b1edbc 5690 #define FB_CSCR_SWS_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 5691 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
AnnaBridge 171:3a7713b1edbc 5692
AnnaBridge 171:3a7713b1edbc 5693 /* The count of FB_CSCR */
AnnaBridge 171:3a7713b1edbc 5694 #define FB_CSCR_COUNT (6U)
AnnaBridge 171:3a7713b1edbc 5695
AnnaBridge 171:3a7713b1edbc 5696 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
AnnaBridge 171:3a7713b1edbc 5697 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 5698 #define FB_CSPMCR_GROUP5_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5699 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
AnnaBridge 171:3a7713b1edbc 5700 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 5701 #define FB_CSPMCR_GROUP4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5702 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
AnnaBridge 171:3a7713b1edbc 5703 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 5704 #define FB_CSPMCR_GROUP3_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5705 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
AnnaBridge 171:3a7713b1edbc 5706 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 5707 #define FB_CSPMCR_GROUP2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5708 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
AnnaBridge 171:3a7713b1edbc 5709 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 5710 #define FB_CSPMCR_GROUP1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5711 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
AnnaBridge 171:3a7713b1edbc 5712
AnnaBridge 171:3a7713b1edbc 5713
AnnaBridge 171:3a7713b1edbc 5714 /*!
AnnaBridge 171:3a7713b1edbc 5715 * @}
AnnaBridge 171:3a7713b1edbc 5716 */ /* end of group FB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5717
AnnaBridge 171:3a7713b1edbc 5718
AnnaBridge 171:3a7713b1edbc 5719 /* FB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5720 /** Peripheral FB base address */
AnnaBridge 171:3a7713b1edbc 5721 #define FB_BASE (0x4000C000u)
AnnaBridge 171:3a7713b1edbc 5722 /** Peripheral FB base pointer */
AnnaBridge 171:3a7713b1edbc 5723 #define FB ((FB_Type *)FB_BASE)
AnnaBridge 171:3a7713b1edbc 5724 /** Array initializer of FB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5725 #define FB_BASE_ADDRS { FB_BASE }
AnnaBridge 171:3a7713b1edbc 5726 /** Array initializer of FB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5727 #define FB_BASE_PTRS { FB }
AnnaBridge 171:3a7713b1edbc 5728
AnnaBridge 171:3a7713b1edbc 5729 /*!
AnnaBridge 171:3a7713b1edbc 5730 * @}
AnnaBridge 171:3a7713b1edbc 5731 */ /* end of group FB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5732
AnnaBridge 171:3a7713b1edbc 5733
AnnaBridge 171:3a7713b1edbc 5734 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5735 -- FMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5736 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5737
AnnaBridge 171:3a7713b1edbc 5738 /*!
AnnaBridge 171:3a7713b1edbc 5739 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5740 * @{
AnnaBridge 171:3a7713b1edbc 5741 */
AnnaBridge 171:3a7713b1edbc 5742
AnnaBridge 171:3a7713b1edbc 5743 /** FMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5744 typedef struct {
AnnaBridge 171:3a7713b1edbc 5745 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5746 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5747 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5748 uint8_t RESERVED_0[244];
AnnaBridge 171:3a7713b1edbc 5749 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5750 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5751 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5752 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 5753 uint8_t RESERVED_1[192];
AnnaBridge 171:3a7713b1edbc 5754 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
AnnaBridge 171:3a7713b1edbc 5755 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
AnnaBridge 171:3a7713b1edbc 5756 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
AnnaBridge 171:3a7713b1edbc 5757 } SET[4][4];
AnnaBridge 171:3a7713b1edbc 5758 } FMC_Type;
AnnaBridge 171:3a7713b1edbc 5759
AnnaBridge 171:3a7713b1edbc 5760 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5761 -- FMC Register Masks
AnnaBridge 171:3a7713b1edbc 5762 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5763
AnnaBridge 171:3a7713b1edbc 5764 /*!
AnnaBridge 171:3a7713b1edbc 5765 * @addtogroup FMC_Register_Masks FMC Register Masks
AnnaBridge 171:3a7713b1edbc 5766 * @{
AnnaBridge 171:3a7713b1edbc 5767 */
AnnaBridge 171:3a7713b1edbc 5768
AnnaBridge 171:3a7713b1edbc 5769 /*! @name PFAPR - Flash Access Protection Register */
AnnaBridge 171:3a7713b1edbc 5770 #define FMC_PFAPR_M0AP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 5771 #define FMC_PFAPR_M0AP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5772 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
AnnaBridge 171:3a7713b1edbc 5773 #define FMC_PFAPR_M1AP_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 5774 #define FMC_PFAPR_M1AP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5775 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
AnnaBridge 171:3a7713b1edbc 5776 #define FMC_PFAPR_M2AP_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 5777 #define FMC_PFAPR_M2AP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5778 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
AnnaBridge 171:3a7713b1edbc 5779 #define FMC_PFAPR_M3AP_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 5780 #define FMC_PFAPR_M3AP_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 5781 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
AnnaBridge 171:3a7713b1edbc 5782 #define FMC_PFAPR_M4AP_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 5783 #define FMC_PFAPR_M4AP_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 5784 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
AnnaBridge 171:3a7713b1edbc 5785 #define FMC_PFAPR_M5AP_MASK (0xC00U)
AnnaBridge 171:3a7713b1edbc 5786 #define FMC_PFAPR_M5AP_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 5787 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
AnnaBridge 171:3a7713b1edbc 5788 #define FMC_PFAPR_M6AP_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 5789 #define FMC_PFAPR_M6AP_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 5790 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
AnnaBridge 171:3a7713b1edbc 5791 #define FMC_PFAPR_M7AP_MASK (0xC000U)
AnnaBridge 171:3a7713b1edbc 5792 #define FMC_PFAPR_M7AP_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 5793 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
AnnaBridge 171:3a7713b1edbc 5794 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 5795 #define FMC_PFAPR_M0PFD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 5796 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5797 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 5798 #define FMC_PFAPR_M1PFD_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5799 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5800 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 5801 #define FMC_PFAPR_M2PFD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 5802 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5803 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 5804 #define FMC_PFAPR_M3PFD_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 5805 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5806 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 5807 #define FMC_PFAPR_M4PFD_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5808 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5809 #define FMC_PFAPR_M5PFD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 5810 #define FMC_PFAPR_M5PFD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 5811 #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5812 #define FMC_PFAPR_M6PFD_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 5813 #define FMC_PFAPR_M6PFD_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 5814 #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5815 #define FMC_PFAPR_M7PFD_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 5816 #define FMC_PFAPR_M7PFD_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 5817 #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
AnnaBridge 171:3a7713b1edbc 5818
AnnaBridge 171:3a7713b1edbc 5819 /*! @name PFB0CR - Flash Bank 0 Control Register */
AnnaBridge 171:3a7713b1edbc 5820 #define FMC_PFB0CR_B0SEBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5821 #define FMC_PFB0CR_B0SEBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5822 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
AnnaBridge 171:3a7713b1edbc 5823 #define FMC_PFB0CR_B0IPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5824 #define FMC_PFB0CR_B0IPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5825 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
AnnaBridge 171:3a7713b1edbc 5826 #define FMC_PFB0CR_B0DPE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5827 #define FMC_PFB0CR_B0DPE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5828 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
AnnaBridge 171:3a7713b1edbc 5829 #define FMC_PFB0CR_B0ICE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5830 #define FMC_PFB0CR_B0ICE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5831 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
AnnaBridge 171:3a7713b1edbc 5832 #define FMC_PFB0CR_B0DCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5833 #define FMC_PFB0CR_B0DCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5834 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
AnnaBridge 171:3a7713b1edbc 5835 #define FMC_PFB0CR_CRC_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 5836 #define FMC_PFB0CR_CRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5837 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 5838 #define FMC_PFB0CR_B0MW_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 5839 #define FMC_PFB0CR_B0MW_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5840 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
AnnaBridge 171:3a7713b1edbc 5841 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 5842 #define FMC_PFB0CR_S_B_INV_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 5843 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
AnnaBridge 171:3a7713b1edbc 5844 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 5845 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 5846 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
AnnaBridge 171:3a7713b1edbc 5847 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 5848 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 5849 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
AnnaBridge 171:3a7713b1edbc 5850 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 5851 #define FMC_PFB0CR_B0RWSC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5852 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
AnnaBridge 171:3a7713b1edbc 5853
AnnaBridge 171:3a7713b1edbc 5854 /*! @name PFB1CR - Flash Bank 1 Control Register */
AnnaBridge 171:3a7713b1edbc 5855 #define FMC_PFB1CR_B1SEBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5856 #define FMC_PFB1CR_B1SEBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5857 #define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
AnnaBridge 171:3a7713b1edbc 5858 #define FMC_PFB1CR_B1IPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 5859 #define FMC_PFB1CR_B1IPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 5860 #define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
AnnaBridge 171:3a7713b1edbc 5861 #define FMC_PFB1CR_B1DPE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 5862 #define FMC_PFB1CR_B1DPE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 5863 #define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
AnnaBridge 171:3a7713b1edbc 5864 #define FMC_PFB1CR_B1ICE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 5865 #define FMC_PFB1CR_B1ICE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 5866 #define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
AnnaBridge 171:3a7713b1edbc 5867 #define FMC_PFB1CR_B1DCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 5868 #define FMC_PFB1CR_B1DCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 5869 #define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
AnnaBridge 171:3a7713b1edbc 5870 #define FMC_PFB1CR_B1MW_MASK (0x60000U)
AnnaBridge 171:3a7713b1edbc 5871 #define FMC_PFB1CR_B1MW_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 5872 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
AnnaBridge 171:3a7713b1edbc 5873 #define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 5874 #define FMC_PFB1CR_B1RWSC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 5875 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
AnnaBridge 171:3a7713b1edbc 5876
AnnaBridge 171:3a7713b1edbc 5877 /*! @name TAGVDW0S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 5878 #define FMC_TAGVDW0S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5879 #define FMC_TAGVDW0S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5880 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 5881 #define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
AnnaBridge 171:3a7713b1edbc 5882 #define FMC_TAGVDW0S_tag_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5883 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 5884
AnnaBridge 171:3a7713b1edbc 5885 /* The count of FMC_TAGVDW0S */
AnnaBridge 171:3a7713b1edbc 5886 #define FMC_TAGVDW0S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5887
AnnaBridge 171:3a7713b1edbc 5888 /*! @name TAGVDW1S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 5889 #define FMC_TAGVDW1S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5890 #define FMC_TAGVDW1S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5891 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 5892 #define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
AnnaBridge 171:3a7713b1edbc 5893 #define FMC_TAGVDW1S_tag_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5894 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 5895
AnnaBridge 171:3a7713b1edbc 5896 /* The count of FMC_TAGVDW1S */
AnnaBridge 171:3a7713b1edbc 5897 #define FMC_TAGVDW1S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5898
AnnaBridge 171:3a7713b1edbc 5899 /*! @name TAGVDW2S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 5900 #define FMC_TAGVDW2S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5901 #define FMC_TAGVDW2S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5902 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 5903 #define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
AnnaBridge 171:3a7713b1edbc 5904 #define FMC_TAGVDW2S_tag_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5905 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 5906
AnnaBridge 171:3a7713b1edbc 5907 /* The count of FMC_TAGVDW2S */
AnnaBridge 171:3a7713b1edbc 5908 #define FMC_TAGVDW2S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5909
AnnaBridge 171:3a7713b1edbc 5910 /*! @name TAGVDW3S - Cache Tag Storage */
AnnaBridge 171:3a7713b1edbc 5911 #define FMC_TAGVDW3S_valid_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 5912 #define FMC_TAGVDW3S_valid_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5913 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
AnnaBridge 171:3a7713b1edbc 5914 #define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
AnnaBridge 171:3a7713b1edbc 5915 #define FMC_TAGVDW3S_tag_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 5916 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
AnnaBridge 171:3a7713b1edbc 5917
AnnaBridge 171:3a7713b1edbc 5918 /* The count of FMC_TAGVDW3S */
AnnaBridge 171:3a7713b1edbc 5919 #define FMC_TAGVDW3S_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5920
AnnaBridge 171:3a7713b1edbc 5921 /*! @name DATA_U - Cache Data Storage (upper word) */
AnnaBridge 171:3a7713b1edbc 5922 #define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5923 #define FMC_DATA_U_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5924 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
AnnaBridge 171:3a7713b1edbc 5925
AnnaBridge 171:3a7713b1edbc 5926 /* The count of FMC_DATA_U */
AnnaBridge 171:3a7713b1edbc 5927 #define FMC_DATA_U_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5928
AnnaBridge 171:3a7713b1edbc 5929 /* The count of FMC_DATA_U */
AnnaBridge 171:3a7713b1edbc 5930 #define FMC_DATA_U_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 5931
AnnaBridge 171:3a7713b1edbc 5932 /*! @name DATA_L - Cache Data Storage (lower word) */
AnnaBridge 171:3a7713b1edbc 5933 #define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 5934 #define FMC_DATA_L_data_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 5935 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
AnnaBridge 171:3a7713b1edbc 5936
AnnaBridge 171:3a7713b1edbc 5937 /* The count of FMC_DATA_L */
AnnaBridge 171:3a7713b1edbc 5938 #define FMC_DATA_L_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 5939
AnnaBridge 171:3a7713b1edbc 5940 /* The count of FMC_DATA_L */
AnnaBridge 171:3a7713b1edbc 5941 #define FMC_DATA_L_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 5942
AnnaBridge 171:3a7713b1edbc 5943
AnnaBridge 171:3a7713b1edbc 5944 /*!
AnnaBridge 171:3a7713b1edbc 5945 * @}
AnnaBridge 171:3a7713b1edbc 5946 */ /* end of group FMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 5947
AnnaBridge 171:3a7713b1edbc 5948
AnnaBridge 171:3a7713b1edbc 5949 /* FMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 5950 /** Peripheral FMC base address */
AnnaBridge 171:3a7713b1edbc 5951 #define FMC_BASE (0x4001F000u)
AnnaBridge 171:3a7713b1edbc 5952 /** Peripheral FMC base pointer */
AnnaBridge 171:3a7713b1edbc 5953 #define FMC ((FMC_Type *)FMC_BASE)
AnnaBridge 171:3a7713b1edbc 5954 /** Array initializer of FMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 5955 #define FMC_BASE_ADDRS { FMC_BASE }
AnnaBridge 171:3a7713b1edbc 5956 /** Array initializer of FMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 5957 #define FMC_BASE_PTRS { FMC }
AnnaBridge 171:3a7713b1edbc 5958
AnnaBridge 171:3a7713b1edbc 5959 /*!
AnnaBridge 171:3a7713b1edbc 5960 * @}
AnnaBridge 171:3a7713b1edbc 5961 */ /* end of group FMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 5962
AnnaBridge 171:3a7713b1edbc 5963
AnnaBridge 171:3a7713b1edbc 5964 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 5965 -- FTFE Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5966 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 5967
AnnaBridge 171:3a7713b1edbc 5968 /*!
AnnaBridge 171:3a7713b1edbc 5969 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 5970 * @{
AnnaBridge 171:3a7713b1edbc 5971 */
AnnaBridge 171:3a7713b1edbc 5972
AnnaBridge 171:3a7713b1edbc 5973 /** FTFE - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 5974 typedef struct {
AnnaBridge 171:3a7713b1edbc 5975 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 5976 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 5977 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 5978 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 5979 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 5980 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 5981 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 5982 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 5983 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 5984 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 5985 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 5986 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 5987 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 5988 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 5989 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 5990 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 5991 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 5992 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 5993 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 5994 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 5995 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 5996 __IO uint8_t FEPROT; /**< EEPROM Protection Register, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 5997 __IO uint8_t FDPROT; /**< Data Flash Protection Register, offset: 0x17 */
AnnaBridge 171:3a7713b1edbc 5998 } FTFE_Type;
AnnaBridge 171:3a7713b1edbc 5999
AnnaBridge 171:3a7713b1edbc 6000 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6001 -- FTFE Register Masks
AnnaBridge 171:3a7713b1edbc 6002 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6003
AnnaBridge 171:3a7713b1edbc 6004 /*!
AnnaBridge 171:3a7713b1edbc 6005 * @addtogroup FTFE_Register_Masks FTFE Register Masks
AnnaBridge 171:3a7713b1edbc 6006 * @{
AnnaBridge 171:3a7713b1edbc 6007 */
AnnaBridge 171:3a7713b1edbc 6008
AnnaBridge 171:3a7713b1edbc 6009 /*! @name FSTAT - Flash Status Register */
AnnaBridge 171:3a7713b1edbc 6010 #define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6011 #define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6012 #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
AnnaBridge 171:3a7713b1edbc 6013 #define FTFE_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6014 #define FTFE_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6015 #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
AnnaBridge 171:3a7713b1edbc 6016 #define FTFE_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6017 #define FTFE_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6018 #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
AnnaBridge 171:3a7713b1edbc 6019 #define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6020 #define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6021 #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
AnnaBridge 171:3a7713b1edbc 6022 #define FTFE_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6023 #define FTFE_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6024 #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
AnnaBridge 171:3a7713b1edbc 6025
AnnaBridge 171:3a7713b1edbc 6026 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 171:3a7713b1edbc 6027 #define FTFE_FCNFG_EEERDY_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6028 #define FTFE_FCNFG_EEERDY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6029 #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
AnnaBridge 171:3a7713b1edbc 6030 #define FTFE_FCNFG_RAMRDY_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6031 #define FTFE_FCNFG_RAMRDY_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6032 #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
AnnaBridge 171:3a7713b1edbc 6033 #define FTFE_FCNFG_PFLSH_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6034 #define FTFE_FCNFG_PFLSH_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6035 #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 6036 #define FTFE_FCNFG_SWAP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6037 #define FTFE_FCNFG_SWAP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6038 #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
AnnaBridge 171:3a7713b1edbc 6039 #define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6040 #define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6041 #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
AnnaBridge 171:3a7713b1edbc 6042 #define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6043 #define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6044 #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
AnnaBridge 171:3a7713b1edbc 6045 #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6046 #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6047 #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
AnnaBridge 171:3a7713b1edbc 6048 #define FTFE_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6049 #define FTFE_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6050 #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
AnnaBridge 171:3a7713b1edbc 6051
AnnaBridge 171:3a7713b1edbc 6052 /*! @name FSEC - Flash Security Register */
AnnaBridge 171:3a7713b1edbc 6053 #define FTFE_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 6054 #define FTFE_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6055 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 6056 #define FTFE_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 6057 #define FTFE_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6058 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 6059 #define FTFE_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 6060 #define FTFE_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6061 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 6062 #define FTFE_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6063 #define FTFE_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6064 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 6065
AnnaBridge 171:3a7713b1edbc 6066 /*! @name FOPT - Flash Option Register */
AnnaBridge 171:3a7713b1edbc 6067 #define FTFE_FOPT_OPT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6068 #define FTFE_FOPT_OPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6069 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
AnnaBridge 171:3a7713b1edbc 6070
AnnaBridge 171:3a7713b1edbc 6071 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6072 #define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6073 #define FTFE_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6074 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6075
AnnaBridge 171:3a7713b1edbc 6076 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6077 #define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6078 #define FTFE_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6079 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6080
AnnaBridge 171:3a7713b1edbc 6081 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6082 #define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6083 #define FTFE_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6084 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6085
AnnaBridge 171:3a7713b1edbc 6086 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6087 #define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6088 #define FTFE_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6089 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6090
AnnaBridge 171:3a7713b1edbc 6091 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6092 #define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6093 #define FTFE_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6094 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6095
AnnaBridge 171:3a7713b1edbc 6096 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6097 #define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6098 #define FTFE_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6099 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6100
AnnaBridge 171:3a7713b1edbc 6101 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6102 #define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6103 #define FTFE_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6104 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6105
AnnaBridge 171:3a7713b1edbc 6106 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6107 #define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6108 #define FTFE_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6109 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6110
AnnaBridge 171:3a7713b1edbc 6111 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6112 #define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6113 #define FTFE_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6114 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6115
AnnaBridge 171:3a7713b1edbc 6116 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6117 #define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6118 #define FTFE_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6119 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6120
AnnaBridge 171:3a7713b1edbc 6121 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6122 #define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6123 #define FTFE_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6124 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6125
AnnaBridge 171:3a7713b1edbc 6126 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 171:3a7713b1edbc 6127 #define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6128 #define FTFE_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6129 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
AnnaBridge 171:3a7713b1edbc 6130
AnnaBridge 171:3a7713b1edbc 6131 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6132 #define FTFE_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6133 #define FTFE_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6134 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6135
AnnaBridge 171:3a7713b1edbc 6136 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6137 #define FTFE_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6138 #define FTFE_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6139 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6140
AnnaBridge 171:3a7713b1edbc 6141 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6142 #define FTFE_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6143 #define FTFE_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6144 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6145
AnnaBridge 171:3a7713b1edbc 6146 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 171:3a7713b1edbc 6147 #define FTFE_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6148 #define FTFE_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6149 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 6150
AnnaBridge 171:3a7713b1edbc 6151 /*! @name FEPROT - EEPROM Protection Register */
AnnaBridge 171:3a7713b1edbc 6152 #define FTFE_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6153 #define FTFE_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6154 #define FTFE_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
AnnaBridge 171:3a7713b1edbc 6155
AnnaBridge 171:3a7713b1edbc 6156 /*! @name FDPROT - Data Flash Protection Register */
AnnaBridge 171:3a7713b1edbc 6157 #define FTFE_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 6158 #define FTFE_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6159 #define FTFE_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
AnnaBridge 171:3a7713b1edbc 6160
AnnaBridge 171:3a7713b1edbc 6161
AnnaBridge 171:3a7713b1edbc 6162 /*!
AnnaBridge 171:3a7713b1edbc 6163 * @}
AnnaBridge 171:3a7713b1edbc 6164 */ /* end of group FTFE_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6165
AnnaBridge 171:3a7713b1edbc 6166
AnnaBridge 171:3a7713b1edbc 6167 /* FTFE - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6168 /** Peripheral FTFE base address */
AnnaBridge 171:3a7713b1edbc 6169 #define FTFE_BASE (0x40020000u)
AnnaBridge 171:3a7713b1edbc 6170 /** Peripheral FTFE base pointer */
AnnaBridge 171:3a7713b1edbc 6171 #define FTFE ((FTFE_Type *)FTFE_BASE)
AnnaBridge 171:3a7713b1edbc 6172 /** Array initializer of FTFE peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6173 #define FTFE_BASE_ADDRS { FTFE_BASE }
AnnaBridge 171:3a7713b1edbc 6174 /** Array initializer of FTFE peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6175 #define FTFE_BASE_PTRS { FTFE }
AnnaBridge 171:3a7713b1edbc 6176 /** Interrupt vectors for the FTFE peripheral type */
AnnaBridge 171:3a7713b1edbc 6177 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
AnnaBridge 171:3a7713b1edbc 6178 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
AnnaBridge 171:3a7713b1edbc 6179
AnnaBridge 171:3a7713b1edbc 6180 /*!
AnnaBridge 171:3a7713b1edbc 6181 * @}
AnnaBridge 171:3a7713b1edbc 6182 */ /* end of group FTFE_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6183
AnnaBridge 171:3a7713b1edbc 6184
AnnaBridge 171:3a7713b1edbc 6185 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6186 -- FTM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6187 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6188
AnnaBridge 171:3a7713b1edbc 6189 /*!
AnnaBridge 171:3a7713b1edbc 6190 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6191 * @{
AnnaBridge 171:3a7713b1edbc 6192 */
AnnaBridge 171:3a7713b1edbc 6193
AnnaBridge 171:3a7713b1edbc 6194 /** FTM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6195 typedef struct {
AnnaBridge 171:3a7713b1edbc 6196 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6197 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6198 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6199 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 6200 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 6201 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 6202 } CONTROLS[8];
AnnaBridge 171:3a7713b1edbc 6203 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
AnnaBridge 171:3a7713b1edbc 6204 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 6205 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 6206 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 6207 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
AnnaBridge 171:3a7713b1edbc 6208 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 6209 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
AnnaBridge 171:3a7713b1edbc 6210 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
AnnaBridge 171:3a7713b1edbc 6211 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
AnnaBridge 171:3a7713b1edbc 6212 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
AnnaBridge 171:3a7713b1edbc 6213 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
AnnaBridge 171:3a7713b1edbc 6214 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
AnnaBridge 171:3a7713b1edbc 6215 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 6216 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 6217 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 6218 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 6219 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 6220 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 6221 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 6222 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 6223 } FTM_Type;
AnnaBridge 171:3a7713b1edbc 6224
AnnaBridge 171:3a7713b1edbc 6225 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6226 -- FTM Register Masks
AnnaBridge 171:3a7713b1edbc 6227 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6228
AnnaBridge 171:3a7713b1edbc 6229 /*!
AnnaBridge 171:3a7713b1edbc 6230 * @addtogroup FTM_Register_Masks FTM Register Masks
AnnaBridge 171:3a7713b1edbc 6231 * @{
AnnaBridge 171:3a7713b1edbc 6232 */
AnnaBridge 171:3a7713b1edbc 6233
AnnaBridge 171:3a7713b1edbc 6234 /*! @name SC - Status And Control */
AnnaBridge 171:3a7713b1edbc 6235 #define FTM_SC_PS_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 6236 #define FTM_SC_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6237 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
AnnaBridge 171:3a7713b1edbc 6238 #define FTM_SC_CLKS_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 6239 #define FTM_SC_CLKS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6240 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 6241 #define FTM_SC_CPWMS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6242 #define FTM_SC_CPWMS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6243 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
AnnaBridge 171:3a7713b1edbc 6244 #define FTM_SC_TOIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6245 #define FTM_SC_TOIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6246 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 6247 #define FTM_SC_TOF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6248 #define FTM_SC_TOF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6249 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 6250
AnnaBridge 171:3a7713b1edbc 6251 /*! @name CNT - Counter */
AnnaBridge 171:3a7713b1edbc 6252 #define FTM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6253 #define FTM_CNT_COUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6254 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
AnnaBridge 171:3a7713b1edbc 6255
AnnaBridge 171:3a7713b1edbc 6256 /*! @name MOD - Modulo */
AnnaBridge 171:3a7713b1edbc 6257 #define FTM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6258 #define FTM_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6259 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 6260
AnnaBridge 171:3a7713b1edbc 6261 /*! @name CnSC - Channel (n) Status And Control */
AnnaBridge 171:3a7713b1edbc 6262 #define FTM_CnSC_DMA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6263 #define FTM_CnSC_DMA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6264 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 6265 #define FTM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6266 #define FTM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6267 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
AnnaBridge 171:3a7713b1edbc 6268 #define FTM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6269 #define FTM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6270 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
AnnaBridge 171:3a7713b1edbc 6271 #define FTM_CnSC_MSA_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6272 #define FTM_CnSC_MSA_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6273 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
AnnaBridge 171:3a7713b1edbc 6274 #define FTM_CnSC_MSB_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6275 #define FTM_CnSC_MSB_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6276 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
AnnaBridge 171:3a7713b1edbc 6277 #define FTM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6278 #define FTM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6279 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
AnnaBridge 171:3a7713b1edbc 6280 #define FTM_CnSC_CHF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6281 #define FTM_CnSC_CHF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6282 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
AnnaBridge 171:3a7713b1edbc 6283
AnnaBridge 171:3a7713b1edbc 6284 /* The count of FTM_CnSC */
AnnaBridge 171:3a7713b1edbc 6285 #define FTM_CnSC_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 6286
AnnaBridge 171:3a7713b1edbc 6287 /*! @name CnV - Channel (n) Value */
AnnaBridge 171:3a7713b1edbc 6288 #define FTM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6289 #define FTM_CnV_VAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6290 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
AnnaBridge 171:3a7713b1edbc 6291
AnnaBridge 171:3a7713b1edbc 6292 /* The count of FTM_CnV */
AnnaBridge 171:3a7713b1edbc 6293 #define FTM_CnV_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 6294
AnnaBridge 171:3a7713b1edbc 6295 /*! @name CNTIN - Counter Initial Value */
AnnaBridge 171:3a7713b1edbc 6296 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 6297 #define FTM_CNTIN_INIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6298 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 6299
AnnaBridge 171:3a7713b1edbc 6300 /*! @name STATUS - Capture And Compare Status */
AnnaBridge 171:3a7713b1edbc 6301 #define FTM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6302 #define FTM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6303 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
AnnaBridge 171:3a7713b1edbc 6304 #define FTM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6305 #define FTM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6306 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
AnnaBridge 171:3a7713b1edbc 6307 #define FTM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6308 #define FTM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6309 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
AnnaBridge 171:3a7713b1edbc 6310 #define FTM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6311 #define FTM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6312 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
AnnaBridge 171:3a7713b1edbc 6313 #define FTM_STATUS_CH4F_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6314 #define FTM_STATUS_CH4F_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6315 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
AnnaBridge 171:3a7713b1edbc 6316 #define FTM_STATUS_CH5F_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6317 #define FTM_STATUS_CH5F_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6318 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
AnnaBridge 171:3a7713b1edbc 6319 #define FTM_STATUS_CH6F_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6320 #define FTM_STATUS_CH6F_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6321 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
AnnaBridge 171:3a7713b1edbc 6322 #define FTM_STATUS_CH7F_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6323 #define FTM_STATUS_CH7F_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6324 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
AnnaBridge 171:3a7713b1edbc 6325
AnnaBridge 171:3a7713b1edbc 6326 /*! @name MODE - Features Mode Selection */
AnnaBridge 171:3a7713b1edbc 6327 #define FTM_MODE_FTMEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6328 #define FTM_MODE_FTMEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6329 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
AnnaBridge 171:3a7713b1edbc 6330 #define FTM_MODE_INIT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6331 #define FTM_MODE_INIT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6332 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 6333 #define FTM_MODE_WPDIS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6334 #define FTM_MODE_WPDIS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6335 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
AnnaBridge 171:3a7713b1edbc 6336 #define FTM_MODE_PWMSYNC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6337 #define FTM_MODE_PWMSYNC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6338 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 6339 #define FTM_MODE_CAPTEST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6340 #define FTM_MODE_CAPTEST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6341 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
AnnaBridge 171:3a7713b1edbc 6342 #define FTM_MODE_FAULTM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 6343 #define FTM_MODE_FAULTM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6344 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
AnnaBridge 171:3a7713b1edbc 6345 #define FTM_MODE_FAULTIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6346 #define FTM_MODE_FAULTIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6347 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
AnnaBridge 171:3a7713b1edbc 6348
AnnaBridge 171:3a7713b1edbc 6349 /*! @name SYNC - Synchronization */
AnnaBridge 171:3a7713b1edbc 6350 #define FTM_SYNC_CNTMIN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6351 #define FTM_SYNC_CNTMIN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6352 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
AnnaBridge 171:3a7713b1edbc 6353 #define FTM_SYNC_CNTMAX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6354 #define FTM_SYNC_CNTMAX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6355 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
AnnaBridge 171:3a7713b1edbc 6356 #define FTM_SYNC_REINIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6357 #define FTM_SYNC_REINIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6358 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
AnnaBridge 171:3a7713b1edbc 6359 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6360 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6361 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
AnnaBridge 171:3a7713b1edbc 6362 #define FTM_SYNC_TRIG0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6363 #define FTM_SYNC_TRIG0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6364 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
AnnaBridge 171:3a7713b1edbc 6365 #define FTM_SYNC_TRIG1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6366 #define FTM_SYNC_TRIG1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6367 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
AnnaBridge 171:3a7713b1edbc 6368 #define FTM_SYNC_TRIG2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6369 #define FTM_SYNC_TRIG2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6370 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
AnnaBridge 171:3a7713b1edbc 6371 #define FTM_SYNC_SWSYNC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6372 #define FTM_SYNC_SWSYNC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6373 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
AnnaBridge 171:3a7713b1edbc 6374
AnnaBridge 171:3a7713b1edbc 6375 /*! @name OUTINIT - Initial State For Channels Output */
AnnaBridge 171:3a7713b1edbc 6376 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6377 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6378 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
AnnaBridge 171:3a7713b1edbc 6379 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6380 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6381 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
AnnaBridge 171:3a7713b1edbc 6382 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6383 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6384 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
AnnaBridge 171:3a7713b1edbc 6385 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6386 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6387 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
AnnaBridge 171:3a7713b1edbc 6388 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6389 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6390 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
AnnaBridge 171:3a7713b1edbc 6391 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6392 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6393 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
AnnaBridge 171:3a7713b1edbc 6394 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6395 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6396 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
AnnaBridge 171:3a7713b1edbc 6397 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6398 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6399 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
AnnaBridge 171:3a7713b1edbc 6400
AnnaBridge 171:3a7713b1edbc 6401 /*! @name OUTMASK - Output Mask */
AnnaBridge 171:3a7713b1edbc 6402 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6403 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6404 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
AnnaBridge 171:3a7713b1edbc 6405 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6406 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6407 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
AnnaBridge 171:3a7713b1edbc 6408 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6409 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6410 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
AnnaBridge 171:3a7713b1edbc 6411 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6412 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6413 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
AnnaBridge 171:3a7713b1edbc 6414 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6415 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6416 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
AnnaBridge 171:3a7713b1edbc 6417 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6418 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6419 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
AnnaBridge 171:3a7713b1edbc 6420 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6421 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6422 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
AnnaBridge 171:3a7713b1edbc 6423 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6424 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6425 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
AnnaBridge 171:3a7713b1edbc 6426
AnnaBridge 171:3a7713b1edbc 6427 /*! @name COMBINE - Function For Linked Channels */
AnnaBridge 171:3a7713b1edbc 6428 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6429 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6430 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
AnnaBridge 171:3a7713b1edbc 6431 #define FTM_COMBINE_COMP0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6432 #define FTM_COMBINE_COMP0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6433 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
AnnaBridge 171:3a7713b1edbc 6434 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6435 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6436 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
AnnaBridge 171:3a7713b1edbc 6437 #define FTM_COMBINE_DECAP0_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6438 #define FTM_COMBINE_DECAP0_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6439 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
AnnaBridge 171:3a7713b1edbc 6440 #define FTM_COMBINE_DTEN0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6441 #define FTM_COMBINE_DTEN0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6442 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 6443 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6444 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6445 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
AnnaBridge 171:3a7713b1edbc 6446 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6447 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6448 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 6449 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6450 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6451 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
AnnaBridge 171:3a7713b1edbc 6452 #define FTM_COMBINE_COMP1_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6453 #define FTM_COMBINE_COMP1_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6454 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
AnnaBridge 171:3a7713b1edbc 6455 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6456 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6457 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
AnnaBridge 171:3a7713b1edbc 6458 #define FTM_COMBINE_DECAP1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6459 #define FTM_COMBINE_DECAP1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6460 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
AnnaBridge 171:3a7713b1edbc 6461 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6462 #define FTM_COMBINE_DTEN1_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6463 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
AnnaBridge 171:3a7713b1edbc 6464 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6465 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6466 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
AnnaBridge 171:3a7713b1edbc 6467 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 6468 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 6469 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
AnnaBridge 171:3a7713b1edbc 6470 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 6471 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6472 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
AnnaBridge 171:3a7713b1edbc 6473 #define FTM_COMBINE_COMP2_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 6474 #define FTM_COMBINE_COMP2_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6475 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
AnnaBridge 171:3a7713b1edbc 6476 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6477 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6478 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
AnnaBridge 171:3a7713b1edbc 6479 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6480 #define FTM_COMBINE_DECAP2_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6481 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
AnnaBridge 171:3a7713b1edbc 6482 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6483 #define FTM_COMBINE_DTEN2_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6484 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
AnnaBridge 171:3a7713b1edbc 6485 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 6486 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 6487 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
AnnaBridge 171:3a7713b1edbc 6488 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 6489 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 6490 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
AnnaBridge 171:3a7713b1edbc 6491 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 6492 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 6493 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
AnnaBridge 171:3a7713b1edbc 6494 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 6495 #define FTM_COMBINE_COMP3_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 6496 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
AnnaBridge 171:3a7713b1edbc 6497 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 6498 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 6499 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
AnnaBridge 171:3a7713b1edbc 6500 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 6501 #define FTM_COMBINE_DECAP3_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 6502 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
AnnaBridge 171:3a7713b1edbc 6503 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 6504 #define FTM_COMBINE_DTEN3_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 6505 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
AnnaBridge 171:3a7713b1edbc 6506 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 6507 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 6508 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
AnnaBridge 171:3a7713b1edbc 6509 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 6510 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 6511 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
AnnaBridge 171:3a7713b1edbc 6512
AnnaBridge 171:3a7713b1edbc 6513 /*! @name DEADTIME - Deadtime Insertion Control */
AnnaBridge 171:3a7713b1edbc 6514 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 6515 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6516 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
AnnaBridge 171:3a7713b1edbc 6517 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6518 #define FTM_DEADTIME_DTPS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6519 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
AnnaBridge 171:3a7713b1edbc 6520
AnnaBridge 171:3a7713b1edbc 6521 /*! @name EXTTRIG - FTM External Trigger */
AnnaBridge 171:3a7713b1edbc 6522 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6523 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6524 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 6525 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6526 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6527 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 6528 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6529 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6530 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 6531 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6532 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6533 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 6534 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6535 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6536 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 6537 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6538 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6539 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
AnnaBridge 171:3a7713b1edbc 6540 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6541 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6542 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
AnnaBridge 171:3a7713b1edbc 6543 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6544 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6545 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
AnnaBridge 171:3a7713b1edbc 6546
AnnaBridge 171:3a7713b1edbc 6547 /*! @name POL - Channels Polarity */
AnnaBridge 171:3a7713b1edbc 6548 #define FTM_POL_POL0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6549 #define FTM_POL_POL0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6550 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
AnnaBridge 171:3a7713b1edbc 6551 #define FTM_POL_POL1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6552 #define FTM_POL_POL1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6553 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
AnnaBridge 171:3a7713b1edbc 6554 #define FTM_POL_POL2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6555 #define FTM_POL_POL2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6556 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
AnnaBridge 171:3a7713b1edbc 6557 #define FTM_POL_POL3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6558 #define FTM_POL_POL3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6559 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
AnnaBridge 171:3a7713b1edbc 6560 #define FTM_POL_POL4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6561 #define FTM_POL_POL4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6562 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
AnnaBridge 171:3a7713b1edbc 6563 #define FTM_POL_POL5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6564 #define FTM_POL_POL5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6565 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
AnnaBridge 171:3a7713b1edbc 6566 #define FTM_POL_POL6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6567 #define FTM_POL_POL6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6568 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
AnnaBridge 171:3a7713b1edbc 6569 #define FTM_POL_POL7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6570 #define FTM_POL_POL7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6571 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
AnnaBridge 171:3a7713b1edbc 6572
AnnaBridge 171:3a7713b1edbc 6573 /*! @name FMS - Fault Mode Status */
AnnaBridge 171:3a7713b1edbc 6574 #define FTM_FMS_FAULTF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6575 #define FTM_FMS_FAULTF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6576 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
AnnaBridge 171:3a7713b1edbc 6577 #define FTM_FMS_FAULTF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6578 #define FTM_FMS_FAULTF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6579 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
AnnaBridge 171:3a7713b1edbc 6580 #define FTM_FMS_FAULTF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6581 #define FTM_FMS_FAULTF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6582 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
AnnaBridge 171:3a7713b1edbc 6583 #define FTM_FMS_FAULTF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6584 #define FTM_FMS_FAULTF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6585 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
AnnaBridge 171:3a7713b1edbc 6586 #define FTM_FMS_FAULTIN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6587 #define FTM_FMS_FAULTIN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6588 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
AnnaBridge 171:3a7713b1edbc 6589 #define FTM_FMS_WPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6590 #define FTM_FMS_WPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6591 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
AnnaBridge 171:3a7713b1edbc 6592 #define FTM_FMS_FAULTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6593 #define FTM_FMS_FAULTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6594 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
AnnaBridge 171:3a7713b1edbc 6595
AnnaBridge 171:3a7713b1edbc 6596 /*! @name FILTER - Input Capture Filter Control */
AnnaBridge 171:3a7713b1edbc 6597 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 6598 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6599 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 6600 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 6601 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6602 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 6603 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 6604 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6605 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 6606 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 6607 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6608 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
AnnaBridge 171:3a7713b1edbc 6609
AnnaBridge 171:3a7713b1edbc 6610 /*! @name FLTCTRL - Fault Control */
AnnaBridge 171:3a7713b1edbc 6611 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6612 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6613 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
AnnaBridge 171:3a7713b1edbc 6614 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6615 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6616 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
AnnaBridge 171:3a7713b1edbc 6617 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6618 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6619 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
AnnaBridge 171:3a7713b1edbc 6620 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6621 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6622 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
AnnaBridge 171:3a7713b1edbc 6623 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6624 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6625 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
AnnaBridge 171:3a7713b1edbc 6626 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6627 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6628 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
AnnaBridge 171:3a7713b1edbc 6629 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6630 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6631 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
AnnaBridge 171:3a7713b1edbc 6632 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6633 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6634 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
AnnaBridge 171:3a7713b1edbc 6635 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 6636 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6637 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
AnnaBridge 171:3a7713b1edbc 6638
AnnaBridge 171:3a7713b1edbc 6639 /*! @name QDCTRL - Quadrature Decoder Control And Status */
AnnaBridge 171:3a7713b1edbc 6640 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6641 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6642 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
AnnaBridge 171:3a7713b1edbc 6643 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6644 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6645 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
AnnaBridge 171:3a7713b1edbc 6646 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6647 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6648 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
AnnaBridge 171:3a7713b1edbc 6649 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6650 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6651 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
AnnaBridge 171:3a7713b1edbc 6652 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6653 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6654 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
AnnaBridge 171:3a7713b1edbc 6655 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6656 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6657 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
AnnaBridge 171:3a7713b1edbc 6658 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6659 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6660 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
AnnaBridge 171:3a7713b1edbc 6661 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6662 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6663 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
AnnaBridge 171:3a7713b1edbc 6664
AnnaBridge 171:3a7713b1edbc 6665 /*! @name CONF - Configuration */
AnnaBridge 171:3a7713b1edbc 6666 #define FTM_CONF_NUMTOF_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 6667 #define FTM_CONF_NUMTOF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6668 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
AnnaBridge 171:3a7713b1edbc 6669 #define FTM_CONF_BDMMODE_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 6670 #define FTM_CONF_BDMMODE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6671 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
AnnaBridge 171:3a7713b1edbc 6672 #define FTM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6673 #define FTM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6674 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
AnnaBridge 171:3a7713b1edbc 6675 #define FTM_CONF_GTBEOUT_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6676 #define FTM_CONF_GTBEOUT_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6677 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
AnnaBridge 171:3a7713b1edbc 6678
AnnaBridge 171:3a7713b1edbc 6679 /*! @name FLTPOL - FTM Fault Input Polarity */
AnnaBridge 171:3a7713b1edbc 6680 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6681 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6682 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
AnnaBridge 171:3a7713b1edbc 6683 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6684 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6685 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
AnnaBridge 171:3a7713b1edbc 6686 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6687 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6688 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
AnnaBridge 171:3a7713b1edbc 6689 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6690 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6691 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
AnnaBridge 171:3a7713b1edbc 6692
AnnaBridge 171:3a7713b1edbc 6693 /*! @name SYNCONF - Synchronization Configuration */
AnnaBridge 171:3a7713b1edbc 6694 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6695 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6696 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
AnnaBridge 171:3a7713b1edbc 6697 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6698 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6699 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
AnnaBridge 171:3a7713b1edbc 6700 #define FTM_SYNCONF_INVC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6701 #define FTM_SYNCONF_INVC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6702 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
AnnaBridge 171:3a7713b1edbc 6703 #define FTM_SYNCONF_SWOC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6704 #define FTM_SYNCONF_SWOC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6705 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
AnnaBridge 171:3a7713b1edbc 6706 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6707 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6708 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
AnnaBridge 171:3a7713b1edbc 6709 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6710 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6711 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 6712 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6713 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6714 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 6715 #define FTM_SYNCONF_SWOM_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6716 #define FTM_SYNCONF_SWOM_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6717 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
AnnaBridge 171:3a7713b1edbc 6718 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6719 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6720 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
AnnaBridge 171:3a7713b1edbc 6721 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6722 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6723 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
AnnaBridge 171:3a7713b1edbc 6724 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 6725 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 6726 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 6727 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 6728 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 6729 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
AnnaBridge 171:3a7713b1edbc 6730 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 6731 #define FTM_SYNCONF_HWOM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 6732 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
AnnaBridge 171:3a7713b1edbc 6733 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 6734 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 6735 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
AnnaBridge 171:3a7713b1edbc 6736 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 6737 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 6738 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
AnnaBridge 171:3a7713b1edbc 6739
AnnaBridge 171:3a7713b1edbc 6740 /*! @name INVCTRL - FTM Inverting Control */
AnnaBridge 171:3a7713b1edbc 6741 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6742 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6743 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
AnnaBridge 171:3a7713b1edbc 6744 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6745 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6746 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
AnnaBridge 171:3a7713b1edbc 6747 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6748 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6749 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
AnnaBridge 171:3a7713b1edbc 6750 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6751 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6752 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
AnnaBridge 171:3a7713b1edbc 6753
AnnaBridge 171:3a7713b1edbc 6754 /*! @name SWOCTRL - FTM Software Output Control */
AnnaBridge 171:3a7713b1edbc 6755 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6756 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6757 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
AnnaBridge 171:3a7713b1edbc 6758 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6759 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6760 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
AnnaBridge 171:3a7713b1edbc 6761 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6762 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6763 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
AnnaBridge 171:3a7713b1edbc 6764 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6765 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6766 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
AnnaBridge 171:3a7713b1edbc 6767 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6768 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6769 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
AnnaBridge 171:3a7713b1edbc 6770 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6771 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6772 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
AnnaBridge 171:3a7713b1edbc 6773 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6774 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6775 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
AnnaBridge 171:3a7713b1edbc 6776 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6777 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6778 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
AnnaBridge 171:3a7713b1edbc 6779 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 6780 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 6781 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6782 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6783 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6784 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6785 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 6786 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 6787 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6788 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 6789 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 6790 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6791 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 6792 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 6793 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6794 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 6795 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 6796 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6797 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 6798 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 6799 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6800 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 6801 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 6802 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
AnnaBridge 171:3a7713b1edbc 6803
AnnaBridge 171:3a7713b1edbc 6804 /*! @name PWMLOAD - FTM PWM Load */
AnnaBridge 171:3a7713b1edbc 6805 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 6806 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6807 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6808 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 6809 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 6810 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6811 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 6812 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 6813 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6814 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 6815 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 6816 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6817 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 6818 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 6819 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6820 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 6821 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 6822 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6823 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 6824 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 6825 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6826 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 6827 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 6828 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
AnnaBridge 171:3a7713b1edbc 6829 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 6830 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 6831 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
AnnaBridge 171:3a7713b1edbc 6832
AnnaBridge 171:3a7713b1edbc 6833
AnnaBridge 171:3a7713b1edbc 6834 /*!
AnnaBridge 171:3a7713b1edbc 6835 * @}
AnnaBridge 171:3a7713b1edbc 6836 */ /* end of group FTM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6837
AnnaBridge 171:3a7713b1edbc 6838
AnnaBridge 171:3a7713b1edbc 6839 /* FTM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6840 /** Peripheral FTM0 base address */
AnnaBridge 171:3a7713b1edbc 6841 #define FTM0_BASE (0x40038000u)
AnnaBridge 171:3a7713b1edbc 6842 /** Peripheral FTM0 base pointer */
AnnaBridge 171:3a7713b1edbc 6843 #define FTM0 ((FTM_Type *)FTM0_BASE)
AnnaBridge 171:3a7713b1edbc 6844 /** Peripheral FTM1 base address */
AnnaBridge 171:3a7713b1edbc 6845 #define FTM1_BASE (0x40039000u)
AnnaBridge 171:3a7713b1edbc 6846 /** Peripheral FTM1 base pointer */
AnnaBridge 171:3a7713b1edbc 6847 #define FTM1 ((FTM_Type *)FTM1_BASE)
AnnaBridge 171:3a7713b1edbc 6848 /** Peripheral FTM2 base address */
AnnaBridge 171:3a7713b1edbc 6849 #define FTM2_BASE (0x4003A000u)
AnnaBridge 171:3a7713b1edbc 6850 /** Peripheral FTM2 base pointer */
AnnaBridge 171:3a7713b1edbc 6851 #define FTM2 ((FTM_Type *)FTM2_BASE)
AnnaBridge 171:3a7713b1edbc 6852 /** Peripheral FTM3 base address */
AnnaBridge 171:3a7713b1edbc 6853 #define FTM3_BASE (0x400B9000u)
AnnaBridge 171:3a7713b1edbc 6854 /** Peripheral FTM3 base pointer */
AnnaBridge 171:3a7713b1edbc 6855 #define FTM3 ((FTM_Type *)FTM3_BASE)
AnnaBridge 171:3a7713b1edbc 6856 /** Array initializer of FTM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6857 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
AnnaBridge 171:3a7713b1edbc 6858 /** Array initializer of FTM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6859 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
AnnaBridge 171:3a7713b1edbc 6860 /** Interrupt vectors for the FTM peripheral type */
AnnaBridge 171:3a7713b1edbc 6861 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
AnnaBridge 171:3a7713b1edbc 6862
AnnaBridge 171:3a7713b1edbc 6863 /*!
AnnaBridge 171:3a7713b1edbc 6864 * @}
AnnaBridge 171:3a7713b1edbc 6865 */ /* end of group FTM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6866
AnnaBridge 171:3a7713b1edbc 6867
AnnaBridge 171:3a7713b1edbc 6868 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6869 -- GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6870 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6871
AnnaBridge 171:3a7713b1edbc 6872 /*!
AnnaBridge 171:3a7713b1edbc 6873 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6874 * @{
AnnaBridge 171:3a7713b1edbc 6875 */
AnnaBridge 171:3a7713b1edbc 6876
AnnaBridge 171:3a7713b1edbc 6877 /** GPIO - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6878 typedef struct {
AnnaBridge 171:3a7713b1edbc 6879 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6880 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6881 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6882 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 6883 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 6884 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 6885 } GPIO_Type;
AnnaBridge 171:3a7713b1edbc 6886
AnnaBridge 171:3a7713b1edbc 6887 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6888 -- GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 6889 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6890
AnnaBridge 171:3a7713b1edbc 6891 /*!
AnnaBridge 171:3a7713b1edbc 6892 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 171:3a7713b1edbc 6893 * @{
AnnaBridge 171:3a7713b1edbc 6894 */
AnnaBridge 171:3a7713b1edbc 6895
AnnaBridge 171:3a7713b1edbc 6896 /*! @name PDOR - Port Data Output Register */
AnnaBridge 171:3a7713b1edbc 6897 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6898 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6899 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 171:3a7713b1edbc 6900
AnnaBridge 171:3a7713b1edbc 6901 /*! @name PSOR - Port Set Output Register */
AnnaBridge 171:3a7713b1edbc 6902 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6903 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6904 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 171:3a7713b1edbc 6905
AnnaBridge 171:3a7713b1edbc 6906 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 171:3a7713b1edbc 6907 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6908 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6909 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 171:3a7713b1edbc 6910
AnnaBridge 171:3a7713b1edbc 6911 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 171:3a7713b1edbc 6912 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6913 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6914 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 171:3a7713b1edbc 6915
AnnaBridge 171:3a7713b1edbc 6916 /*! @name PDIR - Port Data Input Register */
AnnaBridge 171:3a7713b1edbc 6917 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6918 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6919 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 171:3a7713b1edbc 6920
AnnaBridge 171:3a7713b1edbc 6921 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 171:3a7713b1edbc 6922 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 6923 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 6924 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 171:3a7713b1edbc 6925
AnnaBridge 171:3a7713b1edbc 6926
AnnaBridge 171:3a7713b1edbc 6927 /*!
AnnaBridge 171:3a7713b1edbc 6928 * @}
AnnaBridge 171:3a7713b1edbc 6929 */ /* end of group GPIO_Register_Masks */
AnnaBridge 171:3a7713b1edbc 6930
AnnaBridge 171:3a7713b1edbc 6931
AnnaBridge 171:3a7713b1edbc 6932 /* GPIO - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 6933 /** Peripheral GPIOA base address */
AnnaBridge 171:3a7713b1edbc 6934 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 171:3a7713b1edbc 6935 /** Peripheral GPIOA base pointer */
AnnaBridge 171:3a7713b1edbc 6936 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 171:3a7713b1edbc 6937 /** Peripheral GPIOB base address */
AnnaBridge 171:3a7713b1edbc 6938 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 171:3a7713b1edbc 6939 /** Peripheral GPIOB base pointer */
AnnaBridge 171:3a7713b1edbc 6940 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 171:3a7713b1edbc 6941 /** Peripheral GPIOC base address */
AnnaBridge 171:3a7713b1edbc 6942 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 171:3a7713b1edbc 6943 /** Peripheral GPIOC base pointer */
AnnaBridge 171:3a7713b1edbc 6944 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 171:3a7713b1edbc 6945 /** Peripheral GPIOD base address */
AnnaBridge 171:3a7713b1edbc 6946 #define GPIOD_BASE (0x400FF0C0u)
AnnaBridge 171:3a7713b1edbc 6947 /** Peripheral GPIOD base pointer */
AnnaBridge 171:3a7713b1edbc 6948 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
AnnaBridge 171:3a7713b1edbc 6949 /** Peripheral GPIOE base address */
AnnaBridge 171:3a7713b1edbc 6950 #define GPIOE_BASE (0x400FF100u)
AnnaBridge 171:3a7713b1edbc 6951 /** Peripheral GPIOE base pointer */
AnnaBridge 171:3a7713b1edbc 6952 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
AnnaBridge 171:3a7713b1edbc 6953 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 6954 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
AnnaBridge 171:3a7713b1edbc 6955 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 6956 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
AnnaBridge 171:3a7713b1edbc 6957
AnnaBridge 171:3a7713b1edbc 6958 /*!
AnnaBridge 171:3a7713b1edbc 6959 * @}
AnnaBridge 171:3a7713b1edbc 6960 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 6961
AnnaBridge 171:3a7713b1edbc 6962
AnnaBridge 171:3a7713b1edbc 6963 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6964 -- I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6965 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6966
AnnaBridge 171:3a7713b1edbc 6967 /*!
AnnaBridge 171:3a7713b1edbc 6968 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 6969 * @{
AnnaBridge 171:3a7713b1edbc 6970 */
AnnaBridge 171:3a7713b1edbc 6971
AnnaBridge 171:3a7713b1edbc 6972 /** I2C - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 6973 typedef struct {
AnnaBridge 171:3a7713b1edbc 6974 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 6975 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 6976 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 6977 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 6978 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 6979 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 6980 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 6981 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 6982 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 6983 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 6984 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 6985 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 6986 } I2C_Type;
AnnaBridge 171:3a7713b1edbc 6987
AnnaBridge 171:3a7713b1edbc 6988 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 6989 -- I2C Register Masks
AnnaBridge 171:3a7713b1edbc 6990 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 6991
AnnaBridge 171:3a7713b1edbc 6992 /*!
AnnaBridge 171:3a7713b1edbc 6993 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 171:3a7713b1edbc 6994 * @{
AnnaBridge 171:3a7713b1edbc 6995 */
AnnaBridge 171:3a7713b1edbc 6996
AnnaBridge 171:3a7713b1edbc 6997 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 171:3a7713b1edbc 6998 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 6999 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7000 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 171:3a7713b1edbc 7001
AnnaBridge 171:3a7713b1edbc 7002 /*! @name F - I2C Frequency Divider register */
AnnaBridge 171:3a7713b1edbc 7003 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 7004 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7005 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 171:3a7713b1edbc 7006 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7007 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7008 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 7009
AnnaBridge 171:3a7713b1edbc 7010 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 171:3a7713b1edbc 7011 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7012 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7013 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7014 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7015 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7016 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 171:3a7713b1edbc 7017 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7018 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7019 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 7020 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7021 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7022 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 171:3a7713b1edbc 7023 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7024 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7025 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 171:3a7713b1edbc 7026 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7027 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7028 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 171:3a7713b1edbc 7029 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7030 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7031 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 171:3a7713b1edbc 7032 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7033 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7034 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 171:3a7713b1edbc 7035
AnnaBridge 171:3a7713b1edbc 7036 /*! @name S - I2C Status register */
AnnaBridge 171:3a7713b1edbc 7037 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7038 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7039 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 171:3a7713b1edbc 7040 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7041 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7042 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 171:3a7713b1edbc 7043 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7044 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7045 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 7046 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7047 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7048 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 171:3a7713b1edbc 7049 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7050 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7051 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 171:3a7713b1edbc 7052 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7053 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7054 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 171:3a7713b1edbc 7055 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7056 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7057 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 171:3a7713b1edbc 7058 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7059 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7060 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 7061
AnnaBridge 171:3a7713b1edbc 7062 /*! @name D - I2C Data I/O register */
AnnaBridge 171:3a7713b1edbc 7063 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7064 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7065 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 171:3a7713b1edbc 7066
AnnaBridge 171:3a7713b1edbc 7067 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 171:3a7713b1edbc 7068 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7069 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7070 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 171:3a7713b1edbc 7071 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7072 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7073 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 171:3a7713b1edbc 7074 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7075 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7076 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 171:3a7713b1edbc 7077 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7078 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7079 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 171:3a7713b1edbc 7080 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7081 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7082 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 171:3a7713b1edbc 7083 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7084 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7085 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7086
AnnaBridge 171:3a7713b1edbc 7087 /*! @name FLT - I2C Programmable Input Glitch Filter register */
AnnaBridge 171:3a7713b1edbc 7088 #define I2C_FLT_FLT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7089 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7090 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 171:3a7713b1edbc 7091 #define I2C_FLT_STARTF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7092 #define I2C_FLT_STARTF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7093 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
AnnaBridge 171:3a7713b1edbc 7094 #define I2C_FLT_SSIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7095 #define I2C_FLT_SSIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7096 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
AnnaBridge 171:3a7713b1edbc 7097 #define I2C_FLT_STOPF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7098 #define I2C_FLT_STOPF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7099 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
AnnaBridge 171:3a7713b1edbc 7100 #define I2C_FLT_SHEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7101 #define I2C_FLT_SHEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7102 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
AnnaBridge 171:3a7713b1edbc 7103
AnnaBridge 171:3a7713b1edbc 7104 /*! @name RA - I2C Range Address register */
AnnaBridge 171:3a7713b1edbc 7105 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 7106 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7107 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 171:3a7713b1edbc 7108
AnnaBridge 171:3a7713b1edbc 7109 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 171:3a7713b1edbc 7110 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7111 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7112 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 171:3a7713b1edbc 7113 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7114 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7115 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 171:3a7713b1edbc 7116 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7117 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7118 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 171:3a7713b1edbc 7119 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7120 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7121 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 171:3a7713b1edbc 7122 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7123 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7124 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7125 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7126 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7127 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 171:3a7713b1edbc 7128 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7129 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7130 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 171:3a7713b1edbc 7131 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7132 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7133 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 171:3a7713b1edbc 7134
AnnaBridge 171:3a7713b1edbc 7135 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 171:3a7713b1edbc 7136 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 7137 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7138 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 171:3a7713b1edbc 7139
AnnaBridge 171:3a7713b1edbc 7140 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 171:3a7713b1edbc 7141 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7142 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7143 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 7144
AnnaBridge 171:3a7713b1edbc 7145 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 171:3a7713b1edbc 7146 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7147 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7148 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 171:3a7713b1edbc 7149
AnnaBridge 171:3a7713b1edbc 7150
AnnaBridge 171:3a7713b1edbc 7151 /*!
AnnaBridge 171:3a7713b1edbc 7152 * @}
AnnaBridge 171:3a7713b1edbc 7153 */ /* end of group I2C_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7154
AnnaBridge 171:3a7713b1edbc 7155
AnnaBridge 171:3a7713b1edbc 7156 /* I2C - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7157 /** Peripheral I2C0 base address */
AnnaBridge 171:3a7713b1edbc 7158 #define I2C0_BASE (0x40066000u)
AnnaBridge 171:3a7713b1edbc 7159 /** Peripheral I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 7160 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 171:3a7713b1edbc 7161 /** Peripheral I2C1 base address */
AnnaBridge 171:3a7713b1edbc 7162 #define I2C1_BASE (0x40067000u)
AnnaBridge 171:3a7713b1edbc 7163 /** Peripheral I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 7164 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 171:3a7713b1edbc 7165 /** Peripheral I2C2 base address */
AnnaBridge 171:3a7713b1edbc 7166 #define I2C2_BASE (0x400E6000u)
AnnaBridge 171:3a7713b1edbc 7167 /** Peripheral I2C2 base pointer */
AnnaBridge 171:3a7713b1edbc 7168 #define I2C2 ((I2C_Type *)I2C2_BASE)
AnnaBridge 171:3a7713b1edbc 7169 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7170 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
AnnaBridge 171:3a7713b1edbc 7171 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7172 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
AnnaBridge 171:3a7713b1edbc 7173 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 171:3a7713b1edbc 7174 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
AnnaBridge 171:3a7713b1edbc 7175
AnnaBridge 171:3a7713b1edbc 7176 /*!
AnnaBridge 171:3a7713b1edbc 7177 * @}
AnnaBridge 171:3a7713b1edbc 7178 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7179
AnnaBridge 171:3a7713b1edbc 7180
AnnaBridge 171:3a7713b1edbc 7181 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7182 -- I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7183 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7184
AnnaBridge 171:3a7713b1edbc 7185 /*!
AnnaBridge 171:3a7713b1edbc 7186 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7187 * @{
AnnaBridge 171:3a7713b1edbc 7188 */
AnnaBridge 171:3a7713b1edbc 7189
AnnaBridge 171:3a7713b1edbc 7190 /** I2S - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7191 typedef struct {
AnnaBridge 171:3a7713b1edbc 7192 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7193 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7194 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7195 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7196 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 7197 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 7198 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 7199 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7200 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 7201 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7202 uint8_t RESERVED_2[24];
AnnaBridge 171:3a7713b1edbc 7203 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
AnnaBridge 171:3a7713b1edbc 7204 uint8_t RESERVED_3[28];
AnnaBridge 171:3a7713b1edbc 7205 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 7206 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 7207 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 7208 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 7209 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 7210 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 7211 uint8_t RESERVED_4[8];
AnnaBridge 171:3a7713b1edbc 7212 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7213 uint8_t RESERVED_5[24];
AnnaBridge 171:3a7713b1edbc 7214 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 7215 uint8_t RESERVED_6[24];
AnnaBridge 171:3a7713b1edbc 7216 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
AnnaBridge 171:3a7713b1edbc 7217 uint8_t RESERVED_7[28];
AnnaBridge 171:3a7713b1edbc 7218 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 7219 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 7220 } I2S_Type;
AnnaBridge 171:3a7713b1edbc 7221
AnnaBridge 171:3a7713b1edbc 7222 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7223 -- I2S Register Masks
AnnaBridge 171:3a7713b1edbc 7224 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7225
AnnaBridge 171:3a7713b1edbc 7226 /*!
AnnaBridge 171:3a7713b1edbc 7227 * @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge 171:3a7713b1edbc 7228 * @{
AnnaBridge 171:3a7713b1edbc 7229 */
AnnaBridge 171:3a7713b1edbc 7230
AnnaBridge 171:3a7713b1edbc 7231 /*! @name TCSR - SAI Transmit Control Register */
AnnaBridge 171:3a7713b1edbc 7232 #define I2S_TCSR_FRDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7233 #define I2S_TCSR_FRDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7234 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
AnnaBridge 171:3a7713b1edbc 7235 #define I2S_TCSR_FWDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7236 #define I2S_TCSR_FWDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7237 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
AnnaBridge 171:3a7713b1edbc 7238 #define I2S_TCSR_FRIE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7239 #define I2S_TCSR_FRIE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7240 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
AnnaBridge 171:3a7713b1edbc 7241 #define I2S_TCSR_FWIE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7242 #define I2S_TCSR_FWIE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7243 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
AnnaBridge 171:3a7713b1edbc 7244 #define I2S_TCSR_FEIE_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7245 #define I2S_TCSR_FEIE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7246 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7247 #define I2S_TCSR_SEIE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7248 #define I2S_TCSR_SEIE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7249 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7250 #define I2S_TCSR_WSIE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7251 #define I2S_TCSR_WSIE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7252 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
AnnaBridge 171:3a7713b1edbc 7253 #define I2S_TCSR_FRF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7254 #define I2S_TCSR_FRF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7255 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
AnnaBridge 171:3a7713b1edbc 7256 #define I2S_TCSR_FWF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7257 #define I2S_TCSR_FWF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7258 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
AnnaBridge 171:3a7713b1edbc 7259 #define I2S_TCSR_FEF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 7260 #define I2S_TCSR_FEF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 7261 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
AnnaBridge 171:3a7713b1edbc 7262 #define I2S_TCSR_SEF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7263 #define I2S_TCSR_SEF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7264 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 7265 #define I2S_TCSR_WSF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 7266 #define I2S_TCSR_WSF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 7267 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
AnnaBridge 171:3a7713b1edbc 7268 #define I2S_TCSR_SR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 7269 #define I2S_TCSR_SR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7270 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
AnnaBridge 171:3a7713b1edbc 7271 #define I2S_TCSR_FR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7272 #define I2S_TCSR_FR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7273 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
AnnaBridge 171:3a7713b1edbc 7274 #define I2S_TCSR_BCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7275 #define I2S_TCSR_BCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7276 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
AnnaBridge 171:3a7713b1edbc 7277 #define I2S_TCSR_DBGE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 7278 #define I2S_TCSR_DBGE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 7279 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 7280 #define I2S_TCSR_STOPE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 7281 #define I2S_TCSR_STOPE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7282 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
AnnaBridge 171:3a7713b1edbc 7283 #define I2S_TCSR_TE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7284 #define I2S_TCSR_TE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7285 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
AnnaBridge 171:3a7713b1edbc 7286
AnnaBridge 171:3a7713b1edbc 7287 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
AnnaBridge 171:3a7713b1edbc 7288 #define I2S_TCR1_TFW_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7289 #define I2S_TCR1_TFW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7290 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
AnnaBridge 171:3a7713b1edbc 7291
AnnaBridge 171:3a7713b1edbc 7292 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
AnnaBridge 171:3a7713b1edbc 7293 #define I2S_TCR2_DIV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7294 #define I2S_TCR2_DIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7295 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 7296 #define I2S_TCR2_BCD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 7297 #define I2S_TCR2_BCD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7298 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
AnnaBridge 171:3a7713b1edbc 7299 #define I2S_TCR2_BCP_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7300 #define I2S_TCR2_BCP_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7301 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
AnnaBridge 171:3a7713b1edbc 7302 #define I2S_TCR2_MSEL_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 7303 #define I2S_TCR2_MSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 7304 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7305 #define I2S_TCR2_BCI_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7306 #define I2S_TCR2_BCI_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7307 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
AnnaBridge 171:3a7713b1edbc 7308 #define I2S_TCR2_BCS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 7309 #define I2S_TCR2_BCS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 7310 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
AnnaBridge 171:3a7713b1edbc 7311 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 7312 #define I2S_TCR2_SYNC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7313 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 7314
AnnaBridge 171:3a7713b1edbc 7315 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
AnnaBridge 171:3a7713b1edbc 7316 #define I2S_TCR3_WDFL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 7317 #define I2S_TCR3_WDFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7318 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
AnnaBridge 171:3a7713b1edbc 7319 #define I2S_TCR3_TCE_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 7320 #define I2S_TCR3_TCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7321 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 7322
AnnaBridge 171:3a7713b1edbc 7323 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
AnnaBridge 171:3a7713b1edbc 7324 #define I2S_TCR4_FSD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7325 #define I2S_TCR4_FSD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7326 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
AnnaBridge 171:3a7713b1edbc 7327 #define I2S_TCR4_FSP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7328 #define I2S_TCR4_FSP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7329 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
AnnaBridge 171:3a7713b1edbc 7330 #define I2S_TCR4_FSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7331 #define I2S_TCR4_FSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7332 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
AnnaBridge 171:3a7713b1edbc 7333 #define I2S_TCR4_MF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7334 #define I2S_TCR4_MF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7335 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
AnnaBridge 171:3a7713b1edbc 7336 #define I2S_TCR4_SYWD_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 7337 #define I2S_TCR4_SYWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7338 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 7339 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 7340 #define I2S_TCR4_FRSZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7341 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
AnnaBridge 171:3a7713b1edbc 7342
AnnaBridge 171:3a7713b1edbc 7343 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
AnnaBridge 171:3a7713b1edbc 7344 #define I2S_TCR5_FBT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 7345 #define I2S_TCR5_FBT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7346 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 7347 #define I2S_TCR5_W0W_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 7348 #define I2S_TCR5_W0W_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7349 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 7350 #define I2S_TCR5_WNW_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 7351 #define I2S_TCR5_WNW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7352 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 7353
AnnaBridge 171:3a7713b1edbc 7354 /*! @name TDR - SAI Transmit Data Register */
AnnaBridge 171:3a7713b1edbc 7355 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7356 #define I2S_TDR_TDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7357 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
AnnaBridge 171:3a7713b1edbc 7358
AnnaBridge 171:3a7713b1edbc 7359 /* The count of I2S_TDR */
AnnaBridge 171:3a7713b1edbc 7360 #define I2S_TDR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 7361
AnnaBridge 171:3a7713b1edbc 7362 /*! @name TFR - SAI Transmit FIFO Register */
AnnaBridge 171:3a7713b1edbc 7363 #define I2S_TFR_RFP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7364 #define I2S_TFR_RFP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7365 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
AnnaBridge 171:3a7713b1edbc 7366 #define I2S_TFR_WFP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 7367 #define I2S_TFR_WFP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7368 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
AnnaBridge 171:3a7713b1edbc 7369
AnnaBridge 171:3a7713b1edbc 7370 /* The count of I2S_TFR */
AnnaBridge 171:3a7713b1edbc 7371 #define I2S_TFR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 7372
AnnaBridge 171:3a7713b1edbc 7373 /*! @name TMR - SAI Transmit Mask Register */
AnnaBridge 171:3a7713b1edbc 7374 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7375 #define I2S_TMR_TWM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7376 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
AnnaBridge 171:3a7713b1edbc 7377
AnnaBridge 171:3a7713b1edbc 7378 /*! @name RCSR - SAI Receive Control Register */
AnnaBridge 171:3a7713b1edbc 7379 #define I2S_RCSR_FRDE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7380 #define I2S_RCSR_FRDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7381 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
AnnaBridge 171:3a7713b1edbc 7382 #define I2S_RCSR_FWDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7383 #define I2S_RCSR_FWDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7384 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
AnnaBridge 171:3a7713b1edbc 7385 #define I2S_RCSR_FRIE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 7386 #define I2S_RCSR_FRIE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7387 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
AnnaBridge 171:3a7713b1edbc 7388 #define I2S_RCSR_FWIE_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 7389 #define I2S_RCSR_FWIE_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 7390 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
AnnaBridge 171:3a7713b1edbc 7391 #define I2S_RCSR_FEIE_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 7392 #define I2S_RCSR_FEIE_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 7393 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7394 #define I2S_RCSR_SEIE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 7395 #define I2S_RCSR_SEIE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 7396 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
AnnaBridge 171:3a7713b1edbc 7397 #define I2S_RCSR_WSIE_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 7398 #define I2S_RCSR_WSIE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7399 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
AnnaBridge 171:3a7713b1edbc 7400 #define I2S_RCSR_FRF_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 7401 #define I2S_RCSR_FRF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7402 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
AnnaBridge 171:3a7713b1edbc 7403 #define I2S_RCSR_FWF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 7404 #define I2S_RCSR_FWF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 7405 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
AnnaBridge 171:3a7713b1edbc 7406 #define I2S_RCSR_FEF_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 7407 #define I2S_RCSR_FEF_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 7408 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
AnnaBridge 171:3a7713b1edbc 7409 #define I2S_RCSR_SEF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 7410 #define I2S_RCSR_SEF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 7411 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
AnnaBridge 171:3a7713b1edbc 7412 #define I2S_RCSR_WSF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 7413 #define I2S_RCSR_WSF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 7414 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
AnnaBridge 171:3a7713b1edbc 7415 #define I2S_RCSR_SR_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 7416 #define I2S_RCSR_SR_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7417 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
AnnaBridge 171:3a7713b1edbc 7418 #define I2S_RCSR_FR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7419 #define I2S_RCSR_FR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7420 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
AnnaBridge 171:3a7713b1edbc 7421 #define I2S_RCSR_BCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7422 #define I2S_RCSR_BCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7423 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
AnnaBridge 171:3a7713b1edbc 7424 #define I2S_RCSR_DBGE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 7425 #define I2S_RCSR_DBGE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 7426 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
AnnaBridge 171:3a7713b1edbc 7427 #define I2S_RCSR_STOPE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 7428 #define I2S_RCSR_STOPE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7429 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
AnnaBridge 171:3a7713b1edbc 7430 #define I2S_RCSR_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7431 #define I2S_RCSR_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7432 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
AnnaBridge 171:3a7713b1edbc 7433
AnnaBridge 171:3a7713b1edbc 7434 /*! @name RCR1 - SAI Receive Configuration 1 Register */
AnnaBridge 171:3a7713b1edbc 7435 #define I2S_RCR1_RFW_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 7436 #define I2S_RCR1_RFW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7437 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
AnnaBridge 171:3a7713b1edbc 7438
AnnaBridge 171:3a7713b1edbc 7439 /*! @name RCR2 - SAI Receive Configuration 2 Register */
AnnaBridge 171:3a7713b1edbc 7440 #define I2S_RCR2_DIV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7441 #define I2S_RCR2_DIV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7442 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
AnnaBridge 171:3a7713b1edbc 7443 #define I2S_RCR2_BCD_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 7444 #define I2S_RCR2_BCD_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7445 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
AnnaBridge 171:3a7713b1edbc 7446 #define I2S_RCR2_BCP_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 7447 #define I2S_RCR2_BCP_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 7448 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
AnnaBridge 171:3a7713b1edbc 7449 #define I2S_RCR2_MSEL_MASK (0xC000000U)
AnnaBridge 171:3a7713b1edbc 7450 #define I2S_RCR2_MSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 7451 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7452 #define I2S_RCR2_BCI_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 7453 #define I2S_RCR2_BCI_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 7454 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
AnnaBridge 171:3a7713b1edbc 7455 #define I2S_RCR2_BCS_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 7456 #define I2S_RCR2_BCS_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 7457 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
AnnaBridge 171:3a7713b1edbc 7458 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 171:3a7713b1edbc 7459 #define I2S_RCR2_SYNC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7460 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
AnnaBridge 171:3a7713b1edbc 7461
AnnaBridge 171:3a7713b1edbc 7462 /*! @name RCR3 - SAI Receive Configuration 3 Register */
AnnaBridge 171:3a7713b1edbc 7463 #define I2S_RCR3_WDFL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 7464 #define I2S_RCR3_WDFL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7465 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
AnnaBridge 171:3a7713b1edbc 7466 #define I2S_RCR3_RCE_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 7467 #define I2S_RCR3_RCE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7468 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
AnnaBridge 171:3a7713b1edbc 7469
AnnaBridge 171:3a7713b1edbc 7470 /*! @name RCR4 - SAI Receive Configuration 4 Register */
AnnaBridge 171:3a7713b1edbc 7471 #define I2S_RCR4_FSD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7472 #define I2S_RCR4_FSD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7473 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
AnnaBridge 171:3a7713b1edbc 7474 #define I2S_RCR4_FSP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7475 #define I2S_RCR4_FSP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7476 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
AnnaBridge 171:3a7713b1edbc 7477 #define I2S_RCR4_FSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7478 #define I2S_RCR4_FSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7479 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
AnnaBridge 171:3a7713b1edbc 7480 #define I2S_RCR4_MF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7481 #define I2S_RCR4_MF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7482 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
AnnaBridge 171:3a7713b1edbc 7483 #define I2S_RCR4_SYWD_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 7484 #define I2S_RCR4_SYWD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7485 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
AnnaBridge 171:3a7713b1edbc 7486 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 7487 #define I2S_RCR4_FRSZ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7488 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
AnnaBridge 171:3a7713b1edbc 7489
AnnaBridge 171:3a7713b1edbc 7490 /*! @name RCR5 - SAI Receive Configuration 5 Register */
AnnaBridge 171:3a7713b1edbc 7491 #define I2S_RCR5_FBT_MASK (0x1F00U)
AnnaBridge 171:3a7713b1edbc 7492 #define I2S_RCR5_FBT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 7493 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
AnnaBridge 171:3a7713b1edbc 7494 #define I2S_RCR5_W0W_MASK (0x1F0000U)
AnnaBridge 171:3a7713b1edbc 7495 #define I2S_RCR5_W0W_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7496 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
AnnaBridge 171:3a7713b1edbc 7497 #define I2S_RCR5_WNW_MASK (0x1F000000U)
AnnaBridge 171:3a7713b1edbc 7498 #define I2S_RCR5_WNW_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7499 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
AnnaBridge 171:3a7713b1edbc 7500
AnnaBridge 171:3a7713b1edbc 7501 /*! @name RDR - SAI Receive Data Register */
AnnaBridge 171:3a7713b1edbc 7502 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7503 #define I2S_RDR_RDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7504 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
AnnaBridge 171:3a7713b1edbc 7505
AnnaBridge 171:3a7713b1edbc 7506 /* The count of I2S_RDR */
AnnaBridge 171:3a7713b1edbc 7507 #define I2S_RDR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 7508
AnnaBridge 171:3a7713b1edbc 7509 /*! @name RFR - SAI Receive FIFO Register */
AnnaBridge 171:3a7713b1edbc 7510 #define I2S_RFR_RFP_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7511 #define I2S_RFR_RFP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7512 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
AnnaBridge 171:3a7713b1edbc 7513 #define I2S_RFR_WFP_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 7514 #define I2S_RFR_WFP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 7515 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
AnnaBridge 171:3a7713b1edbc 7516
AnnaBridge 171:3a7713b1edbc 7517 /* The count of I2S_RFR */
AnnaBridge 171:3a7713b1edbc 7518 #define I2S_RFR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 7519
AnnaBridge 171:3a7713b1edbc 7520 /*! @name RMR - SAI Receive Mask Register */
AnnaBridge 171:3a7713b1edbc 7521 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 7522 #define I2S_RMR_RWM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7523 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
AnnaBridge 171:3a7713b1edbc 7524
AnnaBridge 171:3a7713b1edbc 7525 /*! @name MCR - SAI MCLK Control Register */
AnnaBridge 171:3a7713b1edbc 7526 #define I2S_MCR_MICS_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 7527 #define I2S_MCR_MICS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 7528 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
AnnaBridge 171:3a7713b1edbc 7529 #define I2S_MCR_MOE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 7530 #define I2S_MCR_MOE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 7531 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
AnnaBridge 171:3a7713b1edbc 7532 #define I2S_MCR_DUF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 7533 #define I2S_MCR_DUF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 7534 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
AnnaBridge 171:3a7713b1edbc 7535
AnnaBridge 171:3a7713b1edbc 7536 /*! @name MDR - SAI MCLK Divide Register */
AnnaBridge 171:3a7713b1edbc 7537 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 7538 #define I2S_MDR_DIVIDE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7539 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
AnnaBridge 171:3a7713b1edbc 7540 #define I2S_MDR_FRACT_MASK (0xFF000U)
AnnaBridge 171:3a7713b1edbc 7541 #define I2S_MDR_FRACT_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 7542 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
AnnaBridge 171:3a7713b1edbc 7543
AnnaBridge 171:3a7713b1edbc 7544
AnnaBridge 171:3a7713b1edbc 7545 /*!
AnnaBridge 171:3a7713b1edbc 7546 * @}
AnnaBridge 171:3a7713b1edbc 7547 */ /* end of group I2S_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7548
AnnaBridge 171:3a7713b1edbc 7549
AnnaBridge 171:3a7713b1edbc 7550 /* I2S - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7551 /** Peripheral I2S0 base address */
AnnaBridge 171:3a7713b1edbc 7552 #define I2S0_BASE (0x4002F000u)
AnnaBridge 171:3a7713b1edbc 7553 /** Peripheral I2S0 base pointer */
AnnaBridge 171:3a7713b1edbc 7554 #define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge 171:3a7713b1edbc 7555 /** Array initializer of I2S peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7556 #define I2S_BASE_ADDRS { I2S0_BASE }
AnnaBridge 171:3a7713b1edbc 7557 /** Array initializer of I2S peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7558 #define I2S_BASE_PTRS { I2S0 }
AnnaBridge 171:3a7713b1edbc 7559 /** Interrupt vectors for the I2S peripheral type */
AnnaBridge 171:3a7713b1edbc 7560 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
AnnaBridge 171:3a7713b1edbc 7561 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
AnnaBridge 171:3a7713b1edbc 7562
AnnaBridge 171:3a7713b1edbc 7563 /*!
AnnaBridge 171:3a7713b1edbc 7564 * @}
AnnaBridge 171:3a7713b1edbc 7565 */ /* end of group I2S_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7566
AnnaBridge 171:3a7713b1edbc 7567
AnnaBridge 171:3a7713b1edbc 7568 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7569 -- LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7570 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7571
AnnaBridge 171:3a7713b1edbc 7572 /*!
AnnaBridge 171:3a7713b1edbc 7573 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7574 * @{
AnnaBridge 171:3a7713b1edbc 7575 */
AnnaBridge 171:3a7713b1edbc 7576
AnnaBridge 171:3a7713b1edbc 7577 /** LLWU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7578 typedef struct {
AnnaBridge 171:3a7713b1edbc 7579 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7580 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 7581 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 7582 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 7583 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7584 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 7585 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 7586 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 7587 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7588 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 7589 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 7590 } LLWU_Type;
AnnaBridge 171:3a7713b1edbc 7591
AnnaBridge 171:3a7713b1edbc 7592 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7593 -- LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 7594 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7595
AnnaBridge 171:3a7713b1edbc 7596 /*!
AnnaBridge 171:3a7713b1edbc 7597 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 171:3a7713b1edbc 7598 * @{
AnnaBridge 171:3a7713b1edbc 7599 */
AnnaBridge 171:3a7713b1edbc 7600
AnnaBridge 171:3a7713b1edbc 7601 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 171:3a7713b1edbc 7602 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7603 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7604 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 171:3a7713b1edbc 7605 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 7606 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7607 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 171:3a7713b1edbc 7608 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 7609 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7610 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 171:3a7713b1edbc 7611 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7612 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7613 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 171:3a7713b1edbc 7614
AnnaBridge 171:3a7713b1edbc 7615 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 171:3a7713b1edbc 7616 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7617 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7618 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 171:3a7713b1edbc 7619 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 7620 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7621 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 171:3a7713b1edbc 7622 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 7623 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7624 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 171:3a7713b1edbc 7625 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7626 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7627 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 171:3a7713b1edbc 7628
AnnaBridge 171:3a7713b1edbc 7629 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 171:3a7713b1edbc 7630 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7631 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7632 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 171:3a7713b1edbc 7633 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 7634 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7635 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 171:3a7713b1edbc 7636 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 7637 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7638 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 171:3a7713b1edbc 7639 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7640 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7641 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 171:3a7713b1edbc 7642
AnnaBridge 171:3a7713b1edbc 7643 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 171:3a7713b1edbc 7644 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7645 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7646 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 171:3a7713b1edbc 7647 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 7648 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7649 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 171:3a7713b1edbc 7650 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 7651 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7652 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 171:3a7713b1edbc 7653 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7654 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7655 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 171:3a7713b1edbc 7656
AnnaBridge 171:3a7713b1edbc 7657 /*! @name ME - LLWU Module Enable register */
AnnaBridge 171:3a7713b1edbc 7658 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7659 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7660 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 171:3a7713b1edbc 7661 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7662 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7663 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 171:3a7713b1edbc 7664 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7665 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7666 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 171:3a7713b1edbc 7667 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7668 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7669 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 171:3a7713b1edbc 7670 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7671 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7672 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 171:3a7713b1edbc 7673 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7674 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7675 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 171:3a7713b1edbc 7676 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7677 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7678 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 171:3a7713b1edbc 7679 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7680 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7681 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 171:3a7713b1edbc 7682
AnnaBridge 171:3a7713b1edbc 7683 /*! @name F1 - LLWU Flag 1 register */
AnnaBridge 171:3a7713b1edbc 7684 #define LLWU_F1_WUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7685 #define LLWU_F1_WUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7686 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
AnnaBridge 171:3a7713b1edbc 7687 #define LLWU_F1_WUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7688 #define LLWU_F1_WUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7689 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
AnnaBridge 171:3a7713b1edbc 7690 #define LLWU_F1_WUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7691 #define LLWU_F1_WUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7692 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
AnnaBridge 171:3a7713b1edbc 7693 #define LLWU_F1_WUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7694 #define LLWU_F1_WUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7695 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
AnnaBridge 171:3a7713b1edbc 7696 #define LLWU_F1_WUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7697 #define LLWU_F1_WUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7698 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
AnnaBridge 171:3a7713b1edbc 7699 #define LLWU_F1_WUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7700 #define LLWU_F1_WUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7701 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
AnnaBridge 171:3a7713b1edbc 7702 #define LLWU_F1_WUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7703 #define LLWU_F1_WUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7704 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
AnnaBridge 171:3a7713b1edbc 7705 #define LLWU_F1_WUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7706 #define LLWU_F1_WUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7707 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
AnnaBridge 171:3a7713b1edbc 7708
AnnaBridge 171:3a7713b1edbc 7709 /*! @name F2 - LLWU Flag 2 register */
AnnaBridge 171:3a7713b1edbc 7710 #define LLWU_F2_WUF8_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7711 #define LLWU_F2_WUF8_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7712 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
AnnaBridge 171:3a7713b1edbc 7713 #define LLWU_F2_WUF9_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7714 #define LLWU_F2_WUF9_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7715 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
AnnaBridge 171:3a7713b1edbc 7716 #define LLWU_F2_WUF10_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7717 #define LLWU_F2_WUF10_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7718 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
AnnaBridge 171:3a7713b1edbc 7719 #define LLWU_F2_WUF11_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7720 #define LLWU_F2_WUF11_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7721 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
AnnaBridge 171:3a7713b1edbc 7722 #define LLWU_F2_WUF12_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7723 #define LLWU_F2_WUF12_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7724 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
AnnaBridge 171:3a7713b1edbc 7725 #define LLWU_F2_WUF13_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7726 #define LLWU_F2_WUF13_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7727 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
AnnaBridge 171:3a7713b1edbc 7728 #define LLWU_F2_WUF14_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7729 #define LLWU_F2_WUF14_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7730 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
AnnaBridge 171:3a7713b1edbc 7731 #define LLWU_F2_WUF15_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7732 #define LLWU_F2_WUF15_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7733 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
AnnaBridge 171:3a7713b1edbc 7734
AnnaBridge 171:3a7713b1edbc 7735 /*! @name F3 - LLWU Flag 3 register */
AnnaBridge 171:3a7713b1edbc 7736 #define LLWU_F3_MWUF0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7737 #define LLWU_F3_MWUF0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7738 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
AnnaBridge 171:3a7713b1edbc 7739 #define LLWU_F3_MWUF1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7740 #define LLWU_F3_MWUF1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7741 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
AnnaBridge 171:3a7713b1edbc 7742 #define LLWU_F3_MWUF2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7743 #define LLWU_F3_MWUF2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7744 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
AnnaBridge 171:3a7713b1edbc 7745 #define LLWU_F3_MWUF3_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7746 #define LLWU_F3_MWUF3_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7747 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
AnnaBridge 171:3a7713b1edbc 7748 #define LLWU_F3_MWUF4_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 7749 #define LLWU_F3_MWUF4_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7750 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
AnnaBridge 171:3a7713b1edbc 7751 #define LLWU_F3_MWUF5_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 7752 #define LLWU_F3_MWUF5_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7753 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
AnnaBridge 171:3a7713b1edbc 7754 #define LLWU_F3_MWUF6_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7755 #define LLWU_F3_MWUF6_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7756 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
AnnaBridge 171:3a7713b1edbc 7757 #define LLWU_F3_MWUF7_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7758 #define LLWU_F3_MWUF7_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7759 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
AnnaBridge 171:3a7713b1edbc 7760
AnnaBridge 171:3a7713b1edbc 7761 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 171:3a7713b1edbc 7762 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7763 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7764 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7765 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 7766 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7767 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 7768 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7769 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7770 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 7771
AnnaBridge 171:3a7713b1edbc 7772 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 171:3a7713b1edbc 7773 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 7774 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7775 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 7776 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 7777 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7778 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 171:3a7713b1edbc 7779 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7780 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7781 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 171:3a7713b1edbc 7782
AnnaBridge 171:3a7713b1edbc 7783 /*! @name RST - LLWU Reset Enable register */
AnnaBridge 171:3a7713b1edbc 7784 #define LLWU_RST_RSTFILT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7785 #define LLWU_RST_RSTFILT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7786 #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
AnnaBridge 171:3a7713b1edbc 7787 #define LLWU_RST_LLRSTE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7788 #define LLWU_RST_LLRSTE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7789 #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
AnnaBridge 171:3a7713b1edbc 7790
AnnaBridge 171:3a7713b1edbc 7791
AnnaBridge 171:3a7713b1edbc 7792 /*!
AnnaBridge 171:3a7713b1edbc 7793 * @}
AnnaBridge 171:3a7713b1edbc 7794 */ /* end of group LLWU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7795
AnnaBridge 171:3a7713b1edbc 7796
AnnaBridge 171:3a7713b1edbc 7797 /* LLWU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7798 /** Peripheral LLWU base address */
AnnaBridge 171:3a7713b1edbc 7799 #define LLWU_BASE (0x4007C000u)
AnnaBridge 171:3a7713b1edbc 7800 /** Peripheral LLWU base pointer */
AnnaBridge 171:3a7713b1edbc 7801 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 171:3a7713b1edbc 7802 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7803 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 171:3a7713b1edbc 7804 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7805 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 171:3a7713b1edbc 7806 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 171:3a7713b1edbc 7807 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 171:3a7713b1edbc 7808
AnnaBridge 171:3a7713b1edbc 7809 /*!
AnnaBridge 171:3a7713b1edbc 7810 * @}
AnnaBridge 171:3a7713b1edbc 7811 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7812
AnnaBridge 171:3a7713b1edbc 7813
AnnaBridge 171:3a7713b1edbc 7814 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7815 -- LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7816 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7817
AnnaBridge 171:3a7713b1edbc 7818 /*!
AnnaBridge 171:3a7713b1edbc 7819 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7820 * @{
AnnaBridge 171:3a7713b1edbc 7821 */
AnnaBridge 171:3a7713b1edbc 7822
AnnaBridge 171:3a7713b1edbc 7823 /** LPTMR - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7824 typedef struct {
AnnaBridge 171:3a7713b1edbc 7825 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7826 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7827 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7828 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7829 } LPTMR_Type;
AnnaBridge 171:3a7713b1edbc 7830
AnnaBridge 171:3a7713b1edbc 7831 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7832 -- LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 7833 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7834
AnnaBridge 171:3a7713b1edbc 7835 /*!
AnnaBridge 171:3a7713b1edbc 7836 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 171:3a7713b1edbc 7837 * @{
AnnaBridge 171:3a7713b1edbc 7838 */
AnnaBridge 171:3a7713b1edbc 7839
AnnaBridge 171:3a7713b1edbc 7840 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 171:3a7713b1edbc 7841 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7842 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7843 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 7844 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7845 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7846 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 171:3a7713b1edbc 7847 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7848 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7849 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 171:3a7713b1edbc 7850 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7851 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7852 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 171:3a7713b1edbc 7853 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 7854 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7855 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 171:3a7713b1edbc 7856 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7857 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7858 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 7859 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7860 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7861 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 7862
AnnaBridge 171:3a7713b1edbc 7863 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 171:3a7713b1edbc 7864 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 7865 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7866 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 7867 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7868 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7869 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 171:3a7713b1edbc 7870 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 171:3a7713b1edbc 7871 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7872 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 171:3a7713b1edbc 7873
AnnaBridge 171:3a7713b1edbc 7874 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 171:3a7713b1edbc 7875 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7876 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7877 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 171:3a7713b1edbc 7878
AnnaBridge 171:3a7713b1edbc 7879 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 171:3a7713b1edbc 7880 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 7881 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7882 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 7883
AnnaBridge 171:3a7713b1edbc 7884
AnnaBridge 171:3a7713b1edbc 7885 /*!
AnnaBridge 171:3a7713b1edbc 7886 * @}
AnnaBridge 171:3a7713b1edbc 7887 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 171:3a7713b1edbc 7888
AnnaBridge 171:3a7713b1edbc 7889
AnnaBridge 171:3a7713b1edbc 7890 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 7891 /** Peripheral LPTMR0 base address */
AnnaBridge 171:3a7713b1edbc 7892 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 171:3a7713b1edbc 7893 /** Peripheral LPTMR0 base pointer */
AnnaBridge 171:3a7713b1edbc 7894 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 171:3a7713b1edbc 7895 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 7896 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
AnnaBridge 171:3a7713b1edbc 7897 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 7898 #define LPTMR_BASE_PTRS { LPTMR0 }
AnnaBridge 171:3a7713b1edbc 7899 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 171:3a7713b1edbc 7900 #define LPTMR_IRQS { LPTMR0_IRQn }
AnnaBridge 171:3a7713b1edbc 7901
AnnaBridge 171:3a7713b1edbc 7902 /*!
AnnaBridge 171:3a7713b1edbc 7903 * @}
AnnaBridge 171:3a7713b1edbc 7904 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 7905
AnnaBridge 171:3a7713b1edbc 7906
AnnaBridge 171:3a7713b1edbc 7907 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7908 -- MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7909 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7910
AnnaBridge 171:3a7713b1edbc 7911 /*!
AnnaBridge 171:3a7713b1edbc 7912 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 7913 * @{
AnnaBridge 171:3a7713b1edbc 7914 */
AnnaBridge 171:3a7713b1edbc 7915
AnnaBridge 171:3a7713b1edbc 7916 /** MCG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 7917 typedef struct {
AnnaBridge 171:3a7713b1edbc 7918 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 7919 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 7920 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 7921 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 7922 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 7923 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 7924 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 7925 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 7926 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 7927 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 7928 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 7929 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 7930 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 7931 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 7932 } MCG_Type;
AnnaBridge 171:3a7713b1edbc 7933
AnnaBridge 171:3a7713b1edbc 7934 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 7935 -- MCG Register Masks
AnnaBridge 171:3a7713b1edbc 7936 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 7937
AnnaBridge 171:3a7713b1edbc 7938 /*!
AnnaBridge 171:3a7713b1edbc 7939 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 171:3a7713b1edbc 7940 * @{
AnnaBridge 171:3a7713b1edbc 7941 */
AnnaBridge 171:3a7713b1edbc 7942
AnnaBridge 171:3a7713b1edbc 7943 /*! @name C1 - MCG Control 1 Register */
AnnaBridge 171:3a7713b1edbc 7944 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7945 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7946 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 7947 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7948 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7949 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 7950 #define MCG_C1_IREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7951 #define MCG_C1_IREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7952 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
AnnaBridge 171:3a7713b1edbc 7953 #define MCG_C1_FRDIV_MASK (0x38U)
AnnaBridge 171:3a7713b1edbc 7954 #define MCG_C1_FRDIV_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7955 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 7956 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 7957 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7958 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 171:3a7713b1edbc 7959
AnnaBridge 171:3a7713b1edbc 7960 /*! @name C2 - MCG Control 2 Register */
AnnaBridge 171:3a7713b1edbc 7961 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7962 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7963 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 171:3a7713b1edbc 7964 #define MCG_C2_LP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 7965 #define MCG_C2_LP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7966 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
AnnaBridge 171:3a7713b1edbc 7967 #define MCG_C2_EREFS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 7968 #define MCG_C2_EREFS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 7969 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
AnnaBridge 171:3a7713b1edbc 7970 #define MCG_C2_HGO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 7971 #define MCG_C2_HGO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 7972 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
AnnaBridge 171:3a7713b1edbc 7973 #define MCG_C2_RANGE_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 7974 #define MCG_C2_RANGE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 7975 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
AnnaBridge 171:3a7713b1edbc 7976 #define MCG_C2_FCFTRIM_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 7977 #define MCG_C2_FCFTRIM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 7978 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7979 #define MCG_C2_LOCRE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7980 #define MCG_C2_LOCRE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 7981 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
AnnaBridge 171:3a7713b1edbc 7982
AnnaBridge 171:3a7713b1edbc 7983 /*! @name C3 - MCG Control 3 Register */
AnnaBridge 171:3a7713b1edbc 7984 #define MCG_C3_SCTRIM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 7985 #define MCG_C3_SCTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7986 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7987
AnnaBridge 171:3a7713b1edbc 7988 /*! @name C4 - MCG Control 4 Register */
AnnaBridge 171:3a7713b1edbc 7989 #define MCG_C4_SCFTRIM_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 7990 #define MCG_C4_SCFTRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 7991 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7992 #define MCG_C4_FCTRIM_MASK (0x1EU)
AnnaBridge 171:3a7713b1edbc 7993 #define MCG_C4_FCTRIM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 7994 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
AnnaBridge 171:3a7713b1edbc 7995 #define MCG_C4_DRST_DRS_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 7996 #define MCG_C4_DRST_DRS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 7997 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
AnnaBridge 171:3a7713b1edbc 7998 #define MCG_C4_DMX32_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 7999 #define MCG_C4_DMX32_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8000 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
AnnaBridge 171:3a7713b1edbc 8001
AnnaBridge 171:3a7713b1edbc 8002 /*! @name C5 - MCG Control 5 Register */
AnnaBridge 171:3a7713b1edbc 8003 #define MCG_C5_PRDIV0_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8004 #define MCG_C5_PRDIV0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8005 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 8006 #define MCG_C5_PLLSTEN0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8007 #define MCG_C5_PLLSTEN0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8008 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
AnnaBridge 171:3a7713b1edbc 8009 #define MCG_C5_PLLCLKEN0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8010 #define MCG_C5_PLLCLKEN0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8011 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
AnnaBridge 171:3a7713b1edbc 8012
AnnaBridge 171:3a7713b1edbc 8013 /*! @name C6 - MCG Control 6 Register */
AnnaBridge 171:3a7713b1edbc 8014 #define MCG_C6_VDIV0_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8015 #define MCG_C6_VDIV0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8016 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
AnnaBridge 171:3a7713b1edbc 8017 #define MCG_C6_CME0_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8018 #define MCG_C6_CME0_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8019 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
AnnaBridge 171:3a7713b1edbc 8020 #define MCG_C6_PLLS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8021 #define MCG_C6_PLLS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8022 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
AnnaBridge 171:3a7713b1edbc 8023 #define MCG_C6_LOLIE0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8024 #define MCG_C6_LOLIE0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8025 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
AnnaBridge 171:3a7713b1edbc 8026
AnnaBridge 171:3a7713b1edbc 8027 /*! @name S - MCG Status Register */
AnnaBridge 171:3a7713b1edbc 8028 #define MCG_S_IRCST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8029 #define MCG_S_IRCST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8030 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
AnnaBridge 171:3a7713b1edbc 8031 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8032 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8033 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 171:3a7713b1edbc 8034 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8035 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8036 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 171:3a7713b1edbc 8037 #define MCG_S_IREFST_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8038 #define MCG_S_IREFST_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8039 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
AnnaBridge 171:3a7713b1edbc 8040 #define MCG_S_PLLST_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8041 #define MCG_S_PLLST_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8042 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
AnnaBridge 171:3a7713b1edbc 8043 #define MCG_S_LOCK0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8044 #define MCG_S_LOCK0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8045 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
AnnaBridge 171:3a7713b1edbc 8046 #define MCG_S_LOLS0_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8047 #define MCG_S_LOLS0_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8048 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
AnnaBridge 171:3a7713b1edbc 8049
AnnaBridge 171:3a7713b1edbc 8050 /*! @name SC - MCG Status and Control Register */
AnnaBridge 171:3a7713b1edbc 8051 #define MCG_SC_LOCS0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8052 #define MCG_SC_LOCS0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8053 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
AnnaBridge 171:3a7713b1edbc 8054 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 8055 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8056 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 171:3a7713b1edbc 8057 #define MCG_SC_FLTPRSRV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8058 #define MCG_SC_FLTPRSRV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8059 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
AnnaBridge 171:3a7713b1edbc 8060 #define MCG_SC_ATMF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8061 #define MCG_SC_ATMF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8062 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
AnnaBridge 171:3a7713b1edbc 8063 #define MCG_SC_ATMS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8064 #define MCG_SC_ATMS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8065 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
AnnaBridge 171:3a7713b1edbc 8066 #define MCG_SC_ATME_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8067 #define MCG_SC_ATME_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8068 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
AnnaBridge 171:3a7713b1edbc 8069
AnnaBridge 171:3a7713b1edbc 8070 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
AnnaBridge 171:3a7713b1edbc 8071 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8072 #define MCG_ATCVH_ATCVH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8073 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
AnnaBridge 171:3a7713b1edbc 8074
AnnaBridge 171:3a7713b1edbc 8075 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
AnnaBridge 171:3a7713b1edbc 8076 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8077 #define MCG_ATCVL_ATCVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8078 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
AnnaBridge 171:3a7713b1edbc 8079
AnnaBridge 171:3a7713b1edbc 8080 /*! @name C7 - MCG Control 7 Register */
AnnaBridge 171:3a7713b1edbc 8081 #define MCG_C7_OSCSEL_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8082 #define MCG_C7_OSCSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8083 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8084
AnnaBridge 171:3a7713b1edbc 8085 /*! @name C8 - MCG Control 8 Register */
AnnaBridge 171:3a7713b1edbc 8086 #define MCG_C8_LOCS1_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8087 #define MCG_C8_LOCS1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8088 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
AnnaBridge 171:3a7713b1edbc 8089 #define MCG_C8_CME1_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8090 #define MCG_C8_CME1_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8091 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
AnnaBridge 171:3a7713b1edbc 8092 #define MCG_C8_LOLRE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8093 #define MCG_C8_LOLRE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8094 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
AnnaBridge 171:3a7713b1edbc 8095 #define MCG_C8_LOCRE1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8096 #define MCG_C8_LOCRE1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8097 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
AnnaBridge 171:3a7713b1edbc 8098
AnnaBridge 171:3a7713b1edbc 8099
AnnaBridge 171:3a7713b1edbc 8100 /*!
AnnaBridge 171:3a7713b1edbc 8101 * @}
AnnaBridge 171:3a7713b1edbc 8102 */ /* end of group MCG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8103
AnnaBridge 171:3a7713b1edbc 8104
AnnaBridge 171:3a7713b1edbc 8105 /* MCG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8106 /** Peripheral MCG base address */
AnnaBridge 171:3a7713b1edbc 8107 #define MCG_BASE (0x40064000u)
AnnaBridge 171:3a7713b1edbc 8108 /** Peripheral MCG base pointer */
AnnaBridge 171:3a7713b1edbc 8109 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 171:3a7713b1edbc 8110 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8111 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 171:3a7713b1edbc 8112 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8113 #define MCG_BASE_PTRS { MCG }
AnnaBridge 171:3a7713b1edbc 8114
AnnaBridge 171:3a7713b1edbc 8115 /*!
AnnaBridge 171:3a7713b1edbc 8116 * @}
AnnaBridge 171:3a7713b1edbc 8117 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8118
AnnaBridge 171:3a7713b1edbc 8119
AnnaBridge 171:3a7713b1edbc 8120 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8121 -- MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8122 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8123
AnnaBridge 171:3a7713b1edbc 8124 /*!
AnnaBridge 171:3a7713b1edbc 8125 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8126 * @{
AnnaBridge 171:3a7713b1edbc 8127 */
AnnaBridge 171:3a7713b1edbc 8128
AnnaBridge 171:3a7713b1edbc 8129 /** MCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8130 typedef struct {
AnnaBridge 171:3a7713b1edbc 8131 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 8132 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8133 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 8134 __IO uint32_t CR; /**< Control Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8135 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 8136 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 8137 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 8138 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 8139 uint8_t RESERVED_1[16];
AnnaBridge 171:3a7713b1edbc 8140 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 8141 } MCM_Type;
AnnaBridge 171:3a7713b1edbc 8142
AnnaBridge 171:3a7713b1edbc 8143 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8144 -- MCM Register Masks
AnnaBridge 171:3a7713b1edbc 8145 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8146
AnnaBridge 171:3a7713b1edbc 8147 /*!
AnnaBridge 171:3a7713b1edbc 8148 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 171:3a7713b1edbc 8149 * @{
AnnaBridge 171:3a7713b1edbc 8150 */
AnnaBridge 171:3a7713b1edbc 8151
AnnaBridge 171:3a7713b1edbc 8152 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 171:3a7713b1edbc 8153 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8154 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8155 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 8156
AnnaBridge 171:3a7713b1edbc 8157 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 171:3a7713b1edbc 8158 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8159 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8160 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 171:3a7713b1edbc 8161
AnnaBridge 171:3a7713b1edbc 8162 /*! @name CR - Control Register */
AnnaBridge 171:3a7713b1edbc 8163 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
AnnaBridge 171:3a7713b1edbc 8164 #define MCM_CR_SRAMUAP_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8165 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
AnnaBridge 171:3a7713b1edbc 8166 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 8167 #define MCM_CR_SRAMUWP_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8168 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
AnnaBridge 171:3a7713b1edbc 8169 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 8170 #define MCM_CR_SRAMLAP_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8171 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
AnnaBridge 171:3a7713b1edbc 8172 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 8173 #define MCM_CR_SRAMLWP_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 8174 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
AnnaBridge 171:3a7713b1edbc 8175
AnnaBridge 171:3a7713b1edbc 8176 /*! @name ISCR - Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 8177 #define MCM_ISCR_IRQ_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8178 #define MCM_ISCR_IRQ_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8179 #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
AnnaBridge 171:3a7713b1edbc 8180 #define MCM_ISCR_NMI_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8181 #define MCM_ISCR_NMI_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8182 #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
AnnaBridge 171:3a7713b1edbc 8183 #define MCM_ISCR_DHREQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8184 #define MCM_ISCR_DHREQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8185 #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
AnnaBridge 171:3a7713b1edbc 8186 #define MCM_ISCR_FIOC_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 8187 #define MCM_ISCR_FIOC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8188 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
AnnaBridge 171:3a7713b1edbc 8189 #define MCM_ISCR_FDZC_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 8190 #define MCM_ISCR_FDZC_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 8191 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
AnnaBridge 171:3a7713b1edbc 8192 #define MCM_ISCR_FOFC_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 8193 #define MCM_ISCR_FOFC_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 8194 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
AnnaBridge 171:3a7713b1edbc 8195 #define MCM_ISCR_FUFC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 8196 #define MCM_ISCR_FUFC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 8197 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
AnnaBridge 171:3a7713b1edbc 8198 #define MCM_ISCR_FIXC_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 8199 #define MCM_ISCR_FIXC_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8200 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
AnnaBridge 171:3a7713b1edbc 8201 #define MCM_ISCR_FIDC_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8202 #define MCM_ISCR_FIDC_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8203 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
AnnaBridge 171:3a7713b1edbc 8204 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8205 #define MCM_ISCR_FIOCE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8206 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
AnnaBridge 171:3a7713b1edbc 8207 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 8208 #define MCM_ISCR_FDZCE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 8209 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
AnnaBridge 171:3a7713b1edbc 8210 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 8211 #define MCM_ISCR_FOFCE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 8212 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
AnnaBridge 171:3a7713b1edbc 8213 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 8214 #define MCM_ISCR_FUFCE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 8215 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
AnnaBridge 171:3a7713b1edbc 8216 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 8217 #define MCM_ISCR_FIXCE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 8218 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
AnnaBridge 171:3a7713b1edbc 8219 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 8220 #define MCM_ISCR_FIDCE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 8221 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
AnnaBridge 171:3a7713b1edbc 8222
AnnaBridge 171:3a7713b1edbc 8223 /*! @name ETBCC - ETB Counter Control register */
AnnaBridge 171:3a7713b1edbc 8224 #define MCM_ETBCC_CNTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8225 #define MCM_ETBCC_CNTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8226 #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
AnnaBridge 171:3a7713b1edbc 8227 #define MCM_ETBCC_RSPT_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 8228 #define MCM_ETBCC_RSPT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8229 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
AnnaBridge 171:3a7713b1edbc 8230 #define MCM_ETBCC_RLRQ_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8231 #define MCM_ETBCC_RLRQ_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8232 #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
AnnaBridge 171:3a7713b1edbc 8233 #define MCM_ETBCC_ETDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8234 #define MCM_ETBCC_ETDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8235 #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
AnnaBridge 171:3a7713b1edbc 8236 #define MCM_ETBCC_ITDIS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8237 #define MCM_ETBCC_ITDIS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8238 #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
AnnaBridge 171:3a7713b1edbc 8239
AnnaBridge 171:3a7713b1edbc 8240 /*! @name ETBRL - ETB Reload register */
AnnaBridge 171:3a7713b1edbc 8241 #define MCM_ETBRL_RELOAD_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 8242 #define MCM_ETBRL_RELOAD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8243 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
AnnaBridge 171:3a7713b1edbc 8244
AnnaBridge 171:3a7713b1edbc 8245 /*! @name ETBCNT - ETB Counter Value register */
AnnaBridge 171:3a7713b1edbc 8246 #define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
AnnaBridge 171:3a7713b1edbc 8247 #define MCM_ETBCNT_COUNTER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8248 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
AnnaBridge 171:3a7713b1edbc 8249
AnnaBridge 171:3a7713b1edbc 8250 /*! @name PID - Process ID register */
AnnaBridge 171:3a7713b1edbc 8251 #define MCM_PID_PID_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8252 #define MCM_PID_PID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8253 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
AnnaBridge 171:3a7713b1edbc 8254
AnnaBridge 171:3a7713b1edbc 8255
AnnaBridge 171:3a7713b1edbc 8256 /*!
AnnaBridge 171:3a7713b1edbc 8257 * @}
AnnaBridge 171:3a7713b1edbc 8258 */ /* end of group MCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8259
AnnaBridge 171:3a7713b1edbc 8260
AnnaBridge 171:3a7713b1edbc 8261 /* MCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8262 /** Peripheral MCM base address */
AnnaBridge 171:3a7713b1edbc 8263 #define MCM_BASE (0xE0080000u)
AnnaBridge 171:3a7713b1edbc 8264 /** Peripheral MCM base pointer */
AnnaBridge 171:3a7713b1edbc 8265 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 171:3a7713b1edbc 8266 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8267 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 171:3a7713b1edbc 8268 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8269 #define MCM_BASE_PTRS { MCM }
AnnaBridge 171:3a7713b1edbc 8270 /** Interrupt vectors for the MCM peripheral type */
AnnaBridge 171:3a7713b1edbc 8271 #define MCM_IRQS { MCM_IRQn }
AnnaBridge 171:3a7713b1edbc 8272
AnnaBridge 171:3a7713b1edbc 8273 /*!
AnnaBridge 171:3a7713b1edbc 8274 * @}
AnnaBridge 171:3a7713b1edbc 8275 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8276
AnnaBridge 171:3a7713b1edbc 8277
AnnaBridge 171:3a7713b1edbc 8278 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8279 -- NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8280 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8281
AnnaBridge 171:3a7713b1edbc 8282 /*!
AnnaBridge 171:3a7713b1edbc 8283 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8284 * @{
AnnaBridge 171:3a7713b1edbc 8285 */
AnnaBridge 171:3a7713b1edbc 8286
AnnaBridge 171:3a7713b1edbc 8287 /** NV - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8288 typedef struct {
AnnaBridge 171:3a7713b1edbc 8289 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8290 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 8291 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 8292 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 8293 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8294 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 8295 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 8296 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 8297 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8298 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 8299 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 8300 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 8301 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8302 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 8303 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 8304 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
AnnaBridge 171:3a7713b1edbc 8305 } NV_Type;
AnnaBridge 171:3a7713b1edbc 8306
AnnaBridge 171:3a7713b1edbc 8307 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8308 -- NV Register Masks
AnnaBridge 171:3a7713b1edbc 8309 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8310
AnnaBridge 171:3a7713b1edbc 8311 /*!
AnnaBridge 171:3a7713b1edbc 8312 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 171:3a7713b1edbc 8313 * @{
AnnaBridge 171:3a7713b1edbc 8314 */
AnnaBridge 171:3a7713b1edbc 8315
AnnaBridge 171:3a7713b1edbc 8316 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 171:3a7713b1edbc 8317 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8318 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8319 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8320
AnnaBridge 171:3a7713b1edbc 8321 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 171:3a7713b1edbc 8322 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8323 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8324 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8325
AnnaBridge 171:3a7713b1edbc 8326 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 171:3a7713b1edbc 8327 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8328 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8329 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8330
AnnaBridge 171:3a7713b1edbc 8331 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 171:3a7713b1edbc 8332 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8333 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8334 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8335
AnnaBridge 171:3a7713b1edbc 8336 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 171:3a7713b1edbc 8337 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8338 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8339 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8340
AnnaBridge 171:3a7713b1edbc 8341 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 171:3a7713b1edbc 8342 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8343 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8344 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8345
AnnaBridge 171:3a7713b1edbc 8346 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 171:3a7713b1edbc 8347 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8348 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8349 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8350
AnnaBridge 171:3a7713b1edbc 8351 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 171:3a7713b1edbc 8352 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8353 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8354 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 171:3a7713b1edbc 8355
AnnaBridge 171:3a7713b1edbc 8356 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 171:3a7713b1edbc 8357 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8358 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8359 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 8360
AnnaBridge 171:3a7713b1edbc 8361 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 171:3a7713b1edbc 8362 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8363 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8364 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 8365
AnnaBridge 171:3a7713b1edbc 8366 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 171:3a7713b1edbc 8367 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8368 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8369 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 8370
AnnaBridge 171:3a7713b1edbc 8371 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 171:3a7713b1edbc 8372 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8373 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8374 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 171:3a7713b1edbc 8375
AnnaBridge 171:3a7713b1edbc 8376 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 171:3a7713b1edbc 8377 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8378 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8379 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 171:3a7713b1edbc 8380 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8381 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8382 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 171:3a7713b1edbc 8383 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 8384 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8385 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 171:3a7713b1edbc 8386 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 8387 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8388 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 171:3a7713b1edbc 8389
AnnaBridge 171:3a7713b1edbc 8390 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 171:3a7713b1edbc 8391 #define NV_FOPT_LPBOOT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8392 #define NV_FOPT_LPBOOT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8393 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
AnnaBridge 171:3a7713b1edbc 8394 #define NV_FOPT_EZPORT_DIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8395 #define NV_FOPT_EZPORT_DIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8396 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
AnnaBridge 171:3a7713b1edbc 8397
AnnaBridge 171:3a7713b1edbc 8398 /*! @name FEPROT - Non-volatile EERAM Protection Register */
AnnaBridge 171:3a7713b1edbc 8399 #define NV_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8400 #define NV_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8401 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
AnnaBridge 171:3a7713b1edbc 8402
AnnaBridge 171:3a7713b1edbc 8403 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
AnnaBridge 171:3a7713b1edbc 8404 #define NV_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8405 #define NV_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8406 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
AnnaBridge 171:3a7713b1edbc 8407
AnnaBridge 171:3a7713b1edbc 8408
AnnaBridge 171:3a7713b1edbc 8409 /*!
AnnaBridge 171:3a7713b1edbc 8410 * @}
AnnaBridge 171:3a7713b1edbc 8411 */ /* end of group NV_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8412
AnnaBridge 171:3a7713b1edbc 8413
AnnaBridge 171:3a7713b1edbc 8414 /* NV - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8415 /** Peripheral FTFE_FlashConfig base address */
AnnaBridge 171:3a7713b1edbc 8416 #define FTFE_FlashConfig_BASE (0x400u)
AnnaBridge 171:3a7713b1edbc 8417 /** Peripheral FTFE_FlashConfig base pointer */
AnnaBridge 171:3a7713b1edbc 8418 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
AnnaBridge 171:3a7713b1edbc 8419 /** Array initializer of NV peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8420 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
AnnaBridge 171:3a7713b1edbc 8421 /** Array initializer of NV peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8422 #define NV_BASE_PTRS { FTFE_FlashConfig }
AnnaBridge 171:3a7713b1edbc 8423
AnnaBridge 171:3a7713b1edbc 8424 /*!
AnnaBridge 171:3a7713b1edbc 8425 * @}
AnnaBridge 171:3a7713b1edbc 8426 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8427
AnnaBridge 171:3a7713b1edbc 8428
AnnaBridge 171:3a7713b1edbc 8429 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8430 -- OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8431 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8432
AnnaBridge 171:3a7713b1edbc 8433 /*!
AnnaBridge 171:3a7713b1edbc 8434 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8435 * @{
AnnaBridge 171:3a7713b1edbc 8436 */
AnnaBridge 171:3a7713b1edbc 8437
AnnaBridge 171:3a7713b1edbc 8438 /** OSC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8439 typedef struct {
AnnaBridge 171:3a7713b1edbc 8440 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8441 } OSC_Type;
AnnaBridge 171:3a7713b1edbc 8442
AnnaBridge 171:3a7713b1edbc 8443 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8444 -- OSC Register Masks
AnnaBridge 171:3a7713b1edbc 8445 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8446
AnnaBridge 171:3a7713b1edbc 8447 /*!
AnnaBridge 171:3a7713b1edbc 8448 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 171:3a7713b1edbc 8449 * @{
AnnaBridge 171:3a7713b1edbc 8450 */
AnnaBridge 171:3a7713b1edbc 8451
AnnaBridge 171:3a7713b1edbc 8452 /*! @name CR - OSC Control Register */
AnnaBridge 171:3a7713b1edbc 8453 #define OSC_CR_SC16P_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8454 #define OSC_CR_SC16P_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8455 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 8456 #define OSC_CR_SC8P_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8457 #define OSC_CR_SC8P_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8458 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 8459 #define OSC_CR_SC4P_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8460 #define OSC_CR_SC4P_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8461 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 8462 #define OSC_CR_SC2P_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8463 #define OSC_CR_SC2P_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8464 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 8465 #define OSC_CR_EREFSTEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8466 #define OSC_CR_EREFSTEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8467 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 8468 #define OSC_CR_ERCLKEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8469 #define OSC_CR_ERCLKEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8470 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 8471
AnnaBridge 171:3a7713b1edbc 8472
AnnaBridge 171:3a7713b1edbc 8473 /*!
AnnaBridge 171:3a7713b1edbc 8474 * @}
AnnaBridge 171:3a7713b1edbc 8475 */ /* end of group OSC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8476
AnnaBridge 171:3a7713b1edbc 8477
AnnaBridge 171:3a7713b1edbc 8478 /* OSC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8479 /** Peripheral OSC base address */
AnnaBridge 171:3a7713b1edbc 8480 #define OSC_BASE (0x40065000u)
AnnaBridge 171:3a7713b1edbc 8481 /** Peripheral OSC base pointer */
AnnaBridge 171:3a7713b1edbc 8482 #define OSC ((OSC_Type *)OSC_BASE)
AnnaBridge 171:3a7713b1edbc 8483 /** Array initializer of OSC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8484 #define OSC_BASE_ADDRS { OSC_BASE }
AnnaBridge 171:3a7713b1edbc 8485 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8486 #define OSC_BASE_PTRS { OSC }
AnnaBridge 171:3a7713b1edbc 8487
AnnaBridge 171:3a7713b1edbc 8488 /*!
AnnaBridge 171:3a7713b1edbc 8489 * @}
AnnaBridge 171:3a7713b1edbc 8490 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8491
AnnaBridge 171:3a7713b1edbc 8492
AnnaBridge 171:3a7713b1edbc 8493 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8494 -- PDB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8495 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8496
AnnaBridge 171:3a7713b1edbc 8497 /*!
AnnaBridge 171:3a7713b1edbc 8498 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8499 * @{
AnnaBridge 171:3a7713b1edbc 8500 */
AnnaBridge 171:3a7713b1edbc 8501
AnnaBridge 171:3a7713b1edbc 8502 /** PDB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8503 typedef struct {
AnnaBridge 171:3a7713b1edbc 8504 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8505 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 8506 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 8507 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 8508 struct { /* offset: 0x10, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 8509 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 8510 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
AnnaBridge 171:3a7713b1edbc 8511 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
AnnaBridge 171:3a7713b1edbc 8512 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 8513 } CH[2];
AnnaBridge 171:3a7713b1edbc 8514 uint8_t RESERVED_0[240];
AnnaBridge 171:3a7713b1edbc 8515 struct { /* offset: 0x150, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 8516 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 8517 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 8518 } DAC[2];
AnnaBridge 171:3a7713b1edbc 8519 uint8_t RESERVED_1[48];
AnnaBridge 171:3a7713b1edbc 8520 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
AnnaBridge 171:3a7713b1edbc 8521 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 8522 } PDB_Type;
AnnaBridge 171:3a7713b1edbc 8523
AnnaBridge 171:3a7713b1edbc 8524 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8525 -- PDB Register Masks
AnnaBridge 171:3a7713b1edbc 8526 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8527
AnnaBridge 171:3a7713b1edbc 8528 /*!
AnnaBridge 171:3a7713b1edbc 8529 * @addtogroup PDB_Register_Masks PDB Register Masks
AnnaBridge 171:3a7713b1edbc 8530 * @{
AnnaBridge 171:3a7713b1edbc 8531 */
AnnaBridge 171:3a7713b1edbc 8532
AnnaBridge 171:3a7713b1edbc 8533 /*! @name SC - Status and Control register */
AnnaBridge 171:3a7713b1edbc 8534 #define PDB_SC_LDOK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8535 #define PDB_SC_LDOK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8536 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
AnnaBridge 171:3a7713b1edbc 8537 #define PDB_SC_CONT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8538 #define PDB_SC_CONT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8539 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 8540 #define PDB_SC_MULT_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 8541 #define PDB_SC_MULT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8542 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
AnnaBridge 171:3a7713b1edbc 8543 #define PDB_SC_PDBIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8544 #define PDB_SC_PDBIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8545 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
AnnaBridge 171:3a7713b1edbc 8546 #define PDB_SC_PDBIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8547 #define PDB_SC_PDBIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8548 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
AnnaBridge 171:3a7713b1edbc 8549 #define PDB_SC_PDBEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8550 #define PDB_SC_PDBEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8551 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
AnnaBridge 171:3a7713b1edbc 8552 #define PDB_SC_TRGSEL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 8553 #define PDB_SC_TRGSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8554 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 8555 #define PDB_SC_PRESCALER_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 8556 #define PDB_SC_PRESCALER_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 8557 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
AnnaBridge 171:3a7713b1edbc 8558 #define PDB_SC_DMAEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8559 #define PDB_SC_DMAEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8560 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 8561 #define PDB_SC_SWTRIG_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 8562 #define PDB_SC_SWTRIG_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8563 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
AnnaBridge 171:3a7713b1edbc 8564 #define PDB_SC_PDBEIE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 8565 #define PDB_SC_PDBEIE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 8566 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
AnnaBridge 171:3a7713b1edbc 8567 #define PDB_SC_LDMOD_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 8568 #define PDB_SC_LDMOD_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 8569 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
AnnaBridge 171:3a7713b1edbc 8570
AnnaBridge 171:3a7713b1edbc 8571 /*! @name MOD - Modulus register */
AnnaBridge 171:3a7713b1edbc 8572 #define PDB_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8573 #define PDB_MOD_MOD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8574 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
AnnaBridge 171:3a7713b1edbc 8575
AnnaBridge 171:3a7713b1edbc 8576 /*! @name CNT - Counter register */
AnnaBridge 171:3a7713b1edbc 8577 #define PDB_CNT_CNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8578 #define PDB_CNT_CNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8579 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 8580
AnnaBridge 171:3a7713b1edbc 8581 /*! @name IDLY - Interrupt Delay register */
AnnaBridge 171:3a7713b1edbc 8582 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8583 #define PDB_IDLY_IDLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8584 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
AnnaBridge 171:3a7713b1edbc 8585
AnnaBridge 171:3a7713b1edbc 8586 /*! @name C1 - Channel n Control register 1 */
AnnaBridge 171:3a7713b1edbc 8587 #define PDB_C1_EN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8588 #define PDB_C1_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8589 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
AnnaBridge 171:3a7713b1edbc 8590 #define PDB_C1_TOS_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 8591 #define PDB_C1_TOS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8592 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
AnnaBridge 171:3a7713b1edbc 8593 #define PDB_C1_BB_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 8594 #define PDB_C1_BB_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8595 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
AnnaBridge 171:3a7713b1edbc 8596
AnnaBridge 171:3a7713b1edbc 8597 /* The count of PDB_C1 */
AnnaBridge 171:3a7713b1edbc 8598 #define PDB_C1_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8599
AnnaBridge 171:3a7713b1edbc 8600 /*! @name S - Channel n Status register */
AnnaBridge 171:3a7713b1edbc 8601 #define PDB_S_ERR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8602 #define PDB_S_ERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8603 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 8604 #define PDB_S_CF_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 8605 #define PDB_S_CF_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8606 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
AnnaBridge 171:3a7713b1edbc 8607
AnnaBridge 171:3a7713b1edbc 8608 /* The count of PDB_S */
AnnaBridge 171:3a7713b1edbc 8609 #define PDB_S_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8610
AnnaBridge 171:3a7713b1edbc 8611 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
AnnaBridge 171:3a7713b1edbc 8612 #define PDB_DLY_DLY_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8613 #define PDB_DLY_DLY_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8614 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
AnnaBridge 171:3a7713b1edbc 8615
AnnaBridge 171:3a7713b1edbc 8616 /* The count of PDB_DLY */
AnnaBridge 171:3a7713b1edbc 8617 #define PDB_DLY_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8618
AnnaBridge 171:3a7713b1edbc 8619 /* The count of PDB_DLY */
AnnaBridge 171:3a7713b1edbc 8620 #define PDB_DLY_COUNT2 (2U)
AnnaBridge 171:3a7713b1edbc 8621
AnnaBridge 171:3a7713b1edbc 8622 /*! @name INTC - DAC Interval Trigger n Control register */
AnnaBridge 171:3a7713b1edbc 8623 #define PDB_INTC_TOE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8624 #define PDB_INTC_TOE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8625 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
AnnaBridge 171:3a7713b1edbc 8626 #define PDB_INTC_EXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8627 #define PDB_INTC_EXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8628 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
AnnaBridge 171:3a7713b1edbc 8629
AnnaBridge 171:3a7713b1edbc 8630 /* The count of PDB_INTC */
AnnaBridge 171:3a7713b1edbc 8631 #define PDB_INTC_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8632
AnnaBridge 171:3a7713b1edbc 8633 /*! @name INT - DAC Interval n register */
AnnaBridge 171:3a7713b1edbc 8634 #define PDB_INT_INT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8635 #define PDB_INT_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8636 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
AnnaBridge 171:3a7713b1edbc 8637
AnnaBridge 171:3a7713b1edbc 8638 /* The count of PDB_INT */
AnnaBridge 171:3a7713b1edbc 8639 #define PDB_INT_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 8640
AnnaBridge 171:3a7713b1edbc 8641 /*! @name POEN - Pulse-Out n Enable register */
AnnaBridge 171:3a7713b1edbc 8642 #define PDB_POEN_POEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 8643 #define PDB_POEN_POEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8644 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
AnnaBridge 171:3a7713b1edbc 8645
AnnaBridge 171:3a7713b1edbc 8646 /*! @name PODLY - Pulse-Out n Delay register */
AnnaBridge 171:3a7713b1edbc 8647 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8648 #define PDB_PODLY_DLY2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8649 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
AnnaBridge 171:3a7713b1edbc 8650 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 8651 #define PDB_PODLY_DLY1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8652 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
AnnaBridge 171:3a7713b1edbc 8653
AnnaBridge 171:3a7713b1edbc 8654 /* The count of PDB_PODLY */
AnnaBridge 171:3a7713b1edbc 8655 #define PDB_PODLY_COUNT (3U)
AnnaBridge 171:3a7713b1edbc 8656
AnnaBridge 171:3a7713b1edbc 8657
AnnaBridge 171:3a7713b1edbc 8658 /*!
AnnaBridge 171:3a7713b1edbc 8659 * @}
AnnaBridge 171:3a7713b1edbc 8660 */ /* end of group PDB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8661
AnnaBridge 171:3a7713b1edbc 8662
AnnaBridge 171:3a7713b1edbc 8663 /* PDB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8664 /** Peripheral PDB0 base address */
AnnaBridge 171:3a7713b1edbc 8665 #define PDB0_BASE (0x40036000u)
AnnaBridge 171:3a7713b1edbc 8666 /** Peripheral PDB0 base pointer */
AnnaBridge 171:3a7713b1edbc 8667 #define PDB0 ((PDB_Type *)PDB0_BASE)
AnnaBridge 171:3a7713b1edbc 8668 /** Array initializer of PDB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8669 #define PDB_BASE_ADDRS { PDB0_BASE }
AnnaBridge 171:3a7713b1edbc 8670 /** Array initializer of PDB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8671 #define PDB_BASE_PTRS { PDB0 }
AnnaBridge 171:3a7713b1edbc 8672 /** Interrupt vectors for the PDB peripheral type */
AnnaBridge 171:3a7713b1edbc 8673 #define PDB_IRQS { PDB0_IRQn }
AnnaBridge 171:3a7713b1edbc 8674
AnnaBridge 171:3a7713b1edbc 8675 /*!
AnnaBridge 171:3a7713b1edbc 8676 * @}
AnnaBridge 171:3a7713b1edbc 8677 */ /* end of group PDB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8678
AnnaBridge 171:3a7713b1edbc 8679
AnnaBridge 171:3a7713b1edbc 8680 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8681 -- PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8682 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8683
AnnaBridge 171:3a7713b1edbc 8684 /*!
AnnaBridge 171:3a7713b1edbc 8685 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8686 * @{
AnnaBridge 171:3a7713b1edbc 8687 */
AnnaBridge 171:3a7713b1edbc 8688
AnnaBridge 171:3a7713b1edbc 8689 /** PIT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8690 typedef struct {
AnnaBridge 171:3a7713b1edbc 8691 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8692 uint8_t RESERVED_0[252];
AnnaBridge 171:3a7713b1edbc 8693 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 8694 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 8695 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 8696 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 8697 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 171:3a7713b1edbc 8698 } CHANNEL[4];
AnnaBridge 171:3a7713b1edbc 8699 } PIT_Type;
AnnaBridge 171:3a7713b1edbc 8700
AnnaBridge 171:3a7713b1edbc 8701 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8702 -- PIT Register Masks
AnnaBridge 171:3a7713b1edbc 8703 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8704
AnnaBridge 171:3a7713b1edbc 8705 /*!
AnnaBridge 171:3a7713b1edbc 8706 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 171:3a7713b1edbc 8707 * @{
AnnaBridge 171:3a7713b1edbc 8708 */
AnnaBridge 171:3a7713b1edbc 8709
AnnaBridge 171:3a7713b1edbc 8710 /*! @name MCR - PIT Module Control Register */
AnnaBridge 171:3a7713b1edbc 8711 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8712 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8713 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 8714 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8715 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8716 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 8717
AnnaBridge 171:3a7713b1edbc 8718 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 171:3a7713b1edbc 8719 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8720 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8721 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 171:3a7713b1edbc 8722
AnnaBridge 171:3a7713b1edbc 8723 /* The count of PIT_LDVAL */
AnnaBridge 171:3a7713b1edbc 8724 #define PIT_LDVAL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 8725
AnnaBridge 171:3a7713b1edbc 8726 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 171:3a7713b1edbc 8727 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8728 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8729 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 171:3a7713b1edbc 8730
AnnaBridge 171:3a7713b1edbc 8731 /* The count of PIT_CVAL */
AnnaBridge 171:3a7713b1edbc 8732 #define PIT_CVAL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 8733
AnnaBridge 171:3a7713b1edbc 8734 /*! @name TCTRL - Timer Control Register */
AnnaBridge 171:3a7713b1edbc 8735 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8736 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8737 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 171:3a7713b1edbc 8738 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8739 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8740 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 8741 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8742 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8743 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 171:3a7713b1edbc 8744
AnnaBridge 171:3a7713b1edbc 8745 /* The count of PIT_TCTRL */
AnnaBridge 171:3a7713b1edbc 8746 #define PIT_TCTRL_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 8747
AnnaBridge 171:3a7713b1edbc 8748 /*! @name TFLG - Timer Flag Register */
AnnaBridge 171:3a7713b1edbc 8749 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8750 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8751 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 8752
AnnaBridge 171:3a7713b1edbc 8753 /* The count of PIT_TFLG */
AnnaBridge 171:3a7713b1edbc 8754 #define PIT_TFLG_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 8755
AnnaBridge 171:3a7713b1edbc 8756
AnnaBridge 171:3a7713b1edbc 8757 /*!
AnnaBridge 171:3a7713b1edbc 8758 * @}
AnnaBridge 171:3a7713b1edbc 8759 */ /* end of group PIT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8760
AnnaBridge 171:3a7713b1edbc 8761
AnnaBridge 171:3a7713b1edbc 8762 /* PIT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8763 /** Peripheral PIT base address */
AnnaBridge 171:3a7713b1edbc 8764 #define PIT_BASE (0x40037000u)
AnnaBridge 171:3a7713b1edbc 8765 /** Peripheral PIT base pointer */
AnnaBridge 171:3a7713b1edbc 8766 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 171:3a7713b1edbc 8767 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8768 #define PIT_BASE_ADDRS { PIT_BASE }
AnnaBridge 171:3a7713b1edbc 8769 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8770 #define PIT_BASE_PTRS { PIT }
AnnaBridge 171:3a7713b1edbc 8771 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 171:3a7713b1edbc 8772 #define PIT_IRQS { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
AnnaBridge 171:3a7713b1edbc 8773
AnnaBridge 171:3a7713b1edbc 8774 /*!
AnnaBridge 171:3a7713b1edbc 8775 * @}
AnnaBridge 171:3a7713b1edbc 8776 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8777
AnnaBridge 171:3a7713b1edbc 8778
AnnaBridge 171:3a7713b1edbc 8779 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8780 -- PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8781 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8782
AnnaBridge 171:3a7713b1edbc 8783 /*!
AnnaBridge 171:3a7713b1edbc 8784 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8785 * @{
AnnaBridge 171:3a7713b1edbc 8786 */
AnnaBridge 171:3a7713b1edbc 8787
AnnaBridge 171:3a7713b1edbc 8788 /** PMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8789 typedef struct {
AnnaBridge 171:3a7713b1edbc 8790 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 8791 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 8792 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 8793 } PMC_Type;
AnnaBridge 171:3a7713b1edbc 8794
AnnaBridge 171:3a7713b1edbc 8795 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8796 -- PMC Register Masks
AnnaBridge 171:3a7713b1edbc 8797 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8798
AnnaBridge 171:3a7713b1edbc 8799 /*!
AnnaBridge 171:3a7713b1edbc 8800 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 171:3a7713b1edbc 8801 * @{
AnnaBridge 171:3a7713b1edbc 8802 */
AnnaBridge 171:3a7713b1edbc 8803
AnnaBridge 171:3a7713b1edbc 8804 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 171:3a7713b1edbc 8805 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8806 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8807 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 171:3a7713b1edbc 8808 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8809 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8810 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 171:3a7713b1edbc 8811 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8812 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8813 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 171:3a7713b1edbc 8814 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8815 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8816 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 171:3a7713b1edbc 8817 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8818 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8819 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 171:3a7713b1edbc 8820
AnnaBridge 171:3a7713b1edbc 8821 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 171:3a7713b1edbc 8822 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 8823 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8824 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 171:3a7713b1edbc 8825 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8826 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8827 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 171:3a7713b1edbc 8828 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8829 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8830 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 171:3a7713b1edbc 8831 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 8832 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 8833 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 171:3a7713b1edbc 8834
AnnaBridge 171:3a7713b1edbc 8835 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 171:3a7713b1edbc 8836 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8837 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8838 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 171:3a7713b1edbc 8839 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8840 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8841 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 171:3a7713b1edbc 8842 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 8843 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 8844 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 171:3a7713b1edbc 8845 #define PMC_REGSC_BGEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8846 #define PMC_REGSC_BGEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8847 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
AnnaBridge 171:3a7713b1edbc 8848
AnnaBridge 171:3a7713b1edbc 8849
AnnaBridge 171:3a7713b1edbc 8850 /*!
AnnaBridge 171:3a7713b1edbc 8851 * @}
AnnaBridge 171:3a7713b1edbc 8852 */ /* end of group PMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8853
AnnaBridge 171:3a7713b1edbc 8854
AnnaBridge 171:3a7713b1edbc 8855 /* PMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8856 /** Peripheral PMC base address */
AnnaBridge 171:3a7713b1edbc 8857 #define PMC_BASE (0x4007D000u)
AnnaBridge 171:3a7713b1edbc 8858 /** Peripheral PMC base pointer */
AnnaBridge 171:3a7713b1edbc 8859 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 171:3a7713b1edbc 8860 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 8861 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 171:3a7713b1edbc 8862 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 8863 #define PMC_BASE_PTRS { PMC }
AnnaBridge 171:3a7713b1edbc 8864 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 171:3a7713b1edbc 8865 #define PMC_IRQS { LVD_LVW_IRQn }
AnnaBridge 171:3a7713b1edbc 8866
AnnaBridge 171:3a7713b1edbc 8867 /*!
AnnaBridge 171:3a7713b1edbc 8868 * @}
AnnaBridge 171:3a7713b1edbc 8869 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 8870
AnnaBridge 171:3a7713b1edbc 8871
AnnaBridge 171:3a7713b1edbc 8872 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8873 -- PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8874 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8875
AnnaBridge 171:3a7713b1edbc 8876 /*!
AnnaBridge 171:3a7713b1edbc 8877 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 8878 * @{
AnnaBridge 171:3a7713b1edbc 8879 */
AnnaBridge 171:3a7713b1edbc 8880
AnnaBridge 171:3a7713b1edbc 8881 /** PORT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 8882 typedef struct {
AnnaBridge 171:3a7713b1edbc 8883 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 8884 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 8885 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 8886 uint8_t RESERVED_0[24];
AnnaBridge 171:3a7713b1edbc 8887 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 8888 uint8_t RESERVED_1[28];
AnnaBridge 171:3a7713b1edbc 8889 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 8890 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 8891 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
AnnaBridge 171:3a7713b1edbc 8892 } PORT_Type;
AnnaBridge 171:3a7713b1edbc 8893
AnnaBridge 171:3a7713b1edbc 8894 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 8895 -- PORT Register Masks
AnnaBridge 171:3a7713b1edbc 8896 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 8897
AnnaBridge 171:3a7713b1edbc 8898 /*!
AnnaBridge 171:3a7713b1edbc 8899 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 171:3a7713b1edbc 8900 * @{
AnnaBridge 171:3a7713b1edbc 8901 */
AnnaBridge 171:3a7713b1edbc 8902
AnnaBridge 171:3a7713b1edbc 8903 /*! @name PCR - Pin Control Register n */
AnnaBridge 171:3a7713b1edbc 8904 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8905 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8906 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 171:3a7713b1edbc 8907 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 8908 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 8909 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 171:3a7713b1edbc 8910 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 8911 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 8912 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 171:3a7713b1edbc 8913 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 8914 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 8915 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 171:3a7713b1edbc 8916 #define PORT_PCR_ODE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 8917 #define PORT_PCR_ODE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 8918 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
AnnaBridge 171:3a7713b1edbc 8919 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 8920 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 8921 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 171:3a7713b1edbc 8922 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 8923 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 8924 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 171:3a7713b1edbc 8925 #define PORT_PCR_LK_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 8926 #define PORT_PCR_LK_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 8927 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
AnnaBridge 171:3a7713b1edbc 8928 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 8929 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8930 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 171:3a7713b1edbc 8931 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 8932 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 8933 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 8934
AnnaBridge 171:3a7713b1edbc 8935 /* The count of PORT_PCR */
AnnaBridge 171:3a7713b1edbc 8936 #define PORT_PCR_COUNT (32U)
AnnaBridge 171:3a7713b1edbc 8937
AnnaBridge 171:3a7713b1edbc 8938 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 171:3a7713b1edbc 8939 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8940 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8941 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 8942 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 8943 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8944 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 8945
AnnaBridge 171:3a7713b1edbc 8946 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 171:3a7713b1edbc 8947 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 8948 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8949 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 171:3a7713b1edbc 8950 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 8951 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 8952 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 171:3a7713b1edbc 8953
AnnaBridge 171:3a7713b1edbc 8954 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 171:3a7713b1edbc 8955 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8956 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8957 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 171:3a7713b1edbc 8958
AnnaBridge 171:3a7713b1edbc 8959 /*! @name DFER - Digital Filter Enable Register */
AnnaBridge 171:3a7713b1edbc 8960 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 8961 #define PORT_DFER_DFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8962 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
AnnaBridge 171:3a7713b1edbc 8963
AnnaBridge 171:3a7713b1edbc 8964 /*! @name DFCR - Digital Filter Clock Register */
AnnaBridge 171:3a7713b1edbc 8965 #define PORT_DFCR_CS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 8966 #define PORT_DFCR_CS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8967 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
AnnaBridge 171:3a7713b1edbc 8968
AnnaBridge 171:3a7713b1edbc 8969 /*! @name DFWR - Digital Filter Width Register */
AnnaBridge 171:3a7713b1edbc 8970 #define PORT_DFWR_FILT_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 8971 #define PORT_DFWR_FILT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 8972 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
AnnaBridge 171:3a7713b1edbc 8973
AnnaBridge 171:3a7713b1edbc 8974
AnnaBridge 171:3a7713b1edbc 8975 /*!
AnnaBridge 171:3a7713b1edbc 8976 * @}
AnnaBridge 171:3a7713b1edbc 8977 */ /* end of group PORT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 8978
AnnaBridge 171:3a7713b1edbc 8979
AnnaBridge 171:3a7713b1edbc 8980 /* PORT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 8981 /** Peripheral PORTA base address */
AnnaBridge 171:3a7713b1edbc 8982 #define PORTA_BASE (0x40049000u)
AnnaBridge 171:3a7713b1edbc 8983 /** Peripheral PORTA base pointer */
AnnaBridge 171:3a7713b1edbc 8984 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 171:3a7713b1edbc 8985 /** Peripheral PORTB base address */
AnnaBridge 171:3a7713b1edbc 8986 #define PORTB_BASE (0x4004A000u)
AnnaBridge 171:3a7713b1edbc 8987 /** Peripheral PORTB base pointer */
AnnaBridge 171:3a7713b1edbc 8988 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 171:3a7713b1edbc 8989 /** Peripheral PORTC base address */
AnnaBridge 171:3a7713b1edbc 8990 #define PORTC_BASE (0x4004B000u)
AnnaBridge 171:3a7713b1edbc 8991 /** Peripheral PORTC base pointer */
AnnaBridge 171:3a7713b1edbc 8992 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 171:3a7713b1edbc 8993 /** Peripheral PORTD base address */
AnnaBridge 171:3a7713b1edbc 8994 #define PORTD_BASE (0x4004C000u)
AnnaBridge 171:3a7713b1edbc 8995 /** Peripheral PORTD base pointer */
AnnaBridge 171:3a7713b1edbc 8996 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 171:3a7713b1edbc 8997 /** Peripheral PORTE base address */
AnnaBridge 171:3a7713b1edbc 8998 #define PORTE_BASE (0x4004D000u)
AnnaBridge 171:3a7713b1edbc 8999 /** Peripheral PORTE base pointer */
AnnaBridge 171:3a7713b1edbc 9000 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 171:3a7713b1edbc 9001 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9002 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
AnnaBridge 171:3a7713b1edbc 9003 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9004 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 171:3a7713b1edbc 9005 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 171:3a7713b1edbc 9006 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
AnnaBridge 171:3a7713b1edbc 9007
AnnaBridge 171:3a7713b1edbc 9008 /*!
AnnaBridge 171:3a7713b1edbc 9009 * @}
AnnaBridge 171:3a7713b1edbc 9010 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9011
AnnaBridge 171:3a7713b1edbc 9012
AnnaBridge 171:3a7713b1edbc 9013 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9014 -- RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9015 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9016
AnnaBridge 171:3a7713b1edbc 9017 /*!
AnnaBridge 171:3a7713b1edbc 9018 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9019 * @{
AnnaBridge 171:3a7713b1edbc 9020 */
AnnaBridge 171:3a7713b1edbc 9021
AnnaBridge 171:3a7713b1edbc 9022 /** RCM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9023 typedef struct {
AnnaBridge 171:3a7713b1edbc 9024 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9025 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 9026 uint8_t RESERVED_0[2];
AnnaBridge 171:3a7713b1edbc 9027 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9028 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 9029 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 9030 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 9031 } RCM_Type;
AnnaBridge 171:3a7713b1edbc 9032
AnnaBridge 171:3a7713b1edbc 9033 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9034 -- RCM Register Masks
AnnaBridge 171:3a7713b1edbc 9035 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9036
AnnaBridge 171:3a7713b1edbc 9037 /*!
AnnaBridge 171:3a7713b1edbc 9038 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 171:3a7713b1edbc 9039 * @{
AnnaBridge 171:3a7713b1edbc 9040 */
AnnaBridge 171:3a7713b1edbc 9041
AnnaBridge 171:3a7713b1edbc 9042 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 171:3a7713b1edbc 9043 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9044 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9045 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 171:3a7713b1edbc 9046 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9047 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9048 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 171:3a7713b1edbc 9049 #define RCM_SRS0_LOC_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9050 #define RCM_SRS0_LOC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9051 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
AnnaBridge 171:3a7713b1edbc 9052 #define RCM_SRS0_LOL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9053 #define RCM_SRS0_LOL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9054 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
AnnaBridge 171:3a7713b1edbc 9055 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9056 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9057 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 171:3a7713b1edbc 9058 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9059 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9060 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 171:3a7713b1edbc 9061 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9062 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9063 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 171:3a7713b1edbc 9064
AnnaBridge 171:3a7713b1edbc 9065 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 171:3a7713b1edbc 9066 #define RCM_SRS1_JTAG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9067 #define RCM_SRS1_JTAG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9068 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
AnnaBridge 171:3a7713b1edbc 9069 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9070 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9071 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 171:3a7713b1edbc 9072 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9073 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9074 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 171:3a7713b1edbc 9075 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9076 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9077 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 171:3a7713b1edbc 9078 #define RCM_SRS1_EZPT_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9079 #define RCM_SRS1_EZPT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9080 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
AnnaBridge 171:3a7713b1edbc 9081 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9082 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9083 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 171:3a7713b1edbc 9084
AnnaBridge 171:3a7713b1edbc 9085 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 171:3a7713b1edbc 9086 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 9087 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9088 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 171:3a7713b1edbc 9089 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9090 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9091 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 171:3a7713b1edbc 9092
AnnaBridge 171:3a7713b1edbc 9093 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 171:3a7713b1edbc 9094 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 9095 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9096 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 9097
AnnaBridge 171:3a7713b1edbc 9098 /*! @name MR - Mode Register */
AnnaBridge 171:3a7713b1edbc 9099 #define RCM_MR_EZP_MS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9100 #define RCM_MR_EZP_MS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9101 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
AnnaBridge 171:3a7713b1edbc 9102
AnnaBridge 171:3a7713b1edbc 9103
AnnaBridge 171:3a7713b1edbc 9104 /*!
AnnaBridge 171:3a7713b1edbc 9105 * @}
AnnaBridge 171:3a7713b1edbc 9106 */ /* end of group RCM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9107
AnnaBridge 171:3a7713b1edbc 9108
AnnaBridge 171:3a7713b1edbc 9109 /* RCM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9110 /** Peripheral RCM base address */
AnnaBridge 171:3a7713b1edbc 9111 #define RCM_BASE (0x4007F000u)
AnnaBridge 171:3a7713b1edbc 9112 /** Peripheral RCM base pointer */
AnnaBridge 171:3a7713b1edbc 9113 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 171:3a7713b1edbc 9114 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9115 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 171:3a7713b1edbc 9116 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9117 #define RCM_BASE_PTRS { RCM }
AnnaBridge 171:3a7713b1edbc 9118
AnnaBridge 171:3a7713b1edbc 9119 /*!
AnnaBridge 171:3a7713b1edbc 9120 * @}
AnnaBridge 171:3a7713b1edbc 9121 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9122
AnnaBridge 171:3a7713b1edbc 9123
AnnaBridge 171:3a7713b1edbc 9124 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9125 -- RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9126 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9127
AnnaBridge 171:3a7713b1edbc 9128 /*!
AnnaBridge 171:3a7713b1edbc 9129 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9130 * @{
AnnaBridge 171:3a7713b1edbc 9131 */
AnnaBridge 171:3a7713b1edbc 9132
AnnaBridge 171:3a7713b1edbc 9133 /** RFSYS - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9134 typedef struct {
AnnaBridge 171:3a7713b1edbc 9135 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 9136 } RFSYS_Type;
AnnaBridge 171:3a7713b1edbc 9137
AnnaBridge 171:3a7713b1edbc 9138 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9139 -- RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 9140 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9141
AnnaBridge 171:3a7713b1edbc 9142 /*!
AnnaBridge 171:3a7713b1edbc 9143 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 171:3a7713b1edbc 9144 * @{
AnnaBridge 171:3a7713b1edbc 9145 */
AnnaBridge 171:3a7713b1edbc 9146
AnnaBridge 171:3a7713b1edbc 9147 /*! @name REG - Register file register */
AnnaBridge 171:3a7713b1edbc 9148 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9149 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9150 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 9151 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9152 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9153 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 9154 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9155 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9156 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 9157 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9158 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9159 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 9160
AnnaBridge 171:3a7713b1edbc 9161 /* The count of RFSYS_REG */
AnnaBridge 171:3a7713b1edbc 9162 #define RFSYS_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 9163
AnnaBridge 171:3a7713b1edbc 9164
AnnaBridge 171:3a7713b1edbc 9165 /*!
AnnaBridge 171:3a7713b1edbc 9166 * @}
AnnaBridge 171:3a7713b1edbc 9167 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9168
AnnaBridge 171:3a7713b1edbc 9169
AnnaBridge 171:3a7713b1edbc 9170 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9171 /** Peripheral RFSYS base address */
AnnaBridge 171:3a7713b1edbc 9172 #define RFSYS_BASE (0x40041000u)
AnnaBridge 171:3a7713b1edbc 9173 /** Peripheral RFSYS base pointer */
AnnaBridge 171:3a7713b1edbc 9174 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 171:3a7713b1edbc 9175 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9176 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 171:3a7713b1edbc 9177 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9178 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 171:3a7713b1edbc 9179
AnnaBridge 171:3a7713b1edbc 9180 /*!
AnnaBridge 171:3a7713b1edbc 9181 * @}
AnnaBridge 171:3a7713b1edbc 9182 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9183
AnnaBridge 171:3a7713b1edbc 9184
AnnaBridge 171:3a7713b1edbc 9185 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9186 -- RFVBAT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9187 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9188
AnnaBridge 171:3a7713b1edbc 9189 /*!
AnnaBridge 171:3a7713b1edbc 9190 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9191 * @{
AnnaBridge 171:3a7713b1edbc 9192 */
AnnaBridge 171:3a7713b1edbc 9193
AnnaBridge 171:3a7713b1edbc 9194 /** RFVBAT - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9195 typedef struct {
AnnaBridge 171:3a7713b1edbc 9196 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 9197 } RFVBAT_Type;
AnnaBridge 171:3a7713b1edbc 9198
AnnaBridge 171:3a7713b1edbc 9199 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9200 -- RFVBAT Register Masks
AnnaBridge 171:3a7713b1edbc 9201 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9202
AnnaBridge 171:3a7713b1edbc 9203 /*!
AnnaBridge 171:3a7713b1edbc 9204 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
AnnaBridge 171:3a7713b1edbc 9205 * @{
AnnaBridge 171:3a7713b1edbc 9206 */
AnnaBridge 171:3a7713b1edbc 9207
AnnaBridge 171:3a7713b1edbc 9208 /*! @name REG - VBAT register file register */
AnnaBridge 171:3a7713b1edbc 9209 #define RFVBAT_REG_LL_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9210 #define RFVBAT_REG_LL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9211 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
AnnaBridge 171:3a7713b1edbc 9212 #define RFVBAT_REG_LH_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9213 #define RFVBAT_REG_LH_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9214 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
AnnaBridge 171:3a7713b1edbc 9215 #define RFVBAT_REG_HL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9216 #define RFVBAT_REG_HL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9217 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
AnnaBridge 171:3a7713b1edbc 9218 #define RFVBAT_REG_HH_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9219 #define RFVBAT_REG_HH_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9220 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
AnnaBridge 171:3a7713b1edbc 9221
AnnaBridge 171:3a7713b1edbc 9222 /* The count of RFVBAT_REG */
AnnaBridge 171:3a7713b1edbc 9223 #define RFVBAT_REG_COUNT (8U)
AnnaBridge 171:3a7713b1edbc 9224
AnnaBridge 171:3a7713b1edbc 9225
AnnaBridge 171:3a7713b1edbc 9226 /*!
AnnaBridge 171:3a7713b1edbc 9227 * @}
AnnaBridge 171:3a7713b1edbc 9228 */ /* end of group RFVBAT_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9229
AnnaBridge 171:3a7713b1edbc 9230
AnnaBridge 171:3a7713b1edbc 9231 /* RFVBAT - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9232 /** Peripheral RFVBAT base address */
AnnaBridge 171:3a7713b1edbc 9233 #define RFVBAT_BASE (0x4003E000u)
AnnaBridge 171:3a7713b1edbc 9234 /** Peripheral RFVBAT base pointer */
AnnaBridge 171:3a7713b1edbc 9235 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
AnnaBridge 171:3a7713b1edbc 9236 /** Array initializer of RFVBAT peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9237 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
AnnaBridge 171:3a7713b1edbc 9238 /** Array initializer of RFVBAT peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9239 #define RFVBAT_BASE_PTRS { RFVBAT }
AnnaBridge 171:3a7713b1edbc 9240
AnnaBridge 171:3a7713b1edbc 9241 /*!
AnnaBridge 171:3a7713b1edbc 9242 * @}
AnnaBridge 171:3a7713b1edbc 9243 */ /* end of group RFVBAT_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9244
AnnaBridge 171:3a7713b1edbc 9245
AnnaBridge 171:3a7713b1edbc 9246 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9247 -- RNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9248 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9249
AnnaBridge 171:3a7713b1edbc 9250 /*!
AnnaBridge 171:3a7713b1edbc 9251 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9252 * @{
AnnaBridge 171:3a7713b1edbc 9253 */
AnnaBridge 171:3a7713b1edbc 9254
AnnaBridge 171:3a7713b1edbc 9255 /** RNG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9256 typedef struct {
AnnaBridge 171:3a7713b1edbc 9257 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9258 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9259 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9260 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9261 } RNG_Type;
AnnaBridge 171:3a7713b1edbc 9262
AnnaBridge 171:3a7713b1edbc 9263 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9264 -- RNG Register Masks
AnnaBridge 171:3a7713b1edbc 9265 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9266
AnnaBridge 171:3a7713b1edbc 9267 /*!
AnnaBridge 171:3a7713b1edbc 9268 * @addtogroup RNG_Register_Masks RNG Register Masks
AnnaBridge 171:3a7713b1edbc 9269 * @{
AnnaBridge 171:3a7713b1edbc 9270 */
AnnaBridge 171:3a7713b1edbc 9271
AnnaBridge 171:3a7713b1edbc 9272 /*! @name CR - RNGA Control Register */
AnnaBridge 171:3a7713b1edbc 9273 #define RNG_CR_GO_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9274 #define RNG_CR_GO_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9275 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
AnnaBridge 171:3a7713b1edbc 9276 #define RNG_CR_HA_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9277 #define RNG_CR_HA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9278 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
AnnaBridge 171:3a7713b1edbc 9279 #define RNG_CR_INTM_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9280 #define RNG_CR_INTM_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9281 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
AnnaBridge 171:3a7713b1edbc 9282 #define RNG_CR_CLRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9283 #define RNG_CR_CLRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9284 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
AnnaBridge 171:3a7713b1edbc 9285 #define RNG_CR_SLP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9286 #define RNG_CR_SLP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9287 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
AnnaBridge 171:3a7713b1edbc 9288
AnnaBridge 171:3a7713b1edbc 9289 /*! @name SR - RNGA Status Register */
AnnaBridge 171:3a7713b1edbc 9290 #define RNG_SR_SECV_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9291 #define RNG_SR_SECV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9292 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
AnnaBridge 171:3a7713b1edbc 9293 #define RNG_SR_LRS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9294 #define RNG_SR_LRS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9295 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
AnnaBridge 171:3a7713b1edbc 9296 #define RNG_SR_ORU_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9297 #define RNG_SR_ORU_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9298 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
AnnaBridge 171:3a7713b1edbc 9299 #define RNG_SR_ERRI_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9300 #define RNG_SR_ERRI_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9301 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
AnnaBridge 171:3a7713b1edbc 9302 #define RNG_SR_SLP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9303 #define RNG_SR_SLP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9304 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
AnnaBridge 171:3a7713b1edbc 9305 #define RNG_SR_OREG_LVL_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9306 #define RNG_SR_OREG_LVL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9307 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
AnnaBridge 171:3a7713b1edbc 9308 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9309 #define RNG_SR_OREG_SIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9310 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
AnnaBridge 171:3a7713b1edbc 9311
AnnaBridge 171:3a7713b1edbc 9312 /*! @name ER - RNGA Entropy Register */
AnnaBridge 171:3a7713b1edbc 9313 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9314 #define RNG_ER_EXT_ENT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9315 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
AnnaBridge 171:3a7713b1edbc 9316
AnnaBridge 171:3a7713b1edbc 9317 /*! @name OR - RNGA Output Register */
AnnaBridge 171:3a7713b1edbc 9318 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9319 #define RNG_OR_RANDOUT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9320 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
AnnaBridge 171:3a7713b1edbc 9321
AnnaBridge 171:3a7713b1edbc 9322
AnnaBridge 171:3a7713b1edbc 9323 /*!
AnnaBridge 171:3a7713b1edbc 9324 * @}
AnnaBridge 171:3a7713b1edbc 9325 */ /* end of group RNG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9326
AnnaBridge 171:3a7713b1edbc 9327
AnnaBridge 171:3a7713b1edbc 9328 /* RNG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9329 /** Peripheral RNG base address */
AnnaBridge 171:3a7713b1edbc 9330 #define RNG_BASE (0x40029000u)
AnnaBridge 171:3a7713b1edbc 9331 /** Peripheral RNG base pointer */
AnnaBridge 171:3a7713b1edbc 9332 #define RNG ((RNG_Type *)RNG_BASE)
AnnaBridge 171:3a7713b1edbc 9333 /** Array initializer of RNG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9334 #define RNG_BASE_ADDRS { RNG_BASE }
AnnaBridge 171:3a7713b1edbc 9335 /** Array initializer of RNG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9336 #define RNG_BASE_PTRS { RNG }
AnnaBridge 171:3a7713b1edbc 9337 /** Interrupt vectors for the RNG peripheral type */
AnnaBridge 171:3a7713b1edbc 9338 #define RNG_IRQS { RNG_IRQn }
AnnaBridge 171:3a7713b1edbc 9339
AnnaBridge 171:3a7713b1edbc 9340 /*!
AnnaBridge 171:3a7713b1edbc 9341 * @}
AnnaBridge 171:3a7713b1edbc 9342 */ /* end of group RNG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9343
AnnaBridge 171:3a7713b1edbc 9344
AnnaBridge 171:3a7713b1edbc 9345 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9346 -- RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9347 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9348
AnnaBridge 171:3a7713b1edbc 9349 /*!
AnnaBridge 171:3a7713b1edbc 9350 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9351 * @{
AnnaBridge 171:3a7713b1edbc 9352 */
AnnaBridge 171:3a7713b1edbc 9353
AnnaBridge 171:3a7713b1edbc 9354 /** RTC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9355 typedef struct {
AnnaBridge 171:3a7713b1edbc 9356 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9357 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9358 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9359 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9360 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 9361 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 9362 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 9363 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 9364 uint8_t RESERVED_0[2016];
AnnaBridge 171:3a7713b1edbc 9365 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
AnnaBridge 171:3a7713b1edbc 9366 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
AnnaBridge 171:3a7713b1edbc 9367 } RTC_Type;
AnnaBridge 171:3a7713b1edbc 9368
AnnaBridge 171:3a7713b1edbc 9369 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9370 -- RTC Register Masks
AnnaBridge 171:3a7713b1edbc 9371 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9372
AnnaBridge 171:3a7713b1edbc 9373 /*!
AnnaBridge 171:3a7713b1edbc 9374 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 171:3a7713b1edbc 9375 * @{
AnnaBridge 171:3a7713b1edbc 9376 */
AnnaBridge 171:3a7713b1edbc 9377
AnnaBridge 171:3a7713b1edbc 9378 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 171:3a7713b1edbc 9379 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9380 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9381 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 171:3a7713b1edbc 9382
AnnaBridge 171:3a7713b1edbc 9383 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 171:3a7713b1edbc 9384 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 9385 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9386 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 171:3a7713b1edbc 9387
AnnaBridge 171:3a7713b1edbc 9388 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 171:3a7713b1edbc 9389 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9390 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9391 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 171:3a7713b1edbc 9392
AnnaBridge 171:3a7713b1edbc 9393 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 171:3a7713b1edbc 9394 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 9395 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9396 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 171:3a7713b1edbc 9397 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9398 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9399 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 171:3a7713b1edbc 9400 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 9401 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9402 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 171:3a7713b1edbc 9403 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9404 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9405 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 171:3a7713b1edbc 9406
AnnaBridge 171:3a7713b1edbc 9407 /*! @name CR - RTC Control Register */
AnnaBridge 171:3a7713b1edbc 9408 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9409 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9410 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 171:3a7713b1edbc 9411 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9412 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9413 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 171:3a7713b1edbc 9414 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9415 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9416 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 171:3a7713b1edbc 9417 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9418 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9419 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 171:3a7713b1edbc 9420 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9421 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9422 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 171:3a7713b1edbc 9423 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9424 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9425 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 171:3a7713b1edbc 9426 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9427 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9428 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 171:3a7713b1edbc 9429 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 9430 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9431 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 171:3a7713b1edbc 9432 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 9433 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 9434 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 171:3a7713b1edbc 9435 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 9436 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 9437 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 171:3a7713b1edbc 9438 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 9439 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 9440 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 171:3a7713b1edbc 9441
AnnaBridge 171:3a7713b1edbc 9442 /*! @name SR - RTC Status Register */
AnnaBridge 171:3a7713b1edbc 9443 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9444 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9445 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 171:3a7713b1edbc 9446 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9447 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9448 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 171:3a7713b1edbc 9449 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9450 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9451 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 171:3a7713b1edbc 9452 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9453 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9454 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 171:3a7713b1edbc 9455
AnnaBridge 171:3a7713b1edbc 9456 /*! @name LR - RTC Lock Register */
AnnaBridge 171:3a7713b1edbc 9457 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9458 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9459 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 171:3a7713b1edbc 9460 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9461 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9462 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 171:3a7713b1edbc 9463 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9464 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9465 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 171:3a7713b1edbc 9466 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9467 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9468 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 171:3a7713b1edbc 9469
AnnaBridge 171:3a7713b1edbc 9470 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 9471 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9472 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9473 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 171:3a7713b1edbc 9474 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9475 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9476 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 171:3a7713b1edbc 9477 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9478 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9479 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 171:3a7713b1edbc 9480 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9481 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9482 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 171:3a7713b1edbc 9483 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9484 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9485 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 171:3a7713b1edbc 9486
AnnaBridge 171:3a7713b1edbc 9487 /*! @name WAR - RTC Write Access Register */
AnnaBridge 171:3a7713b1edbc 9488 #define RTC_WAR_TSRW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9489 #define RTC_WAR_TSRW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9490 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
AnnaBridge 171:3a7713b1edbc 9491 #define RTC_WAR_TPRW_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9492 #define RTC_WAR_TPRW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9493 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
AnnaBridge 171:3a7713b1edbc 9494 #define RTC_WAR_TARW_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9495 #define RTC_WAR_TARW_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9496 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
AnnaBridge 171:3a7713b1edbc 9497 #define RTC_WAR_TCRW_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9498 #define RTC_WAR_TCRW_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9499 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
AnnaBridge 171:3a7713b1edbc 9500 #define RTC_WAR_CRW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9501 #define RTC_WAR_CRW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9502 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
AnnaBridge 171:3a7713b1edbc 9503 #define RTC_WAR_SRW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9504 #define RTC_WAR_SRW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9505 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
AnnaBridge 171:3a7713b1edbc 9506 #define RTC_WAR_LRW_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9507 #define RTC_WAR_LRW_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9508 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
AnnaBridge 171:3a7713b1edbc 9509 #define RTC_WAR_IERW_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9510 #define RTC_WAR_IERW_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9511 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
AnnaBridge 171:3a7713b1edbc 9512
AnnaBridge 171:3a7713b1edbc 9513 /*! @name RAR - RTC Read Access Register */
AnnaBridge 171:3a7713b1edbc 9514 #define RTC_RAR_TSRR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9515 #define RTC_RAR_TSRR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9516 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
AnnaBridge 171:3a7713b1edbc 9517 #define RTC_RAR_TPRR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9518 #define RTC_RAR_TPRR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9519 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
AnnaBridge 171:3a7713b1edbc 9520 #define RTC_RAR_TARR_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9521 #define RTC_RAR_TARR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9522 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
AnnaBridge 171:3a7713b1edbc 9523 #define RTC_RAR_TCRR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9524 #define RTC_RAR_TCRR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9525 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
AnnaBridge 171:3a7713b1edbc 9526 #define RTC_RAR_CRR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9527 #define RTC_RAR_CRR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9528 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
AnnaBridge 171:3a7713b1edbc 9529 #define RTC_RAR_SRR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9530 #define RTC_RAR_SRR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9531 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
AnnaBridge 171:3a7713b1edbc 9532 #define RTC_RAR_LRR_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9533 #define RTC_RAR_LRR_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9534 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
AnnaBridge 171:3a7713b1edbc 9535 #define RTC_RAR_IERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9536 #define RTC_RAR_IERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9537 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
AnnaBridge 171:3a7713b1edbc 9538
AnnaBridge 171:3a7713b1edbc 9539
AnnaBridge 171:3a7713b1edbc 9540 /*!
AnnaBridge 171:3a7713b1edbc 9541 * @}
AnnaBridge 171:3a7713b1edbc 9542 */ /* end of group RTC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 9543
AnnaBridge 171:3a7713b1edbc 9544
AnnaBridge 171:3a7713b1edbc 9545 /* RTC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 9546 /** Peripheral RTC base address */
AnnaBridge 171:3a7713b1edbc 9547 #define RTC_BASE (0x4003D000u)
AnnaBridge 171:3a7713b1edbc 9548 /** Peripheral RTC base pointer */
AnnaBridge 171:3a7713b1edbc 9549 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 171:3a7713b1edbc 9550 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 9551 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 171:3a7713b1edbc 9552 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 9553 #define RTC_BASE_PTRS { RTC }
AnnaBridge 171:3a7713b1edbc 9554 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 171:3a7713b1edbc 9555 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 171:3a7713b1edbc 9556 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 171:3a7713b1edbc 9557
AnnaBridge 171:3a7713b1edbc 9558 /*!
AnnaBridge 171:3a7713b1edbc 9559 * @}
AnnaBridge 171:3a7713b1edbc 9560 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 9561
AnnaBridge 171:3a7713b1edbc 9562
AnnaBridge 171:3a7713b1edbc 9563 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9564 -- SDHC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9565 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9566
AnnaBridge 171:3a7713b1edbc 9567 /*!
AnnaBridge 171:3a7713b1edbc 9568 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 9569 * @{
AnnaBridge 171:3a7713b1edbc 9570 */
AnnaBridge 171:3a7713b1edbc 9571
AnnaBridge 171:3a7713b1edbc 9572 /** SDHC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 9573 typedef struct {
AnnaBridge 171:3a7713b1edbc 9574 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 9575 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 9576 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 9577 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 9578 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 9579 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
AnnaBridge 171:3a7713b1edbc 9580 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
AnnaBridge 171:3a7713b1edbc 9581 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
AnnaBridge 171:3a7713b1edbc 9582 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 9583 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 9584 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 9585 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 9586 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 9587 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 9588 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 9589 uint8_t RESERVED_0[8];
AnnaBridge 171:3a7713b1edbc 9590 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
AnnaBridge 171:3a7713b1edbc 9591 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
AnnaBridge 171:3a7713b1edbc 9592 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
AnnaBridge 171:3a7713b1edbc 9593 uint8_t RESERVED_1[100];
AnnaBridge 171:3a7713b1edbc 9594 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
AnnaBridge 171:3a7713b1edbc 9595 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
AnnaBridge 171:3a7713b1edbc 9596 uint8_t RESERVED_2[52];
AnnaBridge 171:3a7713b1edbc 9597 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
AnnaBridge 171:3a7713b1edbc 9598 } SDHC_Type;
AnnaBridge 171:3a7713b1edbc 9599
AnnaBridge 171:3a7713b1edbc 9600 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 9601 -- SDHC Register Masks
AnnaBridge 171:3a7713b1edbc 9602 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 9603
AnnaBridge 171:3a7713b1edbc 9604 /*!
AnnaBridge 171:3a7713b1edbc 9605 * @addtogroup SDHC_Register_Masks SDHC Register Masks
AnnaBridge 171:3a7713b1edbc 9606 * @{
AnnaBridge 171:3a7713b1edbc 9607 */
AnnaBridge 171:3a7713b1edbc 9608
AnnaBridge 171:3a7713b1edbc 9609 /*! @name DSADDR - DMA System Address register */
AnnaBridge 171:3a7713b1edbc 9610 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 171:3a7713b1edbc 9611 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9612 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
AnnaBridge 171:3a7713b1edbc 9613
AnnaBridge 171:3a7713b1edbc 9614 /*! @name BLKATTR - Block Attributes register */
AnnaBridge 171:3a7713b1edbc 9615 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
AnnaBridge 171:3a7713b1edbc 9616 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9617 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 9618 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 9619 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9620 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
AnnaBridge 171:3a7713b1edbc 9621
AnnaBridge 171:3a7713b1edbc 9622 /*! @name CMDARG - Command Argument register */
AnnaBridge 171:3a7713b1edbc 9623 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9624 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9625 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
AnnaBridge 171:3a7713b1edbc 9626
AnnaBridge 171:3a7713b1edbc 9627 /*! @name XFERTYP - Transfer Type register */
AnnaBridge 171:3a7713b1edbc 9628 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9629 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9630 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 9631 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9632 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9633 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
AnnaBridge 171:3a7713b1edbc 9634 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9635 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9636 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
AnnaBridge 171:3a7713b1edbc 9637 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9638 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9639 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
AnnaBridge 171:3a7713b1edbc 9640 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9641 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9642 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
AnnaBridge 171:3a7713b1edbc 9643 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 9644 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9645 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
AnnaBridge 171:3a7713b1edbc 9646 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9647 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9648 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
AnnaBridge 171:3a7713b1edbc 9649 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9650 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9651 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
AnnaBridge 171:3a7713b1edbc 9652 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9653 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9654 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
AnnaBridge 171:3a7713b1edbc 9655 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 9656 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9657 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
AnnaBridge 171:3a7713b1edbc 9658 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
AnnaBridge 171:3a7713b1edbc 9659 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9660 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
AnnaBridge 171:3a7713b1edbc 9661
AnnaBridge 171:3a7713b1edbc 9662 /*! @name CMDRSP - Command Response 0..Command Response 3 */
AnnaBridge 171:3a7713b1edbc 9663 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9664 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9665 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
AnnaBridge 171:3a7713b1edbc 9666 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9667 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9668 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
AnnaBridge 171:3a7713b1edbc 9669 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9670 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9671 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
AnnaBridge 171:3a7713b1edbc 9672 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9673 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9674 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
AnnaBridge 171:3a7713b1edbc 9675
AnnaBridge 171:3a7713b1edbc 9676 /* The count of SDHC_CMDRSP */
AnnaBridge 171:3a7713b1edbc 9677 #define SDHC_CMDRSP_COUNT (4U)
AnnaBridge 171:3a7713b1edbc 9678
AnnaBridge 171:3a7713b1edbc 9679 /*! @name DATPORT - Buffer Data Port register */
AnnaBridge 171:3a7713b1edbc 9680 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 9681 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9682 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
AnnaBridge 171:3a7713b1edbc 9683
AnnaBridge 171:3a7713b1edbc 9684 /*! @name PRSSTAT - Present State register */
AnnaBridge 171:3a7713b1edbc 9685 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9686 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9687 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
AnnaBridge 171:3a7713b1edbc 9688 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9689 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9690 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
AnnaBridge 171:3a7713b1edbc 9691 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9692 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9693 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
AnnaBridge 171:3a7713b1edbc 9694 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9695 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9696 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
AnnaBridge 171:3a7713b1edbc 9697 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9698 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9699 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
AnnaBridge 171:3a7713b1edbc 9700 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9701 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9702 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
AnnaBridge 171:3a7713b1edbc 9703 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9704 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9705 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
AnnaBridge 171:3a7713b1edbc 9706 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9707 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9708 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
AnnaBridge 171:3a7713b1edbc 9709 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9710 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9711 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
AnnaBridge 171:3a7713b1edbc 9712 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 9713 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 9714 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
AnnaBridge 171:3a7713b1edbc 9715 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 9716 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 9717 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
AnnaBridge 171:3a7713b1edbc 9718 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 9719 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 9720 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
AnnaBridge 171:3a7713b1edbc 9721 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9722 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9723 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
AnnaBridge 171:3a7713b1edbc 9724 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 9725 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 9726 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
AnnaBridge 171:3a7713b1edbc 9727 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 9728 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9729 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
AnnaBridge 171:3a7713b1edbc 9730
AnnaBridge 171:3a7713b1edbc 9731 /*! @name PROCTL - Protocol Control register */
AnnaBridge 171:3a7713b1edbc 9732 #define SDHC_PROCTL_LCTL_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9733 #define SDHC_PROCTL_LCTL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9734 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
AnnaBridge 171:3a7713b1edbc 9735 #define SDHC_PROCTL_DTW_MASK (0x6U)
AnnaBridge 171:3a7713b1edbc 9736 #define SDHC_PROCTL_DTW_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9737 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
AnnaBridge 171:3a7713b1edbc 9738 #define SDHC_PROCTL_D3CD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9739 #define SDHC_PROCTL_D3CD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9740 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
AnnaBridge 171:3a7713b1edbc 9741 #define SDHC_PROCTL_EMODE_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 9742 #define SDHC_PROCTL_EMODE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9743 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
AnnaBridge 171:3a7713b1edbc 9744 #define SDHC_PROCTL_CDTL_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9745 #define SDHC_PROCTL_CDTL_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9746 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
AnnaBridge 171:3a7713b1edbc 9747 #define SDHC_PROCTL_CDSS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9748 #define SDHC_PROCTL_CDSS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9749 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
AnnaBridge 171:3a7713b1edbc 9750 #define SDHC_PROCTL_DMAS_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 9751 #define SDHC_PROCTL_DMAS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9752 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
AnnaBridge 171:3a7713b1edbc 9753 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9754 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9755 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
AnnaBridge 171:3a7713b1edbc 9756 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9757 #define SDHC_PROCTL_CREQ_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9758 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
AnnaBridge 171:3a7713b1edbc 9759 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9760 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9761 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
AnnaBridge 171:3a7713b1edbc 9762 #define SDHC_PROCTL_IABG_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9763 #define SDHC_PROCTL_IABG_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9764 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
AnnaBridge 171:3a7713b1edbc 9765 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9766 #define SDHC_PROCTL_WECINT_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9767 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
AnnaBridge 171:3a7713b1edbc 9768 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 9769 #define SDHC_PROCTL_WECINS_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 9770 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
AnnaBridge 171:3a7713b1edbc 9771 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 9772 #define SDHC_PROCTL_WECRM_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 9773 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
AnnaBridge 171:3a7713b1edbc 9774
AnnaBridge 171:3a7713b1edbc 9775 /*! @name SYSCTL - System Control register */
AnnaBridge 171:3a7713b1edbc 9776 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9777 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9778 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
AnnaBridge 171:3a7713b1edbc 9779 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9780 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9781 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
AnnaBridge 171:3a7713b1edbc 9782 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9783 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9784 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
AnnaBridge 171:3a7713b1edbc 9785 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9786 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9787 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
AnnaBridge 171:3a7713b1edbc 9788 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 9789 #define SDHC_SYSCTL_DVS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9790 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
AnnaBridge 171:3a7713b1edbc 9791 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 9792 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9793 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
AnnaBridge 171:3a7713b1edbc 9794 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 9795 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9796 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
AnnaBridge 171:3a7713b1edbc 9797 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9798 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9799 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
AnnaBridge 171:3a7713b1edbc 9800 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 9801 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 9802 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
AnnaBridge 171:3a7713b1edbc 9803 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 9804 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 9805 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
AnnaBridge 171:3a7713b1edbc 9806 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 9807 #define SDHC_SYSCTL_INITA_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 9808 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
AnnaBridge 171:3a7713b1edbc 9809
AnnaBridge 171:3a7713b1edbc 9810 /*! @name IRQSTAT - Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 9811 #define SDHC_IRQSTAT_CC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9812 #define SDHC_IRQSTAT_CC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9813 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
AnnaBridge 171:3a7713b1edbc 9814 #define SDHC_IRQSTAT_TC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9815 #define SDHC_IRQSTAT_TC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9816 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
AnnaBridge 171:3a7713b1edbc 9817 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9818 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9819 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
AnnaBridge 171:3a7713b1edbc 9820 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9821 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9822 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
AnnaBridge 171:3a7713b1edbc 9823 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9824 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9825 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
AnnaBridge 171:3a7713b1edbc 9826 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9827 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9828 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
AnnaBridge 171:3a7713b1edbc 9829 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9830 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9831 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
AnnaBridge 171:3a7713b1edbc 9832 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9833 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9834 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
AnnaBridge 171:3a7713b1edbc 9835 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9836 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9837 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 9838 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9839 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9840 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
AnnaBridge 171:3a7713b1edbc 9841 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9842 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9843 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
AnnaBridge 171:3a7713b1edbc 9844 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9845 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9846 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
AnnaBridge 171:3a7713b1edbc 9847 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9848 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9849 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
AnnaBridge 171:3a7713b1edbc 9850 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9851 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9852 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
AnnaBridge 171:3a7713b1edbc 9853 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9854 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9855 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
AnnaBridge 171:3a7713b1edbc 9856 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9857 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9858 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
AnnaBridge 171:3a7713b1edbc 9859 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9860 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9861 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
AnnaBridge 171:3a7713b1edbc 9862 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9863 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9864 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
AnnaBridge 171:3a7713b1edbc 9865
AnnaBridge 171:3a7713b1edbc 9866 /*! @name IRQSTATEN - Interrupt Status Enable register */
AnnaBridge 171:3a7713b1edbc 9867 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9868 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9869 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9870 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9871 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9872 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9873 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9874 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9875 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9876 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9877 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9878 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9879 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9880 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9881 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9882 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9883 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9884 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9885 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9886 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9887 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9888 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9889 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9890 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9891 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9892 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9893 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
AnnaBridge 171:3a7713b1edbc 9894 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9895 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9896 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9897 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9898 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9899 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9900 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9901 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9902 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9903 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9904 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9905 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9906 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9907 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9908 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9909 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9910 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9911 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9912 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9913 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9914 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9915 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9916 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9917 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9918 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9919 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9920 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
AnnaBridge 171:3a7713b1edbc 9921
AnnaBridge 171:3a7713b1edbc 9922 /*! @name IRQSIGEN - Interrupt Signal Enable register */
AnnaBridge 171:3a7713b1edbc 9923 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9924 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9925 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9926 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9927 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9928 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9929 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9930 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9931 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9932 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9933 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9934 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9935 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9936 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9937 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9938 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 9939 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 9940 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9941 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 9942 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 9943 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9944 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9945 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9946 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9947 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 9948 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 9949 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9950 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 9951 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 9952 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9953 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 9954 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 9955 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9956 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 9957 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 9958 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9959 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 9960 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 9961 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9962 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 9963 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 9964 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9965 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 9966 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 9967 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9968 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 9969 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 9970 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9971 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 9972 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 9973 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9974 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 9975 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 9976 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
AnnaBridge 171:3a7713b1edbc 9977
AnnaBridge 171:3a7713b1edbc 9978 /*! @name AC12ERR - Auto CMD12 Error Status Register */
AnnaBridge 171:3a7713b1edbc 9979 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 9980 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 9981 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
AnnaBridge 171:3a7713b1edbc 9982 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 9983 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 9984 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
AnnaBridge 171:3a7713b1edbc 9985 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 9986 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 9987 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
AnnaBridge 171:3a7713b1edbc 9988 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 9989 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 9990 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
AnnaBridge 171:3a7713b1edbc 9991 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 9992 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 9993 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
AnnaBridge 171:3a7713b1edbc 9994 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 9995 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 9996 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
AnnaBridge 171:3a7713b1edbc 9997
AnnaBridge 171:3a7713b1edbc 9998 /*! @name HTCAPBLT - Host Controller Capabilities */
AnnaBridge 171:3a7713b1edbc 9999 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
AnnaBridge 171:3a7713b1edbc 10000 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10001 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
AnnaBridge 171:3a7713b1edbc 10002 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10003 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10004 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
AnnaBridge 171:3a7713b1edbc 10005 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 10006 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10007 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
AnnaBridge 171:3a7713b1edbc 10008 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 10009 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 10010 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
AnnaBridge 171:3a7713b1edbc 10011 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 10012 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 10013 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
AnnaBridge 171:3a7713b1edbc 10014 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10015 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10016 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
AnnaBridge 171:3a7713b1edbc 10017
AnnaBridge 171:3a7713b1edbc 10018 /*! @name WML - Watermark Level Register */
AnnaBridge 171:3a7713b1edbc 10019 #define SDHC_WML_RDWML_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10020 #define SDHC_WML_RDWML_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10021 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
AnnaBridge 171:3a7713b1edbc 10022 #define SDHC_WML_WRWML_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10023 #define SDHC_WML_WRWML_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10024 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
AnnaBridge 171:3a7713b1edbc 10025
AnnaBridge 171:3a7713b1edbc 10026 /*! @name FEVT - Force Event register */
AnnaBridge 171:3a7713b1edbc 10027 #define SDHC_FEVT_AC12NE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10028 #define SDHC_FEVT_AC12NE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10029 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
AnnaBridge 171:3a7713b1edbc 10030 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10031 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10032 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
AnnaBridge 171:3a7713b1edbc 10033 #define SDHC_FEVT_AC12CE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10034 #define SDHC_FEVT_AC12CE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10035 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
AnnaBridge 171:3a7713b1edbc 10036 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10037 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10038 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
AnnaBridge 171:3a7713b1edbc 10039 #define SDHC_FEVT_AC12IE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10040 #define SDHC_FEVT_AC12IE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10041 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
AnnaBridge 171:3a7713b1edbc 10042 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10043 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10044 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
AnnaBridge 171:3a7713b1edbc 10045 #define SDHC_FEVT_CTOE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10046 #define SDHC_FEVT_CTOE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10047 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
AnnaBridge 171:3a7713b1edbc 10048 #define SDHC_FEVT_CCE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10049 #define SDHC_FEVT_CCE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10050 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
AnnaBridge 171:3a7713b1edbc 10051 #define SDHC_FEVT_CEBE_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10052 #define SDHC_FEVT_CEBE_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10053 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
AnnaBridge 171:3a7713b1edbc 10054 #define SDHC_FEVT_CIE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10055 #define SDHC_FEVT_CIE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10056 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
AnnaBridge 171:3a7713b1edbc 10057 #define SDHC_FEVT_DTOE_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10058 #define SDHC_FEVT_DTOE_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10059 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
AnnaBridge 171:3a7713b1edbc 10060 #define SDHC_FEVT_DCE_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 10061 #define SDHC_FEVT_DCE_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10062 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
AnnaBridge 171:3a7713b1edbc 10063 #define SDHC_FEVT_DEBE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 10064 #define SDHC_FEVT_DEBE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 10065 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
AnnaBridge 171:3a7713b1edbc 10066 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10067 #define SDHC_FEVT_AC12E_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10068 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
AnnaBridge 171:3a7713b1edbc 10069 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 10070 #define SDHC_FEVT_DMAE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10071 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
AnnaBridge 171:3a7713b1edbc 10072 #define SDHC_FEVT_CINT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10073 #define SDHC_FEVT_CINT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10074 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
AnnaBridge 171:3a7713b1edbc 10075
AnnaBridge 171:3a7713b1edbc 10076 /*! @name ADMAES - ADMA Error Status register */
AnnaBridge 171:3a7713b1edbc 10077 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 10078 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10079 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
AnnaBridge 171:3a7713b1edbc 10080 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10081 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10082 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
AnnaBridge 171:3a7713b1edbc 10083 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10084 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10085 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
AnnaBridge 171:3a7713b1edbc 10086
AnnaBridge 171:3a7713b1edbc 10087 /*! @name ADSADDR - ADMA System Addressregister */
AnnaBridge 171:3a7713b1edbc 10088 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 171:3a7713b1edbc 10089 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10090 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
AnnaBridge 171:3a7713b1edbc 10091
AnnaBridge 171:3a7713b1edbc 10092 /*! @name VENDOR - Vendor Specific register */
AnnaBridge 171:3a7713b1edbc 10093 #define SDHC_VENDOR_EXTDMAEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10094 #define SDHC_VENDOR_EXTDMAEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10095 #define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
AnnaBridge 171:3a7713b1edbc 10096 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10097 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10098 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
AnnaBridge 171:3a7713b1edbc 10099 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 10100 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10101 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
AnnaBridge 171:3a7713b1edbc 10102
AnnaBridge 171:3a7713b1edbc 10103 /*! @name MMCBOOT - MMC Boot register */
AnnaBridge 171:3a7713b1edbc 10104 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10105 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10106 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
AnnaBridge 171:3a7713b1edbc 10107 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10108 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10109 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
AnnaBridge 171:3a7713b1edbc 10110 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10111 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10112 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
AnnaBridge 171:3a7713b1edbc 10113 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10114 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10115 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
AnnaBridge 171:3a7713b1edbc 10116 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10117 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10118 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
AnnaBridge 171:3a7713b1edbc 10119 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10120 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10121 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
AnnaBridge 171:3a7713b1edbc 10122
AnnaBridge 171:3a7713b1edbc 10123 /*! @name HOSTVER - Host Controller Version */
AnnaBridge 171:3a7713b1edbc 10124 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 10125 #define SDHC_HOSTVER_SVN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10126 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
AnnaBridge 171:3a7713b1edbc 10127 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 10128 #define SDHC_HOSTVER_VVN_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10129 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
AnnaBridge 171:3a7713b1edbc 10130
AnnaBridge 171:3a7713b1edbc 10131
AnnaBridge 171:3a7713b1edbc 10132 /*!
AnnaBridge 171:3a7713b1edbc 10133 * @}
AnnaBridge 171:3a7713b1edbc 10134 */ /* end of group SDHC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10135
AnnaBridge 171:3a7713b1edbc 10136
AnnaBridge 171:3a7713b1edbc 10137 /* SDHC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10138 /** Peripheral SDHC base address */
AnnaBridge 171:3a7713b1edbc 10139 #define SDHC_BASE (0x400B1000u)
AnnaBridge 171:3a7713b1edbc 10140 /** Peripheral SDHC base pointer */
AnnaBridge 171:3a7713b1edbc 10141 #define SDHC ((SDHC_Type *)SDHC_BASE)
AnnaBridge 171:3a7713b1edbc 10142 /** Array initializer of SDHC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10143 #define SDHC_BASE_ADDRS { SDHC_BASE }
AnnaBridge 171:3a7713b1edbc 10144 /** Array initializer of SDHC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10145 #define SDHC_BASE_PTRS { SDHC }
AnnaBridge 171:3a7713b1edbc 10146 /** Interrupt vectors for the SDHC peripheral type */
AnnaBridge 171:3a7713b1edbc 10147 #define SDHC_IRQS { SDHC_IRQn }
AnnaBridge 171:3a7713b1edbc 10148
AnnaBridge 171:3a7713b1edbc 10149 /*!
AnnaBridge 171:3a7713b1edbc 10150 * @}
AnnaBridge 171:3a7713b1edbc 10151 */ /* end of group SDHC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10152
AnnaBridge 171:3a7713b1edbc 10153
AnnaBridge 171:3a7713b1edbc 10154 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10155 -- SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10156 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10157
AnnaBridge 171:3a7713b1edbc 10158 /*!
AnnaBridge 171:3a7713b1edbc 10159 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10160 * @{
AnnaBridge 171:3a7713b1edbc 10161 */
AnnaBridge 171:3a7713b1edbc 10162
AnnaBridge 171:3a7713b1edbc 10163 /** SIM - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10164 typedef struct {
AnnaBridge 171:3a7713b1edbc 10165 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10166 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 10167 uint8_t RESERVED_0[4092];
AnnaBridge 171:3a7713b1edbc 10168 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 171:3a7713b1edbc 10169 uint8_t RESERVED_1[4];
AnnaBridge 171:3a7713b1edbc 10170 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 171:3a7713b1edbc 10171 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 171:3a7713b1edbc 10172 uint8_t RESERVED_2[4];
AnnaBridge 171:3a7713b1edbc 10173 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 171:3a7713b1edbc 10174 uint8_t RESERVED_3[8];
AnnaBridge 171:3a7713b1edbc 10175 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 171:3a7713b1edbc 10176 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
AnnaBridge 171:3a7713b1edbc 10177 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
AnnaBridge 171:3a7713b1edbc 10178 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
AnnaBridge 171:3a7713b1edbc 10179 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 171:3a7713b1edbc 10180 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 171:3a7713b1edbc 10181 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 171:3a7713b1edbc 10182 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 171:3a7713b1edbc 10183 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 171:3a7713b1edbc 10184 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
AnnaBridge 171:3a7713b1edbc 10185 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 171:3a7713b1edbc 10186 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 171:3a7713b1edbc 10187 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
AnnaBridge 171:3a7713b1edbc 10188 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 171:3a7713b1edbc 10189 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 171:3a7713b1edbc 10190 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 171:3a7713b1edbc 10191 } SIM_Type;
AnnaBridge 171:3a7713b1edbc 10192
AnnaBridge 171:3a7713b1edbc 10193 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10194 -- SIM Register Masks
AnnaBridge 171:3a7713b1edbc 10195 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10196
AnnaBridge 171:3a7713b1edbc 10197 /*!
AnnaBridge 171:3a7713b1edbc 10198 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 171:3a7713b1edbc 10199 * @{
AnnaBridge 171:3a7713b1edbc 10200 */
AnnaBridge 171:3a7713b1edbc 10201
AnnaBridge 171:3a7713b1edbc 10202 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 171:3a7713b1edbc 10203 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10204 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10205 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 10206 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 10207 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10208 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10209 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 10210 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 10211 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
AnnaBridge 171:3a7713b1edbc 10212 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 10213 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 10214 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
AnnaBridge 171:3a7713b1edbc 10215 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10216 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10217 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
AnnaBridge 171:3a7713b1edbc 10218
AnnaBridge 171:3a7713b1edbc 10219 /*! @name SOPT1CFG - SOPT1 Configuration Register */
AnnaBridge 171:3a7713b1edbc 10220 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10221 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10222 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
AnnaBridge 171:3a7713b1edbc 10223 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10224 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10225 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
AnnaBridge 171:3a7713b1edbc 10226 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10227 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10228 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
AnnaBridge 171:3a7713b1edbc 10229
AnnaBridge 171:3a7713b1edbc 10230 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 171:3a7713b1edbc 10231 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10232 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10233 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10234 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 171:3a7713b1edbc 10235 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10236 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10237 #define SIM_SOPT2_FBSL_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 10238 #define SIM_SOPT2_FBSL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10239 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
AnnaBridge 171:3a7713b1edbc 10240 #define SIM_SOPT2_PTD7PAD_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10241 #define SIM_SOPT2_PTD7PAD_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10242 #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
AnnaBridge 171:3a7713b1edbc 10243 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10244 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10245 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10246 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 10247 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10248 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10249 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10250 #define SIM_SOPT2_USBSRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10251 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
AnnaBridge 171:3a7713b1edbc 10252 #define SIM_SOPT2_RMIISRC_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10253 #define SIM_SOPT2_RMIISRC_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10254 #define SIM_SOPT2_RMIISRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
AnnaBridge 171:3a7713b1edbc 10255 #define SIM_SOPT2_TIMESRC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 10256 #define SIM_SOPT2_TIMESRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10257 #define SIM_SOPT2_TIMESRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
AnnaBridge 171:3a7713b1edbc 10258 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 10259 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10260 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
AnnaBridge 171:3a7713b1edbc 10261
AnnaBridge 171:3a7713b1edbc 10262 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 171:3a7713b1edbc 10263 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10264 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10265 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 10266 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10267 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10268 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
AnnaBridge 171:3a7713b1edbc 10269 #define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10270 #define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10271 #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
AnnaBridge 171:3a7713b1edbc 10272 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10273 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10274 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 10275 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 10276 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10277 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 10278 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10279 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10280 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
AnnaBridge 171:3a7713b1edbc 10281 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 10282 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10283 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 10284 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 10285 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10286 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 10287 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10288 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10289 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10290 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10291 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10292 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10293 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10294 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10295 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10296 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10297 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10298 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10299 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 10300 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10301 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 10302 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 10303 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 10304 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 10305 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 10306 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 10307 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
AnnaBridge 171:3a7713b1edbc 10308 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10309 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10310 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
AnnaBridge 171:3a7713b1edbc 10311
AnnaBridge 171:3a7713b1edbc 10312 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 171:3a7713b1edbc 10313 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 10314 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10315 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 10316 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
AnnaBridge 171:3a7713b1edbc 10317 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10318 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 10319 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
AnnaBridge 171:3a7713b1edbc 10320 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10321 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 10322 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
AnnaBridge 171:3a7713b1edbc 10323 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10324 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
AnnaBridge 171:3a7713b1edbc 10325
AnnaBridge 171:3a7713b1edbc 10326 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 171:3a7713b1edbc 10327 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10328 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10329 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10330 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10331 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10332 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10333 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10334 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10335 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 10336 #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10337 #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10338 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10339 #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10340 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10341 #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
AnnaBridge 171:3a7713b1edbc 10342 #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10343 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10344 #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
AnnaBridge 171:3a7713b1edbc 10345
AnnaBridge 171:3a7713b1edbc 10346 /*! @name SDID - System Device Identification Register */
AnnaBridge 171:3a7713b1edbc 10347 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10348 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10349 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 171:3a7713b1edbc 10350 #define SIM_SDID_FAMID_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 10351 #define SIM_SDID_FAMID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10352 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 171:3a7713b1edbc 10353 #define SIM_SDID_DIEID_MASK (0xF80U)
AnnaBridge 171:3a7713b1edbc 10354 #define SIM_SDID_DIEID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10355 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
AnnaBridge 171:3a7713b1edbc 10356 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10357 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10358 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 171:3a7713b1edbc 10359 #define SIM_SDID_SERIESID_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10360 #define SIM_SDID_SERIESID_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10361 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
AnnaBridge 171:3a7713b1edbc 10362 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10363 #define SIM_SDID_SUBFAMID_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10364 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
AnnaBridge 171:3a7713b1edbc 10365 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10366 #define SIM_SDID_FAMILYID_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10367 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
AnnaBridge 171:3a7713b1edbc 10368
AnnaBridge 171:3a7713b1edbc 10369 /*! @name SCGC1 - System Clock Gating Control Register 1 */
AnnaBridge 171:3a7713b1edbc 10370 #define SIM_SCGC1_I2C2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10371 #define SIM_SCGC1_I2C2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10372 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
AnnaBridge 171:3a7713b1edbc 10373 #define SIM_SCGC1_UART4_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 10374 #define SIM_SCGC1_UART4_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10375 #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
AnnaBridge 171:3a7713b1edbc 10376 #define SIM_SCGC1_UART5_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10377 #define SIM_SCGC1_UART5_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10378 #define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
AnnaBridge 171:3a7713b1edbc 10379
AnnaBridge 171:3a7713b1edbc 10380 /*! @name SCGC2 - System Clock Gating Control Register 2 */
AnnaBridge 171:3a7713b1edbc 10381 #define SIM_SCGC2_ENET_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10382 #define SIM_SCGC2_ENET_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10383 #define SIM_SCGC2_ENET(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
AnnaBridge 171:3a7713b1edbc 10384 #define SIM_SCGC2_DAC0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10385 #define SIM_SCGC2_DAC0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10386 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
AnnaBridge 171:3a7713b1edbc 10387 #define SIM_SCGC2_DAC1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10388 #define SIM_SCGC2_DAC1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10389 #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
AnnaBridge 171:3a7713b1edbc 10390
AnnaBridge 171:3a7713b1edbc 10391 /*! @name SCGC3 - System Clock Gating Control Register 3 */
AnnaBridge 171:3a7713b1edbc 10392 #define SIM_SCGC3_RNGA_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10393 #define SIM_SCGC3_RNGA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10394 #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
AnnaBridge 171:3a7713b1edbc 10395 #define SIM_SCGC3_SPI2_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10396 #define SIM_SCGC3_SPI2_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10397 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
AnnaBridge 171:3a7713b1edbc 10398 #define SIM_SCGC3_SDHC_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10399 #define SIM_SCGC3_SDHC_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10400 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
AnnaBridge 171:3a7713b1edbc 10401 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10402 #define SIM_SCGC3_FTM2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10403 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
AnnaBridge 171:3a7713b1edbc 10404 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10405 #define SIM_SCGC3_FTM3_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10406 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
AnnaBridge 171:3a7713b1edbc 10407 #define SIM_SCGC3_ADC1_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10408 #define SIM_SCGC3_ADC1_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10409 #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
AnnaBridge 171:3a7713b1edbc 10410
AnnaBridge 171:3a7713b1edbc 10411 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 171:3a7713b1edbc 10412 #define SIM_SCGC4_EWM_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10413 #define SIM_SCGC4_EWM_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10414 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
AnnaBridge 171:3a7713b1edbc 10415 #define SIM_SCGC4_CMT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10416 #define SIM_SCGC4_CMT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10417 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
AnnaBridge 171:3a7713b1edbc 10418 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 10419 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 10420 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 171:3a7713b1edbc 10421 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10422 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10423 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 171:3a7713b1edbc 10424 #define SIM_SCGC4_UART0_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 10425 #define SIM_SCGC4_UART0_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10426 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
AnnaBridge 171:3a7713b1edbc 10427 #define SIM_SCGC4_UART1_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10428 #define SIM_SCGC4_UART1_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10429 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
AnnaBridge 171:3a7713b1edbc 10430 #define SIM_SCGC4_UART2_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10431 #define SIM_SCGC4_UART2_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10432 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
AnnaBridge 171:3a7713b1edbc 10433 #define SIM_SCGC4_UART3_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10434 #define SIM_SCGC4_UART3_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10435 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
AnnaBridge 171:3a7713b1edbc 10436 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10437 #define SIM_SCGC4_USBOTG_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10438 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
AnnaBridge 171:3a7713b1edbc 10439 #define SIM_SCGC4_CMP_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10440 #define SIM_SCGC4_CMP_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10441 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
AnnaBridge 171:3a7713b1edbc 10442 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 10443 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10444 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 171:3a7713b1edbc 10445
AnnaBridge 171:3a7713b1edbc 10446 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 171:3a7713b1edbc 10447 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10448 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10449 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 171:3a7713b1edbc 10450 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10451 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10452 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 171:3a7713b1edbc 10453 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 10454 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10455 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 171:3a7713b1edbc 10456 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10457 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10458 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 171:3a7713b1edbc 10459 #define SIM_SCGC5_PORTD_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10460 #define SIM_SCGC5_PORTD_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10461 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
AnnaBridge 171:3a7713b1edbc 10462 #define SIM_SCGC5_PORTE_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10463 #define SIM_SCGC5_PORTE_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10464 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
AnnaBridge 171:3a7713b1edbc 10465
AnnaBridge 171:3a7713b1edbc 10466 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 171:3a7713b1edbc 10467 #define SIM_SCGC6_FTF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10468 #define SIM_SCGC6_FTF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10469 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
AnnaBridge 171:3a7713b1edbc 10470 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10471 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10472 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 171:3a7713b1edbc 10473 #define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 10474 #define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10475 #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
AnnaBridge 171:3a7713b1edbc 10476 #define SIM_SCGC6_RNGA_MASK (0x200U)
AnnaBridge 171:3a7713b1edbc 10477 #define SIM_SCGC6_RNGA_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 10478 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
AnnaBridge 171:3a7713b1edbc 10479 #define SIM_SCGC6_SPI0_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10480 #define SIM_SCGC6_SPI0_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10481 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
AnnaBridge 171:3a7713b1edbc 10482 #define SIM_SCGC6_SPI1_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10483 #define SIM_SCGC6_SPI1_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10484 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
AnnaBridge 171:3a7713b1edbc 10485 #define SIM_SCGC6_I2S_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10486 #define SIM_SCGC6_I2S_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10487 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
AnnaBridge 171:3a7713b1edbc 10488 #define SIM_SCGC6_CRC_MASK (0x40000U)
AnnaBridge 171:3a7713b1edbc 10489 #define SIM_SCGC6_CRC_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10490 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
AnnaBridge 171:3a7713b1edbc 10491 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 10492 #define SIM_SCGC6_USBDCD_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 10493 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
AnnaBridge 171:3a7713b1edbc 10494 #define SIM_SCGC6_PDB_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 10495 #define SIM_SCGC6_PDB_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 10496 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
AnnaBridge 171:3a7713b1edbc 10497 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 10498 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 10499 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 171:3a7713b1edbc 10500 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10501 #define SIM_SCGC6_FTM0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10502 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
AnnaBridge 171:3a7713b1edbc 10503 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10504 #define SIM_SCGC6_FTM1_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10505 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
AnnaBridge 171:3a7713b1edbc 10506 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10507 #define SIM_SCGC6_FTM2_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10508 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
AnnaBridge 171:3a7713b1edbc 10509 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10510 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10511 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 171:3a7713b1edbc 10512 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 10513 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 10514 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 171:3a7713b1edbc 10515 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10516 #define SIM_SCGC6_DAC0_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10517 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
AnnaBridge 171:3a7713b1edbc 10518
AnnaBridge 171:3a7713b1edbc 10519 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 171:3a7713b1edbc 10520 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10521 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10522 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
AnnaBridge 171:3a7713b1edbc 10523 #define SIM_SCGC7_DMA_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10524 #define SIM_SCGC7_DMA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10525 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 171:3a7713b1edbc 10526 #define SIM_SCGC7_MPU_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 10527 #define SIM_SCGC7_MPU_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 10528 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
AnnaBridge 171:3a7713b1edbc 10529
AnnaBridge 171:3a7713b1edbc 10530 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 171:3a7713b1edbc 10531 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10532 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10533 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 171:3a7713b1edbc 10534 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
AnnaBridge 171:3a7713b1edbc 10535 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10536 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
AnnaBridge 171:3a7713b1edbc 10537 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10538 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10539 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
AnnaBridge 171:3a7713b1edbc 10540 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10541 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10542 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 171:3a7713b1edbc 10543
AnnaBridge 171:3a7713b1edbc 10544 /*! @name CLKDIV2 - System Clock Divider Register 2 */
AnnaBridge 171:3a7713b1edbc 10545 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10546 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10547 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
AnnaBridge 171:3a7713b1edbc 10548 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 10549 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10550 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
AnnaBridge 171:3a7713b1edbc 10551
AnnaBridge 171:3a7713b1edbc 10552 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 171:3a7713b1edbc 10553 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10554 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10555 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 171:3a7713b1edbc 10556 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10557 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10558 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 171:3a7713b1edbc 10559 #define SIM_FCFG1_DEPART_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10560 #define SIM_FCFG1_DEPART_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10561 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
AnnaBridge 171:3a7713b1edbc 10562 #define SIM_FCFG1_EESIZE_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 10563 #define SIM_FCFG1_EESIZE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10564 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
AnnaBridge 171:3a7713b1edbc 10565 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 171:3a7713b1edbc 10566 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10567 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 10568 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
AnnaBridge 171:3a7713b1edbc 10569 #define SIM_FCFG1_NVMSIZE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10570 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 10571
AnnaBridge 171:3a7713b1edbc 10572 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 171:3a7713b1edbc 10573 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
AnnaBridge 171:3a7713b1edbc 10574 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10575 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 171:3a7713b1edbc 10576 #define SIM_FCFG2_PFLSH_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 10577 #define SIM_FCFG2_PFLSH_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 10578 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
AnnaBridge 171:3a7713b1edbc 10579 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 171:3a7713b1edbc 10580 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10581 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 171:3a7713b1edbc 10582
AnnaBridge 171:3a7713b1edbc 10583 /*! @name UIDH - Unique Identification Register High */
AnnaBridge 171:3a7713b1edbc 10584 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10585 #define SIM_UIDH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10586 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 10587
AnnaBridge 171:3a7713b1edbc 10588 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 171:3a7713b1edbc 10589 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10590 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10591 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 171:3a7713b1edbc 10592
AnnaBridge 171:3a7713b1edbc 10593 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 171:3a7713b1edbc 10594 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10595 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10596 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 171:3a7713b1edbc 10597
AnnaBridge 171:3a7713b1edbc 10598 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 171:3a7713b1edbc 10599 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10600 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10601 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 171:3a7713b1edbc 10602
AnnaBridge 171:3a7713b1edbc 10603
AnnaBridge 171:3a7713b1edbc 10604 /*!
AnnaBridge 171:3a7713b1edbc 10605 * @}
AnnaBridge 171:3a7713b1edbc 10606 */ /* end of group SIM_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10607
AnnaBridge 171:3a7713b1edbc 10608
AnnaBridge 171:3a7713b1edbc 10609 /* SIM - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10610 /** Peripheral SIM base address */
AnnaBridge 171:3a7713b1edbc 10611 #define SIM_BASE (0x40047000u)
AnnaBridge 171:3a7713b1edbc 10612 /** Peripheral SIM base pointer */
AnnaBridge 171:3a7713b1edbc 10613 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 171:3a7713b1edbc 10614 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10615 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 171:3a7713b1edbc 10616 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10617 #define SIM_BASE_PTRS { SIM }
AnnaBridge 171:3a7713b1edbc 10618
AnnaBridge 171:3a7713b1edbc 10619 /*!
AnnaBridge 171:3a7713b1edbc 10620 * @}
AnnaBridge 171:3a7713b1edbc 10621 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10622
AnnaBridge 171:3a7713b1edbc 10623
AnnaBridge 171:3a7713b1edbc 10624 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10625 -- SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10626 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10627
AnnaBridge 171:3a7713b1edbc 10628 /*!
AnnaBridge 171:3a7713b1edbc 10629 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10630 * @{
AnnaBridge 171:3a7713b1edbc 10631 */
AnnaBridge 171:3a7713b1edbc 10632
AnnaBridge 171:3a7713b1edbc 10633 /** SMC - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10634 typedef struct {
AnnaBridge 171:3a7713b1edbc 10635 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10636 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 10637 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 10638 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 10639 } SMC_Type;
AnnaBridge 171:3a7713b1edbc 10640
AnnaBridge 171:3a7713b1edbc 10641 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10642 -- SMC Register Masks
AnnaBridge 171:3a7713b1edbc 10643 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10644
AnnaBridge 171:3a7713b1edbc 10645 /*!
AnnaBridge 171:3a7713b1edbc 10646 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 171:3a7713b1edbc 10647 * @{
AnnaBridge 171:3a7713b1edbc 10648 */
AnnaBridge 171:3a7713b1edbc 10649
AnnaBridge 171:3a7713b1edbc 10650 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 171:3a7713b1edbc 10651 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 10652 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 10653 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 171:3a7713b1edbc 10654 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10655 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10656 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 171:3a7713b1edbc 10657 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10658 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10659 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 171:3a7713b1edbc 10660
AnnaBridge 171:3a7713b1edbc 10661 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 171:3a7713b1edbc 10662 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 10663 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10664 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 171:3a7713b1edbc 10665 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 10666 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 10667 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 171:3a7713b1edbc 10668 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 171:3a7713b1edbc 10669 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10670 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 171:3a7713b1edbc 10671 #define SMC_PMCTRL_LPWUI_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 10672 #define SMC_PMCTRL_LPWUI_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 10673 #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
AnnaBridge 171:3a7713b1edbc 10674
AnnaBridge 171:3a7713b1edbc 10675 /*! @name VLLSCTRL - VLLS Control register */
AnnaBridge 171:3a7713b1edbc 10676 #define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 10677 #define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10678 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
AnnaBridge 171:3a7713b1edbc 10679 #define SMC_VLLSCTRL_PORPO_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 10680 #define SMC_VLLSCTRL_PORPO_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 10681 #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
AnnaBridge 171:3a7713b1edbc 10682
AnnaBridge 171:3a7713b1edbc 10683 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 171:3a7713b1edbc 10684 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 10685 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10686 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 171:3a7713b1edbc 10687
AnnaBridge 171:3a7713b1edbc 10688
AnnaBridge 171:3a7713b1edbc 10689 /*!
AnnaBridge 171:3a7713b1edbc 10690 * @}
AnnaBridge 171:3a7713b1edbc 10691 */ /* end of group SMC_Register_Masks */
AnnaBridge 171:3a7713b1edbc 10692
AnnaBridge 171:3a7713b1edbc 10693
AnnaBridge 171:3a7713b1edbc 10694 /* SMC - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 10695 /** Peripheral SMC base address */
AnnaBridge 171:3a7713b1edbc 10696 #define SMC_BASE (0x4007E000u)
AnnaBridge 171:3a7713b1edbc 10697 /** Peripheral SMC base pointer */
AnnaBridge 171:3a7713b1edbc 10698 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 171:3a7713b1edbc 10699 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 10700 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 171:3a7713b1edbc 10701 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 10702 #define SMC_BASE_PTRS { SMC }
AnnaBridge 171:3a7713b1edbc 10703
AnnaBridge 171:3a7713b1edbc 10704 /*!
AnnaBridge 171:3a7713b1edbc 10705 * @}
AnnaBridge 171:3a7713b1edbc 10706 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 10707
AnnaBridge 171:3a7713b1edbc 10708
AnnaBridge 171:3a7713b1edbc 10709 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10710 -- SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10711 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10712
AnnaBridge 171:3a7713b1edbc 10713 /*!
AnnaBridge 171:3a7713b1edbc 10714 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 10715 * @{
AnnaBridge 171:3a7713b1edbc 10716 */
AnnaBridge 171:3a7713b1edbc 10717
AnnaBridge 171:3a7713b1edbc 10718 /** SPI - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 10719 typedef struct {
AnnaBridge 171:3a7713b1edbc 10720 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 10721 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 10722 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 10723 union { /* offset: 0xC */
AnnaBridge 171:3a7713b1edbc 10724 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 10725 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 10726 };
AnnaBridge 171:3a7713b1edbc 10727 uint8_t RESERVED_1[24];
AnnaBridge 171:3a7713b1edbc 10728 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
AnnaBridge 171:3a7713b1edbc 10729 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
AnnaBridge 171:3a7713b1edbc 10730 union { /* offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 10731 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 10732 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
AnnaBridge 171:3a7713b1edbc 10733 };
AnnaBridge 171:3a7713b1edbc 10734 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
AnnaBridge 171:3a7713b1edbc 10735 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
AnnaBridge 171:3a7713b1edbc 10736 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
AnnaBridge 171:3a7713b1edbc 10737 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
AnnaBridge 171:3a7713b1edbc 10738 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
AnnaBridge 171:3a7713b1edbc 10739 uint8_t RESERVED_2[48];
AnnaBridge 171:3a7713b1edbc 10740 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
AnnaBridge 171:3a7713b1edbc 10741 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 10742 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 10743 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 10744 } SPI_Type;
AnnaBridge 171:3a7713b1edbc 10745
AnnaBridge 171:3a7713b1edbc 10746 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 10747 -- SPI Register Masks
AnnaBridge 171:3a7713b1edbc 10748 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 10749
AnnaBridge 171:3a7713b1edbc 10750 /*!
AnnaBridge 171:3a7713b1edbc 10751 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 171:3a7713b1edbc 10752 * @{
AnnaBridge 171:3a7713b1edbc 10753 */
AnnaBridge 171:3a7713b1edbc 10754
AnnaBridge 171:3a7713b1edbc 10755 /*! @name MCR - Module Configuration Register */
AnnaBridge 171:3a7713b1edbc 10756 #define SPI_MCR_HALT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 10757 #define SPI_MCR_HALT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10758 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
AnnaBridge 171:3a7713b1edbc 10759 #define SPI_MCR_SMPL_PT_MASK (0x300U)
AnnaBridge 171:3a7713b1edbc 10760 #define SPI_MCR_SMPL_PT_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10761 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
AnnaBridge 171:3a7713b1edbc 10762 #define SPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 10763 #define SPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 10764 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 10765 #define SPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 10766 #define SPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 10767 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 10768 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
AnnaBridge 171:3a7713b1edbc 10769 #define SPI_MCR_DIS_RXF_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10770 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
AnnaBridge 171:3a7713b1edbc 10771 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
AnnaBridge 171:3a7713b1edbc 10772 #define SPI_MCR_DIS_TXF_SHIFT (13U)
AnnaBridge 171:3a7713b1edbc 10773 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
AnnaBridge 171:3a7713b1edbc 10774 #define SPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 10775 #define SPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 10776 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
AnnaBridge 171:3a7713b1edbc 10777 #define SPI_MCR_DOZE_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 10778 #define SPI_MCR_DOZE_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 10779 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
AnnaBridge 171:3a7713b1edbc 10780 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 10781 #define SPI_MCR_PCSIS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10782 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
AnnaBridge 171:3a7713b1edbc 10783 #define SPI_MCR_ROOE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10784 #define SPI_MCR_ROOE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10785 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
AnnaBridge 171:3a7713b1edbc 10786 #define SPI_MCR_PCSSE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10787 #define SPI_MCR_PCSSE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10788 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
AnnaBridge 171:3a7713b1edbc 10789 #define SPI_MCR_MTFE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10790 #define SPI_MCR_MTFE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10791 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
AnnaBridge 171:3a7713b1edbc 10792 #define SPI_MCR_FRZ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10793 #define SPI_MCR_FRZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10794 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
AnnaBridge 171:3a7713b1edbc 10795 #define SPI_MCR_DCONF_MASK (0x30000000U)
AnnaBridge 171:3a7713b1edbc 10796 #define SPI_MCR_DCONF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10797 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
AnnaBridge 171:3a7713b1edbc 10798 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 10799 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 10800 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
AnnaBridge 171:3a7713b1edbc 10801 #define SPI_MCR_MSTR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10802 #define SPI_MCR_MSTR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10803 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
AnnaBridge 171:3a7713b1edbc 10804
AnnaBridge 171:3a7713b1edbc 10805 /*! @name TCR - Transfer Count Register */
AnnaBridge 171:3a7713b1edbc 10806 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10807 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10808 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
AnnaBridge 171:3a7713b1edbc 10809
AnnaBridge 171:3a7713b1edbc 10810 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
AnnaBridge 171:3a7713b1edbc 10811 #define SPI_CTAR_BR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10812 #define SPI_CTAR_BR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10813 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
AnnaBridge 171:3a7713b1edbc 10814 #define SPI_CTAR_DT_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10815 #define SPI_CTAR_DT_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10816 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
AnnaBridge 171:3a7713b1edbc 10817 #define SPI_CTAR_ASC_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10818 #define SPI_CTAR_ASC_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10819 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
AnnaBridge 171:3a7713b1edbc 10820 #define SPI_CTAR_CSSCK_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10821 #define SPI_CTAR_CSSCK_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10822 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 10823 #define SPI_CTAR_PBR_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 10824 #define SPI_CTAR_PBR_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10825 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
AnnaBridge 171:3a7713b1edbc 10826 #define SPI_CTAR_PDT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 10827 #define SPI_CTAR_PDT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 10828 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
AnnaBridge 171:3a7713b1edbc 10829 #define SPI_CTAR_PASC_MASK (0x300000U)
AnnaBridge 171:3a7713b1edbc 10830 #define SPI_CTAR_PASC_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 10831 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
AnnaBridge 171:3a7713b1edbc 10832 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
AnnaBridge 171:3a7713b1edbc 10833 #define SPI_CTAR_PCSSCK_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 10834 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
AnnaBridge 171:3a7713b1edbc 10835 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10836 #define SPI_CTAR_LSBFE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10837 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
AnnaBridge 171:3a7713b1edbc 10838 #define SPI_CTAR_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10839 #define SPI_CTAR_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10840 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 10841 #define SPI_CTAR_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10842 #define SPI_CTAR_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10843 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 10844 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
AnnaBridge 171:3a7713b1edbc 10845 #define SPI_CTAR_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10846 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 10847 #define SPI_CTAR_DBR_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10848 #define SPI_CTAR_DBR_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10849 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
AnnaBridge 171:3a7713b1edbc 10850
AnnaBridge 171:3a7713b1edbc 10851 /* The count of SPI_CTAR */
AnnaBridge 171:3a7713b1edbc 10852 #define SPI_CTAR_COUNT (2U)
AnnaBridge 171:3a7713b1edbc 10853
AnnaBridge 171:3a7713b1edbc 10854 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
AnnaBridge 171:3a7713b1edbc 10855 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10856 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10857 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
AnnaBridge 171:3a7713b1edbc 10858 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10859 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10860 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
AnnaBridge 171:3a7713b1edbc 10861 #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
AnnaBridge 171:3a7713b1edbc 10862 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10863 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge 171:3a7713b1edbc 10864
AnnaBridge 171:3a7713b1edbc 10865 /* The count of SPI_CTAR_SLAVE */
AnnaBridge 171:3a7713b1edbc 10866 #define SPI_CTAR_SLAVE_COUNT (1U)
AnnaBridge 171:3a7713b1edbc 10867
AnnaBridge 171:3a7713b1edbc 10868 /*! @name SR - Status Register */
AnnaBridge 171:3a7713b1edbc 10869 #define SPI_SR_POPNXTPTR_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 10870 #define SPI_SR_POPNXTPTR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10871 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 10872 #define SPI_SR_RXCTR_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 10873 #define SPI_SR_RXCTR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 10874 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 10875 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 10876 #define SPI_SR_TXNXTPTR_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 10877 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
AnnaBridge 171:3a7713b1edbc 10878 #define SPI_SR_TXCTR_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 10879 #define SPI_SR_TXCTR_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 10880 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
AnnaBridge 171:3a7713b1edbc 10881 #define SPI_SR_RFDF_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10882 #define SPI_SR_RFDF_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10883 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
AnnaBridge 171:3a7713b1edbc 10884 #define SPI_SR_RFOF_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10885 #define SPI_SR_RFOF_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10886 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
AnnaBridge 171:3a7713b1edbc 10887 #define SPI_SR_TFFF_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10888 #define SPI_SR_TFFF_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10889 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
AnnaBridge 171:3a7713b1edbc 10890 #define SPI_SR_TFUF_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10891 #define SPI_SR_TFUF_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10892 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
AnnaBridge 171:3a7713b1edbc 10893 #define SPI_SR_EOQF_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 10894 #define SPI_SR_EOQF_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10895 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
AnnaBridge 171:3a7713b1edbc 10896 #define SPI_SR_TXRXS_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 10897 #define SPI_SR_TXRXS_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 10898 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
AnnaBridge 171:3a7713b1edbc 10899 #define SPI_SR_TCF_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10900 #define SPI_SR_TCF_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10901 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
AnnaBridge 171:3a7713b1edbc 10902
AnnaBridge 171:3a7713b1edbc 10903 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
AnnaBridge 171:3a7713b1edbc 10904 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 10905 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10906 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 10907 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 10908 #define SPI_RSER_RFDF_RE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 10909 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 10910 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
AnnaBridge 171:3a7713b1edbc 10911 #define SPI_RSER_RFOF_RE_SHIFT (19U)
AnnaBridge 171:3a7713b1edbc 10912 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 10913 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 10914 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 10915 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
AnnaBridge 171:3a7713b1edbc 10916 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 10917 #define SPI_RSER_TFFF_RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 10918 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 10919 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10920 #define SPI_RSER_TFUF_RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10921 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 10922 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 10923 #define SPI_RSER_EOQF_RE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10924 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 10925 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10926 #define SPI_RSER_TCF_RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10927 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
AnnaBridge 171:3a7713b1edbc 10928
AnnaBridge 171:3a7713b1edbc 10929 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
AnnaBridge 171:3a7713b1edbc 10930 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10931 #define SPI_PUSHR_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10932 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10933 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
AnnaBridge 171:3a7713b1edbc 10934 #define SPI_PUSHR_PCS_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10935 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
AnnaBridge 171:3a7713b1edbc 10936 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 10937 #define SPI_PUSHR_CTCNT_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 10938 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 10939 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 10940 #define SPI_PUSHR_EOQ_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 10941 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
AnnaBridge 171:3a7713b1edbc 10942 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
AnnaBridge 171:3a7713b1edbc 10943 #define SPI_PUSHR_CTAS_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 10944 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
AnnaBridge 171:3a7713b1edbc 10945 #define SPI_PUSHR_CONT_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 10946 #define SPI_PUSHR_CONT_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 10947 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
AnnaBridge 171:3a7713b1edbc 10948
AnnaBridge 171:3a7713b1edbc 10949 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
AnnaBridge 171:3a7713b1edbc 10950 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10951 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10952 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10953
AnnaBridge 171:3a7713b1edbc 10954 /*! @name POPR - POP RX FIFO Register */
AnnaBridge 171:3a7713b1edbc 10955 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10956 #define SPI_POPR_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10957 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10958
AnnaBridge 171:3a7713b1edbc 10959 /*! @name TXFR0 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 10960 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10961 #define SPI_TXFR0_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10962 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10963 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10964 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10965 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10966
AnnaBridge 171:3a7713b1edbc 10967 /*! @name TXFR1 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 10968 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10969 #define SPI_TXFR1_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10970 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10971 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10972 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10973 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10974
AnnaBridge 171:3a7713b1edbc 10975 /*! @name TXFR2 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 10976 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10977 #define SPI_TXFR2_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10978 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10979 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10980 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10981 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10982
AnnaBridge 171:3a7713b1edbc 10983 /*! @name TXFR3 - Transmit FIFO Registers */
AnnaBridge 171:3a7713b1edbc 10984 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 10985 #define SPI_TXFR3_TXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10986 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10987 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 10988 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 10989 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10990
AnnaBridge 171:3a7713b1edbc 10991 /*! @name RXFR0 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 10992 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10993 #define SPI_RXFR0_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10994 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 10995
AnnaBridge 171:3a7713b1edbc 10996 /*! @name RXFR1 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 10997 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 10998 #define SPI_RXFR1_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 10999 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 11000
AnnaBridge 171:3a7713b1edbc 11001 /*! @name RXFR2 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 11002 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11003 #define SPI_RXFR2_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11004 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 11005
AnnaBridge 171:3a7713b1edbc 11006 /*! @name RXFR3 - Receive FIFO Registers */
AnnaBridge 171:3a7713b1edbc 11007 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11008 #define SPI_RXFR3_RXDATA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11009 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
AnnaBridge 171:3a7713b1edbc 11010
AnnaBridge 171:3a7713b1edbc 11011
AnnaBridge 171:3a7713b1edbc 11012 /*!
AnnaBridge 171:3a7713b1edbc 11013 * @}
AnnaBridge 171:3a7713b1edbc 11014 */ /* end of group SPI_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11015
AnnaBridge 171:3a7713b1edbc 11016
AnnaBridge 171:3a7713b1edbc 11017 /* SPI - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11018 /** Peripheral SPI0 base address */
AnnaBridge 171:3a7713b1edbc 11019 #define SPI0_BASE (0x4002C000u)
AnnaBridge 171:3a7713b1edbc 11020 /** Peripheral SPI0 base pointer */
AnnaBridge 171:3a7713b1edbc 11021 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 11022 /** Peripheral SPI1 base address */
AnnaBridge 171:3a7713b1edbc 11023 #define SPI1_BASE (0x4002D000u)
AnnaBridge 171:3a7713b1edbc 11024 /** Peripheral SPI1 base pointer */
AnnaBridge 171:3a7713b1edbc 11025 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 11026 /** Peripheral SPI2 base address */
AnnaBridge 171:3a7713b1edbc 11027 #define SPI2_BASE (0x400AC000u)
AnnaBridge 171:3a7713b1edbc 11028 /** Peripheral SPI2 base pointer */
AnnaBridge 171:3a7713b1edbc 11029 #define SPI2 ((SPI_Type *)SPI2_BASE)
AnnaBridge 171:3a7713b1edbc 11030 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11031 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
AnnaBridge 171:3a7713b1edbc 11032 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11033 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
AnnaBridge 171:3a7713b1edbc 11034 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 171:3a7713b1edbc 11035 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
AnnaBridge 171:3a7713b1edbc 11036
AnnaBridge 171:3a7713b1edbc 11037 /*!
AnnaBridge 171:3a7713b1edbc 11038 * @}
AnnaBridge 171:3a7713b1edbc 11039 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11040
AnnaBridge 171:3a7713b1edbc 11041
AnnaBridge 171:3a7713b1edbc 11042 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11043 -- SYSMPU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11044 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11045
AnnaBridge 171:3a7713b1edbc 11046 /*!
AnnaBridge 171:3a7713b1edbc 11047 * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11048 * @{
AnnaBridge 171:3a7713b1edbc 11049 */
AnnaBridge 171:3a7713b1edbc 11050
AnnaBridge 171:3a7713b1edbc 11051 /** SYSMPU - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11052 typedef struct {
AnnaBridge 171:3a7713b1edbc 11053 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 11054 uint8_t RESERVED_0[12];
AnnaBridge 171:3a7713b1edbc 11055 struct { /* offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 11056 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 11057 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
AnnaBridge 171:3a7713b1edbc 11058 } SP[5];
AnnaBridge 171:3a7713b1edbc 11059 uint8_t RESERVED_1[968];
AnnaBridge 171:3a7713b1edbc 11060 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
AnnaBridge 171:3a7713b1edbc 11061 uint8_t RESERVED_2[832];
AnnaBridge 171:3a7713b1edbc 11062 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 11063 } SYSMPU_Type;
AnnaBridge 171:3a7713b1edbc 11064
AnnaBridge 171:3a7713b1edbc 11065 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11066 -- SYSMPU Register Masks
AnnaBridge 171:3a7713b1edbc 11067 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11068
AnnaBridge 171:3a7713b1edbc 11069 /*!
AnnaBridge 171:3a7713b1edbc 11070 * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
AnnaBridge 171:3a7713b1edbc 11071 * @{
AnnaBridge 171:3a7713b1edbc 11072 */
AnnaBridge 171:3a7713b1edbc 11073
AnnaBridge 171:3a7713b1edbc 11074 /*! @name CESR - Control/Error Status Register */
AnnaBridge 171:3a7713b1edbc 11075 #define SYSMPU_CESR_VLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11076 #define SYSMPU_CESR_VLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11077 #define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 11078 #define SYSMPU_CESR_NRGD_MASK (0xF00U)
AnnaBridge 171:3a7713b1edbc 11079 #define SYSMPU_CESR_NRGD_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11080 #define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
AnnaBridge 171:3a7713b1edbc 11081 #define SYSMPU_CESR_NSP_MASK (0xF000U)
AnnaBridge 171:3a7713b1edbc 11082 #define SYSMPU_CESR_NSP_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11083 #define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
AnnaBridge 171:3a7713b1edbc 11084 #define SYSMPU_CESR_HRL_MASK (0xF0000U)
AnnaBridge 171:3a7713b1edbc 11085 #define SYSMPU_CESR_HRL_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11086 #define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
AnnaBridge 171:3a7713b1edbc 11087 #define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
AnnaBridge 171:3a7713b1edbc 11088 #define SYSMPU_CESR_SPERR_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 11089 #define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
AnnaBridge 171:3a7713b1edbc 11090
AnnaBridge 171:3a7713b1edbc 11091 /*! @name EAR - Error Address Register, slave port n */
AnnaBridge 171:3a7713b1edbc 11092 #define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
AnnaBridge 171:3a7713b1edbc 11093 #define SYSMPU_EAR_EADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11094 #define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
AnnaBridge 171:3a7713b1edbc 11095
AnnaBridge 171:3a7713b1edbc 11096 /* The count of SYSMPU_EAR */
AnnaBridge 171:3a7713b1edbc 11097 #define SYSMPU_EAR_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 11098
AnnaBridge 171:3a7713b1edbc 11099 /*! @name EDR - Error Detail Register, slave port n */
AnnaBridge 171:3a7713b1edbc 11100 #define SYSMPU_EDR_ERW_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11101 #define SYSMPU_EDR_ERW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11102 #define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
AnnaBridge 171:3a7713b1edbc 11103 #define SYSMPU_EDR_EATTR_MASK (0xEU)
AnnaBridge 171:3a7713b1edbc 11104 #define SYSMPU_EDR_EATTR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11105 #define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
AnnaBridge 171:3a7713b1edbc 11106 #define SYSMPU_EDR_EMN_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 11107 #define SYSMPU_EDR_EMN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11108 #define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
AnnaBridge 171:3a7713b1edbc 11109 #define SYSMPU_EDR_EPID_MASK (0xFF00U)
AnnaBridge 171:3a7713b1edbc 11110 #define SYSMPU_EDR_EPID_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 11111 #define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
AnnaBridge 171:3a7713b1edbc 11112 #define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
AnnaBridge 171:3a7713b1edbc 11113 #define SYSMPU_EDR_EACD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11114 #define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
AnnaBridge 171:3a7713b1edbc 11115
AnnaBridge 171:3a7713b1edbc 11116 /* The count of SYSMPU_EDR */
AnnaBridge 171:3a7713b1edbc 11117 #define SYSMPU_EDR_COUNT (5U)
AnnaBridge 171:3a7713b1edbc 11118
AnnaBridge 171:3a7713b1edbc 11119 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
AnnaBridge 171:3a7713b1edbc 11120 #define SYSMPU_WORD_VLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11121 #define SYSMPU_WORD_VLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11122 #define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 11123 #define SYSMPU_WORD_M0UM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 11124 #define SYSMPU_WORD_M0UM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11125 #define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
AnnaBridge 171:3a7713b1edbc 11126 #define SYSMPU_WORD_M0SM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 11127 #define SYSMPU_WORD_M0SM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11128 #define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
AnnaBridge 171:3a7713b1edbc 11129 #define SYSMPU_WORD_M0PE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11130 #define SYSMPU_WORD_M0PE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11131 #define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
AnnaBridge 171:3a7713b1edbc 11132 #define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
AnnaBridge 171:3a7713b1edbc 11133 #define SYSMPU_WORD_ENDADDR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11134 #define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
AnnaBridge 171:3a7713b1edbc 11135 #define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
AnnaBridge 171:3a7713b1edbc 11136 #define SYSMPU_WORD_SRTADDR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11137 #define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
AnnaBridge 171:3a7713b1edbc 11138 #define SYSMPU_WORD_M1UM_MASK (0x1C0U)
AnnaBridge 171:3a7713b1edbc 11139 #define SYSMPU_WORD_M1UM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11140 #define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
AnnaBridge 171:3a7713b1edbc 11141 #define SYSMPU_WORD_M1SM_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 11142 #define SYSMPU_WORD_M1SM_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11143 #define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
AnnaBridge 171:3a7713b1edbc 11144 #define SYSMPU_WORD_M1PE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11145 #define SYSMPU_WORD_M1PE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11146 #define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
AnnaBridge 171:3a7713b1edbc 11147 #define SYSMPU_WORD_M2UM_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 11148 #define SYSMPU_WORD_M2UM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11149 #define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
AnnaBridge 171:3a7713b1edbc 11150 #define SYSMPU_WORD_M2SM_MASK (0x18000U)
AnnaBridge 171:3a7713b1edbc 11151 #define SYSMPU_WORD_M2SM_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 11152 #define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
AnnaBridge 171:3a7713b1edbc 11153 #define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
AnnaBridge 171:3a7713b1edbc 11154 #define SYSMPU_WORD_PIDMASK_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 11155 #define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
AnnaBridge 171:3a7713b1edbc 11156 #define SYSMPU_WORD_M2PE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11157 #define SYSMPU_WORD_M2PE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11158 #define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
AnnaBridge 171:3a7713b1edbc 11159 #define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
AnnaBridge 171:3a7713b1edbc 11160 #define SYSMPU_WORD_M3UM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11161 #define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
AnnaBridge 171:3a7713b1edbc 11162 #define SYSMPU_WORD_M3SM_MASK (0x600000U)
AnnaBridge 171:3a7713b1edbc 11163 #define SYSMPU_WORD_M3SM_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11164 #define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
AnnaBridge 171:3a7713b1edbc 11165 #define SYSMPU_WORD_M3PE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 11166 #define SYSMPU_WORD_M3PE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 11167 #define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
AnnaBridge 171:3a7713b1edbc 11168 #define SYSMPU_WORD_PID_MASK (0xFF000000U)
AnnaBridge 171:3a7713b1edbc 11169 #define SYSMPU_WORD_PID_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11170 #define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
AnnaBridge 171:3a7713b1edbc 11171 #define SYSMPU_WORD_M4WE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11172 #define SYSMPU_WORD_M4WE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11173 #define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
AnnaBridge 171:3a7713b1edbc 11174 #define SYSMPU_WORD_M4RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 11175 #define SYSMPU_WORD_M4RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 11176 #define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
AnnaBridge 171:3a7713b1edbc 11177 #define SYSMPU_WORD_M5WE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 11178 #define SYSMPU_WORD_M5WE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 11179 #define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
AnnaBridge 171:3a7713b1edbc 11180 #define SYSMPU_WORD_M5RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 11181 #define SYSMPU_WORD_M5RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 11182 #define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
AnnaBridge 171:3a7713b1edbc 11183 #define SYSMPU_WORD_M6WE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11184 #define SYSMPU_WORD_M6WE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11185 #define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
AnnaBridge 171:3a7713b1edbc 11186 #define SYSMPU_WORD_M6RE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 11187 #define SYSMPU_WORD_M6RE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 11188 #define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
AnnaBridge 171:3a7713b1edbc 11189 #define SYSMPU_WORD_M7WE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 11190 #define SYSMPU_WORD_M7WE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 11191 #define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
AnnaBridge 171:3a7713b1edbc 11192 #define SYSMPU_WORD_M7RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 11193 #define SYSMPU_WORD_M7RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 11194 #define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
AnnaBridge 171:3a7713b1edbc 11195
AnnaBridge 171:3a7713b1edbc 11196 /* The count of SYSMPU_WORD */
AnnaBridge 171:3a7713b1edbc 11197 #define SYSMPU_WORD_COUNT (12U)
AnnaBridge 171:3a7713b1edbc 11198
AnnaBridge 171:3a7713b1edbc 11199 /* The count of SYSMPU_WORD */
AnnaBridge 171:3a7713b1edbc 11200 #define SYSMPU_WORD_COUNT2 (4U)
AnnaBridge 171:3a7713b1edbc 11201
AnnaBridge 171:3a7713b1edbc 11202 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
AnnaBridge 171:3a7713b1edbc 11203 #define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 11204 #define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11205 #define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
AnnaBridge 171:3a7713b1edbc 11206 #define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
AnnaBridge 171:3a7713b1edbc 11207 #define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11208 #define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
AnnaBridge 171:3a7713b1edbc 11209 #define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11210 #define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11211 #define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
AnnaBridge 171:3a7713b1edbc 11212 #define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
AnnaBridge 171:3a7713b1edbc 11213 #define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11214 #define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
AnnaBridge 171:3a7713b1edbc 11215 #define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
AnnaBridge 171:3a7713b1edbc 11216 #define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
AnnaBridge 171:3a7713b1edbc 11217 #define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
AnnaBridge 171:3a7713b1edbc 11218 #define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 11219 #define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 11220 #define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
AnnaBridge 171:3a7713b1edbc 11221 #define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
AnnaBridge 171:3a7713b1edbc 11222 #define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 11223 #define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
AnnaBridge 171:3a7713b1edbc 11224 #define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
AnnaBridge 171:3a7713b1edbc 11225 #define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 11226 #define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
AnnaBridge 171:3a7713b1edbc 11227 #define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 11228 #define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 11229 #define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
AnnaBridge 171:3a7713b1edbc 11230 #define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
AnnaBridge 171:3a7713b1edbc 11231 #define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 11232 #define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
AnnaBridge 171:3a7713b1edbc 11233 #define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
AnnaBridge 171:3a7713b1edbc 11234 #define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 11235 #define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
AnnaBridge 171:3a7713b1edbc 11236 #define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
AnnaBridge 171:3a7713b1edbc 11237 #define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
AnnaBridge 171:3a7713b1edbc 11238 #define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
AnnaBridge 171:3a7713b1edbc 11239 #define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 11240 #define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 11241 #define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
AnnaBridge 171:3a7713b1edbc 11242 #define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 11243 #define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 11244 #define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
AnnaBridge 171:3a7713b1edbc 11245 #define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
AnnaBridge 171:3a7713b1edbc 11246 #define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
AnnaBridge 171:3a7713b1edbc 11247 #define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
AnnaBridge 171:3a7713b1edbc 11248 #define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
AnnaBridge 171:3a7713b1edbc 11249 #define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
AnnaBridge 171:3a7713b1edbc 11250 #define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
AnnaBridge 171:3a7713b1edbc 11251 #define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
AnnaBridge 171:3a7713b1edbc 11252 #define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
AnnaBridge 171:3a7713b1edbc 11253 #define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
AnnaBridge 171:3a7713b1edbc 11254 #define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
AnnaBridge 171:3a7713b1edbc 11255 #define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
AnnaBridge 171:3a7713b1edbc 11256 #define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
AnnaBridge 171:3a7713b1edbc 11257 #define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
AnnaBridge 171:3a7713b1edbc 11258 #define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
AnnaBridge 171:3a7713b1edbc 11259 #define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
AnnaBridge 171:3a7713b1edbc 11260 #define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
AnnaBridge 171:3a7713b1edbc 11261 #define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
AnnaBridge 171:3a7713b1edbc 11262 #define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
AnnaBridge 171:3a7713b1edbc 11263
AnnaBridge 171:3a7713b1edbc 11264 /* The count of SYSMPU_RGDAAC */
AnnaBridge 171:3a7713b1edbc 11265 #define SYSMPU_RGDAAC_COUNT (12U)
AnnaBridge 171:3a7713b1edbc 11266
AnnaBridge 171:3a7713b1edbc 11267
AnnaBridge 171:3a7713b1edbc 11268 /*!
AnnaBridge 171:3a7713b1edbc 11269 * @}
AnnaBridge 171:3a7713b1edbc 11270 */ /* end of group SYSMPU_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11271
AnnaBridge 171:3a7713b1edbc 11272
AnnaBridge 171:3a7713b1edbc 11273 /* SYSMPU - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11274 /** Peripheral SYSMPU base address */
AnnaBridge 171:3a7713b1edbc 11275 #define SYSMPU_BASE (0x4000D000u)
AnnaBridge 171:3a7713b1edbc 11276 /** Peripheral SYSMPU base pointer */
AnnaBridge 171:3a7713b1edbc 11277 #define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
AnnaBridge 171:3a7713b1edbc 11278 /** Array initializer of SYSMPU peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11279 #define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
AnnaBridge 171:3a7713b1edbc 11280 /** Array initializer of SYSMPU peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11281 #define SYSMPU_BASE_PTRS { SYSMPU }
AnnaBridge 171:3a7713b1edbc 11282
AnnaBridge 171:3a7713b1edbc 11283 /*!
AnnaBridge 171:3a7713b1edbc 11284 * @}
AnnaBridge 171:3a7713b1edbc 11285 */ /* end of group SYSMPU_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11286
AnnaBridge 171:3a7713b1edbc 11287
AnnaBridge 171:3a7713b1edbc 11288 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11289 -- UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11290 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11291
AnnaBridge 171:3a7713b1edbc 11292 /*!
AnnaBridge 171:3a7713b1edbc 11293 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11294 * @{
AnnaBridge 171:3a7713b1edbc 11295 */
AnnaBridge 171:3a7713b1edbc 11296
AnnaBridge 171:3a7713b1edbc 11297 /** UART - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11298 typedef struct {
AnnaBridge 171:3a7713b1edbc 11299 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 11300 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 11301 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 11302 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 171:3a7713b1edbc 11303 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 11304 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 171:3a7713b1edbc 11305 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 11306 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 171:3a7713b1edbc 11307 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 11308 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 171:3a7713b1edbc 11309 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 11310 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 171:3a7713b1edbc 11311 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 11312 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
AnnaBridge 171:3a7713b1edbc 11313 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 11314 uint8_t RESERVED_0[1];
AnnaBridge 171:3a7713b1edbc 11315 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 11316 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
AnnaBridge 171:3a7713b1edbc 11317 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 11318 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
AnnaBridge 171:3a7713b1edbc 11319 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 11320 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
AnnaBridge 171:3a7713b1edbc 11321 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 11322 uint8_t RESERVED_1[1];
AnnaBridge 171:3a7713b1edbc 11323 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 11324 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
AnnaBridge 171:3a7713b1edbc 11325 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
AnnaBridge 171:3a7713b1edbc 11326 union { /* offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 11327 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 11328 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 171:3a7713b1edbc 11329 };
AnnaBridge 171:3a7713b1edbc 11330 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 11331 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
AnnaBridge 171:3a7713b1edbc 11332 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
AnnaBridge 171:3a7713b1edbc 11333 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
AnnaBridge 171:3a7713b1edbc 11334 } UART_Type;
AnnaBridge 171:3a7713b1edbc 11335
AnnaBridge 171:3a7713b1edbc 11336 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11337 -- UART Register Masks
AnnaBridge 171:3a7713b1edbc 11338 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11339
AnnaBridge 171:3a7713b1edbc 11340 /*!
AnnaBridge 171:3a7713b1edbc 11341 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 171:3a7713b1edbc 11342 * @{
AnnaBridge 171:3a7713b1edbc 11343 */
AnnaBridge 171:3a7713b1edbc 11344
AnnaBridge 171:3a7713b1edbc 11345 /*! @name BDH - UART Baud Rate Registers: High */
AnnaBridge 171:3a7713b1edbc 11346 #define UART_BDH_SBR_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 11347 #define UART_BDH_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11348 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 11349 #define UART_BDH_SBNS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11350 #define UART_BDH_SBNS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11351 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
AnnaBridge 171:3a7713b1edbc 11352 #define UART_BDH_RXEDGIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11353 #define UART_BDH_RXEDGIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11354 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
AnnaBridge 171:3a7713b1edbc 11355 #define UART_BDH_LBKDIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11356 #define UART_BDH_LBKDIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11357 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
AnnaBridge 171:3a7713b1edbc 11358
AnnaBridge 171:3a7713b1edbc 11359 /*! @name BDL - UART Baud Rate Registers: Low */
AnnaBridge 171:3a7713b1edbc 11360 #define UART_BDL_SBR_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11361 #define UART_BDL_SBR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11362 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
AnnaBridge 171:3a7713b1edbc 11363
AnnaBridge 171:3a7713b1edbc 11364 /*! @name C1 - UART Control Register 1 */
AnnaBridge 171:3a7713b1edbc 11365 #define UART_C1_PT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11366 #define UART_C1_PT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11367 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
AnnaBridge 171:3a7713b1edbc 11368 #define UART_C1_PE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11369 #define UART_C1_PE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11370 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
AnnaBridge 171:3a7713b1edbc 11371 #define UART_C1_ILT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11372 #define UART_C1_ILT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11373 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
AnnaBridge 171:3a7713b1edbc 11374 #define UART_C1_WAKE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11375 #define UART_C1_WAKE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11376 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
AnnaBridge 171:3a7713b1edbc 11377 #define UART_C1_M_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11378 #define UART_C1_M_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11379 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
AnnaBridge 171:3a7713b1edbc 11380 #define UART_C1_RSRC_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11381 #define UART_C1_RSRC_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11382 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
AnnaBridge 171:3a7713b1edbc 11383 #define UART_C1_UARTSWAI_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11384 #define UART_C1_UARTSWAI_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11385 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
AnnaBridge 171:3a7713b1edbc 11386 #define UART_C1_LOOPS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11387 #define UART_C1_LOOPS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11388 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
AnnaBridge 171:3a7713b1edbc 11389
AnnaBridge 171:3a7713b1edbc 11390 /*! @name C2 - UART Control Register 2 */
AnnaBridge 171:3a7713b1edbc 11391 #define UART_C2_SBK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11392 #define UART_C2_SBK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11393 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
AnnaBridge 171:3a7713b1edbc 11394 #define UART_C2_RWU_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11395 #define UART_C2_RWU_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11396 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
AnnaBridge 171:3a7713b1edbc 11397 #define UART_C2_RE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11398 #define UART_C2_RE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11399 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
AnnaBridge 171:3a7713b1edbc 11400 #define UART_C2_TE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11401 #define UART_C2_TE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11402 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
AnnaBridge 171:3a7713b1edbc 11403 #define UART_C2_ILIE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11404 #define UART_C2_ILIE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11405 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
AnnaBridge 171:3a7713b1edbc 11406 #define UART_C2_RIE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11407 #define UART_C2_RIE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11408 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
AnnaBridge 171:3a7713b1edbc 11409 #define UART_C2_TCIE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11410 #define UART_C2_TCIE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11411 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
AnnaBridge 171:3a7713b1edbc 11412 #define UART_C2_TIE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11413 #define UART_C2_TIE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11414 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
AnnaBridge 171:3a7713b1edbc 11415
AnnaBridge 171:3a7713b1edbc 11416 /*! @name S1 - UART Status Register 1 */
AnnaBridge 171:3a7713b1edbc 11417 #define UART_S1_PF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11418 #define UART_S1_PF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11419 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
AnnaBridge 171:3a7713b1edbc 11420 #define UART_S1_FE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11421 #define UART_S1_FE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11422 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
AnnaBridge 171:3a7713b1edbc 11423 #define UART_S1_NF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11424 #define UART_S1_NF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11425 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
AnnaBridge 171:3a7713b1edbc 11426 #define UART_S1_OR_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11427 #define UART_S1_OR_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11428 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
AnnaBridge 171:3a7713b1edbc 11429 #define UART_S1_IDLE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11430 #define UART_S1_IDLE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11431 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
AnnaBridge 171:3a7713b1edbc 11432 #define UART_S1_RDRF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11433 #define UART_S1_RDRF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11434 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
AnnaBridge 171:3a7713b1edbc 11435 #define UART_S1_TC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11436 #define UART_S1_TC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11437 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
AnnaBridge 171:3a7713b1edbc 11438 #define UART_S1_TDRE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11439 #define UART_S1_TDRE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11440 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
AnnaBridge 171:3a7713b1edbc 11441
AnnaBridge 171:3a7713b1edbc 11442 /*! @name S2 - UART Status Register 2 */
AnnaBridge 171:3a7713b1edbc 11443 #define UART_S2_RAF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11444 #define UART_S2_RAF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11445 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
AnnaBridge 171:3a7713b1edbc 11446 #define UART_S2_LBKDE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11447 #define UART_S2_LBKDE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11448 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
AnnaBridge 171:3a7713b1edbc 11449 #define UART_S2_BRK13_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11450 #define UART_S2_BRK13_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11451 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
AnnaBridge 171:3a7713b1edbc 11452 #define UART_S2_RWUID_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11453 #define UART_S2_RWUID_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11454 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
AnnaBridge 171:3a7713b1edbc 11455 #define UART_S2_RXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11456 #define UART_S2_RXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11457 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
AnnaBridge 171:3a7713b1edbc 11458 #define UART_S2_MSBF_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11459 #define UART_S2_MSBF_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11460 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
AnnaBridge 171:3a7713b1edbc 11461 #define UART_S2_RXEDGIF_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11462 #define UART_S2_RXEDGIF_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11463 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
AnnaBridge 171:3a7713b1edbc 11464 #define UART_S2_LBKDIF_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11465 #define UART_S2_LBKDIF_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11466 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
AnnaBridge 171:3a7713b1edbc 11467
AnnaBridge 171:3a7713b1edbc 11468 /*! @name C3 - UART Control Register 3 */
AnnaBridge 171:3a7713b1edbc 11469 #define UART_C3_PEIE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11470 #define UART_C3_PEIE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11471 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
AnnaBridge 171:3a7713b1edbc 11472 #define UART_C3_FEIE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11473 #define UART_C3_FEIE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11474 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
AnnaBridge 171:3a7713b1edbc 11475 #define UART_C3_NEIE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11476 #define UART_C3_NEIE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11477 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
AnnaBridge 171:3a7713b1edbc 11478 #define UART_C3_ORIE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11479 #define UART_C3_ORIE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11480 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
AnnaBridge 171:3a7713b1edbc 11481 #define UART_C3_TXINV_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11482 #define UART_C3_TXINV_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11483 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
AnnaBridge 171:3a7713b1edbc 11484 #define UART_C3_TXDIR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11485 #define UART_C3_TXDIR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11486 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
AnnaBridge 171:3a7713b1edbc 11487 #define UART_C3_T8_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11488 #define UART_C3_T8_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11489 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
AnnaBridge 171:3a7713b1edbc 11490 #define UART_C3_R8_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11491 #define UART_C3_R8_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11492 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
AnnaBridge 171:3a7713b1edbc 11493
AnnaBridge 171:3a7713b1edbc 11494 /*! @name D - UART Data Register */
AnnaBridge 171:3a7713b1edbc 11495 #define UART_D_RT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11496 #define UART_D_RT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11497 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
AnnaBridge 171:3a7713b1edbc 11498
AnnaBridge 171:3a7713b1edbc 11499 /*! @name MA1 - UART Match Address Registers 1 */
AnnaBridge 171:3a7713b1edbc 11500 #define UART_MA1_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11501 #define UART_MA1_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11502 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
AnnaBridge 171:3a7713b1edbc 11503
AnnaBridge 171:3a7713b1edbc 11504 /*! @name MA2 - UART Match Address Registers 2 */
AnnaBridge 171:3a7713b1edbc 11505 #define UART_MA2_MA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11506 #define UART_MA2_MA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11507 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
AnnaBridge 171:3a7713b1edbc 11508
AnnaBridge 171:3a7713b1edbc 11509 /*! @name C4 - UART Control Register 4 */
AnnaBridge 171:3a7713b1edbc 11510 #define UART_C4_BRFA_MASK (0x1FU)
AnnaBridge 171:3a7713b1edbc 11511 #define UART_C4_BRFA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11512 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
AnnaBridge 171:3a7713b1edbc 11513 #define UART_C4_M10_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11514 #define UART_C4_M10_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11515 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
AnnaBridge 171:3a7713b1edbc 11516 #define UART_C4_MAEN2_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11517 #define UART_C4_MAEN2_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11518 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
AnnaBridge 171:3a7713b1edbc 11519 #define UART_C4_MAEN1_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11520 #define UART_C4_MAEN1_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11521 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
AnnaBridge 171:3a7713b1edbc 11522
AnnaBridge 171:3a7713b1edbc 11523 /*! @name C5 - UART Control Register 5 */
AnnaBridge 171:3a7713b1edbc 11524 #define UART_C5_LBKDDMAS_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11525 #define UART_C5_LBKDDMAS_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11526 #define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11527 #define UART_C5_ILDMAS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11528 #define UART_C5_ILDMAS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11529 #define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11530 #define UART_C5_RDMAS_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11531 #define UART_C5_RDMAS_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11532 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11533 #define UART_C5_TCDMAS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11534 #define UART_C5_TCDMAS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11535 #define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11536 #define UART_C5_TDMAS_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11537 #define UART_C5_TDMAS_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11538 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
AnnaBridge 171:3a7713b1edbc 11539
AnnaBridge 171:3a7713b1edbc 11540 /*! @name ED - UART Extended Data Register */
AnnaBridge 171:3a7713b1edbc 11541 #define UART_ED_PARITYE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11542 #define UART_ED_PARITYE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11543 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
AnnaBridge 171:3a7713b1edbc 11544 #define UART_ED_NOISY_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11545 #define UART_ED_NOISY_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11546 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
AnnaBridge 171:3a7713b1edbc 11547
AnnaBridge 171:3a7713b1edbc 11548 /*! @name MODEM - UART Modem Register */
AnnaBridge 171:3a7713b1edbc 11549 #define UART_MODEM_TXCTSE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11550 #define UART_MODEM_TXCTSE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11551 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
AnnaBridge 171:3a7713b1edbc 11552 #define UART_MODEM_TXRTSE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11553 #define UART_MODEM_TXRTSE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11554 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 11555 #define UART_MODEM_TXRTSPOL_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11556 #define UART_MODEM_TXRTSPOL_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11557 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
AnnaBridge 171:3a7713b1edbc 11558 #define UART_MODEM_RXRTSE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11559 #define UART_MODEM_RXRTSE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11560 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
AnnaBridge 171:3a7713b1edbc 11561
AnnaBridge 171:3a7713b1edbc 11562 /*! @name IR - UART Infrared Register */
AnnaBridge 171:3a7713b1edbc 11563 #define UART_IR_TNP_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 11564 #define UART_IR_TNP_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11565 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
AnnaBridge 171:3a7713b1edbc 11566 #define UART_IR_IREN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11567 #define UART_IR_IREN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11568 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
AnnaBridge 171:3a7713b1edbc 11569
AnnaBridge 171:3a7713b1edbc 11570 /*! @name PFIFO - UART FIFO Parameters */
AnnaBridge 171:3a7713b1edbc 11571 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 11572 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11573 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 11574 #define UART_PFIFO_RXFE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11575 #define UART_PFIFO_RXFE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11576 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
AnnaBridge 171:3a7713b1edbc 11577 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
AnnaBridge 171:3a7713b1edbc 11578 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11579 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
AnnaBridge 171:3a7713b1edbc 11580 #define UART_PFIFO_TXFE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11581 #define UART_PFIFO_TXFE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11582 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
AnnaBridge 171:3a7713b1edbc 11583
AnnaBridge 171:3a7713b1edbc 11584 /*! @name CFIFO - UART FIFO Control Register */
AnnaBridge 171:3a7713b1edbc 11585 #define UART_CFIFO_RXUFE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11586 #define UART_CFIFO_RXUFE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11587 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
AnnaBridge 171:3a7713b1edbc 11588 #define UART_CFIFO_TXOFE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11589 #define UART_CFIFO_TXOFE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11590 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
AnnaBridge 171:3a7713b1edbc 11591 #define UART_CFIFO_RXOFE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11592 #define UART_CFIFO_RXOFE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11593 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
AnnaBridge 171:3a7713b1edbc 11594 #define UART_CFIFO_RXFLUSH_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11595 #define UART_CFIFO_RXFLUSH_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11596 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
AnnaBridge 171:3a7713b1edbc 11597 #define UART_CFIFO_TXFLUSH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11598 #define UART_CFIFO_TXFLUSH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11599 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
AnnaBridge 171:3a7713b1edbc 11600
AnnaBridge 171:3a7713b1edbc 11601 /*! @name SFIFO - UART FIFO Status Register */
AnnaBridge 171:3a7713b1edbc 11602 #define UART_SFIFO_RXUF_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11603 #define UART_SFIFO_RXUF_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11604 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
AnnaBridge 171:3a7713b1edbc 11605 #define UART_SFIFO_TXOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11606 #define UART_SFIFO_TXOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11607 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
AnnaBridge 171:3a7713b1edbc 11608 #define UART_SFIFO_RXOF_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11609 #define UART_SFIFO_RXOF_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11610 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
AnnaBridge 171:3a7713b1edbc 11611 #define UART_SFIFO_RXEMPT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11612 #define UART_SFIFO_RXEMPT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11613 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 11614 #define UART_SFIFO_TXEMPT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11615 #define UART_SFIFO_TXEMPT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11616 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
AnnaBridge 171:3a7713b1edbc 11617
AnnaBridge 171:3a7713b1edbc 11618 /*! @name TWFIFO - UART FIFO Transmit Watermark */
AnnaBridge 171:3a7713b1edbc 11619 #define UART_TWFIFO_TXWATER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11620 #define UART_TWFIFO_TXWATER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11621 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
AnnaBridge 171:3a7713b1edbc 11622
AnnaBridge 171:3a7713b1edbc 11623 /*! @name TCFIFO - UART FIFO Transmit Count */
AnnaBridge 171:3a7713b1edbc 11624 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11625 #define UART_TCFIFO_TXCOUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11626 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 11627
AnnaBridge 171:3a7713b1edbc 11628 /*! @name RWFIFO - UART FIFO Receive Watermark */
AnnaBridge 171:3a7713b1edbc 11629 #define UART_RWFIFO_RXWATER_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11630 #define UART_RWFIFO_RXWATER_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11631 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
AnnaBridge 171:3a7713b1edbc 11632
AnnaBridge 171:3a7713b1edbc 11633 /*! @name RCFIFO - UART FIFO Receive Count */
AnnaBridge 171:3a7713b1edbc 11634 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11635 #define UART_RCFIFO_RXCOUNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11636 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
AnnaBridge 171:3a7713b1edbc 11637
AnnaBridge 171:3a7713b1edbc 11638 /*! @name C7816 - UART 7816 Control Register */
AnnaBridge 171:3a7713b1edbc 11639 #define UART_C7816_ISO_7816E_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11640 #define UART_C7816_ISO_7816E_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11641 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
AnnaBridge 171:3a7713b1edbc 11642 #define UART_C7816_TTYPE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11643 #define UART_C7816_TTYPE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11644 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
AnnaBridge 171:3a7713b1edbc 11645 #define UART_C7816_INIT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11646 #define UART_C7816_INIT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11647 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 11648 #define UART_C7816_ANACK_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11649 #define UART_C7816_ANACK_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11650 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
AnnaBridge 171:3a7713b1edbc 11651 #define UART_C7816_ONACK_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11652 #define UART_C7816_ONACK_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11653 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
AnnaBridge 171:3a7713b1edbc 11654
AnnaBridge 171:3a7713b1edbc 11655 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 11656 #define UART_IE7816_RXTE_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11657 #define UART_IE7816_RXTE_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11658 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
AnnaBridge 171:3a7713b1edbc 11659 #define UART_IE7816_TXTE_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11660 #define UART_IE7816_TXTE_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11661 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
AnnaBridge 171:3a7713b1edbc 11662 #define UART_IE7816_GTVE_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11663 #define UART_IE7816_GTVE_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11664 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
AnnaBridge 171:3a7713b1edbc 11665 #define UART_IE7816_INITDE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11666 #define UART_IE7816_INITDE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11667 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
AnnaBridge 171:3a7713b1edbc 11668 #define UART_IE7816_BWTE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11669 #define UART_IE7816_BWTE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11670 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
AnnaBridge 171:3a7713b1edbc 11671 #define UART_IE7816_CWTE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11672 #define UART_IE7816_CWTE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11673 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
AnnaBridge 171:3a7713b1edbc 11674 #define UART_IE7816_WTE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11675 #define UART_IE7816_WTE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11676 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
AnnaBridge 171:3a7713b1edbc 11677
AnnaBridge 171:3a7713b1edbc 11678 /*! @name IS7816 - UART 7816 Interrupt Status Register */
AnnaBridge 171:3a7713b1edbc 11679 #define UART_IS7816_RXT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11680 #define UART_IS7816_RXT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11681 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
AnnaBridge 171:3a7713b1edbc 11682 #define UART_IS7816_TXT_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11683 #define UART_IS7816_TXT_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11684 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
AnnaBridge 171:3a7713b1edbc 11685 #define UART_IS7816_GTV_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11686 #define UART_IS7816_GTV_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11687 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
AnnaBridge 171:3a7713b1edbc 11688 #define UART_IS7816_INITD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11689 #define UART_IS7816_INITD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11690 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
AnnaBridge 171:3a7713b1edbc 11691 #define UART_IS7816_BWT_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11692 #define UART_IS7816_BWT_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11693 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
AnnaBridge 171:3a7713b1edbc 11694 #define UART_IS7816_CWT_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11695 #define UART_IS7816_CWT_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11696 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
AnnaBridge 171:3a7713b1edbc 11697 #define UART_IS7816_WT_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11698 #define UART_IS7816_WT_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11699 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
AnnaBridge 171:3a7713b1edbc 11700
AnnaBridge 171:3a7713b1edbc 11701 /*! @name WP7816T0 - UART 7816 Wait Parameter Register */
AnnaBridge 171:3a7713b1edbc 11702 #define UART_WP7816T0_WI_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11703 #define UART_WP7816T0_WI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11704 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
AnnaBridge 171:3a7713b1edbc 11705
AnnaBridge 171:3a7713b1edbc 11706 /*! @name WP7816T1 - UART 7816 Wait Parameter Register */
AnnaBridge 171:3a7713b1edbc 11707 #define UART_WP7816T1_BWI_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 11708 #define UART_WP7816T1_BWI_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11709 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
AnnaBridge 171:3a7713b1edbc 11710 #define UART_WP7816T1_CWI_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 11711 #define UART_WP7816T1_CWI_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11712 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
AnnaBridge 171:3a7713b1edbc 11713
AnnaBridge 171:3a7713b1edbc 11714 /*! @name WN7816 - UART 7816 Wait N Register */
AnnaBridge 171:3a7713b1edbc 11715 #define UART_WN7816_GTN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11716 #define UART_WN7816_GTN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11717 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
AnnaBridge 171:3a7713b1edbc 11718
AnnaBridge 171:3a7713b1edbc 11719 /*! @name WF7816 - UART 7816 Wait FD Register */
AnnaBridge 171:3a7713b1edbc 11720 #define UART_WF7816_GTFD_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11721 #define UART_WF7816_GTFD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11722 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
AnnaBridge 171:3a7713b1edbc 11723
AnnaBridge 171:3a7713b1edbc 11724 /*! @name ET7816 - UART 7816 Error Threshold Register */
AnnaBridge 171:3a7713b1edbc 11725 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 11726 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11727 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 11728 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 11729 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11730 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
AnnaBridge 171:3a7713b1edbc 11731
AnnaBridge 171:3a7713b1edbc 11732 /*! @name TL7816 - UART 7816 Transmit Length Register */
AnnaBridge 171:3a7713b1edbc 11733 #define UART_TL7816_TLEN_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11734 #define UART_TL7816_TLEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11735 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
AnnaBridge 171:3a7713b1edbc 11736
AnnaBridge 171:3a7713b1edbc 11737
AnnaBridge 171:3a7713b1edbc 11738 /*!
AnnaBridge 171:3a7713b1edbc 11739 * @}
AnnaBridge 171:3a7713b1edbc 11740 */ /* end of group UART_Register_Masks */
AnnaBridge 171:3a7713b1edbc 11741
AnnaBridge 171:3a7713b1edbc 11742
AnnaBridge 171:3a7713b1edbc 11743 /* UART - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 11744 /** Peripheral UART0 base address */
AnnaBridge 171:3a7713b1edbc 11745 #define UART0_BASE (0x4006A000u)
AnnaBridge 171:3a7713b1edbc 11746 /** Peripheral UART0 base pointer */
AnnaBridge 171:3a7713b1edbc 11747 #define UART0 ((UART_Type *)UART0_BASE)
AnnaBridge 171:3a7713b1edbc 11748 /** Peripheral UART1 base address */
AnnaBridge 171:3a7713b1edbc 11749 #define UART1_BASE (0x4006B000u)
AnnaBridge 171:3a7713b1edbc 11750 /** Peripheral UART1 base pointer */
AnnaBridge 171:3a7713b1edbc 11751 #define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge 171:3a7713b1edbc 11752 /** Peripheral UART2 base address */
AnnaBridge 171:3a7713b1edbc 11753 #define UART2_BASE (0x4006C000u)
AnnaBridge 171:3a7713b1edbc 11754 /** Peripheral UART2 base pointer */
AnnaBridge 171:3a7713b1edbc 11755 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 171:3a7713b1edbc 11756 /** Peripheral UART3 base address */
AnnaBridge 171:3a7713b1edbc 11757 #define UART3_BASE (0x4006D000u)
AnnaBridge 171:3a7713b1edbc 11758 /** Peripheral UART3 base pointer */
AnnaBridge 171:3a7713b1edbc 11759 #define UART3 ((UART_Type *)UART3_BASE)
AnnaBridge 171:3a7713b1edbc 11760 /** Peripheral UART4 base address */
AnnaBridge 171:3a7713b1edbc 11761 #define UART4_BASE (0x400EA000u)
AnnaBridge 171:3a7713b1edbc 11762 /** Peripheral UART4 base pointer */
AnnaBridge 171:3a7713b1edbc 11763 #define UART4 ((UART_Type *)UART4_BASE)
AnnaBridge 171:3a7713b1edbc 11764 /** Peripheral UART5 base address */
AnnaBridge 171:3a7713b1edbc 11765 #define UART5_BASE (0x400EB000u)
AnnaBridge 171:3a7713b1edbc 11766 /** Peripheral UART5 base pointer */
AnnaBridge 171:3a7713b1edbc 11767 #define UART5 ((UART_Type *)UART5_BASE)
AnnaBridge 171:3a7713b1edbc 11768 /** Array initializer of UART peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 11769 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
AnnaBridge 171:3a7713b1edbc 11770 /** Array initializer of UART peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 11771 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
AnnaBridge 171:3a7713b1edbc 11772 /** Interrupt vectors for the UART peripheral type */
AnnaBridge 171:3a7713b1edbc 11773 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
AnnaBridge 171:3a7713b1edbc 11774 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
AnnaBridge 171:3a7713b1edbc 11775 #define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
AnnaBridge 171:3a7713b1edbc 11776
AnnaBridge 171:3a7713b1edbc 11777 /*!
AnnaBridge 171:3a7713b1edbc 11778 * @}
AnnaBridge 171:3a7713b1edbc 11779 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 11780
AnnaBridge 171:3a7713b1edbc 11781
AnnaBridge 171:3a7713b1edbc 11782 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11783 -- USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11784 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11785
AnnaBridge 171:3a7713b1edbc 11786 /*!
AnnaBridge 171:3a7713b1edbc 11787 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 11788 * @{
AnnaBridge 171:3a7713b1edbc 11789 */
AnnaBridge 171:3a7713b1edbc 11790
AnnaBridge 171:3a7713b1edbc 11791 /** USB - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 11792 typedef struct {
AnnaBridge 171:3a7713b1edbc 11793 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 11794 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 11795 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 11796 uint8_t RESERVED_1[3];
AnnaBridge 171:3a7713b1edbc 11797 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 11798 uint8_t RESERVED_2[3];
AnnaBridge 171:3a7713b1edbc 11799 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 11800 uint8_t RESERVED_3[3];
AnnaBridge 171:3a7713b1edbc 11801 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 11802 uint8_t RESERVED_4[3];
AnnaBridge 171:3a7713b1edbc 11803 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 11804 uint8_t RESERVED_5[3];
AnnaBridge 171:3a7713b1edbc 11805 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 11806 uint8_t RESERVED_6[3];
AnnaBridge 171:3a7713b1edbc 11807 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 171:3a7713b1edbc 11808 uint8_t RESERVED_7[99];
AnnaBridge 171:3a7713b1edbc 11809 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 171:3a7713b1edbc 11810 uint8_t RESERVED_8[3];
AnnaBridge 171:3a7713b1edbc 11811 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 171:3a7713b1edbc 11812 uint8_t RESERVED_9[3];
AnnaBridge 171:3a7713b1edbc 11813 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 171:3a7713b1edbc 11814 uint8_t RESERVED_10[3];
AnnaBridge 171:3a7713b1edbc 11815 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 171:3a7713b1edbc 11816 uint8_t RESERVED_11[3];
AnnaBridge 171:3a7713b1edbc 11817 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 171:3a7713b1edbc 11818 uint8_t RESERVED_12[3];
AnnaBridge 171:3a7713b1edbc 11819 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 171:3a7713b1edbc 11820 uint8_t RESERVED_13[3];
AnnaBridge 171:3a7713b1edbc 11821 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 171:3a7713b1edbc 11822 uint8_t RESERVED_14[3];
AnnaBridge 171:3a7713b1edbc 11823 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
AnnaBridge 171:3a7713b1edbc 11824 uint8_t RESERVED_15[3];
AnnaBridge 171:3a7713b1edbc 11825 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
AnnaBridge 171:3a7713b1edbc 11826 uint8_t RESERVED_16[3];
AnnaBridge 171:3a7713b1edbc 11827 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
AnnaBridge 171:3a7713b1edbc 11828 uint8_t RESERVED_17[3];
AnnaBridge 171:3a7713b1edbc 11829 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 171:3a7713b1edbc 11830 uint8_t RESERVED_18[3];
AnnaBridge 171:3a7713b1edbc 11831 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
AnnaBridge 171:3a7713b1edbc 11832 uint8_t RESERVED_19[3];
AnnaBridge 171:3a7713b1edbc 11833 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 171:3a7713b1edbc 11834 uint8_t RESERVED_20[3];
AnnaBridge 171:3a7713b1edbc 11835 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 171:3a7713b1edbc 11836 uint8_t RESERVED_21[11];
AnnaBridge 171:3a7713b1edbc 11837 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 11838 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 171:3a7713b1edbc 11839 uint8_t RESERVED_0[3];
AnnaBridge 171:3a7713b1edbc 11840 } ENDPOINT[16];
AnnaBridge 171:3a7713b1edbc 11841 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 171:3a7713b1edbc 11842 uint8_t RESERVED_22[3];
AnnaBridge 171:3a7713b1edbc 11843 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 171:3a7713b1edbc 11844 uint8_t RESERVED_23[3];
AnnaBridge 171:3a7713b1edbc 11845 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 171:3a7713b1edbc 11846 uint8_t RESERVED_24[3];
AnnaBridge 171:3a7713b1edbc 11847 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
AnnaBridge 171:3a7713b1edbc 11848 uint8_t RESERVED_25[7];
AnnaBridge 171:3a7713b1edbc 11849 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 171:3a7713b1edbc 11850 uint8_t RESERVED_26[43];
AnnaBridge 171:3a7713b1edbc 11851 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
AnnaBridge 171:3a7713b1edbc 11852 uint8_t RESERVED_27[3];
AnnaBridge 171:3a7713b1edbc 11853 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
AnnaBridge 171:3a7713b1edbc 11854 uint8_t RESERVED_28[23];
AnnaBridge 171:3a7713b1edbc 11855 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
AnnaBridge 171:3a7713b1edbc 11856 } USB_Type;
AnnaBridge 171:3a7713b1edbc 11857
AnnaBridge 171:3a7713b1edbc 11858 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 11859 -- USB Register Masks
AnnaBridge 171:3a7713b1edbc 11860 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 11861
AnnaBridge 171:3a7713b1edbc 11862 /*!
AnnaBridge 171:3a7713b1edbc 11863 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 171:3a7713b1edbc 11864 * @{
AnnaBridge 171:3a7713b1edbc 11865 */
AnnaBridge 171:3a7713b1edbc 11866
AnnaBridge 171:3a7713b1edbc 11867 /*! @name PERID - Peripheral ID register */
AnnaBridge 171:3a7713b1edbc 11868 #define USB_PERID_ID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 11869 #define USB_PERID_ID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11870 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
AnnaBridge 171:3a7713b1edbc 11871
AnnaBridge 171:3a7713b1edbc 11872 /*! @name IDCOMP - Peripheral ID Complement register */
AnnaBridge 171:3a7713b1edbc 11873 #define USB_IDCOMP_NID_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 11874 #define USB_IDCOMP_NID_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11875 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
AnnaBridge 171:3a7713b1edbc 11876
AnnaBridge 171:3a7713b1edbc 11877 /*! @name REV - Peripheral Revision register */
AnnaBridge 171:3a7713b1edbc 11878 #define USB_REV_REV_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 11879 #define USB_REV_REV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11880 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
AnnaBridge 171:3a7713b1edbc 11881
AnnaBridge 171:3a7713b1edbc 11882 /*! @name ADDINFO - Peripheral Additional Info register */
AnnaBridge 171:3a7713b1edbc 11883 #define USB_ADDINFO_IEHOST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11884 #define USB_ADDINFO_IEHOST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11885 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
AnnaBridge 171:3a7713b1edbc 11886 #define USB_ADDINFO_IRQNUM_MASK (0xF8U)
AnnaBridge 171:3a7713b1edbc 11887 #define USB_ADDINFO_IRQNUM_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11888 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
AnnaBridge 171:3a7713b1edbc 11889
AnnaBridge 171:3a7713b1edbc 11890 /*! @name OTGISTAT - OTG Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 11891 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11892 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11893 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
AnnaBridge 171:3a7713b1edbc 11894 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11895 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11896 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
AnnaBridge 171:3a7713b1edbc 11897 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11898 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11899 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
AnnaBridge 171:3a7713b1edbc 11900 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11901 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11902 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
AnnaBridge 171:3a7713b1edbc 11903 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11904 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11905 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
AnnaBridge 171:3a7713b1edbc 11906 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11907 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11908 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
AnnaBridge 171:3a7713b1edbc 11909
AnnaBridge 171:3a7713b1edbc 11910 /*! @name OTGICR - OTG Interrupt Control register */
AnnaBridge 171:3a7713b1edbc 11911 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11912 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11913 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11914 #define USB_OTGICR_BSESSEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11915 #define USB_OTGICR_BSESSEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11916 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
AnnaBridge 171:3a7713b1edbc 11917 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11918 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11919 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
AnnaBridge 171:3a7713b1edbc 11920 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11921 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11922 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
AnnaBridge 171:3a7713b1edbc 11923 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11924 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11925 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
AnnaBridge 171:3a7713b1edbc 11926 #define USB_OTGICR_IDEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11927 #define USB_OTGICR_IDEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11928 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
AnnaBridge 171:3a7713b1edbc 11929
AnnaBridge 171:3a7713b1edbc 11930 /*! @name OTGSTAT - OTG Status register */
AnnaBridge 171:3a7713b1edbc 11931 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11932 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11933 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
AnnaBridge 171:3a7713b1edbc 11934 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11935 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11936 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
AnnaBridge 171:3a7713b1edbc 11937 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11938 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11939 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
AnnaBridge 171:3a7713b1edbc 11940 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11941 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11942 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
AnnaBridge 171:3a7713b1edbc 11943 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11944 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11945 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
AnnaBridge 171:3a7713b1edbc 11946 #define USB_OTGSTAT_ID_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11947 #define USB_OTGSTAT_ID_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11948 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
AnnaBridge 171:3a7713b1edbc 11949
AnnaBridge 171:3a7713b1edbc 11950 /*! @name OTGCTL - OTG Control register */
AnnaBridge 171:3a7713b1edbc 11951 #define USB_OTGCTL_OTGEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11952 #define USB_OTGCTL_OTGEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11953 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
AnnaBridge 171:3a7713b1edbc 11954 #define USB_OTGCTL_DMLOW_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11955 #define USB_OTGCTL_DMLOW_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11956 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
AnnaBridge 171:3a7713b1edbc 11957 #define USB_OTGCTL_DPLOW_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11958 #define USB_OTGCTL_DPLOW_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11959 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
AnnaBridge 171:3a7713b1edbc 11960 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11961 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11962 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 11963
AnnaBridge 171:3a7713b1edbc 11964 /*! @name ISTAT - Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 11965 #define USB_ISTAT_USBRST_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11966 #define USB_ISTAT_USBRST_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11967 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
AnnaBridge 171:3a7713b1edbc 11968 #define USB_ISTAT_ERROR_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11969 #define USB_ISTAT_ERROR_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11970 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 11971 #define USB_ISTAT_SOFTOK_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11972 #define USB_ISTAT_SOFTOK_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11973 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
AnnaBridge 171:3a7713b1edbc 11974 #define USB_ISTAT_TOKDNE_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 11975 #define USB_ISTAT_TOKDNE_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 11976 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
AnnaBridge 171:3a7713b1edbc 11977 #define USB_ISTAT_SLEEP_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 11978 #define USB_ISTAT_SLEEP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 11979 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
AnnaBridge 171:3a7713b1edbc 11980 #define USB_ISTAT_RESUME_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 11981 #define USB_ISTAT_RESUME_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 11982 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 11983 #define USB_ISTAT_ATTACH_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 11984 #define USB_ISTAT_ATTACH_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 11985 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
AnnaBridge 171:3a7713b1edbc 11986 #define USB_ISTAT_STALL_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 11987 #define USB_ISTAT_STALL_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 11988 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
AnnaBridge 171:3a7713b1edbc 11989
AnnaBridge 171:3a7713b1edbc 11990 /*! @name INTEN - Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 11991 #define USB_INTEN_USBRSTEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 11992 #define USB_INTEN_USBRSTEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 11993 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 11994 #define USB_INTEN_ERROREN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 11995 #define USB_INTEN_ERROREN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 11996 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
AnnaBridge 171:3a7713b1edbc 11997 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 11998 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 11999 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
AnnaBridge 171:3a7713b1edbc 12000 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12001 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12002 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
AnnaBridge 171:3a7713b1edbc 12003 #define USB_INTEN_SLEEPEN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12004 #define USB_INTEN_SLEEPEN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12005 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
AnnaBridge 171:3a7713b1edbc 12006 #define USB_INTEN_RESUMEEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12007 #define USB_INTEN_RESUMEEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12008 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
AnnaBridge 171:3a7713b1edbc 12009 #define USB_INTEN_ATTACHEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12010 #define USB_INTEN_ATTACHEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12011 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
AnnaBridge 171:3a7713b1edbc 12012 #define USB_INTEN_STALLEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12013 #define USB_INTEN_STALLEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12014 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
AnnaBridge 171:3a7713b1edbc 12015
AnnaBridge 171:3a7713b1edbc 12016 /*! @name ERRSTAT - Error Interrupt Status register */
AnnaBridge 171:3a7713b1edbc 12017 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12018 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12019 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
AnnaBridge 171:3a7713b1edbc 12020 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12021 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12022 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
AnnaBridge 171:3a7713b1edbc 12023 #define USB_ERRSTAT_CRC16_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12024 #define USB_ERRSTAT_CRC16_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12025 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
AnnaBridge 171:3a7713b1edbc 12026 #define USB_ERRSTAT_DFN8_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12027 #define USB_ERRSTAT_DFN8_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12028 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
AnnaBridge 171:3a7713b1edbc 12029 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12030 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12031 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
AnnaBridge 171:3a7713b1edbc 12032 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12033 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12034 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
AnnaBridge 171:3a7713b1edbc 12035 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12036 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12037 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
AnnaBridge 171:3a7713b1edbc 12038
AnnaBridge 171:3a7713b1edbc 12039 /*! @name ERREN - Error Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 12040 #define USB_ERREN_PIDERREN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12041 #define USB_ERREN_PIDERREN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12042 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
AnnaBridge 171:3a7713b1edbc 12043 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12044 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12045 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 12046 #define USB_ERREN_CRC16EN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12047 #define USB_ERREN_CRC16EN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12048 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
AnnaBridge 171:3a7713b1edbc 12049 #define USB_ERREN_DFN8EN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12050 #define USB_ERREN_DFN8EN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12051 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
AnnaBridge 171:3a7713b1edbc 12052 #define USB_ERREN_BTOERREN_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12053 #define USB_ERREN_BTOERREN_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12054 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
AnnaBridge 171:3a7713b1edbc 12055 #define USB_ERREN_DMAERREN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12056 #define USB_ERREN_DMAERREN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12057 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
AnnaBridge 171:3a7713b1edbc 12058 #define USB_ERREN_BTSERREN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12059 #define USB_ERREN_BTSERREN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12060 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
AnnaBridge 171:3a7713b1edbc 12061
AnnaBridge 171:3a7713b1edbc 12062 /*! @name STAT - Status register */
AnnaBridge 171:3a7713b1edbc 12063 #define USB_STAT_ODD_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12064 #define USB_STAT_ODD_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12065 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
AnnaBridge 171:3a7713b1edbc 12066 #define USB_STAT_TX_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12067 #define USB_STAT_TX_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12068 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
AnnaBridge 171:3a7713b1edbc 12069 #define USB_STAT_ENDP_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 12070 #define USB_STAT_ENDP_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12071 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
AnnaBridge 171:3a7713b1edbc 12072
AnnaBridge 171:3a7713b1edbc 12073 /*! @name CTL - Control register */
AnnaBridge 171:3a7713b1edbc 12074 #define USB_CTL_USBENSOFEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12075 #define USB_CTL_USBENSOFEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12076 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
AnnaBridge 171:3a7713b1edbc 12077 #define USB_CTL_ODDRST_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12078 #define USB_CTL_ODDRST_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12079 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
AnnaBridge 171:3a7713b1edbc 12080 #define USB_CTL_RESUME_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12081 #define USB_CTL_RESUME_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12082 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
AnnaBridge 171:3a7713b1edbc 12083 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12084 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12085 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
AnnaBridge 171:3a7713b1edbc 12086 #define USB_CTL_RESET_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12087 #define USB_CTL_RESET_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12088 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
AnnaBridge 171:3a7713b1edbc 12089 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12090 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12091 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
AnnaBridge 171:3a7713b1edbc 12092 #define USB_CTL_SE0_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12093 #define USB_CTL_SE0_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12094 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
AnnaBridge 171:3a7713b1edbc 12095 #define USB_CTL_JSTATE_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12096 #define USB_CTL_JSTATE_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12097 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
AnnaBridge 171:3a7713b1edbc 12098
AnnaBridge 171:3a7713b1edbc 12099 /*! @name ADDR - Address register */
AnnaBridge 171:3a7713b1edbc 12100 #define USB_ADDR_ADDR_MASK (0x7FU)
AnnaBridge 171:3a7713b1edbc 12101 #define USB_ADDR_ADDR_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12102 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
AnnaBridge 171:3a7713b1edbc 12103 #define USB_ADDR_LSEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12104 #define USB_ADDR_LSEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12105 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
AnnaBridge 171:3a7713b1edbc 12106
AnnaBridge 171:3a7713b1edbc 12107 /*! @name BDTPAGE1 - BDT Page register 1 */
AnnaBridge 171:3a7713b1edbc 12108 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
AnnaBridge 171:3a7713b1edbc 12109 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12110 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 12111
AnnaBridge 171:3a7713b1edbc 12112 /*! @name FRMNUML - Frame Number register Low */
AnnaBridge 171:3a7713b1edbc 12113 #define USB_FRMNUML_FRM_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12114 #define USB_FRMNUML_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12115 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 12116
AnnaBridge 171:3a7713b1edbc 12117 /*! @name FRMNUMH - Frame Number register High */
AnnaBridge 171:3a7713b1edbc 12118 #define USB_FRMNUMH_FRM_MASK (0x7U)
AnnaBridge 171:3a7713b1edbc 12119 #define USB_FRMNUMH_FRM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12120 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
AnnaBridge 171:3a7713b1edbc 12121
AnnaBridge 171:3a7713b1edbc 12122 /*! @name TOKEN - Token register */
AnnaBridge 171:3a7713b1edbc 12123 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12124 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12125 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 171:3a7713b1edbc 12126 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
AnnaBridge 171:3a7713b1edbc 12127 #define USB_TOKEN_TOKENPID_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12128 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
AnnaBridge 171:3a7713b1edbc 12129
AnnaBridge 171:3a7713b1edbc 12130 /*! @name SOFTHLD - SOF Threshold register */
AnnaBridge 171:3a7713b1edbc 12131 #define USB_SOFTHLD_CNT_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12132 #define USB_SOFTHLD_CNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12133 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
AnnaBridge 171:3a7713b1edbc 12134
AnnaBridge 171:3a7713b1edbc 12135 /*! @name BDTPAGE2 - BDT Page Register 2 */
AnnaBridge 171:3a7713b1edbc 12136 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12137 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12138 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 12139
AnnaBridge 171:3a7713b1edbc 12140 /*! @name BDTPAGE3 - BDT Page Register 3 */
AnnaBridge 171:3a7713b1edbc 12141 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12142 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12143 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 171:3a7713b1edbc 12144
AnnaBridge 171:3a7713b1edbc 12145 /*! @name ENDPT - Endpoint Control register */
AnnaBridge 171:3a7713b1edbc 12146 #define USB_ENDPT_EPHSHK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12147 #define USB_ENDPT_EPHSHK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12148 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
AnnaBridge 171:3a7713b1edbc 12149 #define USB_ENDPT_EPSTALL_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12150 #define USB_ENDPT_EPSTALL_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12151 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
AnnaBridge 171:3a7713b1edbc 12152 #define USB_ENDPT_EPTXEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12153 #define USB_ENDPT_EPTXEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12154 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
AnnaBridge 171:3a7713b1edbc 12155 #define USB_ENDPT_EPRXEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12156 #define USB_ENDPT_EPRXEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12157 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
AnnaBridge 171:3a7713b1edbc 12158 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12159 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12160 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
AnnaBridge 171:3a7713b1edbc 12161 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12162 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12163 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
AnnaBridge 171:3a7713b1edbc 12164 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12165 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12166 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
AnnaBridge 171:3a7713b1edbc 12167
AnnaBridge 171:3a7713b1edbc 12168 /* The count of USB_ENDPT */
AnnaBridge 171:3a7713b1edbc 12169 #define USB_ENDPT_COUNT (16U)
AnnaBridge 171:3a7713b1edbc 12170
AnnaBridge 171:3a7713b1edbc 12171 /*! @name USBCTRL - USB Control register */
AnnaBridge 171:3a7713b1edbc 12172 #define USB_USBCTRL_PDE_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12173 #define USB_USBCTRL_PDE_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12174 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
AnnaBridge 171:3a7713b1edbc 12175 #define USB_USBCTRL_SUSP_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12176 #define USB_USBCTRL_SUSP_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12177 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
AnnaBridge 171:3a7713b1edbc 12178
AnnaBridge 171:3a7713b1edbc 12179 /*! @name OBSERVE - USB OTG Observe register */
AnnaBridge 171:3a7713b1edbc 12180 #define USB_OBSERVE_DMPD_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12181 #define USB_OBSERVE_DMPD_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12182 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
AnnaBridge 171:3a7713b1edbc 12183 #define USB_OBSERVE_DPPD_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12184 #define USB_OBSERVE_DPPD_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12185 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
AnnaBridge 171:3a7713b1edbc 12186 #define USB_OBSERVE_DPPU_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12187 #define USB_OBSERVE_DPPU_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12188 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
AnnaBridge 171:3a7713b1edbc 12189
AnnaBridge 171:3a7713b1edbc 12190 /*! @name CONTROL - USB OTG Control register */
AnnaBridge 171:3a7713b1edbc 12191 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12192 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12193 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
AnnaBridge 171:3a7713b1edbc 12194
AnnaBridge 171:3a7713b1edbc 12195 /*! @name USBTRC0 - USB Transceiver Control register 0 */
AnnaBridge 171:3a7713b1edbc 12196 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12197 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12198 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
AnnaBridge 171:3a7713b1edbc 12199 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12200 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12201 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
AnnaBridge 171:3a7713b1edbc 12202 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12203 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12204 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
AnnaBridge 171:3a7713b1edbc 12205 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12206 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12207 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
AnnaBridge 171:3a7713b1edbc 12208 #define USB_USBTRC0_USBRESET_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12209 #define USB_USBTRC0_USBRESET_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12210 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
AnnaBridge 171:3a7713b1edbc 12211
AnnaBridge 171:3a7713b1edbc 12212 /*! @name USBFRMADJUST - Frame Adjust Register */
AnnaBridge 171:3a7713b1edbc 12213 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
AnnaBridge 171:3a7713b1edbc 12214 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12215 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 171:3a7713b1edbc 12216
AnnaBridge 171:3a7713b1edbc 12217 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
AnnaBridge 171:3a7713b1edbc 12218 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12219 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12220 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12221 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12222 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12223 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12224 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12225 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12226 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12227
AnnaBridge 171:3a7713b1edbc 12228 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
AnnaBridge 171:3a7713b1edbc 12229 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12230 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12231 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12232 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12233 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12234 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
AnnaBridge 171:3a7713b1edbc 12235
AnnaBridge 171:3a7713b1edbc 12236 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
AnnaBridge 171:3a7713b1edbc 12237 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12238 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12239 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
AnnaBridge 171:3a7713b1edbc 12240
AnnaBridge 171:3a7713b1edbc 12241
AnnaBridge 171:3a7713b1edbc 12242 /*!
AnnaBridge 171:3a7713b1edbc 12243 * @}
AnnaBridge 171:3a7713b1edbc 12244 */ /* end of group USB_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12245
AnnaBridge 171:3a7713b1edbc 12246
AnnaBridge 171:3a7713b1edbc 12247 /* USB - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12248 /** Peripheral USB0 base address */
AnnaBridge 171:3a7713b1edbc 12249 #define USB0_BASE (0x40072000u)
AnnaBridge 171:3a7713b1edbc 12250 /** Peripheral USB0 base pointer */
AnnaBridge 171:3a7713b1edbc 12251 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 171:3a7713b1edbc 12252 /** Array initializer of USB peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12253 #define USB_BASE_ADDRS { USB0_BASE }
AnnaBridge 171:3a7713b1edbc 12254 /** Array initializer of USB peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12255 #define USB_BASE_PTRS { USB0 }
AnnaBridge 171:3a7713b1edbc 12256 /** Interrupt vectors for the USB peripheral type */
AnnaBridge 171:3a7713b1edbc 12257 #define USB_IRQS { USB0_IRQn }
AnnaBridge 171:3a7713b1edbc 12258
AnnaBridge 171:3a7713b1edbc 12259 /*!
AnnaBridge 171:3a7713b1edbc 12260 * @}
AnnaBridge 171:3a7713b1edbc 12261 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12262
AnnaBridge 171:3a7713b1edbc 12263
AnnaBridge 171:3a7713b1edbc 12264 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12265 -- USBDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12266 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12267
AnnaBridge 171:3a7713b1edbc 12268 /*!
AnnaBridge 171:3a7713b1edbc 12269 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12270 * @{
AnnaBridge 171:3a7713b1edbc 12271 */
AnnaBridge 171:3a7713b1edbc 12272
AnnaBridge 171:3a7713b1edbc 12273 /** USBDCD - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12274 typedef struct {
AnnaBridge 171:3a7713b1edbc 12275 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12276 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 12277 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 12278 uint8_t RESERVED_0[4];
AnnaBridge 171:3a7713b1edbc 12279 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 12280 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 12281 union { /* offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 12282 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 12283 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
AnnaBridge 171:3a7713b1edbc 12284 };
AnnaBridge 171:3a7713b1edbc 12285 } USBDCD_Type;
AnnaBridge 171:3a7713b1edbc 12286
AnnaBridge 171:3a7713b1edbc 12287 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12288 -- USBDCD Register Masks
AnnaBridge 171:3a7713b1edbc 12289 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12290
AnnaBridge 171:3a7713b1edbc 12291 /*!
AnnaBridge 171:3a7713b1edbc 12292 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
AnnaBridge 171:3a7713b1edbc 12293 * @{
AnnaBridge 171:3a7713b1edbc 12294 */
AnnaBridge 171:3a7713b1edbc 12295
AnnaBridge 171:3a7713b1edbc 12296 /*! @name CONTROL - Control register */
AnnaBridge 171:3a7713b1edbc 12297 #define USBDCD_CONTROL_IACK_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12298 #define USBDCD_CONTROL_IACK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12299 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
AnnaBridge 171:3a7713b1edbc 12300 #define USBDCD_CONTROL_IF_MASK (0x100U)
AnnaBridge 171:3a7713b1edbc 12301 #define USBDCD_CONTROL_IF_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12302 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
AnnaBridge 171:3a7713b1edbc 12303 #define USBDCD_CONTROL_IE_MASK (0x10000U)
AnnaBridge 171:3a7713b1edbc 12304 #define USBDCD_CONTROL_IE_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12305 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
AnnaBridge 171:3a7713b1edbc 12306 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
AnnaBridge 171:3a7713b1edbc 12307 #define USBDCD_CONTROL_BC12_SHIFT (17U)
AnnaBridge 171:3a7713b1edbc 12308 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
AnnaBridge 171:3a7713b1edbc 12309 #define USBDCD_CONTROL_START_MASK (0x1000000U)
AnnaBridge 171:3a7713b1edbc 12310 #define USBDCD_CONTROL_START_SHIFT (24U)
AnnaBridge 171:3a7713b1edbc 12311 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
AnnaBridge 171:3a7713b1edbc 12312 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
AnnaBridge 171:3a7713b1edbc 12313 #define USBDCD_CONTROL_SR_SHIFT (25U)
AnnaBridge 171:3a7713b1edbc 12314 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
AnnaBridge 171:3a7713b1edbc 12315
AnnaBridge 171:3a7713b1edbc 12316 /*! @name CLOCK - Clock register */
AnnaBridge 171:3a7713b1edbc 12317 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12318 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12319 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
AnnaBridge 171:3a7713b1edbc 12320 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
AnnaBridge 171:3a7713b1edbc 12321 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12322 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge 171:3a7713b1edbc 12323
AnnaBridge 171:3a7713b1edbc 12324 /*! @name STATUS - Status register */
AnnaBridge 171:3a7713b1edbc 12325 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
AnnaBridge 171:3a7713b1edbc 12326 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12327 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
AnnaBridge 171:3a7713b1edbc 12328 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
AnnaBridge 171:3a7713b1edbc 12329 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
AnnaBridge 171:3a7713b1edbc 12330 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge 171:3a7713b1edbc 12331 #define USBDCD_STATUS_ERR_MASK (0x100000U)
AnnaBridge 171:3a7713b1edbc 12332 #define USBDCD_STATUS_ERR_SHIFT (20U)
AnnaBridge 171:3a7713b1edbc 12333 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
AnnaBridge 171:3a7713b1edbc 12334 #define USBDCD_STATUS_TO_MASK (0x200000U)
AnnaBridge 171:3a7713b1edbc 12335 #define USBDCD_STATUS_TO_SHIFT (21U)
AnnaBridge 171:3a7713b1edbc 12336 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
AnnaBridge 171:3a7713b1edbc 12337 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
AnnaBridge 171:3a7713b1edbc 12338 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
AnnaBridge 171:3a7713b1edbc 12339 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
AnnaBridge 171:3a7713b1edbc 12340
AnnaBridge 171:3a7713b1edbc 12341 /*! @name TIMER0 - TIMER0 register */
AnnaBridge 171:3a7713b1edbc 12342 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
AnnaBridge 171:3a7713b1edbc 12343 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12344 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
AnnaBridge 171:3a7713b1edbc 12345 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 12346 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12347 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge 171:3a7713b1edbc 12348
AnnaBridge 171:3a7713b1edbc 12349 /*! @name TIMER1 - TIMER1 register */
AnnaBridge 171:3a7713b1edbc 12350 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 12351 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12352 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 12353 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 12354 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12355 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge 171:3a7713b1edbc 12356
AnnaBridge 171:3a7713b1edbc 12357 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
AnnaBridge 171:3a7713b1edbc 12358 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
AnnaBridge 171:3a7713b1edbc 12359 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12360 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
AnnaBridge 171:3a7713b1edbc 12361 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 12362 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12363 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
AnnaBridge 171:3a7713b1edbc 12364
AnnaBridge 171:3a7713b1edbc 12365 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
AnnaBridge 171:3a7713b1edbc 12366 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
AnnaBridge 171:3a7713b1edbc 12367 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12368 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
AnnaBridge 171:3a7713b1edbc 12369 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
AnnaBridge 171:3a7713b1edbc 12370 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
AnnaBridge 171:3a7713b1edbc 12371 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
AnnaBridge 171:3a7713b1edbc 12372
AnnaBridge 171:3a7713b1edbc 12373
AnnaBridge 171:3a7713b1edbc 12374 /*!
AnnaBridge 171:3a7713b1edbc 12375 * @}
AnnaBridge 171:3a7713b1edbc 12376 */ /* end of group USBDCD_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12377
AnnaBridge 171:3a7713b1edbc 12378
AnnaBridge 171:3a7713b1edbc 12379 /* USBDCD - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12380 /** Peripheral USBDCD base address */
AnnaBridge 171:3a7713b1edbc 12381 #define USBDCD_BASE (0x40035000u)
AnnaBridge 171:3a7713b1edbc 12382 /** Peripheral USBDCD base pointer */
AnnaBridge 171:3a7713b1edbc 12383 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
AnnaBridge 171:3a7713b1edbc 12384 /** Array initializer of USBDCD peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12385 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
AnnaBridge 171:3a7713b1edbc 12386 /** Array initializer of USBDCD peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12387 #define USBDCD_BASE_PTRS { USBDCD }
AnnaBridge 171:3a7713b1edbc 12388 /** Interrupt vectors for the USBDCD peripheral type */
AnnaBridge 171:3a7713b1edbc 12389 #define USBDCD_IRQS { USBDCD_IRQn }
AnnaBridge 171:3a7713b1edbc 12390
AnnaBridge 171:3a7713b1edbc 12391 /*!
AnnaBridge 171:3a7713b1edbc 12392 * @}
AnnaBridge 171:3a7713b1edbc 12393 */ /* end of group USBDCD_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12394
AnnaBridge 171:3a7713b1edbc 12395
AnnaBridge 171:3a7713b1edbc 12396 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12397 -- VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12398 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12399
AnnaBridge 171:3a7713b1edbc 12400 /*!
AnnaBridge 171:3a7713b1edbc 12401 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12402 * @{
AnnaBridge 171:3a7713b1edbc 12403 */
AnnaBridge 171:3a7713b1edbc 12404
AnnaBridge 171:3a7713b1edbc 12405 /** VREF - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12406 typedef struct {
AnnaBridge 171:3a7713b1edbc 12407 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12408 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
AnnaBridge 171:3a7713b1edbc 12409 } VREF_Type;
AnnaBridge 171:3a7713b1edbc 12410
AnnaBridge 171:3a7713b1edbc 12411 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12412 -- VREF Register Masks
AnnaBridge 171:3a7713b1edbc 12413 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12414
AnnaBridge 171:3a7713b1edbc 12415 /*!
AnnaBridge 171:3a7713b1edbc 12416 * @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge 171:3a7713b1edbc 12417 * @{
AnnaBridge 171:3a7713b1edbc 12418 */
AnnaBridge 171:3a7713b1edbc 12419
AnnaBridge 171:3a7713b1edbc 12420 /*! @name TRM - VREF Trim Register */
AnnaBridge 171:3a7713b1edbc 12421 #define VREF_TRM_TRIM_MASK (0x3FU)
AnnaBridge 171:3a7713b1edbc 12422 #define VREF_TRM_TRIM_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12423 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
AnnaBridge 171:3a7713b1edbc 12424 #define VREF_TRM_CHOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12425 #define VREF_TRM_CHOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12426 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 12427
AnnaBridge 171:3a7713b1edbc 12428 /*! @name SC - VREF Status and Control Register */
AnnaBridge 171:3a7713b1edbc 12429 #define VREF_SC_MODE_LV_MASK (0x3U)
AnnaBridge 171:3a7713b1edbc 12430 #define VREF_SC_MODE_LV_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12431 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
AnnaBridge 171:3a7713b1edbc 12432 #define VREF_SC_VREFST_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12433 #define VREF_SC_VREFST_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12434 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
AnnaBridge 171:3a7713b1edbc 12435 #define VREF_SC_ICOMPEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12436 #define VREF_SC_ICOMPEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12437 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
AnnaBridge 171:3a7713b1edbc 12438 #define VREF_SC_REGEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12439 #define VREF_SC_REGEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12440 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12441 #define VREF_SC_VREFEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12442 #define VREF_SC_VREFEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12443 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
AnnaBridge 171:3a7713b1edbc 12444
AnnaBridge 171:3a7713b1edbc 12445
AnnaBridge 171:3a7713b1edbc 12446 /*!
AnnaBridge 171:3a7713b1edbc 12447 * @}
AnnaBridge 171:3a7713b1edbc 12448 */ /* end of group VREF_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12449
AnnaBridge 171:3a7713b1edbc 12450
AnnaBridge 171:3a7713b1edbc 12451 /* VREF - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12452 /** Peripheral VREF base address */
AnnaBridge 171:3a7713b1edbc 12453 #define VREF_BASE (0x40074000u)
AnnaBridge 171:3a7713b1edbc 12454 /** Peripheral VREF base pointer */
AnnaBridge 171:3a7713b1edbc 12455 #define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge 171:3a7713b1edbc 12456 /** Array initializer of VREF peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12457 #define VREF_BASE_ADDRS { VREF_BASE }
AnnaBridge 171:3a7713b1edbc 12458 /** Array initializer of VREF peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12459 #define VREF_BASE_PTRS { VREF }
AnnaBridge 171:3a7713b1edbc 12460
AnnaBridge 171:3a7713b1edbc 12461 /*!
AnnaBridge 171:3a7713b1edbc 12462 * @}
AnnaBridge 171:3a7713b1edbc 12463 */ /* end of group VREF_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12464
AnnaBridge 171:3a7713b1edbc 12465
AnnaBridge 171:3a7713b1edbc 12466 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12467 -- WDOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12468 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12469
AnnaBridge 171:3a7713b1edbc 12470 /*!
AnnaBridge 171:3a7713b1edbc 12471 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
AnnaBridge 171:3a7713b1edbc 12472 * @{
AnnaBridge 171:3a7713b1edbc 12473 */
AnnaBridge 171:3a7713b1edbc 12474
AnnaBridge 171:3a7713b1edbc 12475 /** WDOG - Register Layout Typedef */
AnnaBridge 171:3a7713b1edbc 12476 typedef struct {
AnnaBridge 171:3a7713b1edbc 12477 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
AnnaBridge 171:3a7713b1edbc 12478 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
AnnaBridge 171:3a7713b1edbc 12479 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
AnnaBridge 171:3a7713b1edbc 12480 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
AnnaBridge 171:3a7713b1edbc 12481 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
AnnaBridge 171:3a7713b1edbc 12482 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
AnnaBridge 171:3a7713b1edbc 12483 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
AnnaBridge 171:3a7713b1edbc 12484 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
AnnaBridge 171:3a7713b1edbc 12485 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
AnnaBridge 171:3a7713b1edbc 12486 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
AnnaBridge 171:3a7713b1edbc 12487 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
AnnaBridge 171:3a7713b1edbc 12488 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
AnnaBridge 171:3a7713b1edbc 12489 } WDOG_Type;
AnnaBridge 171:3a7713b1edbc 12490
AnnaBridge 171:3a7713b1edbc 12491 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12492 -- WDOG Register Masks
AnnaBridge 171:3a7713b1edbc 12493 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12494
AnnaBridge 171:3a7713b1edbc 12495 /*!
AnnaBridge 171:3a7713b1edbc 12496 * @addtogroup WDOG_Register_Masks WDOG Register Masks
AnnaBridge 171:3a7713b1edbc 12497 * @{
AnnaBridge 171:3a7713b1edbc 12498 */
AnnaBridge 171:3a7713b1edbc 12499
AnnaBridge 171:3a7713b1edbc 12500 /*! @name STCTRLH - Watchdog Status and Control Register High */
AnnaBridge 171:3a7713b1edbc 12501 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
AnnaBridge 171:3a7713b1edbc 12502 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12503 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12504 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
AnnaBridge 171:3a7713b1edbc 12505 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
AnnaBridge 171:3a7713b1edbc 12506 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
AnnaBridge 171:3a7713b1edbc 12507 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
AnnaBridge 171:3a7713b1edbc 12508 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
AnnaBridge 171:3a7713b1edbc 12509 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
AnnaBridge 171:3a7713b1edbc 12510 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
AnnaBridge 171:3a7713b1edbc 12511 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
AnnaBridge 171:3a7713b1edbc 12512 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
AnnaBridge 171:3a7713b1edbc 12513 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
AnnaBridge 171:3a7713b1edbc 12514 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
AnnaBridge 171:3a7713b1edbc 12515 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
AnnaBridge 171:3a7713b1edbc 12516 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
AnnaBridge 171:3a7713b1edbc 12517 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
AnnaBridge 171:3a7713b1edbc 12518 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
AnnaBridge 171:3a7713b1edbc 12519 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
AnnaBridge 171:3a7713b1edbc 12520 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
AnnaBridge 171:3a7713b1edbc 12521 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
AnnaBridge 171:3a7713b1edbc 12522 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
AnnaBridge 171:3a7713b1edbc 12523 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
AnnaBridge 171:3a7713b1edbc 12524 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
AnnaBridge 171:3a7713b1edbc 12525 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
AnnaBridge 171:3a7713b1edbc 12526 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
AnnaBridge 171:3a7713b1edbc 12527 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 12528 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
AnnaBridge 171:3a7713b1edbc 12529 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
AnnaBridge 171:3a7713b1edbc 12530 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
AnnaBridge 171:3a7713b1edbc 12531 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
AnnaBridge 171:3a7713b1edbc 12532 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
AnnaBridge 171:3a7713b1edbc 12533 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
AnnaBridge 171:3a7713b1edbc 12534 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
AnnaBridge 171:3a7713b1edbc 12535 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
AnnaBridge 171:3a7713b1edbc 12536 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
AnnaBridge 171:3a7713b1edbc 12537
AnnaBridge 171:3a7713b1edbc 12538 /*! @name STCTRLL - Watchdog Status and Control Register Low */
AnnaBridge 171:3a7713b1edbc 12539 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
AnnaBridge 171:3a7713b1edbc 12540 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
AnnaBridge 171:3a7713b1edbc 12541 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
AnnaBridge 171:3a7713b1edbc 12542
AnnaBridge 171:3a7713b1edbc 12543 /*! @name TOVALH - Watchdog Time-out Value Register High */
AnnaBridge 171:3a7713b1edbc 12544 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12545 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12546 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 12547
AnnaBridge 171:3a7713b1edbc 12548 /*! @name TOVALL - Watchdog Time-out Value Register Low */
AnnaBridge 171:3a7713b1edbc 12549 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12550 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12551 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
AnnaBridge 171:3a7713b1edbc 12552
AnnaBridge 171:3a7713b1edbc 12553 /*! @name WINH - Watchdog Window Register High */
AnnaBridge 171:3a7713b1edbc 12554 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12555 #define WDOG_WINH_WINHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12556 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 12557
AnnaBridge 171:3a7713b1edbc 12558 /*! @name WINL - Watchdog Window Register Low */
AnnaBridge 171:3a7713b1edbc 12559 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12560 #define WDOG_WINL_WINLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12561 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
AnnaBridge 171:3a7713b1edbc 12562
AnnaBridge 171:3a7713b1edbc 12563 /*! @name REFRESH - Watchdog Refresh register */
AnnaBridge 171:3a7713b1edbc 12564 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12565 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12566 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
AnnaBridge 171:3a7713b1edbc 12567
AnnaBridge 171:3a7713b1edbc 12568 /*! @name UNLOCK - Watchdog Unlock register */
AnnaBridge 171:3a7713b1edbc 12569 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12570 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12571 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
AnnaBridge 171:3a7713b1edbc 12572
AnnaBridge 171:3a7713b1edbc 12573 /*! @name TMROUTH - Watchdog Timer Output Register High */
AnnaBridge 171:3a7713b1edbc 12574 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12575 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12576 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
AnnaBridge 171:3a7713b1edbc 12577
AnnaBridge 171:3a7713b1edbc 12578 /*! @name TMROUTL - Watchdog Timer Output Register Low */
AnnaBridge 171:3a7713b1edbc 12579 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12580 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12581 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
AnnaBridge 171:3a7713b1edbc 12582
AnnaBridge 171:3a7713b1edbc 12583 /*! @name RSTCNT - Watchdog Reset Count register */
AnnaBridge 171:3a7713b1edbc 12584 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
AnnaBridge 171:3a7713b1edbc 12585 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
AnnaBridge 171:3a7713b1edbc 12586 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
AnnaBridge 171:3a7713b1edbc 12587
AnnaBridge 171:3a7713b1edbc 12588 /*! @name PRESC - Watchdog Prescaler register */
AnnaBridge 171:3a7713b1edbc 12589 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
AnnaBridge 171:3a7713b1edbc 12590 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
AnnaBridge 171:3a7713b1edbc 12591 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
AnnaBridge 171:3a7713b1edbc 12592
AnnaBridge 171:3a7713b1edbc 12593
AnnaBridge 171:3a7713b1edbc 12594 /*!
AnnaBridge 171:3a7713b1edbc 12595 * @}
AnnaBridge 171:3a7713b1edbc 12596 */ /* end of group WDOG_Register_Masks */
AnnaBridge 171:3a7713b1edbc 12597
AnnaBridge 171:3a7713b1edbc 12598
AnnaBridge 171:3a7713b1edbc 12599 /* WDOG - Peripheral instance base addresses */
AnnaBridge 171:3a7713b1edbc 12600 /** Peripheral WDOG base address */
AnnaBridge 171:3a7713b1edbc 12601 #define WDOG_BASE (0x40052000u)
AnnaBridge 171:3a7713b1edbc 12602 /** Peripheral WDOG base pointer */
AnnaBridge 171:3a7713b1edbc 12603 #define WDOG ((WDOG_Type *)WDOG_BASE)
AnnaBridge 171:3a7713b1edbc 12604 /** Array initializer of WDOG peripheral base addresses */
AnnaBridge 171:3a7713b1edbc 12605 #define WDOG_BASE_ADDRS { WDOG_BASE }
AnnaBridge 171:3a7713b1edbc 12606 /** Array initializer of WDOG peripheral base pointers */
AnnaBridge 171:3a7713b1edbc 12607 #define WDOG_BASE_PTRS { WDOG }
AnnaBridge 171:3a7713b1edbc 12608 /** Interrupt vectors for the WDOG peripheral type */
AnnaBridge 171:3a7713b1edbc 12609 #define WDOG_IRQS { WDOG_EWM_IRQn }
AnnaBridge 171:3a7713b1edbc 12610
AnnaBridge 171:3a7713b1edbc 12611 /*!
AnnaBridge 171:3a7713b1edbc 12612 * @}
AnnaBridge 171:3a7713b1edbc 12613 */ /* end of group WDOG_Peripheral_Access_Layer */
AnnaBridge 171:3a7713b1edbc 12614
AnnaBridge 171:3a7713b1edbc 12615
AnnaBridge 171:3a7713b1edbc 12616 /*
AnnaBridge 171:3a7713b1edbc 12617 ** End of section using anonymous unions
AnnaBridge 171:3a7713b1edbc 12618 */
AnnaBridge 171:3a7713b1edbc 12619
AnnaBridge 171:3a7713b1edbc 12620 #if defined(__ARMCC_VERSION)
AnnaBridge 171:3a7713b1edbc 12621 #pragma pop
AnnaBridge 171:3a7713b1edbc 12622 #elif defined(__CWCC__)
AnnaBridge 171:3a7713b1edbc 12623 #pragma pop
AnnaBridge 171:3a7713b1edbc 12624 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 12625 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 12626 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 171:3a7713b1edbc 12627 #pragma language=default
AnnaBridge 171:3a7713b1edbc 12628 #else
AnnaBridge 171:3a7713b1edbc 12629 #error Not supported compiler type
AnnaBridge 171:3a7713b1edbc 12630 #endif
AnnaBridge 171:3a7713b1edbc 12631
AnnaBridge 171:3a7713b1edbc 12632 /*!
AnnaBridge 171:3a7713b1edbc 12633 * @}
AnnaBridge 171:3a7713b1edbc 12634 */ /* end of group Peripheral_access_layer */
AnnaBridge 171:3a7713b1edbc 12635
AnnaBridge 171:3a7713b1edbc 12636
AnnaBridge 171:3a7713b1edbc 12637 /* ----------------------------------------------------------------------------
AnnaBridge 171:3a7713b1edbc 12638 -- SDK Compatibility
AnnaBridge 171:3a7713b1edbc 12639 ---------------------------------------------------------------------------- */
AnnaBridge 171:3a7713b1edbc 12640
AnnaBridge 171:3a7713b1edbc 12641 /*!
AnnaBridge 171:3a7713b1edbc 12642 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 171:3a7713b1edbc 12643 * @{
AnnaBridge 171:3a7713b1edbc 12644 */
AnnaBridge 171:3a7713b1edbc 12645
AnnaBridge 171:3a7713b1edbc 12646 #define ENET_RMON_R_DROP_REG(base) ENET_IEEE_R_DROP_REG(base)
AnnaBridge 171:3a7713b1edbc 12647 #define ENET_RMON_R_FRAME_OK_REG(base) ENET_IEEE_R_FRAME_OK_REG(base)
AnnaBridge 171:3a7713b1edbc 12648 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
AnnaBridge 171:3a7713b1edbc 12649 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
AnnaBridge 171:3a7713b1edbc 12650 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
AnnaBridge 171:3a7713b1edbc 12651 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
AnnaBridge 171:3a7713b1edbc 12652 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
AnnaBridge 171:3a7713b1edbc 12653 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
AnnaBridge 171:3a7713b1edbc 12654 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
AnnaBridge 171:3a7713b1edbc 12655 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
AnnaBridge 171:3a7713b1edbc 12656 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
AnnaBridge 171:3a7713b1edbc 12657 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
AnnaBridge 171:3a7713b1edbc 12658 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
AnnaBridge 171:3a7713b1edbc 12659 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
AnnaBridge 171:3a7713b1edbc 12660 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
AnnaBridge 171:3a7713b1edbc 12661 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
AnnaBridge 171:3a7713b1edbc 12662 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
AnnaBridge 171:3a7713b1edbc 12663 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
AnnaBridge 171:3a7713b1edbc 12664 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
AnnaBridge 171:3a7713b1edbc 12665 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
AnnaBridge 171:3a7713b1edbc 12666 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
AnnaBridge 171:3a7713b1edbc 12667 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
AnnaBridge 171:3a7713b1edbc 12668 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
AnnaBridge 171:3a7713b1edbc 12669 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
AnnaBridge 171:3a7713b1edbc 12670 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
AnnaBridge 171:3a7713b1edbc 12671 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
AnnaBridge 171:3a7713b1edbc 12672 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
AnnaBridge 171:3a7713b1edbc 12673 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
AnnaBridge 171:3a7713b1edbc 12674 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
AnnaBridge 171:3a7713b1edbc 12675 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
AnnaBridge 171:3a7713b1edbc 12676 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
AnnaBridge 171:3a7713b1edbc 12677 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
AnnaBridge 171:3a7713b1edbc 12678 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
AnnaBridge 171:3a7713b1edbc 12679 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
AnnaBridge 171:3a7713b1edbc 12680 #define DSPI0 SPI0
AnnaBridge 171:3a7713b1edbc 12681 #define DSPI1 SPI1
AnnaBridge 171:3a7713b1edbc 12682 #define DSPI2 SPI2
AnnaBridge 171:3a7713b1edbc 12683 #define FLEXCAN0 CAN0
AnnaBridge 171:3a7713b1edbc 12684 #define PTA_BASE GPIOA_BASE
AnnaBridge 171:3a7713b1edbc 12685 #define PTA GPIOA
AnnaBridge 171:3a7713b1edbc 12686 #define PTB_BASE GPIOB_BASE
AnnaBridge 171:3a7713b1edbc 12687 #define PTB GPIOB
AnnaBridge 171:3a7713b1edbc 12688 #define PTC_BASE GPIOC_BASE
AnnaBridge 171:3a7713b1edbc 12689 #define PTC GPIOC
AnnaBridge 171:3a7713b1edbc 12690 #define PTD_BASE GPIOD_BASE
AnnaBridge 171:3a7713b1edbc 12691 #define PTD GPIOD
AnnaBridge 171:3a7713b1edbc 12692 #define PTE_BASE GPIOE_BASE
AnnaBridge 171:3a7713b1edbc 12693 #define PTE GPIOE
AnnaBridge 171:3a7713b1edbc 12694 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
AnnaBridge 171:3a7713b1edbc 12695 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
AnnaBridge 171:3a7713b1edbc 12696 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
AnnaBridge 171:3a7713b1edbc 12697 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
AnnaBridge 171:3a7713b1edbc 12698 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
AnnaBridge 171:3a7713b1edbc 12699 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
AnnaBridge 171:3a7713b1edbc 12700 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
AnnaBridge 171:3a7713b1edbc 12701 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
AnnaBridge 171:3a7713b1edbc 12702 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
AnnaBridge 171:3a7713b1edbc 12703 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
AnnaBridge 171:3a7713b1edbc 12704 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
AnnaBridge 171:3a7713b1edbc 12705 #define Watchdog_IRQn WDOG_EWM_IRQn
AnnaBridge 171:3a7713b1edbc 12706 #define Watchdog_IRQHandler WDOG_EWM_IRQHandler
AnnaBridge 171:3a7713b1edbc 12707 #define LPTimer_IRQn LPTMR0_IRQn
AnnaBridge 171:3a7713b1edbc 12708 #define LPTimer_IRQHandler LPTMR0_IRQHandler
AnnaBridge 171:3a7713b1edbc 12709 #define LLW_IRQn LLWU_IRQn
AnnaBridge 171:3a7713b1edbc 12710 #define LLW_IRQHandler LLWU_IRQHandler
AnnaBridge 171:3a7713b1edbc 12711 #define DMAMUX0 DMAMUX
AnnaBridge 171:3a7713b1edbc 12712 #define WDOG0 WDOG
AnnaBridge 171:3a7713b1edbc 12713 #define MCM0 MCM
AnnaBridge 171:3a7713b1edbc 12714 #define RTC0 RTC
AnnaBridge 171:3a7713b1edbc 12715
AnnaBridge 171:3a7713b1edbc 12716 /*!
AnnaBridge 171:3a7713b1edbc 12717 * @}
AnnaBridge 171:3a7713b1edbc 12718 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 171:3a7713b1edbc 12719
AnnaBridge 171:3a7713b1edbc 12720
AnnaBridge 171:3a7713b1edbc 12721 #endif /* _MK64F12_H_ */
AnnaBridge 171:3a7713b1edbc 12722