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TARGET_EFM32WG_STK3800/TOOLCHAIN_ARM_STD/em_smu.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file em_smu.h
Anna Bridge 142:4eea097334d6 3 * @brief Security Management Unit (SMU) peripheral API
Anna Bridge 160:5571c4ff569f 4 * @version 5.3.3
Anna Bridge 142:4eea097334d6 5 *******************************************************************************
Anna Bridge 160:5571c4ff569f 6 * # License
Anna Bridge 142:4eea097334d6 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 8 *******************************************************************************
Anna Bridge 142:4eea097334d6 9 *
Anna Bridge 142:4eea097334d6 10 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 11 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 12 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 13 *
Anna Bridge 142:4eea097334d6 14 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 15 * claim that you wrote the original software.
Anna Bridge 142:4eea097334d6 16 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 17 * misrepresented as being the original software.
Anna Bridge 142:4eea097334d6 18 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 19 *
Anna Bridge 142:4eea097334d6 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
Anna Bridge 142:4eea097334d6 21 * obligation to support this Software. Silicon Labs is providing the
Anna Bridge 142:4eea097334d6 22 * Software "AS IS", with no express or implied warranties of any kind,
Anna Bridge 142:4eea097334d6 23 * including, but not limited to, any implied warranties of merchantability
Anna Bridge 142:4eea097334d6 24 * or fitness for any particular purpose or warranties against infringement
Anna Bridge 142:4eea097334d6 25 * of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 26 *
Anna Bridge 142:4eea097334d6 27 * Silicon Labs will not be liable for any consequential, incidental, or
Anna Bridge 142:4eea097334d6 28 * special damages, or any other relief, or for any claim by any third party,
Anna Bridge 142:4eea097334d6 29 * arising from your use of this Software.
Anna Bridge 142:4eea097334d6 30 *
Anna Bridge 142:4eea097334d6 31 ******************************************************************************/
Anna Bridge 142:4eea097334d6 32
Anna Bridge 142:4eea097334d6 33 #ifndef EM_SMU_H
Anna Bridge 142:4eea097334d6 34 #define EM_SMU_H
Anna Bridge 142:4eea097334d6 35
Anna Bridge 142:4eea097334d6 36 #include "em_device.h"
Anna Bridge 142:4eea097334d6 37 #if defined(SMU_COUNT) && (SMU_COUNT > 0)
Anna Bridge 142:4eea097334d6 38
Anna Bridge 142:4eea097334d6 39 #include "em_assert.h"
Anna Bridge 142:4eea097334d6 40 #include "em_bus.h"
Anna Bridge 142:4eea097334d6 41
Anna Bridge 142:4eea097334d6 42 #include <stdint.h>
Anna Bridge 142:4eea097334d6 43 #include <stdbool.h>
Anna Bridge 142:4eea097334d6 44
Anna Bridge 142:4eea097334d6 45 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 46 extern "C" {
Anna Bridge 142:4eea097334d6 47 #endif
Anna Bridge 142:4eea097334d6 48
Anna Bridge 142:4eea097334d6 49 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 50 * @addtogroup emlib
Anna Bridge 142:4eea097334d6 51 * @{
Anna Bridge 142:4eea097334d6 52 ******************************************************************************/
Anna Bridge 142:4eea097334d6 53
Anna Bridge 142:4eea097334d6 54 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 55 * @addtogroup SMU
Anna Bridge 142:4eea097334d6 56 * @brief Security Management Unit (SMU) Peripheral API
Anna Bridge 142:4eea097334d6 57 *
Anna Bridge 142:4eea097334d6 58 * @details
Anna Bridge 142:4eea097334d6 59 * The Security Management Unit (SMU) forms the control and status/reporting
Anna Bridge 142:4eea097334d6 60 * component of bus-level security in EFM32/EFR32 devices.
Anna Bridge 142:4eea097334d6 61 *
Anna Bridge 142:4eea097334d6 62 * Peripheral-level protection is provided via the peripheral protection unit
Anna Bridge 142:4eea097334d6 63 * (PPU). The PPU provides a hardware access barrier to any peripheral that is
Anna Bridge 142:4eea097334d6 64 * configured to be protected. When an attempt is made to access a peripheral
Anna Bridge 142:4eea097334d6 65 * without the required privilege/security level, the PPU detects the fault
Anna Bridge 142:4eea097334d6 66 * and intercepts the access. No write or read of the peripheral register
Anna Bridge 142:4eea097334d6 67 * space occurs, and an all-zero value is returned if the access is a read.
Anna Bridge 142:4eea097334d6 68 *
Anna Bridge 142:4eea097334d6 69 * @subsection Usage example
Anna Bridge 142:4eea097334d6 70 * @include em_smu_init.c
Anna Bridge 142:4eea097334d6 71 * @{
Anna Bridge 142:4eea097334d6 72 ******************************************************************************/
Anna Bridge 142:4eea097334d6 73
Anna Bridge 142:4eea097334d6 74 /*******************************************************************************
Anna Bridge 142:4eea097334d6 75 ******************************** ENUMS ************************************
Anna Bridge 142:4eea097334d6 76 ******************************************************************************/
Anna Bridge 142:4eea097334d6 77
Anna Bridge 142:4eea097334d6 78 /** SMU peripheral identifiers. */
Anna Bridge 142:4eea097334d6 79 typedef enum {
Anna Bridge 142:4eea097334d6 80 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
Anna Bridge 142:4eea097334d6 81 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 142:4eea097334d6 82 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 142:4eea097334d6 83 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 142:4eea097334d6 84 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 142:4eea097334d6 85 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 142:4eea097334d6 86 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 142:4eea097334d6 87 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
Anna Bridge 142:4eea097334d6 88 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
Anna Bridge 142:4eea097334d6 89 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 142:4eea097334d6 90 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 142:4eea097334d6 91 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 142:4eea097334d6 92 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
Anna Bridge 142:4eea097334d6 93 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 142:4eea097334d6 94 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 142:4eea097334d6 95 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 142:4eea097334d6 96 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
Anna Bridge 142:4eea097334d6 97 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
Anna Bridge 142:4eea097334d6 98 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
Anna Bridge 142:4eea097334d6 99 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 142:4eea097334d6 100 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 142:4eea097334d6 101 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 142:4eea097334d6 102 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 142:4eea097334d6 103 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 142:4eea097334d6 104 smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
Anna Bridge 142:4eea097334d6 105 smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
Anna Bridge 142:4eea097334d6 106 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 142:4eea097334d6 107 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 142:4eea097334d6 108 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 142:4eea097334d6 109 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 142:4eea097334d6 110 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
Anna Bridge 142:4eea097334d6 111 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 142:4eea097334d6 112 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 142:4eea097334d6 113 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 142:4eea097334d6 114 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
Anna Bridge 142:4eea097334d6 115 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
Anna Bridge 142:4eea097334d6 116 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 142:4eea097334d6 117 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
Anna Bridge 142:4eea097334d6 118 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 142:4eea097334d6 119 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
Anna Bridge 142:4eea097334d6 120
Anna Bridge 142:4eea097334d6 121 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
Anna Bridge 142:4eea097334d6 122 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 142:4eea097334d6 123 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 142:4eea097334d6 124 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 142:4eea097334d6 125 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 142:4eea097334d6 126 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 142:4eea097334d6 127 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 142:4eea097334d6 128 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
Anna Bridge 160:5571c4ff569f 129 #if defined(_SMU_PPUPATD0_CSEN_SHIFT)
Anna Bridge 142:4eea097334d6 130 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
Anna Bridge 160:5571c4ff569f 131 #endif
Anna Bridge 160:5571c4ff569f 132 #if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
Anna Bridge 142:4eea097334d6 133 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 160:5571c4ff569f 134 #endif
Anna Bridge 142:4eea097334d6 135 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 142:4eea097334d6 136 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 142:4eea097334d6 137 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
Anna Bridge 142:4eea097334d6 138 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 142:4eea097334d6 139 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 142:4eea097334d6 140 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 142:4eea097334d6 141 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
Anna Bridge 160:5571c4ff569f 142 #if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
Anna Bridge 142:4eea097334d6 143 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
Anna Bridge 160:5571c4ff569f 144 #endif
Anna Bridge 142:4eea097334d6 145 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
Anna Bridge 142:4eea097334d6 146 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 142:4eea097334d6 147 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 142:4eea097334d6 148 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 142:4eea097334d6 149 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 142:4eea097334d6 150 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 142:4eea097334d6 151 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 142:4eea097334d6 152 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 142:4eea097334d6 153 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 142:4eea097334d6 154 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 142:4eea097334d6 155 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
Anna Bridge 142:4eea097334d6 156 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 142:4eea097334d6 157 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 142:4eea097334d6 158 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 142:4eea097334d6 159 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
Anna Bridge 142:4eea097334d6 160 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 142:4eea097334d6 161 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
Anna Bridge 142:4eea097334d6 162 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 142:4eea097334d6 163
Anna Bridge 160:5571c4ff569f 164 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
Anna Bridge 160:5571c4ff569f 165 #if defined(_SMU_PPUPATD0_ACMP0_SHIFT)
Anna Bridge 160:5571c4ff569f 166 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 160:5571c4ff569f 167 #endif
Anna Bridge 160:5571c4ff569f 168 #if defined(_SMU_PPUPATD0_ACMP1_SHIFT)
Anna Bridge 160:5571c4ff569f 169 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 160:5571c4ff569f 170 #endif
Anna Bridge 160:5571c4ff569f 171 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 160:5571c4ff569f 172 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 160:5571c4ff569f 173 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 160:5571c4ff569f 174 smuPeripheralCRYPTO = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 160:5571c4ff569f 175 #if defined(_SMU_PPUPATD0_VDAC0_SHIFT)
Anna Bridge 160:5571c4ff569f 176 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 160:5571c4ff569f 177 #endif
Anna Bridge 160:5571c4ff569f 178 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 160:5571c4ff569f 179 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 160:5571c4ff569f 180 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
Anna Bridge 160:5571c4ff569f 181 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 160:5571c4ff569f 182 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 160:5571c4ff569f 183 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 160:5571c4ff569f 184 #if defined(_SMU_PPUPATD0_IDAC0_SHIFT)
Anna Bridge 160:5571c4ff569f 185 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
Anna Bridge 160:5571c4ff569f 186 #endif
Anna Bridge 160:5571c4ff569f 187 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
Anna Bridge 160:5571c4ff569f 188 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 160:5571c4ff569f 189 #if defined(_SMU_PPUPATD0_LESENSE_SHIFT)
Anna Bridge 160:5571c4ff569f 190 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 160:5571c4ff569f 191 #endif
Anna Bridge 160:5571c4ff569f 192 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 160:5571c4ff569f 193 smuPeripheralLEUART = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 160:5571c4ff569f 194 #if defined(_SMU_PPUPATD0_PCNT0_SHIFT)
Anna Bridge 160:5571c4ff569f 195 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 160:5571c4ff569f 196 #endif
Anna Bridge 160:5571c4ff569f 197 smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 160:5571c4ff569f 198 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 160:5571c4ff569f 199 smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 160:5571c4ff569f 200 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 160:5571c4ff569f 201 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
Anna Bridge 160:5571c4ff569f 202 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 160:5571c4ff569f 203 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 160:5571c4ff569f 204 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 160:5571c4ff569f 205 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 160:5571c4ff569f 206 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
Anna Bridge 160:5571c4ff569f 207 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 160:5571c4ff569f 208
Anna Bridge 160:5571c4ff569f 209 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
Anna Bridge 160:5571c4ff569f 210 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 160:5571c4ff569f 211 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 160:5571c4ff569f 212 smuPeripheralACMP2 = _SMU_PPUPATD0_ACMP2_SHIFT, /**< SMU peripheral identifier for ACMP2 */
Anna Bridge 160:5571c4ff569f 213 smuPeripheralACMP3 = _SMU_PPUPATD0_ACMP3_SHIFT, /**< SMU peripheral identifier for ACMP3 */
Anna Bridge 160:5571c4ff569f 214 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 160:5571c4ff569f 215 smuPeripheralADC1 = _SMU_PPUPATD0_ADC1_SHIFT, /**< SMU peripheral identifier for ADC1 */
Anna Bridge 160:5571c4ff569f 216 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
Anna Bridge 160:5571c4ff569f 217 smuPeripheralCAN1 = _SMU_PPUPATD0_CAN1_SHIFT, /**< SMU peripheral identifier for CAN1 */
Anna Bridge 160:5571c4ff569f 218 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 160:5571c4ff569f 219 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 160:5571c4ff569f 220 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 160:5571c4ff569f 221 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
Anna Bridge 160:5571c4ff569f 222 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 160:5571c4ff569f 223 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 160:5571c4ff569f 224 smuPeripheralEBI = _SMU_PPUPATD0_EBI_SHIFT, /**< SMU peripheral identifier for EBI */
Anna Bridge 160:5571c4ff569f 225 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 160:5571c4ff569f 226 #if defined(_SMU_PPUPATD0_ETH_SHIFT)
Anna Bridge 160:5571c4ff569f 227 smuPeripheralETH = _SMU_PPUPATD0_ETH_SHIFT, /**< SMU peripheral identifier for ETH */
Anna Bridge 160:5571c4ff569f 228 #endif
Anna Bridge 160:5571c4ff569f 229 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
Anna Bridge 160:5571c4ff569f 230 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 160:5571c4ff569f 231 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 160:5571c4ff569f 232 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 160:5571c4ff569f 233 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
Anna Bridge 160:5571c4ff569f 234 smuPeripheralI2C2 = _SMU_PPUPATD0_I2C2_SHIFT, /**< SMU peripheral identifier for I2C2 */
Anna Bridge 160:5571c4ff569f 235 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
Anna Bridge 160:5571c4ff569f 236 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
Anna Bridge 160:5571c4ff569f 237 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
Anna Bridge 160:5571c4ff569f 238 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
Anna Bridge 160:5571c4ff569f 239 #endif
Anna Bridge 160:5571c4ff569f 240 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 160:5571c4ff569f 241 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 160:5571c4ff569f 242 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 160:5571c4ff569f 243 smuPeripheralLETIMER1 = _SMU_PPUPATD0_LETIMER1_SHIFT, /**< SMU peripheral identifier for LETIMER1 */
Anna Bridge 160:5571c4ff569f 244 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 160:5571c4ff569f 245 smuPeripheralLEUART1 = _SMU_PPUPATD0_LEUART1_SHIFT, /**< SMU peripheral identifier for LEUART1 */
Anna Bridge 160:5571c4ff569f 246 smuPeripheralPCNT0 = 32 + _SMU_PPUPATD1_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 160:5571c4ff569f 247 smuPeripheralPCNT1 = 32 + _SMU_PPUPATD1_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
Anna Bridge 160:5571c4ff569f 248 smuPeripheralPCNT2 = 32 + _SMU_PPUPATD1_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
Anna Bridge 160:5571c4ff569f 249 #if defined(_SMU_PPUPATD1_QSPI0_SHIFT)
Anna Bridge 160:5571c4ff569f 250 smuPeripheralQSPI0 = 32 + _SMU_PPUPATD1_QSPI0_SHIFT, /**< SMU peripheral identifier for QSPI0 */
Anna Bridge 160:5571c4ff569f 251 #endif
Anna Bridge 160:5571c4ff569f 252 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 160:5571c4ff569f 253 smuPeripheralRTC = 32 + _SMU_PPUPATD1_RTC_SHIFT, /**< SMU peripheral identifier for RTC */
Anna Bridge 160:5571c4ff569f 254 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 160:5571c4ff569f 255 #if defined(_SMU_PPUPATD1_SDIO_SHIFT)
Anna Bridge 160:5571c4ff569f 256 smuPeripheralSDIO = 32 + _SMU_PPUPATD1_SDIO_SHIFT, /**< SMU peripheral identifier for SDIO */
Anna Bridge 160:5571c4ff569f 257 #endif
Anna Bridge 160:5571c4ff569f 258 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 160:5571c4ff569f 259 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 160:5571c4ff569f 260 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
Anna Bridge 160:5571c4ff569f 261 smuPeripheralTIMER2 = 32 + _SMU_PPUPATD1_TIMER2_SHIFT, /**< SMU peripheral identifier for TIMER2 */
Anna Bridge 160:5571c4ff569f 262 smuPeripheralTIMER3 = 32 + _SMU_PPUPATD1_TIMER3_SHIFT, /**< SMU peripheral identifier for TIMER3 */
Anna Bridge 160:5571c4ff569f 263 smuPeripheralTIMER4 = 32 + _SMU_PPUPATD1_TIMER4_SHIFT, /**< SMU peripheral identifier for TIMER4 */
Anna Bridge 160:5571c4ff569f 264 smuPeripheralTIMER5 = 32 + _SMU_PPUPATD1_TIMER5_SHIFT, /**< SMU peripheral identifier for TIMER5 */
Anna Bridge 160:5571c4ff569f 265 smuPeripheralTIMER6 = 32 + _SMU_PPUPATD1_TIMER6_SHIFT, /**< SMU peripheral identifier for TIMER6 */
Anna Bridge 160:5571c4ff569f 266 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 160:5571c4ff569f 267 smuPeripheralUART0 = 32 + _SMU_PPUPATD1_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
Anna Bridge 160:5571c4ff569f 268 smuPeripheralUART1 = 32 + _SMU_PPUPATD1_UART1_SHIFT, /**< SMU peripheral identifier for UART1 */
Anna Bridge 160:5571c4ff569f 269 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 160:5571c4ff569f 270 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 160:5571c4ff569f 271 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
Anna Bridge 160:5571c4ff569f 272 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
Anna Bridge 160:5571c4ff569f 273 smuPeripheralUSART4 = 32 + _SMU_PPUPATD1_USART4_SHIFT, /**< SMU peripheral identifier for USART4 */
Anna Bridge 160:5571c4ff569f 274 smuPeripheralUSART5 = 32 + _SMU_PPUPATD1_USART5_SHIFT, /**< SMU peripheral identifier for USART5 */
Anna Bridge 160:5571c4ff569f 275 #if defined(_SMU_PPUPATD1_USB_SHIFT)
Anna Bridge 160:5571c4ff569f 276 smuPeripheralUSB = 32 + _SMU_PPUPATD1_USB_SHIFT, /**< SMU peripheral identifier for USB */
Anna Bridge 160:5571c4ff569f 277 #endif
Anna Bridge 160:5571c4ff569f 278 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 160:5571c4ff569f 279 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
Anna Bridge 160:5571c4ff569f 280 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 160:5571c4ff569f 281 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
Anna Bridge 160:5571c4ff569f 282 smuPeripheralWTIMER2 = 32 + _SMU_PPUPATD1_WTIMER2_SHIFT, /**< SMU peripheral identifier for WTIMER2 */
Anna Bridge 160:5571c4ff569f 283 smuPeripheralWTIMER3 = 32 + _SMU_PPUPATD1_WTIMER3_SHIFT, /**< SMU peripheral identifier for WTIMER3 */
Anna Bridge 160:5571c4ff569f 284
Anna Bridge 160:5571c4ff569f 285 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
Anna Bridge 160:5571c4ff569f 286 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 160:5571c4ff569f 287 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 160:5571c4ff569f 288 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 160:5571c4ff569f 289 smuPeripheralCAN0 = _SMU_PPUPATD0_CAN0_SHIFT, /**< SMU peripheral identifier for CAN0 */
Anna Bridge 160:5571c4ff569f 290 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 160:5571c4ff569f 291 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 160:5571c4ff569f 292 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 160:5571c4ff569f 293 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
Anna Bridge 160:5571c4ff569f 294 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 160:5571c4ff569f 295 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 160:5571c4ff569f 296 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 160:5571c4ff569f 297 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 160:5571c4ff569f 298 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 160:5571c4ff569f 299 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 160:5571c4ff569f 300 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
Anna Bridge 160:5571c4ff569f 301 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MAC */
Anna Bridge 160:5571c4ff569f 302 #if defined(_SMU_PPUPATD0_LCD_SHIFT)
Anna Bridge 160:5571c4ff569f 303 smuPeripheralLCD = _SMU_PPUPATD0_LCD_SHIFT, /**< SMU peripheral identifier for LCD */
Anna Bridge 160:5571c4ff569f 304 #endif
Anna Bridge 160:5571c4ff569f 305 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 160:5571c4ff569f 306 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 160:5571c4ff569f 307 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 160:5571c4ff569f 308 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 160:5571c4ff569f 309 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 160:5571c4ff569f 310 smuPeripheralRMU = _SMU_PPUPATD0_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 160:5571c4ff569f 311 smuPeripheralRTCC = _SMU_PPUPATD0_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 160:5571c4ff569f 312 smuPeripheralSMU = _SMU_PPUPATD0_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 160:5571c4ff569f 313 smuPeripheralTIMER0 = _SMU_PPUPATD0_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 160:5571c4ff569f 314 smuPeripheralTIMER1 = _SMU_PPUPATD0_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 160:5571c4ff569f 315 smuPeripheralTRNG0 = _SMU_PPUPATD0_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 160:5571c4ff569f 316 smuPeripheralUART0 = _SMU_PPUPATD0_UART0_SHIFT, /**< SMU peripheral identifier for UART0 */
Anna Bridge 160:5571c4ff569f 317 smuPeripheralUSART0 = _SMU_PPUPATD0_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 160:5571c4ff569f 318 smuPeripheralUSART1 = _SMU_PPUPATD0_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 160:5571c4ff569f 319 smuPeripheralUSART2 = _SMU_PPUPATD0_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
Anna Bridge 160:5571c4ff569f 320 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
Anna Bridge 160:5571c4ff569f 321 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 160:5571c4ff569f 322 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 160:5571c4ff569f 323 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
Anna Bridge 160:5571c4ff569f 324
Anna Bridge 142:4eea097334d6 325 #else
Anna Bridge 142:4eea097334d6 326 #error "No peripherals defined for SMU for this device configuration."
Anna Bridge 142:4eea097334d6 327 #endif
Anna Bridge 142:4eea097334d6 328 smuPeripheralEnd
Anna Bridge 142:4eea097334d6 329 } SMU_Peripheral_TypeDef;
Anna Bridge 142:4eea097334d6 330
Anna Bridge 142:4eea097334d6 331 /** SMU peripheral privileged access enablers. */
Anna Bridge 142:4eea097334d6 332 typedef struct {
Anna Bridge 142:4eea097334d6 333 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
Anna Bridge 142:4eea097334d6 334 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
Anna Bridge 142:4eea097334d6 335 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
Anna Bridge 142:4eea097334d6 336 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
Anna Bridge 142:4eea097334d6 337 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 338 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 339 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
Anna Bridge 142:4eea097334d6 340 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 341 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
Anna Bridge 142:4eea097334d6 342 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
Anna Bridge 142:4eea097334d6 343 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */
Anna Bridge 142:4eea097334d6 344 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
Anna Bridge 142:4eea097334d6 345 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
Anna Bridge 142:4eea097334d6 346 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
Anna Bridge 142:4eea097334d6 347 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
Anna Bridge 142:4eea097334d6 348 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
Anna Bridge 142:4eea097334d6 349 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 350 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
Anna Bridge 142:4eea097334d6 351 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
Anna Bridge 142:4eea097334d6 352 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
Anna Bridge 142:4eea097334d6 353 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
Anna Bridge 142:4eea097334d6 354 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
Anna Bridge 142:4eea097334d6 355 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
Anna Bridge 142:4eea097334d6 356 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
Anna Bridge 142:4eea097334d6 357 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
Anna Bridge 142:4eea097334d6 358 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
Anna Bridge 142:4eea097334d6 359 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
Anna Bridge 142:4eea097334d6 360 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 361 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
Anna Bridge 142:4eea097334d6 362 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
Anna Bridge 142:4eea097334d6 363 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
Anna Bridge 142:4eea097334d6 364 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 365 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 366 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 367 bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
Anna Bridge 142:4eea097334d6 368 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
Anna Bridge 142:4eea097334d6 369 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
Anna Bridge 142:4eea097334d6 370 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 371 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
Anna Bridge 142:4eea097334d6 372 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
Anna Bridge 142:4eea097334d6 373 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
Anna Bridge 142:4eea097334d6 374 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
Anna Bridge 142:4eea097334d6 375 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
Anna Bridge 142:4eea097334d6 376 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
Anna Bridge 142:4eea097334d6 377 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
Anna Bridge 142:4eea097334d6 378 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
Anna Bridge 142:4eea097334d6 379 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
Anna Bridge 142:4eea097334d6 380 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
Anna Bridge 142:4eea097334d6 381 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
Anna Bridge 142:4eea097334d6 382
Anna Bridge 142:4eea097334d6 383 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
Anna Bridge 142:4eea097334d6 384 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
Anna Bridge 142:4eea097334d6 385 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
Anna Bridge 142:4eea097334d6 386 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
Anna Bridge 142:4eea097334d6 387 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 388 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 389 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
Anna Bridge 142:4eea097334d6 390 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 391 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
Anna Bridge 142:4eea097334d6 392 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
Anna Bridge 142:4eea097334d6 393 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */
Anna Bridge 142:4eea097334d6 394 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
Anna Bridge 142:4eea097334d6 395 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
Anna Bridge 142:4eea097334d6 396 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
Anna Bridge 142:4eea097334d6 397 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
Anna Bridge 142:4eea097334d6 398 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
Anna Bridge 142:4eea097334d6 399 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 400 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
Anna Bridge 142:4eea097334d6 401 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
Anna Bridge 142:4eea097334d6 402 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
Anna Bridge 142:4eea097334d6 403 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
Anna Bridge 142:4eea097334d6 404 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
Anna Bridge 142:4eea097334d6 405 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
Anna Bridge 142:4eea097334d6 406 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
Anna Bridge 142:4eea097334d6 407 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
Anna Bridge 142:4eea097334d6 408 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
Anna Bridge 142:4eea097334d6 409 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
Anna Bridge 142:4eea097334d6 410 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 411 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
Anna Bridge 142:4eea097334d6 412 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 413 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 414 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 415 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 416 bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
Anna Bridge 142:4eea097334d6 417 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
Anna Bridge 142:4eea097334d6 418 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
Anna Bridge 142:4eea097334d6 419 bool privilegedReserved9 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 420 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
Anna Bridge 142:4eea097334d6 421 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
Anna Bridge 142:4eea097334d6 422 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
Anna Bridge 142:4eea097334d6 423 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
Anna Bridge 142:4eea097334d6 424 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
Anna Bridge 142:4eea097334d6 425 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
Anna Bridge 142:4eea097334d6 426 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
Anna Bridge 142:4eea097334d6 427 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
Anna Bridge 142:4eea097334d6 428 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
Anna Bridge 142:4eea097334d6 429
Anna Bridge 160:5571c4ff569f 430 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_95)
Anna Bridge 160:5571c4ff569f 431 bool privilegedACMP0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 432 bool privilegedACMP1 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 433 bool privilegedADC0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 434 bool privilegedReserved0 : 1;
Anna Bridge 160:5571c4ff569f 435 bool privilegedReserved1 : 1;
Anna Bridge 160:5571c4ff569f 436 bool privilegedCMU : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 437 bool privilegedReserved2 : 1;
Anna Bridge 160:5571c4ff569f 438 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 439 bool privilegedCRYPTO : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 440 bool privilegedVDAC0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 441 bool privilegedPRS : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 442 bool privilegedEMU : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 443 bool privilegedFPUEH : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 444 bool privilegedReserved3 : 1;
Anna Bridge 160:5571c4ff569f 445 bool privilegedGPCRC : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 446 bool privilegedGPIO : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 447 bool privilegedI2C0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 448 bool privilegedIDAC0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 449 bool privilegedMSC : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 450 bool privilegedLDMA : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 451 bool privilegedLESENSE : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 452 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 453 bool privilegedLEUART : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 454 bool privilegedReserved4 : 1;
Anna Bridge 160:5571c4ff569f 455 bool privilegedPCNT0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 456 bool privilegedReserved5 : 1;
Anna Bridge 160:5571c4ff569f 457 bool privilegedReserved6 : 1;
Anna Bridge 160:5571c4ff569f 458 bool privilegedReserved7 : 1;
Anna Bridge 160:5571c4ff569f 459 bool privilegedReserved8 : 1;
Anna Bridge 160:5571c4ff569f 460 bool privilegedRMU : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 461 bool privilegedRTCC : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 462 bool privilegedSMU : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 463
Anna Bridge 160:5571c4ff569f 464 bool privilegedReserved9 : 1;
Anna Bridge 160:5571c4ff569f 465 bool privilegedTIMER0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 466 bool privilegedTIMER1 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 467 bool privilegedTRNG0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 468 bool privilegedUSART0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 469 bool privilegedUSART1 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 470 bool privilegedWDOG0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 471 bool privilegedWDOG1 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 472 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for */
Anna Bridge 160:5571c4ff569f 473
Anna Bridge 160:5571c4ff569f 474 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_100)
Anna Bridge 160:5571c4ff569f 475 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
Anna Bridge 160:5571c4ff569f 476 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
Anna Bridge 160:5571c4ff569f 477 bool privilegedACMP2 : 1; /**< Privileged access enabler for ACMP2 */
Anna Bridge 160:5571c4ff569f 478 bool privilegedACMP3 : 1; /**< Privileged access enabler for ACMP3 */
Anna Bridge 160:5571c4ff569f 479 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
Anna Bridge 160:5571c4ff569f 480 bool privilegedADC1 : 1; /**< Privileged access enabler for ADC1 */
Anna Bridge 160:5571c4ff569f 481 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
Anna Bridge 160:5571c4ff569f 482 bool privilegedCAN1 : 1; /**< Privileged access enabler for CAN1 */
Anna Bridge 160:5571c4ff569f 483 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
Anna Bridge 160:5571c4ff569f 484 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
Anna Bridge 160:5571c4ff569f 485 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
Anna Bridge 160:5571c4ff569f 486 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
Anna Bridge 160:5571c4ff569f 487 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
Anna Bridge 160:5571c4ff569f 488 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
Anna Bridge 160:5571c4ff569f 489 bool privilegedEBI : 1; /**< Privileged access enabler for EBI */
Anna Bridge 160:5571c4ff569f 490 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
Anna Bridge 160:5571c4ff569f 491 bool privilegedETH : 1; /**< Privileged access enabler for ETH */
Anna Bridge 160:5571c4ff569f 492 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
Anna Bridge 160:5571c4ff569f 493 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
Anna Bridge 160:5571c4ff569f 494 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
Anna Bridge 160:5571c4ff569f 495 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
Anna Bridge 160:5571c4ff569f 496 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
Anna Bridge 160:5571c4ff569f 497 bool privilegedI2C2 : 1; /**< Privileged access enabler for I2C2 */
Anna Bridge 160:5571c4ff569f 498 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
Anna Bridge 160:5571c4ff569f 499 bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
Anna Bridge 160:5571c4ff569f 500 bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
Anna Bridge 160:5571c4ff569f 501 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
Anna Bridge 160:5571c4ff569f 502 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
Anna Bridge 160:5571c4ff569f 503 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
Anna Bridge 160:5571c4ff569f 504 bool privilegedLETIMER1 : 1; /**< Privileged access enabler for LETIMER1 */
Anna Bridge 160:5571c4ff569f 505 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
Anna Bridge 160:5571c4ff569f 506 bool privilegedLEUART1 : 1; /**< Privileged access enabler for LEUART1 */
Anna Bridge 160:5571c4ff569f 507 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
Anna Bridge 160:5571c4ff569f 508 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
Anna Bridge 160:5571c4ff569f 509 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
Anna Bridge 160:5571c4ff569f 510 bool privilegedQSPI0 : 1; /**< Privileged access enabler for QSPI0 */
Anna Bridge 160:5571c4ff569f 511 bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
Anna Bridge 160:5571c4ff569f 512 bool privilegedRTC : 1; /**< Privileged access enabler for RTC */
Anna Bridge 160:5571c4ff569f 513 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
Anna Bridge 160:5571c4ff569f 514 bool privilegedSDIO : 1; /**< Privileged access enabler for SDIO */
Anna Bridge 160:5571c4ff569f 515 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
Anna Bridge 160:5571c4ff569f 516 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
Anna Bridge 160:5571c4ff569f 517 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
Anna Bridge 160:5571c4ff569f 518 bool privilegedTIMER2 : 1; /**< Privileged access enabler for TIMER2 */
Anna Bridge 160:5571c4ff569f 519 bool privilegedTIMER3 : 1; /**< Privileged access enabler for TIMER3 */
Anna Bridge 160:5571c4ff569f 520 bool privilegedTIMER4 : 1; /**< Privileged access enabler for TIMER4 */
Anna Bridge 160:5571c4ff569f 521 bool privilegedTIMER5 : 1; /**< Privileged access enabler for TIMER5 */
Anna Bridge 160:5571c4ff569f 522 bool privilegedTIMER6 : 1; /**< Privileged access enabler for TIMER6 */
Anna Bridge 160:5571c4ff569f 523 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
Anna Bridge 160:5571c4ff569f 524 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
Anna Bridge 160:5571c4ff569f 525 bool privilegedUART1 : 1; /**< Privileged access enabler for UART1 */
Anna Bridge 160:5571c4ff569f 526 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
Anna Bridge 160:5571c4ff569f 527 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
Anna Bridge 160:5571c4ff569f 528 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
Anna Bridge 160:5571c4ff569f 529 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
Anna Bridge 160:5571c4ff569f 530 bool privilegedUSART4 : 1; /**< Privileged access enabler for USART4 */
Anna Bridge 160:5571c4ff569f 531 bool privilegedUSART5 : 1; /**< Privileged access enabler for USART5 */
Anna Bridge 160:5571c4ff569f 532 bool privilegedUSB : 1; /**< Privileged access enabler for USB */
Anna Bridge 160:5571c4ff569f 533 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
Anna Bridge 160:5571c4ff569f 534 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
Anna Bridge 160:5571c4ff569f 535 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
Anna Bridge 160:5571c4ff569f 536 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
Anna Bridge 160:5571c4ff569f 537 bool privilegedWTIMER2 : 1; /**< Privileged access enabler for WTIMER2 */
Anna Bridge 160:5571c4ff569f 538 bool privilegedWTIMER3 : 1; /**< Privileged access enabler for WTIMER3 */
Anna Bridge 160:5571c4ff569f 539
Anna Bridge 160:5571c4ff569f 540 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_103)
Anna Bridge 160:5571c4ff569f 541 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
Anna Bridge 160:5571c4ff569f 542 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
Anna Bridge 160:5571c4ff569f 543 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
Anna Bridge 160:5571c4ff569f 544 bool privilegedCAN0 : 1; /**< Privileged access enabler for CAN0 */
Anna Bridge 160:5571c4ff569f 545 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
Anna Bridge 160:5571c4ff569f 546 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
Anna Bridge 160:5571c4ff569f 547 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
Anna Bridge 160:5571c4ff569f 548 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
Anna Bridge 160:5571c4ff569f 549 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
Anna Bridge 160:5571c4ff569f 550 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
Anna Bridge 160:5571c4ff569f 551 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
Anna Bridge 160:5571c4ff569f 552 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
Anna Bridge 160:5571c4ff569f 553 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
Anna Bridge 160:5571c4ff569f 554 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
Anna Bridge 160:5571c4ff569f 555 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
Anna Bridge 160:5571c4ff569f 556 bool privilegedMSC : 1; /**< Privileged access enabler for MAC */
Anna Bridge 160:5571c4ff569f 557 bool privilegedLCD : 1; /**< Privileged access enabler for LCD */
Anna Bridge 160:5571c4ff569f 558 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
Anna Bridge 160:5571c4ff569f 559 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
Anna Bridge 160:5571c4ff569f 560 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
Anna Bridge 160:5571c4ff569f 561 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
Anna Bridge 160:5571c4ff569f 562 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
Anna Bridge 160:5571c4ff569f 563 bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
Anna Bridge 160:5571c4ff569f 564 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
Anna Bridge 160:5571c4ff569f 565 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
Anna Bridge 160:5571c4ff569f 566 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
Anna Bridge 160:5571c4ff569f 567 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
Anna Bridge 160:5571c4ff569f 568 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
Anna Bridge 160:5571c4ff569f 569 bool privilegedUART0 : 1; /**< Privileged access enabler for UART0 */
Anna Bridge 160:5571c4ff569f 570 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
Anna Bridge 160:5571c4ff569f 571 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
Anna Bridge 160:5571c4ff569f 572 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
Anna Bridge 160:5571c4ff569f 573 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
Anna Bridge 160:5571c4ff569f 574 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
Anna Bridge 160:5571c4ff569f 575 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
Anna Bridge 160:5571c4ff569f 576 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
Anna Bridge 160:5571c4ff569f 577
Anna Bridge 142:4eea097334d6 578 #else
Anna Bridge 142:4eea097334d6 579 #error "No peripherals defined for SMU for this device configuration"
Anna Bridge 142:4eea097334d6 580 #endif
Anna Bridge 142:4eea097334d6 581 } SMU_PrivilegedAccess_TypeDef;
Anna Bridge 142:4eea097334d6 582
Anna Bridge 142:4eea097334d6 583 /*******************************************************************************
Anna Bridge 142:4eea097334d6 584 ****************************** STRUCTS ************************************
Anna Bridge 142:4eea097334d6 585 ******************************************************************************/
Anna Bridge 142:4eea097334d6 586
Anna Bridge 142:4eea097334d6 587 /** SMU initialization structure. */
Anna Bridge 142:4eea097334d6 588 typedef struct {
Anna Bridge 142:4eea097334d6 589 union {
Anna Bridge 142:4eea097334d6 590 uint32_t reg[2]; /**< Periperal access control array.*/
Anna Bridge 142:4eea097334d6 591 SMU_PrivilegedAccess_TypeDef access; /**< Periperal access control array.*/
Anna Bridge 142:4eea097334d6 592 } ppu;
Anna Bridge 142:4eea097334d6 593 bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/
Anna Bridge 142:4eea097334d6 594 } SMU_Init_TypeDef;
Anna Bridge 142:4eea097334d6 595
Anna Bridge 142:4eea097334d6 596 /** Default SMU initialization struct settings. */
Anna Bridge 160:5571c4ff569f 597 #define SMU_INIT_DEFAULT { \
Anna Bridge 160:5571c4ff569f 598 { { 0 } }, /* No peripherals acsess protected. */ \
Anna Bridge 160:5571c4ff569f 599 true /* Enable SMU.*/ \
Anna Bridge 142:4eea097334d6 600 }
Anna Bridge 142:4eea097334d6 601
Anna Bridge 142:4eea097334d6 602 /*******************************************************************************
Anna Bridge 142:4eea097334d6 603 ***************************** PROTOTYPES **********************************
Anna Bridge 142:4eea097334d6 604 ******************************************************************************/
Anna Bridge 142:4eea097334d6 605
Anna Bridge 142:4eea097334d6 606 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 607 * @brief
Anna Bridge 142:4eea097334d6 608 * Enable or disable the Peripheral Protection Unit of the SMU.
Anna Bridge 142:4eea097334d6 609 *
Anna Bridge 142:4eea097334d6 610 * @param[in] enable
Anna Bridge 142:4eea097334d6 611 * True if the PPU should be enabled, false if it should be disabled.
Anna Bridge 142:4eea097334d6 612 ******************************************************************************/
Anna Bridge 142:4eea097334d6 613 __STATIC_INLINE void SMU_EnablePPU(bool enable)
Anna Bridge 142:4eea097334d6 614 {
Anna Bridge 142:4eea097334d6 615 BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable);
Anna Bridge 142:4eea097334d6 616 }
Anna Bridge 142:4eea097334d6 617
Anna Bridge 142:4eea097334d6 618 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 619 * @brief
Anna Bridge 142:4eea097334d6 620 * Initialize the Peripheral Protection Unit of the SMU.
Anna Bridge 142:4eea097334d6 621 *
Anna Bridge 142:4eea097334d6 622 * @param[in] init
Anna Bridge 142:4eea097334d6 623 * Pointer to initialization struct defining which peripherals should only
Anna Bridge 142:4eea097334d6 624 * be accessed from privileged mode, and whether the PPU should be enabled.
Anna Bridge 142:4eea097334d6 625 ******************************************************************************/
Anna Bridge 142:4eea097334d6 626 __STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
Anna Bridge 142:4eea097334d6 627 {
Anna Bridge 142:4eea097334d6 628 SMU->PPUPATD0 = init->ppu.reg[0];
Anna Bridge 142:4eea097334d6 629 SMU->PPUPATD1 = init->ppu.reg[1];
Anna Bridge 142:4eea097334d6 630
Anna Bridge 142:4eea097334d6 631 SMU_EnablePPU(init->enable);
Anna Bridge 142:4eea097334d6 632 }
Anna Bridge 142:4eea097334d6 633
Anna Bridge 142:4eea097334d6 634 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 635 * @brief
Anna Bridge 142:4eea097334d6 636 * Change the access settings for a peripheral
Anna Bridge 142:4eea097334d6 637 *
Anna Bridge 142:4eea097334d6 638 * @details
Anna Bridge 142:4eea097334d6 639 * Set whether the peripheral can only be accessed from privileged mode
Anna Bridge 142:4eea097334d6 640 *
Anna Bridge 142:4eea097334d6 641 * @param[in] peripheral
Anna Bridge 142:4eea097334d6 642 * ID of the peripheral to change access settings for
Anna Bridge 142:4eea097334d6 643 *
Anna Bridge 142:4eea097334d6 644 * @param[in] privileged
Anna Bridge 142:4eea097334d6 645 * True if the peripheral should only be allowed to be accessed from
Anna Bridge 142:4eea097334d6 646 * privileged mode, false if the peripheral can be accessed from unprivileged
Anna Bridge 142:4eea097334d6 647 * mode.
Anna Bridge 142:4eea097334d6 648 ******************************************************************************/
Anna Bridge 142:4eea097334d6 649 __STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,
Anna Bridge 142:4eea097334d6 650 bool privileged)
Anna Bridge 142:4eea097334d6 651 {
Anna Bridge 142:4eea097334d6 652 EFM_ASSERT(peripheral < smuPeripheralEnd);
Anna Bridge 142:4eea097334d6 653
Anna Bridge 142:4eea097334d6 654 if (peripheral < 32) {
Anna Bridge 142:4eea097334d6 655 BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged);
Anna Bridge 142:4eea097334d6 656 } else {
Anna Bridge 142:4eea097334d6 657 BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged);
Anna Bridge 142:4eea097334d6 658 }
Anna Bridge 142:4eea097334d6 659 }
Anna Bridge 142:4eea097334d6 660
Anna Bridge 142:4eea097334d6 661 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 662 * @brief
Anna Bridge 142:4eea097334d6 663 * Get the ID of the peripheral that caused an access fault.
Anna Bridge 142:4eea097334d6 664 *
Anna Bridge 142:4eea097334d6 665 * @note
Anna Bridge 142:4eea097334d6 666 * The return value is only valid if the @ref SMU_IF_PPUPRIV interrupt flag
Anna Bridge 142:4eea097334d6 667 * is set.
Anna Bridge 142:4eea097334d6 668 *
Anna Bridge 142:4eea097334d6 669 * @return
Anna Bridge 142:4eea097334d6 670 * ID of the faulting peripheral.
Anna Bridge 142:4eea097334d6 671 ******************************************************************************/
Anna Bridge 142:4eea097334d6 672 __STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
Anna Bridge 142:4eea097334d6 673 {
Anna Bridge 142:4eea097334d6 674 return (SMU_Peripheral_TypeDef)SMU->PPUFS;
Anna Bridge 142:4eea097334d6 675 }
Anna Bridge 142:4eea097334d6 676
Anna Bridge 142:4eea097334d6 677 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 678 * @brief
Anna Bridge 142:4eea097334d6 679 * Clear one or more pending SMU interrupts.
Anna Bridge 142:4eea097334d6 680 *
Anna Bridge 142:4eea097334d6 681 * @param[in] flags
Anna Bridge 142:4eea097334d6 682 * Bitwise logic OR of SMU interrupt sources to clear.
Anna Bridge 142:4eea097334d6 683 ******************************************************************************/
Anna Bridge 142:4eea097334d6 684 __STATIC_INLINE void SMU_IntClear(uint32_t flags)
Anna Bridge 142:4eea097334d6 685 {
Anna Bridge 142:4eea097334d6 686 SMU->IFC = flags;
Anna Bridge 142:4eea097334d6 687 }
Anna Bridge 142:4eea097334d6 688
Anna Bridge 142:4eea097334d6 689 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 690 * @brief
Anna Bridge 142:4eea097334d6 691 * Disable one or more SMU interrupts.
Anna Bridge 142:4eea097334d6 692 *
Anna Bridge 142:4eea097334d6 693 * @param[in] flags
Anna Bridge 142:4eea097334d6 694 * SMU interrupt sources to disable.
Anna Bridge 142:4eea097334d6 695 ******************************************************************************/
Anna Bridge 142:4eea097334d6 696 __STATIC_INLINE void SMU_IntDisable(uint32_t flags)
Anna Bridge 142:4eea097334d6 697 {
Anna Bridge 142:4eea097334d6 698 SMU->IEN &= ~flags;
Anna Bridge 142:4eea097334d6 699 }
Anna Bridge 142:4eea097334d6 700
Anna Bridge 142:4eea097334d6 701 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 702 * @brief
Anna Bridge 142:4eea097334d6 703 * Enable one or more SMU interrupts.
Anna Bridge 142:4eea097334d6 704 *
Anna Bridge 142:4eea097334d6 705 * @note
Anna Bridge 142:4eea097334d6 706 * Depending on the use, a pending interrupt may already be set prior to
Anna Bridge 142:4eea097334d6 707 * enabling the interrupt. Consider using SMU_IntClear() prior to enabling
Anna Bridge 142:4eea097334d6 708 * if such a pending interrupt should be ignored.
Anna Bridge 142:4eea097334d6 709 *
Anna Bridge 142:4eea097334d6 710 * @param[in] flags
Anna Bridge 142:4eea097334d6 711 * SMU interrupt sources to enable.
Anna Bridge 142:4eea097334d6 712 ******************************************************************************/
Anna Bridge 142:4eea097334d6 713 __STATIC_INLINE void SMU_IntEnable(uint32_t flags)
Anna Bridge 142:4eea097334d6 714 {
Anna Bridge 142:4eea097334d6 715 SMU->IEN |= flags;
Anna Bridge 142:4eea097334d6 716 }
Anna Bridge 142:4eea097334d6 717
Anna Bridge 142:4eea097334d6 718 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 719 * @brief
Anna Bridge 142:4eea097334d6 720 * Get pending SMU interrupts.
Anna Bridge 142:4eea097334d6 721 *
Anna Bridge 142:4eea097334d6 722 * @return
Anna Bridge 142:4eea097334d6 723 * SMU interrupt sources pending.
Anna Bridge 142:4eea097334d6 724 ******************************************************************************/
Anna Bridge 142:4eea097334d6 725 __STATIC_INLINE uint32_t SMU_IntGet(void)
Anna Bridge 142:4eea097334d6 726 {
Anna Bridge 142:4eea097334d6 727 return SMU->IF;
Anna Bridge 142:4eea097334d6 728 }
Anna Bridge 142:4eea097334d6 729
Anna Bridge 142:4eea097334d6 730 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 731 * @brief
Anna Bridge 142:4eea097334d6 732 * Get enabled and pending SMU interrupt flags.
Anna Bridge 142:4eea097334d6 733 * Useful for handling more interrupt sources in the same interrupt handler.
Anna Bridge 142:4eea097334d6 734 *
Anna Bridge 142:4eea097334d6 735 * @note
Anna Bridge 142:4eea097334d6 736 * Interrupt flags are not cleared by the use of this function.
Anna Bridge 142:4eea097334d6 737 *
Anna Bridge 142:4eea097334d6 738 * @return
Anna Bridge 142:4eea097334d6 739 * Pending and enabled SMU interrupt sources.
Anna Bridge 142:4eea097334d6 740 * The return value is the bitwise AND combination of
Anna Bridge 142:4eea097334d6 741 * - the OR combination of enabled interrupt sources in SMU_IEN register
Anna Bridge 142:4eea097334d6 742 * and
Anna Bridge 142:4eea097334d6 743 * - the OR combination of valid interrupt flags in SMU_IF register.
Anna Bridge 142:4eea097334d6 744 ******************************************************************************/
Anna Bridge 142:4eea097334d6 745 __STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
Anna Bridge 142:4eea097334d6 746 {
Anna Bridge 142:4eea097334d6 747 uint32_t tmp;
Anna Bridge 142:4eea097334d6 748
Anna Bridge 142:4eea097334d6 749 // Store SMU->IEN in temporary variable in order to define explicit order
Anna Bridge 142:4eea097334d6 750 // of volatile accesses.
Anna Bridge 142:4eea097334d6 751 tmp = SMU->IEN;
Anna Bridge 142:4eea097334d6 752
Anna Bridge 142:4eea097334d6 753 // Bitwise AND of pending and enabled interrupts
Anna Bridge 142:4eea097334d6 754 return SMU->IF & tmp;
Anna Bridge 142:4eea097334d6 755 }
Anna Bridge 142:4eea097334d6 756
Anna Bridge 142:4eea097334d6 757 /************************************************************************Æ**//**
Anna Bridge 142:4eea097334d6 758 * @brief
Anna Bridge 142:4eea097334d6 759 * Set one or more pending SMU interrupts from SW.
Anna Bridge 142:4eea097334d6 760 *
Anna Bridge 142:4eea097334d6 761 * @param[in] flags
Anna Bridge 142:4eea097334d6 762 * SMU interrupt sources to set to pending.
Anna Bridge 142:4eea097334d6 763 *************************************************************************Æ****/
Anna Bridge 142:4eea097334d6 764 __STATIC_INLINE void SMU_IntSet(uint32_t flags)
Anna Bridge 142:4eea097334d6 765 {
Anna Bridge 142:4eea097334d6 766 SMU->IFS = flags;
Anna Bridge 142:4eea097334d6 767 }
Anna Bridge 142:4eea097334d6 768
Anna Bridge 142:4eea097334d6 769 /** @} (end addtogroup SMU) */
Anna Bridge 142:4eea097334d6 770 /** @} (end addtogroup emlib) */
Anna Bridge 142:4eea097334d6 771
Anna Bridge 142:4eea097334d6 772 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 773 }
Anna Bridge 142:4eea097334d6 774 #endif
Anna Bridge 142:4eea097334d6 775
Anna Bridge 142:4eea097334d6 776 #endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
Anna Bridge 142:4eea097334d6 777 #endif // EM_SMU_H