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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_smu.h@142:4eea097334d6, 2017-05-10 (annotated)

Committer:
Anna Bridge
Date:
Wed May 10 11:31:27 2017 +0100
Revision:
142:4eea097334d6
Child:
159:7130f322cb7e
Release 142 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



4059: [Silicon Labs] Rename targets https://github.com/ARMmbed/mbed-os/pull/4059

4187: [NCS36510] Reduce default heap size allocated by IAR to 1/4 of RAM https://github.com/ARMmbed/mbed-os/pull/4187

4225: fixed missing device_name for xDot and removed progen https://github.com/ARMmbed/mbed-os/pull/4225

4251: Fix C++11 build error w/ u-blox EVK-ODIN-W2 https://github.com/ARMmbed/mbed-os/pull/4251

4236: STM32 Fixed warning related to __packed redefinition https://github.com/ARMmbed/mbed-os/pull/4236

4190: LPC4088: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/4190

4260: Inherit Xadow M0 target from LPC11U35_501 https://github.com/ARMmbed/mbed-os/pull/4260

4249: Add consistent button names across targets https://github.com/ARMmbed/mbed-os/pull/4249

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file em_smu.h
Anna Bridge 142:4eea097334d6 3 * @brief Security Management Unit (SMU) peripheral API
Anna Bridge 142:4eea097334d6 4 * @version 5.1.2
Anna Bridge 142:4eea097334d6 5 *******************************************************************************
Anna Bridge 142:4eea097334d6 6 * @section License
Anna Bridge 142:4eea097334d6 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 8 *******************************************************************************
Anna Bridge 142:4eea097334d6 9 *
Anna Bridge 142:4eea097334d6 10 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 11 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 12 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 13 *
Anna Bridge 142:4eea097334d6 14 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 15 * claim that you wrote the original software.
Anna Bridge 142:4eea097334d6 16 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 17 * misrepresented as being the original software.
Anna Bridge 142:4eea097334d6 18 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 19 *
Anna Bridge 142:4eea097334d6 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
Anna Bridge 142:4eea097334d6 21 * obligation to support this Software. Silicon Labs is providing the
Anna Bridge 142:4eea097334d6 22 * Software "AS IS", with no express or implied warranties of any kind,
Anna Bridge 142:4eea097334d6 23 * including, but not limited to, any implied warranties of merchantability
Anna Bridge 142:4eea097334d6 24 * or fitness for any particular purpose or warranties against infringement
Anna Bridge 142:4eea097334d6 25 * of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 26 *
Anna Bridge 142:4eea097334d6 27 * Silicon Labs will not be liable for any consequential, incidental, or
Anna Bridge 142:4eea097334d6 28 * special damages, or any other relief, or for any claim by any third party,
Anna Bridge 142:4eea097334d6 29 * arising from your use of this Software.
Anna Bridge 142:4eea097334d6 30 *
Anna Bridge 142:4eea097334d6 31 ******************************************************************************/
Anna Bridge 142:4eea097334d6 32
Anna Bridge 142:4eea097334d6 33 #ifndef EM_SMU_H
Anna Bridge 142:4eea097334d6 34 #define EM_SMU_H
Anna Bridge 142:4eea097334d6 35
Anna Bridge 142:4eea097334d6 36 #include "em_device.h"
Anna Bridge 142:4eea097334d6 37 #if defined(SMU_COUNT) && (SMU_COUNT > 0)
Anna Bridge 142:4eea097334d6 38
Anna Bridge 142:4eea097334d6 39 #include "em_assert.h"
Anna Bridge 142:4eea097334d6 40 #include "em_bus.h"
Anna Bridge 142:4eea097334d6 41
Anna Bridge 142:4eea097334d6 42 #include <stdint.h>
Anna Bridge 142:4eea097334d6 43 #include <stdbool.h>
Anna Bridge 142:4eea097334d6 44
Anna Bridge 142:4eea097334d6 45 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 46 extern "C" {
Anna Bridge 142:4eea097334d6 47 #endif
Anna Bridge 142:4eea097334d6 48
Anna Bridge 142:4eea097334d6 49 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 50 * @addtogroup emlib
Anna Bridge 142:4eea097334d6 51 * @{
Anna Bridge 142:4eea097334d6 52 ******************************************************************************/
Anna Bridge 142:4eea097334d6 53
Anna Bridge 142:4eea097334d6 54 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 55 * @addtogroup SMU
Anna Bridge 142:4eea097334d6 56 * @brief Security Management Unit (SMU) Peripheral API
Anna Bridge 142:4eea097334d6 57 *
Anna Bridge 142:4eea097334d6 58 * @details
Anna Bridge 142:4eea097334d6 59 * The Security Management Unit (SMU) forms the control and status/reporting
Anna Bridge 142:4eea097334d6 60 * component of bus-level security in EFM32/EFR32 devices.
Anna Bridge 142:4eea097334d6 61 *
Anna Bridge 142:4eea097334d6 62 * Peripheral-level protection is provided via the peripheral protection unit
Anna Bridge 142:4eea097334d6 63 * (PPU). The PPU provides a hardware access barrier to any peripheral that is
Anna Bridge 142:4eea097334d6 64 * configured to be protected. When an attempt is made to access a peripheral
Anna Bridge 142:4eea097334d6 65 * without the required privilege/security level, the PPU detects the fault
Anna Bridge 142:4eea097334d6 66 * and intercepts the access. No write or read of the peripheral register
Anna Bridge 142:4eea097334d6 67 * space occurs, and an all-zero value is returned if the access is a read.
Anna Bridge 142:4eea097334d6 68 *
Anna Bridge 142:4eea097334d6 69 * @subsection Usage example
Anna Bridge 142:4eea097334d6 70 * @include em_smu_init.c
Anna Bridge 142:4eea097334d6 71 * @{
Anna Bridge 142:4eea097334d6 72 ******************************************************************************/
Anna Bridge 142:4eea097334d6 73
Anna Bridge 142:4eea097334d6 74 /*******************************************************************************
Anna Bridge 142:4eea097334d6 75 ******************************** ENUMS ************************************
Anna Bridge 142:4eea097334d6 76 ******************************************************************************/
Anna Bridge 142:4eea097334d6 77
Anna Bridge 142:4eea097334d6 78 /** SMU peripheral identifiers. */
Anna Bridge 142:4eea097334d6 79 typedef enum {
Anna Bridge 142:4eea097334d6 80
Anna Bridge 142:4eea097334d6 81 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
Anna Bridge 142:4eea097334d6 82 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 142:4eea097334d6 83 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 142:4eea097334d6 84 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 142:4eea097334d6 85 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 142:4eea097334d6 86 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 142:4eea097334d6 87 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 142:4eea097334d6 88 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
Anna Bridge 142:4eea097334d6 89 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
Anna Bridge 142:4eea097334d6 90 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 142:4eea097334d6 91 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 142:4eea097334d6 92 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 142:4eea097334d6 93 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
Anna Bridge 142:4eea097334d6 94 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 142:4eea097334d6 95 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 142:4eea097334d6 96 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 142:4eea097334d6 97 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
Anna Bridge 142:4eea097334d6 98 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
Anna Bridge 142:4eea097334d6 99 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
Anna Bridge 142:4eea097334d6 100 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 142:4eea097334d6 101 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 142:4eea097334d6 102 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 142:4eea097334d6 103 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 142:4eea097334d6 104 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 142:4eea097334d6 105 smuPeripheralPCNT1 = _SMU_PPUPATD0_PCNT1_SHIFT, /**< SMU peripheral identifier for PCNT1 */
Anna Bridge 142:4eea097334d6 106 smuPeripheralPCNT2 = _SMU_PPUPATD0_PCNT2_SHIFT, /**< SMU peripheral identifier for PCNT2 */
Anna Bridge 142:4eea097334d6 107 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 142:4eea097334d6 108 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 142:4eea097334d6 109 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 142:4eea097334d6 110 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 142:4eea097334d6 111 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
Anna Bridge 142:4eea097334d6 112 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 142:4eea097334d6 113 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 142:4eea097334d6 114 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 142:4eea097334d6 115 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
Anna Bridge 142:4eea097334d6 116 smuPeripheralUSART3 = 32 + _SMU_PPUPATD1_USART3_SHIFT, /**< SMU peripheral identifier for USART3 */
Anna Bridge 142:4eea097334d6 117 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 142:4eea097334d6 118 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
Anna Bridge 142:4eea097334d6 119 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 142:4eea097334d6 120 smuPeripheralWTIMER1 = 32 + _SMU_PPUPATD1_WTIMER1_SHIFT, /**< SMU peripheral identifier for WTIMER1 */
Anna Bridge 142:4eea097334d6 121
Anna Bridge 142:4eea097334d6 122 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
Anna Bridge 142:4eea097334d6 123 smuPeripheralACMP0 = _SMU_PPUPATD0_ACMP0_SHIFT, /**< SMU peripheral identifier for ACMP0 */
Anna Bridge 142:4eea097334d6 124 smuPeripheralACMP1 = _SMU_PPUPATD0_ACMP1_SHIFT, /**< SMU peripheral identifier for ACMP1 */
Anna Bridge 142:4eea097334d6 125 smuPeripheralADC0 = _SMU_PPUPATD0_ADC0_SHIFT, /**< SMU peripheral identifier for ADC0 */
Anna Bridge 142:4eea097334d6 126 smuPeripheralCMU = _SMU_PPUPATD0_CMU_SHIFT, /**< SMU peripheral identifier for CMU */
Anna Bridge 142:4eea097334d6 127 smuPeripheralCRYOTIMER = _SMU_PPUPATD0_CRYOTIMER_SHIFT, /**< SMU peripheral identifier for CRYOTIMER */
Anna Bridge 142:4eea097334d6 128 smuPeripheralCRYPTO0 = _SMU_PPUPATD0_CRYPTO0_SHIFT, /**< SMU peripheral identifier for CRYPTO0 */
Anna Bridge 142:4eea097334d6 129 smuPeripheralCRYPTO1 = _SMU_PPUPATD0_CRYPTO1_SHIFT, /**< SMU peripheral identifier for CRYPTO1 */
Anna Bridge 142:4eea097334d6 130 smuPeripheralCSEN = _SMU_PPUPATD0_CSEN_SHIFT, /**< SMU peripheral identifier for CSEN */
Anna Bridge 142:4eea097334d6 131 smuPeripheralVDAC0 = _SMU_PPUPATD0_VDAC0_SHIFT, /**< SMU peripheral identifier for VDAC0 */
Anna Bridge 142:4eea097334d6 132 smuPeripheralPRS = _SMU_PPUPATD0_PRS_SHIFT, /**< SMU peripheral identifier for PRS */
Anna Bridge 142:4eea097334d6 133 smuPeripheralEMU = _SMU_PPUPATD0_EMU_SHIFT, /**< SMU peripheral identifier for EMU */
Anna Bridge 142:4eea097334d6 134 smuPeripheralFPUEH = _SMU_PPUPATD0_FPUEH_SHIFT, /**< SMU peripheral identifier for FPUEH */
Anna Bridge 142:4eea097334d6 135 smuPeripheralGPCRC = _SMU_PPUPATD0_GPCRC_SHIFT, /**< SMU peripheral identifier for GPCRC */
Anna Bridge 142:4eea097334d6 136 smuPeripheralGPIO = _SMU_PPUPATD0_GPIO_SHIFT, /**< SMU peripheral identifier for GPIO */
Anna Bridge 142:4eea097334d6 137 smuPeripheralI2C0 = _SMU_PPUPATD0_I2C0_SHIFT, /**< SMU peripheral identifier for I2C0 */
Anna Bridge 142:4eea097334d6 138 smuPeripheralI2C1 = _SMU_PPUPATD0_I2C1_SHIFT, /**< SMU peripheral identifier for I2C1 */
Anna Bridge 142:4eea097334d6 139 smuPeripheralIDAC0 = _SMU_PPUPATD0_IDAC0_SHIFT, /**< SMU peripheral identifier for IDAC0 */
Anna Bridge 142:4eea097334d6 140 smuPeripheralMSC = _SMU_PPUPATD0_MSC_SHIFT, /**< SMU peripheral identifier for MSC */
Anna Bridge 142:4eea097334d6 141 smuPeripheralLDMA = _SMU_PPUPATD0_LDMA_SHIFT, /**< SMU peripheral identifier for LDMA */
Anna Bridge 142:4eea097334d6 142 smuPeripheralLESENSE = _SMU_PPUPATD0_LESENSE_SHIFT, /**< SMU peripheral identifier for LESENSE */
Anna Bridge 142:4eea097334d6 143 smuPeripheralLETIMER0 = _SMU_PPUPATD0_LETIMER0_SHIFT, /**< SMU peripheral identifier for LETIMER0 */
Anna Bridge 142:4eea097334d6 144 smuPeripheralLEUART0 = _SMU_PPUPATD0_LEUART0_SHIFT, /**< SMU peripheral identifier for LEUART0 */
Anna Bridge 142:4eea097334d6 145 smuPeripheralPCNT0 = _SMU_PPUPATD0_PCNT0_SHIFT, /**< SMU peripheral identifier for PCNT0 */
Anna Bridge 142:4eea097334d6 146 smuPeripheralRMU = 32 + _SMU_PPUPATD1_RMU_SHIFT, /**< SMU peripheral identifier for RMU */
Anna Bridge 142:4eea097334d6 147 smuPeripheralRTCC = 32 + _SMU_PPUPATD1_RTCC_SHIFT, /**< SMU peripheral identifier for RTCC */
Anna Bridge 142:4eea097334d6 148 smuPeripheralSMU = 32 + _SMU_PPUPATD1_SMU_SHIFT, /**< SMU peripheral identifier for SMU */
Anna Bridge 142:4eea097334d6 149 smuPeripheralTIMER0 = 32 + _SMU_PPUPATD1_TIMER0_SHIFT, /**< SMU peripheral identifier for TIMER0 */
Anna Bridge 142:4eea097334d6 150 smuPeripheralTIMER1 = 32 + _SMU_PPUPATD1_TIMER1_SHIFT, /**< SMU peripheral identifier for TIMER1 */
Anna Bridge 142:4eea097334d6 151 smuPeripheralTRNG0 = 32 + _SMU_PPUPATD1_TRNG0_SHIFT, /**< SMU peripheral identifier for TRNG0 */
Anna Bridge 142:4eea097334d6 152 smuPeripheralUSART0 = 32 + _SMU_PPUPATD1_USART0_SHIFT, /**< SMU peripheral identifier for USART0 */
Anna Bridge 142:4eea097334d6 153 smuPeripheralUSART1 = 32 + _SMU_PPUPATD1_USART1_SHIFT, /**< SMU peripheral identifier for USART1 */
Anna Bridge 142:4eea097334d6 154 smuPeripheralUSART2 = 32 + _SMU_PPUPATD1_USART2_SHIFT, /**< SMU peripheral identifier for USART2 */
Anna Bridge 142:4eea097334d6 155 smuPeripheralWDOG0 = 32 + _SMU_PPUPATD1_WDOG0_SHIFT, /**< SMU peripheral identifier for WDOG0 */
Anna Bridge 142:4eea097334d6 156 smuPeripheralWDOG1 = 32 + _SMU_PPUPATD1_WDOG1_SHIFT, /**< SMU peripheral identifier for WDOG1 */
Anna Bridge 142:4eea097334d6 157 smuPeripheralWTIMER0 = 32 + _SMU_PPUPATD1_WTIMER0_SHIFT, /**< SMU peripheral identifier for WTIMER0 */
Anna Bridge 142:4eea097334d6 158
Anna Bridge 142:4eea097334d6 159 #else
Anna Bridge 142:4eea097334d6 160 #error "No peripherals defined for SMU for this device configuration."
Anna Bridge 142:4eea097334d6 161 #endif
Anna Bridge 142:4eea097334d6 162 smuPeripheralEnd
Anna Bridge 142:4eea097334d6 163 } SMU_Peripheral_TypeDef;
Anna Bridge 142:4eea097334d6 164
Anna Bridge 142:4eea097334d6 165 /** SMU peripheral privileged access enablers. */
Anna Bridge 142:4eea097334d6 166 typedef struct {
Anna Bridge 142:4eea097334d6 167
Anna Bridge 142:4eea097334d6 168 #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_84)
Anna Bridge 142:4eea097334d6 169 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
Anna Bridge 142:4eea097334d6 170 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
Anna Bridge 142:4eea097334d6 171 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
Anna Bridge 142:4eea097334d6 172 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 173 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 174 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
Anna Bridge 142:4eea097334d6 175 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 176 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
Anna Bridge 142:4eea097334d6 177 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
Anna Bridge 142:4eea097334d6 178 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */
Anna Bridge 142:4eea097334d6 179 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
Anna Bridge 142:4eea097334d6 180 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
Anna Bridge 142:4eea097334d6 181 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
Anna Bridge 142:4eea097334d6 182 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
Anna Bridge 142:4eea097334d6 183 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
Anna Bridge 142:4eea097334d6 184 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 185 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
Anna Bridge 142:4eea097334d6 186 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
Anna Bridge 142:4eea097334d6 187 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
Anna Bridge 142:4eea097334d6 188 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
Anna Bridge 142:4eea097334d6 189 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
Anna Bridge 142:4eea097334d6 190 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
Anna Bridge 142:4eea097334d6 191 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
Anna Bridge 142:4eea097334d6 192 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
Anna Bridge 142:4eea097334d6 193 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
Anna Bridge 142:4eea097334d6 194 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
Anna Bridge 142:4eea097334d6 195 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 196 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
Anna Bridge 142:4eea097334d6 197 bool privilegedPCNT1 : 1; /**< Privileged access enabler for PCNT1 */
Anna Bridge 142:4eea097334d6 198 bool privilegedPCNT2 : 1; /**< Privileged access enabler for PCNT2 */
Anna Bridge 142:4eea097334d6 199 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 200 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 201 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 202 bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
Anna Bridge 142:4eea097334d6 203 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
Anna Bridge 142:4eea097334d6 204 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
Anna Bridge 142:4eea097334d6 205 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 206 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
Anna Bridge 142:4eea097334d6 207 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
Anna Bridge 142:4eea097334d6 208 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
Anna Bridge 142:4eea097334d6 209 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
Anna Bridge 142:4eea097334d6 210 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
Anna Bridge 142:4eea097334d6 211 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
Anna Bridge 142:4eea097334d6 212 bool privilegedUSART3 : 1; /**< Privileged access enabler for USART3 */
Anna Bridge 142:4eea097334d6 213 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
Anna Bridge 142:4eea097334d6 214 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
Anna Bridge 142:4eea097334d6 215 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
Anna Bridge 142:4eea097334d6 216 bool privilegedWTIMER1 : 1; /**< Privileged access enabler for WTIMER1 */
Anna Bridge 142:4eea097334d6 217
Anna Bridge 142:4eea097334d6 218 #elif defined(_SILICON_LABS_GECKO_INTERNAL_SDID_89)
Anna Bridge 142:4eea097334d6 219 bool privilegedACMP0 : 1; /**< Privileged access enabler for ACMP0 */
Anna Bridge 142:4eea097334d6 220 bool privilegedACMP1 : 1; /**< Privileged access enabler for ACMP1 */
Anna Bridge 142:4eea097334d6 221 bool privilegedADC0 : 1; /**< Privileged access enabler for ADC0 */
Anna Bridge 142:4eea097334d6 222 bool privilegedReserved0 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 223 bool privilegedReserved1 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 224 bool privilegedCMU : 1; /**< Privileged access enabler for CMU */
Anna Bridge 142:4eea097334d6 225 bool privilegedReserved2 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 226 bool privilegedCRYOTIMER : 1; /**< Privileged access enabler for CRYOTIMER */
Anna Bridge 142:4eea097334d6 227 bool privilegedCRYPTO0 : 1; /**< Privileged access enabler for CRYPTO0 */
Anna Bridge 142:4eea097334d6 228 bool privilegedCRYPTO1 : 1; /**< Privileged access enabler for CRYPTO1 */
Anna Bridge 142:4eea097334d6 229 bool privilegedCSEN : 1; /**< Privileged access enabler for CSEN */
Anna Bridge 142:4eea097334d6 230 bool privilegedVDAC0 : 1; /**< Privileged access enabler for VDAC0 */
Anna Bridge 142:4eea097334d6 231 bool privilegedPRS : 1; /**< Privileged access enabler for PRS */
Anna Bridge 142:4eea097334d6 232 bool privilegedEMU : 1; /**< Privileged access enabler for EMU */
Anna Bridge 142:4eea097334d6 233 bool privilegedFPUEH : 1; /**< Privileged access enabler for FPUEH */
Anna Bridge 142:4eea097334d6 234 bool privilegedReserved3 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 235 bool privilegedGPCRC : 1; /**< Privileged access enabler for GPCRC */
Anna Bridge 142:4eea097334d6 236 bool privilegedGPIO : 1; /**< Privileged access enabler for GPIO */
Anna Bridge 142:4eea097334d6 237 bool privilegedI2C0 : 1; /**< Privileged access enabler for I2C0 */
Anna Bridge 142:4eea097334d6 238 bool privilegedI2C1 : 1; /**< Privileged access enabler for I2C1 */
Anna Bridge 142:4eea097334d6 239 bool privilegedIDAC0 : 1; /**< Privileged access enabler for IDAC0 */
Anna Bridge 142:4eea097334d6 240 bool privilegedMSC : 1; /**< Privileged access enabler for MSC */
Anna Bridge 142:4eea097334d6 241 bool privilegedLDMA : 1; /**< Privileged access enabler for LDMA */
Anna Bridge 142:4eea097334d6 242 bool privilegedLESENSE : 1; /**< Privileged access enabler for LESENSE */
Anna Bridge 142:4eea097334d6 243 bool privilegedLETIMER0 : 1; /**< Privileged access enabler for LETIMER0 */
Anna Bridge 142:4eea097334d6 244 bool privilegedLEUART0 : 1; /**< Privileged access enabler for LEUART0 */
Anna Bridge 142:4eea097334d6 245 bool privilegedReserved4 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 246 bool privilegedPCNT0 : 1; /**< Privileged access enabler for PCNT0 */
Anna Bridge 142:4eea097334d6 247 bool privilegedReserved5 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 248 bool privilegedReserved6 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 249 bool privilegedReserved7 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 250 bool privilegedReserved8 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 251 bool privilegedRMU : 1; /**< Privileged access enabler for RMU */
Anna Bridge 142:4eea097334d6 252 bool privilegedRTCC : 1; /**< Privileged access enabler for RTCC */
Anna Bridge 142:4eea097334d6 253 bool privilegedSMU : 1; /**< Privileged access enabler for SMU */
Anna Bridge 142:4eea097334d6 254 bool privilegedReserved9 : 1; /**< Reserved privileged access enabler */
Anna Bridge 142:4eea097334d6 255 bool privilegedTIMER0 : 1; /**< Privileged access enabler for TIMER0 */
Anna Bridge 142:4eea097334d6 256 bool privilegedTIMER1 : 1; /**< Privileged access enabler for TIMER1 */
Anna Bridge 142:4eea097334d6 257 bool privilegedTRNG0 : 1; /**< Privileged access enabler for TRNG0 */
Anna Bridge 142:4eea097334d6 258 bool privilegedUSART0 : 1; /**< Privileged access enabler for USART0 */
Anna Bridge 142:4eea097334d6 259 bool privilegedUSART1 : 1; /**< Privileged access enabler for USART1 */
Anna Bridge 142:4eea097334d6 260 bool privilegedUSART2 : 1; /**< Privileged access enabler for USART2 */
Anna Bridge 142:4eea097334d6 261 bool privilegedWDOG0 : 1; /**< Privileged access enabler for WDOG0 */
Anna Bridge 142:4eea097334d6 262 bool privilegedWDOG1 : 1; /**< Privileged access enabler for WDOG1 */
Anna Bridge 142:4eea097334d6 263 bool privilegedWTIMER0 : 1; /**< Privileged access enabler for WTIMER0 */
Anna Bridge 142:4eea097334d6 264
Anna Bridge 142:4eea097334d6 265 #else
Anna Bridge 142:4eea097334d6 266 #error "No peripherals defined for SMU for this device configuration"
Anna Bridge 142:4eea097334d6 267 #endif
Anna Bridge 142:4eea097334d6 268 } SMU_PrivilegedAccess_TypeDef;
Anna Bridge 142:4eea097334d6 269
Anna Bridge 142:4eea097334d6 270 /*******************************************************************************
Anna Bridge 142:4eea097334d6 271 ****************************** STRUCTS ************************************
Anna Bridge 142:4eea097334d6 272 ******************************************************************************/
Anna Bridge 142:4eea097334d6 273
Anna Bridge 142:4eea097334d6 274 /** SMU initialization structure. */
Anna Bridge 142:4eea097334d6 275 typedef struct {
Anna Bridge 142:4eea097334d6 276 union {
Anna Bridge 142:4eea097334d6 277 uint32_t reg[2]; /**< Periperal access control array.*/
Anna Bridge 142:4eea097334d6 278 SMU_PrivilegedAccess_TypeDef access; /**< Periperal access control array.*/
Anna Bridge 142:4eea097334d6 279 } ppu;
Anna Bridge 142:4eea097334d6 280 bool enable; /**< SMU enable flag, when set SMU_Init() will enable SMU.*/
Anna Bridge 142:4eea097334d6 281 } SMU_Init_TypeDef;
Anna Bridge 142:4eea097334d6 282
Anna Bridge 142:4eea097334d6 283 #if defined(_SILICON_LABS_32B_SERIES_1) && (_SILICON_LABS_GECKO_INTERNAL_SDID > 80)
Anna Bridge 142:4eea097334d6 284 /** Default SMU initialization struct settings. */
Anna Bridge 142:4eea097334d6 285 #define SMU_INIT_DEFAULT { \
Anna Bridge 142:4eea097334d6 286 {{0}}, /* No peripherals acsess protected. */ \
Anna Bridge 142:4eea097334d6 287 true /* Enable SMU.*/ \
Anna Bridge 142:4eea097334d6 288 }
Anna Bridge 142:4eea097334d6 289 #endif
Anna Bridge 142:4eea097334d6 290
Anna Bridge 142:4eea097334d6 291 /*******************************************************************************
Anna Bridge 142:4eea097334d6 292 ***************************** PROTOTYPES **********************************
Anna Bridge 142:4eea097334d6 293 ******************************************************************************/
Anna Bridge 142:4eea097334d6 294
Anna Bridge 142:4eea097334d6 295 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 296 * @brief
Anna Bridge 142:4eea097334d6 297 * Enable or disable the Peripheral Protection Unit of the SMU.
Anna Bridge 142:4eea097334d6 298 *
Anna Bridge 142:4eea097334d6 299 * @param[in] enable
Anna Bridge 142:4eea097334d6 300 * True if the PPU should be enabled, false if it should be disabled.
Anna Bridge 142:4eea097334d6 301 ******************************************************************************/
Anna Bridge 142:4eea097334d6 302 __STATIC_INLINE void SMU_EnablePPU(bool enable)
Anna Bridge 142:4eea097334d6 303 {
Anna Bridge 142:4eea097334d6 304 BUS_RegBitWrite(&SMU->PPUCTRL, _SMU_PPUCTRL_ENABLE_SHIFT, enable);
Anna Bridge 142:4eea097334d6 305 }
Anna Bridge 142:4eea097334d6 306
Anna Bridge 142:4eea097334d6 307 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 308 * @brief
Anna Bridge 142:4eea097334d6 309 * Initialize the Peripheral Protection Unit of the SMU.
Anna Bridge 142:4eea097334d6 310 *
Anna Bridge 142:4eea097334d6 311 * @param[in] init
Anna Bridge 142:4eea097334d6 312 * Pointer to initialization struct defining which peripherals should only
Anna Bridge 142:4eea097334d6 313 * be accessed from privileged mode, and whether the PPU should be enabled.
Anna Bridge 142:4eea097334d6 314 ******************************************************************************/
Anna Bridge 142:4eea097334d6 315 __STATIC_INLINE void SMU_Init(const SMU_Init_TypeDef *init)
Anna Bridge 142:4eea097334d6 316 {
Anna Bridge 142:4eea097334d6 317 SMU->PPUPATD0 = init->ppu.reg[0];
Anna Bridge 142:4eea097334d6 318 SMU->PPUPATD1 = init->ppu.reg[1];
Anna Bridge 142:4eea097334d6 319
Anna Bridge 142:4eea097334d6 320 SMU_EnablePPU(init->enable);
Anna Bridge 142:4eea097334d6 321 }
Anna Bridge 142:4eea097334d6 322
Anna Bridge 142:4eea097334d6 323 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 324 * @brief
Anna Bridge 142:4eea097334d6 325 * Change the access settings for a peripheral
Anna Bridge 142:4eea097334d6 326 *
Anna Bridge 142:4eea097334d6 327 * @details
Anna Bridge 142:4eea097334d6 328 * Set whether the peripheral can only be accessed from privileged mode
Anna Bridge 142:4eea097334d6 329 *
Anna Bridge 142:4eea097334d6 330 * @param[in] peripheral
Anna Bridge 142:4eea097334d6 331 * ID of the peripheral to change access settings for
Anna Bridge 142:4eea097334d6 332 *
Anna Bridge 142:4eea097334d6 333 * @param[in] privileged
Anna Bridge 142:4eea097334d6 334 * True if the peripheral should only be allowed to be accessed from
Anna Bridge 142:4eea097334d6 335 * privileged mode, false if the peripheral can be accessed from unprivileged
Anna Bridge 142:4eea097334d6 336 * mode.
Anna Bridge 142:4eea097334d6 337 ******************************************************************************/
Anna Bridge 142:4eea097334d6 338 __STATIC_INLINE void SMU_SetPrivilegedAccess(SMU_Peripheral_TypeDef peripheral,
Anna Bridge 142:4eea097334d6 339 bool privileged)
Anna Bridge 142:4eea097334d6 340 {
Anna Bridge 142:4eea097334d6 341 EFM_ASSERT(peripheral < smuPeripheralEnd);
Anna Bridge 142:4eea097334d6 342
Anna Bridge 142:4eea097334d6 343 if (peripheral < 32) {
Anna Bridge 142:4eea097334d6 344 BUS_RegBitWrite(&SMU->PPUPATD0, peripheral, privileged);
Anna Bridge 142:4eea097334d6 345 } else {
Anna Bridge 142:4eea097334d6 346 BUS_RegBitWrite(&SMU->PPUPATD1, peripheral - 32, privileged);
Anna Bridge 142:4eea097334d6 347 }
Anna Bridge 142:4eea097334d6 348 }
Anna Bridge 142:4eea097334d6 349
Anna Bridge 142:4eea097334d6 350 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 351 * @brief
Anna Bridge 142:4eea097334d6 352 * Get the ID of the peripheral that caused an access fault.
Anna Bridge 142:4eea097334d6 353 *
Anna Bridge 142:4eea097334d6 354 * @note
Anna Bridge 142:4eea097334d6 355 * The return value is only valid if the @ref SMU_IF_PPUPRIV interrupt flag
Anna Bridge 142:4eea097334d6 356 * is set.
Anna Bridge 142:4eea097334d6 357 *
Anna Bridge 142:4eea097334d6 358 * @return
Anna Bridge 142:4eea097334d6 359 * ID of the faulting peripheral.
Anna Bridge 142:4eea097334d6 360 ******************************************************************************/
Anna Bridge 142:4eea097334d6 361 __STATIC_INLINE SMU_Peripheral_TypeDef SMU_GetFaultingPeripheral(void)
Anna Bridge 142:4eea097334d6 362 {
Anna Bridge 142:4eea097334d6 363 return (SMU_Peripheral_TypeDef)SMU->PPUFS;
Anna Bridge 142:4eea097334d6 364 }
Anna Bridge 142:4eea097334d6 365
Anna Bridge 142:4eea097334d6 366 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 367 * @brief
Anna Bridge 142:4eea097334d6 368 * Clear one or more pending SMU interrupts.
Anna Bridge 142:4eea097334d6 369 *
Anna Bridge 142:4eea097334d6 370 * @param[in] flags
Anna Bridge 142:4eea097334d6 371 * Bitwise logic OR of SMU interrupt sources to clear.
Anna Bridge 142:4eea097334d6 372 ******************************************************************************/
Anna Bridge 142:4eea097334d6 373 __STATIC_INLINE void SMU_IntClear(uint32_t flags)
Anna Bridge 142:4eea097334d6 374 {
Anna Bridge 142:4eea097334d6 375 SMU->IFC = flags;
Anna Bridge 142:4eea097334d6 376 }
Anna Bridge 142:4eea097334d6 377
Anna Bridge 142:4eea097334d6 378 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 379 * @brief
Anna Bridge 142:4eea097334d6 380 * Disable one or more SMU interrupts.
Anna Bridge 142:4eea097334d6 381 *
Anna Bridge 142:4eea097334d6 382 * @param[in] flags
Anna Bridge 142:4eea097334d6 383 * SMU interrupt sources to disable.
Anna Bridge 142:4eea097334d6 384 ******************************************************************************/
Anna Bridge 142:4eea097334d6 385 __STATIC_INLINE void SMU_IntDisable(uint32_t flags)
Anna Bridge 142:4eea097334d6 386 {
Anna Bridge 142:4eea097334d6 387 SMU->IEN &= ~flags;
Anna Bridge 142:4eea097334d6 388 }
Anna Bridge 142:4eea097334d6 389
Anna Bridge 142:4eea097334d6 390 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 391 * @brief
Anna Bridge 142:4eea097334d6 392 * Enable one or more SMU interrupts.
Anna Bridge 142:4eea097334d6 393 *
Anna Bridge 142:4eea097334d6 394 * @note
Anna Bridge 142:4eea097334d6 395 * Depending on the use, a pending interrupt may already be set prior to
Anna Bridge 142:4eea097334d6 396 * enabling the interrupt. Consider using SMU_IntClear() prior to enabling
Anna Bridge 142:4eea097334d6 397 * if such a pending interrupt should be ignored.
Anna Bridge 142:4eea097334d6 398 *
Anna Bridge 142:4eea097334d6 399 * @param[in] flags
Anna Bridge 142:4eea097334d6 400 * SMU interrupt sources to enable.
Anna Bridge 142:4eea097334d6 401 ******************************************************************************/
Anna Bridge 142:4eea097334d6 402 __STATIC_INLINE void SMU_IntEnable(uint32_t flags)
Anna Bridge 142:4eea097334d6 403 {
Anna Bridge 142:4eea097334d6 404 SMU->IEN |= flags;
Anna Bridge 142:4eea097334d6 405 }
Anna Bridge 142:4eea097334d6 406
Anna Bridge 142:4eea097334d6 407 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 408 * @brief
Anna Bridge 142:4eea097334d6 409 * Get pending SMU interrupts.
Anna Bridge 142:4eea097334d6 410 *
Anna Bridge 142:4eea097334d6 411 * @return
Anna Bridge 142:4eea097334d6 412 * SMU interrupt sources pending.
Anna Bridge 142:4eea097334d6 413 ******************************************************************************/
Anna Bridge 142:4eea097334d6 414 __STATIC_INLINE uint32_t SMU_IntGet(void)
Anna Bridge 142:4eea097334d6 415 {
Anna Bridge 142:4eea097334d6 416 return SMU->IF;
Anna Bridge 142:4eea097334d6 417 }
Anna Bridge 142:4eea097334d6 418
Anna Bridge 142:4eea097334d6 419 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 420 * @brief
Anna Bridge 142:4eea097334d6 421 * Get enabled and pending SMU interrupt flags.
Anna Bridge 142:4eea097334d6 422 * Useful for handling more interrupt sources in the same interrupt handler.
Anna Bridge 142:4eea097334d6 423 *
Anna Bridge 142:4eea097334d6 424 * @note
Anna Bridge 142:4eea097334d6 425 * Interrupt flags are not cleared by the use of this function.
Anna Bridge 142:4eea097334d6 426 *
Anna Bridge 142:4eea097334d6 427 * @return
Anna Bridge 142:4eea097334d6 428 * Pending and enabled SMU interrupt sources.
Anna Bridge 142:4eea097334d6 429 * The return value is the bitwise AND combination of
Anna Bridge 142:4eea097334d6 430 * - the OR combination of enabled interrupt sources in SMU_IEN register
Anna Bridge 142:4eea097334d6 431 * and
Anna Bridge 142:4eea097334d6 432 * - the OR combination of valid interrupt flags in SMU_IF register.
Anna Bridge 142:4eea097334d6 433 ******************************************************************************/
Anna Bridge 142:4eea097334d6 434 __STATIC_INLINE uint32_t SMU_IntGetEnabled(void)
Anna Bridge 142:4eea097334d6 435 {
Anna Bridge 142:4eea097334d6 436 uint32_t tmp;
Anna Bridge 142:4eea097334d6 437
Anna Bridge 142:4eea097334d6 438 // Store SMU->IEN in temporary variable in order to define explicit order
Anna Bridge 142:4eea097334d6 439 // of volatile accesses.
Anna Bridge 142:4eea097334d6 440 tmp = SMU->IEN;
Anna Bridge 142:4eea097334d6 441
Anna Bridge 142:4eea097334d6 442 // Bitwise AND of pending and enabled interrupts
Anna Bridge 142:4eea097334d6 443 return SMU->IF & tmp;
Anna Bridge 142:4eea097334d6 444 }
Anna Bridge 142:4eea097334d6 445
Anna Bridge 142:4eea097334d6 446 /************************************************************************Æ**//**
Anna Bridge 142:4eea097334d6 447 * @brief
Anna Bridge 142:4eea097334d6 448 * Set one or more pending SMU interrupts from SW.
Anna Bridge 142:4eea097334d6 449 *
Anna Bridge 142:4eea097334d6 450 * @param[in] flags
Anna Bridge 142:4eea097334d6 451 * SMU interrupt sources to set to pending.
Anna Bridge 142:4eea097334d6 452 *************************************************************************Æ****/
Anna Bridge 142:4eea097334d6 453 __STATIC_INLINE void SMU_IntSet(uint32_t flags)
Anna Bridge 142:4eea097334d6 454 {
Anna Bridge 142:4eea097334d6 455 SMU->IFS = flags;
Anna Bridge 142:4eea097334d6 456 }
Anna Bridge 142:4eea097334d6 457
Anna Bridge 142:4eea097334d6 458 /** @} (end addtogroup SMU) */
Anna Bridge 142:4eea097334d6 459 /** @} (end addtogroup emlib) */
Anna Bridge 142:4eea097334d6 460
Anna Bridge 142:4eea097334d6 461 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 462 }
Anna Bridge 142:4eea097334d6 463 #endif
Anna Bridge 142:4eea097334d6 464
Anna Bridge 142:4eea097334d6 465 #endif // defined(SMU_COUNT) && (SMU_COUNT > 0)
Anna Bridge 142:4eea097334d6 466 #endif // EM_SMU_H