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TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg990f512.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32gg990f512.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 4 * for EFM32GG990F512
AnnaBridge 171:3a7713b1edbc 5 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @section License
AnnaBridge 171:3a7713b1edbc 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 12 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 13 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 16 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 17 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 18 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 19 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 20 *
AnnaBridge 171:3a7713b1edbc 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 23 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 24 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 25 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 26 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 29 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 30 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 31 *
AnnaBridge 171:3a7713b1edbc 32 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef EFM32GG990F512_H
AnnaBridge 171:3a7713b1edbc 35 #define EFM32GG990F512_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 42 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 47 * @defgroup EFM32GG990F512 EFM32GG990F512
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** Interrupt Number Definition */
AnnaBridge 171:3a7713b1edbc 52 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 53 {
AnnaBridge 171:3a7713b1edbc 54 /****** Cortex-M3 Processor Exceptions Numbers ********************************************/
AnnaBridge 171:3a7713b1edbc 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 56 HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 58 BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 60 SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 62 PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 63 SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /****** EFM32G Peripheral Interrupt Numbers ***********************************************/
AnnaBridge 171:3a7713b1edbc 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
AnnaBridge 171:3a7713b1edbc 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
AnnaBridge 171:3a7713b1edbc 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
AnnaBridge 171:3a7713b1edbc 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 71 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
AnnaBridge 171:3a7713b1edbc 72 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
AnnaBridge 171:3a7713b1edbc 73 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
AnnaBridge 171:3a7713b1edbc 74 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
AnnaBridge 171:3a7713b1edbc 75 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
AnnaBridge 171:3a7713b1edbc 76 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
AnnaBridge 171:3a7713b1edbc 77 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
AnnaBridge 171:3a7713b1edbc 78 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
AnnaBridge 171:3a7713b1edbc 79 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
AnnaBridge 171:3a7713b1edbc 80 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
AnnaBridge 171:3a7713b1edbc 81 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 82 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 83 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
AnnaBridge 171:3a7713b1edbc 84 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 85 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 86 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 87 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 88 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 89 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 90 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
AnnaBridge 171:3a7713b1edbc 91 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
AnnaBridge 171:3a7713b1edbc 92 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
AnnaBridge 171:3a7713b1edbc 93 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
AnnaBridge 171:3a7713b1edbc 94 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
AnnaBridge 171:3a7713b1edbc 95 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
AnnaBridge 171:3a7713b1edbc 96 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
AnnaBridge 171:3a7713b1edbc 97 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
AnnaBridge 171:3a7713b1edbc 98 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
AnnaBridge 171:3a7713b1edbc 99 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
AnnaBridge 171:3a7713b1edbc 100 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
AnnaBridge 171:3a7713b1edbc 101 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
AnnaBridge 171:3a7713b1edbc 102 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
AnnaBridge 171:3a7713b1edbc 103 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
AnnaBridge 171:3a7713b1edbc 104 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
AnnaBridge 171:3a7713b1edbc 105 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 106
AnnaBridge 171:3a7713b1edbc 107 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 108 * @defgroup EFM32GG990F512_Core EFM32GG990F512 Core
AnnaBridge 171:3a7713b1edbc 109 * @{
AnnaBridge 171:3a7713b1edbc 110 * @brief Processor and Core Peripheral Section
AnnaBridge 171:3a7713b1edbc 111 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 112 #define __MPU_PRESENT 1 /**< Presence of MPU */
AnnaBridge 171:3a7713b1edbc 113 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
AnnaBridge 171:3a7713b1edbc 114 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
AnnaBridge 171:3a7713b1edbc 115 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
AnnaBridge 171:3a7713b1edbc 116
AnnaBridge 171:3a7713b1edbc 117 /** @} End of group EFM32GG990F512_Core */
AnnaBridge 171:3a7713b1edbc 118
AnnaBridge 171:3a7713b1edbc 119 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 120 * @defgroup EFM32GG990F512_Part EFM32GG990F512 Part
AnnaBridge 171:3a7713b1edbc 121 * @{
AnnaBridge 171:3a7713b1edbc 122 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 123
AnnaBridge 171:3a7713b1edbc 124 /** Part family */
AnnaBridge 171:3a7713b1edbc 125 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
AnnaBridge 171:3a7713b1edbc 126 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
AnnaBridge 171:3a7713b1edbc 127 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
AnnaBridge 171:3a7713b1edbc 128 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
AnnaBridge 171:3a7713b1edbc 129 #define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */
AnnaBridge 171:3a7713b1edbc 130 #define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */
AnnaBridge 171:3a7713b1edbc 131 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 171:3a7713b1edbc 132 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 171:3a7713b1edbc 133
AnnaBridge 171:3a7713b1edbc 134 /* If part number is not defined as compiler option, define it */
AnnaBridge 171:3a7713b1edbc 135 #if !defined(EFM32GG990F512)
AnnaBridge 171:3a7713b1edbc 136 #define EFM32GG990F512 1 /**< Giant/Leopard Gecko Part */
AnnaBridge 171:3a7713b1edbc 137 #endif
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /** Configure part number */
AnnaBridge 171:3a7713b1edbc 140 #define PART_NUMBER "EFM32GG990F512" /**< Part Number */
AnnaBridge 171:3a7713b1edbc 141
AnnaBridge 171:3a7713b1edbc 142 /** Memory Base addresses and limits */
AnnaBridge 171:3a7713b1edbc 143 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
AnnaBridge 171:3a7713b1edbc 144 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
AnnaBridge 171:3a7713b1edbc 145 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
AnnaBridge 171:3a7713b1edbc 146 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
AnnaBridge 171:3a7713b1edbc 147 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
AnnaBridge 171:3a7713b1edbc 148 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
AnnaBridge 171:3a7713b1edbc 149 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
AnnaBridge 171:3a7713b1edbc 150 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
AnnaBridge 171:3a7713b1edbc 151 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
AnnaBridge 171:3a7713b1edbc 152 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
AnnaBridge 171:3a7713b1edbc 153 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
AnnaBridge 171:3a7713b1edbc 154 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
AnnaBridge 171:3a7713b1edbc 155 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
AnnaBridge 171:3a7713b1edbc 156 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
AnnaBridge 171:3a7713b1edbc 157 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
AnnaBridge 171:3a7713b1edbc 158 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
AnnaBridge 171:3a7713b1edbc 159 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
AnnaBridge 171:3a7713b1edbc 160 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
AnnaBridge 171:3a7713b1edbc 161 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
AnnaBridge 171:3a7713b1edbc 162 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
AnnaBridge 171:3a7713b1edbc 163 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
AnnaBridge 171:3a7713b1edbc 164 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
AnnaBridge 171:3a7713b1edbc 165 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
AnnaBridge 171:3a7713b1edbc 166 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
AnnaBridge 171:3a7713b1edbc 167 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
AnnaBridge 171:3a7713b1edbc 168 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
AnnaBridge 171:3a7713b1edbc 169 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
AnnaBridge 171:3a7713b1edbc 170 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
AnnaBridge 171:3a7713b1edbc 171 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
AnnaBridge 171:3a7713b1edbc 172 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
AnnaBridge 171:3a7713b1edbc 173 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
AnnaBridge 171:3a7713b1edbc 174 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 /** Bit banding area */
AnnaBridge 171:3a7713b1edbc 177 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
AnnaBridge 171:3a7713b1edbc 178 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
AnnaBridge 171:3a7713b1edbc 179
AnnaBridge 171:3a7713b1edbc 180 /** Flash and SRAM limits for EFM32GG990F512 */
AnnaBridge 171:3a7713b1edbc 181 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
AnnaBridge 171:3a7713b1edbc 182 #define FLASH_SIZE (0x00080000UL) /**< Available Flash Memory */
AnnaBridge 171:3a7713b1edbc 183 #define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
AnnaBridge 171:3a7713b1edbc 184 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
AnnaBridge 171:3a7713b1edbc 185 #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
AnnaBridge 171:3a7713b1edbc 186 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
AnnaBridge 171:3a7713b1edbc 187 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
AnnaBridge 171:3a7713b1edbc 188 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
AnnaBridge 171:3a7713b1edbc 189 #define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /** AF channels connect the different on-chip peripherals with the af-mux */
AnnaBridge 171:3a7713b1edbc 192 #define AFCHAN_MAX 163
AnnaBridge 171:3a7713b1edbc 193 #define AFCHANLOC_MAX 7
AnnaBridge 171:3a7713b1edbc 194 /** Analog AF channels */
AnnaBridge 171:3a7713b1edbc 195 #define AFACHAN_MAX 53
AnnaBridge 171:3a7713b1edbc 196
AnnaBridge 171:3a7713b1edbc 197 /* Part number capabilities */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 #define LETIMER_PRESENT /**< LETIMER is available in this part */
AnnaBridge 171:3a7713b1edbc 200 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
AnnaBridge 171:3a7713b1edbc 201 #define USART_PRESENT /**< USART is available in this part */
AnnaBridge 171:3a7713b1edbc 202 #define USART_COUNT 3 /**< 3 USARTs available */
AnnaBridge 171:3a7713b1edbc 203 #define UART_PRESENT /**< UART is available in this part */
AnnaBridge 171:3a7713b1edbc 204 #define UART_COUNT 2 /**< 2 UARTs available */
AnnaBridge 171:3a7713b1edbc 205 #define TIMER_PRESENT /**< TIMER is available in this part */
AnnaBridge 171:3a7713b1edbc 206 #define TIMER_COUNT 4 /**< 4 TIMERs available */
AnnaBridge 171:3a7713b1edbc 207 #define ACMP_PRESENT /**< ACMP is available in this part */
AnnaBridge 171:3a7713b1edbc 208 #define ACMP_COUNT 2 /**< 2 ACMPs available */
AnnaBridge 171:3a7713b1edbc 209 #define I2C_PRESENT /**< I2C is available in this part */
AnnaBridge 171:3a7713b1edbc 210 #define I2C_COUNT 2 /**< 2 I2Cs available */
AnnaBridge 171:3a7713b1edbc 211 #define LEUART_PRESENT /**< LEUART is available in this part */
AnnaBridge 171:3a7713b1edbc 212 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
AnnaBridge 171:3a7713b1edbc 213 #define PCNT_PRESENT /**< PCNT is available in this part */
AnnaBridge 171:3a7713b1edbc 214 #define PCNT_COUNT 3 /**< 3 PCNTs available */
AnnaBridge 171:3a7713b1edbc 215 #define ADC_PRESENT /**< ADC is available in this part */
AnnaBridge 171:3a7713b1edbc 216 #define ADC_COUNT 1 /**< 1 ADCs available */
AnnaBridge 171:3a7713b1edbc 217 #define DAC_PRESENT /**< DAC is available in this part */
AnnaBridge 171:3a7713b1edbc 218 #define DAC_COUNT 1 /**< 1 DACs available */
AnnaBridge 171:3a7713b1edbc 219 #define DMA_PRESENT
AnnaBridge 171:3a7713b1edbc 220 #define DMA_COUNT 1
AnnaBridge 171:3a7713b1edbc 221 #define AES_PRESENT
AnnaBridge 171:3a7713b1edbc 222 #define AES_COUNT 1
AnnaBridge 171:3a7713b1edbc 223 #define USBC_PRESENT
AnnaBridge 171:3a7713b1edbc 224 #define USBC_COUNT 1
AnnaBridge 171:3a7713b1edbc 225 #define USB_PRESENT
AnnaBridge 171:3a7713b1edbc 226 #define USB_COUNT 1
AnnaBridge 171:3a7713b1edbc 227 #define LE_PRESENT
AnnaBridge 171:3a7713b1edbc 228 #define LE_COUNT 1
AnnaBridge 171:3a7713b1edbc 229 #define MSC_PRESENT
AnnaBridge 171:3a7713b1edbc 230 #define MSC_COUNT 1
AnnaBridge 171:3a7713b1edbc 231 #define EMU_PRESENT
AnnaBridge 171:3a7713b1edbc 232 #define EMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 233 #define RMU_PRESENT
AnnaBridge 171:3a7713b1edbc 234 #define RMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 235 #define CMU_PRESENT
AnnaBridge 171:3a7713b1edbc 236 #define CMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 237 #define LESENSE_PRESENT
AnnaBridge 171:3a7713b1edbc 238 #define LESENSE_COUNT 1
AnnaBridge 171:3a7713b1edbc 239 #define RTC_PRESENT
AnnaBridge 171:3a7713b1edbc 240 #define RTC_COUNT 1
AnnaBridge 171:3a7713b1edbc 241 #define EBI_PRESENT
AnnaBridge 171:3a7713b1edbc 242 #define EBI_COUNT 1
AnnaBridge 171:3a7713b1edbc 243 #define GPIO_PRESENT
AnnaBridge 171:3a7713b1edbc 244 #define GPIO_COUNT 1
AnnaBridge 171:3a7713b1edbc 245 #define VCMP_PRESENT
AnnaBridge 171:3a7713b1edbc 246 #define VCMP_COUNT 1
AnnaBridge 171:3a7713b1edbc 247 #define PRS_PRESENT
AnnaBridge 171:3a7713b1edbc 248 #define PRS_COUNT 1
AnnaBridge 171:3a7713b1edbc 249 #define OPAMP_PRESENT
AnnaBridge 171:3a7713b1edbc 250 #define OPAMP_COUNT 1
AnnaBridge 171:3a7713b1edbc 251 #define BU_PRESENT
AnnaBridge 171:3a7713b1edbc 252 #define BU_COUNT 1
AnnaBridge 171:3a7713b1edbc 253 #define LCD_PRESENT
AnnaBridge 171:3a7713b1edbc 254 #define LCD_COUNT 1
AnnaBridge 171:3a7713b1edbc 255 #define BURTC_PRESENT
AnnaBridge 171:3a7713b1edbc 256 #define BURTC_COUNT 1
AnnaBridge 171:3a7713b1edbc 257 #define HFXTAL_PRESENT
AnnaBridge 171:3a7713b1edbc 258 #define HFXTAL_COUNT 1
AnnaBridge 171:3a7713b1edbc 259 #define LFXTAL_PRESENT
AnnaBridge 171:3a7713b1edbc 260 #define LFXTAL_COUNT 1
AnnaBridge 171:3a7713b1edbc 261 #define WDOG_PRESENT
AnnaBridge 171:3a7713b1edbc 262 #define WDOG_COUNT 1
AnnaBridge 171:3a7713b1edbc 263 #define DBG_PRESENT
AnnaBridge 171:3a7713b1edbc 264 #define DBG_COUNT 1
AnnaBridge 171:3a7713b1edbc 265 #define ETM_PRESENT
AnnaBridge 171:3a7713b1edbc 266 #define ETM_COUNT 1
AnnaBridge 171:3a7713b1edbc 267 #define BOOTLOADER_PRESENT
AnnaBridge 171:3a7713b1edbc 268 #define BOOTLOADER_COUNT 1
AnnaBridge 171:3a7713b1edbc 269 #define ANALOG_PRESENT
AnnaBridge 171:3a7713b1edbc 270 #define ANALOG_COUNT 1
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 273 #include "system_efm32gg.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 274
AnnaBridge 171:3a7713b1edbc 275 /** @} End of group EFM32GG990F512_Part */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 278 * @defgroup EFM32GG990F512_Peripheral_TypeDefs EFM32GG990F512 Peripheral TypeDefs
AnnaBridge 171:3a7713b1edbc 279 * @{
AnnaBridge 171:3a7713b1edbc 280 * @brief Device Specific Peripheral Register Structures
AnnaBridge 171:3a7713b1edbc 281 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 282
AnnaBridge 171:3a7713b1edbc 283 #include "efm32gg_dma_ch.h"
AnnaBridge 171:3a7713b1edbc 284 #include "efm32gg_dma.h"
AnnaBridge 171:3a7713b1edbc 285 #include "efm32gg_aes.h"
AnnaBridge 171:3a7713b1edbc 286 #include "efm32gg_usb_hc.h"
AnnaBridge 171:3a7713b1edbc 287 #include "efm32gg_usb_diep.h"
AnnaBridge 171:3a7713b1edbc 288 #include "efm32gg_usb_doep.h"
AnnaBridge 171:3a7713b1edbc 289 #include "efm32gg_usb.h"
AnnaBridge 171:3a7713b1edbc 290 #include "efm32gg_msc.h"
AnnaBridge 171:3a7713b1edbc 291 #include "efm32gg_emu.h"
AnnaBridge 171:3a7713b1edbc 292 #include "efm32gg_rmu.h"
AnnaBridge 171:3a7713b1edbc 293 #include "efm32gg_cmu.h"
AnnaBridge 171:3a7713b1edbc 294 #include "efm32gg_lesense_st.h"
AnnaBridge 171:3a7713b1edbc 295 #include "efm32gg_lesense_buf.h"
AnnaBridge 171:3a7713b1edbc 296 #include "efm32gg_lesense_ch.h"
AnnaBridge 171:3a7713b1edbc 297 #include "efm32gg_lesense.h"
AnnaBridge 171:3a7713b1edbc 298 #include "efm32gg_rtc.h"
AnnaBridge 171:3a7713b1edbc 299 #include "efm32gg_letimer.h"
AnnaBridge 171:3a7713b1edbc 300 #include "efm32gg_ebi.h"
AnnaBridge 171:3a7713b1edbc 301 #include "efm32gg_usart.h"
AnnaBridge 171:3a7713b1edbc 302 #include "efm32gg_timer_cc.h"
AnnaBridge 171:3a7713b1edbc 303 #include "efm32gg_timer.h"
AnnaBridge 171:3a7713b1edbc 304 #include "efm32gg_acmp.h"
AnnaBridge 171:3a7713b1edbc 305 #include "efm32gg_i2c.h"
AnnaBridge 171:3a7713b1edbc 306 #include "efm32gg_gpio_p.h"
AnnaBridge 171:3a7713b1edbc 307 #include "efm32gg_gpio.h"
AnnaBridge 171:3a7713b1edbc 308 #include "efm32gg_vcmp.h"
AnnaBridge 171:3a7713b1edbc 309 #include "efm32gg_prs_ch.h"
AnnaBridge 171:3a7713b1edbc 310 #include "efm32gg_prs.h"
AnnaBridge 171:3a7713b1edbc 311 #include "efm32gg_leuart.h"
AnnaBridge 171:3a7713b1edbc 312 #include "efm32gg_pcnt.h"
AnnaBridge 171:3a7713b1edbc 313 #include "efm32gg_adc.h"
AnnaBridge 171:3a7713b1edbc 314 #include "efm32gg_dac.h"
AnnaBridge 171:3a7713b1edbc 315 #include "efm32gg_lcd.h"
AnnaBridge 171:3a7713b1edbc 316 #include "efm32gg_burtc_ret.h"
AnnaBridge 171:3a7713b1edbc 317 #include "efm32gg_burtc.h"
AnnaBridge 171:3a7713b1edbc 318 #include "efm32gg_wdog.h"
AnnaBridge 171:3a7713b1edbc 319 #include "efm32gg_etm.h"
AnnaBridge 171:3a7713b1edbc 320 #include "efm32gg_dma_descriptor.h"
AnnaBridge 171:3a7713b1edbc 321 #include "efm32gg_devinfo.h"
AnnaBridge 171:3a7713b1edbc 322 #include "efm32gg_romtable.h"
AnnaBridge 171:3a7713b1edbc 323 #include "efm32gg_calibrate.h"
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /** @} End of group EFM32GG990F512_Peripheral_TypeDefs */
AnnaBridge 171:3a7713b1edbc 326
AnnaBridge 171:3a7713b1edbc 327 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 328 * @defgroup EFM32GG990F512_Peripheral_Base EFM32GG990F512 Peripheral Memory Map
AnnaBridge 171:3a7713b1edbc 329 * @{
AnnaBridge 171:3a7713b1edbc 330 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 331
AnnaBridge 171:3a7713b1edbc 332 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
AnnaBridge 171:3a7713b1edbc 333 #define AES_BASE (0x400E0000UL) /**< AES base address */
AnnaBridge 171:3a7713b1edbc 334 #define USB_BASE (0x400C4000UL) /**< USB base address */
AnnaBridge 171:3a7713b1edbc 335 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
AnnaBridge 171:3a7713b1edbc 336 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
AnnaBridge 171:3a7713b1edbc 337 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
AnnaBridge 171:3a7713b1edbc 338 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
AnnaBridge 171:3a7713b1edbc 339 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
AnnaBridge 171:3a7713b1edbc 340 #define RTC_BASE (0x40080000UL) /**< RTC base address */
AnnaBridge 171:3a7713b1edbc 341 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
AnnaBridge 171:3a7713b1edbc 342 #define EBI_BASE (0x40008000UL) /**< EBI base address */
AnnaBridge 171:3a7713b1edbc 343 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
AnnaBridge 171:3a7713b1edbc 344 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
AnnaBridge 171:3a7713b1edbc 345 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
AnnaBridge 171:3a7713b1edbc 346 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
AnnaBridge 171:3a7713b1edbc 347 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
AnnaBridge 171:3a7713b1edbc 348 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
AnnaBridge 171:3a7713b1edbc 349 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
AnnaBridge 171:3a7713b1edbc 350 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
AnnaBridge 171:3a7713b1edbc 351 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
AnnaBridge 171:3a7713b1edbc 352 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
AnnaBridge 171:3a7713b1edbc 353 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
AnnaBridge 171:3a7713b1edbc 354 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
AnnaBridge 171:3a7713b1edbc 355 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
AnnaBridge 171:3a7713b1edbc 356 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
AnnaBridge 171:3a7713b1edbc 357 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
AnnaBridge 171:3a7713b1edbc 358 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
AnnaBridge 171:3a7713b1edbc 359 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
AnnaBridge 171:3a7713b1edbc 360 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
AnnaBridge 171:3a7713b1edbc 361 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
AnnaBridge 171:3a7713b1edbc 362 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
AnnaBridge 171:3a7713b1edbc 363 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
AnnaBridge 171:3a7713b1edbc 364 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
AnnaBridge 171:3a7713b1edbc 365 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
AnnaBridge 171:3a7713b1edbc 366 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
AnnaBridge 171:3a7713b1edbc 367 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
AnnaBridge 171:3a7713b1edbc 368 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
AnnaBridge 171:3a7713b1edbc 369 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
AnnaBridge 171:3a7713b1edbc 370 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
AnnaBridge 171:3a7713b1edbc 371 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
AnnaBridge 171:3a7713b1edbc 372 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
AnnaBridge 171:3a7713b1edbc 373 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
AnnaBridge 171:3a7713b1edbc 374 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
AnnaBridge 171:3a7713b1edbc 375
AnnaBridge 171:3a7713b1edbc 376 /** @} End of group EFM32GG990F512_Peripheral_Base */
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 379 * @defgroup EFM32GG990F512_Peripheral_Declaration EFM32GG990F512 Peripheral Declarations
AnnaBridge 171:3a7713b1edbc 380 * @{
AnnaBridge 171:3a7713b1edbc 381 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 382
AnnaBridge 171:3a7713b1edbc 383 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
AnnaBridge 171:3a7713b1edbc 384 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
AnnaBridge 171:3a7713b1edbc 385 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
AnnaBridge 171:3a7713b1edbc 386 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
AnnaBridge 171:3a7713b1edbc 387 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
AnnaBridge 171:3a7713b1edbc 388 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
AnnaBridge 171:3a7713b1edbc 389 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
AnnaBridge 171:3a7713b1edbc 390 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
AnnaBridge 171:3a7713b1edbc 391 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
AnnaBridge 171:3a7713b1edbc 392 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
AnnaBridge 171:3a7713b1edbc 393 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
AnnaBridge 171:3a7713b1edbc 394 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
AnnaBridge 171:3a7713b1edbc 395 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
AnnaBridge 171:3a7713b1edbc 396 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
AnnaBridge 171:3a7713b1edbc 397 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
AnnaBridge 171:3a7713b1edbc 398 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
AnnaBridge 171:3a7713b1edbc 399 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
AnnaBridge 171:3a7713b1edbc 400 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
AnnaBridge 171:3a7713b1edbc 401 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
AnnaBridge 171:3a7713b1edbc 402 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
AnnaBridge 171:3a7713b1edbc 403 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 404 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
AnnaBridge 171:3a7713b1edbc 405 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 406 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 407 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
AnnaBridge 171:3a7713b1edbc 408 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
AnnaBridge 171:3a7713b1edbc 409 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
AnnaBridge 171:3a7713b1edbc 410 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
AnnaBridge 171:3a7713b1edbc 411 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
AnnaBridge 171:3a7713b1edbc 412 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
AnnaBridge 171:3a7713b1edbc 413 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
AnnaBridge 171:3a7713b1edbc 414 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
AnnaBridge 171:3a7713b1edbc 415 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 416 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 417 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
AnnaBridge 171:3a7713b1edbc 418 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
AnnaBridge 171:3a7713b1edbc 419 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
AnnaBridge 171:3a7713b1edbc 420 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
AnnaBridge 171:3a7713b1edbc 421 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
AnnaBridge 171:3a7713b1edbc 422 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
AnnaBridge 171:3a7713b1edbc 423 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
AnnaBridge 171:3a7713b1edbc 424
AnnaBridge 171:3a7713b1edbc 425 /** @} End of group EFM32GG990F512_Peripheral_Declaration */
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 428 * @defgroup EFM32GG990F512_BitFields EFM32GG990F512 Bit Fields
AnnaBridge 171:3a7713b1edbc 429 * @{
AnnaBridge 171:3a7713b1edbc 430 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 431
AnnaBridge 171:3a7713b1edbc 432 #include "efm32gg_prs_signals.h"
AnnaBridge 171:3a7713b1edbc 433 #include "efm32gg_dmareq.h"
AnnaBridge 171:3a7713b1edbc 434 #include "efm32gg_dmactrl.h"
AnnaBridge 171:3a7713b1edbc 435 #include "efm32gg_uart.h"
AnnaBridge 171:3a7713b1edbc 436
AnnaBridge 171:3a7713b1edbc 437 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 438 * @defgroup EFM32GG990F512_UNLOCK EFM32GG990F512 Unlock Codes
AnnaBridge 171:3a7713b1edbc 439 * @{
AnnaBridge 171:3a7713b1edbc 440 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 441 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
AnnaBridge 171:3a7713b1edbc 442 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
AnnaBridge 171:3a7713b1edbc 443 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
AnnaBridge 171:3a7713b1edbc 444 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
AnnaBridge 171:3a7713b1edbc 445 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
AnnaBridge 171:3a7713b1edbc 446 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
AnnaBridge 171:3a7713b1edbc 447
AnnaBridge 171:3a7713b1edbc 448 /** @} End of group EFM32GG990F512_UNLOCK */
AnnaBridge 171:3a7713b1edbc 449
AnnaBridge 171:3a7713b1edbc 450 /** @} End of group EFM32GG990F512_BitFields */
AnnaBridge 171:3a7713b1edbc 451
AnnaBridge 171:3a7713b1edbc 452 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 453 * @defgroup EFM32GG990F512_Alternate_Function EFM32GG990F512 Alternate Function
AnnaBridge 171:3a7713b1edbc 454 * @{
AnnaBridge 171:3a7713b1edbc 455 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 456
AnnaBridge 171:3a7713b1edbc 457 #include "efm32gg_af_ports.h"
AnnaBridge 171:3a7713b1edbc 458 #include "efm32gg_af_pins.h"
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 /** @} End of group EFM32GG990F512_Alternate_Function */
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 463 * @brief Set the value of a bit field within a register.
AnnaBridge 171:3a7713b1edbc 464 *
AnnaBridge 171:3a7713b1edbc 465 * @param REG
AnnaBridge 171:3a7713b1edbc 466 * The register to update
AnnaBridge 171:3a7713b1edbc 467 * @param MASK
AnnaBridge 171:3a7713b1edbc 468 * The mask for the bit field to update
AnnaBridge 171:3a7713b1edbc 469 * @param VALUE
AnnaBridge 171:3a7713b1edbc 470 * The value to write to the bit field
AnnaBridge 171:3a7713b1edbc 471 * @param OFFSET
AnnaBridge 171:3a7713b1edbc 472 * The number of bits that the field is offset within the register.
AnnaBridge 171:3a7713b1edbc 473 * 0 (zero) means LSB.
AnnaBridge 171:3a7713b1edbc 474 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 475 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
AnnaBridge 171:3a7713b1edbc 476 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
AnnaBridge 171:3a7713b1edbc 477
AnnaBridge 171:3a7713b1edbc 478 /** @} End of group EFM32GG990F512 */
AnnaBridge 171:3a7713b1edbc 479
AnnaBridge 171:3a7713b1edbc 480 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 481
AnnaBridge 171:3a7713b1edbc 482 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 483 }
AnnaBridge 171:3a7713b1edbc 484 #endif
AnnaBridge 171:3a7713b1edbc 485 #endif /* EFM32GG990F512_H */