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TARGET_EFM32GG_STK3700/TOOLCHAIN_IAR/efm32gg842f1024.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2 * @file efm32gg842f1024.h
AnnaBridge 171:3a7713b1edbc 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
AnnaBridge 171:3a7713b1edbc 4 * for EFM32GG842F1024
AnnaBridge 171:3a7713b1edbc 5 * @version 5.1.2
AnnaBridge 171:3a7713b1edbc 6 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 7 * @section License
AnnaBridge 171:3a7713b1edbc 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 171:3a7713b1edbc 9 ******************************************************************************
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 171:3a7713b1edbc 12 * including commercial applications, and to alter it and redistribute it
AnnaBridge 171:3a7713b1edbc 13 * freely, subject to the following restrictions:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 171:3a7713b1edbc 16 * claim that you wrote the original software.@n
AnnaBridge 171:3a7713b1edbc 17 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 171:3a7713b1edbc 18 * misrepresented as being the original software.@n
AnnaBridge 171:3a7713b1edbc 19 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 171:3a7713b1edbc 20 *
AnnaBridge 171:3a7713b1edbc 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 171:3a7713b1edbc 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 171:3a7713b1edbc 23 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 171:3a7713b1edbc 24 * kind, including, but not limited to, any implied warranties of
AnnaBridge 171:3a7713b1edbc 25 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 171:3a7713b1edbc 26 * infringement of any proprietary rights of a third party.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 171:3a7713b1edbc 29 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 171:3a7713b1edbc 30 * any third party, arising from your use of this Software.
AnnaBridge 171:3a7713b1edbc 31 *
AnnaBridge 171:3a7713b1edbc 32 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 33
AnnaBridge 171:3a7713b1edbc 34 #ifndef EFM32GG842F1024_H
AnnaBridge 171:3a7713b1edbc 35 #define EFM32GG842F1024_H
AnnaBridge 171:3a7713b1edbc 36
AnnaBridge 171:3a7713b1edbc 37 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 38 extern "C" {
AnnaBridge 171:3a7713b1edbc 39 #endif
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 42 * @addtogroup Parts
AnnaBridge 171:3a7713b1edbc 43 * @{
AnnaBridge 171:3a7713b1edbc 44 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 45
AnnaBridge 171:3a7713b1edbc 46 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 47 * @defgroup EFM32GG842F1024 EFM32GG842F1024
AnnaBridge 171:3a7713b1edbc 48 * @{
AnnaBridge 171:3a7713b1edbc 49 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 50
AnnaBridge 171:3a7713b1edbc 51 /** Interrupt Number Definition */
AnnaBridge 171:3a7713b1edbc 52 typedef enum IRQn
AnnaBridge 171:3a7713b1edbc 53 {
AnnaBridge 171:3a7713b1edbc 54 /****** Cortex-M3 Processor Exceptions Numbers ********************************************/
AnnaBridge 171:3a7713b1edbc 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M3 Non Maskable Interrupt */
AnnaBridge 171:3a7713b1edbc 56 HardFault_IRQn = -13, /*!< -13 Cortex-M3 Hard Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M3 Memory Management Interrupt */
AnnaBridge 171:3a7713b1edbc 58 BusFault_IRQn = -11, /*!< -11 Cortex-M3 Bus Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M3 Usage Fault Interrupt */
AnnaBridge 171:3a7713b1edbc 60 SVCall_IRQn = -5, /*!< -5 Cortex-M3 SV Call Interrupt */
AnnaBridge 171:3a7713b1edbc 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M3 Debug Monitor Interrupt */
AnnaBridge 171:3a7713b1edbc 62 PendSV_IRQn = -2, /*!< -2 Cortex-M3 Pend SV Interrupt */
AnnaBridge 171:3a7713b1edbc 63 SysTick_IRQn = -1, /*!< -1 Cortex-M3 System Tick Interrupt */
AnnaBridge 171:3a7713b1edbc 64
AnnaBridge 171:3a7713b1edbc 65 /****** EFM32G Peripheral Interrupt Numbers ***********************************************/
AnnaBridge 171:3a7713b1edbc 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
AnnaBridge 171:3a7713b1edbc 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
AnnaBridge 171:3a7713b1edbc 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
AnnaBridge 171:3a7713b1edbc 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 71 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
AnnaBridge 171:3a7713b1edbc 72 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
AnnaBridge 171:3a7713b1edbc 73 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
AnnaBridge 171:3a7713b1edbc 74 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
AnnaBridge 171:3a7713b1edbc 75 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
AnnaBridge 171:3a7713b1edbc 76 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
AnnaBridge 171:3a7713b1edbc 77 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
AnnaBridge 171:3a7713b1edbc 78 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
AnnaBridge 171:3a7713b1edbc 79 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
AnnaBridge 171:3a7713b1edbc 80 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 81 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 82 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
AnnaBridge 171:3a7713b1edbc 83 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
AnnaBridge 171:3a7713b1edbc 84 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
AnnaBridge 171:3a7713b1edbc 85 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
AnnaBridge 171:3a7713b1edbc 86 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
AnnaBridge 171:3a7713b1edbc 87 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
AnnaBridge 171:3a7713b1edbc 88 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
AnnaBridge 171:3a7713b1edbc 89 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
AnnaBridge 171:3a7713b1edbc 90 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
AnnaBridge 171:3a7713b1edbc 91 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
AnnaBridge 171:3a7713b1edbc 92 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
AnnaBridge 171:3a7713b1edbc 93 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
AnnaBridge 171:3a7713b1edbc 94 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
AnnaBridge 171:3a7713b1edbc 95 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
AnnaBridge 171:3a7713b1edbc 96 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
AnnaBridge 171:3a7713b1edbc 97 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
AnnaBridge 171:3a7713b1edbc 98 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
AnnaBridge 171:3a7713b1edbc 99 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 102 * @defgroup EFM32GG842F1024_Core EFM32GG842F1024 Core
AnnaBridge 171:3a7713b1edbc 103 * @{
AnnaBridge 171:3a7713b1edbc 104 * @brief Processor and Core Peripheral Section
AnnaBridge 171:3a7713b1edbc 105 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 106 #define __MPU_PRESENT 1 /**< Presence of MPU */
AnnaBridge 171:3a7713b1edbc 107 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
AnnaBridge 171:3a7713b1edbc 108 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
AnnaBridge 171:3a7713b1edbc 109 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /** @} End of group EFM32GG842F1024_Core */
AnnaBridge 171:3a7713b1edbc 112
AnnaBridge 171:3a7713b1edbc 113 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 114 * @defgroup EFM32GG842F1024_Part EFM32GG842F1024 Part
AnnaBridge 171:3a7713b1edbc 115 * @{
AnnaBridge 171:3a7713b1edbc 116 ******************************************************************************/
AnnaBridge 171:3a7713b1edbc 117
AnnaBridge 171:3a7713b1edbc 118 /** Part family */
AnnaBridge 171:3a7713b1edbc 119 #define _EFM32_GIANT_FAMILY 1 /**< Giant/Leopard Gecko EFM32LG/GG MCU Family */
AnnaBridge 171:3a7713b1edbc 120 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
AnnaBridge 171:3a7713b1edbc 121 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
AnnaBridge 171:3a7713b1edbc 122 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
AnnaBridge 171:3a7713b1edbc 123 #define _SILICON_LABS_GECKO_INTERNAL_SDID 72 /** Silicon Labs internal use only, may change any time */
AnnaBridge 171:3a7713b1edbc 124 #define _SILICON_LABS_GECKO_INTERNAL_SDID_72 /** Silicon Labs internal use only, may change any time */
AnnaBridge 171:3a7713b1edbc 125 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 171:3a7713b1edbc 126 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 /* If part number is not defined as compiler option, define it */
AnnaBridge 171:3a7713b1edbc 129 #if !defined(EFM32GG842F1024)
AnnaBridge 171:3a7713b1edbc 130 #define EFM32GG842F1024 1 /**< Giant/Leopard Gecko Part */
AnnaBridge 171:3a7713b1edbc 131 #endif
AnnaBridge 171:3a7713b1edbc 132
AnnaBridge 171:3a7713b1edbc 133 /** Configure part number */
AnnaBridge 171:3a7713b1edbc 134 #define PART_NUMBER "EFM32GG842F1024" /**< Part Number */
AnnaBridge 171:3a7713b1edbc 135
AnnaBridge 171:3a7713b1edbc 136 /** Memory Base addresses and limits */
AnnaBridge 171:3a7713b1edbc 137 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
AnnaBridge 171:3a7713b1edbc 138 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
AnnaBridge 171:3a7713b1edbc 139 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
AnnaBridge 171:3a7713b1edbc 140 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
AnnaBridge 171:3a7713b1edbc 141 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
AnnaBridge 171:3a7713b1edbc 142 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
AnnaBridge 171:3a7713b1edbc 143 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
AnnaBridge 171:3a7713b1edbc 144 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
AnnaBridge 171:3a7713b1edbc 145 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
AnnaBridge 171:3a7713b1edbc 146 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
AnnaBridge 171:3a7713b1edbc 147 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
AnnaBridge 171:3a7713b1edbc 148 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
AnnaBridge 171:3a7713b1edbc 149 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
AnnaBridge 171:3a7713b1edbc 150 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
AnnaBridge 171:3a7713b1edbc 151 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
AnnaBridge 171:3a7713b1edbc 152 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
AnnaBridge 171:3a7713b1edbc 153 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
AnnaBridge 171:3a7713b1edbc 154 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
AnnaBridge 171:3a7713b1edbc 155 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
AnnaBridge 171:3a7713b1edbc 156 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
AnnaBridge 171:3a7713b1edbc 157 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
AnnaBridge 171:3a7713b1edbc 158 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
AnnaBridge 171:3a7713b1edbc 159 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
AnnaBridge 171:3a7713b1edbc 160 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
AnnaBridge 171:3a7713b1edbc 161 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
AnnaBridge 171:3a7713b1edbc 162 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
AnnaBridge 171:3a7713b1edbc 163 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
AnnaBridge 171:3a7713b1edbc 164 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
AnnaBridge 171:3a7713b1edbc 165 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
AnnaBridge 171:3a7713b1edbc 166 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
AnnaBridge 171:3a7713b1edbc 167 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
AnnaBridge 171:3a7713b1edbc 168 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170 /** Bit banding area */
AnnaBridge 171:3a7713b1edbc 171 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
AnnaBridge 171:3a7713b1edbc 172 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
AnnaBridge 171:3a7713b1edbc 173
AnnaBridge 171:3a7713b1edbc 174 /** Flash and SRAM limits for EFM32GG842F1024 */
AnnaBridge 171:3a7713b1edbc 175 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
AnnaBridge 171:3a7713b1edbc 176 #define FLASH_SIZE (0x00100000UL) /**< Available Flash Memory */
AnnaBridge 171:3a7713b1edbc 177 #define FLASH_PAGE_SIZE 4096 /**< Flash Memory page size */
AnnaBridge 171:3a7713b1edbc 178 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
AnnaBridge 171:3a7713b1edbc 179 #define SRAM_SIZE (0x00020000UL) /**< Available SRAM Memory */
AnnaBridge 171:3a7713b1edbc 180 #define __CM3_REV 0x201 /**< Cortex-M3 Core revision r2p1 */
AnnaBridge 171:3a7713b1edbc 181 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
AnnaBridge 171:3a7713b1edbc 182 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
AnnaBridge 171:3a7713b1edbc 183 #define EXT_IRQ_COUNT 39 /**< Number of External (NVIC) interrupts */
AnnaBridge 171:3a7713b1edbc 184
AnnaBridge 171:3a7713b1edbc 185 /** AF channels connect the different on-chip peripherals with the af-mux */
AnnaBridge 171:3a7713b1edbc 186 #define AFCHAN_MAX 163
AnnaBridge 171:3a7713b1edbc 187 #define AFCHANLOC_MAX 7
AnnaBridge 171:3a7713b1edbc 188 /** Analog AF channels */
AnnaBridge 171:3a7713b1edbc 189 #define AFACHAN_MAX 53
AnnaBridge 171:3a7713b1edbc 190
AnnaBridge 171:3a7713b1edbc 191 /* Part number capabilities */
AnnaBridge 171:3a7713b1edbc 192
AnnaBridge 171:3a7713b1edbc 193 #define LETIMER_PRESENT /**< LETIMER is available in this part */
AnnaBridge 171:3a7713b1edbc 194 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
AnnaBridge 171:3a7713b1edbc 195 #define USART_PRESENT /**< USART is available in this part */
AnnaBridge 171:3a7713b1edbc 196 #define USART_COUNT 3 /**< 3 USARTs available */
AnnaBridge 171:3a7713b1edbc 197 #define TIMER_PRESENT /**< TIMER is available in this part */
AnnaBridge 171:3a7713b1edbc 198 #define TIMER_COUNT 4 /**< 4 TIMERs available */
AnnaBridge 171:3a7713b1edbc 199 #define ACMP_PRESENT /**< ACMP is available in this part */
AnnaBridge 171:3a7713b1edbc 200 #define ACMP_COUNT 2 /**< 2 ACMPs available */
AnnaBridge 171:3a7713b1edbc 201 #define I2C_PRESENT /**< I2C is available in this part */
AnnaBridge 171:3a7713b1edbc 202 #define I2C_COUNT 2 /**< 2 I2Cs available */
AnnaBridge 171:3a7713b1edbc 203 #define LEUART_PRESENT /**< LEUART is available in this part */
AnnaBridge 171:3a7713b1edbc 204 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
AnnaBridge 171:3a7713b1edbc 205 #define PCNT_PRESENT /**< PCNT is available in this part */
AnnaBridge 171:3a7713b1edbc 206 #define PCNT_COUNT 3 /**< 3 PCNTs available */
AnnaBridge 171:3a7713b1edbc 207 #define ADC_PRESENT /**< ADC is available in this part */
AnnaBridge 171:3a7713b1edbc 208 #define ADC_COUNT 1 /**< 1 ADCs available */
AnnaBridge 171:3a7713b1edbc 209 #define DAC_PRESENT /**< DAC is available in this part */
AnnaBridge 171:3a7713b1edbc 210 #define DAC_COUNT 1 /**< 1 DACs available */
AnnaBridge 171:3a7713b1edbc 211 #define DMA_PRESENT
AnnaBridge 171:3a7713b1edbc 212 #define DMA_COUNT 1
AnnaBridge 171:3a7713b1edbc 213 #define AES_PRESENT
AnnaBridge 171:3a7713b1edbc 214 #define AES_COUNT 1
AnnaBridge 171:3a7713b1edbc 215 #define LE_PRESENT
AnnaBridge 171:3a7713b1edbc 216 #define LE_COUNT 1
AnnaBridge 171:3a7713b1edbc 217 #define MSC_PRESENT
AnnaBridge 171:3a7713b1edbc 218 #define MSC_COUNT 1
AnnaBridge 171:3a7713b1edbc 219 #define EMU_PRESENT
AnnaBridge 171:3a7713b1edbc 220 #define EMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 221 #define RMU_PRESENT
AnnaBridge 171:3a7713b1edbc 222 #define RMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 223 #define CMU_PRESENT
AnnaBridge 171:3a7713b1edbc 224 #define CMU_COUNT 1
AnnaBridge 171:3a7713b1edbc 225 #define LESENSE_PRESENT
AnnaBridge 171:3a7713b1edbc 226 #define LESENSE_COUNT 1
AnnaBridge 171:3a7713b1edbc 227 #define RTC_PRESENT
AnnaBridge 171:3a7713b1edbc 228 #define RTC_COUNT 1
AnnaBridge 171:3a7713b1edbc 229 #define GPIO_PRESENT
AnnaBridge 171:3a7713b1edbc 230 #define GPIO_COUNT 1
AnnaBridge 171:3a7713b1edbc 231 #define VCMP_PRESENT
AnnaBridge 171:3a7713b1edbc 232 #define VCMP_COUNT 1
AnnaBridge 171:3a7713b1edbc 233 #define PRS_PRESENT
AnnaBridge 171:3a7713b1edbc 234 #define PRS_COUNT 1
AnnaBridge 171:3a7713b1edbc 235 #define OPAMP_PRESENT
AnnaBridge 171:3a7713b1edbc 236 #define OPAMP_COUNT 1
AnnaBridge 171:3a7713b1edbc 237 #define BU_PRESENT
AnnaBridge 171:3a7713b1edbc 238 #define BU_COUNT 1
AnnaBridge 171:3a7713b1edbc 239 #define LCD_PRESENT
AnnaBridge 171:3a7713b1edbc 240 #define LCD_COUNT 1
AnnaBridge 171:3a7713b1edbc 241 #define BURTC_PRESENT
AnnaBridge 171:3a7713b1edbc 242 #define BURTC_COUNT 1
AnnaBridge 171:3a7713b1edbc 243 #define HFXTAL_PRESENT
AnnaBridge 171:3a7713b1edbc 244 #define HFXTAL_COUNT 1
AnnaBridge 171:3a7713b1edbc 245 #define LFXTAL_PRESENT
AnnaBridge 171:3a7713b1edbc 246 #define LFXTAL_COUNT 1
AnnaBridge 171:3a7713b1edbc 247 #define WDOG_PRESENT
AnnaBridge 171:3a7713b1edbc 248 #define WDOG_COUNT 1
AnnaBridge 171:3a7713b1edbc 249 #define DBG_PRESENT
AnnaBridge 171:3a7713b1edbc 250 #define DBG_COUNT 1
AnnaBridge 171:3a7713b1edbc 251 #define ETM_PRESENT
AnnaBridge 171:3a7713b1edbc 252 #define ETM_COUNT 1
AnnaBridge 171:3a7713b1edbc 253 #define BOOTLOADER_PRESENT
AnnaBridge 171:3a7713b1edbc 254 #define BOOTLOADER_COUNT 1
AnnaBridge 171:3a7713b1edbc 255 #define ANALOG_PRESENT
AnnaBridge 171:3a7713b1edbc 256 #define ANALOG_COUNT 1
AnnaBridge 171:3a7713b1edbc 257
AnnaBridge 171:3a7713b1edbc 258 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 259 #include "system_efm32gg.h" /* System Header */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 /** @} End of group EFM32GG842F1024_Part */
AnnaBridge 171:3a7713b1edbc 262
AnnaBridge 171:3a7713b1edbc 263 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 264 * @defgroup EFM32GG842F1024_Peripheral_TypeDefs EFM32GG842F1024 Peripheral TypeDefs
AnnaBridge 171:3a7713b1edbc 265 * @{
AnnaBridge 171:3a7713b1edbc 266 * @brief Device Specific Peripheral Register Structures
AnnaBridge 171:3a7713b1edbc 267 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 #include "efm32gg_dma_ch.h"
AnnaBridge 171:3a7713b1edbc 270
AnnaBridge 171:3a7713b1edbc 271 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 272 * @defgroup EFM32GG842F1024_DMA EFM32GG842F1024 DMA
AnnaBridge 171:3a7713b1edbc 273 * @{
AnnaBridge 171:3a7713b1edbc 274 * @brief EFM32GG842F1024_DMA Register Declaration
AnnaBridge 171:3a7713b1edbc 275 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 276 typedef struct
AnnaBridge 171:3a7713b1edbc 277 {
AnnaBridge 171:3a7713b1edbc 278 __IM uint32_t STATUS; /**< DMA Status Registers */
AnnaBridge 171:3a7713b1edbc 279 __OM uint32_t CONFIG; /**< DMA Configuration Register */
AnnaBridge 171:3a7713b1edbc 280 __IOM uint32_t CTRLBASE; /**< Channel Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 281 __IM uint32_t ALTCTRLBASE; /**< Channel Alternate Control Data Base Pointer Register */
AnnaBridge 171:3a7713b1edbc 282 __IM uint32_t CHWAITSTATUS; /**< Channel Wait on Request Status Register */
AnnaBridge 171:3a7713b1edbc 283 __OM uint32_t CHSWREQ; /**< Channel Software Request Register */
AnnaBridge 171:3a7713b1edbc 284 __IOM uint32_t CHUSEBURSTS; /**< Channel Useburst Set Register */
AnnaBridge 171:3a7713b1edbc 285 __OM uint32_t CHUSEBURSTC; /**< Channel Useburst Clear Register */
AnnaBridge 171:3a7713b1edbc 286 __IOM uint32_t CHREQMASKS; /**< Channel Request Mask Set Register */
AnnaBridge 171:3a7713b1edbc 287 __OM uint32_t CHREQMASKC; /**< Channel Request Mask Clear Register */
AnnaBridge 171:3a7713b1edbc 288 __IOM uint32_t CHENS; /**< Channel Enable Set Register */
AnnaBridge 171:3a7713b1edbc 289 __OM uint32_t CHENC; /**< Channel Enable Clear Register */
AnnaBridge 171:3a7713b1edbc 290 __IOM uint32_t CHALTS; /**< Channel Alternate Set Register */
AnnaBridge 171:3a7713b1edbc 291 __OM uint32_t CHALTC; /**< Channel Alternate Clear Register */
AnnaBridge 171:3a7713b1edbc 292 __IOM uint32_t CHPRIS; /**< Channel Priority Set Register */
AnnaBridge 171:3a7713b1edbc 293 __OM uint32_t CHPRIC; /**< Channel Priority Clear Register */
AnnaBridge 171:3a7713b1edbc 294 uint32_t RESERVED0[3]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 295 __IOM uint32_t ERRORC; /**< Bus Error Clear Register */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 uint32_t RESERVED1[880]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 298 __IM uint32_t CHREQSTATUS; /**< Channel Request Status */
AnnaBridge 171:3a7713b1edbc 299 uint32_t RESERVED2[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 300 __IM uint32_t CHSREQSTATUS; /**< Channel Single Request Status */
AnnaBridge 171:3a7713b1edbc 301
AnnaBridge 171:3a7713b1edbc 302 uint32_t RESERVED3[121]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 303 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 304 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 305 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 306 __IOM uint32_t IEN; /**< Interrupt Enable register */
AnnaBridge 171:3a7713b1edbc 307 __IOM uint32_t CTRL; /**< DMA Control Register */
AnnaBridge 171:3a7713b1edbc 308 __IOM uint32_t RDS; /**< DMA Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 309
AnnaBridge 171:3a7713b1edbc 310 uint32_t RESERVED4[2]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 311 __IOM uint32_t LOOP0; /**< Channel 0 Loop Register */
AnnaBridge 171:3a7713b1edbc 312 __IOM uint32_t LOOP1; /**< Channel 1 Loop Register */
AnnaBridge 171:3a7713b1edbc 313 uint32_t RESERVED5[14]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 314 __IOM uint32_t RECT0; /**< Channel 0 Rectangle Register */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 uint32_t RESERVED6[39]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 317 DMA_CH_TypeDef CH[12]; /**< Channel registers */
AnnaBridge 171:3a7713b1edbc 318 } DMA_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 319
AnnaBridge 171:3a7713b1edbc 320 #include "efm32gg_aes.h"
AnnaBridge 171:3a7713b1edbc 321 #include "efm32gg_msc.h"
AnnaBridge 171:3a7713b1edbc 322 #include "efm32gg_emu.h"
AnnaBridge 171:3a7713b1edbc 323 #include "efm32gg_rmu.h"
AnnaBridge 171:3a7713b1edbc 324
AnnaBridge 171:3a7713b1edbc 325 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 326 * @defgroup EFM32GG842F1024_CMU EFM32GG842F1024 CMU
AnnaBridge 171:3a7713b1edbc 327 * @{
AnnaBridge 171:3a7713b1edbc 328 * @brief EFM32GG842F1024_CMU Register Declaration
AnnaBridge 171:3a7713b1edbc 329 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 330 typedef struct
AnnaBridge 171:3a7713b1edbc 331 {
AnnaBridge 171:3a7713b1edbc 332 __IOM uint32_t CTRL; /**< CMU Control Register */
AnnaBridge 171:3a7713b1edbc 333 __IOM uint32_t HFCORECLKDIV; /**< High Frequency Core Clock Division Register */
AnnaBridge 171:3a7713b1edbc 334 __IOM uint32_t HFPERCLKDIV; /**< High Frequency Peripheral Clock Division Register */
AnnaBridge 171:3a7713b1edbc 335 __IOM uint32_t HFRCOCTRL; /**< HFRCO Control Register */
AnnaBridge 171:3a7713b1edbc 336 __IOM uint32_t LFRCOCTRL; /**< LFRCO Control Register */
AnnaBridge 171:3a7713b1edbc 337 __IOM uint32_t AUXHFRCOCTRL; /**< AUXHFRCO Control Register */
AnnaBridge 171:3a7713b1edbc 338 __IOM uint32_t CALCTRL; /**< Calibration Control Register */
AnnaBridge 171:3a7713b1edbc 339 __IOM uint32_t CALCNT; /**< Calibration Counter Register */
AnnaBridge 171:3a7713b1edbc 340 __IOM uint32_t OSCENCMD; /**< Oscillator Enable/Disable Command Register */
AnnaBridge 171:3a7713b1edbc 341 __IOM uint32_t CMD; /**< Command Register */
AnnaBridge 171:3a7713b1edbc 342 __IOM uint32_t LFCLKSEL; /**< Low Frequency Clock Select Register */
AnnaBridge 171:3a7713b1edbc 343 __IM uint32_t STATUS; /**< Status Register */
AnnaBridge 171:3a7713b1edbc 344 __IM uint32_t IF; /**< Interrupt Flag Register */
AnnaBridge 171:3a7713b1edbc 345 __IOM uint32_t IFS; /**< Interrupt Flag Set Register */
AnnaBridge 171:3a7713b1edbc 346 __IOM uint32_t IFC; /**< Interrupt Flag Clear Register */
AnnaBridge 171:3a7713b1edbc 347 __IOM uint32_t IEN; /**< Interrupt Enable Register */
AnnaBridge 171:3a7713b1edbc 348 __IOM uint32_t HFCORECLKEN0; /**< High Frequency Core Clock Enable Register 0 */
AnnaBridge 171:3a7713b1edbc 349 __IOM uint32_t HFPERCLKEN0; /**< High Frequency Peripheral Clock Enable Register 0 */
AnnaBridge 171:3a7713b1edbc 350 uint32_t RESERVED0[2]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 351 __IM uint32_t SYNCBUSY; /**< Synchronization Busy Register */
AnnaBridge 171:3a7713b1edbc 352 __IOM uint32_t FREEZE; /**< Freeze Register */
AnnaBridge 171:3a7713b1edbc 353 __IOM uint32_t LFACLKEN0; /**< Low Frequency A Clock Enable Register 0 (Async Reg) */
AnnaBridge 171:3a7713b1edbc 354 uint32_t RESERVED1[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 355 __IOM uint32_t LFBCLKEN0; /**< Low Frequency B Clock Enable Register 0 (Async Reg) */
AnnaBridge 171:3a7713b1edbc 356
AnnaBridge 171:3a7713b1edbc 357 uint32_t RESERVED2[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 358 __IOM uint32_t LFAPRESC0; /**< Low Frequency A Prescaler Register 0 (Async Reg) */
AnnaBridge 171:3a7713b1edbc 359 uint32_t RESERVED3[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 360 __IOM uint32_t LFBPRESC0; /**< Low Frequency B Prescaler Register 0 (Async Reg) */
AnnaBridge 171:3a7713b1edbc 361 uint32_t RESERVED4[1]; /**< Reserved for future use **/
AnnaBridge 171:3a7713b1edbc 362 __IOM uint32_t PCNTCTRL; /**< PCNT Control Register */
AnnaBridge 171:3a7713b1edbc 363 __IOM uint32_t LCDCTRL; /**< LCD Control Register */
AnnaBridge 171:3a7713b1edbc 364 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 365 __IOM uint32_t LOCK; /**< Configuration Lock Register */
AnnaBridge 171:3a7713b1edbc 366 } CMU_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368 #include "efm32gg_lesense_st.h"
AnnaBridge 171:3a7713b1edbc 369 #include "efm32gg_lesense_buf.h"
AnnaBridge 171:3a7713b1edbc 370 #include "efm32gg_lesense_ch.h"
AnnaBridge 171:3a7713b1edbc 371 #include "efm32gg_lesense.h"
AnnaBridge 171:3a7713b1edbc 372 #include "efm32gg_rtc.h"
AnnaBridge 171:3a7713b1edbc 373 #include "efm32gg_letimer.h"
AnnaBridge 171:3a7713b1edbc 374 #include "efm32gg_usart.h"
AnnaBridge 171:3a7713b1edbc 375 #include "efm32gg_timer_cc.h"
AnnaBridge 171:3a7713b1edbc 376 #include "efm32gg_timer.h"
AnnaBridge 171:3a7713b1edbc 377 #include "efm32gg_acmp.h"
AnnaBridge 171:3a7713b1edbc 378 #include "efm32gg_i2c.h"
AnnaBridge 171:3a7713b1edbc 379 #include "efm32gg_gpio_p.h"
AnnaBridge 171:3a7713b1edbc 380 #include "efm32gg_gpio.h"
AnnaBridge 171:3a7713b1edbc 381 #include "efm32gg_vcmp.h"
AnnaBridge 171:3a7713b1edbc 382 #include "efm32gg_prs_ch.h"
AnnaBridge 171:3a7713b1edbc 383
AnnaBridge 171:3a7713b1edbc 384 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 385 * @defgroup EFM32GG842F1024_PRS EFM32GG842F1024 PRS
AnnaBridge 171:3a7713b1edbc 386 * @{
AnnaBridge 171:3a7713b1edbc 387 * @brief EFM32GG842F1024_PRS Register Declaration
AnnaBridge 171:3a7713b1edbc 388 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 389 typedef struct
AnnaBridge 171:3a7713b1edbc 390 {
AnnaBridge 171:3a7713b1edbc 391 __IOM uint32_t SWPULSE; /**< Software Pulse Register */
AnnaBridge 171:3a7713b1edbc 392 __IOM uint32_t SWLEVEL; /**< Software Level Register */
AnnaBridge 171:3a7713b1edbc 393 __IOM uint32_t ROUTE; /**< I/O Routing Register */
AnnaBridge 171:3a7713b1edbc 394
AnnaBridge 171:3a7713b1edbc 395 uint32_t RESERVED0[1]; /**< Reserved registers */
AnnaBridge 171:3a7713b1edbc 396 PRS_CH_TypeDef CH[12]; /**< Channel registers */
AnnaBridge 171:3a7713b1edbc 397 } PRS_TypeDef; /** @} */
AnnaBridge 171:3a7713b1edbc 398
AnnaBridge 171:3a7713b1edbc 399 #include "efm32gg_leuart.h"
AnnaBridge 171:3a7713b1edbc 400 #include "efm32gg_pcnt.h"
AnnaBridge 171:3a7713b1edbc 401 #include "efm32gg_adc.h"
AnnaBridge 171:3a7713b1edbc 402 #include "efm32gg_dac.h"
AnnaBridge 171:3a7713b1edbc 403 #include "efm32gg_lcd.h"
AnnaBridge 171:3a7713b1edbc 404 #include "efm32gg_burtc_ret.h"
AnnaBridge 171:3a7713b1edbc 405 #include "efm32gg_burtc.h"
AnnaBridge 171:3a7713b1edbc 406 #include "efm32gg_wdog.h"
AnnaBridge 171:3a7713b1edbc 407 #include "efm32gg_etm.h"
AnnaBridge 171:3a7713b1edbc 408 #include "efm32gg_dma_descriptor.h"
AnnaBridge 171:3a7713b1edbc 409 #include "efm32gg_devinfo.h"
AnnaBridge 171:3a7713b1edbc 410 #include "efm32gg_romtable.h"
AnnaBridge 171:3a7713b1edbc 411 #include "efm32gg_calibrate.h"
AnnaBridge 171:3a7713b1edbc 412
AnnaBridge 171:3a7713b1edbc 413 /** @} End of group EFM32GG842F1024_Peripheral_TypeDefs */
AnnaBridge 171:3a7713b1edbc 414
AnnaBridge 171:3a7713b1edbc 415 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 416 * @defgroup EFM32GG842F1024_Peripheral_Base EFM32GG842F1024 Peripheral Memory Map
AnnaBridge 171:3a7713b1edbc 417 * @{
AnnaBridge 171:3a7713b1edbc 418 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 419
AnnaBridge 171:3a7713b1edbc 420 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
AnnaBridge 171:3a7713b1edbc 421 #define AES_BASE (0x400E0000UL) /**< AES base address */
AnnaBridge 171:3a7713b1edbc 422 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
AnnaBridge 171:3a7713b1edbc 423 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
AnnaBridge 171:3a7713b1edbc 424 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
AnnaBridge 171:3a7713b1edbc 425 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
AnnaBridge 171:3a7713b1edbc 426 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
AnnaBridge 171:3a7713b1edbc 427 #define RTC_BASE (0x40080000UL) /**< RTC base address */
AnnaBridge 171:3a7713b1edbc 428 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
AnnaBridge 171:3a7713b1edbc 429 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
AnnaBridge 171:3a7713b1edbc 430 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
AnnaBridge 171:3a7713b1edbc 431 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
AnnaBridge 171:3a7713b1edbc 432 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
AnnaBridge 171:3a7713b1edbc 433 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
AnnaBridge 171:3a7713b1edbc 434 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
AnnaBridge 171:3a7713b1edbc 435 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
AnnaBridge 171:3a7713b1edbc 436 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
AnnaBridge 171:3a7713b1edbc 437 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
AnnaBridge 171:3a7713b1edbc 438 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
AnnaBridge 171:3a7713b1edbc 439 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
AnnaBridge 171:3a7713b1edbc 440 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
AnnaBridge 171:3a7713b1edbc 441 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
AnnaBridge 171:3a7713b1edbc 442 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
AnnaBridge 171:3a7713b1edbc 443 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
AnnaBridge 171:3a7713b1edbc 444 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
AnnaBridge 171:3a7713b1edbc 445 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
AnnaBridge 171:3a7713b1edbc 446 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
AnnaBridge 171:3a7713b1edbc 447 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
AnnaBridge 171:3a7713b1edbc 448 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
AnnaBridge 171:3a7713b1edbc 449 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
AnnaBridge 171:3a7713b1edbc 450 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
AnnaBridge 171:3a7713b1edbc 451 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
AnnaBridge 171:3a7713b1edbc 452 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
AnnaBridge 171:3a7713b1edbc 453 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
AnnaBridge 171:3a7713b1edbc 454 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
AnnaBridge 171:3a7713b1edbc 455 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
AnnaBridge 171:3a7713b1edbc 456 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
AnnaBridge 171:3a7713b1edbc 457 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
AnnaBridge 171:3a7713b1edbc 458 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 /** @} End of group EFM32GG842F1024_Peripheral_Base */
AnnaBridge 171:3a7713b1edbc 461
AnnaBridge 171:3a7713b1edbc 462 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 463 * @defgroup EFM32GG842F1024_Peripheral_Declaration EFM32GG842F1024 Peripheral Declarations
AnnaBridge 171:3a7713b1edbc 464 * @{
AnnaBridge 171:3a7713b1edbc 465 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 466
AnnaBridge 171:3a7713b1edbc 467 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
AnnaBridge 171:3a7713b1edbc 468 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
AnnaBridge 171:3a7713b1edbc 469 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
AnnaBridge 171:3a7713b1edbc 470 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
AnnaBridge 171:3a7713b1edbc 471 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
AnnaBridge 171:3a7713b1edbc 472 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
AnnaBridge 171:3a7713b1edbc 473 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
AnnaBridge 171:3a7713b1edbc 474 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
AnnaBridge 171:3a7713b1edbc 475 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
AnnaBridge 171:3a7713b1edbc 476 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
AnnaBridge 171:3a7713b1edbc 477 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
AnnaBridge 171:3a7713b1edbc 478 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
AnnaBridge 171:3a7713b1edbc 479 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
AnnaBridge 171:3a7713b1edbc 480 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
AnnaBridge 171:3a7713b1edbc 481 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
AnnaBridge 171:3a7713b1edbc 482 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
AnnaBridge 171:3a7713b1edbc 483 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
AnnaBridge 171:3a7713b1edbc 484 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
AnnaBridge 171:3a7713b1edbc 485 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
AnnaBridge 171:3a7713b1edbc 486 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
AnnaBridge 171:3a7713b1edbc 487 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
AnnaBridge 171:3a7713b1edbc 488 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
AnnaBridge 171:3a7713b1edbc 489 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
AnnaBridge 171:3a7713b1edbc 490 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
AnnaBridge 171:3a7713b1edbc 491 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
AnnaBridge 171:3a7713b1edbc 492 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
AnnaBridge 171:3a7713b1edbc 493 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
AnnaBridge 171:3a7713b1edbc 494 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
AnnaBridge 171:3a7713b1edbc 495 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
AnnaBridge 171:3a7713b1edbc 496 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
AnnaBridge 171:3a7713b1edbc 497 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
AnnaBridge 171:3a7713b1edbc 498 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
AnnaBridge 171:3a7713b1edbc 499 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
AnnaBridge 171:3a7713b1edbc 500 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
AnnaBridge 171:3a7713b1edbc 501 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
AnnaBridge 171:3a7713b1edbc 502 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
AnnaBridge 171:3a7713b1edbc 503 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
AnnaBridge 171:3a7713b1edbc 504
AnnaBridge 171:3a7713b1edbc 505 /** @} End of group EFM32GG842F1024_Peripheral_Declaration */
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 508 * @defgroup EFM32GG842F1024_BitFields EFM32GG842F1024 Bit Fields
AnnaBridge 171:3a7713b1edbc 509 * @{
AnnaBridge 171:3a7713b1edbc 510 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 513 * @addtogroup EFM32GG842F1024_PRS_Signals
AnnaBridge 171:3a7713b1edbc 514 * @{
AnnaBridge 171:3a7713b1edbc 515 * @brief PRS Signal names
AnnaBridge 171:3a7713b1edbc 516 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 517 #define PRS_VCMP_OUT ((1 << 16) + 0) /**< PRS Voltage comparator output */
AnnaBridge 171:3a7713b1edbc 518 #define PRS_ACMP0_OUT ((2 << 16) + 0) /**< PRS Analog comparator output */
AnnaBridge 171:3a7713b1edbc 519 #define PRS_ACMP1_OUT ((3 << 16) + 0) /**< PRS Analog comparator output */
AnnaBridge 171:3a7713b1edbc 520 #define PRS_DAC0_CH0 ((6 << 16) + 0) /**< PRS DAC ch0 conversion done */
AnnaBridge 171:3a7713b1edbc 521 #define PRS_DAC0_CH1 ((6 << 16) + 1) /**< PRS DAC ch1 conversion done */
AnnaBridge 171:3a7713b1edbc 522 #define PRS_ADC0_SINGLE ((8 << 16) + 0) /**< PRS ADC single conversion done */
AnnaBridge 171:3a7713b1edbc 523 #define PRS_ADC0_SCAN ((8 << 16) + 1) /**< PRS ADC scan conversion done */
AnnaBridge 171:3a7713b1edbc 524 #define PRS_USART0_IRTX ((16 << 16) + 0) /**< PRS USART 0 IRDA out */
AnnaBridge 171:3a7713b1edbc 525 #define PRS_USART0_TXC ((16 << 16) + 1) /**< PRS USART 0 TX complete */
AnnaBridge 171:3a7713b1edbc 526 #define PRS_USART0_RXDATAV ((16 << 16) + 2) /**< PRS USART 0 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 527 #define PRS_USART1_TXC ((17 << 16) + 1) /**< PRS USART 1 TX complete */
AnnaBridge 171:3a7713b1edbc 528 #define PRS_USART1_RXDATAV ((17 << 16) + 2) /**< PRS USART 1 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 529 #define PRS_USART2_TXC ((18 << 16) + 1) /**< PRS USART 2 TX complete */
AnnaBridge 171:3a7713b1edbc 530 #define PRS_USART2_RXDATAV ((18 << 16) + 2) /**< PRS USART 2 RX Data Valid */
AnnaBridge 171:3a7713b1edbc 531 #define PRS_TIMER0_UF ((28 << 16) + 0) /**< PRS Timer 0 Underflow */
AnnaBridge 171:3a7713b1edbc 532 #define PRS_TIMER0_OF ((28 << 16) + 1) /**< PRS Timer 0 Overflow */
AnnaBridge 171:3a7713b1edbc 533 #define PRS_TIMER0_CC0 ((28 << 16) + 2) /**< PRS Timer 0 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 534 #define PRS_TIMER0_CC1 ((28 << 16) + 3) /**< PRS Timer 0 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 535 #define PRS_TIMER0_CC2 ((28 << 16) + 4) /**< PRS Timer 0 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 536 #define PRS_TIMER1_UF ((29 << 16) + 0) /**< PRS Timer 1 Underflow */
AnnaBridge 171:3a7713b1edbc 537 #define PRS_TIMER1_OF ((29 << 16) + 1) /**< PRS Timer 1 Overflow */
AnnaBridge 171:3a7713b1edbc 538 #define PRS_TIMER1_CC0 ((29 << 16) + 2) /**< PRS Timer 1 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 539 #define PRS_TIMER1_CC1 ((29 << 16) + 3) /**< PRS Timer 1 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 540 #define PRS_TIMER1_CC2 ((29 << 16) + 4) /**< PRS Timer 1 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 541 #define PRS_TIMER2_UF ((30 << 16) + 0) /**< PRS Timer 2 Underflow */
AnnaBridge 171:3a7713b1edbc 542 #define PRS_TIMER2_OF ((30 << 16) + 1) /**< PRS Timer 2 Overflow */
AnnaBridge 171:3a7713b1edbc 543 #define PRS_TIMER2_CC0 ((30 << 16) + 2) /**< PRS Timer 2 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 544 #define PRS_TIMER2_CC1 ((30 << 16) + 3) /**< PRS Timer 2 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 545 #define PRS_TIMER2_CC2 ((30 << 16) + 4) /**< PRS Timer 2 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 546 #define PRS_TIMER3_UF ((31 << 16) + 0) /**< PRS Timer 3 Underflow */
AnnaBridge 171:3a7713b1edbc 547 #define PRS_TIMER3_OF ((31 << 16) + 1) /**< PRS Timer 3 Overflow */
AnnaBridge 171:3a7713b1edbc 548 #define PRS_TIMER3_CC0 ((31 << 16) + 2) /**< PRS Timer 3 Compare/Capture 0 */
AnnaBridge 171:3a7713b1edbc 549 #define PRS_TIMER3_CC1 ((31 << 16) + 3) /**< PRS Timer 3 Compare/Capture 1 */
AnnaBridge 171:3a7713b1edbc 550 #define PRS_TIMER3_CC2 ((31 << 16) + 4) /**< PRS Timer 3 Compare/Capture 2 */
AnnaBridge 171:3a7713b1edbc 551 #define PRS_RTC_OF ((40 << 16) + 0) /**< PRS RTC Overflow */
AnnaBridge 171:3a7713b1edbc 552 #define PRS_RTC_COMP0 ((40 << 16) + 1) /**< PRS RTC Compare 0 */
AnnaBridge 171:3a7713b1edbc 553 #define PRS_RTC_COMP1 ((40 << 16) + 2) /**< PRS RTC Compare 1 */
AnnaBridge 171:3a7713b1edbc 554 #define PRS_GPIO_PIN0 ((48 << 16) + 0) /**< PRS GPIO pin 0 */
AnnaBridge 171:3a7713b1edbc 555 #define PRS_GPIO_PIN1 ((48 << 16) + 1) /**< PRS GPIO pin 1 */
AnnaBridge 171:3a7713b1edbc 556 #define PRS_GPIO_PIN2 ((48 << 16) + 2) /**< PRS GPIO pin 2 */
AnnaBridge 171:3a7713b1edbc 557 #define PRS_GPIO_PIN3 ((48 << 16) + 3) /**< PRS GPIO pin 3 */
AnnaBridge 171:3a7713b1edbc 558 #define PRS_GPIO_PIN4 ((48 << 16) + 4) /**< PRS GPIO pin 4 */
AnnaBridge 171:3a7713b1edbc 559 #define PRS_GPIO_PIN5 ((48 << 16) + 5) /**< PRS GPIO pin 5 */
AnnaBridge 171:3a7713b1edbc 560 #define PRS_GPIO_PIN6 ((48 << 16) + 6) /**< PRS GPIO pin 6 */
AnnaBridge 171:3a7713b1edbc 561 #define PRS_GPIO_PIN7 ((48 << 16) + 7) /**< PRS GPIO pin 7 */
AnnaBridge 171:3a7713b1edbc 562 #define PRS_GPIO_PIN8 ((49 << 16) + 0) /**< PRS GPIO pin 8 */
AnnaBridge 171:3a7713b1edbc 563 #define PRS_GPIO_PIN9 ((49 << 16) + 1) /**< PRS GPIO pin 9 */
AnnaBridge 171:3a7713b1edbc 564 #define PRS_GPIO_PIN10 ((49 << 16) + 2) /**< PRS GPIO pin 10 */
AnnaBridge 171:3a7713b1edbc 565 #define PRS_GPIO_PIN11 ((49 << 16) + 3) /**< PRS GPIO pin 11 */
AnnaBridge 171:3a7713b1edbc 566 #define PRS_GPIO_PIN12 ((49 << 16) + 4) /**< PRS GPIO pin 12 */
AnnaBridge 171:3a7713b1edbc 567 #define PRS_GPIO_PIN13 ((49 << 16) + 5) /**< PRS GPIO pin 13 */
AnnaBridge 171:3a7713b1edbc 568 #define PRS_GPIO_PIN14 ((49 << 16) + 6) /**< PRS GPIO pin 14 */
AnnaBridge 171:3a7713b1edbc 569 #define PRS_GPIO_PIN15 ((49 << 16) + 7) /**< PRS GPIO pin 15 */
AnnaBridge 171:3a7713b1edbc 570 #define PRS_LETIMER0_CH0 ((52 << 16) + 0) /**< PRS LETIMER CH0 Out */
AnnaBridge 171:3a7713b1edbc 571 #define PRS_LETIMER0_CH1 ((52 << 16) + 1) /**< PRS LETIMER CH1 Out */
AnnaBridge 171:3a7713b1edbc 572 #define PRS_BURTC_OF ((55 << 16) + 0) /**< PRS BURTC Overflow */
AnnaBridge 171:3a7713b1edbc 573 #define PRS_BURTC_COMP0 ((55 << 16) + 1) /**< PRS BURTC Compare 0 */
AnnaBridge 171:3a7713b1edbc 574 #define PRS_LESENSE_SCANRES0 ((57 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 0 */
AnnaBridge 171:3a7713b1edbc 575 #define PRS_LESENSE_SCANRES1 ((57 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 1 */
AnnaBridge 171:3a7713b1edbc 576 #define PRS_LESENSE_SCANRES2 ((57 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 2 */
AnnaBridge 171:3a7713b1edbc 577 #define PRS_LESENSE_SCANRES3 ((57 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 3 */
AnnaBridge 171:3a7713b1edbc 578 #define PRS_LESENSE_SCANRES4 ((57 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 4 */
AnnaBridge 171:3a7713b1edbc 579 #define PRS_LESENSE_SCANRES5 ((57 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 5 */
AnnaBridge 171:3a7713b1edbc 580 #define PRS_LESENSE_SCANRES6 ((57 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 6 */
AnnaBridge 171:3a7713b1edbc 581 #define PRS_LESENSE_SCANRES7 ((57 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 7 */
AnnaBridge 171:3a7713b1edbc 582 #define PRS_LESENSE_SCANRES8 ((58 << 16) + 0) /**< PRS LESENSE SCANRES register, bit 8 */
AnnaBridge 171:3a7713b1edbc 583 #define PRS_LESENSE_SCANRES9 ((58 << 16) + 1) /**< PRS LESENSE SCANRES register, bit 9 */
AnnaBridge 171:3a7713b1edbc 584 #define PRS_LESENSE_SCANRES10 ((58 << 16) + 2) /**< PRS LESENSE SCANRES register, bit 10 */
AnnaBridge 171:3a7713b1edbc 585 #define PRS_LESENSE_SCANRES11 ((58 << 16) + 3) /**< PRS LESENSE SCANRES register, bit 11 */
AnnaBridge 171:3a7713b1edbc 586 #define PRS_LESENSE_SCANRES12 ((58 << 16) + 4) /**< PRS LESENSE SCANRES register, bit 12 */
AnnaBridge 171:3a7713b1edbc 587 #define PRS_LESENSE_SCANRES13 ((58 << 16) + 5) /**< PRS LESENSE SCANRES register, bit 13 */
AnnaBridge 171:3a7713b1edbc 588 #define PRS_LESENSE_SCANRES14 ((58 << 16) + 6) /**< PRS LESENSE SCANRES register, bit 14 */
AnnaBridge 171:3a7713b1edbc 589 #define PRS_LESENSE_SCANRES15 ((58 << 16) + 7) /**< PRS LESENSE SCANRES register, bit 15 */
AnnaBridge 171:3a7713b1edbc 590 #define PRS_LESENSE_DEC0 ((59 << 16) + 0) /**< PRS LESENSE Decoder PRS out 0 */
AnnaBridge 171:3a7713b1edbc 591 #define PRS_LESENSE_DEC1 ((59 << 16) + 1) /**< PRS LESENSE Decoder PRS out 1 */
AnnaBridge 171:3a7713b1edbc 592 #define PRS_LESENSE_DEC2 ((59 << 16) + 2) /**< PRS LESENSE Decoder PRS out 2 */
AnnaBridge 171:3a7713b1edbc 593
AnnaBridge 171:3a7713b1edbc 594 /** @} End of group EFM32GG842F1024_PRS */
AnnaBridge 171:3a7713b1edbc 595
AnnaBridge 171:3a7713b1edbc 596 #include "efm32gg_dmareq.h"
AnnaBridge 171:3a7713b1edbc 597 #include "efm32gg_dmactrl.h"
AnnaBridge 171:3a7713b1edbc 598
AnnaBridge 171:3a7713b1edbc 599 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 600 * @defgroup EFM32GG842F1024_DMA_BitFields EFM32GG842F1024_DMA Bit Fields
AnnaBridge 171:3a7713b1edbc 601 * @{
AnnaBridge 171:3a7713b1edbc 602 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 603
AnnaBridge 171:3a7713b1edbc 604 /* Bit fields for DMA STATUS */
AnnaBridge 171:3a7713b1edbc 605 #define _DMA_STATUS_RESETVALUE 0x100B0000UL /**< Default value for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 606 #define _DMA_STATUS_MASK 0x001F00F1UL /**< Mask for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 607 #define DMA_STATUS_EN (0x1UL << 0) /**< DMA Enable Status */
AnnaBridge 171:3a7713b1edbc 608 #define _DMA_STATUS_EN_SHIFT 0 /**< Shift value for DMA_EN */
AnnaBridge 171:3a7713b1edbc 609 #define _DMA_STATUS_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
AnnaBridge 171:3a7713b1edbc 610 #define _DMA_STATUS_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 611 #define DMA_STATUS_EN_DEFAULT (_DMA_STATUS_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 612 #define _DMA_STATUS_STATE_SHIFT 4 /**< Shift value for DMA_STATE */
AnnaBridge 171:3a7713b1edbc 613 #define _DMA_STATUS_STATE_MASK 0xF0UL /**< Bit mask for DMA_STATE */
AnnaBridge 171:3a7713b1edbc 614 #define _DMA_STATUS_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 615 #define _DMA_STATUS_STATE_IDLE 0x00000000UL /**< Mode IDLE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 616 #define _DMA_STATUS_STATE_RDCHCTRLDATA 0x00000001UL /**< Mode RDCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 617 #define _DMA_STATUS_STATE_RDSRCENDPTR 0x00000002UL /**< Mode RDSRCENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 618 #define _DMA_STATUS_STATE_RDDSTENDPTR 0x00000003UL /**< Mode RDDSTENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 619 #define _DMA_STATUS_STATE_RDSRCDATA 0x00000004UL /**< Mode RDSRCDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 620 #define _DMA_STATUS_STATE_WRDSTDATA 0x00000005UL /**< Mode WRDSTDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 621 #define _DMA_STATUS_STATE_WAITREQCLR 0x00000006UL /**< Mode WAITREQCLR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 622 #define _DMA_STATUS_STATE_WRCHCTRLDATA 0x00000007UL /**< Mode WRCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 623 #define _DMA_STATUS_STATE_STALLED 0x00000008UL /**< Mode STALLED for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 624 #define _DMA_STATUS_STATE_DONE 0x00000009UL /**< Mode DONE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 625 #define _DMA_STATUS_STATE_PERSCATTRANS 0x0000000AUL /**< Mode PERSCATTRANS for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 626 #define DMA_STATUS_STATE_DEFAULT (_DMA_STATUS_STATE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 627 #define DMA_STATUS_STATE_IDLE (_DMA_STATUS_STATE_IDLE << 4) /**< Shifted mode IDLE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 628 #define DMA_STATUS_STATE_RDCHCTRLDATA (_DMA_STATUS_STATE_RDCHCTRLDATA << 4) /**< Shifted mode RDCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 629 #define DMA_STATUS_STATE_RDSRCENDPTR (_DMA_STATUS_STATE_RDSRCENDPTR << 4) /**< Shifted mode RDSRCENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 630 #define DMA_STATUS_STATE_RDDSTENDPTR (_DMA_STATUS_STATE_RDDSTENDPTR << 4) /**< Shifted mode RDDSTENDPTR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 631 #define DMA_STATUS_STATE_RDSRCDATA (_DMA_STATUS_STATE_RDSRCDATA << 4) /**< Shifted mode RDSRCDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 632 #define DMA_STATUS_STATE_WRDSTDATA (_DMA_STATUS_STATE_WRDSTDATA << 4) /**< Shifted mode WRDSTDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 633 #define DMA_STATUS_STATE_WAITREQCLR (_DMA_STATUS_STATE_WAITREQCLR << 4) /**< Shifted mode WAITREQCLR for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 634 #define DMA_STATUS_STATE_WRCHCTRLDATA (_DMA_STATUS_STATE_WRCHCTRLDATA << 4) /**< Shifted mode WRCHCTRLDATA for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 635 #define DMA_STATUS_STATE_STALLED (_DMA_STATUS_STATE_STALLED << 4) /**< Shifted mode STALLED for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 636 #define DMA_STATUS_STATE_DONE (_DMA_STATUS_STATE_DONE << 4) /**< Shifted mode DONE for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 637 #define DMA_STATUS_STATE_PERSCATTRANS (_DMA_STATUS_STATE_PERSCATTRANS << 4) /**< Shifted mode PERSCATTRANS for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 638 #define _DMA_STATUS_CHNUM_SHIFT 16 /**< Shift value for DMA_CHNUM */
AnnaBridge 171:3a7713b1edbc 639 #define _DMA_STATUS_CHNUM_MASK 0x1F0000UL /**< Bit mask for DMA_CHNUM */
AnnaBridge 171:3a7713b1edbc 640 #define _DMA_STATUS_CHNUM_DEFAULT 0x0000000BUL /**< Mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 641 #define DMA_STATUS_CHNUM_DEFAULT (_DMA_STATUS_CHNUM_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_STATUS */
AnnaBridge 171:3a7713b1edbc 642
AnnaBridge 171:3a7713b1edbc 643 /* Bit fields for DMA CONFIG */
AnnaBridge 171:3a7713b1edbc 644 #define _DMA_CONFIG_RESETVALUE 0x00000000UL /**< Default value for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 645 #define _DMA_CONFIG_MASK 0x00000021UL /**< Mask for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 646 #define DMA_CONFIG_EN (0x1UL << 0) /**< Enable DMA */
AnnaBridge 171:3a7713b1edbc 647 #define _DMA_CONFIG_EN_SHIFT 0 /**< Shift value for DMA_EN */
AnnaBridge 171:3a7713b1edbc 648 #define _DMA_CONFIG_EN_MASK 0x1UL /**< Bit mask for DMA_EN */
AnnaBridge 171:3a7713b1edbc 649 #define _DMA_CONFIG_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 650 #define DMA_CONFIG_EN_DEFAULT (_DMA_CONFIG_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 651 #define DMA_CONFIG_CHPROT (0x1UL << 5) /**< Channel Protection Control */
AnnaBridge 171:3a7713b1edbc 652 #define _DMA_CONFIG_CHPROT_SHIFT 5 /**< Shift value for DMA_CHPROT */
AnnaBridge 171:3a7713b1edbc 653 #define _DMA_CONFIG_CHPROT_MASK 0x20UL /**< Bit mask for DMA_CHPROT */
AnnaBridge 171:3a7713b1edbc 654 #define _DMA_CONFIG_CHPROT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 655 #define DMA_CONFIG_CHPROT_DEFAULT (_DMA_CONFIG_CHPROT_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CONFIG */
AnnaBridge 171:3a7713b1edbc 656
AnnaBridge 171:3a7713b1edbc 657 /* Bit fields for DMA CTRLBASE */
AnnaBridge 171:3a7713b1edbc 658 #define _DMA_CTRLBASE_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 659 #define _DMA_CTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 660 #define _DMA_CTRLBASE_CTRLBASE_SHIFT 0 /**< Shift value for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 661 #define _DMA_CTRLBASE_CTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 662 #define _DMA_CTRLBASE_CTRLBASE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 663 #define DMA_CTRLBASE_CTRLBASE_DEFAULT (_DMA_CTRLBASE_CTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRLBASE */
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665 /* Bit fields for DMA ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 666 #define _DMA_ALTCTRLBASE_RESETVALUE 0x00000100UL /**< Default value for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 667 #define _DMA_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Mask for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 668 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_SHIFT 0 /**< Shift value for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 669 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_MASK 0xFFFFFFFFUL /**< Bit mask for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 670 #define _DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT 0x00000100UL /**< Mode DEFAULT for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 671 #define DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT (_DMA_ALTCTRLBASE_ALTCTRLBASE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ALTCTRLBASE */
AnnaBridge 171:3a7713b1edbc 672
AnnaBridge 171:3a7713b1edbc 673 /* Bit fields for DMA CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 674 #define _DMA_CHWAITSTATUS_RESETVALUE 0x00000FFFUL /**< Default value for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 675 #define _DMA_CHWAITSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 676 #define DMA_CHWAITSTATUS_CH0WAITSTATUS (0x1UL << 0) /**< Channel 0 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 677 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_SHIFT 0 /**< Shift value for DMA_CH0WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 678 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 679 #define _DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 680 #define DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH0WAITSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 681 #define DMA_CHWAITSTATUS_CH1WAITSTATUS (0x1UL << 1) /**< Channel 1 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 682 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_SHIFT 1 /**< Shift value for DMA_CH1WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 683 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 684 #define _DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 685 #define DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH1WAITSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 686 #define DMA_CHWAITSTATUS_CH2WAITSTATUS (0x1UL << 2) /**< Channel 2 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 687 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_SHIFT 2 /**< Shift value for DMA_CH2WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 688 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 689 #define _DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 690 #define DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH2WAITSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 691 #define DMA_CHWAITSTATUS_CH3WAITSTATUS (0x1UL << 3) /**< Channel 3 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 692 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_SHIFT 3 /**< Shift value for DMA_CH3WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 693 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 694 #define _DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 695 #define DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH3WAITSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 696 #define DMA_CHWAITSTATUS_CH4WAITSTATUS (0x1UL << 4) /**< Channel 4 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 697 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_SHIFT 4 /**< Shift value for DMA_CH4WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 698 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 699 #define _DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 700 #define DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH4WAITSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 701 #define DMA_CHWAITSTATUS_CH5WAITSTATUS (0x1UL << 5) /**< Channel 5 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 702 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_SHIFT 5 /**< Shift value for DMA_CH5WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 703 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 704 #define _DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 705 #define DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH5WAITSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 706 #define DMA_CHWAITSTATUS_CH6WAITSTATUS (0x1UL << 6) /**< Channel 6 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 707 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_SHIFT 6 /**< Shift value for DMA_CH6WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 708 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 709 #define _DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 710 #define DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH6WAITSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 711 #define DMA_CHWAITSTATUS_CH7WAITSTATUS (0x1UL << 7) /**< Channel 7 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 712 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_SHIFT 7 /**< Shift value for DMA_CH7WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 713 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 714 #define _DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 715 #define DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH7WAITSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 716 #define DMA_CHWAITSTATUS_CH8WAITSTATUS (0x1UL << 8) /**< Channel 8 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 717 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_SHIFT 8 /**< Shift value for DMA_CH8WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 718 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 719 #define _DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 720 #define DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH8WAITSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 721 #define DMA_CHWAITSTATUS_CH9WAITSTATUS (0x1UL << 9) /**< Channel 9 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 722 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_SHIFT 9 /**< Shift value for DMA_CH9WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 723 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 724 #define _DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 725 #define DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH9WAITSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 726 #define DMA_CHWAITSTATUS_CH10WAITSTATUS (0x1UL << 10) /**< Channel 10 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 727 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_SHIFT 10 /**< Shift value for DMA_CH10WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 728 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 729 #define _DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 730 #define DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH10WAITSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 731 #define DMA_CHWAITSTATUS_CH11WAITSTATUS (0x1UL << 11) /**< Channel 11 Wait on Request Status */
AnnaBridge 171:3a7713b1edbc 732 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_SHIFT 11 /**< Shift value for DMA_CH11WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 733 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11WAITSTATUS */
AnnaBridge 171:3a7713b1edbc 734 #define _DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT 0x00000001UL /**< Mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 735 #define DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT (_DMA_CHWAITSTATUS_CH11WAITSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHWAITSTATUS */
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737 /* Bit fields for DMA CHSWREQ */
AnnaBridge 171:3a7713b1edbc 738 #define _DMA_CHSWREQ_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 739 #define _DMA_CHSWREQ_MASK 0x00000FFFUL /**< Mask for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 740 #define DMA_CHSWREQ_CH0SWREQ (0x1UL << 0) /**< Channel 0 Software Request */
AnnaBridge 171:3a7713b1edbc 741 #define _DMA_CHSWREQ_CH0SWREQ_SHIFT 0 /**< Shift value for DMA_CH0SWREQ */
AnnaBridge 171:3a7713b1edbc 742 #define _DMA_CHSWREQ_CH0SWREQ_MASK 0x1UL /**< Bit mask for DMA_CH0SWREQ */
AnnaBridge 171:3a7713b1edbc 743 #define _DMA_CHSWREQ_CH0SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 744 #define DMA_CHSWREQ_CH0SWREQ_DEFAULT (_DMA_CHSWREQ_CH0SWREQ_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 745 #define DMA_CHSWREQ_CH1SWREQ (0x1UL << 1) /**< Channel 1 Software Request */
AnnaBridge 171:3a7713b1edbc 746 #define _DMA_CHSWREQ_CH1SWREQ_SHIFT 1 /**< Shift value for DMA_CH1SWREQ */
AnnaBridge 171:3a7713b1edbc 747 #define _DMA_CHSWREQ_CH1SWREQ_MASK 0x2UL /**< Bit mask for DMA_CH1SWREQ */
AnnaBridge 171:3a7713b1edbc 748 #define _DMA_CHSWREQ_CH1SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 749 #define DMA_CHSWREQ_CH1SWREQ_DEFAULT (_DMA_CHSWREQ_CH1SWREQ_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 750 #define DMA_CHSWREQ_CH2SWREQ (0x1UL << 2) /**< Channel 2 Software Request */
AnnaBridge 171:3a7713b1edbc 751 #define _DMA_CHSWREQ_CH2SWREQ_SHIFT 2 /**< Shift value for DMA_CH2SWREQ */
AnnaBridge 171:3a7713b1edbc 752 #define _DMA_CHSWREQ_CH2SWREQ_MASK 0x4UL /**< Bit mask for DMA_CH2SWREQ */
AnnaBridge 171:3a7713b1edbc 753 #define _DMA_CHSWREQ_CH2SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 754 #define DMA_CHSWREQ_CH2SWREQ_DEFAULT (_DMA_CHSWREQ_CH2SWREQ_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 755 #define DMA_CHSWREQ_CH3SWREQ (0x1UL << 3) /**< Channel 3 Software Request */
AnnaBridge 171:3a7713b1edbc 756 #define _DMA_CHSWREQ_CH3SWREQ_SHIFT 3 /**< Shift value for DMA_CH3SWREQ */
AnnaBridge 171:3a7713b1edbc 757 #define _DMA_CHSWREQ_CH3SWREQ_MASK 0x8UL /**< Bit mask for DMA_CH3SWREQ */
AnnaBridge 171:3a7713b1edbc 758 #define _DMA_CHSWREQ_CH3SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 759 #define DMA_CHSWREQ_CH3SWREQ_DEFAULT (_DMA_CHSWREQ_CH3SWREQ_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 760 #define DMA_CHSWREQ_CH4SWREQ (0x1UL << 4) /**< Channel 4 Software Request */
AnnaBridge 171:3a7713b1edbc 761 #define _DMA_CHSWREQ_CH4SWREQ_SHIFT 4 /**< Shift value for DMA_CH4SWREQ */
AnnaBridge 171:3a7713b1edbc 762 #define _DMA_CHSWREQ_CH4SWREQ_MASK 0x10UL /**< Bit mask for DMA_CH4SWREQ */
AnnaBridge 171:3a7713b1edbc 763 #define _DMA_CHSWREQ_CH4SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 764 #define DMA_CHSWREQ_CH4SWREQ_DEFAULT (_DMA_CHSWREQ_CH4SWREQ_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 765 #define DMA_CHSWREQ_CH5SWREQ (0x1UL << 5) /**< Channel 5 Software Request */
AnnaBridge 171:3a7713b1edbc 766 #define _DMA_CHSWREQ_CH5SWREQ_SHIFT 5 /**< Shift value for DMA_CH5SWREQ */
AnnaBridge 171:3a7713b1edbc 767 #define _DMA_CHSWREQ_CH5SWREQ_MASK 0x20UL /**< Bit mask for DMA_CH5SWREQ */
AnnaBridge 171:3a7713b1edbc 768 #define _DMA_CHSWREQ_CH5SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 769 #define DMA_CHSWREQ_CH5SWREQ_DEFAULT (_DMA_CHSWREQ_CH5SWREQ_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 770 #define DMA_CHSWREQ_CH6SWREQ (0x1UL << 6) /**< Channel 6 Software Request */
AnnaBridge 171:3a7713b1edbc 771 #define _DMA_CHSWREQ_CH6SWREQ_SHIFT 6 /**< Shift value for DMA_CH6SWREQ */
AnnaBridge 171:3a7713b1edbc 772 #define _DMA_CHSWREQ_CH6SWREQ_MASK 0x40UL /**< Bit mask for DMA_CH6SWREQ */
AnnaBridge 171:3a7713b1edbc 773 #define _DMA_CHSWREQ_CH6SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 774 #define DMA_CHSWREQ_CH6SWREQ_DEFAULT (_DMA_CHSWREQ_CH6SWREQ_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 775 #define DMA_CHSWREQ_CH7SWREQ (0x1UL << 7) /**< Channel 7 Software Request */
AnnaBridge 171:3a7713b1edbc 776 #define _DMA_CHSWREQ_CH7SWREQ_SHIFT 7 /**< Shift value for DMA_CH7SWREQ */
AnnaBridge 171:3a7713b1edbc 777 #define _DMA_CHSWREQ_CH7SWREQ_MASK 0x80UL /**< Bit mask for DMA_CH7SWREQ */
AnnaBridge 171:3a7713b1edbc 778 #define _DMA_CHSWREQ_CH7SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 779 #define DMA_CHSWREQ_CH7SWREQ_DEFAULT (_DMA_CHSWREQ_CH7SWREQ_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 780 #define DMA_CHSWREQ_CH8SWREQ (0x1UL << 8) /**< Channel 8 Software Request */
AnnaBridge 171:3a7713b1edbc 781 #define _DMA_CHSWREQ_CH8SWREQ_SHIFT 8 /**< Shift value for DMA_CH8SWREQ */
AnnaBridge 171:3a7713b1edbc 782 #define _DMA_CHSWREQ_CH8SWREQ_MASK 0x100UL /**< Bit mask for DMA_CH8SWREQ */
AnnaBridge 171:3a7713b1edbc 783 #define _DMA_CHSWREQ_CH8SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 784 #define DMA_CHSWREQ_CH8SWREQ_DEFAULT (_DMA_CHSWREQ_CH8SWREQ_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 785 #define DMA_CHSWREQ_CH9SWREQ (0x1UL << 9) /**< Channel 9 Software Request */
AnnaBridge 171:3a7713b1edbc 786 #define _DMA_CHSWREQ_CH9SWREQ_SHIFT 9 /**< Shift value for DMA_CH9SWREQ */
AnnaBridge 171:3a7713b1edbc 787 #define _DMA_CHSWREQ_CH9SWREQ_MASK 0x200UL /**< Bit mask for DMA_CH9SWREQ */
AnnaBridge 171:3a7713b1edbc 788 #define _DMA_CHSWREQ_CH9SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 789 #define DMA_CHSWREQ_CH9SWREQ_DEFAULT (_DMA_CHSWREQ_CH9SWREQ_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 790 #define DMA_CHSWREQ_CH10SWREQ (0x1UL << 10) /**< Channel 10 Software Request */
AnnaBridge 171:3a7713b1edbc 791 #define _DMA_CHSWREQ_CH10SWREQ_SHIFT 10 /**< Shift value for DMA_CH10SWREQ */
AnnaBridge 171:3a7713b1edbc 792 #define _DMA_CHSWREQ_CH10SWREQ_MASK 0x400UL /**< Bit mask for DMA_CH10SWREQ */
AnnaBridge 171:3a7713b1edbc 793 #define _DMA_CHSWREQ_CH10SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 794 #define DMA_CHSWREQ_CH10SWREQ_DEFAULT (_DMA_CHSWREQ_CH10SWREQ_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 795 #define DMA_CHSWREQ_CH11SWREQ (0x1UL << 11) /**< Channel 11 Software Request */
AnnaBridge 171:3a7713b1edbc 796 #define _DMA_CHSWREQ_CH11SWREQ_SHIFT 11 /**< Shift value for DMA_CH11SWREQ */
AnnaBridge 171:3a7713b1edbc 797 #define _DMA_CHSWREQ_CH11SWREQ_MASK 0x800UL /**< Bit mask for DMA_CH11SWREQ */
AnnaBridge 171:3a7713b1edbc 798 #define _DMA_CHSWREQ_CH11SWREQ_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 799 #define DMA_CHSWREQ_CH11SWREQ_DEFAULT (_DMA_CHSWREQ_CH11SWREQ_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSWREQ */
AnnaBridge 171:3a7713b1edbc 800
AnnaBridge 171:3a7713b1edbc 801 /* Bit fields for DMA CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 802 #define _DMA_CHUSEBURSTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 803 #define _DMA_CHUSEBURSTS_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 804 #define DMA_CHUSEBURSTS_CH0USEBURSTS (0x1UL << 0) /**< Channel 0 Useburst Set */
AnnaBridge 171:3a7713b1edbc 805 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTS */
AnnaBridge 171:3a7713b1edbc 806 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTS */
AnnaBridge 171:3a7713b1edbc 807 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 808 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST 0x00000000UL /**< Mode SINGLEANDBURST for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 809 #define _DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY 0x00000001UL /**< Mode BURSTONLY for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 810 #define DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH0USEBURSTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 811 #define DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST (_DMA_CHUSEBURSTS_CH0USEBURSTS_SINGLEANDBURST << 0) /**< Shifted mode SINGLEANDBURST for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 812 #define DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY (_DMA_CHUSEBURSTS_CH0USEBURSTS_BURSTONLY << 0) /**< Shifted mode BURSTONLY for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 813 #define DMA_CHUSEBURSTS_CH1USEBURSTS (0x1UL << 1) /**< Channel 1 Useburst Set */
AnnaBridge 171:3a7713b1edbc 814 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTS */
AnnaBridge 171:3a7713b1edbc 815 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTS */
AnnaBridge 171:3a7713b1edbc 816 #define _DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 817 #define DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH1USEBURSTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 818 #define DMA_CHUSEBURSTS_CH2USEBURSTS (0x1UL << 2) /**< Channel 2 Useburst Set */
AnnaBridge 171:3a7713b1edbc 819 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTS */
AnnaBridge 171:3a7713b1edbc 820 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTS */
AnnaBridge 171:3a7713b1edbc 821 #define _DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 822 #define DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH2USEBURSTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 823 #define DMA_CHUSEBURSTS_CH3USEBURSTS (0x1UL << 3) /**< Channel 3 Useburst Set */
AnnaBridge 171:3a7713b1edbc 824 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTS */
AnnaBridge 171:3a7713b1edbc 825 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTS */
AnnaBridge 171:3a7713b1edbc 826 #define _DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 827 #define DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH3USEBURSTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 828 #define DMA_CHUSEBURSTS_CH4USEBURSTS (0x1UL << 4) /**< Channel 4 Useburst Set */
AnnaBridge 171:3a7713b1edbc 829 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTS */
AnnaBridge 171:3a7713b1edbc 830 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTS */
AnnaBridge 171:3a7713b1edbc 831 #define _DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 832 #define DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH4USEBURSTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 833 #define DMA_CHUSEBURSTS_CH5USEBURSTS (0x1UL << 5) /**< Channel 5 Useburst Set */
AnnaBridge 171:3a7713b1edbc 834 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTS */
AnnaBridge 171:3a7713b1edbc 835 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTS */
AnnaBridge 171:3a7713b1edbc 836 #define _DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 837 #define DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH5USEBURSTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 838 #define DMA_CHUSEBURSTS_CH6USEBURSTS (0x1UL << 6) /**< Channel 6 Useburst Set */
AnnaBridge 171:3a7713b1edbc 839 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTS */
AnnaBridge 171:3a7713b1edbc 840 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTS */
AnnaBridge 171:3a7713b1edbc 841 #define _DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 842 #define DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH6USEBURSTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 843 #define DMA_CHUSEBURSTS_CH7USEBURSTS (0x1UL << 7) /**< Channel 7 Useburst Set */
AnnaBridge 171:3a7713b1edbc 844 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTS */
AnnaBridge 171:3a7713b1edbc 845 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTS */
AnnaBridge 171:3a7713b1edbc 846 #define _DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 847 #define DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH7USEBURSTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 848 #define DMA_CHUSEBURSTS_CH8USEBURSTS (0x1UL << 8) /**< Channel 8 Useburst Set */
AnnaBridge 171:3a7713b1edbc 849 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_SHIFT 8 /**< Shift value for DMA_CH8USEBURSTS */
AnnaBridge 171:3a7713b1edbc 850 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_MASK 0x100UL /**< Bit mask for DMA_CH8USEBURSTS */
AnnaBridge 171:3a7713b1edbc 851 #define _DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 852 #define DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH8USEBURSTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 853 #define DMA_CHUSEBURSTS_CH9USEBURSTS (0x1UL << 9) /**< Channel 9 Useburst Set */
AnnaBridge 171:3a7713b1edbc 854 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTS */
AnnaBridge 171:3a7713b1edbc 855 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTS */
AnnaBridge 171:3a7713b1edbc 856 #define _DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 857 #define DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH9USEBURSTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 858 #define DMA_CHUSEBURSTS_CH10USEBURSTS (0x1UL << 10) /**< Channel 10 Useburst Set */
AnnaBridge 171:3a7713b1edbc 859 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTS */
AnnaBridge 171:3a7713b1edbc 860 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTS */
AnnaBridge 171:3a7713b1edbc 861 #define _DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 862 #define DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH10USEBURSTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 863 #define DMA_CHUSEBURSTS_CH11USEBURSTS (0x1UL << 11) /**< Channel 11 Useburst Set */
AnnaBridge 171:3a7713b1edbc 864 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTS */
AnnaBridge 171:3a7713b1edbc 865 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTS */
AnnaBridge 171:3a7713b1edbc 866 #define _DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 867 #define DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT (_DMA_CHUSEBURSTS_CH11USEBURSTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTS */
AnnaBridge 171:3a7713b1edbc 868
AnnaBridge 171:3a7713b1edbc 869 /* Bit fields for DMA CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 870 #define _DMA_CHUSEBURSTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 871 #define _DMA_CHUSEBURSTC_MASK 0x00000FFFUL /**< Mask for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 872 #define DMA_CHUSEBURSTC_CH0USEBURSTC (0x1UL << 0) /**< Channel 0 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 873 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_SHIFT 0 /**< Shift value for DMA_CH0USEBURSTC */
AnnaBridge 171:3a7713b1edbc 874 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_MASK 0x1UL /**< Bit mask for DMA_CH0USEBURSTC */
AnnaBridge 171:3a7713b1edbc 875 #define _DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 876 #define DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH0USEBURSTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 877 #define DMA_CHUSEBURSTC_CH1USEBURSTC (0x1UL << 1) /**< Channel 1 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 878 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_SHIFT 1 /**< Shift value for DMA_CH1USEBURSTC */
AnnaBridge 171:3a7713b1edbc 879 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_MASK 0x2UL /**< Bit mask for DMA_CH1USEBURSTC */
AnnaBridge 171:3a7713b1edbc 880 #define _DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 881 #define DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH1USEBURSTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 882 #define DMA_CHUSEBURSTC_CH2USEBURSTC (0x1UL << 2) /**< Channel 2 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 883 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_SHIFT 2 /**< Shift value for DMA_CH2USEBURSTC */
AnnaBridge 171:3a7713b1edbc 884 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_MASK 0x4UL /**< Bit mask for DMA_CH2USEBURSTC */
AnnaBridge 171:3a7713b1edbc 885 #define _DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 886 #define DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH2USEBURSTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 887 #define DMA_CHUSEBURSTC_CH3USEBURSTC (0x1UL << 3) /**< Channel 3 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 888 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_SHIFT 3 /**< Shift value for DMA_CH3USEBURSTC */
AnnaBridge 171:3a7713b1edbc 889 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_MASK 0x8UL /**< Bit mask for DMA_CH3USEBURSTC */
AnnaBridge 171:3a7713b1edbc 890 #define _DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 891 #define DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH3USEBURSTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 892 #define DMA_CHUSEBURSTC_CH4USEBURSTC (0x1UL << 4) /**< Channel 4 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 893 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_SHIFT 4 /**< Shift value for DMA_CH4USEBURSTC */
AnnaBridge 171:3a7713b1edbc 894 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_MASK 0x10UL /**< Bit mask for DMA_CH4USEBURSTC */
AnnaBridge 171:3a7713b1edbc 895 #define _DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 896 #define DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH4USEBURSTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 897 #define DMA_CHUSEBURSTC_CH5USEBURSTC (0x1UL << 5) /**< Channel 5 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 898 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_SHIFT 5 /**< Shift value for DMA_CH5USEBURSTC */
AnnaBridge 171:3a7713b1edbc 899 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_MASK 0x20UL /**< Bit mask for DMA_CH5USEBURSTC */
AnnaBridge 171:3a7713b1edbc 900 #define _DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 901 #define DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH5USEBURSTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 902 #define DMA_CHUSEBURSTC_CH6USEBURSTC (0x1UL << 6) /**< Channel 6 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 903 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_SHIFT 6 /**< Shift value for DMA_CH6USEBURSTC */
AnnaBridge 171:3a7713b1edbc 904 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_MASK 0x40UL /**< Bit mask for DMA_CH6USEBURSTC */
AnnaBridge 171:3a7713b1edbc 905 #define _DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 906 #define DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH6USEBURSTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 907 #define DMA_CHUSEBURSTC_CH7USEBURSTC (0x1UL << 7) /**< Channel 7 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 908 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_SHIFT 7 /**< Shift value for DMA_CH7USEBURSTC */
AnnaBridge 171:3a7713b1edbc 909 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_MASK 0x80UL /**< Bit mask for DMA_CH7USEBURSTC */
AnnaBridge 171:3a7713b1edbc 910 #define _DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 911 #define DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH7USEBURSTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 912 #define DMA_CHUSEBURSTC_CH08USEBURSTC (0x1UL << 8) /**< Channel 8 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 913 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_SHIFT 8 /**< Shift value for DMA_CH08USEBURSTC */
AnnaBridge 171:3a7713b1edbc 914 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_MASK 0x100UL /**< Bit mask for DMA_CH08USEBURSTC */
AnnaBridge 171:3a7713b1edbc 915 #define _DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 916 #define DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH08USEBURSTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 917 #define DMA_CHUSEBURSTC_CH9USEBURSTC (0x1UL << 9) /**< Channel 9 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 918 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_SHIFT 9 /**< Shift value for DMA_CH9USEBURSTC */
AnnaBridge 171:3a7713b1edbc 919 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_MASK 0x200UL /**< Bit mask for DMA_CH9USEBURSTC */
AnnaBridge 171:3a7713b1edbc 920 #define _DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 921 #define DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH9USEBURSTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 922 #define DMA_CHUSEBURSTC_CH10USEBURSTC (0x1UL << 10) /**< Channel 10 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 923 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_SHIFT 10 /**< Shift value for DMA_CH10USEBURSTC */
AnnaBridge 171:3a7713b1edbc 924 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_MASK 0x400UL /**< Bit mask for DMA_CH10USEBURSTC */
AnnaBridge 171:3a7713b1edbc 925 #define _DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 926 #define DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH10USEBURSTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 927 #define DMA_CHUSEBURSTC_CH11USEBURSTC (0x1UL << 11) /**< Channel 11 Useburst Clear */
AnnaBridge 171:3a7713b1edbc 928 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_SHIFT 11 /**< Shift value for DMA_CH11USEBURSTC */
AnnaBridge 171:3a7713b1edbc 929 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_MASK 0x800UL /**< Bit mask for DMA_CH11USEBURSTC */
AnnaBridge 171:3a7713b1edbc 930 #define _DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 931 #define DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT (_DMA_CHUSEBURSTC_CH11USEBURSTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHUSEBURSTC */
AnnaBridge 171:3a7713b1edbc 932
AnnaBridge 171:3a7713b1edbc 933 /* Bit fields for DMA CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 934 #define _DMA_CHREQMASKS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 935 #define _DMA_CHREQMASKS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 936 #define DMA_CHREQMASKS_CH0REQMASKS (0x1UL << 0) /**< Channel 0 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 937 #define _DMA_CHREQMASKS_CH0REQMASKS_SHIFT 0 /**< Shift value for DMA_CH0REQMASKS */
AnnaBridge 171:3a7713b1edbc 938 #define _DMA_CHREQMASKS_CH0REQMASKS_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKS */
AnnaBridge 171:3a7713b1edbc 939 #define _DMA_CHREQMASKS_CH0REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 940 #define DMA_CHREQMASKS_CH0REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH0REQMASKS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 941 #define DMA_CHREQMASKS_CH1REQMASKS (0x1UL << 1) /**< Channel 1 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 942 #define _DMA_CHREQMASKS_CH1REQMASKS_SHIFT 1 /**< Shift value for DMA_CH1REQMASKS */
AnnaBridge 171:3a7713b1edbc 943 #define _DMA_CHREQMASKS_CH1REQMASKS_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKS */
AnnaBridge 171:3a7713b1edbc 944 #define _DMA_CHREQMASKS_CH1REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 945 #define DMA_CHREQMASKS_CH1REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH1REQMASKS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 946 #define DMA_CHREQMASKS_CH2REQMASKS (0x1UL << 2) /**< Channel 2 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 947 #define _DMA_CHREQMASKS_CH2REQMASKS_SHIFT 2 /**< Shift value for DMA_CH2REQMASKS */
AnnaBridge 171:3a7713b1edbc 948 #define _DMA_CHREQMASKS_CH2REQMASKS_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKS */
AnnaBridge 171:3a7713b1edbc 949 #define _DMA_CHREQMASKS_CH2REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 950 #define DMA_CHREQMASKS_CH2REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH2REQMASKS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 951 #define DMA_CHREQMASKS_CH3REQMASKS (0x1UL << 3) /**< Channel 3 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 952 #define _DMA_CHREQMASKS_CH3REQMASKS_SHIFT 3 /**< Shift value for DMA_CH3REQMASKS */
AnnaBridge 171:3a7713b1edbc 953 #define _DMA_CHREQMASKS_CH3REQMASKS_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKS */
AnnaBridge 171:3a7713b1edbc 954 #define _DMA_CHREQMASKS_CH3REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 955 #define DMA_CHREQMASKS_CH3REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH3REQMASKS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 956 #define DMA_CHREQMASKS_CH4REQMASKS (0x1UL << 4) /**< Channel 4 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 957 #define _DMA_CHREQMASKS_CH4REQMASKS_SHIFT 4 /**< Shift value for DMA_CH4REQMASKS */
AnnaBridge 171:3a7713b1edbc 958 #define _DMA_CHREQMASKS_CH4REQMASKS_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKS */
AnnaBridge 171:3a7713b1edbc 959 #define _DMA_CHREQMASKS_CH4REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 960 #define DMA_CHREQMASKS_CH4REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH4REQMASKS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 961 #define DMA_CHREQMASKS_CH5REQMASKS (0x1UL << 5) /**< Channel 5 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 962 #define _DMA_CHREQMASKS_CH5REQMASKS_SHIFT 5 /**< Shift value for DMA_CH5REQMASKS */
AnnaBridge 171:3a7713b1edbc 963 #define _DMA_CHREQMASKS_CH5REQMASKS_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKS */
AnnaBridge 171:3a7713b1edbc 964 #define _DMA_CHREQMASKS_CH5REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 965 #define DMA_CHREQMASKS_CH5REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH5REQMASKS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 966 #define DMA_CHREQMASKS_CH6REQMASKS (0x1UL << 6) /**< Channel 6 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 967 #define _DMA_CHREQMASKS_CH6REQMASKS_SHIFT 6 /**< Shift value for DMA_CH6REQMASKS */
AnnaBridge 171:3a7713b1edbc 968 #define _DMA_CHREQMASKS_CH6REQMASKS_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKS */
AnnaBridge 171:3a7713b1edbc 969 #define _DMA_CHREQMASKS_CH6REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 970 #define DMA_CHREQMASKS_CH6REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH6REQMASKS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 971 #define DMA_CHREQMASKS_CH7REQMASKS (0x1UL << 7) /**< Channel 7 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 972 #define _DMA_CHREQMASKS_CH7REQMASKS_SHIFT 7 /**< Shift value for DMA_CH7REQMASKS */
AnnaBridge 171:3a7713b1edbc 973 #define _DMA_CHREQMASKS_CH7REQMASKS_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKS */
AnnaBridge 171:3a7713b1edbc 974 #define _DMA_CHREQMASKS_CH7REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 975 #define DMA_CHREQMASKS_CH7REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH7REQMASKS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 976 #define DMA_CHREQMASKS_CH8REQMASKS (0x1UL << 8) /**< Channel 8 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 977 #define _DMA_CHREQMASKS_CH8REQMASKS_SHIFT 8 /**< Shift value for DMA_CH8REQMASKS */
AnnaBridge 171:3a7713b1edbc 978 #define _DMA_CHREQMASKS_CH8REQMASKS_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKS */
AnnaBridge 171:3a7713b1edbc 979 #define _DMA_CHREQMASKS_CH8REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 980 #define DMA_CHREQMASKS_CH8REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH8REQMASKS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 981 #define DMA_CHREQMASKS_CH9REQMASKS (0x1UL << 9) /**< Channel 9 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 982 #define _DMA_CHREQMASKS_CH9REQMASKS_SHIFT 9 /**< Shift value for DMA_CH9REQMASKS */
AnnaBridge 171:3a7713b1edbc 983 #define _DMA_CHREQMASKS_CH9REQMASKS_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKS */
AnnaBridge 171:3a7713b1edbc 984 #define _DMA_CHREQMASKS_CH9REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 985 #define DMA_CHREQMASKS_CH9REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH9REQMASKS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 986 #define DMA_CHREQMASKS_CH10REQMASKS (0x1UL << 10) /**< Channel 10 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 987 #define _DMA_CHREQMASKS_CH10REQMASKS_SHIFT 10 /**< Shift value for DMA_CH10REQMASKS */
AnnaBridge 171:3a7713b1edbc 988 #define _DMA_CHREQMASKS_CH10REQMASKS_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKS */
AnnaBridge 171:3a7713b1edbc 989 #define _DMA_CHREQMASKS_CH10REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 990 #define DMA_CHREQMASKS_CH10REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH10REQMASKS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 991 #define DMA_CHREQMASKS_CH11REQMASKS (0x1UL << 11) /**< Channel 11 Request Mask Set */
AnnaBridge 171:3a7713b1edbc 992 #define _DMA_CHREQMASKS_CH11REQMASKS_SHIFT 11 /**< Shift value for DMA_CH11REQMASKS */
AnnaBridge 171:3a7713b1edbc 993 #define _DMA_CHREQMASKS_CH11REQMASKS_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKS */
AnnaBridge 171:3a7713b1edbc 994 #define _DMA_CHREQMASKS_CH11REQMASKS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 995 #define DMA_CHREQMASKS_CH11REQMASKS_DEFAULT (_DMA_CHREQMASKS_CH11REQMASKS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKS */
AnnaBridge 171:3a7713b1edbc 996
AnnaBridge 171:3a7713b1edbc 997 /* Bit fields for DMA CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 998 #define _DMA_CHREQMASKC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 999 #define _DMA_CHREQMASKC_MASK 0x00000FFFUL /**< Mask for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1000 #define DMA_CHREQMASKC_CH0REQMASKC (0x1UL << 0) /**< Channel 0 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1001 #define _DMA_CHREQMASKC_CH0REQMASKC_SHIFT 0 /**< Shift value for DMA_CH0REQMASKC */
AnnaBridge 171:3a7713b1edbc 1002 #define _DMA_CHREQMASKC_CH0REQMASKC_MASK 0x1UL /**< Bit mask for DMA_CH0REQMASKC */
AnnaBridge 171:3a7713b1edbc 1003 #define _DMA_CHREQMASKC_CH0REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1004 #define DMA_CHREQMASKC_CH0REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH0REQMASKC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1005 #define DMA_CHREQMASKC_CH1REQMASKC (0x1UL << 1) /**< Channel 1 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1006 #define _DMA_CHREQMASKC_CH1REQMASKC_SHIFT 1 /**< Shift value for DMA_CH1REQMASKC */
AnnaBridge 171:3a7713b1edbc 1007 #define _DMA_CHREQMASKC_CH1REQMASKC_MASK 0x2UL /**< Bit mask for DMA_CH1REQMASKC */
AnnaBridge 171:3a7713b1edbc 1008 #define _DMA_CHREQMASKC_CH1REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1009 #define DMA_CHREQMASKC_CH1REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH1REQMASKC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1010 #define DMA_CHREQMASKC_CH2REQMASKC (0x1UL << 2) /**< Channel 2 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1011 #define _DMA_CHREQMASKC_CH2REQMASKC_SHIFT 2 /**< Shift value for DMA_CH2REQMASKC */
AnnaBridge 171:3a7713b1edbc 1012 #define _DMA_CHREQMASKC_CH2REQMASKC_MASK 0x4UL /**< Bit mask for DMA_CH2REQMASKC */
AnnaBridge 171:3a7713b1edbc 1013 #define _DMA_CHREQMASKC_CH2REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1014 #define DMA_CHREQMASKC_CH2REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH2REQMASKC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1015 #define DMA_CHREQMASKC_CH3REQMASKC (0x1UL << 3) /**< Channel 3 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1016 #define _DMA_CHREQMASKC_CH3REQMASKC_SHIFT 3 /**< Shift value for DMA_CH3REQMASKC */
AnnaBridge 171:3a7713b1edbc 1017 #define _DMA_CHREQMASKC_CH3REQMASKC_MASK 0x8UL /**< Bit mask for DMA_CH3REQMASKC */
AnnaBridge 171:3a7713b1edbc 1018 #define _DMA_CHREQMASKC_CH3REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1019 #define DMA_CHREQMASKC_CH3REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH3REQMASKC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1020 #define DMA_CHREQMASKC_CH4REQMASKC (0x1UL << 4) /**< Channel 4 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1021 #define _DMA_CHREQMASKC_CH4REQMASKC_SHIFT 4 /**< Shift value for DMA_CH4REQMASKC */
AnnaBridge 171:3a7713b1edbc 1022 #define _DMA_CHREQMASKC_CH4REQMASKC_MASK 0x10UL /**< Bit mask for DMA_CH4REQMASKC */
AnnaBridge 171:3a7713b1edbc 1023 #define _DMA_CHREQMASKC_CH4REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1024 #define DMA_CHREQMASKC_CH4REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH4REQMASKC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1025 #define DMA_CHREQMASKC_CH5REQMASKC (0x1UL << 5) /**< Channel 5 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1026 #define _DMA_CHREQMASKC_CH5REQMASKC_SHIFT 5 /**< Shift value for DMA_CH5REQMASKC */
AnnaBridge 171:3a7713b1edbc 1027 #define _DMA_CHREQMASKC_CH5REQMASKC_MASK 0x20UL /**< Bit mask for DMA_CH5REQMASKC */
AnnaBridge 171:3a7713b1edbc 1028 #define _DMA_CHREQMASKC_CH5REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1029 #define DMA_CHREQMASKC_CH5REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH5REQMASKC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1030 #define DMA_CHREQMASKC_CH6REQMASKC (0x1UL << 6) /**< Channel 6 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1031 #define _DMA_CHREQMASKC_CH6REQMASKC_SHIFT 6 /**< Shift value for DMA_CH6REQMASKC */
AnnaBridge 171:3a7713b1edbc 1032 #define _DMA_CHREQMASKC_CH6REQMASKC_MASK 0x40UL /**< Bit mask for DMA_CH6REQMASKC */
AnnaBridge 171:3a7713b1edbc 1033 #define _DMA_CHREQMASKC_CH6REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1034 #define DMA_CHREQMASKC_CH6REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH6REQMASKC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1035 #define DMA_CHREQMASKC_CH7REQMASKC (0x1UL << 7) /**< Channel 7 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1036 #define _DMA_CHREQMASKC_CH7REQMASKC_SHIFT 7 /**< Shift value for DMA_CH7REQMASKC */
AnnaBridge 171:3a7713b1edbc 1037 #define _DMA_CHREQMASKC_CH7REQMASKC_MASK 0x80UL /**< Bit mask for DMA_CH7REQMASKC */
AnnaBridge 171:3a7713b1edbc 1038 #define _DMA_CHREQMASKC_CH7REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1039 #define DMA_CHREQMASKC_CH7REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH7REQMASKC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1040 #define DMA_CHREQMASKC_CH8REQMASKC (0x1UL << 8) /**< Channel 8 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1041 #define _DMA_CHREQMASKC_CH8REQMASKC_SHIFT 8 /**< Shift value for DMA_CH8REQMASKC */
AnnaBridge 171:3a7713b1edbc 1042 #define _DMA_CHREQMASKC_CH8REQMASKC_MASK 0x100UL /**< Bit mask for DMA_CH8REQMASKC */
AnnaBridge 171:3a7713b1edbc 1043 #define _DMA_CHREQMASKC_CH8REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1044 #define DMA_CHREQMASKC_CH8REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH8REQMASKC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1045 #define DMA_CHREQMASKC_CH9REQMASKC (0x1UL << 9) /**< Channel 9 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1046 #define _DMA_CHREQMASKC_CH9REQMASKC_SHIFT 9 /**< Shift value for DMA_CH9REQMASKC */
AnnaBridge 171:3a7713b1edbc 1047 #define _DMA_CHREQMASKC_CH9REQMASKC_MASK 0x200UL /**< Bit mask for DMA_CH9REQMASKC */
AnnaBridge 171:3a7713b1edbc 1048 #define _DMA_CHREQMASKC_CH9REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1049 #define DMA_CHREQMASKC_CH9REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH9REQMASKC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1050 #define DMA_CHREQMASKC_CH10REQMASKC (0x1UL << 10) /**< Channel 10 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1051 #define _DMA_CHREQMASKC_CH10REQMASKC_SHIFT 10 /**< Shift value for DMA_CH10REQMASKC */
AnnaBridge 171:3a7713b1edbc 1052 #define _DMA_CHREQMASKC_CH10REQMASKC_MASK 0x400UL /**< Bit mask for DMA_CH10REQMASKC */
AnnaBridge 171:3a7713b1edbc 1053 #define _DMA_CHREQMASKC_CH10REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1054 #define DMA_CHREQMASKC_CH10REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH10REQMASKC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1055 #define DMA_CHREQMASKC_CH11REQMASKC (0x1UL << 11) /**< Channel 11 Request Mask Clear */
AnnaBridge 171:3a7713b1edbc 1056 #define _DMA_CHREQMASKC_CH11REQMASKC_SHIFT 11 /**< Shift value for DMA_CH11REQMASKC */
AnnaBridge 171:3a7713b1edbc 1057 #define _DMA_CHREQMASKC_CH11REQMASKC_MASK 0x800UL /**< Bit mask for DMA_CH11REQMASKC */
AnnaBridge 171:3a7713b1edbc 1058 #define _DMA_CHREQMASKC_CH11REQMASKC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1059 #define DMA_CHREQMASKC_CH11REQMASKC_DEFAULT (_DMA_CHREQMASKC_CH11REQMASKC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQMASKC */
AnnaBridge 171:3a7713b1edbc 1060
AnnaBridge 171:3a7713b1edbc 1061 /* Bit fields for DMA CHENS */
AnnaBridge 171:3a7713b1edbc 1062 #define _DMA_CHENS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1063 #define _DMA_CHENS_MASK 0x00000FFFUL /**< Mask for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1064 #define DMA_CHENS_CH0ENS (0x1UL << 0) /**< Channel 0 Enable Set */
AnnaBridge 171:3a7713b1edbc 1065 #define _DMA_CHENS_CH0ENS_SHIFT 0 /**< Shift value for DMA_CH0ENS */
AnnaBridge 171:3a7713b1edbc 1066 #define _DMA_CHENS_CH0ENS_MASK 0x1UL /**< Bit mask for DMA_CH0ENS */
AnnaBridge 171:3a7713b1edbc 1067 #define _DMA_CHENS_CH0ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1068 #define DMA_CHENS_CH0ENS_DEFAULT (_DMA_CHENS_CH0ENS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1069 #define DMA_CHENS_CH1ENS (0x1UL << 1) /**< Channel 1 Enable Set */
AnnaBridge 171:3a7713b1edbc 1070 #define _DMA_CHENS_CH1ENS_SHIFT 1 /**< Shift value for DMA_CH1ENS */
AnnaBridge 171:3a7713b1edbc 1071 #define _DMA_CHENS_CH1ENS_MASK 0x2UL /**< Bit mask for DMA_CH1ENS */
AnnaBridge 171:3a7713b1edbc 1072 #define _DMA_CHENS_CH1ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1073 #define DMA_CHENS_CH1ENS_DEFAULT (_DMA_CHENS_CH1ENS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1074 #define DMA_CHENS_CH2ENS (0x1UL << 2) /**< Channel 2 Enable Set */
AnnaBridge 171:3a7713b1edbc 1075 #define _DMA_CHENS_CH2ENS_SHIFT 2 /**< Shift value for DMA_CH2ENS */
AnnaBridge 171:3a7713b1edbc 1076 #define _DMA_CHENS_CH2ENS_MASK 0x4UL /**< Bit mask for DMA_CH2ENS */
AnnaBridge 171:3a7713b1edbc 1077 #define _DMA_CHENS_CH2ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1078 #define DMA_CHENS_CH2ENS_DEFAULT (_DMA_CHENS_CH2ENS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1079 #define DMA_CHENS_CH3ENS (0x1UL << 3) /**< Channel 3 Enable Set */
AnnaBridge 171:3a7713b1edbc 1080 #define _DMA_CHENS_CH3ENS_SHIFT 3 /**< Shift value for DMA_CH3ENS */
AnnaBridge 171:3a7713b1edbc 1081 #define _DMA_CHENS_CH3ENS_MASK 0x8UL /**< Bit mask for DMA_CH3ENS */
AnnaBridge 171:3a7713b1edbc 1082 #define _DMA_CHENS_CH3ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1083 #define DMA_CHENS_CH3ENS_DEFAULT (_DMA_CHENS_CH3ENS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1084 #define DMA_CHENS_CH4ENS (0x1UL << 4) /**< Channel 4 Enable Set */
AnnaBridge 171:3a7713b1edbc 1085 #define _DMA_CHENS_CH4ENS_SHIFT 4 /**< Shift value for DMA_CH4ENS */
AnnaBridge 171:3a7713b1edbc 1086 #define _DMA_CHENS_CH4ENS_MASK 0x10UL /**< Bit mask for DMA_CH4ENS */
AnnaBridge 171:3a7713b1edbc 1087 #define _DMA_CHENS_CH4ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1088 #define DMA_CHENS_CH4ENS_DEFAULT (_DMA_CHENS_CH4ENS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1089 #define DMA_CHENS_CH5ENS (0x1UL << 5) /**< Channel 5 Enable Set */
AnnaBridge 171:3a7713b1edbc 1090 #define _DMA_CHENS_CH5ENS_SHIFT 5 /**< Shift value for DMA_CH5ENS */
AnnaBridge 171:3a7713b1edbc 1091 #define _DMA_CHENS_CH5ENS_MASK 0x20UL /**< Bit mask for DMA_CH5ENS */
AnnaBridge 171:3a7713b1edbc 1092 #define _DMA_CHENS_CH5ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1093 #define DMA_CHENS_CH5ENS_DEFAULT (_DMA_CHENS_CH5ENS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1094 #define DMA_CHENS_CH6ENS (0x1UL << 6) /**< Channel 6 Enable Set */
AnnaBridge 171:3a7713b1edbc 1095 #define _DMA_CHENS_CH6ENS_SHIFT 6 /**< Shift value for DMA_CH6ENS */
AnnaBridge 171:3a7713b1edbc 1096 #define _DMA_CHENS_CH6ENS_MASK 0x40UL /**< Bit mask for DMA_CH6ENS */
AnnaBridge 171:3a7713b1edbc 1097 #define _DMA_CHENS_CH6ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1098 #define DMA_CHENS_CH6ENS_DEFAULT (_DMA_CHENS_CH6ENS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1099 #define DMA_CHENS_CH7ENS (0x1UL << 7) /**< Channel 7 Enable Set */
AnnaBridge 171:3a7713b1edbc 1100 #define _DMA_CHENS_CH7ENS_SHIFT 7 /**< Shift value for DMA_CH7ENS */
AnnaBridge 171:3a7713b1edbc 1101 #define _DMA_CHENS_CH7ENS_MASK 0x80UL /**< Bit mask for DMA_CH7ENS */
AnnaBridge 171:3a7713b1edbc 1102 #define _DMA_CHENS_CH7ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1103 #define DMA_CHENS_CH7ENS_DEFAULT (_DMA_CHENS_CH7ENS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1104 #define DMA_CHENS_CH8ENS (0x1UL << 8) /**< Channel 8 Enable Set */
AnnaBridge 171:3a7713b1edbc 1105 #define _DMA_CHENS_CH8ENS_SHIFT 8 /**< Shift value for DMA_CH8ENS */
AnnaBridge 171:3a7713b1edbc 1106 #define _DMA_CHENS_CH8ENS_MASK 0x100UL /**< Bit mask for DMA_CH8ENS */
AnnaBridge 171:3a7713b1edbc 1107 #define _DMA_CHENS_CH8ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1108 #define DMA_CHENS_CH8ENS_DEFAULT (_DMA_CHENS_CH8ENS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1109 #define DMA_CHENS_CH9ENS (0x1UL << 9) /**< Channel 9 Enable Set */
AnnaBridge 171:3a7713b1edbc 1110 #define _DMA_CHENS_CH9ENS_SHIFT 9 /**< Shift value for DMA_CH9ENS */
AnnaBridge 171:3a7713b1edbc 1111 #define _DMA_CHENS_CH9ENS_MASK 0x200UL /**< Bit mask for DMA_CH9ENS */
AnnaBridge 171:3a7713b1edbc 1112 #define _DMA_CHENS_CH9ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1113 #define DMA_CHENS_CH9ENS_DEFAULT (_DMA_CHENS_CH9ENS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1114 #define DMA_CHENS_CH10ENS (0x1UL << 10) /**< Channel 10 Enable Set */
AnnaBridge 171:3a7713b1edbc 1115 #define _DMA_CHENS_CH10ENS_SHIFT 10 /**< Shift value for DMA_CH10ENS */
AnnaBridge 171:3a7713b1edbc 1116 #define _DMA_CHENS_CH10ENS_MASK 0x400UL /**< Bit mask for DMA_CH10ENS */
AnnaBridge 171:3a7713b1edbc 1117 #define _DMA_CHENS_CH10ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1118 #define DMA_CHENS_CH10ENS_DEFAULT (_DMA_CHENS_CH10ENS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1119 #define DMA_CHENS_CH11ENS (0x1UL << 11) /**< Channel 11 Enable Set */
AnnaBridge 171:3a7713b1edbc 1120 #define _DMA_CHENS_CH11ENS_SHIFT 11 /**< Shift value for DMA_CH11ENS */
AnnaBridge 171:3a7713b1edbc 1121 #define _DMA_CHENS_CH11ENS_MASK 0x800UL /**< Bit mask for DMA_CH11ENS */
AnnaBridge 171:3a7713b1edbc 1122 #define _DMA_CHENS_CH11ENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1123 #define DMA_CHENS_CH11ENS_DEFAULT (_DMA_CHENS_CH11ENS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENS */
AnnaBridge 171:3a7713b1edbc 1124
AnnaBridge 171:3a7713b1edbc 1125 /* Bit fields for DMA CHENC */
AnnaBridge 171:3a7713b1edbc 1126 #define _DMA_CHENC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1127 #define _DMA_CHENC_MASK 0x00000FFFUL /**< Mask for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1128 #define DMA_CHENC_CH0ENC (0x1UL << 0) /**< Channel 0 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1129 #define _DMA_CHENC_CH0ENC_SHIFT 0 /**< Shift value for DMA_CH0ENC */
AnnaBridge 171:3a7713b1edbc 1130 #define _DMA_CHENC_CH0ENC_MASK 0x1UL /**< Bit mask for DMA_CH0ENC */
AnnaBridge 171:3a7713b1edbc 1131 #define _DMA_CHENC_CH0ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1132 #define DMA_CHENC_CH0ENC_DEFAULT (_DMA_CHENC_CH0ENC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1133 #define DMA_CHENC_CH1ENC (0x1UL << 1) /**< Channel 1 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1134 #define _DMA_CHENC_CH1ENC_SHIFT 1 /**< Shift value for DMA_CH1ENC */
AnnaBridge 171:3a7713b1edbc 1135 #define _DMA_CHENC_CH1ENC_MASK 0x2UL /**< Bit mask for DMA_CH1ENC */
AnnaBridge 171:3a7713b1edbc 1136 #define _DMA_CHENC_CH1ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1137 #define DMA_CHENC_CH1ENC_DEFAULT (_DMA_CHENC_CH1ENC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1138 #define DMA_CHENC_CH2ENC (0x1UL << 2) /**< Channel 2 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1139 #define _DMA_CHENC_CH2ENC_SHIFT 2 /**< Shift value for DMA_CH2ENC */
AnnaBridge 171:3a7713b1edbc 1140 #define _DMA_CHENC_CH2ENC_MASK 0x4UL /**< Bit mask for DMA_CH2ENC */
AnnaBridge 171:3a7713b1edbc 1141 #define _DMA_CHENC_CH2ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1142 #define DMA_CHENC_CH2ENC_DEFAULT (_DMA_CHENC_CH2ENC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1143 #define DMA_CHENC_CH3ENC (0x1UL << 3) /**< Channel 3 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1144 #define _DMA_CHENC_CH3ENC_SHIFT 3 /**< Shift value for DMA_CH3ENC */
AnnaBridge 171:3a7713b1edbc 1145 #define _DMA_CHENC_CH3ENC_MASK 0x8UL /**< Bit mask for DMA_CH3ENC */
AnnaBridge 171:3a7713b1edbc 1146 #define _DMA_CHENC_CH3ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1147 #define DMA_CHENC_CH3ENC_DEFAULT (_DMA_CHENC_CH3ENC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1148 #define DMA_CHENC_CH4ENC (0x1UL << 4) /**< Channel 4 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1149 #define _DMA_CHENC_CH4ENC_SHIFT 4 /**< Shift value for DMA_CH4ENC */
AnnaBridge 171:3a7713b1edbc 1150 #define _DMA_CHENC_CH4ENC_MASK 0x10UL /**< Bit mask for DMA_CH4ENC */
AnnaBridge 171:3a7713b1edbc 1151 #define _DMA_CHENC_CH4ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1152 #define DMA_CHENC_CH4ENC_DEFAULT (_DMA_CHENC_CH4ENC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1153 #define DMA_CHENC_CH5ENC (0x1UL << 5) /**< Channel 5 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1154 #define _DMA_CHENC_CH5ENC_SHIFT 5 /**< Shift value for DMA_CH5ENC */
AnnaBridge 171:3a7713b1edbc 1155 #define _DMA_CHENC_CH5ENC_MASK 0x20UL /**< Bit mask for DMA_CH5ENC */
AnnaBridge 171:3a7713b1edbc 1156 #define _DMA_CHENC_CH5ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1157 #define DMA_CHENC_CH5ENC_DEFAULT (_DMA_CHENC_CH5ENC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1158 #define DMA_CHENC_CH6ENC (0x1UL << 6) /**< Channel 6 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1159 #define _DMA_CHENC_CH6ENC_SHIFT 6 /**< Shift value for DMA_CH6ENC */
AnnaBridge 171:3a7713b1edbc 1160 #define _DMA_CHENC_CH6ENC_MASK 0x40UL /**< Bit mask for DMA_CH6ENC */
AnnaBridge 171:3a7713b1edbc 1161 #define _DMA_CHENC_CH6ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1162 #define DMA_CHENC_CH6ENC_DEFAULT (_DMA_CHENC_CH6ENC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1163 #define DMA_CHENC_CH7ENC (0x1UL << 7) /**< Channel 7 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1164 #define _DMA_CHENC_CH7ENC_SHIFT 7 /**< Shift value for DMA_CH7ENC */
AnnaBridge 171:3a7713b1edbc 1165 #define _DMA_CHENC_CH7ENC_MASK 0x80UL /**< Bit mask for DMA_CH7ENC */
AnnaBridge 171:3a7713b1edbc 1166 #define _DMA_CHENC_CH7ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1167 #define DMA_CHENC_CH7ENC_DEFAULT (_DMA_CHENC_CH7ENC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1168 #define DMA_CHENC_CH8ENC (0x1UL << 8) /**< Channel 8 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1169 #define _DMA_CHENC_CH8ENC_SHIFT 8 /**< Shift value for DMA_CH8ENC */
AnnaBridge 171:3a7713b1edbc 1170 #define _DMA_CHENC_CH8ENC_MASK 0x100UL /**< Bit mask for DMA_CH8ENC */
AnnaBridge 171:3a7713b1edbc 1171 #define _DMA_CHENC_CH8ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1172 #define DMA_CHENC_CH8ENC_DEFAULT (_DMA_CHENC_CH8ENC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1173 #define DMA_CHENC_CH9ENC (0x1UL << 9) /**< Channel 9 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1174 #define _DMA_CHENC_CH9ENC_SHIFT 9 /**< Shift value for DMA_CH9ENC */
AnnaBridge 171:3a7713b1edbc 1175 #define _DMA_CHENC_CH9ENC_MASK 0x200UL /**< Bit mask for DMA_CH9ENC */
AnnaBridge 171:3a7713b1edbc 1176 #define _DMA_CHENC_CH9ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1177 #define DMA_CHENC_CH9ENC_DEFAULT (_DMA_CHENC_CH9ENC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1178 #define DMA_CHENC_CH10ENC (0x1UL << 10) /**< Channel 10 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1179 #define _DMA_CHENC_CH10ENC_SHIFT 10 /**< Shift value for DMA_CH10ENC */
AnnaBridge 171:3a7713b1edbc 1180 #define _DMA_CHENC_CH10ENC_MASK 0x400UL /**< Bit mask for DMA_CH10ENC */
AnnaBridge 171:3a7713b1edbc 1181 #define _DMA_CHENC_CH10ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1182 #define DMA_CHENC_CH10ENC_DEFAULT (_DMA_CHENC_CH10ENC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1183 #define DMA_CHENC_CH11ENC (0x1UL << 11) /**< Channel 11 Enable Clear */
AnnaBridge 171:3a7713b1edbc 1184 #define _DMA_CHENC_CH11ENC_SHIFT 11 /**< Shift value for DMA_CH11ENC */
AnnaBridge 171:3a7713b1edbc 1185 #define _DMA_CHENC_CH11ENC_MASK 0x800UL /**< Bit mask for DMA_CH11ENC */
AnnaBridge 171:3a7713b1edbc 1186 #define _DMA_CHENC_CH11ENC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1187 #define DMA_CHENC_CH11ENC_DEFAULT (_DMA_CHENC_CH11ENC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHENC */
AnnaBridge 171:3a7713b1edbc 1188
AnnaBridge 171:3a7713b1edbc 1189 /* Bit fields for DMA CHALTS */
AnnaBridge 171:3a7713b1edbc 1190 #define _DMA_CHALTS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1191 #define _DMA_CHALTS_MASK 0x00000FFFUL /**< Mask for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1192 #define DMA_CHALTS_CH0ALTS (0x1UL << 0) /**< Channel 0 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1193 #define _DMA_CHALTS_CH0ALTS_SHIFT 0 /**< Shift value for DMA_CH0ALTS */
AnnaBridge 171:3a7713b1edbc 1194 #define _DMA_CHALTS_CH0ALTS_MASK 0x1UL /**< Bit mask for DMA_CH0ALTS */
AnnaBridge 171:3a7713b1edbc 1195 #define _DMA_CHALTS_CH0ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1196 #define DMA_CHALTS_CH0ALTS_DEFAULT (_DMA_CHALTS_CH0ALTS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1197 #define DMA_CHALTS_CH1ALTS (0x1UL << 1) /**< Channel 1 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1198 #define _DMA_CHALTS_CH1ALTS_SHIFT 1 /**< Shift value for DMA_CH1ALTS */
AnnaBridge 171:3a7713b1edbc 1199 #define _DMA_CHALTS_CH1ALTS_MASK 0x2UL /**< Bit mask for DMA_CH1ALTS */
AnnaBridge 171:3a7713b1edbc 1200 #define _DMA_CHALTS_CH1ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1201 #define DMA_CHALTS_CH1ALTS_DEFAULT (_DMA_CHALTS_CH1ALTS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1202 #define DMA_CHALTS_CH2ALTS (0x1UL << 2) /**< Channel 2 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1203 #define _DMA_CHALTS_CH2ALTS_SHIFT 2 /**< Shift value for DMA_CH2ALTS */
AnnaBridge 171:3a7713b1edbc 1204 #define _DMA_CHALTS_CH2ALTS_MASK 0x4UL /**< Bit mask for DMA_CH2ALTS */
AnnaBridge 171:3a7713b1edbc 1205 #define _DMA_CHALTS_CH2ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1206 #define DMA_CHALTS_CH2ALTS_DEFAULT (_DMA_CHALTS_CH2ALTS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1207 #define DMA_CHALTS_CH3ALTS (0x1UL << 3) /**< Channel 3 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1208 #define _DMA_CHALTS_CH3ALTS_SHIFT 3 /**< Shift value for DMA_CH3ALTS */
AnnaBridge 171:3a7713b1edbc 1209 #define _DMA_CHALTS_CH3ALTS_MASK 0x8UL /**< Bit mask for DMA_CH3ALTS */
AnnaBridge 171:3a7713b1edbc 1210 #define _DMA_CHALTS_CH3ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1211 #define DMA_CHALTS_CH3ALTS_DEFAULT (_DMA_CHALTS_CH3ALTS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1212 #define DMA_CHALTS_CH4ALTS (0x1UL << 4) /**< Channel 4 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1213 #define _DMA_CHALTS_CH4ALTS_SHIFT 4 /**< Shift value for DMA_CH4ALTS */
AnnaBridge 171:3a7713b1edbc 1214 #define _DMA_CHALTS_CH4ALTS_MASK 0x10UL /**< Bit mask for DMA_CH4ALTS */
AnnaBridge 171:3a7713b1edbc 1215 #define _DMA_CHALTS_CH4ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1216 #define DMA_CHALTS_CH4ALTS_DEFAULT (_DMA_CHALTS_CH4ALTS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1217 #define DMA_CHALTS_CH5ALTS (0x1UL << 5) /**< Channel 5 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1218 #define _DMA_CHALTS_CH5ALTS_SHIFT 5 /**< Shift value for DMA_CH5ALTS */
AnnaBridge 171:3a7713b1edbc 1219 #define _DMA_CHALTS_CH5ALTS_MASK 0x20UL /**< Bit mask for DMA_CH5ALTS */
AnnaBridge 171:3a7713b1edbc 1220 #define _DMA_CHALTS_CH5ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1221 #define DMA_CHALTS_CH5ALTS_DEFAULT (_DMA_CHALTS_CH5ALTS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1222 #define DMA_CHALTS_CH6ALTS (0x1UL << 6) /**< Channel 6 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1223 #define _DMA_CHALTS_CH6ALTS_SHIFT 6 /**< Shift value for DMA_CH6ALTS */
AnnaBridge 171:3a7713b1edbc 1224 #define _DMA_CHALTS_CH6ALTS_MASK 0x40UL /**< Bit mask for DMA_CH6ALTS */
AnnaBridge 171:3a7713b1edbc 1225 #define _DMA_CHALTS_CH6ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1226 #define DMA_CHALTS_CH6ALTS_DEFAULT (_DMA_CHALTS_CH6ALTS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1227 #define DMA_CHALTS_CH7ALTS (0x1UL << 7) /**< Channel 7 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1228 #define _DMA_CHALTS_CH7ALTS_SHIFT 7 /**< Shift value for DMA_CH7ALTS */
AnnaBridge 171:3a7713b1edbc 1229 #define _DMA_CHALTS_CH7ALTS_MASK 0x80UL /**< Bit mask for DMA_CH7ALTS */
AnnaBridge 171:3a7713b1edbc 1230 #define _DMA_CHALTS_CH7ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1231 #define DMA_CHALTS_CH7ALTS_DEFAULT (_DMA_CHALTS_CH7ALTS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1232 #define DMA_CHALTS_CH8ALTS (0x1UL << 8) /**< Channel 8 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1233 #define _DMA_CHALTS_CH8ALTS_SHIFT 8 /**< Shift value for DMA_CH8ALTS */
AnnaBridge 171:3a7713b1edbc 1234 #define _DMA_CHALTS_CH8ALTS_MASK 0x100UL /**< Bit mask for DMA_CH8ALTS */
AnnaBridge 171:3a7713b1edbc 1235 #define _DMA_CHALTS_CH8ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1236 #define DMA_CHALTS_CH8ALTS_DEFAULT (_DMA_CHALTS_CH8ALTS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1237 #define DMA_CHALTS_CH9ALTS (0x1UL << 9) /**< Channel 9 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1238 #define _DMA_CHALTS_CH9ALTS_SHIFT 9 /**< Shift value for DMA_CH9ALTS */
AnnaBridge 171:3a7713b1edbc 1239 #define _DMA_CHALTS_CH9ALTS_MASK 0x200UL /**< Bit mask for DMA_CH9ALTS */
AnnaBridge 171:3a7713b1edbc 1240 #define _DMA_CHALTS_CH9ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1241 #define DMA_CHALTS_CH9ALTS_DEFAULT (_DMA_CHALTS_CH9ALTS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1242 #define DMA_CHALTS_CH10ALTS (0x1UL << 10) /**< Channel 10 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1243 #define _DMA_CHALTS_CH10ALTS_SHIFT 10 /**< Shift value for DMA_CH10ALTS */
AnnaBridge 171:3a7713b1edbc 1244 #define _DMA_CHALTS_CH10ALTS_MASK 0x400UL /**< Bit mask for DMA_CH10ALTS */
AnnaBridge 171:3a7713b1edbc 1245 #define _DMA_CHALTS_CH10ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1246 #define DMA_CHALTS_CH10ALTS_DEFAULT (_DMA_CHALTS_CH10ALTS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1247 #define DMA_CHALTS_CH11ALTS (0x1UL << 11) /**< Channel 11 Alternate Structure Set */
AnnaBridge 171:3a7713b1edbc 1248 #define _DMA_CHALTS_CH11ALTS_SHIFT 11 /**< Shift value for DMA_CH11ALTS */
AnnaBridge 171:3a7713b1edbc 1249 #define _DMA_CHALTS_CH11ALTS_MASK 0x800UL /**< Bit mask for DMA_CH11ALTS */
AnnaBridge 171:3a7713b1edbc 1250 #define _DMA_CHALTS_CH11ALTS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1251 #define DMA_CHALTS_CH11ALTS_DEFAULT (_DMA_CHALTS_CH11ALTS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTS */
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /* Bit fields for DMA CHALTC */
AnnaBridge 171:3a7713b1edbc 1254 #define _DMA_CHALTC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1255 #define _DMA_CHALTC_MASK 0x00000FFFUL /**< Mask for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1256 #define DMA_CHALTC_CH0ALTC (0x1UL << 0) /**< Channel 0 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1257 #define _DMA_CHALTC_CH0ALTC_SHIFT 0 /**< Shift value for DMA_CH0ALTC */
AnnaBridge 171:3a7713b1edbc 1258 #define _DMA_CHALTC_CH0ALTC_MASK 0x1UL /**< Bit mask for DMA_CH0ALTC */
AnnaBridge 171:3a7713b1edbc 1259 #define _DMA_CHALTC_CH0ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1260 #define DMA_CHALTC_CH0ALTC_DEFAULT (_DMA_CHALTC_CH0ALTC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1261 #define DMA_CHALTC_CH1ALTC (0x1UL << 1) /**< Channel 1 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1262 #define _DMA_CHALTC_CH1ALTC_SHIFT 1 /**< Shift value for DMA_CH1ALTC */
AnnaBridge 171:3a7713b1edbc 1263 #define _DMA_CHALTC_CH1ALTC_MASK 0x2UL /**< Bit mask for DMA_CH1ALTC */
AnnaBridge 171:3a7713b1edbc 1264 #define _DMA_CHALTC_CH1ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1265 #define DMA_CHALTC_CH1ALTC_DEFAULT (_DMA_CHALTC_CH1ALTC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1266 #define DMA_CHALTC_CH2ALTC (0x1UL << 2) /**< Channel 2 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1267 #define _DMA_CHALTC_CH2ALTC_SHIFT 2 /**< Shift value for DMA_CH2ALTC */
AnnaBridge 171:3a7713b1edbc 1268 #define _DMA_CHALTC_CH2ALTC_MASK 0x4UL /**< Bit mask for DMA_CH2ALTC */
AnnaBridge 171:3a7713b1edbc 1269 #define _DMA_CHALTC_CH2ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1270 #define DMA_CHALTC_CH2ALTC_DEFAULT (_DMA_CHALTC_CH2ALTC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1271 #define DMA_CHALTC_CH3ALTC (0x1UL << 3) /**< Channel 3 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1272 #define _DMA_CHALTC_CH3ALTC_SHIFT 3 /**< Shift value for DMA_CH3ALTC */
AnnaBridge 171:3a7713b1edbc 1273 #define _DMA_CHALTC_CH3ALTC_MASK 0x8UL /**< Bit mask for DMA_CH3ALTC */
AnnaBridge 171:3a7713b1edbc 1274 #define _DMA_CHALTC_CH3ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1275 #define DMA_CHALTC_CH3ALTC_DEFAULT (_DMA_CHALTC_CH3ALTC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1276 #define DMA_CHALTC_CH4ALTC (0x1UL << 4) /**< Channel 4 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1277 #define _DMA_CHALTC_CH4ALTC_SHIFT 4 /**< Shift value for DMA_CH4ALTC */
AnnaBridge 171:3a7713b1edbc 1278 #define _DMA_CHALTC_CH4ALTC_MASK 0x10UL /**< Bit mask for DMA_CH4ALTC */
AnnaBridge 171:3a7713b1edbc 1279 #define _DMA_CHALTC_CH4ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1280 #define DMA_CHALTC_CH4ALTC_DEFAULT (_DMA_CHALTC_CH4ALTC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1281 #define DMA_CHALTC_CH5ALTC (0x1UL << 5) /**< Channel 5 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1282 #define _DMA_CHALTC_CH5ALTC_SHIFT 5 /**< Shift value for DMA_CH5ALTC */
AnnaBridge 171:3a7713b1edbc 1283 #define _DMA_CHALTC_CH5ALTC_MASK 0x20UL /**< Bit mask for DMA_CH5ALTC */
AnnaBridge 171:3a7713b1edbc 1284 #define _DMA_CHALTC_CH5ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1285 #define DMA_CHALTC_CH5ALTC_DEFAULT (_DMA_CHALTC_CH5ALTC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1286 #define DMA_CHALTC_CH6ALTC (0x1UL << 6) /**< Channel 6 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1287 #define _DMA_CHALTC_CH6ALTC_SHIFT 6 /**< Shift value for DMA_CH6ALTC */
AnnaBridge 171:3a7713b1edbc 1288 #define _DMA_CHALTC_CH6ALTC_MASK 0x40UL /**< Bit mask for DMA_CH6ALTC */
AnnaBridge 171:3a7713b1edbc 1289 #define _DMA_CHALTC_CH6ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1290 #define DMA_CHALTC_CH6ALTC_DEFAULT (_DMA_CHALTC_CH6ALTC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1291 #define DMA_CHALTC_CH7ALTC (0x1UL << 7) /**< Channel 7 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1292 #define _DMA_CHALTC_CH7ALTC_SHIFT 7 /**< Shift value for DMA_CH7ALTC */
AnnaBridge 171:3a7713b1edbc 1293 #define _DMA_CHALTC_CH7ALTC_MASK 0x80UL /**< Bit mask for DMA_CH7ALTC */
AnnaBridge 171:3a7713b1edbc 1294 #define _DMA_CHALTC_CH7ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1295 #define DMA_CHALTC_CH7ALTC_DEFAULT (_DMA_CHALTC_CH7ALTC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1296 #define DMA_CHALTC_CH8ALTC (0x1UL << 8) /**< Channel 8 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1297 #define _DMA_CHALTC_CH8ALTC_SHIFT 8 /**< Shift value for DMA_CH8ALTC */
AnnaBridge 171:3a7713b1edbc 1298 #define _DMA_CHALTC_CH8ALTC_MASK 0x100UL /**< Bit mask for DMA_CH8ALTC */
AnnaBridge 171:3a7713b1edbc 1299 #define _DMA_CHALTC_CH8ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1300 #define DMA_CHALTC_CH8ALTC_DEFAULT (_DMA_CHALTC_CH8ALTC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1301 #define DMA_CHALTC_CH9ALTC (0x1UL << 9) /**< Channel 9 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1302 #define _DMA_CHALTC_CH9ALTC_SHIFT 9 /**< Shift value for DMA_CH9ALTC */
AnnaBridge 171:3a7713b1edbc 1303 #define _DMA_CHALTC_CH9ALTC_MASK 0x200UL /**< Bit mask for DMA_CH9ALTC */
AnnaBridge 171:3a7713b1edbc 1304 #define _DMA_CHALTC_CH9ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1305 #define DMA_CHALTC_CH9ALTC_DEFAULT (_DMA_CHALTC_CH9ALTC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1306 #define DMA_CHALTC_CH10ALTC (0x1UL << 10) /**< Channel 10 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1307 #define _DMA_CHALTC_CH10ALTC_SHIFT 10 /**< Shift value for DMA_CH10ALTC */
AnnaBridge 171:3a7713b1edbc 1308 #define _DMA_CHALTC_CH10ALTC_MASK 0x400UL /**< Bit mask for DMA_CH10ALTC */
AnnaBridge 171:3a7713b1edbc 1309 #define _DMA_CHALTC_CH10ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1310 #define DMA_CHALTC_CH10ALTC_DEFAULT (_DMA_CHALTC_CH10ALTC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1311 #define DMA_CHALTC_CH11ALTC (0x1UL << 11) /**< Channel 11 Alternate Clear */
AnnaBridge 171:3a7713b1edbc 1312 #define _DMA_CHALTC_CH11ALTC_SHIFT 11 /**< Shift value for DMA_CH11ALTC */
AnnaBridge 171:3a7713b1edbc 1313 #define _DMA_CHALTC_CH11ALTC_MASK 0x800UL /**< Bit mask for DMA_CH11ALTC */
AnnaBridge 171:3a7713b1edbc 1314 #define _DMA_CHALTC_CH11ALTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1315 #define DMA_CHALTC_CH11ALTC_DEFAULT (_DMA_CHALTC_CH11ALTC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHALTC */
AnnaBridge 171:3a7713b1edbc 1316
AnnaBridge 171:3a7713b1edbc 1317 /* Bit fields for DMA CHPRIS */
AnnaBridge 171:3a7713b1edbc 1318 #define _DMA_CHPRIS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1319 #define _DMA_CHPRIS_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1320 #define DMA_CHPRIS_CH0PRIS (0x1UL << 0) /**< Channel 0 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1321 #define _DMA_CHPRIS_CH0PRIS_SHIFT 0 /**< Shift value for DMA_CH0PRIS */
AnnaBridge 171:3a7713b1edbc 1322 #define _DMA_CHPRIS_CH0PRIS_MASK 0x1UL /**< Bit mask for DMA_CH0PRIS */
AnnaBridge 171:3a7713b1edbc 1323 #define _DMA_CHPRIS_CH0PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1324 #define DMA_CHPRIS_CH0PRIS_DEFAULT (_DMA_CHPRIS_CH0PRIS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1325 #define DMA_CHPRIS_CH1PRIS (0x1UL << 1) /**< Channel 1 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1326 #define _DMA_CHPRIS_CH1PRIS_SHIFT 1 /**< Shift value for DMA_CH1PRIS */
AnnaBridge 171:3a7713b1edbc 1327 #define _DMA_CHPRIS_CH1PRIS_MASK 0x2UL /**< Bit mask for DMA_CH1PRIS */
AnnaBridge 171:3a7713b1edbc 1328 #define _DMA_CHPRIS_CH1PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1329 #define DMA_CHPRIS_CH1PRIS_DEFAULT (_DMA_CHPRIS_CH1PRIS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1330 #define DMA_CHPRIS_CH2PRIS (0x1UL << 2) /**< Channel 2 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1331 #define _DMA_CHPRIS_CH2PRIS_SHIFT 2 /**< Shift value for DMA_CH2PRIS */
AnnaBridge 171:3a7713b1edbc 1332 #define _DMA_CHPRIS_CH2PRIS_MASK 0x4UL /**< Bit mask for DMA_CH2PRIS */
AnnaBridge 171:3a7713b1edbc 1333 #define _DMA_CHPRIS_CH2PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1334 #define DMA_CHPRIS_CH2PRIS_DEFAULT (_DMA_CHPRIS_CH2PRIS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1335 #define DMA_CHPRIS_CH3PRIS (0x1UL << 3) /**< Channel 3 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1336 #define _DMA_CHPRIS_CH3PRIS_SHIFT 3 /**< Shift value for DMA_CH3PRIS */
AnnaBridge 171:3a7713b1edbc 1337 #define _DMA_CHPRIS_CH3PRIS_MASK 0x8UL /**< Bit mask for DMA_CH3PRIS */
AnnaBridge 171:3a7713b1edbc 1338 #define _DMA_CHPRIS_CH3PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1339 #define DMA_CHPRIS_CH3PRIS_DEFAULT (_DMA_CHPRIS_CH3PRIS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1340 #define DMA_CHPRIS_CH4PRIS (0x1UL << 4) /**< Channel 4 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1341 #define _DMA_CHPRIS_CH4PRIS_SHIFT 4 /**< Shift value for DMA_CH4PRIS */
AnnaBridge 171:3a7713b1edbc 1342 #define _DMA_CHPRIS_CH4PRIS_MASK 0x10UL /**< Bit mask for DMA_CH4PRIS */
AnnaBridge 171:3a7713b1edbc 1343 #define _DMA_CHPRIS_CH4PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1344 #define DMA_CHPRIS_CH4PRIS_DEFAULT (_DMA_CHPRIS_CH4PRIS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1345 #define DMA_CHPRIS_CH5PRIS (0x1UL << 5) /**< Channel 5 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1346 #define _DMA_CHPRIS_CH5PRIS_SHIFT 5 /**< Shift value for DMA_CH5PRIS */
AnnaBridge 171:3a7713b1edbc 1347 #define _DMA_CHPRIS_CH5PRIS_MASK 0x20UL /**< Bit mask for DMA_CH5PRIS */
AnnaBridge 171:3a7713b1edbc 1348 #define _DMA_CHPRIS_CH5PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1349 #define DMA_CHPRIS_CH5PRIS_DEFAULT (_DMA_CHPRIS_CH5PRIS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1350 #define DMA_CHPRIS_CH6PRIS (0x1UL << 6) /**< Channel 6 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1351 #define _DMA_CHPRIS_CH6PRIS_SHIFT 6 /**< Shift value for DMA_CH6PRIS */
AnnaBridge 171:3a7713b1edbc 1352 #define _DMA_CHPRIS_CH6PRIS_MASK 0x40UL /**< Bit mask for DMA_CH6PRIS */
AnnaBridge 171:3a7713b1edbc 1353 #define _DMA_CHPRIS_CH6PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1354 #define DMA_CHPRIS_CH6PRIS_DEFAULT (_DMA_CHPRIS_CH6PRIS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1355 #define DMA_CHPRIS_CH7PRIS (0x1UL << 7) /**< Channel 7 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1356 #define _DMA_CHPRIS_CH7PRIS_SHIFT 7 /**< Shift value for DMA_CH7PRIS */
AnnaBridge 171:3a7713b1edbc 1357 #define _DMA_CHPRIS_CH7PRIS_MASK 0x80UL /**< Bit mask for DMA_CH7PRIS */
AnnaBridge 171:3a7713b1edbc 1358 #define _DMA_CHPRIS_CH7PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1359 #define DMA_CHPRIS_CH7PRIS_DEFAULT (_DMA_CHPRIS_CH7PRIS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1360 #define DMA_CHPRIS_CH8PRIS (0x1UL << 8) /**< Channel 8 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1361 #define _DMA_CHPRIS_CH8PRIS_SHIFT 8 /**< Shift value for DMA_CH8PRIS */
AnnaBridge 171:3a7713b1edbc 1362 #define _DMA_CHPRIS_CH8PRIS_MASK 0x100UL /**< Bit mask for DMA_CH8PRIS */
AnnaBridge 171:3a7713b1edbc 1363 #define _DMA_CHPRIS_CH8PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1364 #define DMA_CHPRIS_CH8PRIS_DEFAULT (_DMA_CHPRIS_CH8PRIS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1365 #define DMA_CHPRIS_CH9PRIS (0x1UL << 9) /**< Channel 9 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1366 #define _DMA_CHPRIS_CH9PRIS_SHIFT 9 /**< Shift value for DMA_CH9PRIS */
AnnaBridge 171:3a7713b1edbc 1367 #define _DMA_CHPRIS_CH9PRIS_MASK 0x200UL /**< Bit mask for DMA_CH9PRIS */
AnnaBridge 171:3a7713b1edbc 1368 #define _DMA_CHPRIS_CH9PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1369 #define DMA_CHPRIS_CH9PRIS_DEFAULT (_DMA_CHPRIS_CH9PRIS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1370 #define DMA_CHPRIS_CH10PRIS (0x1UL << 10) /**< Channel 10 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1371 #define _DMA_CHPRIS_CH10PRIS_SHIFT 10 /**< Shift value for DMA_CH10PRIS */
AnnaBridge 171:3a7713b1edbc 1372 #define _DMA_CHPRIS_CH10PRIS_MASK 0x400UL /**< Bit mask for DMA_CH10PRIS */
AnnaBridge 171:3a7713b1edbc 1373 #define _DMA_CHPRIS_CH10PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1374 #define DMA_CHPRIS_CH10PRIS_DEFAULT (_DMA_CHPRIS_CH10PRIS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1375 #define DMA_CHPRIS_CH11PRIS (0x1UL << 11) /**< Channel 11 High Priority Set */
AnnaBridge 171:3a7713b1edbc 1376 #define _DMA_CHPRIS_CH11PRIS_SHIFT 11 /**< Shift value for DMA_CH11PRIS */
AnnaBridge 171:3a7713b1edbc 1377 #define _DMA_CHPRIS_CH11PRIS_MASK 0x800UL /**< Bit mask for DMA_CH11PRIS */
AnnaBridge 171:3a7713b1edbc 1378 #define _DMA_CHPRIS_CH11PRIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1379 #define DMA_CHPRIS_CH11PRIS_DEFAULT (_DMA_CHPRIS_CH11PRIS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIS */
AnnaBridge 171:3a7713b1edbc 1380
AnnaBridge 171:3a7713b1edbc 1381 /* Bit fields for DMA CHPRIC */
AnnaBridge 171:3a7713b1edbc 1382 #define _DMA_CHPRIC_RESETVALUE 0x00000000UL /**< Default value for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1383 #define _DMA_CHPRIC_MASK 0x00000FFFUL /**< Mask for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1384 #define DMA_CHPRIC_CH0PRIC (0x1UL << 0) /**< Channel 0 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1385 #define _DMA_CHPRIC_CH0PRIC_SHIFT 0 /**< Shift value for DMA_CH0PRIC */
AnnaBridge 171:3a7713b1edbc 1386 #define _DMA_CHPRIC_CH0PRIC_MASK 0x1UL /**< Bit mask for DMA_CH0PRIC */
AnnaBridge 171:3a7713b1edbc 1387 #define _DMA_CHPRIC_CH0PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1388 #define DMA_CHPRIC_CH0PRIC_DEFAULT (_DMA_CHPRIC_CH0PRIC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1389 #define DMA_CHPRIC_CH1PRIC (0x1UL << 1) /**< Channel 1 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1390 #define _DMA_CHPRIC_CH1PRIC_SHIFT 1 /**< Shift value for DMA_CH1PRIC */
AnnaBridge 171:3a7713b1edbc 1391 #define _DMA_CHPRIC_CH1PRIC_MASK 0x2UL /**< Bit mask for DMA_CH1PRIC */
AnnaBridge 171:3a7713b1edbc 1392 #define _DMA_CHPRIC_CH1PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1393 #define DMA_CHPRIC_CH1PRIC_DEFAULT (_DMA_CHPRIC_CH1PRIC_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1394 #define DMA_CHPRIC_CH2PRIC (0x1UL << 2) /**< Channel 2 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1395 #define _DMA_CHPRIC_CH2PRIC_SHIFT 2 /**< Shift value for DMA_CH2PRIC */
AnnaBridge 171:3a7713b1edbc 1396 #define _DMA_CHPRIC_CH2PRIC_MASK 0x4UL /**< Bit mask for DMA_CH2PRIC */
AnnaBridge 171:3a7713b1edbc 1397 #define _DMA_CHPRIC_CH2PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1398 #define DMA_CHPRIC_CH2PRIC_DEFAULT (_DMA_CHPRIC_CH2PRIC_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1399 #define DMA_CHPRIC_CH3PRIC (0x1UL << 3) /**< Channel 3 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1400 #define _DMA_CHPRIC_CH3PRIC_SHIFT 3 /**< Shift value for DMA_CH3PRIC */
AnnaBridge 171:3a7713b1edbc 1401 #define _DMA_CHPRIC_CH3PRIC_MASK 0x8UL /**< Bit mask for DMA_CH3PRIC */
AnnaBridge 171:3a7713b1edbc 1402 #define _DMA_CHPRIC_CH3PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1403 #define DMA_CHPRIC_CH3PRIC_DEFAULT (_DMA_CHPRIC_CH3PRIC_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1404 #define DMA_CHPRIC_CH4PRIC (0x1UL << 4) /**< Channel 4 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1405 #define _DMA_CHPRIC_CH4PRIC_SHIFT 4 /**< Shift value for DMA_CH4PRIC */
AnnaBridge 171:3a7713b1edbc 1406 #define _DMA_CHPRIC_CH4PRIC_MASK 0x10UL /**< Bit mask for DMA_CH4PRIC */
AnnaBridge 171:3a7713b1edbc 1407 #define _DMA_CHPRIC_CH4PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1408 #define DMA_CHPRIC_CH4PRIC_DEFAULT (_DMA_CHPRIC_CH4PRIC_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1409 #define DMA_CHPRIC_CH5PRIC (0x1UL << 5) /**< Channel 5 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1410 #define _DMA_CHPRIC_CH5PRIC_SHIFT 5 /**< Shift value for DMA_CH5PRIC */
AnnaBridge 171:3a7713b1edbc 1411 #define _DMA_CHPRIC_CH5PRIC_MASK 0x20UL /**< Bit mask for DMA_CH5PRIC */
AnnaBridge 171:3a7713b1edbc 1412 #define _DMA_CHPRIC_CH5PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1413 #define DMA_CHPRIC_CH5PRIC_DEFAULT (_DMA_CHPRIC_CH5PRIC_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1414 #define DMA_CHPRIC_CH6PRIC (0x1UL << 6) /**< Channel 6 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1415 #define _DMA_CHPRIC_CH6PRIC_SHIFT 6 /**< Shift value for DMA_CH6PRIC */
AnnaBridge 171:3a7713b1edbc 1416 #define _DMA_CHPRIC_CH6PRIC_MASK 0x40UL /**< Bit mask for DMA_CH6PRIC */
AnnaBridge 171:3a7713b1edbc 1417 #define _DMA_CHPRIC_CH6PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1418 #define DMA_CHPRIC_CH6PRIC_DEFAULT (_DMA_CHPRIC_CH6PRIC_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1419 #define DMA_CHPRIC_CH7PRIC (0x1UL << 7) /**< Channel 7 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1420 #define _DMA_CHPRIC_CH7PRIC_SHIFT 7 /**< Shift value for DMA_CH7PRIC */
AnnaBridge 171:3a7713b1edbc 1421 #define _DMA_CHPRIC_CH7PRIC_MASK 0x80UL /**< Bit mask for DMA_CH7PRIC */
AnnaBridge 171:3a7713b1edbc 1422 #define _DMA_CHPRIC_CH7PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1423 #define DMA_CHPRIC_CH7PRIC_DEFAULT (_DMA_CHPRIC_CH7PRIC_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1424 #define DMA_CHPRIC_CH8PRIC (0x1UL << 8) /**< Channel 8 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1425 #define _DMA_CHPRIC_CH8PRIC_SHIFT 8 /**< Shift value for DMA_CH8PRIC */
AnnaBridge 171:3a7713b1edbc 1426 #define _DMA_CHPRIC_CH8PRIC_MASK 0x100UL /**< Bit mask for DMA_CH8PRIC */
AnnaBridge 171:3a7713b1edbc 1427 #define _DMA_CHPRIC_CH8PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1428 #define DMA_CHPRIC_CH8PRIC_DEFAULT (_DMA_CHPRIC_CH8PRIC_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1429 #define DMA_CHPRIC_CH9PRIC (0x1UL << 9) /**< Channel 9 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1430 #define _DMA_CHPRIC_CH9PRIC_SHIFT 9 /**< Shift value for DMA_CH9PRIC */
AnnaBridge 171:3a7713b1edbc 1431 #define _DMA_CHPRIC_CH9PRIC_MASK 0x200UL /**< Bit mask for DMA_CH9PRIC */
AnnaBridge 171:3a7713b1edbc 1432 #define _DMA_CHPRIC_CH9PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1433 #define DMA_CHPRIC_CH9PRIC_DEFAULT (_DMA_CHPRIC_CH9PRIC_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1434 #define DMA_CHPRIC_CH10PRIC (0x1UL << 10) /**< Channel 10 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1435 #define _DMA_CHPRIC_CH10PRIC_SHIFT 10 /**< Shift value for DMA_CH10PRIC */
AnnaBridge 171:3a7713b1edbc 1436 #define _DMA_CHPRIC_CH10PRIC_MASK 0x400UL /**< Bit mask for DMA_CH10PRIC */
AnnaBridge 171:3a7713b1edbc 1437 #define _DMA_CHPRIC_CH10PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1438 #define DMA_CHPRIC_CH10PRIC_DEFAULT (_DMA_CHPRIC_CH10PRIC_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1439 #define DMA_CHPRIC_CH11PRIC (0x1UL << 11) /**< Channel 11 High Priority Clear */
AnnaBridge 171:3a7713b1edbc 1440 #define _DMA_CHPRIC_CH11PRIC_SHIFT 11 /**< Shift value for DMA_CH11PRIC */
AnnaBridge 171:3a7713b1edbc 1441 #define _DMA_CHPRIC_CH11PRIC_MASK 0x800UL /**< Bit mask for DMA_CH11PRIC */
AnnaBridge 171:3a7713b1edbc 1442 #define _DMA_CHPRIC_CH11PRIC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1443 #define DMA_CHPRIC_CH11PRIC_DEFAULT (_DMA_CHPRIC_CH11PRIC_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHPRIC */
AnnaBridge 171:3a7713b1edbc 1444
AnnaBridge 171:3a7713b1edbc 1445 /* Bit fields for DMA ERRORC */
AnnaBridge 171:3a7713b1edbc 1446 #define _DMA_ERRORC_RESETVALUE 0x00000000UL /**< Default value for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 1447 #define _DMA_ERRORC_MASK 0x00000001UL /**< Mask for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 1448 #define DMA_ERRORC_ERRORC (0x1UL << 0) /**< Bus Error Clear */
AnnaBridge 171:3a7713b1edbc 1449 #define _DMA_ERRORC_ERRORC_SHIFT 0 /**< Shift value for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 1450 #define _DMA_ERRORC_ERRORC_MASK 0x1UL /**< Bit mask for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 1451 #define _DMA_ERRORC_ERRORC_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 1452 #define DMA_ERRORC_ERRORC_DEFAULT (_DMA_ERRORC_ERRORC_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_ERRORC */
AnnaBridge 171:3a7713b1edbc 1453
AnnaBridge 171:3a7713b1edbc 1454 /* Bit fields for DMA CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1455 #define _DMA_CHREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1456 #define _DMA_CHREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1457 #define DMA_CHREQSTATUS_CH0REQSTATUS (0x1UL << 0) /**< Channel 0 Request Status */
AnnaBridge 171:3a7713b1edbc 1458 #define _DMA_CHREQSTATUS_CH0REQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1459 #define _DMA_CHREQSTATUS_CH0REQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1460 #define _DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1461 #define DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH0REQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1462 #define DMA_CHREQSTATUS_CH1REQSTATUS (0x1UL << 1) /**< Channel 1 Request Status */
AnnaBridge 171:3a7713b1edbc 1463 #define _DMA_CHREQSTATUS_CH1REQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1464 #define _DMA_CHREQSTATUS_CH1REQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1465 #define _DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1466 #define DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH1REQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1467 #define DMA_CHREQSTATUS_CH2REQSTATUS (0x1UL << 2) /**< Channel 2 Request Status */
AnnaBridge 171:3a7713b1edbc 1468 #define _DMA_CHREQSTATUS_CH2REQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1469 #define _DMA_CHREQSTATUS_CH2REQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1470 #define _DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1471 #define DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH2REQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1472 #define DMA_CHREQSTATUS_CH3REQSTATUS (0x1UL << 3) /**< Channel 3 Request Status */
AnnaBridge 171:3a7713b1edbc 1473 #define _DMA_CHREQSTATUS_CH3REQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1474 #define _DMA_CHREQSTATUS_CH3REQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1475 #define _DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1476 #define DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH3REQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1477 #define DMA_CHREQSTATUS_CH4REQSTATUS (0x1UL << 4) /**< Channel 4 Request Status */
AnnaBridge 171:3a7713b1edbc 1478 #define _DMA_CHREQSTATUS_CH4REQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1479 #define _DMA_CHREQSTATUS_CH4REQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1480 #define _DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1481 #define DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH4REQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1482 #define DMA_CHREQSTATUS_CH5REQSTATUS (0x1UL << 5) /**< Channel 5 Request Status */
AnnaBridge 171:3a7713b1edbc 1483 #define _DMA_CHREQSTATUS_CH5REQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1484 #define _DMA_CHREQSTATUS_CH5REQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1485 #define _DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1486 #define DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH5REQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1487 #define DMA_CHREQSTATUS_CH6REQSTATUS (0x1UL << 6) /**< Channel 6 Request Status */
AnnaBridge 171:3a7713b1edbc 1488 #define _DMA_CHREQSTATUS_CH6REQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1489 #define _DMA_CHREQSTATUS_CH6REQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1490 #define _DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1491 #define DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH6REQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1492 #define DMA_CHREQSTATUS_CH7REQSTATUS (0x1UL << 7) /**< Channel 7 Request Status */
AnnaBridge 171:3a7713b1edbc 1493 #define _DMA_CHREQSTATUS_CH7REQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1494 #define _DMA_CHREQSTATUS_CH7REQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1495 #define _DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1496 #define DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH7REQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1497 #define DMA_CHREQSTATUS_CH8REQSTATUS (0x1UL << 8) /**< Channel 8 Request Status */
AnnaBridge 171:3a7713b1edbc 1498 #define _DMA_CHREQSTATUS_CH8REQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1499 #define _DMA_CHREQSTATUS_CH8REQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1500 #define _DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1501 #define DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH8REQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1502 #define DMA_CHREQSTATUS_CH9REQSTATUS (0x1UL << 9) /**< Channel 9 Request Status */
AnnaBridge 171:3a7713b1edbc 1503 #define _DMA_CHREQSTATUS_CH9REQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1504 #define _DMA_CHREQSTATUS_CH9REQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1505 #define _DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1506 #define DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH9REQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1507 #define DMA_CHREQSTATUS_CH10REQSTATUS (0x1UL << 10) /**< Channel 10 Request Status */
AnnaBridge 171:3a7713b1edbc 1508 #define _DMA_CHREQSTATUS_CH10REQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1509 #define _DMA_CHREQSTATUS_CH10REQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1510 #define _DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1511 #define DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH10REQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1512 #define DMA_CHREQSTATUS_CH11REQSTATUS (0x1UL << 11) /**< Channel 11 Request Status */
AnnaBridge 171:3a7713b1edbc 1513 #define _DMA_CHREQSTATUS_CH11REQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1514 #define _DMA_CHREQSTATUS_CH11REQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11REQSTATUS */
AnnaBridge 171:3a7713b1edbc 1515 #define _DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1516 #define DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT (_DMA_CHREQSTATUS_CH11REQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1517
AnnaBridge 171:3a7713b1edbc 1518 /* Bit fields for DMA CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1519 #define _DMA_CHSREQSTATUS_RESETVALUE 0x00000000UL /**< Default value for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1520 #define _DMA_CHSREQSTATUS_MASK 0x00000FFFUL /**< Mask for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1521 #define DMA_CHSREQSTATUS_CH0SREQSTATUS (0x1UL << 0) /**< Channel 0 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1522 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_SHIFT 0 /**< Shift value for DMA_CH0SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1523 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_MASK 0x1UL /**< Bit mask for DMA_CH0SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1524 #define _DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1525 #define DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH0SREQSTATUS_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1526 #define DMA_CHSREQSTATUS_CH1SREQSTATUS (0x1UL << 1) /**< Channel 1 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1527 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_SHIFT 1 /**< Shift value for DMA_CH1SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1528 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_MASK 0x2UL /**< Bit mask for DMA_CH1SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1529 #define _DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1530 #define DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH1SREQSTATUS_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1531 #define DMA_CHSREQSTATUS_CH2SREQSTATUS (0x1UL << 2) /**< Channel 2 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1532 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_SHIFT 2 /**< Shift value for DMA_CH2SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1533 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_MASK 0x4UL /**< Bit mask for DMA_CH2SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1534 #define _DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1535 #define DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH2SREQSTATUS_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1536 #define DMA_CHSREQSTATUS_CH3SREQSTATUS (0x1UL << 3) /**< Channel 3 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1537 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_SHIFT 3 /**< Shift value for DMA_CH3SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1538 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_MASK 0x8UL /**< Bit mask for DMA_CH3SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1539 #define _DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1540 #define DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH3SREQSTATUS_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1541 #define DMA_CHSREQSTATUS_CH4SREQSTATUS (0x1UL << 4) /**< Channel 4 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1542 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_SHIFT 4 /**< Shift value for DMA_CH4SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1543 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_MASK 0x10UL /**< Bit mask for DMA_CH4SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1544 #define _DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1545 #define DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH4SREQSTATUS_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1546 #define DMA_CHSREQSTATUS_CH5SREQSTATUS (0x1UL << 5) /**< Channel 5 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1547 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_SHIFT 5 /**< Shift value for DMA_CH5SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1548 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_MASK 0x20UL /**< Bit mask for DMA_CH5SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1549 #define _DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1550 #define DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH5SREQSTATUS_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1551 #define DMA_CHSREQSTATUS_CH6SREQSTATUS (0x1UL << 6) /**< Channel 6 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1552 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_SHIFT 6 /**< Shift value for DMA_CH6SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1553 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_MASK 0x40UL /**< Bit mask for DMA_CH6SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1554 #define _DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1555 #define DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH6SREQSTATUS_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1556 #define DMA_CHSREQSTATUS_CH7SREQSTATUS (0x1UL << 7) /**< Channel 7 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1557 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_SHIFT 7 /**< Shift value for DMA_CH7SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1558 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_MASK 0x80UL /**< Bit mask for DMA_CH7SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1559 #define _DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1560 #define DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH7SREQSTATUS_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1561 #define DMA_CHSREQSTATUS_CH8SREQSTATUS (0x1UL << 8) /**< Channel 8 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1562 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_SHIFT 8 /**< Shift value for DMA_CH8SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1563 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_MASK 0x100UL /**< Bit mask for DMA_CH8SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1564 #define _DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1565 #define DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH8SREQSTATUS_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1566 #define DMA_CHSREQSTATUS_CH9SREQSTATUS (0x1UL << 9) /**< Channel 9 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1567 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_SHIFT 9 /**< Shift value for DMA_CH9SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1568 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_MASK 0x200UL /**< Bit mask for DMA_CH9SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1569 #define _DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1570 #define DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH9SREQSTATUS_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1571 #define DMA_CHSREQSTATUS_CH10SREQSTATUS (0x1UL << 10) /**< Channel 10 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1572 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_SHIFT 10 /**< Shift value for DMA_CH10SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1573 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_MASK 0x400UL /**< Bit mask for DMA_CH10SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1574 #define _DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1575 #define DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH10SREQSTATUS_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1576 #define DMA_CHSREQSTATUS_CH11SREQSTATUS (0x1UL << 11) /**< Channel 11 Single Request Status */
AnnaBridge 171:3a7713b1edbc 1577 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_SHIFT 11 /**< Shift value for DMA_CH11SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1578 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_MASK 0x800UL /**< Bit mask for DMA_CH11SREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1579 #define _DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1580 #define DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT (_DMA_CHSREQSTATUS_CH11SREQSTATUS_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_CHSREQSTATUS */
AnnaBridge 171:3a7713b1edbc 1581
AnnaBridge 171:3a7713b1edbc 1582 /* Bit fields for DMA IF */
AnnaBridge 171:3a7713b1edbc 1583 #define _DMA_IF_RESETVALUE 0x00000000UL /**< Default value for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1584 #define _DMA_IF_MASK 0x80000FFFUL /**< Mask for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1585 #define DMA_IF_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1586 #define _DMA_IF_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1587 #define _DMA_IF_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1588 #define _DMA_IF_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1589 #define DMA_IF_CH0DONE_DEFAULT (_DMA_IF_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1590 #define DMA_IF_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1591 #define _DMA_IF_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1592 #define _DMA_IF_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1593 #define _DMA_IF_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1594 #define DMA_IF_CH1DONE_DEFAULT (_DMA_IF_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1595 #define DMA_IF_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1596 #define _DMA_IF_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1597 #define _DMA_IF_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1598 #define _DMA_IF_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1599 #define DMA_IF_CH2DONE_DEFAULT (_DMA_IF_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1600 #define DMA_IF_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1601 #define _DMA_IF_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1602 #define _DMA_IF_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1603 #define _DMA_IF_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1604 #define DMA_IF_CH3DONE_DEFAULT (_DMA_IF_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1605 #define DMA_IF_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1606 #define _DMA_IF_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1607 #define _DMA_IF_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1608 #define _DMA_IF_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1609 #define DMA_IF_CH4DONE_DEFAULT (_DMA_IF_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1610 #define DMA_IF_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1611 #define _DMA_IF_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1612 #define _DMA_IF_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1613 #define _DMA_IF_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1614 #define DMA_IF_CH5DONE_DEFAULT (_DMA_IF_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1615 #define DMA_IF_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1616 #define _DMA_IF_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1617 #define _DMA_IF_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1618 #define _DMA_IF_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1619 #define DMA_IF_CH6DONE_DEFAULT (_DMA_IF_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1620 #define DMA_IF_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1621 #define _DMA_IF_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1622 #define _DMA_IF_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1623 #define _DMA_IF_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1624 #define DMA_IF_CH7DONE_DEFAULT (_DMA_IF_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1625 #define DMA_IF_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1626 #define _DMA_IF_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1627 #define _DMA_IF_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1628 #define _DMA_IF_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1629 #define DMA_IF_CH8DONE_DEFAULT (_DMA_IF_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1630 #define DMA_IF_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1631 #define _DMA_IF_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1632 #define _DMA_IF_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1633 #define _DMA_IF_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1634 #define DMA_IF_CH9DONE_DEFAULT (_DMA_IF_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1635 #define DMA_IF_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1636 #define _DMA_IF_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1637 #define _DMA_IF_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1638 #define _DMA_IF_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1639 #define DMA_IF_CH10DONE_DEFAULT (_DMA_IF_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1640 #define DMA_IF_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1641 #define _DMA_IF_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1642 #define _DMA_IF_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1643 #define _DMA_IF_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1644 #define DMA_IF_CH11DONE_DEFAULT (_DMA_IF_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1645 #define DMA_IF_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 1646 #define _DMA_IF_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1647 #define _DMA_IF_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1648 #define _DMA_IF_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1649 #define DMA_IF_ERR_DEFAULT (_DMA_IF_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IF */
AnnaBridge 171:3a7713b1edbc 1650
AnnaBridge 171:3a7713b1edbc 1651 /* Bit fields for DMA IFS */
AnnaBridge 171:3a7713b1edbc 1652 #define _DMA_IFS_RESETVALUE 0x00000000UL /**< Default value for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1653 #define _DMA_IFS_MASK 0x80000FFFUL /**< Mask for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1654 #define DMA_IFS_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1655 #define _DMA_IFS_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1656 #define _DMA_IFS_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1657 #define _DMA_IFS_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1658 #define DMA_IFS_CH0DONE_DEFAULT (_DMA_IFS_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1659 #define DMA_IFS_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1660 #define _DMA_IFS_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1661 #define _DMA_IFS_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1662 #define _DMA_IFS_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1663 #define DMA_IFS_CH1DONE_DEFAULT (_DMA_IFS_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1664 #define DMA_IFS_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1665 #define _DMA_IFS_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1666 #define _DMA_IFS_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1667 #define _DMA_IFS_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1668 #define DMA_IFS_CH2DONE_DEFAULT (_DMA_IFS_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1669 #define DMA_IFS_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1670 #define _DMA_IFS_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1671 #define _DMA_IFS_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1672 #define _DMA_IFS_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1673 #define DMA_IFS_CH3DONE_DEFAULT (_DMA_IFS_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1674 #define DMA_IFS_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1675 #define _DMA_IFS_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1676 #define _DMA_IFS_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1677 #define _DMA_IFS_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1678 #define DMA_IFS_CH4DONE_DEFAULT (_DMA_IFS_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1679 #define DMA_IFS_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1680 #define _DMA_IFS_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1681 #define _DMA_IFS_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1682 #define _DMA_IFS_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1683 #define DMA_IFS_CH5DONE_DEFAULT (_DMA_IFS_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1684 #define DMA_IFS_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1685 #define _DMA_IFS_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1686 #define _DMA_IFS_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1687 #define _DMA_IFS_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1688 #define DMA_IFS_CH6DONE_DEFAULT (_DMA_IFS_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1689 #define DMA_IFS_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1690 #define _DMA_IFS_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1691 #define _DMA_IFS_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1692 #define _DMA_IFS_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1693 #define DMA_IFS_CH7DONE_DEFAULT (_DMA_IFS_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1694 #define DMA_IFS_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1695 #define _DMA_IFS_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1696 #define _DMA_IFS_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1697 #define _DMA_IFS_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1698 #define DMA_IFS_CH8DONE_DEFAULT (_DMA_IFS_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1699 #define DMA_IFS_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1700 #define _DMA_IFS_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1701 #define _DMA_IFS_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1702 #define _DMA_IFS_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1703 #define DMA_IFS_CH9DONE_DEFAULT (_DMA_IFS_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1704 #define DMA_IFS_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1705 #define _DMA_IFS_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1706 #define _DMA_IFS_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1707 #define _DMA_IFS_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1708 #define DMA_IFS_CH10DONE_DEFAULT (_DMA_IFS_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1709 #define DMA_IFS_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1710 #define _DMA_IFS_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1711 #define _DMA_IFS_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1712 #define _DMA_IFS_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1713 #define DMA_IFS_CH11DONE_DEFAULT (_DMA_IFS_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1714 #define DMA_IFS_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 1715 #define _DMA_IFS_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1716 #define _DMA_IFS_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1717 #define _DMA_IFS_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1718 #define DMA_IFS_ERR_DEFAULT (_DMA_IFS_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFS */
AnnaBridge 171:3a7713b1edbc 1719
AnnaBridge 171:3a7713b1edbc 1720 /* Bit fields for DMA IFC */
AnnaBridge 171:3a7713b1edbc 1721 #define _DMA_IFC_RESETVALUE 0x00000000UL /**< Default value for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1722 #define _DMA_IFC_MASK 0x80000FFFUL /**< Mask for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1723 #define DMA_IFC_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1724 #define _DMA_IFC_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1725 #define _DMA_IFC_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1726 #define _DMA_IFC_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1727 #define DMA_IFC_CH0DONE_DEFAULT (_DMA_IFC_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1728 #define DMA_IFC_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1729 #define _DMA_IFC_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1730 #define _DMA_IFC_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1731 #define _DMA_IFC_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1732 #define DMA_IFC_CH1DONE_DEFAULT (_DMA_IFC_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1733 #define DMA_IFC_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1734 #define _DMA_IFC_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1735 #define _DMA_IFC_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1736 #define _DMA_IFC_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1737 #define DMA_IFC_CH2DONE_DEFAULT (_DMA_IFC_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1738 #define DMA_IFC_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1739 #define _DMA_IFC_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1740 #define _DMA_IFC_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1741 #define _DMA_IFC_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1742 #define DMA_IFC_CH3DONE_DEFAULT (_DMA_IFC_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1743 #define DMA_IFC_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1744 #define _DMA_IFC_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1745 #define _DMA_IFC_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1746 #define _DMA_IFC_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1747 #define DMA_IFC_CH4DONE_DEFAULT (_DMA_IFC_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1748 #define DMA_IFC_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1749 #define _DMA_IFC_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1750 #define _DMA_IFC_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1751 #define _DMA_IFC_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1752 #define DMA_IFC_CH5DONE_DEFAULT (_DMA_IFC_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1753 #define DMA_IFC_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1754 #define _DMA_IFC_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1755 #define _DMA_IFC_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1756 #define _DMA_IFC_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1757 #define DMA_IFC_CH6DONE_DEFAULT (_DMA_IFC_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1758 #define DMA_IFC_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1759 #define _DMA_IFC_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1760 #define _DMA_IFC_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1761 #define _DMA_IFC_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1762 #define DMA_IFC_CH7DONE_DEFAULT (_DMA_IFC_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1763 #define DMA_IFC_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1764 #define _DMA_IFC_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1765 #define _DMA_IFC_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1766 #define _DMA_IFC_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1767 #define DMA_IFC_CH8DONE_DEFAULT (_DMA_IFC_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1768 #define DMA_IFC_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1769 #define _DMA_IFC_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1770 #define _DMA_IFC_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1771 #define _DMA_IFC_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1772 #define DMA_IFC_CH9DONE_DEFAULT (_DMA_IFC_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1773 #define DMA_IFC_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1774 #define _DMA_IFC_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1775 #define _DMA_IFC_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1776 #define _DMA_IFC_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1777 #define DMA_IFC_CH10DONE_DEFAULT (_DMA_IFC_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1778 #define DMA_IFC_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1779 #define _DMA_IFC_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1780 #define _DMA_IFC_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1781 #define _DMA_IFC_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1782 #define DMA_IFC_CH11DONE_DEFAULT (_DMA_IFC_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1783 #define DMA_IFC_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 1784 #define _DMA_IFC_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1785 #define _DMA_IFC_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1786 #define _DMA_IFC_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1787 #define DMA_IFC_ERR_DEFAULT (_DMA_IFC_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IFC */
AnnaBridge 171:3a7713b1edbc 1788
AnnaBridge 171:3a7713b1edbc 1789 /* Bit fields for DMA IEN */
AnnaBridge 171:3a7713b1edbc 1790 #define _DMA_IEN_RESETVALUE 0x00000000UL /**< Default value for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1791 #define _DMA_IEN_MASK 0x80000FFFUL /**< Mask for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1792 #define DMA_IEN_CH0DONE (0x1UL << 0) /**< DMA Channel 0 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1793 #define _DMA_IEN_CH0DONE_SHIFT 0 /**< Shift value for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1794 #define _DMA_IEN_CH0DONE_MASK 0x1UL /**< Bit mask for DMA_CH0DONE */
AnnaBridge 171:3a7713b1edbc 1795 #define _DMA_IEN_CH0DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1796 #define DMA_IEN_CH0DONE_DEFAULT (_DMA_IEN_CH0DONE_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1797 #define DMA_IEN_CH1DONE (0x1UL << 1) /**< DMA Channel 1 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1798 #define _DMA_IEN_CH1DONE_SHIFT 1 /**< Shift value for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1799 #define _DMA_IEN_CH1DONE_MASK 0x2UL /**< Bit mask for DMA_CH1DONE */
AnnaBridge 171:3a7713b1edbc 1800 #define _DMA_IEN_CH1DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1801 #define DMA_IEN_CH1DONE_DEFAULT (_DMA_IEN_CH1DONE_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1802 #define DMA_IEN_CH2DONE (0x1UL << 2) /**< DMA Channel 2 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1803 #define _DMA_IEN_CH2DONE_SHIFT 2 /**< Shift value for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1804 #define _DMA_IEN_CH2DONE_MASK 0x4UL /**< Bit mask for DMA_CH2DONE */
AnnaBridge 171:3a7713b1edbc 1805 #define _DMA_IEN_CH2DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1806 #define DMA_IEN_CH2DONE_DEFAULT (_DMA_IEN_CH2DONE_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1807 #define DMA_IEN_CH3DONE (0x1UL << 3) /**< DMA Channel 3 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1808 #define _DMA_IEN_CH3DONE_SHIFT 3 /**< Shift value for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1809 #define _DMA_IEN_CH3DONE_MASK 0x8UL /**< Bit mask for DMA_CH3DONE */
AnnaBridge 171:3a7713b1edbc 1810 #define _DMA_IEN_CH3DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1811 #define DMA_IEN_CH3DONE_DEFAULT (_DMA_IEN_CH3DONE_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1812 #define DMA_IEN_CH4DONE (0x1UL << 4) /**< DMA Channel 4 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1813 #define _DMA_IEN_CH4DONE_SHIFT 4 /**< Shift value for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1814 #define _DMA_IEN_CH4DONE_MASK 0x10UL /**< Bit mask for DMA_CH4DONE */
AnnaBridge 171:3a7713b1edbc 1815 #define _DMA_IEN_CH4DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1816 #define DMA_IEN_CH4DONE_DEFAULT (_DMA_IEN_CH4DONE_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1817 #define DMA_IEN_CH5DONE (0x1UL << 5) /**< DMA Channel 5 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1818 #define _DMA_IEN_CH5DONE_SHIFT 5 /**< Shift value for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1819 #define _DMA_IEN_CH5DONE_MASK 0x20UL /**< Bit mask for DMA_CH5DONE */
AnnaBridge 171:3a7713b1edbc 1820 #define _DMA_IEN_CH5DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1821 #define DMA_IEN_CH5DONE_DEFAULT (_DMA_IEN_CH5DONE_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1822 #define DMA_IEN_CH6DONE (0x1UL << 6) /**< DMA Channel 6 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1823 #define _DMA_IEN_CH6DONE_SHIFT 6 /**< Shift value for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1824 #define _DMA_IEN_CH6DONE_MASK 0x40UL /**< Bit mask for DMA_CH6DONE */
AnnaBridge 171:3a7713b1edbc 1825 #define _DMA_IEN_CH6DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1826 #define DMA_IEN_CH6DONE_DEFAULT (_DMA_IEN_CH6DONE_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1827 #define DMA_IEN_CH7DONE (0x1UL << 7) /**< DMA Channel 7 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1828 #define _DMA_IEN_CH7DONE_SHIFT 7 /**< Shift value for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1829 #define _DMA_IEN_CH7DONE_MASK 0x80UL /**< Bit mask for DMA_CH7DONE */
AnnaBridge 171:3a7713b1edbc 1830 #define _DMA_IEN_CH7DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1831 #define DMA_IEN_CH7DONE_DEFAULT (_DMA_IEN_CH7DONE_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1832 #define DMA_IEN_CH8DONE (0x1UL << 8) /**< DMA Channel 8 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1833 #define _DMA_IEN_CH8DONE_SHIFT 8 /**< Shift value for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1834 #define _DMA_IEN_CH8DONE_MASK 0x100UL /**< Bit mask for DMA_CH8DONE */
AnnaBridge 171:3a7713b1edbc 1835 #define _DMA_IEN_CH8DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1836 #define DMA_IEN_CH8DONE_DEFAULT (_DMA_IEN_CH8DONE_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1837 #define DMA_IEN_CH9DONE (0x1UL << 9) /**< DMA Channel 9 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1838 #define _DMA_IEN_CH9DONE_SHIFT 9 /**< Shift value for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1839 #define _DMA_IEN_CH9DONE_MASK 0x200UL /**< Bit mask for DMA_CH9DONE */
AnnaBridge 171:3a7713b1edbc 1840 #define _DMA_IEN_CH9DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1841 #define DMA_IEN_CH9DONE_DEFAULT (_DMA_IEN_CH9DONE_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1842 #define DMA_IEN_CH10DONE (0x1UL << 10) /**< DMA Channel 10 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1843 #define _DMA_IEN_CH10DONE_SHIFT 10 /**< Shift value for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1844 #define _DMA_IEN_CH10DONE_MASK 0x400UL /**< Bit mask for DMA_CH10DONE */
AnnaBridge 171:3a7713b1edbc 1845 #define _DMA_IEN_CH10DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1846 #define DMA_IEN_CH10DONE_DEFAULT (_DMA_IEN_CH10DONE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1847 #define DMA_IEN_CH11DONE (0x1UL << 11) /**< DMA Channel 11 Complete Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 1848 #define _DMA_IEN_CH11DONE_SHIFT 11 /**< Shift value for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1849 #define _DMA_IEN_CH11DONE_MASK 0x800UL /**< Bit mask for DMA_CH11DONE */
AnnaBridge 171:3a7713b1edbc 1850 #define _DMA_IEN_CH11DONE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1851 #define DMA_IEN_CH11DONE_DEFAULT (_DMA_IEN_CH11DONE_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1852 #define DMA_IEN_ERR (0x1UL << 31) /**< DMA Error Interrupt Flag Enable */
AnnaBridge 171:3a7713b1edbc 1853 #define _DMA_IEN_ERR_SHIFT 31 /**< Shift value for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1854 #define _DMA_IEN_ERR_MASK 0x80000000UL /**< Bit mask for DMA_ERR */
AnnaBridge 171:3a7713b1edbc 1855 #define _DMA_IEN_ERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1856 #define DMA_IEN_ERR_DEFAULT (_DMA_IEN_ERR_DEFAULT << 31) /**< Shifted mode DEFAULT for DMA_IEN */
AnnaBridge 171:3a7713b1edbc 1857
AnnaBridge 171:3a7713b1edbc 1858 /* Bit fields for DMA CTRL */
AnnaBridge 171:3a7713b1edbc 1859 #define _DMA_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CTRL */
AnnaBridge 171:3a7713b1edbc 1860 #define _DMA_CTRL_MASK 0x00000003UL /**< Mask for DMA_CTRL */
AnnaBridge 171:3a7713b1edbc 1861 #define DMA_CTRL_DESCRECT (0x1UL << 0) /**< Descriptor Specifies Rectangle */
AnnaBridge 171:3a7713b1edbc 1862 #define _DMA_CTRL_DESCRECT_SHIFT 0 /**< Shift value for DMA_DESCRECT */
AnnaBridge 171:3a7713b1edbc 1863 #define _DMA_CTRL_DESCRECT_MASK 0x1UL /**< Bit mask for DMA_DESCRECT */
AnnaBridge 171:3a7713b1edbc 1864 #define _DMA_CTRL_DESCRECT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
AnnaBridge 171:3a7713b1edbc 1865 #define DMA_CTRL_DESCRECT_DEFAULT (_DMA_CTRL_DESCRECT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_CTRL */
AnnaBridge 171:3a7713b1edbc 1866 #define DMA_CTRL_PRDU (0x1UL << 1) /**< Prevent Rect Descriptor Update */
AnnaBridge 171:3a7713b1edbc 1867 #define _DMA_CTRL_PRDU_SHIFT 1 /**< Shift value for DMA_PRDU */
AnnaBridge 171:3a7713b1edbc 1868 #define _DMA_CTRL_PRDU_MASK 0x2UL /**< Bit mask for DMA_PRDU */
AnnaBridge 171:3a7713b1edbc 1869 #define _DMA_CTRL_PRDU_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_CTRL */
AnnaBridge 171:3a7713b1edbc 1870 #define DMA_CTRL_PRDU_DEFAULT (_DMA_CTRL_PRDU_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_CTRL */
AnnaBridge 171:3a7713b1edbc 1871
AnnaBridge 171:3a7713b1edbc 1872 /* Bit fields for DMA RDS */
AnnaBridge 171:3a7713b1edbc 1873 #define _DMA_RDS_RESETVALUE 0x00000000UL /**< Default value for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1874 #define _DMA_RDS_MASK 0x00000FFFUL /**< Mask for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1875 #define DMA_RDS_RDSCH0 (0x1UL << 0) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1876 #define _DMA_RDS_RDSCH0_SHIFT 0 /**< Shift value for DMA_RDSCH0 */
AnnaBridge 171:3a7713b1edbc 1877 #define _DMA_RDS_RDSCH0_MASK 0x1UL /**< Bit mask for DMA_RDSCH0 */
AnnaBridge 171:3a7713b1edbc 1878 #define _DMA_RDS_RDSCH0_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1879 #define DMA_RDS_RDSCH0_DEFAULT (_DMA_RDS_RDSCH0_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1880 #define DMA_RDS_RDSCH1 (0x1UL << 1) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1881 #define _DMA_RDS_RDSCH1_SHIFT 1 /**< Shift value for DMA_RDSCH1 */
AnnaBridge 171:3a7713b1edbc 1882 #define _DMA_RDS_RDSCH1_MASK 0x2UL /**< Bit mask for DMA_RDSCH1 */
AnnaBridge 171:3a7713b1edbc 1883 #define _DMA_RDS_RDSCH1_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1884 #define DMA_RDS_RDSCH1_DEFAULT (_DMA_RDS_RDSCH1_DEFAULT << 1) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1885 #define DMA_RDS_RDSCH2 (0x1UL << 2) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1886 #define _DMA_RDS_RDSCH2_SHIFT 2 /**< Shift value for DMA_RDSCH2 */
AnnaBridge 171:3a7713b1edbc 1887 #define _DMA_RDS_RDSCH2_MASK 0x4UL /**< Bit mask for DMA_RDSCH2 */
AnnaBridge 171:3a7713b1edbc 1888 #define _DMA_RDS_RDSCH2_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1889 #define DMA_RDS_RDSCH2_DEFAULT (_DMA_RDS_RDSCH2_DEFAULT << 2) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1890 #define DMA_RDS_RDSCH3 (0x1UL << 3) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1891 #define _DMA_RDS_RDSCH3_SHIFT 3 /**< Shift value for DMA_RDSCH3 */
AnnaBridge 171:3a7713b1edbc 1892 #define _DMA_RDS_RDSCH3_MASK 0x8UL /**< Bit mask for DMA_RDSCH3 */
AnnaBridge 171:3a7713b1edbc 1893 #define _DMA_RDS_RDSCH3_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1894 #define DMA_RDS_RDSCH3_DEFAULT (_DMA_RDS_RDSCH3_DEFAULT << 3) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1895 #define DMA_RDS_RDSCH4 (0x1UL << 4) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1896 #define _DMA_RDS_RDSCH4_SHIFT 4 /**< Shift value for DMA_RDSCH4 */
AnnaBridge 171:3a7713b1edbc 1897 #define _DMA_RDS_RDSCH4_MASK 0x10UL /**< Bit mask for DMA_RDSCH4 */
AnnaBridge 171:3a7713b1edbc 1898 #define _DMA_RDS_RDSCH4_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1899 #define DMA_RDS_RDSCH4_DEFAULT (_DMA_RDS_RDSCH4_DEFAULT << 4) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1900 #define DMA_RDS_RDSCH5 (0x1UL << 5) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1901 #define _DMA_RDS_RDSCH5_SHIFT 5 /**< Shift value for DMA_RDSCH5 */
AnnaBridge 171:3a7713b1edbc 1902 #define _DMA_RDS_RDSCH5_MASK 0x20UL /**< Bit mask for DMA_RDSCH5 */
AnnaBridge 171:3a7713b1edbc 1903 #define _DMA_RDS_RDSCH5_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1904 #define DMA_RDS_RDSCH5_DEFAULT (_DMA_RDS_RDSCH5_DEFAULT << 5) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1905 #define DMA_RDS_RDSCH6 (0x1UL << 6) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1906 #define _DMA_RDS_RDSCH6_SHIFT 6 /**< Shift value for DMA_RDSCH6 */
AnnaBridge 171:3a7713b1edbc 1907 #define _DMA_RDS_RDSCH6_MASK 0x40UL /**< Bit mask for DMA_RDSCH6 */
AnnaBridge 171:3a7713b1edbc 1908 #define _DMA_RDS_RDSCH6_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1909 #define DMA_RDS_RDSCH6_DEFAULT (_DMA_RDS_RDSCH6_DEFAULT << 6) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1910 #define DMA_RDS_RDSCH7 (0x1UL << 7) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1911 #define _DMA_RDS_RDSCH7_SHIFT 7 /**< Shift value for DMA_RDSCH7 */
AnnaBridge 171:3a7713b1edbc 1912 #define _DMA_RDS_RDSCH7_MASK 0x80UL /**< Bit mask for DMA_RDSCH7 */
AnnaBridge 171:3a7713b1edbc 1913 #define _DMA_RDS_RDSCH7_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1914 #define DMA_RDS_RDSCH7_DEFAULT (_DMA_RDS_RDSCH7_DEFAULT << 7) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1915 #define DMA_RDS_RDSCH8 (0x1UL << 8) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1916 #define _DMA_RDS_RDSCH8_SHIFT 8 /**< Shift value for DMA_RDSCH8 */
AnnaBridge 171:3a7713b1edbc 1917 #define _DMA_RDS_RDSCH8_MASK 0x100UL /**< Bit mask for DMA_RDSCH8 */
AnnaBridge 171:3a7713b1edbc 1918 #define _DMA_RDS_RDSCH8_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1919 #define DMA_RDS_RDSCH8_DEFAULT (_DMA_RDS_RDSCH8_DEFAULT << 8) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1920 #define DMA_RDS_RDSCH9 (0x1UL << 9) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1921 #define _DMA_RDS_RDSCH9_SHIFT 9 /**< Shift value for DMA_RDSCH9 */
AnnaBridge 171:3a7713b1edbc 1922 #define _DMA_RDS_RDSCH9_MASK 0x200UL /**< Bit mask for DMA_RDSCH9 */
AnnaBridge 171:3a7713b1edbc 1923 #define _DMA_RDS_RDSCH9_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1924 #define DMA_RDS_RDSCH9_DEFAULT (_DMA_RDS_RDSCH9_DEFAULT << 9) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1925 #define DMA_RDS_RDSCH10 (0x1UL << 10) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1926 #define _DMA_RDS_RDSCH10_SHIFT 10 /**< Shift value for DMA_RDSCH10 */
AnnaBridge 171:3a7713b1edbc 1927 #define _DMA_RDS_RDSCH10_MASK 0x400UL /**< Bit mask for DMA_RDSCH10 */
AnnaBridge 171:3a7713b1edbc 1928 #define _DMA_RDS_RDSCH10_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1929 #define DMA_RDS_RDSCH10_DEFAULT (_DMA_RDS_RDSCH10_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1930 #define DMA_RDS_RDSCH11 (0x1UL << 11) /**< Retain Descriptor State */
AnnaBridge 171:3a7713b1edbc 1931 #define _DMA_RDS_RDSCH11_SHIFT 11 /**< Shift value for DMA_RDSCH11 */
AnnaBridge 171:3a7713b1edbc 1932 #define _DMA_RDS_RDSCH11_MASK 0x800UL /**< Bit mask for DMA_RDSCH11 */
AnnaBridge 171:3a7713b1edbc 1933 #define _DMA_RDS_RDSCH11_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1934 #define DMA_RDS_RDSCH11_DEFAULT (_DMA_RDS_RDSCH11_DEFAULT << 11) /**< Shifted mode DEFAULT for DMA_RDS */
AnnaBridge 171:3a7713b1edbc 1935
AnnaBridge 171:3a7713b1edbc 1936 /* Bit fields for DMA LOOP0 */
AnnaBridge 171:3a7713b1edbc 1937 #define _DMA_LOOP0_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP0 */
AnnaBridge 171:3a7713b1edbc 1938 #define _DMA_LOOP0_MASK 0x000103FFUL /**< Mask for DMA_LOOP0 */
AnnaBridge 171:3a7713b1edbc 1939 #define _DMA_LOOP0_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
AnnaBridge 171:3a7713b1edbc 1940 #define _DMA_LOOP0_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
AnnaBridge 171:3a7713b1edbc 1941 #define _DMA_LOOP0_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
AnnaBridge 171:3a7713b1edbc 1942 #define DMA_LOOP0_WIDTH_DEFAULT (_DMA_LOOP0_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP0 */
AnnaBridge 171:3a7713b1edbc 1943 #define DMA_LOOP0_EN (0x1UL << 16) /**< DMA Channel 0 Loop Enable */
AnnaBridge 171:3a7713b1edbc 1944 #define _DMA_LOOP0_EN_SHIFT 16 /**< Shift value for DMA_EN */
AnnaBridge 171:3a7713b1edbc 1945 #define _DMA_LOOP0_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
AnnaBridge 171:3a7713b1edbc 1946 #define _DMA_LOOP0_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP0 */
AnnaBridge 171:3a7713b1edbc 1947 #define DMA_LOOP0_EN_DEFAULT (_DMA_LOOP0_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP0 */
AnnaBridge 171:3a7713b1edbc 1948
AnnaBridge 171:3a7713b1edbc 1949 /* Bit fields for DMA LOOP1 */
AnnaBridge 171:3a7713b1edbc 1950 #define _DMA_LOOP1_RESETVALUE 0x00000000UL /**< Default value for DMA_LOOP1 */
AnnaBridge 171:3a7713b1edbc 1951 #define _DMA_LOOP1_MASK 0x000103FFUL /**< Mask for DMA_LOOP1 */
AnnaBridge 171:3a7713b1edbc 1952 #define _DMA_LOOP1_WIDTH_SHIFT 0 /**< Shift value for DMA_WIDTH */
AnnaBridge 171:3a7713b1edbc 1953 #define _DMA_LOOP1_WIDTH_MASK 0x3FFUL /**< Bit mask for DMA_WIDTH */
AnnaBridge 171:3a7713b1edbc 1954 #define _DMA_LOOP1_WIDTH_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
AnnaBridge 171:3a7713b1edbc 1955 #define DMA_LOOP1_WIDTH_DEFAULT (_DMA_LOOP1_WIDTH_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_LOOP1 */
AnnaBridge 171:3a7713b1edbc 1956 #define DMA_LOOP1_EN (0x1UL << 16) /**< DMA Channel 1 Loop Enable */
AnnaBridge 171:3a7713b1edbc 1957 #define _DMA_LOOP1_EN_SHIFT 16 /**< Shift value for DMA_EN */
AnnaBridge 171:3a7713b1edbc 1958 #define _DMA_LOOP1_EN_MASK 0x10000UL /**< Bit mask for DMA_EN */
AnnaBridge 171:3a7713b1edbc 1959 #define _DMA_LOOP1_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_LOOP1 */
AnnaBridge 171:3a7713b1edbc 1960 #define DMA_LOOP1_EN_DEFAULT (_DMA_LOOP1_EN_DEFAULT << 16) /**< Shifted mode DEFAULT for DMA_LOOP1 */
AnnaBridge 171:3a7713b1edbc 1961
AnnaBridge 171:3a7713b1edbc 1962 /* Bit fields for DMA RECT0 */
AnnaBridge 171:3a7713b1edbc 1963 #define _DMA_RECT0_RESETVALUE 0x00000000UL /**< Default value for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1964 #define _DMA_RECT0_MASK 0xFFFFFFFFUL /**< Mask for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1965 #define _DMA_RECT0_HEIGHT_SHIFT 0 /**< Shift value for DMA_HEIGHT */
AnnaBridge 171:3a7713b1edbc 1966 #define _DMA_RECT0_HEIGHT_MASK 0x3FFUL /**< Bit mask for DMA_HEIGHT */
AnnaBridge 171:3a7713b1edbc 1967 #define _DMA_RECT0_HEIGHT_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1968 #define DMA_RECT0_HEIGHT_DEFAULT (_DMA_RECT0_HEIGHT_DEFAULT << 0) /**< Shifted mode DEFAULT for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1969 #define _DMA_RECT0_SRCSTRIDE_SHIFT 10 /**< Shift value for DMA_SRCSTRIDE */
AnnaBridge 171:3a7713b1edbc 1970 #define _DMA_RECT0_SRCSTRIDE_MASK 0x1FFC00UL /**< Bit mask for DMA_SRCSTRIDE */
AnnaBridge 171:3a7713b1edbc 1971 #define _DMA_RECT0_SRCSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1972 #define DMA_RECT0_SRCSTRIDE_DEFAULT (_DMA_RECT0_SRCSTRIDE_DEFAULT << 10) /**< Shifted mode DEFAULT for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1973 #define _DMA_RECT0_DSTSTRIDE_SHIFT 21 /**< Shift value for DMA_DSTSTRIDE */
AnnaBridge 171:3a7713b1edbc 1974 #define _DMA_RECT0_DSTSTRIDE_MASK 0xFFE00000UL /**< Bit mask for DMA_DSTSTRIDE */
AnnaBridge 171:3a7713b1edbc 1975 #define _DMA_RECT0_DSTSTRIDE_DEFAULT 0x00000000UL /**< Mode DEFAULT for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1976 #define DMA_RECT0_DSTSTRIDE_DEFAULT (_DMA_RECT0_DSTSTRIDE_DEFAULT << 21) /**< Shifted mode DEFAULT for DMA_RECT0 */
AnnaBridge 171:3a7713b1edbc 1977
AnnaBridge 171:3a7713b1edbc 1978 /* Bit fields for DMA CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1979 #define _DMA_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1980 #define _DMA_CH_CTRL_MASK 0x003F000FUL /**< Mask for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1981 #define _DMA_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for DMA_SIGSEL */
AnnaBridge 171:3a7713b1edbc 1982 #define _DMA_CH_CTRL_SIGSEL_MASK 0xFUL /**< Bit mask for DMA_SIGSEL */
AnnaBridge 171:3a7713b1edbc 1983 #define _DMA_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1984 #define _DMA_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1985 #define _DMA_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000000UL /**< Mode USART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1986 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000000UL /**< Mode USART1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1987 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000000UL /**< Mode USART2RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1988 #define _DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV 0x00000000UL /**< Mode LEUART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1989 #define _DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV 0x00000000UL /**< Mode LEUART1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1990 #define _DMA_CH_CTRL_SIGSEL_I2C0RXDATAV 0x00000000UL /**< Mode I2C0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1991 #define _DMA_CH_CTRL_SIGSEL_I2C1RXDATAV 0x00000000UL /**< Mode I2C1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1992 #define _DMA_CH_CTRL_SIGSEL_TIMER0UFOF 0x00000000UL /**< Mode TIMER0UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1993 #define _DMA_CH_CTRL_SIGSEL_TIMER1UFOF 0x00000000UL /**< Mode TIMER1UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1994 #define _DMA_CH_CTRL_SIGSEL_TIMER2UFOF 0x00000000UL /**< Mode TIMER2UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1995 #define _DMA_CH_CTRL_SIGSEL_TIMER3UFOF 0x00000000UL /**< Mode TIMER3UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1996 #define _DMA_CH_CTRL_SIGSEL_MSCWDATA 0x00000000UL /**< Mode MSCWDATA for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1997 #define _DMA_CH_CTRL_SIGSEL_AESDATAWR 0x00000000UL /**< Mode AESDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1998 #define _DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV 0x00000000UL /**< Mode LESENSEBUFDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 1999 #define _DMA_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2000 #define _DMA_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2001 #define _DMA_CH_CTRL_SIGSEL_USART0TXBL 0x00000001UL /**< Mode USART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2002 #define _DMA_CH_CTRL_SIGSEL_USART1TXBL 0x00000001UL /**< Mode USART1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2003 #define _DMA_CH_CTRL_SIGSEL_USART2TXBL 0x00000001UL /**< Mode USART2TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2004 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXBL 0x00000001UL /**< Mode LEUART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2005 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXBL 0x00000001UL /**< Mode LEUART1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2006 #define _DMA_CH_CTRL_SIGSEL_I2C0TXBL 0x00000001UL /**< Mode I2C0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2007 #define _DMA_CH_CTRL_SIGSEL_I2C1TXBL 0x00000001UL /**< Mode I2C1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2008 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC0 0x00000001UL /**< Mode TIMER0CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2009 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC0 0x00000001UL /**< Mode TIMER1CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2010 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC0 0x00000001UL /**< Mode TIMER2CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2011 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC0 0x00000001UL /**< Mode TIMER3CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2012 #define _DMA_CH_CTRL_SIGSEL_AESXORDATAWR 0x00000001UL /**< Mode AESXORDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2013 #define _DMA_CH_CTRL_SIGSEL_USART0TXEMPTY 0x00000002UL /**< Mode USART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2014 #define _DMA_CH_CTRL_SIGSEL_USART1TXEMPTY 0x00000002UL /**< Mode USART1TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2015 #define _DMA_CH_CTRL_SIGSEL_USART2TXEMPTY 0x00000002UL /**< Mode USART2TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2016 #define _DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY 0x00000002UL /**< Mode LEUART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2017 #define _DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY 0x00000002UL /**< Mode LEUART1TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2018 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC1 0x00000002UL /**< Mode TIMER0CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2019 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC1 0x00000002UL /**< Mode TIMER1CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2020 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC1 0x00000002UL /**< Mode TIMER2CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2021 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC1 0x00000002UL /**< Mode TIMER3CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2022 #define _DMA_CH_CTRL_SIGSEL_AESDATARD 0x00000002UL /**< Mode AESDATARD for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2023 #define _DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT 0x00000003UL /**< Mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2024 #define _DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT 0x00000003UL /**< Mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2025 #define _DMA_CH_CTRL_SIGSEL_TIMER0CC2 0x00000003UL /**< Mode TIMER0CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2026 #define _DMA_CH_CTRL_SIGSEL_TIMER1CC2 0x00000003UL /**< Mode TIMER1CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2027 #define _DMA_CH_CTRL_SIGSEL_TIMER2CC2 0x00000003UL /**< Mode TIMER2CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2028 #define _DMA_CH_CTRL_SIGSEL_TIMER3CC2 0x00000003UL /**< Mode TIMER3CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2029 #define _DMA_CH_CTRL_SIGSEL_AESKEYWR 0x00000003UL /**< Mode AESKEYWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2030 #define _DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT 0x00000004UL /**< Mode USART1TXBLRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2031 #define _DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT 0x00000004UL /**< Mode USART2TXBLRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2032 #define DMA_CH_CTRL_SIGSEL_ADC0SINGLE (_DMA_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2033 #define DMA_CH_CTRL_SIGSEL_DAC0CH0 (_DMA_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2034 #define DMA_CH_CTRL_SIGSEL_USART0RXDATAV (_DMA_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2035 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAV (_DMA_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2036 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAV (_DMA_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2037 #define DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART0RXDATAV << 0) /**< Shifted mode LEUART0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2038 #define DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV (_DMA_CH_CTRL_SIGSEL_LEUART1RXDATAV << 0) /**< Shifted mode LEUART1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2039 #define DMA_CH_CTRL_SIGSEL_I2C0RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C0RXDATAV << 0) /**< Shifted mode I2C0RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2040 #define DMA_CH_CTRL_SIGSEL_I2C1RXDATAV (_DMA_CH_CTRL_SIGSEL_I2C1RXDATAV << 0) /**< Shifted mode I2C1RXDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2041 #define DMA_CH_CTRL_SIGSEL_TIMER0UFOF (_DMA_CH_CTRL_SIGSEL_TIMER0UFOF << 0) /**< Shifted mode TIMER0UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2042 #define DMA_CH_CTRL_SIGSEL_TIMER1UFOF (_DMA_CH_CTRL_SIGSEL_TIMER1UFOF << 0) /**< Shifted mode TIMER1UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2043 #define DMA_CH_CTRL_SIGSEL_TIMER2UFOF (_DMA_CH_CTRL_SIGSEL_TIMER2UFOF << 0) /**< Shifted mode TIMER2UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2044 #define DMA_CH_CTRL_SIGSEL_TIMER3UFOF (_DMA_CH_CTRL_SIGSEL_TIMER3UFOF << 0) /**< Shifted mode TIMER3UFOF for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2045 #define DMA_CH_CTRL_SIGSEL_MSCWDATA (_DMA_CH_CTRL_SIGSEL_MSCWDATA << 0) /**< Shifted mode MSCWDATA for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2046 #define DMA_CH_CTRL_SIGSEL_AESDATAWR (_DMA_CH_CTRL_SIGSEL_AESDATAWR << 0) /**< Shifted mode AESDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2047 #define DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV (_DMA_CH_CTRL_SIGSEL_LESENSEBUFDATAV << 0) /**< Shifted mode LESENSEBUFDATAV for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2048 #define DMA_CH_CTRL_SIGSEL_ADC0SCAN (_DMA_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2049 #define DMA_CH_CTRL_SIGSEL_DAC0CH1 (_DMA_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2050 #define DMA_CH_CTRL_SIGSEL_USART0TXBL (_DMA_CH_CTRL_SIGSEL_USART0TXBL << 0) /**< Shifted mode USART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2051 #define DMA_CH_CTRL_SIGSEL_USART1TXBL (_DMA_CH_CTRL_SIGSEL_USART1TXBL << 0) /**< Shifted mode USART1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2052 #define DMA_CH_CTRL_SIGSEL_USART2TXBL (_DMA_CH_CTRL_SIGSEL_USART2TXBL << 0) /**< Shifted mode USART2TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2053 #define DMA_CH_CTRL_SIGSEL_LEUART0TXBL (_DMA_CH_CTRL_SIGSEL_LEUART0TXBL << 0) /**< Shifted mode LEUART0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2054 #define DMA_CH_CTRL_SIGSEL_LEUART1TXBL (_DMA_CH_CTRL_SIGSEL_LEUART1TXBL << 0) /**< Shifted mode LEUART1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2055 #define DMA_CH_CTRL_SIGSEL_I2C0TXBL (_DMA_CH_CTRL_SIGSEL_I2C0TXBL << 0) /**< Shifted mode I2C0TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2056 #define DMA_CH_CTRL_SIGSEL_I2C1TXBL (_DMA_CH_CTRL_SIGSEL_I2C1TXBL << 0) /**< Shifted mode I2C1TXBL for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2057 #define DMA_CH_CTRL_SIGSEL_TIMER0CC0 (_DMA_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2058 #define DMA_CH_CTRL_SIGSEL_TIMER1CC0 (_DMA_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2059 #define DMA_CH_CTRL_SIGSEL_TIMER2CC0 (_DMA_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2060 #define DMA_CH_CTRL_SIGSEL_TIMER3CC0 (_DMA_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2061 #define DMA_CH_CTRL_SIGSEL_AESXORDATAWR (_DMA_CH_CTRL_SIGSEL_AESXORDATAWR << 0) /**< Shifted mode AESXORDATAWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2062 #define DMA_CH_CTRL_SIGSEL_USART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART0TXEMPTY << 0) /**< Shifted mode USART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2063 #define DMA_CH_CTRL_SIGSEL_USART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART1TXEMPTY << 0) /**< Shifted mode USART1TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2064 #define DMA_CH_CTRL_SIGSEL_USART2TXEMPTY (_DMA_CH_CTRL_SIGSEL_USART2TXEMPTY << 0) /**< Shifted mode USART2TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2065 #define DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART0TXEMPTY << 0) /**< Shifted mode LEUART0TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2066 #define DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY (_DMA_CH_CTRL_SIGSEL_LEUART1TXEMPTY << 0) /**< Shifted mode LEUART1TXEMPTY for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2067 #define DMA_CH_CTRL_SIGSEL_TIMER0CC1 (_DMA_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2068 #define DMA_CH_CTRL_SIGSEL_TIMER1CC1 (_DMA_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2069 #define DMA_CH_CTRL_SIGSEL_TIMER2CC1 (_DMA_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2070 #define DMA_CH_CTRL_SIGSEL_TIMER3CC1 (_DMA_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2071 #define DMA_CH_CTRL_SIGSEL_AESDATARD (_DMA_CH_CTRL_SIGSEL_AESDATARD << 0) /**< Shifted mode AESDATARD for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2072 #define DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART1RXDATAVRIGHT << 0) /**< Shifted mode USART1RXDATAVRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2073 #define DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT (_DMA_CH_CTRL_SIGSEL_USART2RXDATAVRIGHT << 0) /**< Shifted mode USART2RXDATAVRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2074 #define DMA_CH_CTRL_SIGSEL_TIMER0CC2 (_DMA_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2075 #define DMA_CH_CTRL_SIGSEL_TIMER1CC2 (_DMA_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2076 #define DMA_CH_CTRL_SIGSEL_TIMER2CC2 (_DMA_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2077 #define DMA_CH_CTRL_SIGSEL_TIMER3CC2 (_DMA_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2078 #define DMA_CH_CTRL_SIGSEL_AESKEYWR (_DMA_CH_CTRL_SIGSEL_AESKEYWR << 0) /**< Shifted mode AESKEYWR for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2079 #define DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART1TXBLRIGHT << 0) /**< Shifted mode USART1TXBLRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2080 #define DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT (_DMA_CH_CTRL_SIGSEL_USART2TXBLRIGHT << 0) /**< Shifted mode USART2TXBLRIGHT for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2081 #define _DMA_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for DMA_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 2082 #define _DMA_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for DMA_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 2083 #define _DMA_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2084 #define _DMA_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2085 #define _DMA_CH_CTRL_SOURCESEL_DAC0 0x0000000AUL /**< Mode DAC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2086 #define _DMA_CH_CTRL_SOURCESEL_USART0 0x0000000CUL /**< Mode USART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2087 #define _DMA_CH_CTRL_SOURCESEL_USART1 0x0000000DUL /**< Mode USART1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2088 #define _DMA_CH_CTRL_SOURCESEL_USART2 0x0000000EUL /**< Mode USART2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2089 #define _DMA_CH_CTRL_SOURCESEL_LEUART0 0x00000010UL /**< Mode LEUART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2090 #define _DMA_CH_CTRL_SOURCESEL_LEUART1 0x00000011UL /**< Mode LEUART1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2091 #define _DMA_CH_CTRL_SOURCESEL_I2C0 0x00000014UL /**< Mode I2C0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2092 #define _DMA_CH_CTRL_SOURCESEL_I2C1 0x00000015UL /**< Mode I2C1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2093 #define _DMA_CH_CTRL_SOURCESEL_TIMER0 0x00000018UL /**< Mode TIMER0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2094 #define _DMA_CH_CTRL_SOURCESEL_TIMER1 0x00000019UL /**< Mode TIMER1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2095 #define _DMA_CH_CTRL_SOURCESEL_TIMER2 0x0000001AUL /**< Mode TIMER2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2096 #define _DMA_CH_CTRL_SOURCESEL_TIMER3 0x0000001BUL /**< Mode TIMER3 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2097 #define _DMA_CH_CTRL_SOURCESEL_MSC 0x00000030UL /**< Mode MSC for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2098 #define _DMA_CH_CTRL_SOURCESEL_AES 0x00000031UL /**< Mode AES for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2099 #define _DMA_CH_CTRL_SOURCESEL_LESENSE 0x00000032UL /**< Mode LESENSE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2100 #define DMA_CH_CTRL_SOURCESEL_NONE (_DMA_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2101 #define DMA_CH_CTRL_SOURCESEL_ADC0 (_DMA_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2102 #define DMA_CH_CTRL_SOURCESEL_DAC0 (_DMA_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2103 #define DMA_CH_CTRL_SOURCESEL_USART0 (_DMA_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2104 #define DMA_CH_CTRL_SOURCESEL_USART1 (_DMA_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2105 #define DMA_CH_CTRL_SOURCESEL_USART2 (_DMA_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2106 #define DMA_CH_CTRL_SOURCESEL_LEUART0 (_DMA_CH_CTRL_SOURCESEL_LEUART0 << 16) /**< Shifted mode LEUART0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2107 #define DMA_CH_CTRL_SOURCESEL_LEUART1 (_DMA_CH_CTRL_SOURCESEL_LEUART1 << 16) /**< Shifted mode LEUART1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2108 #define DMA_CH_CTRL_SOURCESEL_I2C0 (_DMA_CH_CTRL_SOURCESEL_I2C0 << 16) /**< Shifted mode I2C0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2109 #define DMA_CH_CTRL_SOURCESEL_I2C1 (_DMA_CH_CTRL_SOURCESEL_I2C1 << 16) /**< Shifted mode I2C1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2110 #define DMA_CH_CTRL_SOURCESEL_TIMER0 (_DMA_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2111 #define DMA_CH_CTRL_SOURCESEL_TIMER1 (_DMA_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2112 #define DMA_CH_CTRL_SOURCESEL_TIMER2 (_DMA_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2113 #define DMA_CH_CTRL_SOURCESEL_TIMER3 (_DMA_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2114 #define DMA_CH_CTRL_SOURCESEL_MSC (_DMA_CH_CTRL_SOURCESEL_MSC << 16) /**< Shifted mode MSC for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2115 #define DMA_CH_CTRL_SOURCESEL_AES (_DMA_CH_CTRL_SOURCESEL_AES << 16) /**< Shifted mode AES for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2116 #define DMA_CH_CTRL_SOURCESEL_LESENSE (_DMA_CH_CTRL_SOURCESEL_LESENSE << 16) /**< Shifted mode LESENSE for DMA_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 2117
AnnaBridge 171:3a7713b1edbc 2118 /** @} End of group EFM32GG842F1024_DMA */
AnnaBridge 171:3a7713b1edbc 2119
AnnaBridge 171:3a7713b1edbc 2120
AnnaBridge 171:3a7713b1edbc 2121
AnnaBridge 171:3a7713b1edbc 2122 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 2123 * @defgroup EFM32GG842F1024_CMU_BitFields EFM32GG842F1024_CMU Bit Fields
AnnaBridge 171:3a7713b1edbc 2124 * @{
AnnaBridge 171:3a7713b1edbc 2125 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 2126
AnnaBridge 171:3a7713b1edbc 2127 /* Bit fields for CMU CTRL */
AnnaBridge 171:3a7713b1edbc 2128 #define _CMU_CTRL_RESETVALUE 0x000C062CUL /**< Default value for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2129 #define _CMU_CTRL_MASK 0x57FFFEEFUL /**< Mask for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2130 #define _CMU_CTRL_HFXOMODE_SHIFT 0 /**< Shift value for CMU_HFXOMODE */
AnnaBridge 171:3a7713b1edbc 2131 #define _CMU_CTRL_HFXOMODE_MASK 0x3UL /**< Bit mask for CMU_HFXOMODE */
AnnaBridge 171:3a7713b1edbc 2132 #define _CMU_CTRL_HFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2133 #define _CMU_CTRL_HFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2134 #define _CMU_CTRL_HFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2135 #define _CMU_CTRL_HFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2136 #define CMU_CTRL_HFXOMODE_DEFAULT (_CMU_CTRL_HFXOMODE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2137 #define CMU_CTRL_HFXOMODE_XTAL (_CMU_CTRL_HFXOMODE_XTAL << 0) /**< Shifted mode XTAL for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2138 #define CMU_CTRL_HFXOMODE_BUFEXTCLK (_CMU_CTRL_HFXOMODE_BUFEXTCLK << 0) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2139 #define CMU_CTRL_HFXOMODE_DIGEXTCLK (_CMU_CTRL_HFXOMODE_DIGEXTCLK << 0) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2140 #define _CMU_CTRL_HFXOBOOST_SHIFT 2 /**< Shift value for CMU_HFXOBOOST */
AnnaBridge 171:3a7713b1edbc 2141 #define _CMU_CTRL_HFXOBOOST_MASK 0xCUL /**< Bit mask for CMU_HFXOBOOST */
AnnaBridge 171:3a7713b1edbc 2142 #define _CMU_CTRL_HFXOBOOST_50PCENT 0x00000000UL /**< Mode 50PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2143 #define _CMU_CTRL_HFXOBOOST_70PCENT 0x00000001UL /**< Mode 70PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2144 #define _CMU_CTRL_HFXOBOOST_80PCENT 0x00000002UL /**< Mode 80PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2145 #define _CMU_CTRL_HFXOBOOST_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2146 #define _CMU_CTRL_HFXOBOOST_100PCENT 0x00000003UL /**< Mode 100PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2147 #define CMU_CTRL_HFXOBOOST_50PCENT (_CMU_CTRL_HFXOBOOST_50PCENT << 2) /**< Shifted mode 50PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2148 #define CMU_CTRL_HFXOBOOST_70PCENT (_CMU_CTRL_HFXOBOOST_70PCENT << 2) /**< Shifted mode 70PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2149 #define CMU_CTRL_HFXOBOOST_80PCENT (_CMU_CTRL_HFXOBOOST_80PCENT << 2) /**< Shifted mode 80PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2150 #define CMU_CTRL_HFXOBOOST_DEFAULT (_CMU_CTRL_HFXOBOOST_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2151 #define CMU_CTRL_HFXOBOOST_100PCENT (_CMU_CTRL_HFXOBOOST_100PCENT << 2) /**< Shifted mode 100PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2152 #define _CMU_CTRL_HFXOBUFCUR_SHIFT 5 /**< Shift value for CMU_HFXOBUFCUR */
AnnaBridge 171:3a7713b1edbc 2153 #define _CMU_CTRL_HFXOBUFCUR_MASK 0x60UL /**< Bit mask for CMU_HFXOBUFCUR */
AnnaBridge 171:3a7713b1edbc 2154 #define _CMU_CTRL_HFXOBUFCUR_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2155 #define _CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ 0x00000001UL /**< Mode BOOSTUPTO32MHZ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2156 #define _CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ 0x00000003UL /**< Mode BOOSTABOVE32MHZ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2157 #define CMU_CTRL_HFXOBUFCUR_DEFAULT (_CMU_CTRL_HFXOBUFCUR_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2158 #define CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTUPTO32MHZ << 5) /**< Shifted mode BOOSTUPTO32MHZ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2159 #define CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ (_CMU_CTRL_HFXOBUFCUR_BOOSTABOVE32MHZ << 5) /**< Shifted mode BOOSTABOVE32MHZ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2160 #define CMU_CTRL_HFXOGLITCHDETEN (0x1UL << 7) /**< HFXO Glitch Detector Enable */
AnnaBridge 171:3a7713b1edbc 2161 #define _CMU_CTRL_HFXOGLITCHDETEN_SHIFT 7 /**< Shift value for CMU_HFXOGLITCHDETEN */
AnnaBridge 171:3a7713b1edbc 2162 #define _CMU_CTRL_HFXOGLITCHDETEN_MASK 0x80UL /**< Bit mask for CMU_HFXOGLITCHDETEN */
AnnaBridge 171:3a7713b1edbc 2163 #define _CMU_CTRL_HFXOGLITCHDETEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2164 #define CMU_CTRL_HFXOGLITCHDETEN_DEFAULT (_CMU_CTRL_HFXOGLITCHDETEN_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2165 #define _CMU_CTRL_HFXOTIMEOUT_SHIFT 9 /**< Shift value for CMU_HFXOTIMEOUT */
AnnaBridge 171:3a7713b1edbc 2166 #define _CMU_CTRL_HFXOTIMEOUT_MASK 0x600UL /**< Bit mask for CMU_HFXOTIMEOUT */
AnnaBridge 171:3a7713b1edbc 2167 #define _CMU_CTRL_HFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2168 #define _CMU_CTRL_HFXOTIMEOUT_256CYCLES 0x00000001UL /**< Mode 256CYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2169 #define _CMU_CTRL_HFXOTIMEOUT_1KCYCLES 0x00000002UL /**< Mode 1KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2170 #define _CMU_CTRL_HFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2171 #define _CMU_CTRL_HFXOTIMEOUT_16KCYCLES 0x00000003UL /**< Mode 16KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2172 #define CMU_CTRL_HFXOTIMEOUT_8CYCLES (_CMU_CTRL_HFXOTIMEOUT_8CYCLES << 9) /**< Shifted mode 8CYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2173 #define CMU_CTRL_HFXOTIMEOUT_256CYCLES (_CMU_CTRL_HFXOTIMEOUT_256CYCLES << 9) /**< Shifted mode 256CYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2174 #define CMU_CTRL_HFXOTIMEOUT_1KCYCLES (_CMU_CTRL_HFXOTIMEOUT_1KCYCLES << 9) /**< Shifted mode 1KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2175 #define CMU_CTRL_HFXOTIMEOUT_DEFAULT (_CMU_CTRL_HFXOTIMEOUT_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2176 #define CMU_CTRL_HFXOTIMEOUT_16KCYCLES (_CMU_CTRL_HFXOTIMEOUT_16KCYCLES << 9) /**< Shifted mode 16KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2177 #define _CMU_CTRL_LFXOMODE_SHIFT 11 /**< Shift value for CMU_LFXOMODE */
AnnaBridge 171:3a7713b1edbc 2178 #define _CMU_CTRL_LFXOMODE_MASK 0x1800UL /**< Bit mask for CMU_LFXOMODE */
AnnaBridge 171:3a7713b1edbc 2179 #define _CMU_CTRL_LFXOMODE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2180 #define _CMU_CTRL_LFXOMODE_XTAL 0x00000000UL /**< Mode XTAL for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2181 #define _CMU_CTRL_LFXOMODE_BUFEXTCLK 0x00000001UL /**< Mode BUFEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2182 #define _CMU_CTRL_LFXOMODE_DIGEXTCLK 0x00000002UL /**< Mode DIGEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2183 #define CMU_CTRL_LFXOMODE_DEFAULT (_CMU_CTRL_LFXOMODE_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2184 #define CMU_CTRL_LFXOMODE_XTAL (_CMU_CTRL_LFXOMODE_XTAL << 11) /**< Shifted mode XTAL for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2185 #define CMU_CTRL_LFXOMODE_BUFEXTCLK (_CMU_CTRL_LFXOMODE_BUFEXTCLK << 11) /**< Shifted mode BUFEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2186 #define CMU_CTRL_LFXOMODE_DIGEXTCLK (_CMU_CTRL_LFXOMODE_DIGEXTCLK << 11) /**< Shifted mode DIGEXTCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2187 #define CMU_CTRL_LFXOBOOST (0x1UL << 13) /**< LFXO Start-up Boost Current */
AnnaBridge 171:3a7713b1edbc 2188 #define _CMU_CTRL_LFXOBOOST_SHIFT 13 /**< Shift value for CMU_LFXOBOOST */
AnnaBridge 171:3a7713b1edbc 2189 #define _CMU_CTRL_LFXOBOOST_MASK 0x2000UL /**< Bit mask for CMU_LFXOBOOST */
AnnaBridge 171:3a7713b1edbc 2190 #define _CMU_CTRL_LFXOBOOST_70PCENT 0x00000000UL /**< Mode 70PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2191 #define _CMU_CTRL_LFXOBOOST_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2192 #define _CMU_CTRL_LFXOBOOST_100PCENT 0x00000001UL /**< Mode 100PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2193 #define CMU_CTRL_LFXOBOOST_70PCENT (_CMU_CTRL_LFXOBOOST_70PCENT << 13) /**< Shifted mode 70PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2194 #define CMU_CTRL_LFXOBOOST_DEFAULT (_CMU_CTRL_LFXOBOOST_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2195 #define CMU_CTRL_LFXOBOOST_100PCENT (_CMU_CTRL_LFXOBOOST_100PCENT << 13) /**< Shifted mode 100PCENT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2196 #define _CMU_CTRL_HFCLKDIV_SHIFT 14 /**< Shift value for CMU_HFCLKDIV */
AnnaBridge 171:3a7713b1edbc 2197 #define _CMU_CTRL_HFCLKDIV_MASK 0x1C000UL /**< Bit mask for CMU_HFCLKDIV */
AnnaBridge 171:3a7713b1edbc 2198 #define _CMU_CTRL_HFCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2199 #define CMU_CTRL_HFCLKDIV_DEFAULT (_CMU_CTRL_HFCLKDIV_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2200 #define CMU_CTRL_LFXOBUFCUR (0x1UL << 17) /**< LFXO Boost Buffer Current */
AnnaBridge 171:3a7713b1edbc 2201 #define _CMU_CTRL_LFXOBUFCUR_SHIFT 17 /**< Shift value for CMU_LFXOBUFCUR */
AnnaBridge 171:3a7713b1edbc 2202 #define _CMU_CTRL_LFXOBUFCUR_MASK 0x20000UL /**< Bit mask for CMU_LFXOBUFCUR */
AnnaBridge 171:3a7713b1edbc 2203 #define _CMU_CTRL_LFXOBUFCUR_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2204 #define CMU_CTRL_LFXOBUFCUR_DEFAULT (_CMU_CTRL_LFXOBUFCUR_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2205 #define _CMU_CTRL_LFXOTIMEOUT_SHIFT 18 /**< Shift value for CMU_LFXOTIMEOUT */
AnnaBridge 171:3a7713b1edbc 2206 #define _CMU_CTRL_LFXOTIMEOUT_MASK 0xC0000UL /**< Bit mask for CMU_LFXOTIMEOUT */
AnnaBridge 171:3a7713b1edbc 2207 #define _CMU_CTRL_LFXOTIMEOUT_8CYCLES 0x00000000UL /**< Mode 8CYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2208 #define _CMU_CTRL_LFXOTIMEOUT_1KCYCLES 0x00000001UL /**< Mode 1KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2209 #define _CMU_CTRL_LFXOTIMEOUT_16KCYCLES 0x00000002UL /**< Mode 16KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2210 #define _CMU_CTRL_LFXOTIMEOUT_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2211 #define _CMU_CTRL_LFXOTIMEOUT_32KCYCLES 0x00000003UL /**< Mode 32KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2212 #define CMU_CTRL_LFXOTIMEOUT_8CYCLES (_CMU_CTRL_LFXOTIMEOUT_8CYCLES << 18) /**< Shifted mode 8CYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2213 #define CMU_CTRL_LFXOTIMEOUT_1KCYCLES (_CMU_CTRL_LFXOTIMEOUT_1KCYCLES << 18) /**< Shifted mode 1KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2214 #define CMU_CTRL_LFXOTIMEOUT_16KCYCLES (_CMU_CTRL_LFXOTIMEOUT_16KCYCLES << 18) /**< Shifted mode 16KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2215 #define CMU_CTRL_LFXOTIMEOUT_DEFAULT (_CMU_CTRL_LFXOTIMEOUT_DEFAULT << 18) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2216 #define CMU_CTRL_LFXOTIMEOUT_32KCYCLES (_CMU_CTRL_LFXOTIMEOUT_32KCYCLES << 18) /**< Shifted mode 32KCYCLES for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2217 #define _CMU_CTRL_CLKOUTSEL0_SHIFT 20 /**< Shift value for CMU_CLKOUTSEL0 */
AnnaBridge 171:3a7713b1edbc 2218 #define _CMU_CTRL_CLKOUTSEL0_MASK 0x700000UL /**< Bit mask for CMU_CLKOUTSEL0 */
AnnaBridge 171:3a7713b1edbc 2219 #define _CMU_CTRL_CLKOUTSEL0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2220 #define _CMU_CTRL_CLKOUTSEL0_HFRCO 0x00000000UL /**< Mode HFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2221 #define _CMU_CTRL_CLKOUTSEL0_HFXO 0x00000001UL /**< Mode HFXO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2222 #define _CMU_CTRL_CLKOUTSEL0_HFCLK2 0x00000002UL /**< Mode HFCLK2 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2223 #define _CMU_CTRL_CLKOUTSEL0_HFCLK4 0x00000003UL /**< Mode HFCLK4 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2224 #define _CMU_CTRL_CLKOUTSEL0_HFCLK8 0x00000004UL /**< Mode HFCLK8 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2225 #define _CMU_CTRL_CLKOUTSEL0_HFCLK16 0x00000005UL /**< Mode HFCLK16 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2226 #define _CMU_CTRL_CLKOUTSEL0_ULFRCO 0x00000006UL /**< Mode ULFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2227 #define _CMU_CTRL_CLKOUTSEL0_AUXHFRCO 0x00000007UL /**< Mode AUXHFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2228 #define CMU_CTRL_CLKOUTSEL0_DEFAULT (_CMU_CTRL_CLKOUTSEL0_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2229 #define CMU_CTRL_CLKOUTSEL0_HFRCO (_CMU_CTRL_CLKOUTSEL0_HFRCO << 20) /**< Shifted mode HFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2230 #define CMU_CTRL_CLKOUTSEL0_HFXO (_CMU_CTRL_CLKOUTSEL0_HFXO << 20) /**< Shifted mode HFXO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2231 #define CMU_CTRL_CLKOUTSEL0_HFCLK2 (_CMU_CTRL_CLKOUTSEL0_HFCLK2 << 20) /**< Shifted mode HFCLK2 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2232 #define CMU_CTRL_CLKOUTSEL0_HFCLK4 (_CMU_CTRL_CLKOUTSEL0_HFCLK4 << 20) /**< Shifted mode HFCLK4 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2233 #define CMU_CTRL_CLKOUTSEL0_HFCLK8 (_CMU_CTRL_CLKOUTSEL0_HFCLK8 << 20) /**< Shifted mode HFCLK8 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2234 #define CMU_CTRL_CLKOUTSEL0_HFCLK16 (_CMU_CTRL_CLKOUTSEL0_HFCLK16 << 20) /**< Shifted mode HFCLK16 for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2235 #define CMU_CTRL_CLKOUTSEL0_ULFRCO (_CMU_CTRL_CLKOUTSEL0_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2236 #define CMU_CTRL_CLKOUTSEL0_AUXHFRCO (_CMU_CTRL_CLKOUTSEL0_AUXHFRCO << 20) /**< Shifted mode AUXHFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2237 #define _CMU_CTRL_CLKOUTSEL1_SHIFT 23 /**< Shift value for CMU_CLKOUTSEL1 */
AnnaBridge 171:3a7713b1edbc 2238 #define _CMU_CTRL_CLKOUTSEL1_MASK 0x7800000UL /**< Bit mask for CMU_CLKOUTSEL1 */
AnnaBridge 171:3a7713b1edbc 2239 #define _CMU_CTRL_CLKOUTSEL1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2240 #define _CMU_CTRL_CLKOUTSEL1_LFRCO 0x00000000UL /**< Mode LFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2241 #define _CMU_CTRL_CLKOUTSEL1_LFXO 0x00000001UL /**< Mode LFXO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2242 #define _CMU_CTRL_CLKOUTSEL1_HFCLK 0x00000002UL /**< Mode HFCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2243 #define _CMU_CTRL_CLKOUTSEL1_LFXOQ 0x00000003UL /**< Mode LFXOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2244 #define _CMU_CTRL_CLKOUTSEL1_HFXOQ 0x00000004UL /**< Mode HFXOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2245 #define _CMU_CTRL_CLKOUTSEL1_LFRCOQ 0x00000005UL /**< Mode LFRCOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2246 #define _CMU_CTRL_CLKOUTSEL1_HFRCOQ 0x00000006UL /**< Mode HFRCOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2247 #define _CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ 0x00000007UL /**< Mode AUXHFRCOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2248 #define CMU_CTRL_CLKOUTSEL1_DEFAULT (_CMU_CTRL_CLKOUTSEL1_DEFAULT << 23) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2249 #define CMU_CTRL_CLKOUTSEL1_LFRCO (_CMU_CTRL_CLKOUTSEL1_LFRCO << 23) /**< Shifted mode LFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2250 #define CMU_CTRL_CLKOUTSEL1_LFXO (_CMU_CTRL_CLKOUTSEL1_LFXO << 23) /**< Shifted mode LFXO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2251 #define CMU_CTRL_CLKOUTSEL1_HFCLK (_CMU_CTRL_CLKOUTSEL1_HFCLK << 23) /**< Shifted mode HFCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2252 #define CMU_CTRL_CLKOUTSEL1_LFXOQ (_CMU_CTRL_CLKOUTSEL1_LFXOQ << 23) /**< Shifted mode LFXOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2253 #define CMU_CTRL_CLKOUTSEL1_HFXOQ (_CMU_CTRL_CLKOUTSEL1_HFXOQ << 23) /**< Shifted mode HFXOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2254 #define CMU_CTRL_CLKOUTSEL1_LFRCOQ (_CMU_CTRL_CLKOUTSEL1_LFRCOQ << 23) /**< Shifted mode LFRCOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2255 #define CMU_CTRL_CLKOUTSEL1_HFRCOQ (_CMU_CTRL_CLKOUTSEL1_HFRCOQ << 23) /**< Shifted mode HFRCOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2256 #define CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ (_CMU_CTRL_CLKOUTSEL1_AUXHFRCOQ << 23) /**< Shifted mode AUXHFRCOQ for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2257 #define CMU_CTRL_DBGCLK (0x1UL << 28) /**< Debug Clock */
AnnaBridge 171:3a7713b1edbc 2258 #define _CMU_CTRL_DBGCLK_SHIFT 28 /**< Shift value for CMU_DBGCLK */
AnnaBridge 171:3a7713b1edbc 2259 #define _CMU_CTRL_DBGCLK_MASK 0x10000000UL /**< Bit mask for CMU_DBGCLK */
AnnaBridge 171:3a7713b1edbc 2260 #define _CMU_CTRL_DBGCLK_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2261 #define _CMU_CTRL_DBGCLK_AUXHFRCO 0x00000000UL /**< Mode AUXHFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2262 #define _CMU_CTRL_DBGCLK_HFCLK 0x00000001UL /**< Mode HFCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2263 #define CMU_CTRL_DBGCLK_DEFAULT (_CMU_CTRL_DBGCLK_DEFAULT << 28) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2264 #define CMU_CTRL_DBGCLK_AUXHFRCO (_CMU_CTRL_DBGCLK_AUXHFRCO << 28) /**< Shifted mode AUXHFRCO for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2265 #define CMU_CTRL_DBGCLK_HFCLK (_CMU_CTRL_DBGCLK_HFCLK << 28) /**< Shifted mode HFCLK for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2266 #define CMU_CTRL_HFLE (0x1UL << 30) /**< High-Frequency LE Interface */
AnnaBridge 171:3a7713b1edbc 2267 #define _CMU_CTRL_HFLE_SHIFT 30 /**< Shift value for CMU_HFLE */
AnnaBridge 171:3a7713b1edbc 2268 #define _CMU_CTRL_HFLE_MASK 0x40000000UL /**< Bit mask for CMU_HFLE */
AnnaBridge 171:3a7713b1edbc 2269 #define _CMU_CTRL_HFLE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2270 #define CMU_CTRL_HFLE_DEFAULT (_CMU_CTRL_HFLE_DEFAULT << 30) /**< Shifted mode DEFAULT for CMU_CTRL */
AnnaBridge 171:3a7713b1edbc 2271
AnnaBridge 171:3a7713b1edbc 2272 /* Bit fields for CMU HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2273 #define _CMU_HFCORECLKDIV_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2274 #define _CMU_HFCORECLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2275 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_SHIFT 0 /**< Shift value for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2276 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2277 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2278 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2279 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2280 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2281 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2282 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2283 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2284 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2285 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2286 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2287 #define _CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2288 #define CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2289 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2290 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2291 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2292 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2293 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2294 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2295 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2296 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2297 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2298 #define CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 (_CMU_HFCORECLKDIV_HFCORECLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2299 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV (0x1UL << 8) /**< Additional Division Factor For HFCORECLKLE */
AnnaBridge 171:3a7713b1edbc 2300 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_SHIFT 8 /**< Shift value for CMU_HFCORECLKLEDIV */
AnnaBridge 171:3a7713b1edbc 2301 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_MASK 0x100UL /**< Bit mask for CMU_HFCORECLKLEDIV */
AnnaBridge 171:3a7713b1edbc 2302 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2303 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 0x00000000UL /**< Mode DIV2 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2304 #define _CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 0x00000001UL /**< Mode DIV4 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2305 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2306 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV2 << 8) /**< Shifted mode DIV2 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2307 #define CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 (_CMU_HFCORECLKDIV_HFCORECLKLEDIV_DIV4 << 8) /**< Shifted mode DIV4 for CMU_HFCORECLKDIV */
AnnaBridge 171:3a7713b1edbc 2308
AnnaBridge 171:3a7713b1edbc 2309 /* Bit fields for CMU HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2310 #define _CMU_HFPERCLKDIV_RESETVALUE 0x00000100UL /**< Default value for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2311 #define _CMU_HFPERCLKDIV_MASK 0x0000010FUL /**< Mask for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2312 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_SHIFT 0 /**< Shift value for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2313 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_MASK 0xFUL /**< Bit mask for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2314 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2315 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2316 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 0x00000001UL /**< Mode HFCLK2 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2317 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 0x00000002UL /**< Mode HFCLK4 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2318 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 0x00000003UL /**< Mode HFCLK8 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2319 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 0x00000004UL /**< Mode HFCLK16 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2320 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 0x00000005UL /**< Mode HFCLK32 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2321 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 0x00000006UL /**< Mode HFCLK64 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2322 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 0x00000007UL /**< Mode HFCLK128 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2323 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 0x00000008UL /**< Mode HFCLK256 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2324 #define _CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 0x00000009UL /**< Mode HFCLK512 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2325 #define CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2326 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK << 0) /**< Shifted mode HFCLK for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2327 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK2 << 0) /**< Shifted mode HFCLK2 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2328 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK4 << 0) /**< Shifted mode HFCLK4 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2329 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK8 << 0) /**< Shifted mode HFCLK8 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2330 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK16 << 0) /**< Shifted mode HFCLK16 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2331 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK32 << 0) /**< Shifted mode HFCLK32 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2332 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK64 << 0) /**< Shifted mode HFCLK64 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2333 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK128 << 0) /**< Shifted mode HFCLK128 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2334 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK256 << 0) /**< Shifted mode HFCLK256 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2335 #define CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 (_CMU_HFPERCLKDIV_HFPERCLKDIV_HFCLK512 << 0) /**< Shifted mode HFCLK512 for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2336 #define CMU_HFPERCLKDIV_HFPERCLKEN (0x1UL << 8) /**< HFPERCLK Enable */
AnnaBridge 171:3a7713b1edbc 2337 #define _CMU_HFPERCLKDIV_HFPERCLKEN_SHIFT 8 /**< Shift value for CMU_HFPERCLKEN */
AnnaBridge 171:3a7713b1edbc 2338 #define _CMU_HFPERCLKDIV_HFPERCLKEN_MASK 0x100UL /**< Bit mask for CMU_HFPERCLKEN */
AnnaBridge 171:3a7713b1edbc 2339 #define _CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2340 #define CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT (_CMU_HFPERCLKDIV_HFPERCLKEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKDIV */
AnnaBridge 171:3a7713b1edbc 2341
AnnaBridge 171:3a7713b1edbc 2342 /* Bit fields for CMU HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2343 #define _CMU_HFRCOCTRL_RESETVALUE 0x00000380UL /**< Default value for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2344 #define _CMU_HFRCOCTRL_MASK 0x0001F7FFUL /**< Mask for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2345 #define _CMU_HFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
AnnaBridge 171:3a7713b1edbc 2346 #define _CMU_HFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
AnnaBridge 171:3a7713b1edbc 2347 #define _CMU_HFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2348 #define CMU_HFRCOCTRL_TUNING_DEFAULT (_CMU_HFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2349 #define _CMU_HFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
AnnaBridge 171:3a7713b1edbc 2350 #define _CMU_HFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
AnnaBridge 171:3a7713b1edbc 2351 #define _CMU_HFRCOCTRL_BAND_1MHZ 0x00000000UL /**< Mode 1MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2352 #define _CMU_HFRCOCTRL_BAND_7MHZ 0x00000001UL /**< Mode 7MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2353 #define _CMU_HFRCOCTRL_BAND_11MHZ 0x00000002UL /**< Mode 11MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2354 #define _CMU_HFRCOCTRL_BAND_DEFAULT 0x00000003UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2355 #define _CMU_HFRCOCTRL_BAND_14MHZ 0x00000003UL /**< Mode 14MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2356 #define _CMU_HFRCOCTRL_BAND_21MHZ 0x00000004UL /**< Mode 21MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2357 #define _CMU_HFRCOCTRL_BAND_28MHZ 0x00000005UL /**< Mode 28MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2358 #define CMU_HFRCOCTRL_BAND_1MHZ (_CMU_HFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2359 #define CMU_HFRCOCTRL_BAND_7MHZ (_CMU_HFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2360 #define CMU_HFRCOCTRL_BAND_11MHZ (_CMU_HFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2361 #define CMU_HFRCOCTRL_BAND_DEFAULT (_CMU_HFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2362 #define CMU_HFRCOCTRL_BAND_14MHZ (_CMU_HFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2363 #define CMU_HFRCOCTRL_BAND_21MHZ (_CMU_HFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2364 #define CMU_HFRCOCTRL_BAND_28MHZ (_CMU_HFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2365 #define _CMU_HFRCOCTRL_SUDELAY_SHIFT 12 /**< Shift value for CMU_SUDELAY */
AnnaBridge 171:3a7713b1edbc 2366 #define _CMU_HFRCOCTRL_SUDELAY_MASK 0x1F000UL /**< Bit mask for CMU_SUDELAY */
AnnaBridge 171:3a7713b1edbc 2367 #define _CMU_HFRCOCTRL_SUDELAY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2368 #define CMU_HFRCOCTRL_SUDELAY_DEFAULT (_CMU_HFRCOCTRL_SUDELAY_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2369
AnnaBridge 171:3a7713b1edbc 2370 /* Bit fields for CMU LFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2371 #define _CMU_LFRCOCTRL_RESETVALUE 0x00000040UL /**< Default value for CMU_LFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2372 #define _CMU_LFRCOCTRL_MASK 0x0000007FUL /**< Mask for CMU_LFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2373 #define _CMU_LFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
AnnaBridge 171:3a7713b1edbc 2374 #define _CMU_LFRCOCTRL_TUNING_MASK 0x7FUL /**< Bit mask for CMU_TUNING */
AnnaBridge 171:3a7713b1edbc 2375 #define _CMU_LFRCOCTRL_TUNING_DEFAULT 0x00000040UL /**< Mode DEFAULT for CMU_LFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2376 #define CMU_LFRCOCTRL_TUNING_DEFAULT (_CMU_LFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2377
AnnaBridge 171:3a7713b1edbc 2378 /* Bit fields for CMU AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2379 #define _CMU_AUXHFRCOCTRL_RESETVALUE 0x00000080UL /**< Default value for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2380 #define _CMU_AUXHFRCOCTRL_MASK 0x000007FFUL /**< Mask for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2381 #define _CMU_AUXHFRCOCTRL_TUNING_SHIFT 0 /**< Shift value for CMU_TUNING */
AnnaBridge 171:3a7713b1edbc 2382 #define _CMU_AUXHFRCOCTRL_TUNING_MASK 0xFFUL /**< Bit mask for CMU_TUNING */
AnnaBridge 171:3a7713b1edbc 2383 #define _CMU_AUXHFRCOCTRL_TUNING_DEFAULT 0x00000080UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2384 #define CMU_AUXHFRCOCTRL_TUNING_DEFAULT (_CMU_AUXHFRCOCTRL_TUNING_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2385 #define _CMU_AUXHFRCOCTRL_BAND_SHIFT 8 /**< Shift value for CMU_BAND */
AnnaBridge 171:3a7713b1edbc 2386 #define _CMU_AUXHFRCOCTRL_BAND_MASK 0x700UL /**< Bit mask for CMU_BAND */
AnnaBridge 171:3a7713b1edbc 2387 #define _CMU_AUXHFRCOCTRL_BAND_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2388 #define _CMU_AUXHFRCOCTRL_BAND_14MHZ 0x00000000UL /**< Mode 14MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2389 #define _CMU_AUXHFRCOCTRL_BAND_11MHZ 0x00000001UL /**< Mode 11MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2390 #define _CMU_AUXHFRCOCTRL_BAND_7MHZ 0x00000002UL /**< Mode 7MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2391 #define _CMU_AUXHFRCOCTRL_BAND_1MHZ 0x00000003UL /**< Mode 1MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2392 #define _CMU_AUXHFRCOCTRL_BAND_28MHZ 0x00000006UL /**< Mode 28MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2393 #define _CMU_AUXHFRCOCTRL_BAND_21MHZ 0x00000007UL /**< Mode 21MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2394 #define CMU_AUXHFRCOCTRL_BAND_DEFAULT (_CMU_AUXHFRCOCTRL_BAND_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2395 #define CMU_AUXHFRCOCTRL_BAND_14MHZ (_CMU_AUXHFRCOCTRL_BAND_14MHZ << 8) /**< Shifted mode 14MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2396 #define CMU_AUXHFRCOCTRL_BAND_11MHZ (_CMU_AUXHFRCOCTRL_BAND_11MHZ << 8) /**< Shifted mode 11MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2397 #define CMU_AUXHFRCOCTRL_BAND_7MHZ (_CMU_AUXHFRCOCTRL_BAND_7MHZ << 8) /**< Shifted mode 7MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2398 #define CMU_AUXHFRCOCTRL_BAND_1MHZ (_CMU_AUXHFRCOCTRL_BAND_1MHZ << 8) /**< Shifted mode 1MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2399 #define CMU_AUXHFRCOCTRL_BAND_28MHZ (_CMU_AUXHFRCOCTRL_BAND_28MHZ << 8) /**< Shifted mode 28MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2400 #define CMU_AUXHFRCOCTRL_BAND_21MHZ (_CMU_AUXHFRCOCTRL_BAND_21MHZ << 8) /**< Shifted mode 21MHZ for CMU_AUXHFRCOCTRL */
AnnaBridge 171:3a7713b1edbc 2401
AnnaBridge 171:3a7713b1edbc 2402 /* Bit fields for CMU CALCTRL */
AnnaBridge 171:3a7713b1edbc 2403 #define _CMU_CALCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2404 #define _CMU_CALCTRL_MASK 0x0000007FUL /**< Mask for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2405 #define _CMU_CALCTRL_UPSEL_SHIFT 0 /**< Shift value for CMU_UPSEL */
AnnaBridge 171:3a7713b1edbc 2406 #define _CMU_CALCTRL_UPSEL_MASK 0x7UL /**< Bit mask for CMU_UPSEL */
AnnaBridge 171:3a7713b1edbc 2407 #define _CMU_CALCTRL_UPSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2408 #define _CMU_CALCTRL_UPSEL_HFXO 0x00000000UL /**< Mode HFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2409 #define _CMU_CALCTRL_UPSEL_LFXO 0x00000001UL /**< Mode LFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2410 #define _CMU_CALCTRL_UPSEL_HFRCO 0x00000002UL /**< Mode HFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2411 #define _CMU_CALCTRL_UPSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2412 #define _CMU_CALCTRL_UPSEL_AUXHFRCO 0x00000004UL /**< Mode AUXHFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2413 #define CMU_CALCTRL_UPSEL_DEFAULT (_CMU_CALCTRL_UPSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2414 #define CMU_CALCTRL_UPSEL_HFXO (_CMU_CALCTRL_UPSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2415 #define CMU_CALCTRL_UPSEL_LFXO (_CMU_CALCTRL_UPSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2416 #define CMU_CALCTRL_UPSEL_HFRCO (_CMU_CALCTRL_UPSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2417 #define CMU_CALCTRL_UPSEL_LFRCO (_CMU_CALCTRL_UPSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2418 #define CMU_CALCTRL_UPSEL_AUXHFRCO (_CMU_CALCTRL_UPSEL_AUXHFRCO << 0) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2419 #define _CMU_CALCTRL_DOWNSEL_SHIFT 3 /**< Shift value for CMU_DOWNSEL */
AnnaBridge 171:3a7713b1edbc 2420 #define _CMU_CALCTRL_DOWNSEL_MASK 0x38UL /**< Bit mask for CMU_DOWNSEL */
AnnaBridge 171:3a7713b1edbc 2421 #define _CMU_CALCTRL_DOWNSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2422 #define _CMU_CALCTRL_DOWNSEL_HFCLK 0x00000000UL /**< Mode HFCLK for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2423 #define _CMU_CALCTRL_DOWNSEL_HFXO 0x00000001UL /**< Mode HFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2424 #define _CMU_CALCTRL_DOWNSEL_LFXO 0x00000002UL /**< Mode LFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2425 #define _CMU_CALCTRL_DOWNSEL_HFRCO 0x00000003UL /**< Mode HFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2426 #define _CMU_CALCTRL_DOWNSEL_LFRCO 0x00000004UL /**< Mode LFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2427 #define _CMU_CALCTRL_DOWNSEL_AUXHFRCO 0x00000005UL /**< Mode AUXHFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2428 #define CMU_CALCTRL_DOWNSEL_DEFAULT (_CMU_CALCTRL_DOWNSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2429 #define CMU_CALCTRL_DOWNSEL_HFCLK (_CMU_CALCTRL_DOWNSEL_HFCLK << 3) /**< Shifted mode HFCLK for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2430 #define CMU_CALCTRL_DOWNSEL_HFXO (_CMU_CALCTRL_DOWNSEL_HFXO << 3) /**< Shifted mode HFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2431 #define CMU_CALCTRL_DOWNSEL_LFXO (_CMU_CALCTRL_DOWNSEL_LFXO << 3) /**< Shifted mode LFXO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2432 #define CMU_CALCTRL_DOWNSEL_HFRCO (_CMU_CALCTRL_DOWNSEL_HFRCO << 3) /**< Shifted mode HFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2433 #define CMU_CALCTRL_DOWNSEL_LFRCO (_CMU_CALCTRL_DOWNSEL_LFRCO << 3) /**< Shifted mode LFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2434 #define CMU_CALCTRL_DOWNSEL_AUXHFRCO (_CMU_CALCTRL_DOWNSEL_AUXHFRCO << 3) /**< Shifted mode AUXHFRCO for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2435 #define CMU_CALCTRL_CONT (0x1UL << 6) /**< Continuous Calibration */
AnnaBridge 171:3a7713b1edbc 2436 #define _CMU_CALCTRL_CONT_SHIFT 6 /**< Shift value for CMU_CONT */
AnnaBridge 171:3a7713b1edbc 2437 #define _CMU_CALCTRL_CONT_MASK 0x40UL /**< Bit mask for CMU_CONT */
AnnaBridge 171:3a7713b1edbc 2438 #define _CMU_CALCTRL_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2439 #define CMU_CALCTRL_CONT_DEFAULT (_CMU_CALCTRL_CONT_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_CALCTRL */
AnnaBridge 171:3a7713b1edbc 2440
AnnaBridge 171:3a7713b1edbc 2441 /* Bit fields for CMU CALCNT */
AnnaBridge 171:3a7713b1edbc 2442 #define _CMU_CALCNT_RESETVALUE 0x00000000UL /**< Default value for CMU_CALCNT */
AnnaBridge 171:3a7713b1edbc 2443 #define _CMU_CALCNT_MASK 0x000FFFFFUL /**< Mask for CMU_CALCNT */
AnnaBridge 171:3a7713b1edbc 2444 #define _CMU_CALCNT_CALCNT_SHIFT 0 /**< Shift value for CMU_CALCNT */
AnnaBridge 171:3a7713b1edbc 2445 #define _CMU_CALCNT_CALCNT_MASK 0xFFFFFUL /**< Bit mask for CMU_CALCNT */
AnnaBridge 171:3a7713b1edbc 2446 #define _CMU_CALCNT_CALCNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CALCNT */
AnnaBridge 171:3a7713b1edbc 2447 #define CMU_CALCNT_CALCNT_DEFAULT (_CMU_CALCNT_CALCNT_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CALCNT */
AnnaBridge 171:3a7713b1edbc 2448
AnnaBridge 171:3a7713b1edbc 2449 /* Bit fields for CMU OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2450 #define _CMU_OSCENCMD_RESETVALUE 0x00000000UL /**< Default value for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2451 #define _CMU_OSCENCMD_MASK 0x000003FFUL /**< Mask for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2452 #define CMU_OSCENCMD_HFRCOEN (0x1UL << 0) /**< HFRCO Enable */
AnnaBridge 171:3a7713b1edbc 2453 #define _CMU_OSCENCMD_HFRCOEN_SHIFT 0 /**< Shift value for CMU_HFRCOEN */
AnnaBridge 171:3a7713b1edbc 2454 #define _CMU_OSCENCMD_HFRCOEN_MASK 0x1UL /**< Bit mask for CMU_HFRCOEN */
AnnaBridge 171:3a7713b1edbc 2455 #define _CMU_OSCENCMD_HFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2456 #define CMU_OSCENCMD_HFRCOEN_DEFAULT (_CMU_OSCENCMD_HFRCOEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2457 #define CMU_OSCENCMD_HFRCODIS (0x1UL << 1) /**< HFRCO Disable */
AnnaBridge 171:3a7713b1edbc 2458 #define _CMU_OSCENCMD_HFRCODIS_SHIFT 1 /**< Shift value for CMU_HFRCODIS */
AnnaBridge 171:3a7713b1edbc 2459 #define _CMU_OSCENCMD_HFRCODIS_MASK 0x2UL /**< Bit mask for CMU_HFRCODIS */
AnnaBridge 171:3a7713b1edbc 2460 #define _CMU_OSCENCMD_HFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2461 #define CMU_OSCENCMD_HFRCODIS_DEFAULT (_CMU_OSCENCMD_HFRCODIS_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2462 #define CMU_OSCENCMD_HFXOEN (0x1UL << 2) /**< HFXO Enable */
AnnaBridge 171:3a7713b1edbc 2463 #define _CMU_OSCENCMD_HFXOEN_SHIFT 2 /**< Shift value for CMU_HFXOEN */
AnnaBridge 171:3a7713b1edbc 2464 #define _CMU_OSCENCMD_HFXOEN_MASK 0x4UL /**< Bit mask for CMU_HFXOEN */
AnnaBridge 171:3a7713b1edbc 2465 #define _CMU_OSCENCMD_HFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2466 #define CMU_OSCENCMD_HFXOEN_DEFAULT (_CMU_OSCENCMD_HFXOEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2467 #define CMU_OSCENCMD_HFXODIS (0x1UL << 3) /**< HFXO Disable */
AnnaBridge 171:3a7713b1edbc 2468 #define _CMU_OSCENCMD_HFXODIS_SHIFT 3 /**< Shift value for CMU_HFXODIS */
AnnaBridge 171:3a7713b1edbc 2469 #define _CMU_OSCENCMD_HFXODIS_MASK 0x8UL /**< Bit mask for CMU_HFXODIS */
AnnaBridge 171:3a7713b1edbc 2470 #define _CMU_OSCENCMD_HFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2471 #define CMU_OSCENCMD_HFXODIS_DEFAULT (_CMU_OSCENCMD_HFXODIS_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2472 #define CMU_OSCENCMD_AUXHFRCOEN (0x1UL << 4) /**< AUXHFRCO Enable */
AnnaBridge 171:3a7713b1edbc 2473 #define _CMU_OSCENCMD_AUXHFRCOEN_SHIFT 4 /**< Shift value for CMU_AUXHFRCOEN */
AnnaBridge 171:3a7713b1edbc 2474 #define _CMU_OSCENCMD_AUXHFRCOEN_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOEN */
AnnaBridge 171:3a7713b1edbc 2475 #define _CMU_OSCENCMD_AUXHFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2476 #define CMU_OSCENCMD_AUXHFRCOEN_DEFAULT (_CMU_OSCENCMD_AUXHFRCOEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2477 #define CMU_OSCENCMD_AUXHFRCODIS (0x1UL << 5) /**< AUXHFRCO Disable */
AnnaBridge 171:3a7713b1edbc 2478 #define _CMU_OSCENCMD_AUXHFRCODIS_SHIFT 5 /**< Shift value for CMU_AUXHFRCODIS */
AnnaBridge 171:3a7713b1edbc 2479 #define _CMU_OSCENCMD_AUXHFRCODIS_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCODIS */
AnnaBridge 171:3a7713b1edbc 2480 #define _CMU_OSCENCMD_AUXHFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2481 #define CMU_OSCENCMD_AUXHFRCODIS_DEFAULT (_CMU_OSCENCMD_AUXHFRCODIS_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2482 #define CMU_OSCENCMD_LFRCOEN (0x1UL << 6) /**< LFRCO Enable */
AnnaBridge 171:3a7713b1edbc 2483 #define _CMU_OSCENCMD_LFRCOEN_SHIFT 6 /**< Shift value for CMU_LFRCOEN */
AnnaBridge 171:3a7713b1edbc 2484 #define _CMU_OSCENCMD_LFRCOEN_MASK 0x40UL /**< Bit mask for CMU_LFRCOEN */
AnnaBridge 171:3a7713b1edbc 2485 #define _CMU_OSCENCMD_LFRCOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2486 #define CMU_OSCENCMD_LFRCOEN_DEFAULT (_CMU_OSCENCMD_LFRCOEN_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2487 #define CMU_OSCENCMD_LFRCODIS (0x1UL << 7) /**< LFRCO Disable */
AnnaBridge 171:3a7713b1edbc 2488 #define _CMU_OSCENCMD_LFRCODIS_SHIFT 7 /**< Shift value for CMU_LFRCODIS */
AnnaBridge 171:3a7713b1edbc 2489 #define _CMU_OSCENCMD_LFRCODIS_MASK 0x80UL /**< Bit mask for CMU_LFRCODIS */
AnnaBridge 171:3a7713b1edbc 2490 #define _CMU_OSCENCMD_LFRCODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2491 #define CMU_OSCENCMD_LFRCODIS_DEFAULT (_CMU_OSCENCMD_LFRCODIS_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2492 #define CMU_OSCENCMD_LFXOEN (0x1UL << 8) /**< LFXO Enable */
AnnaBridge 171:3a7713b1edbc 2493 #define _CMU_OSCENCMD_LFXOEN_SHIFT 8 /**< Shift value for CMU_LFXOEN */
AnnaBridge 171:3a7713b1edbc 2494 #define _CMU_OSCENCMD_LFXOEN_MASK 0x100UL /**< Bit mask for CMU_LFXOEN */
AnnaBridge 171:3a7713b1edbc 2495 #define _CMU_OSCENCMD_LFXOEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2496 #define CMU_OSCENCMD_LFXOEN_DEFAULT (_CMU_OSCENCMD_LFXOEN_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2497 #define CMU_OSCENCMD_LFXODIS (0x1UL << 9) /**< LFXO Disable */
AnnaBridge 171:3a7713b1edbc 2498 #define _CMU_OSCENCMD_LFXODIS_SHIFT 9 /**< Shift value for CMU_LFXODIS */
AnnaBridge 171:3a7713b1edbc 2499 #define _CMU_OSCENCMD_LFXODIS_MASK 0x200UL /**< Bit mask for CMU_LFXODIS */
AnnaBridge 171:3a7713b1edbc 2500 #define _CMU_OSCENCMD_LFXODIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2501 #define CMU_OSCENCMD_LFXODIS_DEFAULT (_CMU_OSCENCMD_LFXODIS_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_OSCENCMD */
AnnaBridge 171:3a7713b1edbc 2502
AnnaBridge 171:3a7713b1edbc 2503 /* Bit fields for CMU CMD */
AnnaBridge 171:3a7713b1edbc 2504 #define _CMU_CMD_RESETVALUE 0x00000000UL /**< Default value for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2505 #define _CMU_CMD_MASK 0x0000001FUL /**< Mask for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2506 #define _CMU_CMD_HFCLKSEL_SHIFT 0 /**< Shift value for CMU_HFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2507 #define _CMU_CMD_HFCLKSEL_MASK 0x7UL /**< Bit mask for CMU_HFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2508 #define _CMU_CMD_HFCLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2509 #define _CMU_CMD_HFCLKSEL_HFRCO 0x00000001UL /**< Mode HFRCO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2510 #define _CMU_CMD_HFCLKSEL_HFXO 0x00000002UL /**< Mode HFXO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2511 #define _CMU_CMD_HFCLKSEL_LFRCO 0x00000003UL /**< Mode LFRCO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2512 #define _CMU_CMD_HFCLKSEL_LFXO 0x00000004UL /**< Mode LFXO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2513 #define CMU_CMD_HFCLKSEL_DEFAULT (_CMU_CMD_HFCLKSEL_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2514 #define CMU_CMD_HFCLKSEL_HFRCO (_CMU_CMD_HFCLKSEL_HFRCO << 0) /**< Shifted mode HFRCO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2515 #define CMU_CMD_HFCLKSEL_HFXO (_CMU_CMD_HFCLKSEL_HFXO << 0) /**< Shifted mode HFXO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2516 #define CMU_CMD_HFCLKSEL_LFRCO (_CMU_CMD_HFCLKSEL_LFRCO << 0) /**< Shifted mode LFRCO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2517 #define CMU_CMD_HFCLKSEL_LFXO (_CMU_CMD_HFCLKSEL_LFXO << 0) /**< Shifted mode LFXO for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2518 #define CMU_CMD_CALSTART (0x1UL << 3) /**< Calibration Start */
AnnaBridge 171:3a7713b1edbc 2519 #define _CMU_CMD_CALSTART_SHIFT 3 /**< Shift value for CMU_CALSTART */
AnnaBridge 171:3a7713b1edbc 2520 #define _CMU_CMD_CALSTART_MASK 0x8UL /**< Bit mask for CMU_CALSTART */
AnnaBridge 171:3a7713b1edbc 2521 #define _CMU_CMD_CALSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2522 #define CMU_CMD_CALSTART_DEFAULT (_CMU_CMD_CALSTART_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2523 #define CMU_CMD_CALSTOP (0x1UL << 4) /**< Calibration Stop */
AnnaBridge 171:3a7713b1edbc 2524 #define _CMU_CMD_CALSTOP_SHIFT 4 /**< Shift value for CMU_CALSTOP */
AnnaBridge 171:3a7713b1edbc 2525 #define _CMU_CMD_CALSTOP_MASK 0x10UL /**< Bit mask for CMU_CALSTOP */
AnnaBridge 171:3a7713b1edbc 2526 #define _CMU_CMD_CALSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2527 #define CMU_CMD_CALSTOP_DEFAULT (_CMU_CMD_CALSTOP_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_CMD */
AnnaBridge 171:3a7713b1edbc 2528
AnnaBridge 171:3a7713b1edbc 2529 /* Bit fields for CMU LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2530 #define _CMU_LFCLKSEL_RESETVALUE 0x00000005UL /**< Default value for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2531 #define _CMU_LFCLKSEL_MASK 0x0011000FUL /**< Mask for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2532 #define _CMU_LFCLKSEL_LFA_SHIFT 0 /**< Shift value for CMU_LFA */
AnnaBridge 171:3a7713b1edbc 2533 #define _CMU_LFCLKSEL_LFA_MASK 0x3UL /**< Bit mask for CMU_LFA */
AnnaBridge 171:3a7713b1edbc 2534 #define _CMU_LFCLKSEL_LFA_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2535 #define _CMU_LFCLKSEL_LFA_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2536 #define _CMU_LFCLKSEL_LFA_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2537 #define _CMU_LFCLKSEL_LFA_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2538 #define _CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2539 #define CMU_LFCLKSEL_LFA_DISABLED (_CMU_LFCLKSEL_LFA_DISABLED << 0) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2540 #define CMU_LFCLKSEL_LFA_DEFAULT (_CMU_LFCLKSEL_LFA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2541 #define CMU_LFCLKSEL_LFA_LFRCO (_CMU_LFCLKSEL_LFA_LFRCO << 0) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2542 #define CMU_LFCLKSEL_LFA_LFXO (_CMU_LFCLKSEL_LFA_LFXO << 0) /**< Shifted mode LFXO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2543 #define CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFA_HFCORECLKLEDIV2 << 0) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2544 #define _CMU_LFCLKSEL_LFB_SHIFT 2 /**< Shift value for CMU_LFB */
AnnaBridge 171:3a7713b1edbc 2545 #define _CMU_LFCLKSEL_LFB_MASK 0xCUL /**< Bit mask for CMU_LFB */
AnnaBridge 171:3a7713b1edbc 2546 #define _CMU_LFCLKSEL_LFB_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2547 #define _CMU_LFCLKSEL_LFB_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2548 #define _CMU_LFCLKSEL_LFB_LFRCO 0x00000001UL /**< Mode LFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2549 #define _CMU_LFCLKSEL_LFB_LFXO 0x00000002UL /**< Mode LFXO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2550 #define _CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 0x00000003UL /**< Mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2551 #define CMU_LFCLKSEL_LFB_DISABLED (_CMU_LFCLKSEL_LFB_DISABLED << 2) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2552 #define CMU_LFCLKSEL_LFB_DEFAULT (_CMU_LFCLKSEL_LFB_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2553 #define CMU_LFCLKSEL_LFB_LFRCO (_CMU_LFCLKSEL_LFB_LFRCO << 2) /**< Shifted mode LFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2554 #define CMU_LFCLKSEL_LFB_LFXO (_CMU_LFCLKSEL_LFB_LFXO << 2) /**< Shifted mode LFXO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2555 #define CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 (_CMU_LFCLKSEL_LFB_HFCORECLKLEDIV2 << 2) /**< Shifted mode HFCORECLKLEDIV2 for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2556 #define CMU_LFCLKSEL_LFAE (0x1UL << 16) /**< Clock Select for LFA Extended */
AnnaBridge 171:3a7713b1edbc 2557 #define _CMU_LFCLKSEL_LFAE_SHIFT 16 /**< Shift value for CMU_LFAE */
AnnaBridge 171:3a7713b1edbc 2558 #define _CMU_LFCLKSEL_LFAE_MASK 0x10000UL /**< Bit mask for CMU_LFAE */
AnnaBridge 171:3a7713b1edbc 2559 #define _CMU_LFCLKSEL_LFAE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2560 #define _CMU_LFCLKSEL_LFAE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2561 #define _CMU_LFCLKSEL_LFAE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2562 #define CMU_LFCLKSEL_LFAE_DEFAULT (_CMU_LFCLKSEL_LFAE_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2563 #define CMU_LFCLKSEL_LFAE_DISABLED (_CMU_LFCLKSEL_LFAE_DISABLED << 16) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2564 #define CMU_LFCLKSEL_LFAE_ULFRCO (_CMU_LFCLKSEL_LFAE_ULFRCO << 16) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2565 #define CMU_LFCLKSEL_LFBE (0x1UL << 20) /**< Clock Select for LFB Extended */
AnnaBridge 171:3a7713b1edbc 2566 #define _CMU_LFCLKSEL_LFBE_SHIFT 20 /**< Shift value for CMU_LFBE */
AnnaBridge 171:3a7713b1edbc 2567 #define _CMU_LFCLKSEL_LFBE_MASK 0x100000UL /**< Bit mask for CMU_LFBE */
AnnaBridge 171:3a7713b1edbc 2568 #define _CMU_LFCLKSEL_LFBE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2569 #define _CMU_LFCLKSEL_LFBE_DISABLED 0x00000000UL /**< Mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2570 #define _CMU_LFCLKSEL_LFBE_ULFRCO 0x00000001UL /**< Mode ULFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2571 #define CMU_LFCLKSEL_LFBE_DEFAULT (_CMU_LFCLKSEL_LFBE_DEFAULT << 20) /**< Shifted mode DEFAULT for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2572 #define CMU_LFCLKSEL_LFBE_DISABLED (_CMU_LFCLKSEL_LFBE_DISABLED << 20) /**< Shifted mode DISABLED for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2573 #define CMU_LFCLKSEL_LFBE_ULFRCO (_CMU_LFCLKSEL_LFBE_ULFRCO << 20) /**< Shifted mode ULFRCO for CMU_LFCLKSEL */
AnnaBridge 171:3a7713b1edbc 2574
AnnaBridge 171:3a7713b1edbc 2575 /* Bit fields for CMU STATUS */
AnnaBridge 171:3a7713b1edbc 2576 #define _CMU_STATUS_RESETVALUE 0x00000403UL /**< Default value for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2577 #define _CMU_STATUS_MASK 0x00007FFFUL /**< Mask for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2578 #define CMU_STATUS_HFRCOENS (0x1UL << 0) /**< HFRCO Enable Status */
AnnaBridge 171:3a7713b1edbc 2579 #define _CMU_STATUS_HFRCOENS_SHIFT 0 /**< Shift value for CMU_HFRCOENS */
AnnaBridge 171:3a7713b1edbc 2580 #define _CMU_STATUS_HFRCOENS_MASK 0x1UL /**< Bit mask for CMU_HFRCOENS */
AnnaBridge 171:3a7713b1edbc 2581 #define _CMU_STATUS_HFRCOENS_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2582 #define CMU_STATUS_HFRCOENS_DEFAULT (_CMU_STATUS_HFRCOENS_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2583 #define CMU_STATUS_HFRCORDY (0x1UL << 1) /**< HFRCO Ready */
AnnaBridge 171:3a7713b1edbc 2584 #define _CMU_STATUS_HFRCORDY_SHIFT 1 /**< Shift value for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2585 #define _CMU_STATUS_HFRCORDY_MASK 0x2UL /**< Bit mask for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2586 #define _CMU_STATUS_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2587 #define CMU_STATUS_HFRCORDY_DEFAULT (_CMU_STATUS_HFRCORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2588 #define CMU_STATUS_HFXOENS (0x1UL << 2) /**< HFXO Enable Status */
AnnaBridge 171:3a7713b1edbc 2589 #define _CMU_STATUS_HFXOENS_SHIFT 2 /**< Shift value for CMU_HFXOENS */
AnnaBridge 171:3a7713b1edbc 2590 #define _CMU_STATUS_HFXOENS_MASK 0x4UL /**< Bit mask for CMU_HFXOENS */
AnnaBridge 171:3a7713b1edbc 2591 #define _CMU_STATUS_HFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2592 #define CMU_STATUS_HFXOENS_DEFAULT (_CMU_STATUS_HFXOENS_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2593 #define CMU_STATUS_HFXORDY (0x1UL << 3) /**< HFXO Ready */
AnnaBridge 171:3a7713b1edbc 2594 #define _CMU_STATUS_HFXORDY_SHIFT 3 /**< Shift value for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2595 #define _CMU_STATUS_HFXORDY_MASK 0x8UL /**< Bit mask for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2596 #define _CMU_STATUS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2597 #define CMU_STATUS_HFXORDY_DEFAULT (_CMU_STATUS_HFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2598 #define CMU_STATUS_AUXHFRCOENS (0x1UL << 4) /**< AUXHFRCO Enable Status */
AnnaBridge 171:3a7713b1edbc 2599 #define _CMU_STATUS_AUXHFRCOENS_SHIFT 4 /**< Shift value for CMU_AUXHFRCOENS */
AnnaBridge 171:3a7713b1edbc 2600 #define _CMU_STATUS_AUXHFRCOENS_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCOENS */
AnnaBridge 171:3a7713b1edbc 2601 #define _CMU_STATUS_AUXHFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2602 #define CMU_STATUS_AUXHFRCOENS_DEFAULT (_CMU_STATUS_AUXHFRCOENS_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2603 #define CMU_STATUS_AUXHFRCORDY (0x1UL << 5) /**< AUXHFRCO Ready */
AnnaBridge 171:3a7713b1edbc 2604 #define _CMU_STATUS_AUXHFRCORDY_SHIFT 5 /**< Shift value for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2605 #define _CMU_STATUS_AUXHFRCORDY_MASK 0x20UL /**< Bit mask for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2606 #define _CMU_STATUS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2607 #define CMU_STATUS_AUXHFRCORDY_DEFAULT (_CMU_STATUS_AUXHFRCORDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2608 #define CMU_STATUS_LFRCOENS (0x1UL << 6) /**< LFRCO Enable Status */
AnnaBridge 171:3a7713b1edbc 2609 #define _CMU_STATUS_LFRCOENS_SHIFT 6 /**< Shift value for CMU_LFRCOENS */
AnnaBridge 171:3a7713b1edbc 2610 #define _CMU_STATUS_LFRCOENS_MASK 0x40UL /**< Bit mask for CMU_LFRCOENS */
AnnaBridge 171:3a7713b1edbc 2611 #define _CMU_STATUS_LFRCOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2612 #define CMU_STATUS_LFRCOENS_DEFAULT (_CMU_STATUS_LFRCOENS_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2613 #define CMU_STATUS_LFRCORDY (0x1UL << 7) /**< LFRCO Ready */
AnnaBridge 171:3a7713b1edbc 2614 #define _CMU_STATUS_LFRCORDY_SHIFT 7 /**< Shift value for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2615 #define _CMU_STATUS_LFRCORDY_MASK 0x80UL /**< Bit mask for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2616 #define _CMU_STATUS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2617 #define CMU_STATUS_LFRCORDY_DEFAULT (_CMU_STATUS_LFRCORDY_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2618 #define CMU_STATUS_LFXOENS (0x1UL << 8) /**< LFXO Enable Status */
AnnaBridge 171:3a7713b1edbc 2619 #define _CMU_STATUS_LFXOENS_SHIFT 8 /**< Shift value for CMU_LFXOENS */
AnnaBridge 171:3a7713b1edbc 2620 #define _CMU_STATUS_LFXOENS_MASK 0x100UL /**< Bit mask for CMU_LFXOENS */
AnnaBridge 171:3a7713b1edbc 2621 #define _CMU_STATUS_LFXOENS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2622 #define CMU_STATUS_LFXOENS_DEFAULT (_CMU_STATUS_LFXOENS_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2623 #define CMU_STATUS_LFXORDY (0x1UL << 9) /**< LFXO Ready */
AnnaBridge 171:3a7713b1edbc 2624 #define _CMU_STATUS_LFXORDY_SHIFT 9 /**< Shift value for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2625 #define _CMU_STATUS_LFXORDY_MASK 0x200UL /**< Bit mask for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2626 #define _CMU_STATUS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2627 #define CMU_STATUS_LFXORDY_DEFAULT (_CMU_STATUS_LFXORDY_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2628 #define CMU_STATUS_HFRCOSEL (0x1UL << 10) /**< HFRCO Selected */
AnnaBridge 171:3a7713b1edbc 2629 #define _CMU_STATUS_HFRCOSEL_SHIFT 10 /**< Shift value for CMU_HFRCOSEL */
AnnaBridge 171:3a7713b1edbc 2630 #define _CMU_STATUS_HFRCOSEL_MASK 0x400UL /**< Bit mask for CMU_HFRCOSEL */
AnnaBridge 171:3a7713b1edbc 2631 #define _CMU_STATUS_HFRCOSEL_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2632 #define CMU_STATUS_HFRCOSEL_DEFAULT (_CMU_STATUS_HFRCOSEL_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2633 #define CMU_STATUS_HFXOSEL (0x1UL << 11) /**< HFXO Selected */
AnnaBridge 171:3a7713b1edbc 2634 #define _CMU_STATUS_HFXOSEL_SHIFT 11 /**< Shift value for CMU_HFXOSEL */
AnnaBridge 171:3a7713b1edbc 2635 #define _CMU_STATUS_HFXOSEL_MASK 0x800UL /**< Bit mask for CMU_HFXOSEL */
AnnaBridge 171:3a7713b1edbc 2636 #define _CMU_STATUS_HFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2637 #define CMU_STATUS_HFXOSEL_DEFAULT (_CMU_STATUS_HFXOSEL_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2638 #define CMU_STATUS_LFRCOSEL (0x1UL << 12) /**< LFRCO Selected */
AnnaBridge 171:3a7713b1edbc 2639 #define _CMU_STATUS_LFRCOSEL_SHIFT 12 /**< Shift value for CMU_LFRCOSEL */
AnnaBridge 171:3a7713b1edbc 2640 #define _CMU_STATUS_LFRCOSEL_MASK 0x1000UL /**< Bit mask for CMU_LFRCOSEL */
AnnaBridge 171:3a7713b1edbc 2641 #define _CMU_STATUS_LFRCOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2642 #define CMU_STATUS_LFRCOSEL_DEFAULT (_CMU_STATUS_LFRCOSEL_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2643 #define CMU_STATUS_LFXOSEL (0x1UL << 13) /**< LFXO Selected */
AnnaBridge 171:3a7713b1edbc 2644 #define _CMU_STATUS_LFXOSEL_SHIFT 13 /**< Shift value for CMU_LFXOSEL */
AnnaBridge 171:3a7713b1edbc 2645 #define _CMU_STATUS_LFXOSEL_MASK 0x2000UL /**< Bit mask for CMU_LFXOSEL */
AnnaBridge 171:3a7713b1edbc 2646 #define _CMU_STATUS_LFXOSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2647 #define CMU_STATUS_LFXOSEL_DEFAULT (_CMU_STATUS_LFXOSEL_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2648 #define CMU_STATUS_CALBSY (0x1UL << 14) /**< Calibration Busy */
AnnaBridge 171:3a7713b1edbc 2649 #define _CMU_STATUS_CALBSY_SHIFT 14 /**< Shift value for CMU_CALBSY */
AnnaBridge 171:3a7713b1edbc 2650 #define _CMU_STATUS_CALBSY_MASK 0x4000UL /**< Bit mask for CMU_CALBSY */
AnnaBridge 171:3a7713b1edbc 2651 #define _CMU_STATUS_CALBSY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2652 #define CMU_STATUS_CALBSY_DEFAULT (_CMU_STATUS_CALBSY_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_STATUS */
AnnaBridge 171:3a7713b1edbc 2653
AnnaBridge 171:3a7713b1edbc 2654 /* Bit fields for CMU IF */
AnnaBridge 171:3a7713b1edbc 2655 #define _CMU_IF_RESETVALUE 0x00000001UL /**< Default value for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2656 #define _CMU_IF_MASK 0x0000007FUL /**< Mask for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2657 #define CMU_IF_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2658 #define _CMU_IF_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2659 #define _CMU_IF_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2660 #define _CMU_IF_HFRCORDY_DEFAULT 0x00000001UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2661 #define CMU_IF_HFRCORDY_DEFAULT (_CMU_IF_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2662 #define CMU_IF_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2663 #define _CMU_IF_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2664 #define _CMU_IF_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2665 #define _CMU_IF_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2666 #define CMU_IF_HFXORDY_DEFAULT (_CMU_IF_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2667 #define CMU_IF_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2668 #define _CMU_IF_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2669 #define _CMU_IF_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2670 #define _CMU_IF_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2671 #define CMU_IF_LFRCORDY_DEFAULT (_CMU_IF_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2672 #define CMU_IF_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2673 #define _CMU_IF_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2674 #define _CMU_IF_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2675 #define _CMU_IF_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2676 #define CMU_IF_LFXORDY_DEFAULT (_CMU_IF_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2677 #define CMU_IF_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2678 #define _CMU_IF_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2679 #define _CMU_IF_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2680 #define _CMU_IF_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2681 #define CMU_IF_AUXHFRCORDY_DEFAULT (_CMU_IF_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2682 #define CMU_IF_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2683 #define _CMU_IF_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2684 #define _CMU_IF_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2685 #define _CMU_IF_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2686 #define CMU_IF_CALRDY_DEFAULT (_CMU_IF_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2687 #define CMU_IF_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag */
AnnaBridge 171:3a7713b1edbc 2688 #define _CMU_IF_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2689 #define _CMU_IF_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2690 #define _CMU_IF_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2691 #define CMU_IF_CALOF_DEFAULT (_CMU_IF_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IF */
AnnaBridge 171:3a7713b1edbc 2692
AnnaBridge 171:3a7713b1edbc 2693 /* Bit fields for CMU IFS */
AnnaBridge 171:3a7713b1edbc 2694 #define _CMU_IFS_RESETVALUE 0x00000000UL /**< Default value for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2695 #define _CMU_IFS_MASK 0x0000007FUL /**< Mask for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2696 #define CMU_IFS_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2697 #define _CMU_IFS_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2698 #define _CMU_IFS_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2699 #define _CMU_IFS_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2700 #define CMU_IFS_HFRCORDY_DEFAULT (_CMU_IFS_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2701 #define CMU_IFS_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2702 #define _CMU_IFS_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2703 #define _CMU_IFS_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2704 #define _CMU_IFS_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2705 #define CMU_IFS_HFXORDY_DEFAULT (_CMU_IFS_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2706 #define CMU_IFS_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2707 #define _CMU_IFS_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2708 #define _CMU_IFS_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2709 #define _CMU_IFS_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2710 #define CMU_IFS_LFRCORDY_DEFAULT (_CMU_IFS_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2711 #define CMU_IFS_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2712 #define _CMU_IFS_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2713 #define _CMU_IFS_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2714 #define _CMU_IFS_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2715 #define CMU_IFS_LFXORDY_DEFAULT (_CMU_IFS_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2716 #define CMU_IFS_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2717 #define _CMU_IFS_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2718 #define _CMU_IFS_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2719 #define _CMU_IFS_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2720 #define CMU_IFS_AUXHFRCORDY_DEFAULT (_CMU_IFS_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2721 #define CMU_IFS_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2722 #define _CMU_IFS_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2723 #define _CMU_IFS_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2724 #define _CMU_IFS_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2725 #define CMU_IFS_CALRDY_DEFAULT (_CMU_IFS_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2726 #define CMU_IFS_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Set */
AnnaBridge 171:3a7713b1edbc 2727 #define _CMU_IFS_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2728 #define _CMU_IFS_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2729 #define _CMU_IFS_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2730 #define CMU_IFS_CALOF_DEFAULT (_CMU_IFS_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFS */
AnnaBridge 171:3a7713b1edbc 2731
AnnaBridge 171:3a7713b1edbc 2732 /* Bit fields for CMU IFC */
AnnaBridge 171:3a7713b1edbc 2733 #define _CMU_IFC_RESETVALUE 0x00000000UL /**< Default value for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2734 #define _CMU_IFC_MASK 0x0000007FUL /**< Mask for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2735 #define CMU_IFC_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2736 #define _CMU_IFC_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2737 #define _CMU_IFC_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2738 #define _CMU_IFC_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2739 #define CMU_IFC_HFRCORDY_DEFAULT (_CMU_IFC_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2740 #define CMU_IFC_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2741 #define _CMU_IFC_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2742 #define _CMU_IFC_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2743 #define _CMU_IFC_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2744 #define CMU_IFC_HFXORDY_DEFAULT (_CMU_IFC_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2745 #define CMU_IFC_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2746 #define _CMU_IFC_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2747 #define _CMU_IFC_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2748 #define _CMU_IFC_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2749 #define CMU_IFC_LFRCORDY_DEFAULT (_CMU_IFC_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2750 #define CMU_IFC_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2751 #define _CMU_IFC_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2752 #define _CMU_IFC_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2753 #define _CMU_IFC_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2754 #define CMU_IFC_LFXORDY_DEFAULT (_CMU_IFC_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2755 #define CMU_IFC_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2756 #define _CMU_IFC_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2757 #define _CMU_IFC_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2758 #define _CMU_IFC_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2759 #define CMU_IFC_AUXHFRCORDY_DEFAULT (_CMU_IFC_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2760 #define CMU_IFC_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2761 #define _CMU_IFC_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2762 #define _CMU_IFC_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2763 #define _CMU_IFC_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2764 #define CMU_IFC_CALRDY_DEFAULT (_CMU_IFC_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2765 #define CMU_IFC_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Flag Clear */
AnnaBridge 171:3a7713b1edbc 2766 #define _CMU_IFC_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2767 #define _CMU_IFC_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2768 #define _CMU_IFC_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2769 #define CMU_IFC_CALOF_DEFAULT (_CMU_IFC_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IFC */
AnnaBridge 171:3a7713b1edbc 2770
AnnaBridge 171:3a7713b1edbc 2771 /* Bit fields for CMU IEN */
AnnaBridge 171:3a7713b1edbc 2772 #define _CMU_IEN_RESETVALUE 0x00000000UL /**< Default value for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2773 #define _CMU_IEN_MASK 0x0000007FUL /**< Mask for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2774 #define CMU_IEN_HFRCORDY (0x1UL << 0) /**< HFRCO Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2775 #define _CMU_IEN_HFRCORDY_SHIFT 0 /**< Shift value for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2776 #define _CMU_IEN_HFRCORDY_MASK 0x1UL /**< Bit mask for CMU_HFRCORDY */
AnnaBridge 171:3a7713b1edbc 2777 #define _CMU_IEN_HFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2778 #define CMU_IEN_HFRCORDY_DEFAULT (_CMU_IEN_HFRCORDY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2779 #define CMU_IEN_HFXORDY (0x1UL << 1) /**< HFXO Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2780 #define _CMU_IEN_HFXORDY_SHIFT 1 /**< Shift value for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2781 #define _CMU_IEN_HFXORDY_MASK 0x2UL /**< Bit mask for CMU_HFXORDY */
AnnaBridge 171:3a7713b1edbc 2782 #define _CMU_IEN_HFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2783 #define CMU_IEN_HFXORDY_DEFAULT (_CMU_IEN_HFXORDY_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2784 #define CMU_IEN_LFRCORDY (0x1UL << 2) /**< LFRCO Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2785 #define _CMU_IEN_LFRCORDY_SHIFT 2 /**< Shift value for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2786 #define _CMU_IEN_LFRCORDY_MASK 0x4UL /**< Bit mask for CMU_LFRCORDY */
AnnaBridge 171:3a7713b1edbc 2787 #define _CMU_IEN_LFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2788 #define CMU_IEN_LFRCORDY_DEFAULT (_CMU_IEN_LFRCORDY_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2789 #define CMU_IEN_LFXORDY (0x1UL << 3) /**< LFXO Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2790 #define _CMU_IEN_LFXORDY_SHIFT 3 /**< Shift value for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2791 #define _CMU_IEN_LFXORDY_MASK 0x8UL /**< Bit mask for CMU_LFXORDY */
AnnaBridge 171:3a7713b1edbc 2792 #define _CMU_IEN_LFXORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2793 #define CMU_IEN_LFXORDY_DEFAULT (_CMU_IEN_LFXORDY_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2794 #define CMU_IEN_AUXHFRCORDY (0x1UL << 4) /**< AUXHFRCO Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2795 #define _CMU_IEN_AUXHFRCORDY_SHIFT 4 /**< Shift value for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2796 #define _CMU_IEN_AUXHFRCORDY_MASK 0x10UL /**< Bit mask for CMU_AUXHFRCORDY */
AnnaBridge 171:3a7713b1edbc 2797 #define _CMU_IEN_AUXHFRCORDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2798 #define CMU_IEN_AUXHFRCORDY_DEFAULT (_CMU_IEN_AUXHFRCORDY_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2799 #define CMU_IEN_CALRDY (0x1UL << 5) /**< Calibration Ready Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2800 #define _CMU_IEN_CALRDY_SHIFT 5 /**< Shift value for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2801 #define _CMU_IEN_CALRDY_MASK 0x20UL /**< Bit mask for CMU_CALRDY */
AnnaBridge 171:3a7713b1edbc 2802 #define _CMU_IEN_CALRDY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2803 #define CMU_IEN_CALRDY_DEFAULT (_CMU_IEN_CALRDY_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2804 #define CMU_IEN_CALOF (0x1UL << 6) /**< Calibration Overflow Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 2805 #define _CMU_IEN_CALOF_SHIFT 6 /**< Shift value for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2806 #define _CMU_IEN_CALOF_MASK 0x40UL /**< Bit mask for CMU_CALOF */
AnnaBridge 171:3a7713b1edbc 2807 #define _CMU_IEN_CALOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2808 #define CMU_IEN_CALOF_DEFAULT (_CMU_IEN_CALOF_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_IEN */
AnnaBridge 171:3a7713b1edbc 2809
AnnaBridge 171:3a7713b1edbc 2810 /* Bit fields for CMU HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2811 #define _CMU_HFCORECLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2812 #define _CMU_HFCORECLKEN0_MASK 0x00000013UL /**< Mask for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2813 #define CMU_HFCORECLKEN0_DMA (0x1UL << 0) /**< Direct Memory Access Controller Clock Enable */
AnnaBridge 171:3a7713b1edbc 2814 #define _CMU_HFCORECLKEN0_DMA_SHIFT 0 /**< Shift value for CMU_DMA */
AnnaBridge 171:3a7713b1edbc 2815 #define _CMU_HFCORECLKEN0_DMA_MASK 0x1UL /**< Bit mask for CMU_DMA */
AnnaBridge 171:3a7713b1edbc 2816 #define _CMU_HFCORECLKEN0_DMA_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2817 #define CMU_HFCORECLKEN0_DMA_DEFAULT (_CMU_HFCORECLKEN0_DMA_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2818 #define CMU_HFCORECLKEN0_AES (0x1UL << 1) /**< Advanced Encryption Standard Accelerator Clock Enable */
AnnaBridge 171:3a7713b1edbc 2819 #define _CMU_HFCORECLKEN0_AES_SHIFT 1 /**< Shift value for CMU_AES */
AnnaBridge 171:3a7713b1edbc 2820 #define _CMU_HFCORECLKEN0_AES_MASK 0x2UL /**< Bit mask for CMU_AES */
AnnaBridge 171:3a7713b1edbc 2821 #define _CMU_HFCORECLKEN0_AES_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2822 #define CMU_HFCORECLKEN0_AES_DEFAULT (_CMU_HFCORECLKEN0_AES_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2823 #define CMU_HFCORECLKEN0_LE (0x1UL << 4) /**< Low Energy Peripheral Interface Clock Enable */
AnnaBridge 171:3a7713b1edbc 2824 #define _CMU_HFCORECLKEN0_LE_SHIFT 4 /**< Shift value for CMU_LE */
AnnaBridge 171:3a7713b1edbc 2825 #define _CMU_HFCORECLKEN0_LE_MASK 0x10UL /**< Bit mask for CMU_LE */
AnnaBridge 171:3a7713b1edbc 2826 #define _CMU_HFCORECLKEN0_LE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2827 #define CMU_HFCORECLKEN0_LE_DEFAULT (_CMU_HFCORECLKEN0_LE_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_HFCORECLKEN0 */
AnnaBridge 171:3a7713b1edbc 2828
AnnaBridge 171:3a7713b1edbc 2829 /* Bit fields for CMU HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2830 #define _CMU_HFPERCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2831 #define _CMU_HFPERCLKEN0_MASK 0x0003FFE7UL /**< Mask for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2832 #define CMU_HFPERCLKEN0_USART0 (0x1UL << 0) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2833 #define _CMU_HFPERCLKEN0_USART0_SHIFT 0 /**< Shift value for CMU_USART0 */
AnnaBridge 171:3a7713b1edbc 2834 #define _CMU_HFPERCLKEN0_USART0_MASK 0x1UL /**< Bit mask for CMU_USART0 */
AnnaBridge 171:3a7713b1edbc 2835 #define _CMU_HFPERCLKEN0_USART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2836 #define CMU_HFPERCLKEN0_USART0_DEFAULT (_CMU_HFPERCLKEN0_USART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2837 #define CMU_HFPERCLKEN0_USART1 (0x1UL << 1) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 1 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2838 #define _CMU_HFPERCLKEN0_USART1_SHIFT 1 /**< Shift value for CMU_USART1 */
AnnaBridge 171:3a7713b1edbc 2839 #define _CMU_HFPERCLKEN0_USART1_MASK 0x2UL /**< Bit mask for CMU_USART1 */
AnnaBridge 171:3a7713b1edbc 2840 #define _CMU_HFPERCLKEN0_USART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2841 #define CMU_HFPERCLKEN0_USART1_DEFAULT (_CMU_HFPERCLKEN0_USART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2842 #define CMU_HFPERCLKEN0_USART2 (0x1UL << 2) /**< Universal Synchronous/Asynchronous Receiver/Transmitter 2 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2843 #define _CMU_HFPERCLKEN0_USART2_SHIFT 2 /**< Shift value for CMU_USART2 */
AnnaBridge 171:3a7713b1edbc 2844 #define _CMU_HFPERCLKEN0_USART2_MASK 0x4UL /**< Bit mask for CMU_USART2 */
AnnaBridge 171:3a7713b1edbc 2845 #define _CMU_HFPERCLKEN0_USART2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2846 #define CMU_HFPERCLKEN0_USART2_DEFAULT (_CMU_HFPERCLKEN0_USART2_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2847 #define CMU_HFPERCLKEN0_TIMER0 (0x1UL << 5) /**< Timer 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2848 #define _CMU_HFPERCLKEN0_TIMER0_SHIFT 5 /**< Shift value for CMU_TIMER0 */
AnnaBridge 171:3a7713b1edbc 2849 #define _CMU_HFPERCLKEN0_TIMER0_MASK 0x20UL /**< Bit mask for CMU_TIMER0 */
AnnaBridge 171:3a7713b1edbc 2850 #define _CMU_HFPERCLKEN0_TIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2851 #define CMU_HFPERCLKEN0_TIMER0_DEFAULT (_CMU_HFPERCLKEN0_TIMER0_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2852 #define CMU_HFPERCLKEN0_TIMER1 (0x1UL << 6) /**< Timer 1 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2853 #define _CMU_HFPERCLKEN0_TIMER1_SHIFT 6 /**< Shift value for CMU_TIMER1 */
AnnaBridge 171:3a7713b1edbc 2854 #define _CMU_HFPERCLKEN0_TIMER1_MASK 0x40UL /**< Bit mask for CMU_TIMER1 */
AnnaBridge 171:3a7713b1edbc 2855 #define _CMU_HFPERCLKEN0_TIMER1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2856 #define CMU_HFPERCLKEN0_TIMER1_DEFAULT (_CMU_HFPERCLKEN0_TIMER1_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2857 #define CMU_HFPERCLKEN0_TIMER2 (0x1UL << 7) /**< Timer 2 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2858 #define _CMU_HFPERCLKEN0_TIMER2_SHIFT 7 /**< Shift value for CMU_TIMER2 */
AnnaBridge 171:3a7713b1edbc 2859 #define _CMU_HFPERCLKEN0_TIMER2_MASK 0x80UL /**< Bit mask for CMU_TIMER2 */
AnnaBridge 171:3a7713b1edbc 2860 #define _CMU_HFPERCLKEN0_TIMER2_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2861 #define CMU_HFPERCLKEN0_TIMER2_DEFAULT (_CMU_HFPERCLKEN0_TIMER2_DEFAULT << 7) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2862 #define CMU_HFPERCLKEN0_TIMER3 (0x1UL << 8) /**< Timer 3 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2863 #define _CMU_HFPERCLKEN0_TIMER3_SHIFT 8 /**< Shift value for CMU_TIMER3 */
AnnaBridge 171:3a7713b1edbc 2864 #define _CMU_HFPERCLKEN0_TIMER3_MASK 0x100UL /**< Bit mask for CMU_TIMER3 */
AnnaBridge 171:3a7713b1edbc 2865 #define _CMU_HFPERCLKEN0_TIMER3_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2866 #define CMU_HFPERCLKEN0_TIMER3_DEFAULT (_CMU_HFPERCLKEN0_TIMER3_DEFAULT << 8) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2867 #define CMU_HFPERCLKEN0_ACMP0 (0x1UL << 9) /**< Analog Comparator 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2868 #define _CMU_HFPERCLKEN0_ACMP0_SHIFT 9 /**< Shift value for CMU_ACMP0 */
AnnaBridge 171:3a7713b1edbc 2869 #define _CMU_HFPERCLKEN0_ACMP0_MASK 0x200UL /**< Bit mask for CMU_ACMP0 */
AnnaBridge 171:3a7713b1edbc 2870 #define _CMU_HFPERCLKEN0_ACMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2871 #define CMU_HFPERCLKEN0_ACMP0_DEFAULT (_CMU_HFPERCLKEN0_ACMP0_DEFAULT << 9) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2872 #define CMU_HFPERCLKEN0_ACMP1 (0x1UL << 10) /**< Analog Comparator 1 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2873 #define _CMU_HFPERCLKEN0_ACMP1_SHIFT 10 /**< Shift value for CMU_ACMP1 */
AnnaBridge 171:3a7713b1edbc 2874 #define _CMU_HFPERCLKEN0_ACMP1_MASK 0x400UL /**< Bit mask for CMU_ACMP1 */
AnnaBridge 171:3a7713b1edbc 2875 #define _CMU_HFPERCLKEN0_ACMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2876 #define CMU_HFPERCLKEN0_ACMP1_DEFAULT (_CMU_HFPERCLKEN0_ACMP1_DEFAULT << 10) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2877 #define CMU_HFPERCLKEN0_I2C0 (0x1UL << 11) /**< I2C 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2878 #define _CMU_HFPERCLKEN0_I2C0_SHIFT 11 /**< Shift value for CMU_I2C0 */
AnnaBridge 171:3a7713b1edbc 2879 #define _CMU_HFPERCLKEN0_I2C0_MASK 0x800UL /**< Bit mask for CMU_I2C0 */
AnnaBridge 171:3a7713b1edbc 2880 #define _CMU_HFPERCLKEN0_I2C0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2881 #define CMU_HFPERCLKEN0_I2C0_DEFAULT (_CMU_HFPERCLKEN0_I2C0_DEFAULT << 11) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2882 #define CMU_HFPERCLKEN0_I2C1 (0x1UL << 12) /**< I2C 1 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2883 #define _CMU_HFPERCLKEN0_I2C1_SHIFT 12 /**< Shift value for CMU_I2C1 */
AnnaBridge 171:3a7713b1edbc 2884 #define _CMU_HFPERCLKEN0_I2C1_MASK 0x1000UL /**< Bit mask for CMU_I2C1 */
AnnaBridge 171:3a7713b1edbc 2885 #define _CMU_HFPERCLKEN0_I2C1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2886 #define CMU_HFPERCLKEN0_I2C1_DEFAULT (_CMU_HFPERCLKEN0_I2C1_DEFAULT << 12) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2887 #define CMU_HFPERCLKEN0_GPIO (0x1UL << 13) /**< General purpose Input/Output Clock Enable */
AnnaBridge 171:3a7713b1edbc 2888 #define _CMU_HFPERCLKEN0_GPIO_SHIFT 13 /**< Shift value for CMU_GPIO */
AnnaBridge 171:3a7713b1edbc 2889 #define _CMU_HFPERCLKEN0_GPIO_MASK 0x2000UL /**< Bit mask for CMU_GPIO */
AnnaBridge 171:3a7713b1edbc 2890 #define _CMU_HFPERCLKEN0_GPIO_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2891 #define CMU_HFPERCLKEN0_GPIO_DEFAULT (_CMU_HFPERCLKEN0_GPIO_DEFAULT << 13) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2892 #define CMU_HFPERCLKEN0_VCMP (0x1UL << 14) /**< Voltage Comparator Clock Enable */
AnnaBridge 171:3a7713b1edbc 2893 #define _CMU_HFPERCLKEN0_VCMP_SHIFT 14 /**< Shift value for CMU_VCMP */
AnnaBridge 171:3a7713b1edbc 2894 #define _CMU_HFPERCLKEN0_VCMP_MASK 0x4000UL /**< Bit mask for CMU_VCMP */
AnnaBridge 171:3a7713b1edbc 2895 #define _CMU_HFPERCLKEN0_VCMP_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2896 #define CMU_HFPERCLKEN0_VCMP_DEFAULT (_CMU_HFPERCLKEN0_VCMP_DEFAULT << 14) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2897 #define CMU_HFPERCLKEN0_PRS (0x1UL << 15) /**< Peripheral Reflex System Clock Enable */
AnnaBridge 171:3a7713b1edbc 2898 #define _CMU_HFPERCLKEN0_PRS_SHIFT 15 /**< Shift value for CMU_PRS */
AnnaBridge 171:3a7713b1edbc 2899 #define _CMU_HFPERCLKEN0_PRS_MASK 0x8000UL /**< Bit mask for CMU_PRS */
AnnaBridge 171:3a7713b1edbc 2900 #define _CMU_HFPERCLKEN0_PRS_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2901 #define CMU_HFPERCLKEN0_PRS_DEFAULT (_CMU_HFPERCLKEN0_PRS_DEFAULT << 15) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2902 #define CMU_HFPERCLKEN0_ADC0 (0x1UL << 16) /**< Analog to Digital Converter 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2903 #define _CMU_HFPERCLKEN0_ADC0_SHIFT 16 /**< Shift value for CMU_ADC0 */
AnnaBridge 171:3a7713b1edbc 2904 #define _CMU_HFPERCLKEN0_ADC0_MASK 0x10000UL /**< Bit mask for CMU_ADC0 */
AnnaBridge 171:3a7713b1edbc 2905 #define _CMU_HFPERCLKEN0_ADC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2906 #define CMU_HFPERCLKEN0_ADC0_DEFAULT (_CMU_HFPERCLKEN0_ADC0_DEFAULT << 16) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2907 #define CMU_HFPERCLKEN0_DAC0 (0x1UL << 17) /**< Digital to Analog Converter 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2908 #define _CMU_HFPERCLKEN0_DAC0_SHIFT 17 /**< Shift value for CMU_DAC0 */
AnnaBridge 171:3a7713b1edbc 2909 #define _CMU_HFPERCLKEN0_DAC0_MASK 0x20000UL /**< Bit mask for CMU_DAC0 */
AnnaBridge 171:3a7713b1edbc 2910 #define _CMU_HFPERCLKEN0_DAC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2911 #define CMU_HFPERCLKEN0_DAC0_DEFAULT (_CMU_HFPERCLKEN0_DAC0_DEFAULT << 17) /**< Shifted mode DEFAULT for CMU_HFPERCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2912
AnnaBridge 171:3a7713b1edbc 2913 /* Bit fields for CMU SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2914 #define _CMU_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2915 #define _CMU_SYNCBUSY_MASK 0x00000055UL /**< Mask for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2916 #define CMU_SYNCBUSY_LFACLKEN0 (0x1UL << 0) /**< Low Frequency A Clock Enable 0 Busy */
AnnaBridge 171:3a7713b1edbc 2917 #define _CMU_SYNCBUSY_LFACLKEN0_SHIFT 0 /**< Shift value for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2918 #define _CMU_SYNCBUSY_LFACLKEN0_MASK 0x1UL /**< Bit mask for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2919 #define _CMU_SYNCBUSY_LFACLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2920 #define CMU_SYNCBUSY_LFACLKEN0_DEFAULT (_CMU_SYNCBUSY_LFACLKEN0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2921 #define CMU_SYNCBUSY_LFAPRESC0 (0x1UL << 2) /**< Low Frequency A Prescaler 0 Busy */
AnnaBridge 171:3a7713b1edbc 2922 #define _CMU_SYNCBUSY_LFAPRESC0_SHIFT 2 /**< Shift value for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2923 #define _CMU_SYNCBUSY_LFAPRESC0_MASK 0x4UL /**< Bit mask for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2924 #define _CMU_SYNCBUSY_LFAPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2925 #define CMU_SYNCBUSY_LFAPRESC0_DEFAULT (_CMU_SYNCBUSY_LFAPRESC0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2926 #define CMU_SYNCBUSY_LFBCLKEN0 (0x1UL << 4) /**< Low Frequency B Clock Enable 0 Busy */
AnnaBridge 171:3a7713b1edbc 2927 #define _CMU_SYNCBUSY_LFBCLKEN0_SHIFT 4 /**< Shift value for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2928 #define _CMU_SYNCBUSY_LFBCLKEN0_MASK 0x10UL /**< Bit mask for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2929 #define _CMU_SYNCBUSY_LFBCLKEN0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2930 #define CMU_SYNCBUSY_LFBCLKEN0_DEFAULT (_CMU_SYNCBUSY_LFBCLKEN0_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2931 #define CMU_SYNCBUSY_LFBPRESC0 (0x1UL << 6) /**< Low Frequency B Prescaler 0 Busy */
AnnaBridge 171:3a7713b1edbc 2932 #define _CMU_SYNCBUSY_LFBPRESC0_SHIFT 6 /**< Shift value for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 2933 #define _CMU_SYNCBUSY_LFBPRESC0_MASK 0x40UL /**< Bit mask for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 2934 #define _CMU_SYNCBUSY_LFBPRESC0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2935 #define CMU_SYNCBUSY_LFBPRESC0_DEFAULT (_CMU_SYNCBUSY_LFBPRESC0_DEFAULT << 6) /**< Shifted mode DEFAULT for CMU_SYNCBUSY */
AnnaBridge 171:3a7713b1edbc 2936
AnnaBridge 171:3a7713b1edbc 2937 /* Bit fields for CMU FREEZE */
AnnaBridge 171:3a7713b1edbc 2938 #define _CMU_FREEZE_RESETVALUE 0x00000000UL /**< Default value for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2939 #define _CMU_FREEZE_MASK 0x00000001UL /**< Mask for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2940 #define CMU_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
AnnaBridge 171:3a7713b1edbc 2941 #define _CMU_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for CMU_REGFREEZE */
AnnaBridge 171:3a7713b1edbc 2942 #define _CMU_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for CMU_REGFREEZE */
AnnaBridge 171:3a7713b1edbc 2943 #define _CMU_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2944 #define _CMU_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2945 #define _CMU_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2946 #define CMU_FREEZE_REGFREEZE_DEFAULT (_CMU_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2947 #define CMU_FREEZE_REGFREEZE_UPDATE (_CMU_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2948 #define CMU_FREEZE_REGFREEZE_FREEZE (_CMU_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for CMU_FREEZE */
AnnaBridge 171:3a7713b1edbc 2949
AnnaBridge 171:3a7713b1edbc 2950 /* Bit fields for CMU LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2951 #define _CMU_LFACLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2952 #define _CMU_LFACLKEN0_MASK 0x0000000FUL /**< Mask for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2953 #define CMU_LFACLKEN0_LESENSE (0x1UL << 0) /**< Low Energy Sensor Interface Clock Enable */
AnnaBridge 171:3a7713b1edbc 2954 #define _CMU_LFACLKEN0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
AnnaBridge 171:3a7713b1edbc 2955 #define _CMU_LFACLKEN0_LESENSE_MASK 0x1UL /**< Bit mask for CMU_LESENSE */
AnnaBridge 171:3a7713b1edbc 2956 #define _CMU_LFACLKEN0_LESENSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2957 #define CMU_LFACLKEN0_LESENSE_DEFAULT (_CMU_LFACLKEN0_LESENSE_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2958 #define CMU_LFACLKEN0_RTC (0x1UL << 1) /**< Real-Time Counter Clock Enable */
AnnaBridge 171:3a7713b1edbc 2959 #define _CMU_LFACLKEN0_RTC_SHIFT 1 /**< Shift value for CMU_RTC */
AnnaBridge 171:3a7713b1edbc 2960 #define _CMU_LFACLKEN0_RTC_MASK 0x2UL /**< Bit mask for CMU_RTC */
AnnaBridge 171:3a7713b1edbc 2961 #define _CMU_LFACLKEN0_RTC_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2962 #define CMU_LFACLKEN0_RTC_DEFAULT (_CMU_LFACLKEN0_RTC_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2963 #define CMU_LFACLKEN0_LETIMER0 (0x1UL << 2) /**< Low Energy Timer 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2964 #define _CMU_LFACLKEN0_LETIMER0_SHIFT 2 /**< Shift value for CMU_LETIMER0 */
AnnaBridge 171:3a7713b1edbc 2965 #define _CMU_LFACLKEN0_LETIMER0_MASK 0x4UL /**< Bit mask for CMU_LETIMER0 */
AnnaBridge 171:3a7713b1edbc 2966 #define _CMU_LFACLKEN0_LETIMER0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2967 #define CMU_LFACLKEN0_LETIMER0_DEFAULT (_CMU_LFACLKEN0_LETIMER0_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2968 #define CMU_LFACLKEN0_LCD (0x1UL << 3) /**< Liquid Crystal Display Controller Clock Enable */
AnnaBridge 171:3a7713b1edbc 2969 #define _CMU_LFACLKEN0_LCD_SHIFT 3 /**< Shift value for CMU_LCD */
AnnaBridge 171:3a7713b1edbc 2970 #define _CMU_LFACLKEN0_LCD_MASK 0x8UL /**< Bit mask for CMU_LCD */
AnnaBridge 171:3a7713b1edbc 2971 #define _CMU_LFACLKEN0_LCD_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2972 #define CMU_LFACLKEN0_LCD_DEFAULT (_CMU_LFACLKEN0_LCD_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LFACLKEN0 */
AnnaBridge 171:3a7713b1edbc 2973
AnnaBridge 171:3a7713b1edbc 2974 /* Bit fields for CMU LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2975 #define _CMU_LFBCLKEN0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2976 #define _CMU_LFBCLKEN0_MASK 0x00000003UL /**< Mask for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2977 #define CMU_LFBCLKEN0_LEUART0 (0x1UL << 0) /**< Low Energy UART 0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2978 #define _CMU_LFBCLKEN0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
AnnaBridge 171:3a7713b1edbc 2979 #define _CMU_LFBCLKEN0_LEUART0_MASK 0x1UL /**< Bit mask for CMU_LEUART0 */
AnnaBridge 171:3a7713b1edbc 2980 #define _CMU_LFBCLKEN0_LEUART0_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2981 #define CMU_LFBCLKEN0_LEUART0_DEFAULT (_CMU_LFBCLKEN0_LEUART0_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2982 #define CMU_LFBCLKEN0_LEUART1 (0x1UL << 1) /**< Low Energy UART 1 Clock Enable */
AnnaBridge 171:3a7713b1edbc 2983 #define _CMU_LFBCLKEN0_LEUART1_SHIFT 1 /**< Shift value for CMU_LEUART1 */
AnnaBridge 171:3a7713b1edbc 2984 #define _CMU_LFBCLKEN0_LEUART1_MASK 0x2UL /**< Bit mask for CMU_LEUART1 */
AnnaBridge 171:3a7713b1edbc 2985 #define _CMU_LFBCLKEN0_LEUART1_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2986 #define CMU_LFBCLKEN0_LEUART1_DEFAULT (_CMU_LFBCLKEN0_LEUART1_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_LFBCLKEN0 */
AnnaBridge 171:3a7713b1edbc 2987
AnnaBridge 171:3a7713b1edbc 2988 /* Bit fields for CMU LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2989 #define _CMU_LFAPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2990 #define _CMU_LFAPRESC0_MASK 0x00003FF3UL /**< Mask for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2991 #define _CMU_LFAPRESC0_LESENSE_SHIFT 0 /**< Shift value for CMU_LESENSE */
AnnaBridge 171:3a7713b1edbc 2992 #define _CMU_LFAPRESC0_LESENSE_MASK 0x3UL /**< Bit mask for CMU_LESENSE */
AnnaBridge 171:3a7713b1edbc 2993 #define _CMU_LFAPRESC0_LESENSE_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2994 #define _CMU_LFAPRESC0_LESENSE_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2995 #define _CMU_LFAPRESC0_LESENSE_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2996 #define _CMU_LFAPRESC0_LESENSE_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2997 #define CMU_LFAPRESC0_LESENSE_DIV1 (_CMU_LFAPRESC0_LESENSE_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2998 #define CMU_LFAPRESC0_LESENSE_DIV2 (_CMU_LFAPRESC0_LESENSE_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 2999 #define CMU_LFAPRESC0_LESENSE_DIV4 (_CMU_LFAPRESC0_LESENSE_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3000 #define CMU_LFAPRESC0_LESENSE_DIV8 (_CMU_LFAPRESC0_LESENSE_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3001 #define _CMU_LFAPRESC0_RTC_SHIFT 4 /**< Shift value for CMU_RTC */
AnnaBridge 171:3a7713b1edbc 3002 #define _CMU_LFAPRESC0_RTC_MASK 0xF0UL /**< Bit mask for CMU_RTC */
AnnaBridge 171:3a7713b1edbc 3003 #define _CMU_LFAPRESC0_RTC_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3004 #define _CMU_LFAPRESC0_RTC_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3005 #define _CMU_LFAPRESC0_RTC_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3006 #define _CMU_LFAPRESC0_RTC_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3007 #define _CMU_LFAPRESC0_RTC_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3008 #define _CMU_LFAPRESC0_RTC_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3009 #define _CMU_LFAPRESC0_RTC_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3010 #define _CMU_LFAPRESC0_RTC_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3011 #define _CMU_LFAPRESC0_RTC_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3012 #define _CMU_LFAPRESC0_RTC_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3013 #define _CMU_LFAPRESC0_RTC_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3014 #define _CMU_LFAPRESC0_RTC_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3015 #define _CMU_LFAPRESC0_RTC_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3016 #define _CMU_LFAPRESC0_RTC_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3017 #define _CMU_LFAPRESC0_RTC_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3018 #define _CMU_LFAPRESC0_RTC_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3019 #define CMU_LFAPRESC0_RTC_DIV1 (_CMU_LFAPRESC0_RTC_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3020 #define CMU_LFAPRESC0_RTC_DIV2 (_CMU_LFAPRESC0_RTC_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3021 #define CMU_LFAPRESC0_RTC_DIV4 (_CMU_LFAPRESC0_RTC_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3022 #define CMU_LFAPRESC0_RTC_DIV8 (_CMU_LFAPRESC0_RTC_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3023 #define CMU_LFAPRESC0_RTC_DIV16 (_CMU_LFAPRESC0_RTC_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3024 #define CMU_LFAPRESC0_RTC_DIV32 (_CMU_LFAPRESC0_RTC_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3025 #define CMU_LFAPRESC0_RTC_DIV64 (_CMU_LFAPRESC0_RTC_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3026 #define CMU_LFAPRESC0_RTC_DIV128 (_CMU_LFAPRESC0_RTC_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3027 #define CMU_LFAPRESC0_RTC_DIV256 (_CMU_LFAPRESC0_RTC_DIV256 << 4) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3028 #define CMU_LFAPRESC0_RTC_DIV512 (_CMU_LFAPRESC0_RTC_DIV512 << 4) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3029 #define CMU_LFAPRESC0_RTC_DIV1024 (_CMU_LFAPRESC0_RTC_DIV1024 << 4) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3030 #define CMU_LFAPRESC0_RTC_DIV2048 (_CMU_LFAPRESC0_RTC_DIV2048 << 4) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3031 #define CMU_LFAPRESC0_RTC_DIV4096 (_CMU_LFAPRESC0_RTC_DIV4096 << 4) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3032 #define CMU_LFAPRESC0_RTC_DIV8192 (_CMU_LFAPRESC0_RTC_DIV8192 << 4) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3033 #define CMU_LFAPRESC0_RTC_DIV16384 (_CMU_LFAPRESC0_RTC_DIV16384 << 4) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3034 #define CMU_LFAPRESC0_RTC_DIV32768 (_CMU_LFAPRESC0_RTC_DIV32768 << 4) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3035 #define _CMU_LFAPRESC0_LETIMER0_SHIFT 8 /**< Shift value for CMU_LETIMER0 */
AnnaBridge 171:3a7713b1edbc 3036 #define _CMU_LFAPRESC0_LETIMER0_MASK 0xF00UL /**< Bit mask for CMU_LETIMER0 */
AnnaBridge 171:3a7713b1edbc 3037 #define _CMU_LFAPRESC0_LETIMER0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3038 #define _CMU_LFAPRESC0_LETIMER0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3039 #define _CMU_LFAPRESC0_LETIMER0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3040 #define _CMU_LFAPRESC0_LETIMER0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3041 #define _CMU_LFAPRESC0_LETIMER0_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3042 #define _CMU_LFAPRESC0_LETIMER0_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3043 #define _CMU_LFAPRESC0_LETIMER0_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3044 #define _CMU_LFAPRESC0_LETIMER0_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3045 #define _CMU_LFAPRESC0_LETIMER0_DIV256 0x00000008UL /**< Mode DIV256 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3046 #define _CMU_LFAPRESC0_LETIMER0_DIV512 0x00000009UL /**< Mode DIV512 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3047 #define _CMU_LFAPRESC0_LETIMER0_DIV1024 0x0000000AUL /**< Mode DIV1024 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3048 #define _CMU_LFAPRESC0_LETIMER0_DIV2048 0x0000000BUL /**< Mode DIV2048 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3049 #define _CMU_LFAPRESC0_LETIMER0_DIV4096 0x0000000CUL /**< Mode DIV4096 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3050 #define _CMU_LFAPRESC0_LETIMER0_DIV8192 0x0000000DUL /**< Mode DIV8192 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3051 #define _CMU_LFAPRESC0_LETIMER0_DIV16384 0x0000000EUL /**< Mode DIV16384 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3052 #define _CMU_LFAPRESC0_LETIMER0_DIV32768 0x0000000FUL /**< Mode DIV32768 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3053 #define CMU_LFAPRESC0_LETIMER0_DIV1 (_CMU_LFAPRESC0_LETIMER0_DIV1 << 8) /**< Shifted mode DIV1 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3054 #define CMU_LFAPRESC0_LETIMER0_DIV2 (_CMU_LFAPRESC0_LETIMER0_DIV2 << 8) /**< Shifted mode DIV2 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3055 #define CMU_LFAPRESC0_LETIMER0_DIV4 (_CMU_LFAPRESC0_LETIMER0_DIV4 << 8) /**< Shifted mode DIV4 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3056 #define CMU_LFAPRESC0_LETIMER0_DIV8 (_CMU_LFAPRESC0_LETIMER0_DIV8 << 8) /**< Shifted mode DIV8 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3057 #define CMU_LFAPRESC0_LETIMER0_DIV16 (_CMU_LFAPRESC0_LETIMER0_DIV16 << 8) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3058 #define CMU_LFAPRESC0_LETIMER0_DIV32 (_CMU_LFAPRESC0_LETIMER0_DIV32 << 8) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3059 #define CMU_LFAPRESC0_LETIMER0_DIV64 (_CMU_LFAPRESC0_LETIMER0_DIV64 << 8) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3060 #define CMU_LFAPRESC0_LETIMER0_DIV128 (_CMU_LFAPRESC0_LETIMER0_DIV128 << 8) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3061 #define CMU_LFAPRESC0_LETIMER0_DIV256 (_CMU_LFAPRESC0_LETIMER0_DIV256 << 8) /**< Shifted mode DIV256 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3062 #define CMU_LFAPRESC0_LETIMER0_DIV512 (_CMU_LFAPRESC0_LETIMER0_DIV512 << 8) /**< Shifted mode DIV512 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3063 #define CMU_LFAPRESC0_LETIMER0_DIV1024 (_CMU_LFAPRESC0_LETIMER0_DIV1024 << 8) /**< Shifted mode DIV1024 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3064 #define CMU_LFAPRESC0_LETIMER0_DIV2048 (_CMU_LFAPRESC0_LETIMER0_DIV2048 << 8) /**< Shifted mode DIV2048 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3065 #define CMU_LFAPRESC0_LETIMER0_DIV4096 (_CMU_LFAPRESC0_LETIMER0_DIV4096 << 8) /**< Shifted mode DIV4096 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3066 #define CMU_LFAPRESC0_LETIMER0_DIV8192 (_CMU_LFAPRESC0_LETIMER0_DIV8192 << 8) /**< Shifted mode DIV8192 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3067 #define CMU_LFAPRESC0_LETIMER0_DIV16384 (_CMU_LFAPRESC0_LETIMER0_DIV16384 << 8) /**< Shifted mode DIV16384 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3068 #define CMU_LFAPRESC0_LETIMER0_DIV32768 (_CMU_LFAPRESC0_LETIMER0_DIV32768 << 8) /**< Shifted mode DIV32768 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3069 #define _CMU_LFAPRESC0_LCD_SHIFT 12 /**< Shift value for CMU_LCD */
AnnaBridge 171:3a7713b1edbc 3070 #define _CMU_LFAPRESC0_LCD_MASK 0x3000UL /**< Bit mask for CMU_LCD */
AnnaBridge 171:3a7713b1edbc 3071 #define _CMU_LFAPRESC0_LCD_DIV16 0x00000000UL /**< Mode DIV16 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3072 #define _CMU_LFAPRESC0_LCD_DIV32 0x00000001UL /**< Mode DIV32 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3073 #define _CMU_LFAPRESC0_LCD_DIV64 0x00000002UL /**< Mode DIV64 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3074 #define _CMU_LFAPRESC0_LCD_DIV128 0x00000003UL /**< Mode DIV128 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3075 #define CMU_LFAPRESC0_LCD_DIV16 (_CMU_LFAPRESC0_LCD_DIV16 << 12) /**< Shifted mode DIV16 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3076 #define CMU_LFAPRESC0_LCD_DIV32 (_CMU_LFAPRESC0_LCD_DIV32 << 12) /**< Shifted mode DIV32 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3077 #define CMU_LFAPRESC0_LCD_DIV64 (_CMU_LFAPRESC0_LCD_DIV64 << 12) /**< Shifted mode DIV64 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3078 #define CMU_LFAPRESC0_LCD_DIV128 (_CMU_LFAPRESC0_LCD_DIV128 << 12) /**< Shifted mode DIV128 for CMU_LFAPRESC0 */
AnnaBridge 171:3a7713b1edbc 3079
AnnaBridge 171:3a7713b1edbc 3080 /* Bit fields for CMU LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3081 #define _CMU_LFBPRESC0_RESETVALUE 0x00000000UL /**< Default value for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3082 #define _CMU_LFBPRESC0_MASK 0x00000033UL /**< Mask for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3083 #define _CMU_LFBPRESC0_LEUART0_SHIFT 0 /**< Shift value for CMU_LEUART0 */
AnnaBridge 171:3a7713b1edbc 3084 #define _CMU_LFBPRESC0_LEUART0_MASK 0x3UL /**< Bit mask for CMU_LEUART0 */
AnnaBridge 171:3a7713b1edbc 3085 #define _CMU_LFBPRESC0_LEUART0_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3086 #define _CMU_LFBPRESC0_LEUART0_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3087 #define _CMU_LFBPRESC0_LEUART0_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3088 #define _CMU_LFBPRESC0_LEUART0_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3089 #define CMU_LFBPRESC0_LEUART0_DIV1 (_CMU_LFBPRESC0_LEUART0_DIV1 << 0) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3090 #define CMU_LFBPRESC0_LEUART0_DIV2 (_CMU_LFBPRESC0_LEUART0_DIV2 << 0) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3091 #define CMU_LFBPRESC0_LEUART0_DIV4 (_CMU_LFBPRESC0_LEUART0_DIV4 << 0) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3092 #define CMU_LFBPRESC0_LEUART0_DIV8 (_CMU_LFBPRESC0_LEUART0_DIV8 << 0) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3093 #define _CMU_LFBPRESC0_LEUART1_SHIFT 4 /**< Shift value for CMU_LEUART1 */
AnnaBridge 171:3a7713b1edbc 3094 #define _CMU_LFBPRESC0_LEUART1_MASK 0x30UL /**< Bit mask for CMU_LEUART1 */
AnnaBridge 171:3a7713b1edbc 3095 #define _CMU_LFBPRESC0_LEUART1_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3096 #define _CMU_LFBPRESC0_LEUART1_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3097 #define _CMU_LFBPRESC0_LEUART1_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3098 #define _CMU_LFBPRESC0_LEUART1_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3099 #define CMU_LFBPRESC0_LEUART1_DIV1 (_CMU_LFBPRESC0_LEUART1_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3100 #define CMU_LFBPRESC0_LEUART1_DIV2 (_CMU_LFBPRESC0_LEUART1_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3101 #define CMU_LFBPRESC0_LEUART1_DIV4 (_CMU_LFBPRESC0_LEUART1_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3102 #define CMU_LFBPRESC0_LEUART1_DIV8 (_CMU_LFBPRESC0_LEUART1_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LFBPRESC0 */
AnnaBridge 171:3a7713b1edbc 3103
AnnaBridge 171:3a7713b1edbc 3104 /* Bit fields for CMU PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3105 #define _CMU_PCNTCTRL_RESETVALUE 0x00000000UL /**< Default value for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3106 #define _CMU_PCNTCTRL_MASK 0x0000003FUL /**< Mask for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3107 #define CMU_PCNTCTRL_PCNT0CLKEN (0x1UL << 0) /**< PCNT0 Clock Enable */
AnnaBridge 171:3a7713b1edbc 3108 #define _CMU_PCNTCTRL_PCNT0CLKEN_SHIFT 0 /**< Shift value for CMU_PCNT0CLKEN */
AnnaBridge 171:3a7713b1edbc 3109 #define _CMU_PCNTCTRL_PCNT0CLKEN_MASK 0x1UL /**< Bit mask for CMU_PCNT0CLKEN */
AnnaBridge 171:3a7713b1edbc 3110 #define _CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3111 #define CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3112 #define CMU_PCNTCTRL_PCNT0CLKSEL (0x1UL << 1) /**< PCNT0 Clock Select */
AnnaBridge 171:3a7713b1edbc 3113 #define _CMU_PCNTCTRL_PCNT0CLKSEL_SHIFT 1 /**< Shift value for CMU_PCNT0CLKSEL */
AnnaBridge 171:3a7713b1edbc 3114 #define _CMU_PCNTCTRL_PCNT0CLKSEL_MASK 0x2UL /**< Bit mask for CMU_PCNT0CLKSEL */
AnnaBridge 171:3a7713b1edbc 3115 #define _CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3116 #define _CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3117 #define _CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 0x00000001UL /**< Mode PCNT0S0 for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3118 #define CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT0CLKSEL_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3119 #define CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT0CLKSEL_LFACLK << 1) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3120 #define CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 (_CMU_PCNTCTRL_PCNT0CLKSEL_PCNT0S0 << 1) /**< Shifted mode PCNT0S0 for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3121 #define CMU_PCNTCTRL_PCNT1CLKEN (0x1UL << 2) /**< PCNT1 Clock Enable */
AnnaBridge 171:3a7713b1edbc 3122 #define _CMU_PCNTCTRL_PCNT1CLKEN_SHIFT 2 /**< Shift value for CMU_PCNT1CLKEN */
AnnaBridge 171:3a7713b1edbc 3123 #define _CMU_PCNTCTRL_PCNT1CLKEN_MASK 0x4UL /**< Bit mask for CMU_PCNT1CLKEN */
AnnaBridge 171:3a7713b1edbc 3124 #define _CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3125 #define CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKEN_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3126 #define CMU_PCNTCTRL_PCNT1CLKSEL (0x1UL << 3) /**< PCNT1 Clock Select */
AnnaBridge 171:3a7713b1edbc 3127 #define _CMU_PCNTCTRL_PCNT1CLKSEL_SHIFT 3 /**< Shift value for CMU_PCNT1CLKSEL */
AnnaBridge 171:3a7713b1edbc 3128 #define _CMU_PCNTCTRL_PCNT1CLKSEL_MASK 0x8UL /**< Bit mask for CMU_PCNT1CLKSEL */
AnnaBridge 171:3a7713b1edbc 3129 #define _CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3130 #define _CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3131 #define _CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 0x00000001UL /**< Mode PCNT1S0 for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3132 #define CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT1CLKSEL_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3133 #define CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT1CLKSEL_LFACLK << 3) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3134 #define CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 (_CMU_PCNTCTRL_PCNT1CLKSEL_PCNT1S0 << 3) /**< Shifted mode PCNT1S0 for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3135 #define CMU_PCNTCTRL_PCNT2CLKEN (0x1UL << 4) /**< PCNT2 Clock Enable */
AnnaBridge 171:3a7713b1edbc 3136 #define _CMU_PCNTCTRL_PCNT2CLKEN_SHIFT 4 /**< Shift value for CMU_PCNT2CLKEN */
AnnaBridge 171:3a7713b1edbc 3137 #define _CMU_PCNTCTRL_PCNT2CLKEN_MASK 0x10UL /**< Bit mask for CMU_PCNT2CLKEN */
AnnaBridge 171:3a7713b1edbc 3138 #define _CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3139 #define CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKEN_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3140 #define CMU_PCNTCTRL_PCNT2CLKSEL (0x1UL << 5) /**< PCNT2 Clock Select */
AnnaBridge 171:3a7713b1edbc 3141 #define _CMU_PCNTCTRL_PCNT2CLKSEL_SHIFT 5 /**< Shift value for CMU_PCNT2CLKSEL */
AnnaBridge 171:3a7713b1edbc 3142 #define _CMU_PCNTCTRL_PCNT2CLKSEL_MASK 0x20UL /**< Bit mask for CMU_PCNT2CLKSEL */
AnnaBridge 171:3a7713b1edbc 3143 #define _CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3144 #define _CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK 0x00000000UL /**< Mode LFACLK for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3145 #define _CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 0x00000001UL /**< Mode PCNT2S0 for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3146 #define CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT (_CMU_PCNTCTRL_PCNT2CLKSEL_DEFAULT << 5) /**< Shifted mode DEFAULT for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3147 #define CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK (_CMU_PCNTCTRL_PCNT2CLKSEL_LFACLK << 5) /**< Shifted mode LFACLK for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3148 #define CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 (_CMU_PCNTCTRL_PCNT2CLKSEL_PCNT2S0 << 5) /**< Shifted mode PCNT2S0 for CMU_PCNTCTRL */
AnnaBridge 171:3a7713b1edbc 3149
AnnaBridge 171:3a7713b1edbc 3150 /* Bit fields for CMU LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3151 #define _CMU_LCDCTRL_RESETVALUE 0x00000020UL /**< Default value for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3152 #define _CMU_LCDCTRL_MASK 0x0000007FUL /**< Mask for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3153 #define _CMU_LCDCTRL_FDIV_SHIFT 0 /**< Shift value for CMU_FDIV */
AnnaBridge 171:3a7713b1edbc 3154 #define _CMU_LCDCTRL_FDIV_MASK 0x7UL /**< Bit mask for CMU_FDIV */
AnnaBridge 171:3a7713b1edbc 3155 #define _CMU_LCDCTRL_FDIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3156 #define CMU_LCDCTRL_FDIV_DEFAULT (_CMU_LCDCTRL_FDIV_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3157 #define CMU_LCDCTRL_VBOOSTEN (0x1UL << 3) /**< Voltage Boost Enable */
AnnaBridge 171:3a7713b1edbc 3158 #define _CMU_LCDCTRL_VBOOSTEN_SHIFT 3 /**< Shift value for CMU_VBOOSTEN */
AnnaBridge 171:3a7713b1edbc 3159 #define _CMU_LCDCTRL_VBOOSTEN_MASK 0x8UL /**< Bit mask for CMU_VBOOSTEN */
AnnaBridge 171:3a7713b1edbc 3160 #define _CMU_LCDCTRL_VBOOSTEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3161 #define CMU_LCDCTRL_VBOOSTEN_DEFAULT (_CMU_LCDCTRL_VBOOSTEN_DEFAULT << 3) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3162 #define _CMU_LCDCTRL_VBFDIV_SHIFT 4 /**< Shift value for CMU_VBFDIV */
AnnaBridge 171:3a7713b1edbc 3163 #define _CMU_LCDCTRL_VBFDIV_MASK 0x70UL /**< Bit mask for CMU_VBFDIV */
AnnaBridge 171:3a7713b1edbc 3164 #define _CMU_LCDCTRL_VBFDIV_DIV1 0x00000000UL /**< Mode DIV1 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3165 #define _CMU_LCDCTRL_VBFDIV_DIV2 0x00000001UL /**< Mode DIV2 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3166 #define _CMU_LCDCTRL_VBFDIV_DEFAULT 0x00000002UL /**< Mode DEFAULT for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3167 #define _CMU_LCDCTRL_VBFDIV_DIV4 0x00000002UL /**< Mode DIV4 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3168 #define _CMU_LCDCTRL_VBFDIV_DIV8 0x00000003UL /**< Mode DIV8 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3169 #define _CMU_LCDCTRL_VBFDIV_DIV16 0x00000004UL /**< Mode DIV16 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3170 #define _CMU_LCDCTRL_VBFDIV_DIV32 0x00000005UL /**< Mode DIV32 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3171 #define _CMU_LCDCTRL_VBFDIV_DIV64 0x00000006UL /**< Mode DIV64 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3172 #define _CMU_LCDCTRL_VBFDIV_DIV128 0x00000007UL /**< Mode DIV128 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3173 #define CMU_LCDCTRL_VBFDIV_DIV1 (_CMU_LCDCTRL_VBFDIV_DIV1 << 4) /**< Shifted mode DIV1 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3174 #define CMU_LCDCTRL_VBFDIV_DIV2 (_CMU_LCDCTRL_VBFDIV_DIV2 << 4) /**< Shifted mode DIV2 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3175 #define CMU_LCDCTRL_VBFDIV_DEFAULT (_CMU_LCDCTRL_VBFDIV_DEFAULT << 4) /**< Shifted mode DEFAULT for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3176 #define CMU_LCDCTRL_VBFDIV_DIV4 (_CMU_LCDCTRL_VBFDIV_DIV4 << 4) /**< Shifted mode DIV4 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3177 #define CMU_LCDCTRL_VBFDIV_DIV8 (_CMU_LCDCTRL_VBFDIV_DIV8 << 4) /**< Shifted mode DIV8 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3178 #define CMU_LCDCTRL_VBFDIV_DIV16 (_CMU_LCDCTRL_VBFDIV_DIV16 << 4) /**< Shifted mode DIV16 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3179 #define CMU_LCDCTRL_VBFDIV_DIV32 (_CMU_LCDCTRL_VBFDIV_DIV32 << 4) /**< Shifted mode DIV32 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3180 #define CMU_LCDCTRL_VBFDIV_DIV64 (_CMU_LCDCTRL_VBFDIV_DIV64 << 4) /**< Shifted mode DIV64 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3181 #define CMU_LCDCTRL_VBFDIV_DIV128 (_CMU_LCDCTRL_VBFDIV_DIV128 << 4) /**< Shifted mode DIV128 for CMU_LCDCTRL */
AnnaBridge 171:3a7713b1edbc 3182
AnnaBridge 171:3a7713b1edbc 3183 /* Bit fields for CMU ROUTE */
AnnaBridge 171:3a7713b1edbc 3184 #define _CMU_ROUTE_RESETVALUE 0x00000000UL /**< Default value for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3185 #define _CMU_ROUTE_MASK 0x0000001FUL /**< Mask for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3186 #define CMU_ROUTE_CLKOUT0PEN (0x1UL << 0) /**< CLKOUT0 Pin Enable */
AnnaBridge 171:3a7713b1edbc 3187 #define _CMU_ROUTE_CLKOUT0PEN_SHIFT 0 /**< Shift value for CMU_CLKOUT0PEN */
AnnaBridge 171:3a7713b1edbc 3188 #define _CMU_ROUTE_CLKOUT0PEN_MASK 0x1UL /**< Bit mask for CMU_CLKOUT0PEN */
AnnaBridge 171:3a7713b1edbc 3189 #define _CMU_ROUTE_CLKOUT0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3190 #define CMU_ROUTE_CLKOUT0PEN_DEFAULT (_CMU_ROUTE_CLKOUT0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3191 #define CMU_ROUTE_CLKOUT1PEN (0x1UL << 1) /**< CLKOUT1 Pin Enable */
AnnaBridge 171:3a7713b1edbc 3192 #define _CMU_ROUTE_CLKOUT1PEN_SHIFT 1 /**< Shift value for CMU_CLKOUT1PEN */
AnnaBridge 171:3a7713b1edbc 3193 #define _CMU_ROUTE_CLKOUT1PEN_MASK 0x2UL /**< Bit mask for CMU_CLKOUT1PEN */
AnnaBridge 171:3a7713b1edbc 3194 #define _CMU_ROUTE_CLKOUT1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3195 #define CMU_ROUTE_CLKOUT1PEN_DEFAULT (_CMU_ROUTE_CLKOUT1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3196 #define _CMU_ROUTE_LOCATION_SHIFT 2 /**< Shift value for CMU_LOCATION */
AnnaBridge 171:3a7713b1edbc 3197 #define _CMU_ROUTE_LOCATION_MASK 0x1CUL /**< Bit mask for CMU_LOCATION */
AnnaBridge 171:3a7713b1edbc 3198 #define _CMU_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3199 #define _CMU_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3200 #define _CMU_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3201 #define _CMU_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3202 #define CMU_ROUTE_LOCATION_LOC0 (_CMU_ROUTE_LOCATION_LOC0 << 2) /**< Shifted mode LOC0 for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3203 #define CMU_ROUTE_LOCATION_DEFAULT (_CMU_ROUTE_LOCATION_DEFAULT << 2) /**< Shifted mode DEFAULT for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3204 #define CMU_ROUTE_LOCATION_LOC1 (_CMU_ROUTE_LOCATION_LOC1 << 2) /**< Shifted mode LOC1 for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3205 #define CMU_ROUTE_LOCATION_LOC2 (_CMU_ROUTE_LOCATION_LOC2 << 2) /**< Shifted mode LOC2 for CMU_ROUTE */
AnnaBridge 171:3a7713b1edbc 3206
AnnaBridge 171:3a7713b1edbc 3207 /* Bit fields for CMU LOCK */
AnnaBridge 171:3a7713b1edbc 3208 #define _CMU_LOCK_RESETVALUE 0x00000000UL /**< Default value for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3209 #define _CMU_LOCK_MASK 0x0000FFFFUL /**< Mask for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3210 #define _CMU_LOCK_LOCKKEY_SHIFT 0 /**< Shift value for CMU_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 3211 #define _CMU_LOCK_LOCKKEY_MASK 0xFFFFUL /**< Bit mask for CMU_LOCKKEY */
AnnaBridge 171:3a7713b1edbc 3212 #define _CMU_LOCK_LOCKKEY_DEFAULT 0x00000000UL /**< Mode DEFAULT for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3213 #define _CMU_LOCK_LOCKKEY_LOCK 0x00000000UL /**< Mode LOCK for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3214 #define _CMU_LOCK_LOCKKEY_UNLOCKED 0x00000000UL /**< Mode UNLOCKED for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3215 #define _CMU_LOCK_LOCKKEY_LOCKED 0x00000001UL /**< Mode LOCKED for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3216 #define _CMU_LOCK_LOCKKEY_UNLOCK 0x0000580EUL /**< Mode UNLOCK for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3217 #define CMU_LOCK_LOCKKEY_DEFAULT (_CMU_LOCK_LOCKKEY_DEFAULT << 0) /**< Shifted mode DEFAULT for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3218 #define CMU_LOCK_LOCKKEY_LOCK (_CMU_LOCK_LOCKKEY_LOCK << 0) /**< Shifted mode LOCK for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3219 #define CMU_LOCK_LOCKKEY_UNLOCKED (_CMU_LOCK_LOCKKEY_UNLOCKED << 0) /**< Shifted mode UNLOCKED for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3220 #define CMU_LOCK_LOCKKEY_LOCKED (_CMU_LOCK_LOCKKEY_LOCKED << 0) /**< Shifted mode LOCKED for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3221 #define CMU_LOCK_LOCKKEY_UNLOCK (_CMU_LOCK_LOCKKEY_UNLOCK << 0) /**< Shifted mode UNLOCK for CMU_LOCK */
AnnaBridge 171:3a7713b1edbc 3222
AnnaBridge 171:3a7713b1edbc 3223 /** @} End of group EFM32GG842F1024_CMU */
AnnaBridge 171:3a7713b1edbc 3224
AnnaBridge 171:3a7713b1edbc 3225
AnnaBridge 171:3a7713b1edbc 3226
AnnaBridge 171:3a7713b1edbc 3227 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 3228 * @defgroup EFM32GG842F1024_PRS_BitFields EFM32GG842F1024_PRS Bit Fields
AnnaBridge 171:3a7713b1edbc 3229 * @{
AnnaBridge 171:3a7713b1edbc 3230 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3231
AnnaBridge 171:3a7713b1edbc 3232 /* Bit fields for PRS SWPULSE */
AnnaBridge 171:3a7713b1edbc 3233 #define _PRS_SWPULSE_RESETVALUE 0x00000000UL /**< Default value for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3234 #define _PRS_SWPULSE_MASK 0x00000FFFUL /**< Mask for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3235 #define PRS_SWPULSE_CH0PULSE (0x1UL << 0) /**< Channel 0 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3236 #define _PRS_SWPULSE_CH0PULSE_SHIFT 0 /**< Shift value for PRS_CH0PULSE */
AnnaBridge 171:3a7713b1edbc 3237 #define _PRS_SWPULSE_CH0PULSE_MASK 0x1UL /**< Bit mask for PRS_CH0PULSE */
AnnaBridge 171:3a7713b1edbc 3238 #define _PRS_SWPULSE_CH0PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3239 #define PRS_SWPULSE_CH0PULSE_DEFAULT (_PRS_SWPULSE_CH0PULSE_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3240 #define PRS_SWPULSE_CH1PULSE (0x1UL << 1) /**< Channel 1 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3241 #define _PRS_SWPULSE_CH1PULSE_SHIFT 1 /**< Shift value for PRS_CH1PULSE */
AnnaBridge 171:3a7713b1edbc 3242 #define _PRS_SWPULSE_CH1PULSE_MASK 0x2UL /**< Bit mask for PRS_CH1PULSE */
AnnaBridge 171:3a7713b1edbc 3243 #define _PRS_SWPULSE_CH1PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3244 #define PRS_SWPULSE_CH1PULSE_DEFAULT (_PRS_SWPULSE_CH1PULSE_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3245 #define PRS_SWPULSE_CH2PULSE (0x1UL << 2) /**< Channel 2 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3246 #define _PRS_SWPULSE_CH2PULSE_SHIFT 2 /**< Shift value for PRS_CH2PULSE */
AnnaBridge 171:3a7713b1edbc 3247 #define _PRS_SWPULSE_CH2PULSE_MASK 0x4UL /**< Bit mask for PRS_CH2PULSE */
AnnaBridge 171:3a7713b1edbc 3248 #define _PRS_SWPULSE_CH2PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3249 #define PRS_SWPULSE_CH2PULSE_DEFAULT (_PRS_SWPULSE_CH2PULSE_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3250 #define PRS_SWPULSE_CH3PULSE (0x1UL << 3) /**< Channel 3 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3251 #define _PRS_SWPULSE_CH3PULSE_SHIFT 3 /**< Shift value for PRS_CH3PULSE */
AnnaBridge 171:3a7713b1edbc 3252 #define _PRS_SWPULSE_CH3PULSE_MASK 0x8UL /**< Bit mask for PRS_CH3PULSE */
AnnaBridge 171:3a7713b1edbc 3253 #define _PRS_SWPULSE_CH3PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3254 #define PRS_SWPULSE_CH3PULSE_DEFAULT (_PRS_SWPULSE_CH3PULSE_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3255 #define PRS_SWPULSE_CH4PULSE (0x1UL << 4) /**< Channel 4 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3256 #define _PRS_SWPULSE_CH4PULSE_SHIFT 4 /**< Shift value for PRS_CH4PULSE */
AnnaBridge 171:3a7713b1edbc 3257 #define _PRS_SWPULSE_CH4PULSE_MASK 0x10UL /**< Bit mask for PRS_CH4PULSE */
AnnaBridge 171:3a7713b1edbc 3258 #define _PRS_SWPULSE_CH4PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3259 #define PRS_SWPULSE_CH4PULSE_DEFAULT (_PRS_SWPULSE_CH4PULSE_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3260 #define PRS_SWPULSE_CH5PULSE (0x1UL << 5) /**< Channel 5 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3261 #define _PRS_SWPULSE_CH5PULSE_SHIFT 5 /**< Shift value for PRS_CH5PULSE */
AnnaBridge 171:3a7713b1edbc 3262 #define _PRS_SWPULSE_CH5PULSE_MASK 0x20UL /**< Bit mask for PRS_CH5PULSE */
AnnaBridge 171:3a7713b1edbc 3263 #define _PRS_SWPULSE_CH5PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3264 #define PRS_SWPULSE_CH5PULSE_DEFAULT (_PRS_SWPULSE_CH5PULSE_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3265 #define PRS_SWPULSE_CH6PULSE (0x1UL << 6) /**< Channel 6 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3266 #define _PRS_SWPULSE_CH6PULSE_SHIFT 6 /**< Shift value for PRS_CH6PULSE */
AnnaBridge 171:3a7713b1edbc 3267 #define _PRS_SWPULSE_CH6PULSE_MASK 0x40UL /**< Bit mask for PRS_CH6PULSE */
AnnaBridge 171:3a7713b1edbc 3268 #define _PRS_SWPULSE_CH6PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3269 #define PRS_SWPULSE_CH6PULSE_DEFAULT (_PRS_SWPULSE_CH6PULSE_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3270 #define PRS_SWPULSE_CH7PULSE (0x1UL << 7) /**< Channel 7 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3271 #define _PRS_SWPULSE_CH7PULSE_SHIFT 7 /**< Shift value for PRS_CH7PULSE */
AnnaBridge 171:3a7713b1edbc 3272 #define _PRS_SWPULSE_CH7PULSE_MASK 0x80UL /**< Bit mask for PRS_CH7PULSE */
AnnaBridge 171:3a7713b1edbc 3273 #define _PRS_SWPULSE_CH7PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3274 #define PRS_SWPULSE_CH7PULSE_DEFAULT (_PRS_SWPULSE_CH7PULSE_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3275 #define PRS_SWPULSE_CH8PULSE (0x1UL << 8) /**< Channel 8 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3276 #define _PRS_SWPULSE_CH8PULSE_SHIFT 8 /**< Shift value for PRS_CH8PULSE */
AnnaBridge 171:3a7713b1edbc 3277 #define _PRS_SWPULSE_CH8PULSE_MASK 0x100UL /**< Bit mask for PRS_CH8PULSE */
AnnaBridge 171:3a7713b1edbc 3278 #define _PRS_SWPULSE_CH8PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3279 #define PRS_SWPULSE_CH8PULSE_DEFAULT (_PRS_SWPULSE_CH8PULSE_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3280 #define PRS_SWPULSE_CH9PULSE (0x1UL << 9) /**< Channel 9 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3281 #define _PRS_SWPULSE_CH9PULSE_SHIFT 9 /**< Shift value for PRS_CH9PULSE */
AnnaBridge 171:3a7713b1edbc 3282 #define _PRS_SWPULSE_CH9PULSE_MASK 0x200UL /**< Bit mask for PRS_CH9PULSE */
AnnaBridge 171:3a7713b1edbc 3283 #define _PRS_SWPULSE_CH9PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3284 #define PRS_SWPULSE_CH9PULSE_DEFAULT (_PRS_SWPULSE_CH9PULSE_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3285 #define PRS_SWPULSE_CH10PULSE (0x1UL << 10) /**< Channel 10 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3286 #define _PRS_SWPULSE_CH10PULSE_SHIFT 10 /**< Shift value for PRS_CH10PULSE */
AnnaBridge 171:3a7713b1edbc 3287 #define _PRS_SWPULSE_CH10PULSE_MASK 0x400UL /**< Bit mask for PRS_CH10PULSE */
AnnaBridge 171:3a7713b1edbc 3288 #define _PRS_SWPULSE_CH10PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3289 #define PRS_SWPULSE_CH10PULSE_DEFAULT (_PRS_SWPULSE_CH10PULSE_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3290 #define PRS_SWPULSE_CH11PULSE (0x1UL << 11) /**< Channel 11 Pulse Generation */
AnnaBridge 171:3a7713b1edbc 3291 #define _PRS_SWPULSE_CH11PULSE_SHIFT 11 /**< Shift value for PRS_CH11PULSE */
AnnaBridge 171:3a7713b1edbc 3292 #define _PRS_SWPULSE_CH11PULSE_MASK 0x800UL /**< Bit mask for PRS_CH11PULSE */
AnnaBridge 171:3a7713b1edbc 3293 #define _PRS_SWPULSE_CH11PULSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3294 #define PRS_SWPULSE_CH11PULSE_DEFAULT (_PRS_SWPULSE_CH11PULSE_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWPULSE */
AnnaBridge 171:3a7713b1edbc 3295
AnnaBridge 171:3a7713b1edbc 3296 /* Bit fields for PRS SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3297 #define _PRS_SWLEVEL_RESETVALUE 0x00000000UL /**< Default value for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3298 #define _PRS_SWLEVEL_MASK 0x00000FFFUL /**< Mask for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3299 #define PRS_SWLEVEL_CH0LEVEL (0x1UL << 0) /**< Channel 0 Software Level */
AnnaBridge 171:3a7713b1edbc 3300 #define _PRS_SWLEVEL_CH0LEVEL_SHIFT 0 /**< Shift value for PRS_CH0LEVEL */
AnnaBridge 171:3a7713b1edbc 3301 #define _PRS_SWLEVEL_CH0LEVEL_MASK 0x1UL /**< Bit mask for PRS_CH0LEVEL */
AnnaBridge 171:3a7713b1edbc 3302 #define _PRS_SWLEVEL_CH0LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3303 #define PRS_SWLEVEL_CH0LEVEL_DEFAULT (_PRS_SWLEVEL_CH0LEVEL_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3304 #define PRS_SWLEVEL_CH1LEVEL (0x1UL << 1) /**< Channel 1 Software Level */
AnnaBridge 171:3a7713b1edbc 3305 #define _PRS_SWLEVEL_CH1LEVEL_SHIFT 1 /**< Shift value for PRS_CH1LEVEL */
AnnaBridge 171:3a7713b1edbc 3306 #define _PRS_SWLEVEL_CH1LEVEL_MASK 0x2UL /**< Bit mask for PRS_CH1LEVEL */
AnnaBridge 171:3a7713b1edbc 3307 #define _PRS_SWLEVEL_CH1LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3308 #define PRS_SWLEVEL_CH1LEVEL_DEFAULT (_PRS_SWLEVEL_CH1LEVEL_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3309 #define PRS_SWLEVEL_CH2LEVEL (0x1UL << 2) /**< Channel 2 Software Level */
AnnaBridge 171:3a7713b1edbc 3310 #define _PRS_SWLEVEL_CH2LEVEL_SHIFT 2 /**< Shift value for PRS_CH2LEVEL */
AnnaBridge 171:3a7713b1edbc 3311 #define _PRS_SWLEVEL_CH2LEVEL_MASK 0x4UL /**< Bit mask for PRS_CH2LEVEL */
AnnaBridge 171:3a7713b1edbc 3312 #define _PRS_SWLEVEL_CH2LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3313 #define PRS_SWLEVEL_CH2LEVEL_DEFAULT (_PRS_SWLEVEL_CH2LEVEL_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3314 #define PRS_SWLEVEL_CH3LEVEL (0x1UL << 3) /**< Channel 3 Software Level */
AnnaBridge 171:3a7713b1edbc 3315 #define _PRS_SWLEVEL_CH3LEVEL_SHIFT 3 /**< Shift value for PRS_CH3LEVEL */
AnnaBridge 171:3a7713b1edbc 3316 #define _PRS_SWLEVEL_CH3LEVEL_MASK 0x8UL /**< Bit mask for PRS_CH3LEVEL */
AnnaBridge 171:3a7713b1edbc 3317 #define _PRS_SWLEVEL_CH3LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3318 #define PRS_SWLEVEL_CH3LEVEL_DEFAULT (_PRS_SWLEVEL_CH3LEVEL_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3319 #define PRS_SWLEVEL_CH4LEVEL (0x1UL << 4) /**< Channel 4 Software Level */
AnnaBridge 171:3a7713b1edbc 3320 #define _PRS_SWLEVEL_CH4LEVEL_SHIFT 4 /**< Shift value for PRS_CH4LEVEL */
AnnaBridge 171:3a7713b1edbc 3321 #define _PRS_SWLEVEL_CH4LEVEL_MASK 0x10UL /**< Bit mask for PRS_CH4LEVEL */
AnnaBridge 171:3a7713b1edbc 3322 #define _PRS_SWLEVEL_CH4LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3323 #define PRS_SWLEVEL_CH4LEVEL_DEFAULT (_PRS_SWLEVEL_CH4LEVEL_DEFAULT << 4) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3324 #define PRS_SWLEVEL_CH5LEVEL (0x1UL << 5) /**< Channel 5 Software Level */
AnnaBridge 171:3a7713b1edbc 3325 #define _PRS_SWLEVEL_CH5LEVEL_SHIFT 5 /**< Shift value for PRS_CH5LEVEL */
AnnaBridge 171:3a7713b1edbc 3326 #define _PRS_SWLEVEL_CH5LEVEL_MASK 0x20UL /**< Bit mask for PRS_CH5LEVEL */
AnnaBridge 171:3a7713b1edbc 3327 #define _PRS_SWLEVEL_CH5LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3328 #define PRS_SWLEVEL_CH5LEVEL_DEFAULT (_PRS_SWLEVEL_CH5LEVEL_DEFAULT << 5) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3329 #define PRS_SWLEVEL_CH6LEVEL (0x1UL << 6) /**< Channel 6 Software Level */
AnnaBridge 171:3a7713b1edbc 3330 #define _PRS_SWLEVEL_CH6LEVEL_SHIFT 6 /**< Shift value for PRS_CH6LEVEL */
AnnaBridge 171:3a7713b1edbc 3331 #define _PRS_SWLEVEL_CH6LEVEL_MASK 0x40UL /**< Bit mask for PRS_CH6LEVEL */
AnnaBridge 171:3a7713b1edbc 3332 #define _PRS_SWLEVEL_CH6LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3333 #define PRS_SWLEVEL_CH6LEVEL_DEFAULT (_PRS_SWLEVEL_CH6LEVEL_DEFAULT << 6) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3334 #define PRS_SWLEVEL_CH7LEVEL (0x1UL << 7) /**< Channel 7 Software Level */
AnnaBridge 171:3a7713b1edbc 3335 #define _PRS_SWLEVEL_CH7LEVEL_SHIFT 7 /**< Shift value for PRS_CH7LEVEL */
AnnaBridge 171:3a7713b1edbc 3336 #define _PRS_SWLEVEL_CH7LEVEL_MASK 0x80UL /**< Bit mask for PRS_CH7LEVEL */
AnnaBridge 171:3a7713b1edbc 3337 #define _PRS_SWLEVEL_CH7LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3338 #define PRS_SWLEVEL_CH7LEVEL_DEFAULT (_PRS_SWLEVEL_CH7LEVEL_DEFAULT << 7) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3339 #define PRS_SWLEVEL_CH8LEVEL (0x1UL << 8) /**< Channel 8 Software Level */
AnnaBridge 171:3a7713b1edbc 3340 #define _PRS_SWLEVEL_CH8LEVEL_SHIFT 8 /**< Shift value for PRS_CH8LEVEL */
AnnaBridge 171:3a7713b1edbc 3341 #define _PRS_SWLEVEL_CH8LEVEL_MASK 0x100UL /**< Bit mask for PRS_CH8LEVEL */
AnnaBridge 171:3a7713b1edbc 3342 #define _PRS_SWLEVEL_CH8LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3343 #define PRS_SWLEVEL_CH8LEVEL_DEFAULT (_PRS_SWLEVEL_CH8LEVEL_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3344 #define PRS_SWLEVEL_CH9LEVEL (0x1UL << 9) /**< Channel 9 Software Level */
AnnaBridge 171:3a7713b1edbc 3345 #define _PRS_SWLEVEL_CH9LEVEL_SHIFT 9 /**< Shift value for PRS_CH9LEVEL */
AnnaBridge 171:3a7713b1edbc 3346 #define _PRS_SWLEVEL_CH9LEVEL_MASK 0x200UL /**< Bit mask for PRS_CH9LEVEL */
AnnaBridge 171:3a7713b1edbc 3347 #define _PRS_SWLEVEL_CH9LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3348 #define PRS_SWLEVEL_CH9LEVEL_DEFAULT (_PRS_SWLEVEL_CH9LEVEL_DEFAULT << 9) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3349 #define PRS_SWLEVEL_CH10LEVEL (0x1UL << 10) /**< Channel 10 Software Level */
AnnaBridge 171:3a7713b1edbc 3350 #define _PRS_SWLEVEL_CH10LEVEL_SHIFT 10 /**< Shift value for PRS_CH10LEVEL */
AnnaBridge 171:3a7713b1edbc 3351 #define _PRS_SWLEVEL_CH10LEVEL_MASK 0x400UL /**< Bit mask for PRS_CH10LEVEL */
AnnaBridge 171:3a7713b1edbc 3352 #define _PRS_SWLEVEL_CH10LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3353 #define PRS_SWLEVEL_CH10LEVEL_DEFAULT (_PRS_SWLEVEL_CH10LEVEL_DEFAULT << 10) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3354 #define PRS_SWLEVEL_CH11LEVEL (0x1UL << 11) /**< Channel 11 Software Level */
AnnaBridge 171:3a7713b1edbc 3355 #define _PRS_SWLEVEL_CH11LEVEL_SHIFT 11 /**< Shift value for PRS_CH11LEVEL */
AnnaBridge 171:3a7713b1edbc 3356 #define _PRS_SWLEVEL_CH11LEVEL_MASK 0x800UL /**< Bit mask for PRS_CH11LEVEL */
AnnaBridge 171:3a7713b1edbc 3357 #define _PRS_SWLEVEL_CH11LEVEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3358 #define PRS_SWLEVEL_CH11LEVEL_DEFAULT (_PRS_SWLEVEL_CH11LEVEL_DEFAULT << 11) /**< Shifted mode DEFAULT for PRS_SWLEVEL */
AnnaBridge 171:3a7713b1edbc 3359
AnnaBridge 171:3a7713b1edbc 3360 /* Bit fields for PRS ROUTE */
AnnaBridge 171:3a7713b1edbc 3361 #define _PRS_ROUTE_RESETVALUE 0x00000000UL /**< Default value for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3362 #define _PRS_ROUTE_MASK 0x0000070FUL /**< Mask for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3363 #define PRS_ROUTE_CH0PEN (0x1UL << 0) /**< CH0 Pin Enable */
AnnaBridge 171:3a7713b1edbc 3364 #define _PRS_ROUTE_CH0PEN_SHIFT 0 /**< Shift value for PRS_CH0PEN */
AnnaBridge 171:3a7713b1edbc 3365 #define _PRS_ROUTE_CH0PEN_MASK 0x1UL /**< Bit mask for PRS_CH0PEN */
AnnaBridge 171:3a7713b1edbc 3366 #define _PRS_ROUTE_CH0PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3367 #define PRS_ROUTE_CH0PEN_DEFAULT (_PRS_ROUTE_CH0PEN_DEFAULT << 0) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3368 #define PRS_ROUTE_CH1PEN (0x1UL << 1) /**< CH1 Pin Enable */
AnnaBridge 171:3a7713b1edbc 3369 #define _PRS_ROUTE_CH1PEN_SHIFT 1 /**< Shift value for PRS_CH1PEN */
AnnaBridge 171:3a7713b1edbc 3370 #define _PRS_ROUTE_CH1PEN_MASK 0x2UL /**< Bit mask for PRS_CH1PEN */
AnnaBridge 171:3a7713b1edbc 3371 #define _PRS_ROUTE_CH1PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3372 #define PRS_ROUTE_CH1PEN_DEFAULT (_PRS_ROUTE_CH1PEN_DEFAULT << 1) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3373 #define PRS_ROUTE_CH2PEN (0x1UL << 2) /**< CH2 Pin Enable */
AnnaBridge 171:3a7713b1edbc 3374 #define _PRS_ROUTE_CH2PEN_SHIFT 2 /**< Shift value for PRS_CH2PEN */
AnnaBridge 171:3a7713b1edbc 3375 #define _PRS_ROUTE_CH2PEN_MASK 0x4UL /**< Bit mask for PRS_CH2PEN */
AnnaBridge 171:3a7713b1edbc 3376 #define _PRS_ROUTE_CH2PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3377 #define PRS_ROUTE_CH2PEN_DEFAULT (_PRS_ROUTE_CH2PEN_DEFAULT << 2) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3378 #define PRS_ROUTE_CH3PEN (0x1UL << 3) /**< CH3 Pin Enable */
AnnaBridge 171:3a7713b1edbc 3379 #define _PRS_ROUTE_CH3PEN_SHIFT 3 /**< Shift value for PRS_CH3PEN */
AnnaBridge 171:3a7713b1edbc 3380 #define _PRS_ROUTE_CH3PEN_MASK 0x8UL /**< Bit mask for PRS_CH3PEN */
AnnaBridge 171:3a7713b1edbc 3381 #define _PRS_ROUTE_CH3PEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3382 #define PRS_ROUTE_CH3PEN_DEFAULT (_PRS_ROUTE_CH3PEN_DEFAULT << 3) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3383 #define _PRS_ROUTE_LOCATION_SHIFT 8 /**< Shift value for PRS_LOCATION */
AnnaBridge 171:3a7713b1edbc 3384 #define _PRS_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for PRS_LOCATION */
AnnaBridge 171:3a7713b1edbc 3385 #define _PRS_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3386 #define _PRS_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3387 #define _PRS_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3388 #define PRS_ROUTE_LOCATION_LOC0 (_PRS_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3389 #define PRS_ROUTE_LOCATION_DEFAULT (_PRS_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3390 #define PRS_ROUTE_LOCATION_LOC1 (_PRS_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for PRS_ROUTE */
AnnaBridge 171:3a7713b1edbc 3391
AnnaBridge 171:3a7713b1edbc 3392 /* Bit fields for PRS CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3393 #define _PRS_CH_CTRL_RESETVALUE 0x00000000UL /**< Default value for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3394 #define _PRS_CH_CTRL_MASK 0x133F0007UL /**< Mask for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3395 #define _PRS_CH_CTRL_SIGSEL_SHIFT 0 /**< Shift value for PRS_SIGSEL */
AnnaBridge 171:3a7713b1edbc 3396 #define _PRS_CH_CTRL_SIGSEL_MASK 0x7UL /**< Bit mask for PRS_SIGSEL */
AnnaBridge 171:3a7713b1edbc 3397 #define _PRS_CH_CTRL_SIGSEL_VCMPOUT 0x00000000UL /**< Mode VCMPOUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3398 #define _PRS_CH_CTRL_SIGSEL_ACMP0OUT 0x00000000UL /**< Mode ACMP0OUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3399 #define _PRS_CH_CTRL_SIGSEL_ACMP1OUT 0x00000000UL /**< Mode ACMP1OUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3400 #define _PRS_CH_CTRL_SIGSEL_DAC0CH0 0x00000000UL /**< Mode DAC0CH0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3401 #define _PRS_CH_CTRL_SIGSEL_ADC0SINGLE 0x00000000UL /**< Mode ADC0SINGLE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3402 #define _PRS_CH_CTRL_SIGSEL_USART0IRTX 0x00000000UL /**< Mode USART0IRTX for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3403 #define _PRS_CH_CTRL_SIGSEL_TIMER0UF 0x00000000UL /**< Mode TIMER0UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3404 #define _PRS_CH_CTRL_SIGSEL_TIMER1UF 0x00000000UL /**< Mode TIMER1UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3405 #define _PRS_CH_CTRL_SIGSEL_TIMER2UF 0x00000000UL /**< Mode TIMER2UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3406 #define _PRS_CH_CTRL_SIGSEL_TIMER3UF 0x00000000UL /**< Mode TIMER3UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3407 #define _PRS_CH_CTRL_SIGSEL_RTCOF 0x00000000UL /**< Mode RTCOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3408 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN0 0x00000000UL /**< Mode GPIOPIN0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3409 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN8 0x00000000UL /**< Mode GPIOPIN8 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3410 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH0 0x00000000UL /**< Mode LETIMER0CH0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3411 #define _PRS_CH_CTRL_SIGSEL_BURTCOF 0x00000000UL /**< Mode BURTCOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3412 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 0x00000000UL /**< Mode LESENSESCANRES0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3413 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 0x00000000UL /**< Mode LESENSESCANRES8 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3414 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC0 0x00000000UL /**< Mode LESENSEDEC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3415 #define _PRS_CH_CTRL_SIGSEL_DAC0CH1 0x00000001UL /**< Mode DAC0CH1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3416 #define _PRS_CH_CTRL_SIGSEL_ADC0SCAN 0x00000001UL /**< Mode ADC0SCAN for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3417 #define _PRS_CH_CTRL_SIGSEL_USART0TXC 0x00000001UL /**< Mode USART0TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3418 #define _PRS_CH_CTRL_SIGSEL_USART1TXC 0x00000001UL /**< Mode USART1TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3419 #define _PRS_CH_CTRL_SIGSEL_USART2TXC 0x00000001UL /**< Mode USART2TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3420 #define _PRS_CH_CTRL_SIGSEL_TIMER0OF 0x00000001UL /**< Mode TIMER0OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3421 #define _PRS_CH_CTRL_SIGSEL_TIMER1OF 0x00000001UL /**< Mode TIMER1OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3422 #define _PRS_CH_CTRL_SIGSEL_TIMER2OF 0x00000001UL /**< Mode TIMER2OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3423 #define _PRS_CH_CTRL_SIGSEL_TIMER3OF 0x00000001UL /**< Mode TIMER3OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3424 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP0 0x00000001UL /**< Mode RTCCOMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3425 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN1 0x00000001UL /**< Mode GPIOPIN1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3426 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN9 0x00000001UL /**< Mode GPIOPIN9 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3427 #define _PRS_CH_CTRL_SIGSEL_LETIMER0CH1 0x00000001UL /**< Mode LETIMER0CH1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3428 #define _PRS_CH_CTRL_SIGSEL_BURTCCOMP0 0x00000001UL /**< Mode BURTCCOMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3429 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 0x00000001UL /**< Mode LESENSESCANRES1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3430 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 0x00000001UL /**< Mode LESENSESCANRES9 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3431 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC1 0x00000001UL /**< Mode LESENSEDEC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3432 #define _PRS_CH_CTRL_SIGSEL_USART0RXDATAV 0x00000002UL /**< Mode USART0RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3433 #define _PRS_CH_CTRL_SIGSEL_USART1RXDATAV 0x00000002UL /**< Mode USART1RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3434 #define _PRS_CH_CTRL_SIGSEL_USART2RXDATAV 0x00000002UL /**< Mode USART2RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3435 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC0 0x00000002UL /**< Mode TIMER0CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3436 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC0 0x00000002UL /**< Mode TIMER1CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3437 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC0 0x00000002UL /**< Mode TIMER2CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3438 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC0 0x00000002UL /**< Mode TIMER3CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3439 #define _PRS_CH_CTRL_SIGSEL_RTCCOMP1 0x00000002UL /**< Mode RTCCOMP1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3440 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN2 0x00000002UL /**< Mode GPIOPIN2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3441 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN10 0x00000002UL /**< Mode GPIOPIN10 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3442 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 0x00000002UL /**< Mode LESENSESCANRES2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3443 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 0x00000002UL /**< Mode LESENSESCANRES10 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3444 #define _PRS_CH_CTRL_SIGSEL_LESENSEDEC2 0x00000002UL /**< Mode LESENSEDEC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3445 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC1 0x00000003UL /**< Mode TIMER0CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3446 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC1 0x00000003UL /**< Mode TIMER1CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3447 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC1 0x00000003UL /**< Mode TIMER2CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3448 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC1 0x00000003UL /**< Mode TIMER3CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3449 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN3 0x00000003UL /**< Mode GPIOPIN3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3450 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN11 0x00000003UL /**< Mode GPIOPIN11 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3451 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 0x00000003UL /**< Mode LESENSESCANRES3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3452 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 0x00000003UL /**< Mode LESENSESCANRES11 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3453 #define _PRS_CH_CTRL_SIGSEL_TIMER0CC2 0x00000004UL /**< Mode TIMER0CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3454 #define _PRS_CH_CTRL_SIGSEL_TIMER1CC2 0x00000004UL /**< Mode TIMER1CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3455 #define _PRS_CH_CTRL_SIGSEL_TIMER2CC2 0x00000004UL /**< Mode TIMER2CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3456 #define _PRS_CH_CTRL_SIGSEL_TIMER3CC2 0x00000004UL /**< Mode TIMER3CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3457 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN4 0x00000004UL /**< Mode GPIOPIN4 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3458 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN12 0x00000004UL /**< Mode GPIOPIN12 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3459 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 0x00000004UL /**< Mode LESENSESCANRES4 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3460 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 0x00000004UL /**< Mode LESENSESCANRES12 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3461 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN5 0x00000005UL /**< Mode GPIOPIN5 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3462 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN13 0x00000005UL /**< Mode GPIOPIN13 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3463 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 0x00000005UL /**< Mode LESENSESCANRES5 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3464 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 0x00000005UL /**< Mode LESENSESCANRES13 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3465 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN6 0x00000006UL /**< Mode GPIOPIN6 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3466 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN14 0x00000006UL /**< Mode GPIOPIN14 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3467 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 0x00000006UL /**< Mode LESENSESCANRES6 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3468 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 0x00000006UL /**< Mode LESENSESCANRES14 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3469 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN7 0x00000007UL /**< Mode GPIOPIN7 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3470 #define _PRS_CH_CTRL_SIGSEL_GPIOPIN15 0x00000007UL /**< Mode GPIOPIN15 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3471 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 0x00000007UL /**< Mode LESENSESCANRES7 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3472 #define _PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 0x00000007UL /**< Mode LESENSESCANRES15 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3473 #define PRS_CH_CTRL_SIGSEL_VCMPOUT (_PRS_CH_CTRL_SIGSEL_VCMPOUT << 0) /**< Shifted mode VCMPOUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3474 #define PRS_CH_CTRL_SIGSEL_ACMP0OUT (_PRS_CH_CTRL_SIGSEL_ACMP0OUT << 0) /**< Shifted mode ACMP0OUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3475 #define PRS_CH_CTRL_SIGSEL_ACMP1OUT (_PRS_CH_CTRL_SIGSEL_ACMP1OUT << 0) /**< Shifted mode ACMP1OUT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3476 #define PRS_CH_CTRL_SIGSEL_DAC0CH0 (_PRS_CH_CTRL_SIGSEL_DAC0CH0 << 0) /**< Shifted mode DAC0CH0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3477 #define PRS_CH_CTRL_SIGSEL_ADC0SINGLE (_PRS_CH_CTRL_SIGSEL_ADC0SINGLE << 0) /**< Shifted mode ADC0SINGLE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3478 #define PRS_CH_CTRL_SIGSEL_USART0IRTX (_PRS_CH_CTRL_SIGSEL_USART0IRTX << 0) /**< Shifted mode USART0IRTX for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3479 #define PRS_CH_CTRL_SIGSEL_TIMER0UF (_PRS_CH_CTRL_SIGSEL_TIMER0UF << 0) /**< Shifted mode TIMER0UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3480 #define PRS_CH_CTRL_SIGSEL_TIMER1UF (_PRS_CH_CTRL_SIGSEL_TIMER1UF << 0) /**< Shifted mode TIMER1UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3481 #define PRS_CH_CTRL_SIGSEL_TIMER2UF (_PRS_CH_CTRL_SIGSEL_TIMER2UF << 0) /**< Shifted mode TIMER2UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3482 #define PRS_CH_CTRL_SIGSEL_TIMER3UF (_PRS_CH_CTRL_SIGSEL_TIMER3UF << 0) /**< Shifted mode TIMER3UF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3483 #define PRS_CH_CTRL_SIGSEL_RTCOF (_PRS_CH_CTRL_SIGSEL_RTCOF << 0) /**< Shifted mode RTCOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3484 #define PRS_CH_CTRL_SIGSEL_GPIOPIN0 (_PRS_CH_CTRL_SIGSEL_GPIOPIN0 << 0) /**< Shifted mode GPIOPIN0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3485 #define PRS_CH_CTRL_SIGSEL_GPIOPIN8 (_PRS_CH_CTRL_SIGSEL_GPIOPIN8 << 0) /**< Shifted mode GPIOPIN8 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3486 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH0 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH0 << 0) /**< Shifted mode LETIMER0CH0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3487 #define PRS_CH_CTRL_SIGSEL_BURTCOF (_PRS_CH_CTRL_SIGSEL_BURTCOF << 0) /**< Shifted mode BURTCOF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3488 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES0 << 0) /**< Shifted mode LESENSESCANRES0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3489 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES8 << 0) /**< Shifted mode LESENSESCANRES8 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3490 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC0 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC0 << 0) /**< Shifted mode LESENSEDEC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3491 #define PRS_CH_CTRL_SIGSEL_DAC0CH1 (_PRS_CH_CTRL_SIGSEL_DAC0CH1 << 0) /**< Shifted mode DAC0CH1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3492 #define PRS_CH_CTRL_SIGSEL_ADC0SCAN (_PRS_CH_CTRL_SIGSEL_ADC0SCAN << 0) /**< Shifted mode ADC0SCAN for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3493 #define PRS_CH_CTRL_SIGSEL_USART0TXC (_PRS_CH_CTRL_SIGSEL_USART0TXC << 0) /**< Shifted mode USART0TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3494 #define PRS_CH_CTRL_SIGSEL_USART1TXC (_PRS_CH_CTRL_SIGSEL_USART1TXC << 0) /**< Shifted mode USART1TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3495 #define PRS_CH_CTRL_SIGSEL_USART2TXC (_PRS_CH_CTRL_SIGSEL_USART2TXC << 0) /**< Shifted mode USART2TXC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3496 #define PRS_CH_CTRL_SIGSEL_TIMER0OF (_PRS_CH_CTRL_SIGSEL_TIMER0OF << 0) /**< Shifted mode TIMER0OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3497 #define PRS_CH_CTRL_SIGSEL_TIMER1OF (_PRS_CH_CTRL_SIGSEL_TIMER1OF << 0) /**< Shifted mode TIMER1OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3498 #define PRS_CH_CTRL_SIGSEL_TIMER2OF (_PRS_CH_CTRL_SIGSEL_TIMER2OF << 0) /**< Shifted mode TIMER2OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3499 #define PRS_CH_CTRL_SIGSEL_TIMER3OF (_PRS_CH_CTRL_SIGSEL_TIMER3OF << 0) /**< Shifted mode TIMER3OF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3500 #define PRS_CH_CTRL_SIGSEL_RTCCOMP0 (_PRS_CH_CTRL_SIGSEL_RTCCOMP0 << 0) /**< Shifted mode RTCCOMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3501 #define PRS_CH_CTRL_SIGSEL_GPIOPIN1 (_PRS_CH_CTRL_SIGSEL_GPIOPIN1 << 0) /**< Shifted mode GPIOPIN1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3502 #define PRS_CH_CTRL_SIGSEL_GPIOPIN9 (_PRS_CH_CTRL_SIGSEL_GPIOPIN9 << 0) /**< Shifted mode GPIOPIN9 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3503 #define PRS_CH_CTRL_SIGSEL_LETIMER0CH1 (_PRS_CH_CTRL_SIGSEL_LETIMER0CH1 << 0) /**< Shifted mode LETIMER0CH1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3504 #define PRS_CH_CTRL_SIGSEL_BURTCCOMP0 (_PRS_CH_CTRL_SIGSEL_BURTCCOMP0 << 0) /**< Shifted mode BURTCCOMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3505 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES1 << 0) /**< Shifted mode LESENSESCANRES1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3506 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES9 << 0) /**< Shifted mode LESENSESCANRES9 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3507 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC1 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC1 << 0) /**< Shifted mode LESENSEDEC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3508 #define PRS_CH_CTRL_SIGSEL_USART0RXDATAV (_PRS_CH_CTRL_SIGSEL_USART0RXDATAV << 0) /**< Shifted mode USART0RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3509 #define PRS_CH_CTRL_SIGSEL_USART1RXDATAV (_PRS_CH_CTRL_SIGSEL_USART1RXDATAV << 0) /**< Shifted mode USART1RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3510 #define PRS_CH_CTRL_SIGSEL_USART2RXDATAV (_PRS_CH_CTRL_SIGSEL_USART2RXDATAV << 0) /**< Shifted mode USART2RXDATAV for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3511 #define PRS_CH_CTRL_SIGSEL_TIMER0CC0 (_PRS_CH_CTRL_SIGSEL_TIMER0CC0 << 0) /**< Shifted mode TIMER0CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3512 #define PRS_CH_CTRL_SIGSEL_TIMER1CC0 (_PRS_CH_CTRL_SIGSEL_TIMER1CC0 << 0) /**< Shifted mode TIMER1CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3513 #define PRS_CH_CTRL_SIGSEL_TIMER2CC0 (_PRS_CH_CTRL_SIGSEL_TIMER2CC0 << 0) /**< Shifted mode TIMER2CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3514 #define PRS_CH_CTRL_SIGSEL_TIMER3CC0 (_PRS_CH_CTRL_SIGSEL_TIMER3CC0 << 0) /**< Shifted mode TIMER3CC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3515 #define PRS_CH_CTRL_SIGSEL_RTCCOMP1 (_PRS_CH_CTRL_SIGSEL_RTCCOMP1 << 0) /**< Shifted mode RTCCOMP1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3516 #define PRS_CH_CTRL_SIGSEL_GPIOPIN2 (_PRS_CH_CTRL_SIGSEL_GPIOPIN2 << 0) /**< Shifted mode GPIOPIN2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3517 #define PRS_CH_CTRL_SIGSEL_GPIOPIN10 (_PRS_CH_CTRL_SIGSEL_GPIOPIN10 << 0) /**< Shifted mode GPIOPIN10 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3518 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES2 << 0) /**< Shifted mode LESENSESCANRES2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3519 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES10 << 0) /**< Shifted mode LESENSESCANRES10 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3520 #define PRS_CH_CTRL_SIGSEL_LESENSEDEC2 (_PRS_CH_CTRL_SIGSEL_LESENSEDEC2 << 0) /**< Shifted mode LESENSEDEC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3521 #define PRS_CH_CTRL_SIGSEL_TIMER0CC1 (_PRS_CH_CTRL_SIGSEL_TIMER0CC1 << 0) /**< Shifted mode TIMER0CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3522 #define PRS_CH_CTRL_SIGSEL_TIMER1CC1 (_PRS_CH_CTRL_SIGSEL_TIMER1CC1 << 0) /**< Shifted mode TIMER1CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3523 #define PRS_CH_CTRL_SIGSEL_TIMER2CC1 (_PRS_CH_CTRL_SIGSEL_TIMER2CC1 << 0) /**< Shifted mode TIMER2CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3524 #define PRS_CH_CTRL_SIGSEL_TIMER3CC1 (_PRS_CH_CTRL_SIGSEL_TIMER3CC1 << 0) /**< Shifted mode TIMER3CC1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3525 #define PRS_CH_CTRL_SIGSEL_GPIOPIN3 (_PRS_CH_CTRL_SIGSEL_GPIOPIN3 << 0) /**< Shifted mode GPIOPIN3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3526 #define PRS_CH_CTRL_SIGSEL_GPIOPIN11 (_PRS_CH_CTRL_SIGSEL_GPIOPIN11 << 0) /**< Shifted mode GPIOPIN11 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3527 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES3 << 0) /**< Shifted mode LESENSESCANRES3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3528 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES11 << 0) /**< Shifted mode LESENSESCANRES11 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3529 #define PRS_CH_CTRL_SIGSEL_TIMER0CC2 (_PRS_CH_CTRL_SIGSEL_TIMER0CC2 << 0) /**< Shifted mode TIMER0CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3530 #define PRS_CH_CTRL_SIGSEL_TIMER1CC2 (_PRS_CH_CTRL_SIGSEL_TIMER1CC2 << 0) /**< Shifted mode TIMER1CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3531 #define PRS_CH_CTRL_SIGSEL_TIMER2CC2 (_PRS_CH_CTRL_SIGSEL_TIMER2CC2 << 0) /**< Shifted mode TIMER2CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3532 #define PRS_CH_CTRL_SIGSEL_TIMER3CC2 (_PRS_CH_CTRL_SIGSEL_TIMER3CC2 << 0) /**< Shifted mode TIMER3CC2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3533 #define PRS_CH_CTRL_SIGSEL_GPIOPIN4 (_PRS_CH_CTRL_SIGSEL_GPIOPIN4 << 0) /**< Shifted mode GPIOPIN4 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3534 #define PRS_CH_CTRL_SIGSEL_GPIOPIN12 (_PRS_CH_CTRL_SIGSEL_GPIOPIN12 << 0) /**< Shifted mode GPIOPIN12 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3535 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES4 << 0) /**< Shifted mode LESENSESCANRES4 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3536 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES12 << 0) /**< Shifted mode LESENSESCANRES12 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3537 #define PRS_CH_CTRL_SIGSEL_GPIOPIN5 (_PRS_CH_CTRL_SIGSEL_GPIOPIN5 << 0) /**< Shifted mode GPIOPIN5 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3538 #define PRS_CH_CTRL_SIGSEL_GPIOPIN13 (_PRS_CH_CTRL_SIGSEL_GPIOPIN13 << 0) /**< Shifted mode GPIOPIN13 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3539 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES5 << 0) /**< Shifted mode LESENSESCANRES5 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3540 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES13 << 0) /**< Shifted mode LESENSESCANRES13 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3541 #define PRS_CH_CTRL_SIGSEL_GPIOPIN6 (_PRS_CH_CTRL_SIGSEL_GPIOPIN6 << 0) /**< Shifted mode GPIOPIN6 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3542 #define PRS_CH_CTRL_SIGSEL_GPIOPIN14 (_PRS_CH_CTRL_SIGSEL_GPIOPIN14 << 0) /**< Shifted mode GPIOPIN14 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3543 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES6 << 0) /**< Shifted mode LESENSESCANRES6 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3544 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES14 << 0) /**< Shifted mode LESENSESCANRES14 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3545 #define PRS_CH_CTRL_SIGSEL_GPIOPIN7 (_PRS_CH_CTRL_SIGSEL_GPIOPIN7 << 0) /**< Shifted mode GPIOPIN7 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3546 #define PRS_CH_CTRL_SIGSEL_GPIOPIN15 (_PRS_CH_CTRL_SIGSEL_GPIOPIN15 << 0) /**< Shifted mode GPIOPIN15 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3547 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES7 << 0) /**< Shifted mode LESENSESCANRES7 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3548 #define PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 (_PRS_CH_CTRL_SIGSEL_LESENSESCANRES15 << 0) /**< Shifted mode LESENSESCANRES15 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3549 #define _PRS_CH_CTRL_SOURCESEL_SHIFT 16 /**< Shift value for PRS_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 3550 #define _PRS_CH_CTRL_SOURCESEL_MASK 0x3F0000UL /**< Bit mask for PRS_SOURCESEL */
AnnaBridge 171:3a7713b1edbc 3551 #define _PRS_CH_CTRL_SOURCESEL_NONE 0x00000000UL /**< Mode NONE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3552 #define _PRS_CH_CTRL_SOURCESEL_VCMP 0x00000001UL /**< Mode VCMP for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3553 #define _PRS_CH_CTRL_SOURCESEL_ACMP0 0x00000002UL /**< Mode ACMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3554 #define _PRS_CH_CTRL_SOURCESEL_ACMP1 0x00000003UL /**< Mode ACMP1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3555 #define _PRS_CH_CTRL_SOURCESEL_DAC0 0x00000006UL /**< Mode DAC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3556 #define _PRS_CH_CTRL_SOURCESEL_ADC0 0x00000008UL /**< Mode ADC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3557 #define _PRS_CH_CTRL_SOURCESEL_USART0 0x00000010UL /**< Mode USART0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3558 #define _PRS_CH_CTRL_SOURCESEL_USART1 0x00000011UL /**< Mode USART1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3559 #define _PRS_CH_CTRL_SOURCESEL_USART2 0x00000012UL /**< Mode USART2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3560 #define _PRS_CH_CTRL_SOURCESEL_TIMER0 0x0000001CUL /**< Mode TIMER0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3561 #define _PRS_CH_CTRL_SOURCESEL_TIMER1 0x0000001DUL /**< Mode TIMER1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3562 #define _PRS_CH_CTRL_SOURCESEL_TIMER2 0x0000001EUL /**< Mode TIMER2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3563 #define _PRS_CH_CTRL_SOURCESEL_TIMER3 0x0000001FUL /**< Mode TIMER3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3564 #define _PRS_CH_CTRL_SOURCESEL_RTC 0x00000028UL /**< Mode RTC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3565 #define _PRS_CH_CTRL_SOURCESEL_GPIOL 0x00000030UL /**< Mode GPIOL for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3566 #define _PRS_CH_CTRL_SOURCESEL_GPIOH 0x00000031UL /**< Mode GPIOH for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3567 #define _PRS_CH_CTRL_SOURCESEL_LETIMER0 0x00000034UL /**< Mode LETIMER0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3568 #define _PRS_CH_CTRL_SOURCESEL_BURTC 0x00000037UL /**< Mode BURTC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3569 #define _PRS_CH_CTRL_SOURCESEL_LESENSEL 0x00000039UL /**< Mode LESENSEL for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3570 #define _PRS_CH_CTRL_SOURCESEL_LESENSEH 0x0000003AUL /**< Mode LESENSEH for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3571 #define _PRS_CH_CTRL_SOURCESEL_LESENSED 0x0000003BUL /**< Mode LESENSED for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3572 #define PRS_CH_CTRL_SOURCESEL_NONE (_PRS_CH_CTRL_SOURCESEL_NONE << 16) /**< Shifted mode NONE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3573 #define PRS_CH_CTRL_SOURCESEL_VCMP (_PRS_CH_CTRL_SOURCESEL_VCMP << 16) /**< Shifted mode VCMP for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3574 #define PRS_CH_CTRL_SOURCESEL_ACMP0 (_PRS_CH_CTRL_SOURCESEL_ACMP0 << 16) /**< Shifted mode ACMP0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3575 #define PRS_CH_CTRL_SOURCESEL_ACMP1 (_PRS_CH_CTRL_SOURCESEL_ACMP1 << 16) /**< Shifted mode ACMP1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3576 #define PRS_CH_CTRL_SOURCESEL_DAC0 (_PRS_CH_CTRL_SOURCESEL_DAC0 << 16) /**< Shifted mode DAC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3577 #define PRS_CH_CTRL_SOURCESEL_ADC0 (_PRS_CH_CTRL_SOURCESEL_ADC0 << 16) /**< Shifted mode ADC0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3578 #define PRS_CH_CTRL_SOURCESEL_USART0 (_PRS_CH_CTRL_SOURCESEL_USART0 << 16) /**< Shifted mode USART0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3579 #define PRS_CH_CTRL_SOURCESEL_USART1 (_PRS_CH_CTRL_SOURCESEL_USART1 << 16) /**< Shifted mode USART1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3580 #define PRS_CH_CTRL_SOURCESEL_USART2 (_PRS_CH_CTRL_SOURCESEL_USART2 << 16) /**< Shifted mode USART2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3581 #define PRS_CH_CTRL_SOURCESEL_TIMER0 (_PRS_CH_CTRL_SOURCESEL_TIMER0 << 16) /**< Shifted mode TIMER0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3582 #define PRS_CH_CTRL_SOURCESEL_TIMER1 (_PRS_CH_CTRL_SOURCESEL_TIMER1 << 16) /**< Shifted mode TIMER1 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3583 #define PRS_CH_CTRL_SOURCESEL_TIMER2 (_PRS_CH_CTRL_SOURCESEL_TIMER2 << 16) /**< Shifted mode TIMER2 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3584 #define PRS_CH_CTRL_SOURCESEL_TIMER3 (_PRS_CH_CTRL_SOURCESEL_TIMER3 << 16) /**< Shifted mode TIMER3 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3585 #define PRS_CH_CTRL_SOURCESEL_RTC (_PRS_CH_CTRL_SOURCESEL_RTC << 16) /**< Shifted mode RTC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3586 #define PRS_CH_CTRL_SOURCESEL_GPIOL (_PRS_CH_CTRL_SOURCESEL_GPIOL << 16) /**< Shifted mode GPIOL for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3587 #define PRS_CH_CTRL_SOURCESEL_GPIOH (_PRS_CH_CTRL_SOURCESEL_GPIOH << 16) /**< Shifted mode GPIOH for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3588 #define PRS_CH_CTRL_SOURCESEL_LETIMER0 (_PRS_CH_CTRL_SOURCESEL_LETIMER0 << 16) /**< Shifted mode LETIMER0 for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3589 #define PRS_CH_CTRL_SOURCESEL_BURTC (_PRS_CH_CTRL_SOURCESEL_BURTC << 16) /**< Shifted mode BURTC for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3590 #define PRS_CH_CTRL_SOURCESEL_LESENSEL (_PRS_CH_CTRL_SOURCESEL_LESENSEL << 16) /**< Shifted mode LESENSEL for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3591 #define PRS_CH_CTRL_SOURCESEL_LESENSEH (_PRS_CH_CTRL_SOURCESEL_LESENSEH << 16) /**< Shifted mode LESENSEH for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3592 #define PRS_CH_CTRL_SOURCESEL_LESENSED (_PRS_CH_CTRL_SOURCESEL_LESENSED << 16) /**< Shifted mode LESENSED for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3593 #define _PRS_CH_CTRL_EDSEL_SHIFT 24 /**< Shift value for PRS_EDSEL */
AnnaBridge 171:3a7713b1edbc 3594 #define _PRS_CH_CTRL_EDSEL_MASK 0x3000000UL /**< Bit mask for PRS_EDSEL */
AnnaBridge 171:3a7713b1edbc 3595 #define _PRS_CH_CTRL_EDSEL_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3596 #define _PRS_CH_CTRL_EDSEL_OFF 0x00000000UL /**< Mode OFF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3597 #define _PRS_CH_CTRL_EDSEL_POSEDGE 0x00000001UL /**< Mode POSEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3598 #define _PRS_CH_CTRL_EDSEL_NEGEDGE 0x00000002UL /**< Mode NEGEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3599 #define _PRS_CH_CTRL_EDSEL_BOTHEDGES 0x00000003UL /**< Mode BOTHEDGES for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3600 #define PRS_CH_CTRL_EDSEL_DEFAULT (_PRS_CH_CTRL_EDSEL_DEFAULT << 24) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3601 #define PRS_CH_CTRL_EDSEL_OFF (_PRS_CH_CTRL_EDSEL_OFF << 24) /**< Shifted mode OFF for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3602 #define PRS_CH_CTRL_EDSEL_POSEDGE (_PRS_CH_CTRL_EDSEL_POSEDGE << 24) /**< Shifted mode POSEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3603 #define PRS_CH_CTRL_EDSEL_NEGEDGE (_PRS_CH_CTRL_EDSEL_NEGEDGE << 24) /**< Shifted mode NEGEDGE for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3604 #define PRS_CH_CTRL_EDSEL_BOTHEDGES (_PRS_CH_CTRL_EDSEL_BOTHEDGES << 24) /**< Shifted mode BOTHEDGES for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3605 #define PRS_CH_CTRL_ASYNC (0x1UL << 28) /**< Asynchronous reflex */
AnnaBridge 171:3a7713b1edbc 3606 #define _PRS_CH_CTRL_ASYNC_SHIFT 28 /**< Shift value for PRS_ASYNC */
AnnaBridge 171:3a7713b1edbc 3607 #define _PRS_CH_CTRL_ASYNC_MASK 0x10000000UL /**< Bit mask for PRS_ASYNC */
AnnaBridge 171:3a7713b1edbc 3608 #define _PRS_CH_CTRL_ASYNC_DEFAULT 0x00000000UL /**< Mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3609 #define PRS_CH_CTRL_ASYNC_DEFAULT (_PRS_CH_CTRL_ASYNC_DEFAULT << 28) /**< Shifted mode DEFAULT for PRS_CH_CTRL */
AnnaBridge 171:3a7713b1edbc 3610
AnnaBridge 171:3a7713b1edbc 3611 /** @} End of group EFM32GG842F1024_PRS */
AnnaBridge 171:3a7713b1edbc 3612
AnnaBridge 171:3a7713b1edbc 3613
AnnaBridge 171:3a7713b1edbc 3614
AnnaBridge 171:3a7713b1edbc 3615 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 3616 * @defgroup EFM32GG842F1024_UNLOCK EFM32GG842F1024 Unlock Codes
AnnaBridge 171:3a7713b1edbc 3617 * @{
AnnaBridge 171:3a7713b1edbc 3618 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3619 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
AnnaBridge 171:3a7713b1edbc 3620 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
AnnaBridge 171:3a7713b1edbc 3621 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
AnnaBridge 171:3a7713b1edbc 3622 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
AnnaBridge 171:3a7713b1edbc 3623 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
AnnaBridge 171:3a7713b1edbc 3624 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
AnnaBridge 171:3a7713b1edbc 3625
AnnaBridge 171:3a7713b1edbc 3626 /** @} End of group EFM32GG842F1024_UNLOCK */
AnnaBridge 171:3a7713b1edbc 3627
AnnaBridge 171:3a7713b1edbc 3628 /** @} End of group EFM32GG842F1024_BitFields */
AnnaBridge 171:3a7713b1edbc 3629
AnnaBridge 171:3a7713b1edbc 3630 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 3631 * @defgroup EFM32GG842F1024_Alternate_Function EFM32GG842F1024 Alternate Function
AnnaBridge 171:3a7713b1edbc 3632 * @{
AnnaBridge 171:3a7713b1edbc 3633 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3634
AnnaBridge 171:3a7713b1edbc 3635 #include "efm32gg_af_ports.h"
AnnaBridge 171:3a7713b1edbc 3636 #include "efm32gg_af_pins.h"
AnnaBridge 171:3a7713b1edbc 3637
AnnaBridge 171:3a7713b1edbc 3638 /** @} End of group EFM32GG842F1024_Alternate_Function */
AnnaBridge 171:3a7713b1edbc 3639
AnnaBridge 171:3a7713b1edbc 3640 /**************************************************************************//**
AnnaBridge 171:3a7713b1edbc 3641 * @brief Set the value of a bit field within a register.
AnnaBridge 171:3a7713b1edbc 3642 *
AnnaBridge 171:3a7713b1edbc 3643 * @param REG
AnnaBridge 171:3a7713b1edbc 3644 * The register to update
AnnaBridge 171:3a7713b1edbc 3645 * @param MASK
AnnaBridge 171:3a7713b1edbc 3646 * The mask for the bit field to update
AnnaBridge 171:3a7713b1edbc 3647 * @param VALUE
AnnaBridge 171:3a7713b1edbc 3648 * The value to write to the bit field
AnnaBridge 171:3a7713b1edbc 3649 * @param OFFSET
AnnaBridge 171:3a7713b1edbc 3650 * The number of bits that the field is offset within the register.
AnnaBridge 171:3a7713b1edbc 3651 * 0 (zero) means LSB.
AnnaBridge 171:3a7713b1edbc 3652 *****************************************************************************/
AnnaBridge 171:3a7713b1edbc 3653 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
AnnaBridge 171:3a7713b1edbc 3654 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
AnnaBridge 171:3a7713b1edbc 3655
AnnaBridge 171:3a7713b1edbc 3656 /** @} End of group EFM32GG842F1024 */
AnnaBridge 171:3a7713b1edbc 3657
AnnaBridge 171:3a7713b1edbc 3658 /** @} End of group Parts */
AnnaBridge 171:3a7713b1edbc 3659
AnnaBridge 171:3a7713b1edbc 3660 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 3661 }
AnnaBridge 171:3a7713b1edbc 3662 #endif
AnnaBridge 171:3a7713b1edbc 3663 #endif /* EFM32GG842F1024_H */