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TARGET_DISCO_L053C8/TOOLCHAIN_IAR/stm32l0xx_hal_adc.h@172:65be27845400, 2019-02-20 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Feb 20 20:53:29 2019 +0000
- Revision:
- 172:65be27845400
- Parent:
- 171:3a7713b1edbc
mbed library release version 165
Who changed what in which revision?
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AnnaBridge | 143:86740a56073b | 1 | /** |
AnnaBridge | 143:86740a56073b | 2 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 3 | * @file stm32l0xx_hal_adc.h |
AnnaBridge | 143:86740a56073b | 4 | * @author MCD Application Team |
AnnaBridge | 167:84c0a372a020 | 5 | * @brief Header file of ADC HAL module. |
AnnaBridge | 143:86740a56073b | 6 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 7 | * @attention |
AnnaBridge | 143:86740a56073b | 8 | * |
AnnaBridge | 143:86740a56073b | 9 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 143:86740a56073b | 10 | * |
AnnaBridge | 143:86740a56073b | 11 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 143:86740a56073b | 12 | * are permitted provided that the following conditions are met: |
AnnaBridge | 143:86740a56073b | 13 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 143:86740a56073b | 14 | * this list of conditions and the following disclaimer. |
AnnaBridge | 143:86740a56073b | 15 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 143:86740a56073b | 16 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 143:86740a56073b | 17 | * and/or other materials provided with the distribution. |
AnnaBridge | 143:86740a56073b | 18 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 143:86740a56073b | 19 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 143:86740a56073b | 20 | * without specific prior written permission. |
AnnaBridge | 143:86740a56073b | 21 | * |
AnnaBridge | 143:86740a56073b | 22 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 143:86740a56073b | 23 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 143:86740a56073b | 24 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 143:86740a56073b | 25 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 143:86740a56073b | 26 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 143:86740a56073b | 27 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 143:86740a56073b | 28 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 143:86740a56073b | 29 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 143:86740a56073b | 30 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 143:86740a56073b | 31 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 143:86740a56073b | 32 | * |
AnnaBridge | 143:86740a56073b | 33 | ****************************************************************************** |
AnnaBridge | 143:86740a56073b | 34 | */ |
AnnaBridge | 143:86740a56073b | 35 | |
AnnaBridge | 143:86740a56073b | 36 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 167:84c0a372a020 | 37 | #ifndef __STM32L0xx_HAL_ADC_H |
AnnaBridge | 167:84c0a372a020 | 38 | #define __STM32L0xx_HAL_ADC_H |
AnnaBridge | 143:86740a56073b | 39 | |
AnnaBridge | 143:86740a56073b | 40 | #ifdef __cplusplus |
AnnaBridge | 143:86740a56073b | 41 | extern "C" { |
AnnaBridge | 143:86740a56073b | 42 | #endif |
AnnaBridge | 143:86740a56073b | 43 | |
AnnaBridge | 143:86740a56073b | 44 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 45 | #include "stm32l0xx_hal_def.h" |
AnnaBridge | 167:84c0a372a020 | 46 | |
Anna Bridge |
169:a7c7b631e539 | 47 | /* Include low level driver */ |
Anna Bridge |
169:a7c7b631e539 | 48 | #include "stm32l0xx_ll_adc.h" |
Anna Bridge |
169:a7c7b631e539 | 49 | |
AnnaBridge | 143:86740a56073b | 50 | /** @addtogroup STM32L0xx_HAL_Driver |
AnnaBridge | 143:86740a56073b | 51 | * @{ |
AnnaBridge | 143:86740a56073b | 52 | */ |
AnnaBridge | 143:86740a56073b | 53 | |
AnnaBridge | 167:84c0a372a020 | 54 | /** @addtogroup ADC |
AnnaBridge | 143:86740a56073b | 55 | * @{ |
AnnaBridge | 167:84c0a372a020 | 56 | */ |
AnnaBridge | 143:86740a56073b | 57 | |
AnnaBridge | 167:84c0a372a020 | 58 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 59 | /** @defgroup ADC_Exported_Types ADC Exported Types |
AnnaBridge | 143:86740a56073b | 60 | * @{ |
AnnaBridge | 143:86740a56073b | 61 | */ |
AnnaBridge | 143:86740a56073b | 62 | |
AnnaBridge | 143:86740a56073b | 63 | /** |
AnnaBridge | 167:84c0a372a020 | 64 | * @brief ADC group regular oversampling structure definition |
AnnaBridge | 143:86740a56073b | 65 | */ |
AnnaBridge | 143:86740a56073b | 66 | typedef struct |
AnnaBridge | 143:86740a56073b | 67 | { |
AnnaBridge | 143:86740a56073b | 68 | uint32_t Ratio; /*!< Configures the oversampling ratio. |
AnnaBridge | 143:86740a56073b | 69 | This parameter can be a value of @ref ADC_Oversampling_Ratio */ |
AnnaBridge | 167:84c0a372a020 | 70 | |
AnnaBridge | 143:86740a56073b | 71 | uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. |
AnnaBridge | 143:86740a56073b | 72 | This parameter can be a value of @ref ADC_Right_Bit_Shift */ |
AnnaBridge | 167:84c0a372a020 | 73 | |
AnnaBridge | 167:84c0a372a020 | 74 | uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. |
AnnaBridge | 143:86740a56073b | 75 | This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */ |
AnnaBridge | 143:86740a56073b | 76 | }ADC_OversamplingTypeDef; |
AnnaBridge | 143:86740a56073b | 77 | |
AnnaBridge | 143:86740a56073b | 78 | /** |
AnnaBridge | 167:84c0a372a020 | 79 | * @brief Structure definition of ADC instance and ADC group regular. |
AnnaBridge | 167:84c0a372a020 | 80 | * @note Parameters of this structure are shared within 2 scopes: |
AnnaBridge | 167:84c0a372a020 | 81 | * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, |
AnnaBridge | 167:84c0a372a020 | 82 | * ScanConvMode, EOCSelection, LowPowerAutoWait. |
AnnaBridge | 167:84c0a372a020 | 83 | * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, |
AnnaBridge | 167:84c0a372a020 | 84 | * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. |
AnnaBridge | 167:84c0a372a020 | 85 | * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. |
AnnaBridge | 167:84c0a372a020 | 86 | * ADC state can be either: |
AnnaBridge | 167:84c0a372a020 | 87 | * - For all parameters: ADC disabled |
AnnaBridge | 167:84c0a372a020 | 88 | * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on group regular. |
AnnaBridge | 143:86740a56073b | 89 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
AnnaBridge | 167:84c0a372a020 | 90 | * without error reporting (as it can be the expected behavior in case of intended action to update another parameter |
AnnaBridge | 167:84c0a372a020 | 91 | * (which fulfills the ADC state condition) on the fly). |
AnnaBridge | 143:86740a56073b | 92 | */ |
AnnaBridge | 143:86740a56073b | 93 | typedef struct |
AnnaBridge | 143:86740a56073b | 94 | { |
AnnaBridge | 167:84c0a372a020 | 95 | uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from ADC dedicated HSI RC oscillator) and clock prescaler. |
AnnaBridge | 167:84c0a372a020 | 96 | This parameter can be a value of @ref ADC_ClockPrescaler. |
AnnaBridge | 167:84c0a372a020 | 97 | Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only |
AnnaBridge | 167:84c0a372a020 | 98 | if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC |
AnnaBridge | 167:84c0a372a020 | 99 | must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. |
AnnaBridge | 167:84c0a372a020 | 100 | Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. |
AnnaBridge | 167:84c0a372a020 | 101 | Note: This parameter can be modified only if the ADC is disabled. */ |
AnnaBridge | 167:84c0a372a020 | 102 | |
AnnaBridge | 167:84c0a372a020 | 103 | uint32_t Resolution; /*!< Configure the ADC resolution. |
AnnaBridge | 167:84c0a372a020 | 104 | This parameter can be a value of @ref ADC_Resolution */ |
AnnaBridge | 167:84c0a372a020 | 105 | |
AnnaBridge | 167:84c0a372a020 | 106 | uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). |
AnnaBridge | 167:84c0a372a020 | 107 | Refer to reference manual for alignments formats versus resolutions. |
AnnaBridge | 167:84c0a372a020 | 108 | This parameter can be a value of @ref ADC_Data_align */ |
AnnaBridge | 167:84c0a372a020 | 109 | |
AnnaBridge | 167:84c0a372a020 | 110 | uint32_t ScanConvMode; /*!< Configure the sequencer of regular group. |
AnnaBridge | 167:84c0a372a020 | 111 | This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. |
AnnaBridge | 167:84c0a372a020 | 112 | Sequencer is automatically enabled if several channels are set (sequencer cannot be disabled, as it can be the case on other STM32 devices): |
AnnaBridge | 167:84c0a372a020 | 113 | If only 1 channel is set: Conversion is performed in single mode. |
AnnaBridge | 167:84c0a372a020 | 114 | If several channels are set: Conversions are performed in sequence mode (ranks defined by each channel number: channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
AnnaBridge | 167:84c0a372a020 | 115 | Scan direction can be set to forward (from channel 0 to channel 18) or backward (from channel 18 to channel 0). |
AnnaBridge | 167:84c0a372a020 | 116 | This parameter can be a value of @ref ADC_Scan_mode */ |
AnnaBridge | 167:84c0a372a020 | 117 | |
AnnaBridge | 167:84c0a372a020 | 118 | uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. |
AnnaBridge | 167:84c0a372a020 | 119 | This parameter can be a value of @ref ADC_EOCSelection. */ |
AnnaBridge | 167:84c0a372a020 | 120 | |
AnnaBridge | 167:84c0a372a020 | 121 | uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous |
AnnaBridge | 167:84c0a372a020 | 122 | conversion (for ADC group regular) has been retrieved by user software, |
AnnaBridge | 167:84c0a372a020 | 123 | using function HAL_ADC_GetValue(). |
AnnaBridge | 167:84c0a372a020 | 124 | This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun |
AnnaBridge | 167:84c0a372a020 | 125 | for low frequency applications. |
AnnaBridge | 167:84c0a372a020 | 126 | This parameter can be set to ENABLE or DISABLE. |
AnnaBridge | 167:84c0a372a020 | 127 | Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag |
AnnaBridge | 167:84c0a372a020 | 128 | to free the IRQ vector sequencer. |
AnnaBridge | 167:84c0a372a020 | 129 | Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: |
AnnaBridge | 167:84c0a372a020 | 130 | use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. */ |
AnnaBridge | 167:84c0a372a020 | 131 | |
AnnaBridge | 167:84c0a372a020 | 132 | uint32_t LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling). |
AnnaBridge | 167:84c0a372a020 | 133 | This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait'). |
AnnaBridge | 167:84c0a372a020 | 134 | This parameter can be set to ENABLE or DISABLE. |
AnnaBridge | 167:84c0a372a020 | 135 | Note: If enabled, this feature also turns off the ADC dedicated 14 MHz RC oscillator (HSI14) */ |
AnnaBridge | 167:84c0a372a020 | 136 | |
AnnaBridge | 167:84c0a372a020 | 137 | uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, |
AnnaBridge | 167:84c0a372a020 | 138 | after the first ADC conversion start trigger occurred (software start or external trigger). |
AnnaBridge | 167:84c0a372a020 | 139 | This parameter can be set to ENABLE or DISABLE. */ |
AnnaBridge | 167:84c0a372a020 | 140 | |
AnnaBridge | 167:84c0a372a020 | 141 | uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence |
AnnaBridge | 167:84c0a372a020 | 142 | (main sequence subdivided in successive parts). |
AnnaBridge | 167:84c0a372a020 | 143 | Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. |
AnnaBridge | 167:84c0a372a020 | 144 | Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. |
AnnaBridge | 167:84c0a372a020 | 145 | This parameter can be set to ENABLE or DISABLE. |
AnnaBridge | 167:84c0a372a020 | 146 | Note: On this STM32 serie, ADC group regular number of discontinuous ranks increment is fixed to one-by-one. */ |
AnnaBridge | 167:84c0a372a020 | 147 | |
AnnaBridge | 167:84c0a372a020 | 148 | uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. |
AnnaBridge | 167:84c0a372a020 | 149 | If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. |
AnnaBridge | 167:84c0a372a020 | 150 | This parameter can be a value of @ref ADC_regular_external_trigger_source. |
AnnaBridge | 167:84c0a372a020 | 151 | Caution: external trigger source is common to all ADC instances. */ |
AnnaBridge | 167:84c0a372a020 | 152 | |
AnnaBridge | 167:84c0a372a020 | 153 | uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. |
AnnaBridge | 167:84c0a372a020 | 154 | If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. |
AnnaBridge | 167:84c0a372a020 | 155 | This parameter can be a value of @ref ADC_regular_external_trigger_edge */ |
AnnaBridge | 167:84c0a372a020 | 156 | |
AnnaBridge | 167:84c0a372a020 | 157 | uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) |
AnnaBridge | 167:84c0a372a020 | 158 | or in continuous mode (DMA transfer unlimited, whatever number of conversions). |
AnnaBridge | 167:84c0a372a020 | 159 | This parameter can be set to ENABLE or DISABLE. |
AnnaBridge | 167:84c0a372a020 | 160 | Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ |
AnnaBridge | 167:84c0a372a020 | 161 | |
AnnaBridge | 167:84c0a372a020 | 162 | uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). |
AnnaBridge | 167:84c0a372a020 | 163 | This parameter can be a value of @ref ADC_Overrun. |
AnnaBridge | 167:84c0a372a020 | 164 | Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear |
AnnaBridge | 167:84c0a372a020 | 165 | end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function |
AnnaBridge | 167:84c0a372a020 | 166 | HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). |
AnnaBridge | 167:84c0a372a020 | 167 | Note: Error reporting with respect to the conversion mode: |
AnnaBridge | 167:84c0a372a020 | 168 | - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data |
AnnaBridge | 167:84c0a372a020 | 169 | overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. |
AnnaBridge | 167:84c0a372a020 | 170 | - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ |
AnnaBridge | 167:84c0a372a020 | 171 | |
AnnaBridge | 167:84c0a372a020 | 172 | uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz, |
AnnaBridge | 167:84c0a372a020 | 173 | it is mandatory to first enable the Low Frequency Mode. |
AnnaBridge | 167:84c0a372a020 | 174 | This parameter can be set to ENABLE or DISABLE. |
AnnaBridge | 167:84c0a372a020 | 175 | Note: This parameter can be modified only if there is no conversion is ongoing. */ |
AnnaBridge | 167:84c0a372a020 | 176 | |
AnnaBridge | 167:84c0a372a020 | 177 | |
AnnaBridge | 167:84c0a372a020 | 178 | uint32_t SamplingTime; /*!< The sample time common to all channels. |
AnnaBridge | 167:84c0a372a020 | 179 | Unit: ADC clock cycles |
AnnaBridge | 143:86740a56073b | 180 | This parameter can be a value of @ref ADC_sampling_times |
AnnaBridge | 143:86740a56073b | 181 | Note: This parameter can be modified only if there is no conversion ongoing. */ |
AnnaBridge | 167:84c0a372a020 | 182 | |
AnnaBridge | 167:84c0a372a020 | 183 | uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. |
AnnaBridge | 167:84c0a372a020 | 184 | This parameter can be set to ENABLE or DISABLE. |
AnnaBridge | 167:84c0a372a020 | 185 | Note: This parameter can be modified only if there is no conversion is ongoing on ADC group regular. */ |
AnnaBridge | 167:84c0a372a020 | 186 | |
AnnaBridge | 167:84c0a372a020 | 187 | |
AnnaBridge | 167:84c0a372a020 | 188 | ADC_OversamplingTypeDef Oversample; /*!< Specify the Oversampling parameters |
AnnaBridge | 167:84c0a372a020 | 189 | Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ |
AnnaBridge | 143:86740a56073b | 190 | }ADC_InitTypeDef; |
AnnaBridge | 143:86740a56073b | 191 | |
AnnaBridge | 167:84c0a372a020 | 192 | /** |
AnnaBridge | 167:84c0a372a020 | 193 | * @brief Structure definition of ADC channel for regular group |
AnnaBridge | 167:84c0a372a020 | 194 | * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. |
AnnaBridge | 167:84c0a372a020 | 195 | * ADC state can be either: |
AnnaBridge | 167:84c0a372a020 | 196 | * - For all parameters: ADC disabled or enabled without conversion on going on regular group. |
AnnaBridge | 167:84c0a372a020 | 197 | * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed |
AnnaBridge | 167:84c0a372a020 | 198 | * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). |
AnnaBridge | 167:84c0a372a020 | 199 | */ |
AnnaBridge | 167:84c0a372a020 | 200 | typedef struct |
AnnaBridge | 167:84c0a372a020 | 201 | { |
AnnaBridge | 167:84c0a372a020 | 202 | uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. |
AnnaBridge | 167:84c0a372a020 | 203 | This parameter can be a value of @ref ADC_channels |
AnnaBridge | 167:84c0a372a020 | 204 | Note: Depending on devices, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ |
AnnaBridge | 167:84c0a372a020 | 205 | |
AnnaBridge | 167:84c0a372a020 | 206 | uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer. |
AnnaBridge | 167:84c0a372a020 | 207 | On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number |
AnnaBridge | 167:84c0a372a020 | 208 | (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). |
AnnaBridge | 167:84c0a372a020 | 209 | Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer. |
AnnaBridge | 167:84c0a372a020 | 210 | This parameter can be a value of @ref ADC_rank */ |
AnnaBridge | 167:84c0a372a020 | 211 | }ADC_ChannelConfTypeDef; |
AnnaBridge | 167:84c0a372a020 | 212 | |
AnnaBridge | 167:84c0a372a020 | 213 | /** |
AnnaBridge | 167:84c0a372a020 | 214 | * @brief Structure definition of ADC analog watchdog |
AnnaBridge | 167:84c0a372a020 | 215 | * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. |
AnnaBridge | 167:84c0a372a020 | 216 | * ADC state can be either: |
AnnaBridge | 167:84c0a372a020 | 217 | * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC group regular |
AnnaBridge | 167:84c0a372a020 | 218 | * - For parameters 'HighThreshold' and 'LowThreshold': ADC enabled with conversion on going on regular group (AWD thresholds can be modify on the fly while ADC conversion is on going) |
AnnaBridge | 167:84c0a372a020 | 219 | */ |
AnnaBridge | 167:84c0a372a020 | 220 | typedef struct |
AnnaBridge | 167:84c0a372a020 | 221 | { |
AnnaBridge | 167:84c0a372a020 | 222 | uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all channels. |
AnnaBridge | 167:84c0a372a020 | 223 | This parameter can be a value of @ref ADC_analog_watchdog_mode */ |
AnnaBridge | 167:84c0a372a020 | 224 | |
AnnaBridge | 167:84c0a372a020 | 225 | uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. |
AnnaBridge | 167:84c0a372a020 | 226 | This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode) |
AnnaBridge | 167:84c0a372a020 | 227 | This parameter can be a value of @ref ADC_channels */ |
AnnaBridge | 167:84c0a372a020 | 228 | |
AnnaBridge | 167:84c0a372a020 | 229 | uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. |
AnnaBridge | 167:84c0a372a020 | 230 | This parameter can be set to ENABLE or DISABLE */ |
AnnaBridge | 167:84c0a372a020 | 231 | uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
AnnaBridge | 167:84c0a372a020 | 232 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
AnnaBridge | 167:84c0a372a020 | 233 | this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
AnnaBridge | 167:84c0a372a020 | 234 | |
AnnaBridge | 167:84c0a372a020 | 235 | uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value. |
AnnaBridge | 167:84c0a372a020 | 236 | Depending of ADC resolution selected (12, 10, 8 or 6 bits), |
AnnaBridge | 167:84c0a372a020 | 237 | this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */ |
AnnaBridge | 167:84c0a372a020 | 238 | }ADC_AnalogWDGConfTypeDef; |
AnnaBridge | 167:84c0a372a020 | 239 | |
AnnaBridge | 167:84c0a372a020 | 240 | /** |
AnnaBridge | 167:84c0a372a020 | 241 | * @brief HAL ADC state machine: ADC states definition (bitfields) |
AnnaBridge | 167:84c0a372a020 | 242 | * @note ADC state machine is managed by bitfields, state must be compared |
AnnaBridge | 167:84c0a372a020 | 243 | * with bit by bit. |
AnnaBridge | 167:84c0a372a020 | 244 | * For example: |
AnnaBridge | 167:84c0a372a020 | 245 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " |
AnnaBridge | 167:84c0a372a020 | 246 | * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " |
AnnaBridge | 167:84c0a372a020 | 247 | */ |
AnnaBridge | 167:84c0a372a020 | 248 | /* States of ADC global scope */ |
AnnaBridge | 167:84c0a372a020 | 249 | #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */ |
AnnaBridge | 167:84c0a372a020 | 250 | #define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */ |
AnnaBridge | 167:84c0a372a020 | 251 | #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy due to an internal process (initialization, calibration) */ |
AnnaBridge | 167:84c0a372a020 | 252 | #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */ |
AnnaBridge | 167:84c0a372a020 | 253 | |
AnnaBridge | 167:84c0a372a020 | 254 | /* States of ADC errors */ |
AnnaBridge | 167:84c0a372a020 | 255 | #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */ |
AnnaBridge | 167:84c0a372a020 | 256 | #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */ |
AnnaBridge | 167:84c0a372a020 | 257 | #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */ |
AnnaBridge | 167:84c0a372a020 | 258 | |
AnnaBridge | 167:84c0a372a020 | 259 | /* States of ADC group regular */ |
AnnaBridge | 167:84c0a372a020 | 260 | #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, |
AnnaBridge | 167:84c0a372a020 | 261 | external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ |
AnnaBridge | 167:84c0a372a020 | 262 | #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */ |
AnnaBridge | 167:84c0a372a020 | 263 | #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */ |
AnnaBridge | 167:84c0a372a020 | 264 | #define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ |
AnnaBridge | 167:84c0a372a020 | 265 | |
AnnaBridge | 167:84c0a372a020 | 266 | /* States of ADC group injected */ |
AnnaBridge | 167:84c0a372a020 | 267 | #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< Not available on this STM32 serie: A conversion on group injected is ongoing or can occur (either by auto-injection mode, |
AnnaBridge | 167:84c0a372a020 | 268 | external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ |
AnnaBridge | 167:84c0a372a020 | 269 | #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Not available on this STM32 serie: Conversion data available on group injected */ |
AnnaBridge | 167:84c0a372a020 | 270 | #define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000) /*!< Not available on this STM32 serie: Injected queue overflow occurrence */ |
AnnaBridge | 167:84c0a372a020 | 271 | |
AnnaBridge | 167:84c0a372a020 | 272 | /* States of ADC analog watchdogs */ |
AnnaBridge | 167:84c0a372a020 | 273 | #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ |
AnnaBridge | 167:84c0a372a020 | 274 | #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 2 */ |
AnnaBridge | 167:84c0a372a020 | 275 | #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on this STM32 serie: Out-of-window occurrence of ADC analog watchdog 3 */ |
AnnaBridge | 167:84c0a372a020 | 276 | |
AnnaBridge | 167:84c0a372a020 | 277 | /* States of ADC multi-mode */ |
AnnaBridge | 167:84c0a372a020 | 278 | #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on this STM32 serie: ADC in multimode slave state, controlled by another ADC master (when feature available) */ |
AnnaBridge | 167:84c0a372a020 | 279 | |
AnnaBridge | 167:84c0a372a020 | 280 | |
AnnaBridge | 167:84c0a372a020 | 281 | |
AnnaBridge | 143:86740a56073b | 282 | /** |
AnnaBridge | 167:84c0a372a020 | 283 | * @brief ADC handle Structure definition |
AnnaBridge | 167:84c0a372a020 | 284 | */ |
AnnaBridge | 143:86740a56073b | 285 | typedef struct |
AnnaBridge | 143:86740a56073b | 286 | { |
AnnaBridge | 143:86740a56073b | 287 | ADC_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 143:86740a56073b | 288 | |
AnnaBridge | 143:86740a56073b | 289 | ADC_InitTypeDef Init; /*!< ADC required parameters */ |
AnnaBridge | 143:86740a56073b | 290 | |
AnnaBridge | 143:86740a56073b | 291 | DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ |
AnnaBridge | 143:86740a56073b | 292 | |
AnnaBridge | 143:86740a56073b | 293 | HAL_LockTypeDef Lock; /*!< ADC locking object */ |
AnnaBridge | 143:86740a56073b | 294 | |
AnnaBridge | 143:86740a56073b | 295 | __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ |
AnnaBridge | 143:86740a56073b | 296 | |
AnnaBridge | 143:86740a56073b | 297 | __IO uint32_t ErrorCode; /*!< ADC Error code */ |
AnnaBridge | 143:86740a56073b | 298 | }ADC_HandleTypeDef; |
AnnaBridge | 143:86740a56073b | 299 | /** |
AnnaBridge | 143:86740a56073b | 300 | * @} |
AnnaBridge | 143:86740a56073b | 301 | */ |
AnnaBridge | 143:86740a56073b | 302 | |
AnnaBridge | 143:86740a56073b | 303 | |
AnnaBridge | 143:86740a56073b | 304 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 143:86740a56073b | 305 | |
AnnaBridge | 143:86740a56073b | 306 | /** @defgroup ADC_Exported_Constants ADC Exported Constants |
AnnaBridge | 143:86740a56073b | 307 | * @{ |
AnnaBridge | 143:86740a56073b | 308 | */ |
AnnaBridge | 143:86740a56073b | 309 | |
AnnaBridge | 143:86740a56073b | 310 | /** @defgroup ADC_Error_Code ADC Error Code |
AnnaBridge | 143:86740a56073b | 311 | * @{ |
AnnaBridge | 167:84c0a372a020 | 312 | */ |
AnnaBridge | 167:84c0a372a020 | 313 | #define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */ |
AnnaBridge | 167:84c0a372a020 | 314 | #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error (problem of clocking, |
AnnaBridge | 167:84c0a372a020 | 315 | enable/disable, erroneous state, ...) */ |
AnnaBridge | 167:84c0a372a020 | 316 | #define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */ |
AnnaBridge | 167:84c0a372a020 | 317 | #define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */ |
AnnaBridge | 143:86740a56073b | 318 | /** |
AnnaBridge | 143:86740a56073b | 319 | * @} |
AnnaBridge | 167:84c0a372a020 | 320 | */ |
AnnaBridge | 143:86740a56073b | 321 | |
AnnaBridge | 143:86740a56073b | 322 | /** @defgroup ADC_TimeOut_Values ADC TimeOut Values |
AnnaBridge | 143:86740a56073b | 323 | * @{ |
AnnaBridge | 167:84c0a372a020 | 324 | */ |
AnnaBridge | 143:86740a56073b | 325 | |
AnnaBridge | 143:86740a56073b | 326 | /* Fixed timeout values for ADC calibration, enable settling time, disable */ |
AnnaBridge | 143:86740a56073b | 327 | /* settling time. */ |
AnnaBridge | 143:86740a56073b | 328 | /* Values defined to be higher than worst cases: low clocks freq, */ |
AnnaBridge | 143:86740a56073b | 329 | /* maximum prescalers. */ |
AnnaBridge | 143:86740a56073b | 330 | /* Unit: ms */ |
AnnaBridge | 143:86740a56073b | 331 | #define ADC_ENABLE_TIMEOUT 10U |
AnnaBridge | 143:86740a56073b | 332 | #define ADC_DISABLE_TIMEOUT 10U |
AnnaBridge | 143:86740a56073b | 333 | #define ADC_STOP_CONVERSION_TIMEOUT 10U |
AnnaBridge | 143:86740a56073b | 334 | |
AnnaBridge | 143:86740a56073b | 335 | /* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */ |
AnnaBridge | 143:86740a56073b | 336 | /* the minimum number of CPU cycles to fulfill this delay */ |
AnnaBridge | 143:86740a56073b | 337 | #define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U |
AnnaBridge | 143:86740a56073b | 338 | /** |
AnnaBridge | 143:86740a56073b | 339 | * @} |
AnnaBridge | 143:86740a56073b | 340 | */ |
AnnaBridge | 143:86740a56073b | 341 | |
AnnaBridge | 143:86740a56073b | 342 | /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler |
AnnaBridge | 143:86740a56073b | 343 | * @{ |
AnnaBridge | 143:86740a56073b | 344 | */ |
AnnaBridge | 143:86740a56073b | 345 | #define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /*!< ADC Asynchronous clock mode divided by 1 */ |
AnnaBridge | 143:86740a56073b | 346 | #define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 347 | #define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 348 | #define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 349 | #define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 350 | #define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 351 | #define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 352 | #define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 353 | #define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 354 | #define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 355 | #define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 356 | #define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC Asynchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 357 | |
AnnaBridge | 143:86740a56073b | 358 | #define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1 |
AnnaBridge | 143:86740a56073b | 359 | This configuration must be enabled only if PCLK has a 50% |
AnnaBridge | 143:86740a56073b | 360 | duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock |
AnnaBridge | 143:86740a56073b | 361 | must by 50% duty cycle)*/ |
AnnaBridge | 143:86740a56073b | 362 | #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /*!< Synchronous clock mode divided by 2 */ |
AnnaBridge | 143:86740a56073b | 363 | #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /*!< Synchronous clock mode divided by 4 */ |
AnnaBridge | 143:86740a56073b | 364 | |
AnnaBridge | 143:86740a56073b | 365 | /** |
AnnaBridge | 143:86740a56073b | 366 | * @} |
AnnaBridge | 143:86740a56073b | 367 | */ |
AnnaBridge | 143:86740a56073b | 368 | |
AnnaBridge | 143:86740a56073b | 369 | /** @defgroup ADC_Resolution ADC Resolution |
AnnaBridge | 143:86740a56073b | 370 | * @{ |
AnnaBridge | 167:84c0a372a020 | 371 | */ |
AnnaBridge | 167:84c0a372a020 | 372 | #define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /*!< ADC 12-bit resolution */ |
AnnaBridge | 167:84c0a372a020 | 373 | #define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /*!< ADC 10-bit resolution */ |
AnnaBridge | 167:84c0a372a020 | 374 | #define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /*!< ADC 8-bit resolution */ |
AnnaBridge | 167:84c0a372a020 | 375 | #define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /*!< ADC 6-bit resolution */ |
AnnaBridge | 143:86740a56073b | 376 | /** |
AnnaBridge | 143:86740a56073b | 377 | * @} |
AnnaBridge | 167:84c0a372a020 | 378 | */ |
AnnaBridge | 143:86740a56073b | 379 | |
AnnaBridge | 167:84c0a372a020 | 380 | /** @defgroup ADC_Data_align ADC conversion data alignment |
AnnaBridge | 143:86740a56073b | 381 | * @{ |
AnnaBridge | 167:84c0a372a020 | 382 | */ |
AnnaBridge | 143:86740a56073b | 383 | #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) |
AnnaBridge | 143:86740a56073b | 384 | #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN) |
AnnaBridge | 143:86740a56073b | 385 | /** |
AnnaBridge | 143:86740a56073b | 386 | * @} |
AnnaBridge | 167:84c0a372a020 | 387 | */ |
AnnaBridge | 143:86740a56073b | 388 | |
AnnaBridge | 167:84c0a372a020 | 389 | /** @defgroup ADC_regular_external_trigger_edge ADC External Trigger Source Edge for Regular Group |
AnnaBridge | 143:86740a56073b | 390 | * @{ |
AnnaBridge | 167:84c0a372a020 | 391 | */ |
AnnaBridge | 143:86740a56073b | 392 | #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U) |
AnnaBridge | 143:86740a56073b | 393 | #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0) |
AnnaBridge | 143:86740a56073b | 394 | #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1) |
AnnaBridge | 143:86740a56073b | 395 | #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN) |
AnnaBridge | 143:86740a56073b | 396 | /** |
AnnaBridge | 143:86740a56073b | 397 | * @} |
AnnaBridge | 143:86740a56073b | 398 | */ |
AnnaBridge | 143:86740a56073b | 399 | |
AnnaBridge | 143:86740a56073b | 400 | /** @defgroup ADC_EOCSelection ADC EOC Selection |
AnnaBridge | 143:86740a56073b | 401 | * @{ |
AnnaBridge | 143:86740a56073b | 402 | */ |
AnnaBridge | 143:86740a56073b | 403 | #define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC) |
AnnaBridge | 143:86740a56073b | 404 | #define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS) |
AnnaBridge | 143:86740a56073b | 405 | #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS)) /*!< reserved for future use */ |
AnnaBridge | 143:86740a56073b | 406 | /** |
AnnaBridge | 143:86740a56073b | 407 | * @} |
AnnaBridge | 143:86740a56073b | 408 | */ |
AnnaBridge | 143:86740a56073b | 409 | |
AnnaBridge | 143:86740a56073b | 410 | /** @defgroup ADC_Overrun ADC Overrun |
AnnaBridge | 143:86740a56073b | 411 | * @{ |
AnnaBridge | 143:86740a56073b | 412 | */ |
AnnaBridge | 143:86740a56073b | 413 | #define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U) |
AnnaBridge | 143:86740a56073b | 414 | #define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD) |
AnnaBridge | 143:86740a56073b | 415 | /** |
AnnaBridge | 143:86740a56073b | 416 | * @} |
AnnaBridge | 167:84c0a372a020 | 417 | */ |
AnnaBridge | 143:86740a56073b | 418 | |
AnnaBridge | 143:86740a56073b | 419 | |
AnnaBridge | 143:86740a56073b | 420 | /** @defgroup ADC_rank ADC rank |
AnnaBridge | 143:86740a56073b | 421 | * @{ |
AnnaBridge | 167:84c0a372a020 | 422 | */ |
AnnaBridge | 143:86740a56073b | 423 | #define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /*!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ |
AnnaBridge | 143:86740a56073b | 424 | #define ADC_RANK_NONE ((uint32_t)0x00001001U) /*!< Disable the selected rank (selected channel) from sequencer */ |
AnnaBridge | 143:86740a56073b | 425 | /** |
AnnaBridge | 143:86740a56073b | 426 | * @} |
AnnaBridge | 143:86740a56073b | 427 | */ |
AnnaBridge | 143:86740a56073b | 428 | |
AnnaBridge | 143:86740a56073b | 429 | |
AnnaBridge | 143:86740a56073b | 430 | /** @defgroup ADC_channels ADC_Channels |
AnnaBridge | 143:86740a56073b | 431 | * @{ |
AnnaBridge | 143:86740a56073b | 432 | */ |
AnnaBridge | 143:86740a56073b | 433 | #define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0)) |
AnnaBridge | 143:86740a56073b | 434 | #define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) | ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 435 | #define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) | ADC_CFGR1_AWDCH_1) |
AnnaBridge | 143:86740a56073b | 436 | #define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 437 | #define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)| ADC_CFGR1_AWDCH_2) |
AnnaBridge | 143:86740a56073b | 438 | #define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 439 | #define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) |
AnnaBridge | 143:86740a56073b | 440 | #define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 441 | #define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)| ADC_CFGR1_AWDCH_3) |
AnnaBridge | 143:86740a56073b | 442 | #define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 443 | #define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1) |
AnnaBridge | 143:86740a56073b | 444 | #define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 445 | #define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2) |
AnnaBridge | 143:86740a56073b | 446 | #define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 447 | #define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1) |
AnnaBridge | 143:86740a56073b | 448 | #define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)| ADC_CFGR1_AWDCH_3| ADC_CFGR1_AWDCH_2| ADC_CFGR1_AWDCH_1| ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 449 | #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) |
AnnaBridge | 143:86740a56073b | 450 | #define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)| ADC_CFGR1_AWDCH_4) |
AnnaBridge | 143:86740a56073b | 451 | #endif |
AnnaBridge | 143:86740a56073b | 452 | #define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_0) |
AnnaBridge | 143:86740a56073b | 453 | #define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)| ADC_CFGR1_AWDCH_4| ADC_CFGR1_AWDCH_1) |
AnnaBridge | 143:86740a56073b | 454 | |
AnnaBridge | 143:86740a56073b | 455 | /* Internal channels */ |
AnnaBridge | 143:86740a56073b | 456 | #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) |
AnnaBridge | 143:86740a56073b | 457 | #define ADC_CHANNEL_VLCD ADC_CHANNEL_16 |
AnnaBridge | 143:86740a56073b | 458 | #endif |
AnnaBridge | 143:86740a56073b | 459 | #define ADC_CHANNEL_VREFINT ADC_CHANNEL_17 |
AnnaBridge | 143:86740a56073b | 460 | #define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18 |
AnnaBridge | 143:86740a56073b | 461 | /** |
AnnaBridge | 143:86740a56073b | 462 | * @} |
AnnaBridge | 143:86740a56073b | 463 | */ |
AnnaBridge | 143:86740a56073b | 464 | |
AnnaBridge | 143:86740a56073b | 465 | /** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks |
AnnaBridge | 143:86740a56073b | 466 | * @{ |
AnnaBridge | 143:86740a56073b | 467 | */ |
AnnaBridge | 143:86740a56073b | 468 | #define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU) |
AnnaBridge | 143:86740a56073b | 469 | #define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U) |
AnnaBridge | 143:86740a56073b | 470 | /** |
AnnaBridge | 143:86740a56073b | 471 | * @} |
AnnaBridge | 143:86740a56073b | 472 | */ |
AnnaBridge | 143:86740a56073b | 473 | |
AnnaBridge | 143:86740a56073b | 474 | /** @defgroup ADC_sampling_times ADC Sampling Cycles |
AnnaBridge | 143:86740a56073b | 475 | * @{ |
AnnaBridge | 143:86740a56073b | 476 | */ |
AnnaBridge | 143:86740a56073b | 477 | #define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /*!< ADC sampling time 1.5 cycle */ |
AnnaBridge | 167:84c0a372a020 | 478 | #define ADC_SAMPLETIME_3CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /*!< ADC sampling time 3.5 CYCLES */ |
AnnaBridge | 167:84c0a372a020 | 479 | #define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /*!< ADC sampling time 7.5 CYCLES */ |
AnnaBridge | 167:84c0a372a020 | 480 | #define ADC_SAMPLETIME_12CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 12.5 CYCLES */ |
AnnaBridge | 167:84c0a372a020 | 481 | #define ADC_SAMPLETIME_19CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /*!< ADC sampling time 19.5 CYCLES */ |
AnnaBridge | 167:84c0a372a020 | 482 | #define ADC_SAMPLETIME_39CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_0)) /*!< ADC sampling time 39.5 CYCLES */ |
AnnaBridge | 167:84c0a372a020 | 483 | #define ADC_SAMPLETIME_79CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 | ADC_SMPR_SMPR_1)) /*!< ADC sampling time 79.5 CYCLES */ |
AnnaBridge | 167:84c0a372a020 | 484 | #define ADC_SAMPLETIME_160CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /*!< ADC sampling time 160.5 CYCLES */ |
AnnaBridge | 143:86740a56073b | 485 | /** |
AnnaBridge | 143:86740a56073b | 486 | * @} |
AnnaBridge | 143:86740a56073b | 487 | */ |
AnnaBridge | 143:86740a56073b | 488 | |
AnnaBridge | 143:86740a56073b | 489 | /** @defgroup ADC_Scan_mode ADC Scan mode |
AnnaBridge | 143:86740a56073b | 490 | * @{ |
AnnaBridge | 143:86740a56073b | 491 | */ |
AnnaBridge | 143:86740a56073b | 492 | /* Note: Scan mode values must be compatible with other STM32 devices having */ |
AnnaBridge | 143:86740a56073b | 493 | /* a configurable sequencer. */ |
AnnaBridge | 143:86740a56073b | 494 | /* Scan direction setting values are defined by taking in account */ |
AnnaBridge | 143:86740a56073b | 495 | /* already defined values for other STM32 devices: */ |
AnnaBridge | 143:86740a56073b | 496 | /* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */ |
AnnaBridge | 143:86740a56073b | 497 | /* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */ |
AnnaBridge | 143:86740a56073b | 498 | /* Scan direction forward is considered as default setting equivalent */ |
AnnaBridge | 143:86740a56073b | 499 | /* to scan enable. */ |
AnnaBridge | 143:86740a56073b | 500 | /* Scan direction backward is considered as additional setting. */ |
AnnaBridge | 143:86740a56073b | 501 | /* In case of migration from another STM32 device, the user will be */ |
AnnaBridge | 143:86740a56073b | 502 | /* warned of change of setting choices with assert check. */ |
AnnaBridge | 143:86740a56073b | 503 | #define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /*!< Scan direction forward: from channel 0 to channel 18 */ |
AnnaBridge | 143:86740a56073b | 504 | #define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /*!< Scan direction backward: from channel 18 to channel 0 */ |
AnnaBridge | 143:86740a56073b | 505 | |
AnnaBridge | 143:86740a56073b | 506 | #define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */ |
AnnaBridge | 143:86740a56073b | 507 | /** |
AnnaBridge | 143:86740a56073b | 508 | * @} |
AnnaBridge | 143:86740a56073b | 509 | */ |
AnnaBridge | 143:86740a56073b | 510 | |
AnnaBridge | 143:86740a56073b | 511 | /** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio |
AnnaBridge | 143:86740a56073b | 512 | * @{ |
AnnaBridge | 143:86740a56073b | 513 | */ |
AnnaBridge | 143:86740a56073b | 514 | |
AnnaBridge | 143:86740a56073b | 515 | #define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /*!< ADC Oversampling ratio 2x */ |
AnnaBridge | 143:86740a56073b | 516 | #define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /*!< ADC Oversampling ratio 4x */ |
AnnaBridge | 143:86740a56073b | 517 | #define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /*!< ADC Oversampling ratio 8x */ |
AnnaBridge | 143:86740a56073b | 518 | #define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /*!< ADC Oversampling ratio 16x */ |
AnnaBridge | 143:86740a56073b | 519 | #define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /*!< ADC Oversampling ratio 32x */ |
AnnaBridge | 143:86740a56073b | 520 | #define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /*!< ADC Oversampling ratio 64x */ |
AnnaBridge | 143:86740a56073b | 521 | #define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /*!< ADC Oversampling ratio 128x */ |
AnnaBridge | 143:86740a56073b | 522 | #define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /*!< ADC Oversampling ratio 256x */ |
AnnaBridge | 143:86740a56073b | 523 | /** |
AnnaBridge | 143:86740a56073b | 524 | * @} |
AnnaBridge | 143:86740a56073b | 525 | */ |
AnnaBridge | 143:86740a56073b | 526 | |
AnnaBridge | 143:86740a56073b | 527 | /** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift |
AnnaBridge | 143:86740a56073b | 528 | * @{ |
AnnaBridge | 143:86740a56073b | 529 | */ |
AnnaBridge | 143:86740a56073b | 530 | #define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 531 | #define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /*!< ADC 1 bit shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 532 | #define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /*!< ADC 2 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 533 | #define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /*!< ADC 3 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 534 | #define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /*!< ADC 4 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 535 | #define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /*!< ADC 5 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 536 | #define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /*!< ADC 6 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 537 | #define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /*!< ADC 7 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 538 | #define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /*!< ADC 8 bits shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 539 | /** |
AnnaBridge | 143:86740a56073b | 540 | * @} |
AnnaBridge | 143:86740a56073b | 541 | */ |
AnnaBridge | 143:86740a56073b | 542 | |
AnnaBridge | 143:86740a56073b | 543 | /** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode |
AnnaBridge | 143:86740a56073b | 544 | * @{ |
AnnaBridge | 143:86740a56073b | 545 | */ |
AnnaBridge | 143:86740a56073b | 546 | #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /*!< ADC No bit shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 547 | #define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /*!< ADC No bit shift for oversampling */ |
AnnaBridge | 143:86740a56073b | 548 | /** |
AnnaBridge | 143:86740a56073b | 549 | * @} |
AnnaBridge | 143:86740a56073b | 550 | */ |
AnnaBridge | 143:86740a56073b | 551 | |
AnnaBridge | 143:86740a56073b | 552 | /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode |
AnnaBridge | 143:86740a56073b | 553 | * @{ |
AnnaBridge | 143:86740a56073b | 554 | */ |
AnnaBridge | 143:86740a56073b | 555 | #define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U) |
AnnaBridge | 143:86740a56073b | 556 | #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)) |
AnnaBridge | 143:86740a56073b | 557 | #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN) |
AnnaBridge | 143:86740a56073b | 558 | /** |
AnnaBridge | 143:86740a56073b | 559 | * @} |
AnnaBridge | 143:86740a56073b | 560 | */ |
AnnaBridge | 143:86740a56073b | 561 | |
AnnaBridge | 143:86740a56073b | 562 | /** @defgroup ADC_conversion_type ADC Conversion Group |
AnnaBridge | 143:86740a56073b | 563 | * @{ |
AnnaBridge | 143:86740a56073b | 564 | */ |
AnnaBridge | 143:86740a56073b | 565 | #define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_EOS)) |
AnnaBridge | 143:86740a56073b | 566 | /** |
AnnaBridge | 143:86740a56073b | 567 | * @} |
AnnaBridge | 143:86740a56073b | 568 | */ |
AnnaBridge | 143:86740a56073b | 569 | |
AnnaBridge | 143:86740a56073b | 570 | /** @defgroup ADC_Event_type ADC Event |
AnnaBridge | 143:86740a56073b | 571 | * @{ |
AnnaBridge | 167:84c0a372a020 | 572 | */ |
AnnaBridge | 143:86740a56073b | 573 | #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD) |
AnnaBridge | 143:86740a56073b | 574 | #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR) |
AnnaBridge | 143:86740a56073b | 575 | /** |
AnnaBridge | 143:86740a56073b | 576 | * @} |
AnnaBridge | 143:86740a56073b | 577 | */ |
AnnaBridge | 143:86740a56073b | 578 | |
AnnaBridge | 143:86740a56073b | 579 | /** @defgroup ADC_interrupts_definition ADC Interrupts Definition |
AnnaBridge | 143:86740a56073b | 580 | * @{ |
AnnaBridge | 143:86740a56073b | 581 | */ |
AnnaBridge | 143:86740a56073b | 582 | #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready (ADRDY) interrupt source */ |
AnnaBridge | 143:86740a56073b | 583 | #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of Sampling interrupt source */ |
AnnaBridge | 143:86740a56073b | 584 | #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of Regular Conversion interrupt source */ |
AnnaBridge | 143:86740a56073b | 585 | #define ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC End of Regular sequence of Conversions interrupt source */ |
AnnaBridge | 143:86740a56073b | 586 | #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ |
AnnaBridge | 143:86740a56073b | 587 | #define ADC_IT_AWD ADC_IER_AWDIE /*!< ADC Analog watchdog 1 interrupt source */ |
AnnaBridge | 143:86740a56073b | 588 | #define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ |
AnnaBridge | 143:86740a56073b | 589 | /** |
AnnaBridge | 143:86740a56073b | 590 | * @} |
AnnaBridge | 167:84c0a372a020 | 591 | */ |
AnnaBridge | 143:86740a56073b | 592 | |
AnnaBridge | 167:84c0a372a020 | 593 | /** @defgroup ADC_flags_definition ADC flags definition |
AnnaBridge | 143:86740a56073b | 594 | * @{ |
AnnaBridge | 143:86740a56073b | 595 | */ |
AnnaBridge | 167:84c0a372a020 | 596 | #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ |
AnnaBridge | 143:86740a56073b | 597 | #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ |
AnnaBridge | 143:86740a56073b | 598 | #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ |
AnnaBridge | 143:86740a56073b | 599 | #define ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC End of Regular sequence of Conversions flag */ |
AnnaBridge | 143:86740a56073b | 600 | #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ |
AnnaBridge | 143:86740a56073b | 601 | #define ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC Analog watchdog flag */ |
AnnaBridge | 143:86740a56073b | 602 | #define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC Enf Of Calibration flag */ |
AnnaBridge | 143:86740a56073b | 603 | |
AnnaBridge | 143:86740a56073b | 604 | |
AnnaBridge | 143:86740a56073b | 605 | #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ |
AnnaBridge | 143:86740a56073b | 606 | ADC_FLAG_OVR | ADC_FLAG_AWD | ADC_FLAG_EOCAL) |
AnnaBridge | 143:86740a56073b | 607 | /** |
AnnaBridge | 143:86740a56073b | 608 | * @} |
AnnaBridge | 143:86740a56073b | 609 | */ |
AnnaBridge | 143:86740a56073b | 610 | |
AnnaBridge | 143:86740a56073b | 611 | /** |
AnnaBridge | 143:86740a56073b | 612 | * @} |
AnnaBridge | 143:86740a56073b | 613 | */ |
AnnaBridge | 167:84c0a372a020 | 614 | |
AnnaBridge | 167:84c0a372a020 | 615 | |
AnnaBridge | 143:86740a56073b | 616 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 167:84c0a372a020 | 617 | |
AnnaBridge | 167:84c0a372a020 | 618 | /** @defgroup ADC_Exported_Macros ADC Exported Macros |
AnnaBridge | 143:86740a56073b | 619 | * @{ |
AnnaBridge | 143:86740a56073b | 620 | */ |
AnnaBridge | 143:86740a56073b | 621 | /** @brief Reset ADC handle state |
AnnaBridge | 143:86740a56073b | 622 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 623 | * @retval None |
AnnaBridge | 143:86740a56073b | 624 | */ |
AnnaBridge | 143:86740a56073b | 625 | #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) |
AnnaBridge | 143:86740a56073b | 626 | |
AnnaBridge | 143:86740a56073b | 627 | /** |
AnnaBridge | 143:86740a56073b | 628 | * @brief Enable the ADC peripheral |
AnnaBridge | 143:86740a56073b | 629 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 630 | * @retval None |
AnnaBridge | 143:86740a56073b | 631 | */ |
AnnaBridge | 143:86740a56073b | 632 | #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= ADC_CR_ADEN) |
AnnaBridge | 143:86740a56073b | 633 | |
AnnaBridge | 143:86740a56073b | 634 | /** |
AnnaBridge | 143:86740a56073b | 635 | * @brief Verification of hardware constraints before ADC can be enabled |
AnnaBridge | 143:86740a56073b | 636 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 637 | * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled) |
AnnaBridge | 143:86740a56073b | 638 | */ |
AnnaBridge | 143:86740a56073b | 639 | #define ADC_ENABLING_CONDITIONS(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 640 | (( ( ((__HANDLE__)->Instance->CR) & \ |
AnnaBridge | 143:86740a56073b | 641 | (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | \ |
AnnaBridge | 143:86740a56073b | 642 | ADC_CR_ADDIS | ADC_CR_ADEN ) \ |
AnnaBridge | 143:86740a56073b | 643 | ) == RESET \ |
AnnaBridge | 143:86740a56073b | 644 | ) ? SET : RESET) |
AnnaBridge | 143:86740a56073b | 645 | |
AnnaBridge | 143:86740a56073b | 646 | /** |
AnnaBridge | 143:86740a56073b | 647 | * @brief Disable the ADC peripheral |
AnnaBridge | 143:86740a56073b | 648 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 649 | * @retval None |
AnnaBridge | 143:86740a56073b | 650 | */ |
AnnaBridge | 143:86740a56073b | 651 | #define __HAL_ADC_DISABLE(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 652 | do{ \ |
AnnaBridge | 143:86740a56073b | 653 | (__HANDLE__)->Instance->CR |= ADC_CR_ADDIS; \ |
AnnaBridge | 143:86740a56073b | 654 | __HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); \ |
AnnaBridge | 143:86740a56073b | 655 | } while(0) |
AnnaBridge | 143:86740a56073b | 656 | |
AnnaBridge | 143:86740a56073b | 657 | /** |
AnnaBridge | 143:86740a56073b | 658 | * @brief Verification of hardware constraints before ADC can be disabled |
AnnaBridge | 143:86740a56073b | 659 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 660 | * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled) |
AnnaBridge | 143:86740a56073b | 661 | */ |
AnnaBridge | 143:86740a56073b | 662 | #define ADC_DISABLING_CONDITIONS(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 663 | (( ( ((__HANDLE__)->Instance->CR) & \ |
AnnaBridge | 143:86740a56073b | 664 | (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN \ |
AnnaBridge | 143:86740a56073b | 665 | ) ? SET : RESET) |
AnnaBridge | 143:86740a56073b | 666 | |
AnnaBridge | 143:86740a56073b | 667 | /** |
AnnaBridge | 143:86740a56073b | 668 | * @brief Verification of ADC state: enabled or disabled |
AnnaBridge | 143:86740a56073b | 669 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 670 | * @retval SET (ADC enabled) or RESET (ADC disabled) |
AnnaBridge | 143:86740a56073b | 671 | */ |
AnnaBridge | 143:86740a56073b | 672 | #define ADC_IS_ENABLE(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 673 | (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ |
AnnaBridge | 143:86740a56073b | 674 | ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ |
AnnaBridge | 143:86740a56073b | 675 | ) ? SET : RESET) |
AnnaBridge | 143:86740a56073b | 676 | |
AnnaBridge | 143:86740a56073b | 677 | /** |
AnnaBridge | 143:86740a56073b | 678 | * @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution. |
AnnaBridge | 143:86740a56073b | 679 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 680 | * @retval None |
AnnaBridge | 143:86740a56073b | 681 | */ |
AnnaBridge | 143:86740a56073b | 682 | #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES) |
AnnaBridge | 143:86740a56073b | 683 | /** |
AnnaBridge | 143:86740a56073b | 684 | * @brief Test if conversion trigger of regular group is software start |
AnnaBridge | 143:86740a56073b | 685 | * or external trigger. |
AnnaBridge | 143:86740a56073b | 686 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 687 | * @retval SET (software start) or RESET (external trigger) |
AnnaBridge | 143:86740a56073b | 688 | */ |
AnnaBridge | 143:86740a56073b | 689 | #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 690 | (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET) |
AnnaBridge | 143:86740a56073b | 691 | |
AnnaBridge | 143:86740a56073b | 692 | |
AnnaBridge | 143:86740a56073b | 693 | |
AnnaBridge | 143:86740a56073b | 694 | /** |
AnnaBridge | 143:86740a56073b | 695 | * @brief Check if no conversion on going on regular group |
AnnaBridge | 143:86740a56073b | 696 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 697 | * @retval SET (conversion is on going) or RESET (no conversion is on going) |
AnnaBridge | 143:86740a56073b | 698 | */ |
AnnaBridge | 143:86740a56073b | 699 | #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 700 | (( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \ |
AnnaBridge | 143:86740a56073b | 701 | ) ? RESET : SET) |
AnnaBridge | 167:84c0a372a020 | 702 | |
AnnaBridge | 143:86740a56073b | 703 | /** |
AnnaBridge | 143:86740a56073b | 704 | * @brief Enable ADC continuous conversion mode. |
AnnaBridge | 143:86740a56073b | 705 | * @param _CONTINUOUS_MODE_: Continuous mode. |
AnnaBridge | 143:86740a56073b | 706 | * @retval None |
AnnaBridge | 143:86740a56073b | 707 | */ |
AnnaBridge | 143:86740a56073b | 708 | #define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U) |
AnnaBridge | 143:86740a56073b | 709 | |
AnnaBridge | 143:86740a56073b | 710 | /** |
AnnaBridge | 143:86740a56073b | 711 | * @brief Enable ADC scan mode to convert multiple ranks with sequencer. |
AnnaBridge | 143:86740a56073b | 712 | * @param _SCAN_MODE_: Scan conversion mode. |
AnnaBridge | 143:86740a56073b | 713 | * @retval None |
AnnaBridge | 143:86740a56073b | 714 | */ |
AnnaBridge | 143:86740a56073b | 715 | #define ADC_SCANDIR(_SCAN_MODE_) \ |
AnnaBridge | 143:86740a56073b | 716 | ( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \ |
AnnaBridge | 143:86740a56073b | 717 | )? (ADC_CFGR1_SCANDIR) : (0x00000000U) \ |
AnnaBridge | 143:86740a56073b | 718 | ) |
AnnaBridge | 143:86740a56073b | 719 | |
AnnaBridge | 143:86740a56073b | 720 | /** |
AnnaBridge | 143:86740a56073b | 721 | * @brief Configures the number of discontinuous conversions for the regular group channels. |
AnnaBridge | 143:86740a56073b | 722 | * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions. |
AnnaBridge | 143:86740a56073b | 723 | * @retval None |
AnnaBridge | 143:86740a56073b | 724 | */ |
AnnaBridge | 143:86740a56073b | 725 | #define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U) |
AnnaBridge | 143:86740a56073b | 726 | |
AnnaBridge | 143:86740a56073b | 727 | /** |
AnnaBridge | 143:86740a56073b | 728 | * @brief Enable the ADC DMA continuous request. |
AnnaBridge | 143:86740a56073b | 729 | * @param _DMAContReq_MODE_: DMA continuous request mode. |
AnnaBridge | 143:86740a56073b | 730 | * @retval None |
AnnaBridge | 143:86740a56073b | 731 | */ |
AnnaBridge | 143:86740a56073b | 732 | #define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U) |
AnnaBridge | 143:86740a56073b | 733 | |
AnnaBridge | 143:86740a56073b | 734 | /** |
AnnaBridge | 143:86740a56073b | 735 | * @brief Enable the ADC Auto Delay. |
AnnaBridge | 143:86740a56073b | 736 | * @param _AutoDelay_: Auto delay bit enable or disable. |
AnnaBridge | 143:86740a56073b | 737 | * @retval None |
AnnaBridge | 143:86740a56073b | 738 | */ |
AnnaBridge | 143:86740a56073b | 739 | #define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U) |
AnnaBridge | 143:86740a56073b | 740 | |
AnnaBridge | 143:86740a56073b | 741 | /** |
AnnaBridge | 143:86740a56073b | 742 | * @brief Enable the ADC LowPowerAutoPowerOff. |
AnnaBridge | 143:86740a56073b | 743 | * @param _AUTOFF_: AutoOff bit enable or disable. |
AnnaBridge | 143:86740a56073b | 744 | * @retval None |
AnnaBridge | 143:86740a56073b | 745 | */ |
AnnaBridge | 143:86740a56073b | 746 | #define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U) |
AnnaBridge | 167:84c0a372a020 | 747 | |
AnnaBridge | 143:86740a56073b | 748 | /** |
AnnaBridge | 143:86740a56073b | 749 | * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3. |
AnnaBridge | 143:86740a56073b | 750 | * @param _Threshold_: Threshold value |
AnnaBridge | 143:86740a56073b | 751 | * @retval None |
AnnaBridge | 143:86740a56073b | 752 | */ |
AnnaBridge | 143:86740a56073b | 753 | #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U) |
AnnaBridge | 143:86740a56073b | 754 | |
AnnaBridge | 143:86740a56073b | 755 | /** |
AnnaBridge | 143:86740a56073b | 756 | * @brief Enable the ADC Low Frequency mode. |
AnnaBridge | 143:86740a56073b | 757 | * @param _LOW_FREQUENCY_MODE_: Low Frequency mode. |
AnnaBridge | 143:86740a56073b | 758 | * @retval None |
AnnaBridge | 143:86740a56073b | 759 | */ |
AnnaBridge | 143:86740a56073b | 760 | #define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U) |
AnnaBridge | 167:84c0a372a020 | 761 | |
AnnaBridge | 143:86740a56073b | 762 | /** |
AnnaBridge | 143:86740a56073b | 763 | * @brief Shift the offset in function of the selected ADC resolution. |
AnnaBridge | 143:86740a56073b | 764 | * Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 |
AnnaBridge | 143:86740a56073b | 765 | * If resolution 12 bits, no shift. |
AnnaBridge | 143:86740a56073b | 766 | * If resolution 10 bits, shift of 2 ranks on the right. |
AnnaBridge | 143:86740a56073b | 767 | * If resolution 8 bits, shift of 4 ranks on the right. |
AnnaBridge | 143:86740a56073b | 768 | * If resolution 6 bits, shift of 6 ranks on the right. |
AnnaBridge | 143:86740a56073b | 769 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
AnnaBridge | 143:86740a56073b | 770 | * @param __HANDLE__: ADC handle. |
AnnaBridge | 143:86740a56073b | 771 | * @param _Offset_: Value to be shifted |
AnnaBridge | 143:86740a56073b | 772 | * @retval None |
AnnaBridge | 143:86740a56073b | 773 | */ |
AnnaBridge | 143:86740a56073b | 774 | #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \ |
AnnaBridge | 143:86740a56073b | 775 | ((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U)) |
AnnaBridge | 143:86740a56073b | 776 | |
AnnaBridge | 143:86740a56073b | 777 | /** |
AnnaBridge | 143:86740a56073b | 778 | * @brief Shift the AWD1 threshold in function of the selected ADC resolution. |
AnnaBridge | 143:86740a56073b | 779 | * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0 |
AnnaBridge | 143:86740a56073b | 780 | * If resolution 12 bits, no shift. |
AnnaBridge | 143:86740a56073b | 781 | * If resolution 10 bits, shift of 2 ranks on the right. |
AnnaBridge | 143:86740a56073b | 782 | * If resolution 8 bits, shift of 4 ranks on the right. |
AnnaBridge | 143:86740a56073b | 783 | * If resolution 6 bits, shift of 6 ranks on the right. |
AnnaBridge | 143:86740a56073b | 784 | * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) |
AnnaBridge | 143:86740a56073b | 785 | * @param __HANDLE__: ADC handle. |
AnnaBridge | 143:86740a56073b | 786 | * @param _Threshold_: Value to be shifted |
AnnaBridge | 143:86740a56073b | 787 | * @retval None |
AnnaBridge | 143:86740a56073b | 788 | */ |
AnnaBridge | 143:86740a56073b | 789 | #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ |
AnnaBridge | 143:86740a56073b | 790 | ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) |
AnnaBridge | 167:84c0a372a020 | 791 | |
AnnaBridge | 143:86740a56073b | 792 | /** |
AnnaBridge | 143:86740a56073b | 793 | * @brief Shift the value on the left, less significant are set to 0. |
AnnaBridge | 143:86740a56073b | 794 | * @param _Value_: Value to be shifted |
AnnaBridge | 143:86740a56073b | 795 | * @param _Shift_: Number of shift to be done |
AnnaBridge | 143:86740a56073b | 796 | * @retval None |
AnnaBridge | 143:86740a56073b | 797 | */ |
AnnaBridge | 143:86740a56073b | 798 | #define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_)) |
AnnaBridge | 143:86740a56073b | 799 | |
AnnaBridge | 143:86740a56073b | 800 | |
AnnaBridge | 143:86740a56073b | 801 | /** |
AnnaBridge | 143:86740a56073b | 802 | * @brief Enable the ADC end of conversion interrupt. |
AnnaBridge | 143:86740a56073b | 803 | * @param __HANDLE__: ADC handle. |
AnnaBridge | 143:86740a56073b | 804 | * @param __INTERRUPT__: ADC Interrupt. |
AnnaBridge | 143:86740a56073b | 805 | * @retval None |
AnnaBridge | 143:86740a56073b | 806 | */ |
AnnaBridge | 143:86740a56073b | 807 | #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ |
AnnaBridge | 143:86740a56073b | 808 | (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) |
AnnaBridge | 143:86740a56073b | 809 | |
AnnaBridge | 143:86740a56073b | 810 | /** |
AnnaBridge | 143:86740a56073b | 811 | * @brief Disable the ADC end of conversion interrupt. |
AnnaBridge | 143:86740a56073b | 812 | * @param __HANDLE__: ADC handle. |
AnnaBridge | 143:86740a56073b | 813 | * @param __INTERRUPT__: ADC interrupt. |
AnnaBridge | 143:86740a56073b | 814 | * @retval None |
AnnaBridge | 143:86740a56073b | 815 | */ |
AnnaBridge | 143:86740a56073b | 816 | #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ |
AnnaBridge | 143:86740a56073b | 817 | (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) |
AnnaBridge | 143:86740a56073b | 818 | |
AnnaBridge | 143:86740a56073b | 819 | /** @brief Checks if the specified ADC interrupt source is enabled or disabled. |
AnnaBridge | 143:86740a56073b | 820 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 821 | * @param __INTERRUPT__: ADC interrupt source to check |
AnnaBridge | 143:86740a56073b | 822 | * @arg ... |
AnnaBridge | 143:86740a56073b | 823 | * @arg ... |
AnnaBridge | 143:86740a56073b | 824 | * @retval State of interruption (TRUE or FALSE) |
AnnaBridge | 143:86740a56073b | 825 | */ |
AnnaBridge | 143:86740a56073b | 826 | #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ |
AnnaBridge | 143:86740a56073b | 827 | (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) |
AnnaBridge | 143:86740a56073b | 828 | |
AnnaBridge | 143:86740a56073b | 829 | /** |
AnnaBridge | 143:86740a56073b | 830 | * @brief Clear the ADC's pending flags |
AnnaBridge | 143:86740a56073b | 831 | * @param __HANDLE__: ADC handle. |
AnnaBridge | 143:86740a56073b | 832 | * @param __FLAG__: ADC flag. |
AnnaBridge | 143:86740a56073b | 833 | * @retval None |
AnnaBridge | 143:86740a56073b | 834 | */ |
AnnaBridge | 143:86740a56073b | 835 | /* Note: bit cleared bit by writing 1 */ |
AnnaBridge | 143:86740a56073b | 836 | #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ |
AnnaBridge | 143:86740a56073b | 837 | (((__HANDLE__)->Instance->ISR) = (__FLAG__)) |
AnnaBridge | 143:86740a56073b | 838 | |
AnnaBridge | 143:86740a56073b | 839 | /** |
AnnaBridge | 143:86740a56073b | 840 | * @brief Get the selected ADC's flag status. |
AnnaBridge | 143:86740a56073b | 841 | * @param __HANDLE__: ADC handle. |
AnnaBridge | 143:86740a56073b | 842 | * @param __FLAG__: ADC flag. |
AnnaBridge | 143:86740a56073b | 843 | * @retval None |
AnnaBridge | 143:86740a56073b | 844 | */ |
AnnaBridge | 143:86740a56073b | 845 | #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ |
AnnaBridge | 143:86740a56073b | 846 | ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) |
AnnaBridge | 143:86740a56073b | 847 | |
AnnaBridge | 143:86740a56073b | 848 | |
AnnaBridge | 143:86740a56073b | 849 | /** |
AnnaBridge | 143:86740a56073b | 850 | * @brief Simultaneously clears and sets specific bits of the handle State |
AnnaBridge | 143:86740a56073b | 851 | * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), |
AnnaBridge | 143:86740a56073b | 852 | * the first parameter is the ADC handle State, the second parameter is the |
AnnaBridge | 143:86740a56073b | 853 | * bit field to clear, the third and last parameter is the bit field to set. |
AnnaBridge | 143:86740a56073b | 854 | * @retval None |
AnnaBridge | 143:86740a56073b | 855 | */ |
AnnaBridge | 143:86740a56073b | 856 | #define ADC_STATE_CLR_SET MODIFY_REG |
AnnaBridge | 143:86740a56073b | 857 | |
AnnaBridge | 143:86740a56073b | 858 | /** |
AnnaBridge | 143:86740a56073b | 859 | * @brief Clear ADC error code (set it to error code: "no error") |
AnnaBridge | 143:86740a56073b | 860 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 861 | * @retval None |
AnnaBridge | 143:86740a56073b | 862 | */ |
AnnaBridge | 143:86740a56073b | 863 | #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 864 | ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) |
AnnaBridge | 143:86740a56073b | 865 | |
AnnaBridge | 143:86740a56073b | 866 | |
AnnaBridge | 143:86740a56073b | 867 | /** |
AnnaBridge | 143:86740a56073b | 868 | * @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler |
AnnaBridge | 143:86740a56073b | 869 | * @param __HANDLE__: ADC handle |
AnnaBridge | 143:86740a56073b | 870 | * @retval None |
AnnaBridge | 143:86740a56073b | 871 | */ |
AnnaBridge | 143:86740a56073b | 872 | |
AnnaBridge | 143:86740a56073b | 873 | #define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \ |
AnnaBridge | 143:86740a56073b | 874 | do{ \ |
AnnaBridge | 143:86740a56073b | 875 | if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ |
AnnaBridge | 143:86740a56073b | 876 | (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ |
AnnaBridge | 143:86740a56073b | 877 | (((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \ |
AnnaBridge | 143:86740a56073b | 878 | { \ |
AnnaBridge | 143:86740a56073b | 879 | (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ |
AnnaBridge | 143:86740a56073b | 880 | (__HANDLE__)->Instance->CFGR2 |= (__HANDLE__)->Init.ClockPrescaler; \ |
AnnaBridge | 143:86740a56073b | 881 | } \ |
AnnaBridge | 143:86740a56073b | 882 | else \ |
AnnaBridge | 143:86740a56073b | 883 | { \ |
AnnaBridge | 143:86740a56073b | 884 | /* CKMOD bits must be reset */ \ |
AnnaBridge | 143:86740a56073b | 885 | (__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \ |
AnnaBridge | 143:86740a56073b | 886 | ADC->CCR &= ~(ADC_CCR_PRESC); \ |
AnnaBridge | 143:86740a56073b | 887 | ADC->CCR |= (__HANDLE__)->Init.ClockPrescaler; \ |
AnnaBridge | 143:86740a56073b | 888 | } \ |
AnnaBridge | 143:86740a56073b | 889 | } while(0) |
AnnaBridge | 143:86740a56073b | 890 | |
AnnaBridge | 143:86740a56073b | 891 | |
AnnaBridge | 143:86740a56073b | 892 | #define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) ||\ |
AnnaBridge | 143:86740a56073b | 893 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ |
AnnaBridge | 143:86740a56073b | 894 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ |
AnnaBridge | 143:86740a56073b | 895 | ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ |
AnnaBridge | 143:86740a56073b | 896 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ |
AnnaBridge | 143:86740a56073b | 897 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ |
AnnaBridge | 143:86740a56073b | 898 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ |
AnnaBridge | 143:86740a56073b | 899 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ |
AnnaBridge | 143:86740a56073b | 900 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ |
AnnaBridge | 143:86740a56073b | 901 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ |
AnnaBridge | 143:86740a56073b | 902 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ |
AnnaBridge | 143:86740a56073b | 903 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ |
AnnaBridge | 143:86740a56073b | 904 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ |
AnnaBridge | 143:86740a56073b | 905 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ |
AnnaBridge | 143:86740a56073b | 906 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ |
AnnaBridge | 143:86740a56073b | 907 | ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) |
AnnaBridge | 143:86740a56073b | 908 | |
AnnaBridge | 143:86740a56073b | 909 | #define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ |
AnnaBridge | 143:86740a56073b | 910 | ((RESOLUTION) == ADC_RESOLUTION_10B) || \ |
AnnaBridge | 143:86740a56073b | 911 | ((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
AnnaBridge | 143:86740a56073b | 912 | ((RESOLUTION) == ADC_RESOLUTION_6B)) |
AnnaBridge | 143:86740a56073b | 913 | |
AnnaBridge | 143:86740a56073b | 914 | #define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) || \ |
AnnaBridge | 143:86740a56073b | 915 | ((RESOLUTION) == ADC_RESOLUTION_6B)) |
AnnaBridge | 143:86740a56073b | 916 | |
AnnaBridge | 143:86740a56073b | 917 | #define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ |
AnnaBridge | 143:86740a56073b | 918 | ((ALIGN) == ADC_DATAALIGN_LEFT)) |
AnnaBridge | 143:86740a56073b | 919 | |
AnnaBridge | 143:86740a56073b | 920 | #define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ |
AnnaBridge | 143:86740a56073b | 921 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ |
AnnaBridge | 143:86740a56073b | 922 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ |
AnnaBridge | 143:86740a56073b | 923 | ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)) |
AnnaBridge | 143:86740a56073b | 924 | |
AnnaBridge | 143:86740a56073b | 925 | #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ |
AnnaBridge | 143:86740a56073b | 926 | ((EOC_SELECTION) == ADC_EOC_SEQ_CONV) || \ |
AnnaBridge | 143:86740a56073b | 927 | ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV)) |
AnnaBridge | 143:86740a56073b | 928 | |
AnnaBridge | 143:86740a56073b | 929 | #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ |
AnnaBridge | 143:86740a56073b | 930 | ((OVR) == ADC_OVR_DATA_OVERWRITTEN)) |
AnnaBridge | 143:86740a56073b | 931 | |
AnnaBridge | 143:86740a56073b | 932 | #define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) || \ |
AnnaBridge | 143:86740a56073b | 933 | ((WATCHDOG) == ADC_RANK_NONE)) |
AnnaBridge | 143:86740a56073b | 934 | |
AnnaBridge | 143:86740a56073b | 935 | #if defined (STM32L053xx) || defined (STM32L063xx) || defined (STM32L073xx) || defined (STM32L083xx) |
AnnaBridge | 143:86740a56073b | 936 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
AnnaBridge | 143:86740a56073b | 937 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
AnnaBridge | 143:86740a56073b | 938 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
AnnaBridge | 143:86740a56073b | 939 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
AnnaBridge | 143:86740a56073b | 940 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
AnnaBridge | 143:86740a56073b | 941 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
AnnaBridge | 143:86740a56073b | 942 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
AnnaBridge | 143:86740a56073b | 943 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
AnnaBridge | 143:86740a56073b | 944 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
AnnaBridge | 143:86740a56073b | 945 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
AnnaBridge | 143:86740a56073b | 946 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
AnnaBridge | 143:86740a56073b | 947 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
AnnaBridge | 143:86740a56073b | 948 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
AnnaBridge | 143:86740a56073b | 949 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
AnnaBridge | 143:86740a56073b | 950 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
AnnaBridge | 143:86740a56073b | 951 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
AnnaBridge | 143:86740a56073b | 952 | ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ |
AnnaBridge | 143:86740a56073b | 953 | ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ |
AnnaBridge | 143:86740a56073b | 954 | ((CHANNEL) == ADC_CHANNEL_VLCD)) |
AnnaBridge | 143:86740a56073b | 955 | #else |
AnnaBridge | 143:86740a56073b | 956 | #define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ |
AnnaBridge | 143:86740a56073b | 957 | ((CHANNEL) == ADC_CHANNEL_1) || \ |
AnnaBridge | 143:86740a56073b | 958 | ((CHANNEL) == ADC_CHANNEL_2) || \ |
AnnaBridge | 143:86740a56073b | 959 | ((CHANNEL) == ADC_CHANNEL_3) || \ |
AnnaBridge | 143:86740a56073b | 960 | ((CHANNEL) == ADC_CHANNEL_4) || \ |
AnnaBridge | 143:86740a56073b | 961 | ((CHANNEL) == ADC_CHANNEL_5) || \ |
AnnaBridge | 143:86740a56073b | 962 | ((CHANNEL) == ADC_CHANNEL_6) || \ |
AnnaBridge | 143:86740a56073b | 963 | ((CHANNEL) == ADC_CHANNEL_7) || \ |
AnnaBridge | 143:86740a56073b | 964 | ((CHANNEL) == ADC_CHANNEL_8) || \ |
AnnaBridge | 143:86740a56073b | 965 | ((CHANNEL) == ADC_CHANNEL_9) || \ |
AnnaBridge | 143:86740a56073b | 966 | ((CHANNEL) == ADC_CHANNEL_10) || \ |
AnnaBridge | 143:86740a56073b | 967 | ((CHANNEL) == ADC_CHANNEL_11) || \ |
AnnaBridge | 143:86740a56073b | 968 | ((CHANNEL) == ADC_CHANNEL_12) || \ |
AnnaBridge | 143:86740a56073b | 969 | ((CHANNEL) == ADC_CHANNEL_13) || \ |
AnnaBridge | 143:86740a56073b | 970 | ((CHANNEL) == ADC_CHANNEL_14) || \ |
AnnaBridge | 143:86740a56073b | 971 | ((CHANNEL) == ADC_CHANNEL_15) || \ |
AnnaBridge | 143:86740a56073b | 972 | ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ |
AnnaBridge | 143:86740a56073b | 973 | ((CHANNEL) == ADC_CHANNEL_VREFINT)) |
AnnaBridge | 143:86740a56073b | 974 | #endif |
AnnaBridge | 143:86740a56073b | 975 | |
AnnaBridge | 143:86740a56073b | 976 | #define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) || \ |
AnnaBridge | 167:84c0a372a020 | 977 | ((TIME) == ADC_SAMPLETIME_3CYCLES_5 ) || \ |
AnnaBridge | 143:86740a56073b | 978 | ((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) || \ |
AnnaBridge | 167:84c0a372a020 | 979 | ((TIME) == ADC_SAMPLETIME_12CYCLES_5 ) || \ |
AnnaBridge | 167:84c0a372a020 | 980 | ((TIME) == ADC_SAMPLETIME_19CYCLES_5 ) || \ |
AnnaBridge | 167:84c0a372a020 | 981 | ((TIME) == ADC_SAMPLETIME_39CYCLES_5 ) || \ |
AnnaBridge | 167:84c0a372a020 | 982 | ((TIME) == ADC_SAMPLETIME_79CYCLES_5 ) || \ |
AnnaBridge | 167:84c0a372a020 | 983 | ((TIME) == ADC_SAMPLETIME_160CYCLES_5)) |
AnnaBridge | 143:86740a56073b | 984 | |
AnnaBridge | 143:86740a56073b | 985 | #define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) || \ |
AnnaBridge | 143:86740a56073b | 986 | ((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD)) |
AnnaBridge | 143:86740a56073b | 987 | |
AnnaBridge | 143:86740a56073b | 988 | #define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) || \ |
AnnaBridge | 143:86740a56073b | 989 | ((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) || \ |
AnnaBridge | 143:86740a56073b | 990 | ((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) || \ |
AnnaBridge | 143:86740a56073b | 991 | ((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) || \ |
AnnaBridge | 143:86740a56073b | 992 | ((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) || \ |
AnnaBridge | 143:86740a56073b | 993 | ((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) || \ |
AnnaBridge | 143:86740a56073b | 994 | ((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) || \ |
AnnaBridge | 143:86740a56073b | 995 | ((RATIO) == ADC_OVERSAMPLING_RATIO_256 )) |
AnnaBridge | 143:86740a56073b | 996 | |
AnnaBridge | 143:86740a56073b | 997 | #define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) || \ |
AnnaBridge | 143:86740a56073b | 998 | ((SHIFT) == ADC_RIGHTBITSHIFT_1 ) || \ |
AnnaBridge | 143:86740a56073b | 999 | ((SHIFT) == ADC_RIGHTBITSHIFT_2 ) || \ |
AnnaBridge | 143:86740a56073b | 1000 | ((SHIFT) == ADC_RIGHTBITSHIFT_3 ) || \ |
AnnaBridge | 143:86740a56073b | 1001 | ((SHIFT) == ADC_RIGHTBITSHIFT_4 ) || \ |
AnnaBridge | 143:86740a56073b | 1002 | ((SHIFT) == ADC_RIGHTBITSHIFT_5 ) || \ |
AnnaBridge | 143:86740a56073b | 1003 | ((SHIFT) == ADC_RIGHTBITSHIFT_6 ) || \ |
AnnaBridge | 143:86740a56073b | 1004 | ((SHIFT) == ADC_RIGHTBITSHIFT_7 ) || \ |
AnnaBridge | 143:86740a56073b | 1005 | ((SHIFT) == ADC_RIGHTBITSHIFT_8 )) |
AnnaBridge | 143:86740a56073b | 1006 | |
AnnaBridge | 143:86740a56073b | 1007 | #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ |
AnnaBridge | 143:86740a56073b | 1008 | ((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) |
AnnaBridge | 143:86740a56073b | 1009 | |
AnnaBridge | 143:86740a56073b | 1010 | #define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) || \ |
AnnaBridge | 143:86740a56073b | 1011 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ |
AnnaBridge | 143:86740a56073b | 1012 | ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG )) |
AnnaBridge | 143:86740a56073b | 1013 | |
AnnaBridge | 143:86740a56073b | 1014 | #define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP) |
AnnaBridge | 143:86740a56073b | 1015 | |
AnnaBridge | 143:86740a56073b | 1016 | #define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) || \ |
AnnaBridge | 143:86740a56073b | 1017 | ((EVENT) == ADC_OVR_EVENT)) |
AnnaBridge | 143:86740a56073b | 1018 | |
AnnaBridge | 143:86740a56073b | 1019 | |
AnnaBridge | 143:86740a56073b | 1020 | /** @defgroup ADC_range_verification ADC Range Verification |
AnnaBridge | 143:86740a56073b | 1021 | * in function of ADC resolution selected (12, 10, 8 or 6 bits) |
AnnaBridge | 143:86740a56073b | 1022 | * @{ |
AnnaBridge | 167:84c0a372a020 | 1023 | */ |
AnnaBridge | 143:86740a56073b | 1024 | #define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \ |
AnnaBridge | 143:86740a56073b | 1025 | ((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) || \ |
AnnaBridge | 143:86740a56073b | 1026 | (((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) || \ |
AnnaBridge | 143:86740a56073b | 1027 | (((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) || \ |
AnnaBridge | 143:86740a56073b | 1028 | (((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU)))) |
AnnaBridge | 143:86740a56073b | 1029 | /** |
AnnaBridge | 143:86740a56073b | 1030 | * @} |
AnnaBridge | 167:84c0a372a020 | 1031 | */ |
AnnaBridge | 143:86740a56073b | 1032 | |
AnnaBridge | 143:86740a56073b | 1033 | /** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification |
AnnaBridge | 143:86740a56073b | 1034 | * @{ |
AnnaBridge | 167:84c0a372a020 | 1035 | */ |
AnnaBridge | 143:86740a56073b | 1036 | #define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U))) |
AnnaBridge | 143:86740a56073b | 1037 | /** |
AnnaBridge | 143:86740a56073b | 1038 | * @} |
AnnaBridge | 143:86740a56073b | 1039 | */ |
AnnaBridge | 167:84c0a372a020 | 1040 | |
AnnaBridge | 167:84c0a372a020 | 1041 | /** |
AnnaBridge | 143:86740a56073b | 1042 | * @} |
AnnaBridge | 143:86740a56073b | 1043 | */ |
AnnaBridge | 167:84c0a372a020 | 1044 | |
AnnaBridge | 167:84c0a372a020 | 1045 | /* Include ADC HAL Extended module */ |
AnnaBridge | 143:86740a56073b | 1046 | #include "stm32l0xx_hal_adc_ex.h" |
AnnaBridge | 167:84c0a372a020 | 1047 | |
AnnaBridge | 167:84c0a372a020 | 1048 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 167:84c0a372a020 | 1049 | /** @addtogroup ADC_Exported_Functions |
AnnaBridge | 143:86740a56073b | 1050 | * @{ |
AnnaBridge | 143:86740a56073b | 1051 | */ |
AnnaBridge | 167:84c0a372a020 | 1052 | |
AnnaBridge | 167:84c0a372a020 | 1053 | /** @addtogroup ADC_Exported_Functions_Group1 |
AnnaBridge | 167:84c0a372a020 | 1054 | * @brief Initialization and Configuration functions |
AnnaBridge | 167:84c0a372a020 | 1055 | * @{ |
AnnaBridge | 167:84c0a372a020 | 1056 | */ |
AnnaBridge | 167:84c0a372a020 | 1057 | /* Initialization and de-initialization functions ****************************/ |
AnnaBridge | 143:86740a56073b | 1058 | HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1059 | HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); |
AnnaBridge | 143:86740a56073b | 1060 | void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1061 | void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1062 | /** |
AnnaBridge | 143:86740a56073b | 1063 | * @} |
AnnaBridge | 167:84c0a372a020 | 1064 | */ |
AnnaBridge | 143:86740a56073b | 1065 | |
AnnaBridge | 167:84c0a372a020 | 1066 | /** @addtogroup ADC_Exported_Functions_Group2 |
AnnaBridge | 167:84c0a372a020 | 1067 | * @brief IO operation functions |
AnnaBridge | 143:86740a56073b | 1068 | * @{ |
AnnaBridge | 143:86740a56073b | 1069 | */ |
AnnaBridge | 167:84c0a372a020 | 1070 | /* IO operation functions *****************************************************/ |
AnnaBridge | 167:84c0a372a020 | 1071 | |
AnnaBridge | 143:86740a56073b | 1072 | /* Blocking mode: Polling */ |
AnnaBridge | 143:86740a56073b | 1073 | HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1074 | HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); |
AnnaBridge | 167:84c0a372a020 | 1075 | HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); |
AnnaBridge | 143:86740a56073b | 1076 | HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); |
AnnaBridge | 167:84c0a372a020 | 1077 | |
AnnaBridge | 143:86740a56073b | 1078 | /* Non-blocking mode: Interruption */ |
AnnaBridge | 143:86740a56073b | 1079 | HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1080 | HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); |
AnnaBridge | 167:84c0a372a020 | 1081 | |
AnnaBridge | 143:86740a56073b | 1082 | /* Non-blocking mode: DMA */ |
AnnaBridge | 143:86740a56073b | 1083 | HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); |
AnnaBridge | 143:86740a56073b | 1084 | HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); |
AnnaBridge | 167:84c0a372a020 | 1085 | |
AnnaBridge | 143:86740a56073b | 1086 | /* ADC retrieve conversion value intended to be used with polling or interruption */ |
AnnaBridge | 143:86740a56073b | 1087 | uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); |
AnnaBridge | 167:84c0a372a020 | 1088 | |
AnnaBridge | 143:86740a56073b | 1089 | /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ |
AnnaBridge | 143:86740a56073b | 1090 | void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1091 | void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1092 | void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1093 | void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1094 | void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); |
AnnaBridge | 143:86740a56073b | 1095 | /** |
AnnaBridge | 143:86740a56073b | 1096 | * @} |
AnnaBridge | 167:84c0a372a020 | 1097 | */ |
AnnaBridge | 143:86740a56073b | 1098 | |
AnnaBridge | 167:84c0a372a020 | 1099 | /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions |
AnnaBridge | 167:84c0a372a020 | 1100 | * @brief Peripheral Control functions |
AnnaBridge | 167:84c0a372a020 | 1101 | * @{ |
AnnaBridge | 167:84c0a372a020 | 1102 | */ |
AnnaBridge | 143:86740a56073b | 1103 | /* Peripheral Control functions ***********************************************/ |
AnnaBridge | 143:86740a56073b | 1104 | HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); |
AnnaBridge | 143:86740a56073b | 1105 | HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); |
AnnaBridge | 143:86740a56073b | 1106 | /** |
AnnaBridge | 143:86740a56073b | 1107 | * @} |
AnnaBridge | 167:84c0a372a020 | 1108 | */ |
AnnaBridge | 143:86740a56073b | 1109 | |
AnnaBridge | 143:86740a56073b | 1110 | /* Peripheral State functions *************************************************/ |
AnnaBridge | 167:84c0a372a020 | 1111 | /** @addtogroup ADC_Exported_Functions_Group4 |
AnnaBridge | 143:86740a56073b | 1112 | * @{ |
AnnaBridge | 143:86740a56073b | 1113 | */ |
AnnaBridge | 143:86740a56073b | 1114 | uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); |
AnnaBridge | 143:86740a56073b | 1115 | uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); |
AnnaBridge | 143:86740a56073b | 1116 | /** |
AnnaBridge | 143:86740a56073b | 1117 | * @} |
AnnaBridge | 167:84c0a372a020 | 1118 | */ |
AnnaBridge | 143:86740a56073b | 1119 | |
AnnaBridge | 143:86740a56073b | 1120 | |
AnnaBridge | 143:86740a56073b | 1121 | /** |
AnnaBridge | 143:86740a56073b | 1122 | * @} |
AnnaBridge | 167:84c0a372a020 | 1123 | */ |
AnnaBridge | 143:86740a56073b | 1124 | |
AnnaBridge | 143:86740a56073b | 1125 | /** |
AnnaBridge | 143:86740a56073b | 1126 | * @} |
AnnaBridge | 143:86740a56073b | 1127 | */ |
AnnaBridge | 143:86740a56073b | 1128 | |
AnnaBridge | 143:86740a56073b | 1129 | /** |
AnnaBridge | 143:86740a56073b | 1130 | * @} |
AnnaBridge | 143:86740a56073b | 1131 | */ |
AnnaBridge | 143:86740a56073b | 1132 | |
AnnaBridge | 143:86740a56073b | 1133 | #ifdef __cplusplus |
AnnaBridge | 143:86740a56073b | 1134 | } |
AnnaBridge | 143:86740a56073b | 1135 | #endif |
AnnaBridge | 143:86740a56073b | 1136 | |
AnnaBridge | 143:86740a56073b | 1137 | |
AnnaBridge | 167:84c0a372a020 | 1138 | #endif /*__STM32L0xx_HAL_ADC_H */ |
AnnaBridge | 143:86740a56073b | 1139 | |
AnnaBridge | 143:86740a56073b | 1140 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |