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TARGET_DISCO_L072CZ_LRWAN1/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_adc.h@143:86740a56073b, 2017-05-26 (annotated)

Committer:: AnnaBridge
Date:: Fri May 26 12:30:20 2017 +0100
Revision:: 143:86740a56073b
Child:: 167:84c0a372a020

Release 143 of the mbed library.

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	143:86740a56073b	1	/**
AnnaBridge	143:86740a56073b	2	******************************************************************************
AnnaBridge	143:86740a56073b	3	* @file stm32l0xx_hal_adc.h
AnnaBridge	143:86740a56073b	4	* @author MCD Application Team
AnnaBridge	143:86740a56073b	5	* @version V1.7.0
AnnaBridge	143:86740a56073b	6	* @date 31-May-2016
AnnaBridge	143:86740a56073b	7	* @brief This file contains all the functions prototypes for the ADC firmware
AnnaBridge	143:86740a56073b	8	* library.
AnnaBridge	143:86740a56073b	9	******************************************************************************
AnnaBridge	143:86740a56073b	10	* @attention
AnnaBridge	143:86740a56073b	11	*
AnnaBridge	143:86740a56073b	12	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
AnnaBridge	143:86740a56073b	13	*
AnnaBridge	143:86740a56073b	14	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	143:86740a56073b	15	* are permitted provided that the following conditions are met:
AnnaBridge	143:86740a56073b	16	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	143:86740a56073b	17	* this list of conditions and the following disclaimer.
AnnaBridge	143:86740a56073b	18	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	143:86740a56073b	19	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	143:86740a56073b	20	* and/or other materials provided with the distribution.
AnnaBridge	143:86740a56073b	21	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	143:86740a56073b	22	* may be used to endorse or promote products derived from this software
AnnaBridge	143:86740a56073b	23	* without specific prior written permission.
AnnaBridge	143:86740a56073b	24	*
AnnaBridge	143:86740a56073b	25	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	143:86740a56073b	26	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	143:86740a56073b	27	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	143:86740a56073b	28	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	143:86740a56073b	29	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	143:86740a56073b	30	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	143:86740a56073b	31	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	143:86740a56073b	32	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	143:86740a56073b	33	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	143:86740a56073b	34	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	143:86740a56073b	35	*
AnnaBridge	143:86740a56073b	36	******************************************************************************
AnnaBridge	143:86740a56073b	37	*/
AnnaBridge	143:86740a56073b	38
AnnaBridge	143:86740a56073b	39	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	143:86740a56073b	40	#ifndef __STM32L0xx_ADC_H
AnnaBridge	143:86740a56073b	41	#define __STM32L0xx_ADC_H
AnnaBridge	143:86740a56073b	42
AnnaBridge	143:86740a56073b	43	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	44	extern "C" {
AnnaBridge	143:86740a56073b	45	#endif
AnnaBridge	143:86740a56073b	46
AnnaBridge	143:86740a56073b	47	/* Includes ------------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	48	#include "stm32l0xx_hal_def.h"
AnnaBridge	143:86740a56073b	49
AnnaBridge	143:86740a56073b	50	/** @addtogroup STM32L0xx_HAL_Driver
AnnaBridge	143:86740a56073b	51	* @{
AnnaBridge	143:86740a56073b	52	*/
AnnaBridge	143:86740a56073b	53
AnnaBridge	143:86740a56073b	54	/** @defgroup ADC ADC
AnnaBridge	143:86740a56073b	55	* @{
AnnaBridge	143:86740a56073b	56	*/
AnnaBridge	143:86740a56073b	57
AnnaBridge	143:86740a56073b	58	/** @defgroup ADC_Exported_Types ADC Exported Types
AnnaBridge	143:86740a56073b	59	* @{
AnnaBridge	143:86740a56073b	60	*/
AnnaBridge	143:86740a56073b	61
AnnaBridge	143:86740a56073b	62	/* Exported types ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	63	/**
AnnaBridge	143:86740a56073b	64	* @brief HAL ADC state machine: ADC states definition (bitfields)
AnnaBridge	143:86740a56073b	65	*/
AnnaBridge	143:86740a56073b	66	/* States of ADC global scope */
AnnaBridge	143:86740a56073b	67	#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /!< ADC not yet initialized or disabled /
AnnaBridge	143:86740a56073b	68	#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /!< ADC peripheral ready for use /
AnnaBridge	143:86740a56073b	69	#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /!< ADC is busy to internal process (initialization, calibration) /
AnnaBridge	143:86740a56073b	70	#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /!< TimeOut occurrence /
AnnaBridge	143:86740a56073b	71
AnnaBridge	143:86740a56073b	72	/* States of ADC errors */
AnnaBridge	143:86740a56073b	73	#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /!< Internal error occurrence /
AnnaBridge	143:86740a56073b	74	#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /!< Configuration error occurrence /
AnnaBridge	143:86740a56073b	75	#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /!< DMA error occurrence /
AnnaBridge	143:86740a56073b	76
AnnaBridge	143:86740a56073b	77	/* States of ADC group regular */
AnnaBridge	143:86740a56073b	78	#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
AnnaBridge	143:86740a56073b	79	external trigger, low power auto power-on, multimode ADC master control) */
AnnaBridge	143:86740a56073b	80	#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /!< Conversion data available on group regular /
AnnaBridge	143:86740a56073b	81	#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /!< Overrun occurrence /
AnnaBridge	143:86740a56073b	82	#define HAL_ADC_STATE_REG_EOSMP ((uint32_t)0x00000800U) /!< Not available on STM32F0 device: End Of Sampling flag raised /
AnnaBridge	143:86740a56073b	83
AnnaBridge	143:86740a56073b	84	/* States of ADC group injected */
AnnaBridge	143:86740a56073b	85	#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< Not available on STM32F0 device: A conversion on group injected is ongoing or can occur (either by auto-injection mode,
AnnaBridge	143:86740a56073b	86	external trigger, low power auto power-on, multimode ADC master control) */
AnnaBridge	143:86740a56073b	87	#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /!< Not available on STM32F0 device: Conversion data available on group injected /
AnnaBridge	143:86740a56073b	88	#define HAL_ADC_STATE_INJ_JQOVF ((uint32_t)0x00004000U) /!< Not available on STM32F0 device: Not available on STM32F0 device: Injected queue overflow occurrence /
AnnaBridge	143:86740a56073b	89
AnnaBridge	143:86740a56073b	90	/* States of ADC analog watchdogs */
AnnaBridge	143:86740a56073b	91	#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /!< Out-of-window occurrence of analog watchdog 1 /
AnnaBridge	143:86740a56073b	92	#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 2 /
AnnaBridge	143:86740a56073b	93	#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /!< Not available on STM32F0 device: Out-of-window occurrence of analog watchdog 3 /
AnnaBridge	143:86740a56073b	94
AnnaBridge	143:86740a56073b	95	/* States of ADC multi-mode */
AnnaBridge	143:86740a56073b	96	#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /!< Not available on STM32F0 device: ADC in multimode slave state, controlled by another ADC master ( /
AnnaBridge	143:86740a56073b	97
AnnaBridge	143:86740a56073b	98
AnnaBridge	143:86740a56073b	99	/**
AnnaBridge	143:86740a56073b	100	* @brief ADC Oversampler structure definition
AnnaBridge	143:86740a56073b	101	*/
AnnaBridge	143:86740a56073b	102	typedef struct
AnnaBridge	143:86740a56073b	103	{
AnnaBridge	143:86740a56073b	104	uint32_t Ratio; /*!< Configures the oversampling ratio.
AnnaBridge	143:86740a56073b	105	This parameter can be a value of @ref ADC_Oversampling_Ratio */
AnnaBridge	143:86740a56073b	106	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
AnnaBridge	143:86740a56073b	107	This parameter can be a value of @ref ADC_Right_Bit_Shift */
AnnaBridge	143:86740a56073b	108	uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode
AnnaBridge	143:86740a56073b	109	This parameter can be a value of @ref ADC_Triggered_Oversampling_Mode */
AnnaBridge	143:86740a56073b	110
AnnaBridge	143:86740a56073b	111	}ADC_OversamplingTypeDef;
AnnaBridge	143:86740a56073b	112
AnnaBridge	143:86740a56073b	113	/**
AnnaBridge	143:86740a56073b	114	* @brief ADC Init structure definition
AnnaBridge	143:86740a56073b	115	* @note The setting of these parameters with function HAL_ADC_Init() is conditioned by the ADC state.
AnnaBridge	143:86740a56073b	116	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge	143:86740a56073b	117	* without error reporting (as it can be the expected behavior in case of intended action to update antother parameter (which fullfills the ADC state condition) on the fly).
AnnaBridge	143:86740a56073b	118	*/
AnnaBridge	143:86740a56073b	119	typedef struct
AnnaBridge	143:86740a56073b	120	{
AnnaBridge	143:86740a56073b	121	uint32_t OversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled
AnnaBridge	143:86740a56073b	122	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	123	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	124	ADC_OversamplingTypeDef Oversample; /*!< Specifies the Oversampling parameters
AnnaBridge	143:86740a56073b	125	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	126	uint32_t ClockPrescaler; /*!< Selects the ADC clock frequency.
AnnaBridge	143:86740a56073b	127	This parameter can be a value of @ref ADC_ClockPrescaler
AnnaBridge	143:86740a56073b	128	Note: This parameter can be modified only if ADC is disabled.
AnnaBridge	143:86740a56073b	129	Note: In case of Synchronous clock mode divided by 1, this configuration must be enabled only
AnnaBridge	143:86740a56073b	130	if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC
AnnaBridge	143:86740a56073b	131	must be bypassed and the system clock must by 50% duty cycle). Refer to reference manual for details */
AnnaBridge	143:86740a56073b	132	uint32_t Resolution; /*!< Configures the ADC resolution mode.
AnnaBridge	143:86740a56073b	133	This parameter can be a value of @ref ADC_Resolution
AnnaBridge	143:86740a56073b	134	Note: This parameter can be modified only if ADC is disabled. */
AnnaBridge	143:86740a56073b	135	uint32_t SamplingTime; /*!< The sample time value to be set for all channels.
AnnaBridge	143:86740a56073b	136	This parameter can be a value of @ref ADC_sampling_times
AnnaBridge	143:86740a56073b	137	Note: This parameter can be modified only if there is no conversion ongoing. */
AnnaBridge	143:86740a56073b	138	uint32_t ScanConvMode; /*!< The scan sequence direction.
AnnaBridge	143:86740a56073b	139	If several channels are set: Conversions are performed in sequence mode
AnnaBridge	143:86740a56073b	140	(ranks defined by each channel number: channel 0 fixed on rank 0,
AnnaBridge	143:86740a56073b	141	channel 1 fixed on rank1, ...).
AnnaBridge	143:86740a56073b	142	This parameter can be a value of @ref ADC_Scan_mode
AnnaBridge	143:86740a56073b	143	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	144	uint32_t DataAlign; /*!< Specifies whether the ADC data alignment is left or right.
AnnaBridge	143:86740a56073b	145	This parameter can be a value of @ref ADC_data_align
AnnaBridge	143:86740a56073b	146	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	147	uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in Continuous or Single mode.
AnnaBridge	143:86740a56073b	148	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	149	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	150	uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversion is performed
AnnaBridge	143:86740a56073b	151	in Complete-sequence/Discontinuous-sequence.
AnnaBridge	143:86740a56073b	152	Discontinuous mode can be enabled only if continuous mode is disabled.
AnnaBridge	143:86740a56073b	153	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	154	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	155	uint32_t ExternalTrigConv; /*!< Select the external event used to trigger the start of conversion.
AnnaBridge	143:86740a56073b	156	If set to ADC_SOFTWARE_START, external triggers are disabled.
AnnaBridge	143:86740a56073b	157	This parameter can be a value of @ref ADC_External_trigger_Source
AnnaBridge	143:86740a56073b	158	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	159	uint32_t ExternalTrigConvEdge; /*!< Select the external trigger edge and enable the trigger.
AnnaBridge	143:86740a56073b	160	If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
AnnaBridge	143:86740a56073b	161	This parameter can be a value of @ref ADC_Regular_External_Trigger_Source_Edge
AnnaBridge	143:86740a56073b	162	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	163	uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
AnnaBridge	143:86740a56073b	164	or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
AnnaBridge	143:86740a56073b	165	Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer max pointer is reached.
AnnaBridge	143:86740a56073b	166	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	167	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	168	uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion polling and interruption:
AnnaBridge	143:86740a56073b	169	end of single channel conversion or end of channels conversions sequence.
AnnaBridge	143:86740a56073b	170	This parameter can be a value of @ref ADC_EOCSelection */
AnnaBridge	143:86740a56073b	171	uint32_t Overrun; /*!< Select the behaviour in case of overrun: data preserved or overwritten
AnnaBridge	143:86740a56073b	172	This parameter has an effect on regular channels only, including in DMA mode.
AnnaBridge	143:86740a56073b	173	This parameter can be a value of @ref ADC_Overrun
AnnaBridge	143:86740a56073b	174	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	175	uint32_t LowPowerAutoWait; /*!< Specifies the usage of dynamic low power Auto Delay: new conversion start only
AnnaBridge	143:86740a56073b	176	when the previous conversion (for regular channel) is completed.
AnnaBridge	143:86740a56073b	177	This avoids risk of overrun for low frequency application.
AnnaBridge	143:86740a56073b	178	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	179	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	180	uint32_t LowPowerFrequencyMode; /*!< When selecting an analog ADC clock frequency lower than 2.8MHz,
AnnaBridge	143:86740a56073b	181	it is mandatory to first enable the Low Frequency Mode.
AnnaBridge	143:86740a56073b	182	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	183	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	184	uint32_t LowPowerAutoPowerOff; /*!< When setting the AutoOff feature, the ADC is always powered off when not converting and automatically
AnnaBridge	143:86740a56073b	185	wakes-up when a conversion is started (by software or hardware trigger).
AnnaBridge	143:86740a56073b	186	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	143:86740a56073b	187	Note: This parameter can be modified only if there is no conversion is ongoing. */
AnnaBridge	143:86740a56073b	188	}ADC_InitTypeDef;
AnnaBridge	143:86740a56073b	189
AnnaBridge	143:86740a56073b	190	/**
AnnaBridge	143:86740a56073b	191	* @brief ADC handle Structure definition
AnnaBridge	143:86740a56073b	192	*/
AnnaBridge	143:86740a56073b	193	typedef struct
AnnaBridge	143:86740a56073b	194	{
AnnaBridge	143:86740a56073b	195	ADC_TypeDef Instance; /!< Register base address */
AnnaBridge	143:86740a56073b	196
AnnaBridge	143:86740a56073b	197	ADC_InitTypeDef Init; /!< ADC required parameters /
AnnaBridge	143:86740a56073b	198
AnnaBridge	143:86740a56073b	199	DMA_HandleTypeDef DMA_Handle; /!< Pointer DMA Handler */
AnnaBridge	143:86740a56073b	200
AnnaBridge	143:86740a56073b	201	HAL_LockTypeDef Lock; /!< ADC locking object /
AnnaBridge	143:86740a56073b	202
AnnaBridge	143:86740a56073b	203	__IO uint32_t State; /!< ADC communication state (bitmap of ADC states) /
AnnaBridge	143:86740a56073b	204
AnnaBridge	143:86740a56073b	205	__IO uint32_t ErrorCode; /!< ADC Error code /
AnnaBridge	143:86740a56073b	206	}ADC_HandleTypeDef;
AnnaBridge	143:86740a56073b	207
AnnaBridge	143:86740a56073b	208	/**
AnnaBridge	143:86740a56073b	209	* @brief ADC Configuration regular Channel structure definition
AnnaBridge	143:86740a56073b	210	*/
AnnaBridge	143:86740a56073b	211	typedef struct
AnnaBridge	143:86740a56073b	212	{
AnnaBridge	143:86740a56073b	213	uint32_t Channel; /*!< the ADC channel to configure
AnnaBridge	143:86740a56073b	214	This parameter can be a value of @ref ADC_channels */
AnnaBridge	143:86740a56073b	215
AnnaBridge	143:86740a56073b	216	uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer.
AnnaBridge	143:86740a56073b	217	On STM32L0 devices, number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number
AnnaBridge	143:86740a56073b	218	(channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
AnnaBridge	143:86740a56073b	219	Despite the channel rank is fixed, this parameter allow an additional possibility: to remove the selected rank (selected channel) from sequencer.
AnnaBridge	143:86740a56073b	220	This parameter can be a value of @ref ADC_rank */
AnnaBridge	143:86740a56073b	221	}ADC_ChannelConfTypeDef;
AnnaBridge	143:86740a56073b	222
AnnaBridge	143:86740a56073b	223
AnnaBridge	143:86740a56073b	224	/**
AnnaBridge	143:86740a56073b	225	* @brief ADC Configuration analog watchdog definition
AnnaBridge	143:86740a56073b	226	*/
AnnaBridge	143:86740a56073b	227	typedef struct
AnnaBridge	143:86740a56073b	228	{
AnnaBridge	143:86740a56073b	229	uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode: single/all channels.
AnnaBridge	143:86740a56073b	230	This parameter can be a value of @ref ADC_analog_watchdog_mode */
AnnaBridge	143:86740a56073b	231	uint32_t Channel; /*!< Selects which ADC channel to monitor by analog watchdog.
AnnaBridge	143:86740a56073b	232	This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
AnnaBridge	143:86740a56073b	233	This parameter can be a value of @ref ADC_channels */
AnnaBridge	143:86740a56073b	234	uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
AnnaBridge	143:86740a56073b	235	This parameter can be set to ENABLE or DISABLE */
AnnaBridge	143:86740a56073b	236	uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge	143:86740a56073b	237	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
AnnaBridge	143:86740a56073b	238	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
AnnaBridge	143:86740a56073b	239	uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
AnnaBridge	143:86740a56073b	240	Depending of ADC resolution selected (12, 10, 8 or 6 bits),
AnnaBridge	143:86740a56073b	241	this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
AnnaBridge	143:86740a56073b	242	}ADC_AnalogWDGConfTypeDef;
AnnaBridge	143:86740a56073b	243
AnnaBridge	143:86740a56073b	244	/**
AnnaBridge	143:86740a56073b	245	* @}
AnnaBridge	143:86740a56073b	246	*/
AnnaBridge	143:86740a56073b	247
AnnaBridge	143:86740a56073b	248
AnnaBridge	143:86740a56073b	249	/* Exported constants --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	250
AnnaBridge	143:86740a56073b	251	/** @defgroup ADC_Exported_Constants ADC Exported Constants
AnnaBridge	143:86740a56073b	252	* @{
AnnaBridge	143:86740a56073b	253	*/
AnnaBridge	143:86740a56073b	254
AnnaBridge	143:86740a56073b	255	/** @defgroup ADC_Error_Code ADC Error Code
AnnaBridge	143:86740a56073b	256	* @{
AnnaBridge	143:86740a56073b	257	*/
AnnaBridge	143:86740a56073b	258	#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /!< No error /
AnnaBridge	143:86740a56073b	259	#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
AnnaBridge	143:86740a56073b	260	enable/disable, erroneous state */
AnnaBridge	143:86740a56073b	261	#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /!< OVR error /
AnnaBridge	143:86740a56073b	262	#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /!< DMA transfer error /
AnnaBridge	143:86740a56073b	263	/**
AnnaBridge	143:86740a56073b	264	* @}
AnnaBridge	143:86740a56073b	265	*/
AnnaBridge	143:86740a56073b	266
AnnaBridge	143:86740a56073b	267	/** @defgroup ADC_TimeOut_Values ADC TimeOut Values
AnnaBridge	143:86740a56073b	268	* @{
AnnaBridge	143:86740a56073b	269	*/
AnnaBridge	143:86740a56073b	270
AnnaBridge	143:86740a56073b	271	/* Fixed timeout values for ADC calibration, enable settling time, disable */
AnnaBridge	143:86740a56073b	272	/* settling time. */
AnnaBridge	143:86740a56073b	273	/* Values defined to be higher than worst cases: low clocks freq, */
AnnaBridge	143:86740a56073b	274	/* maximum prescalers. */
AnnaBridge	143:86740a56073b	275	/* Unit: ms */
AnnaBridge	143:86740a56073b	276	#define ADC_ENABLE_TIMEOUT 10U
AnnaBridge	143:86740a56073b	277	#define ADC_DISABLE_TIMEOUT 10U
AnnaBridge	143:86740a56073b	278	#define ADC_STOP_CONVERSION_TIMEOUT 10U
AnnaBridge	143:86740a56073b	279
AnnaBridge	143:86740a56073b	280	/* Delay of 10us fixed to worst case: maximum CPU frequency 180MHz to have */
AnnaBridge	143:86740a56073b	281	/* the minimum number of CPU cycles to fulfill this delay */
AnnaBridge	143:86740a56073b	282	#define ADC_DELAY_10US_MIN_CPU_CYCLES 1800U
AnnaBridge	143:86740a56073b	283	/**
AnnaBridge	143:86740a56073b	284	* @}
AnnaBridge	143:86740a56073b	285	*/
AnnaBridge	143:86740a56073b	286
AnnaBridge	143:86740a56073b	287	/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
AnnaBridge	143:86740a56073b	288	* @{
AnnaBridge	143:86740a56073b	289	*/
AnnaBridge	143:86740a56073b	290	#define ADC_CLOCK_ASYNC_DIV1 ((uint32_t)0x00000000U) /!< ADC Asynchronous clock mode divided by 1 /
AnnaBridge	143:86740a56073b	291	#define ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	292	#define ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	293	#define ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	294	#define ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	295	#define ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	296	#define ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	297	#define ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	298	#define ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	299	#define ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	300	#define ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	301	#define ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 \| ADC_CCR_PRESC_1 \| ADC_CCR_PRESC_0) /!< ADC Asynchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	302
AnnaBridge	143:86740a56073b	303	#define ADC_CLOCK_SYNC_PCLK_DIV1 ((uint32_t)ADC_CFGR2_CKMODE) /*!< Synchronous clock mode divided by 1
AnnaBridge	143:86740a56073b	304	This configuration must be enabled only if PCLK has a 50%
AnnaBridge	143:86740a56073b	305	duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock
AnnaBridge	143:86740a56073b	306	must by 50% duty cycle)*/
AnnaBridge	143:86740a56073b	307	#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)ADC_CFGR2_CKMODE_0) /!< Synchronous clock mode divided by 2 /
AnnaBridge	143:86740a56073b	308	#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CFGR2_CKMODE_1) /!< Synchronous clock mode divided by 4 /
AnnaBridge	143:86740a56073b	309
AnnaBridge	143:86740a56073b	310	/**
AnnaBridge	143:86740a56073b	311	* @}
AnnaBridge	143:86740a56073b	312	*/
AnnaBridge	143:86740a56073b	313
AnnaBridge	143:86740a56073b	314	/** @defgroup ADC_Resolution ADC Resolution
AnnaBridge	143:86740a56073b	315	* @{
AnnaBridge	143:86740a56073b	316	*/
AnnaBridge	143:86740a56073b	317	#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U) /!< ADC 12-bit resolution /
AnnaBridge	143:86740a56073b	318	#define ADC_RESOLUTION_10B ((uint32_t)ADC_CFGR1_RES_0) /!< ADC 10-bit resolution /
AnnaBridge	143:86740a56073b	319	#define ADC_RESOLUTION_8B ((uint32_t)ADC_CFGR1_RES_1) /!< ADC 8-bit resolution /
AnnaBridge	143:86740a56073b	320	#define ADC_RESOLUTION_6B ((uint32_t)ADC_CFGR1_RES) /!< ADC 6-bit resolution /
AnnaBridge	143:86740a56073b	321	/**
AnnaBridge	143:86740a56073b	322	* @}
AnnaBridge	143:86740a56073b	323	*/
AnnaBridge	143:86740a56073b	324
AnnaBridge	143:86740a56073b	325	/** @defgroup ADC_data_align ADC Data Align
AnnaBridge	143:86740a56073b	326	* @{
AnnaBridge	143:86740a56073b	327	*/
AnnaBridge	143:86740a56073b	328	#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	329	#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CFGR1_ALIGN)
AnnaBridge	143:86740a56073b	330
AnnaBridge	143:86740a56073b	331	/**
AnnaBridge	143:86740a56073b	332	* @}
AnnaBridge	143:86740a56073b	333	*/
AnnaBridge	143:86740a56073b	334
AnnaBridge	143:86740a56073b	335	/** @defgroup ADC_Regular_External_Trigger_Source_Edge ADC External Trigger Source Edge for Regular Group
AnnaBridge	143:86740a56073b	336	* @{
AnnaBridge	143:86740a56073b	337	*/
AnnaBridge	143:86740a56073b	338	#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	339	#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CFGR1_EXTEN_0)
AnnaBridge	143:86740a56073b	340	#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CFGR1_EXTEN_1)
AnnaBridge	143:86740a56073b	341	#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CFGR1_EXTEN)
AnnaBridge	143:86740a56073b	342	/**
AnnaBridge	143:86740a56073b	343	* @}
AnnaBridge	143:86740a56073b	344	*/
AnnaBridge	143:86740a56073b	345
AnnaBridge	143:86740a56073b	346	/** @defgroup ADC_EOCSelection ADC EOC Selection
AnnaBridge	143:86740a56073b	347	* @{
AnnaBridge	143:86740a56073b	348	*/
AnnaBridge	143:86740a56073b	349	#define ADC_EOC_SINGLE_CONV ((uint32_t) ADC_ISR_EOC)
AnnaBridge	143:86740a56073b	350	#define ADC_EOC_SEQ_CONV ((uint32_t) ADC_ISR_EOS)
AnnaBridge	143:86740a56073b	351	#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)(ADC_ISR_EOC \| ADC_ISR_EOS)) /!< reserved for future use /
AnnaBridge	143:86740a56073b	352	/**
AnnaBridge	143:86740a56073b	353	* @}
AnnaBridge	143:86740a56073b	354	*/
AnnaBridge	143:86740a56073b	355
AnnaBridge	143:86740a56073b	356	/** @defgroup ADC_Overrun ADC Overrun
AnnaBridge	143:86740a56073b	357	* @{
AnnaBridge	143:86740a56073b	358	*/
AnnaBridge	143:86740a56073b	359	#define ADC_OVR_DATA_PRESERVED ((uint32_t)0x00000000U)
AnnaBridge	143:86740a56073b	360	#define ADC_OVR_DATA_OVERWRITTEN ((uint32_t)ADC_CFGR1_OVRMOD)
AnnaBridge	143:86740a56073b	361	/**
AnnaBridge	143:86740a56073b	362	* @}
AnnaBridge	143:86740a56073b	363	*/
AnnaBridge	143:86740a56073b	364
AnnaBridge	143:86740a56073b	365
AnnaBridge	143:86740a56073b	366	/** @defgroup ADC_rank ADC rank
AnnaBridge	143:86740a56073b	367	* @{
AnnaBridge	143:86740a56073b	368	*/
AnnaBridge	143:86740a56073b	369	#define ADC_RANK_CHANNEL_NUMBER ((uint32_t)0x00001000U) /!< Enable the rank of the selected channels. Number of ranks in the sequence is defined by number of channels enabled, rank of each channel is defined by channel number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) /
AnnaBridge	143:86740a56073b	370	#define ADC_RANK_NONE ((uint32_t)0x00001001U) /!< Disable the selected rank (selected channel) from sequencer /
AnnaBridge	143:86740a56073b	371	/**
AnnaBridge	143:86740a56073b	372	* @}
AnnaBridge	143:86740a56073b	373	*/
AnnaBridge	143:86740a56073b	374
AnnaBridge	143:86740a56073b	375
AnnaBridge	143:86740a56073b	376	/** @defgroup ADC_channels ADC_Channels
AnnaBridge	143:86740a56073b	377	* @{
AnnaBridge	143:86740a56073b	378	*/
AnnaBridge	143:86740a56073b	379	#define ADC_CHANNEL_0 ((uint32_t)(ADC_CHSELR_CHSEL0))
AnnaBridge	143:86740a56073b	380	#define ADC_CHANNEL_1 ((uint32_t)(ADC_CHSELR_CHSEL1) \| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	381	#define ADC_CHANNEL_2 ((uint32_t)(ADC_CHSELR_CHSEL2) \| ADC_CFGR1_AWDCH_1)
AnnaBridge	143:86740a56073b	382	#define ADC_CHANNEL_3 ((uint32_t)(ADC_CHSELR_CHSEL3)\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	383	#define ADC_CHANNEL_4 ((uint32_t)(ADC_CHSELR_CHSEL4)\| ADC_CFGR1_AWDCH_2)
AnnaBridge	143:86740a56073b	384	#define ADC_CHANNEL_5 ((uint32_t)(ADC_CHSELR_CHSEL5)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	385	#define ADC_CHANNEL_6 ((uint32_t)(ADC_CHSELR_CHSEL6)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
AnnaBridge	143:86740a56073b	386	#define ADC_CHANNEL_7 ((uint32_t)(ADC_CHSELR_CHSEL7)\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1 \| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	387	#define ADC_CHANNEL_8 ((uint32_t)(ADC_CHSELR_CHSEL8)\| ADC_CFGR1_AWDCH_3)
AnnaBridge	143:86740a56073b	388	#define ADC_CHANNEL_9 ((uint32_t)(ADC_CHSELR_CHSEL9)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	389	#define ADC_CHANNEL_10 ((uint32_t)(ADC_CHSELR_CHSEL10)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1)
AnnaBridge	143:86740a56073b	390	#define ADC_CHANNEL_11 ((uint32_t)(ADC_CHSELR_CHSEL11)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	391	#define ADC_CHANNEL_12 ((uint32_t)(ADC_CHSELR_CHSEL12)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2)
AnnaBridge	143:86740a56073b	392	#define ADC_CHANNEL_13 ((uint32_t)(ADC_CHSELR_CHSEL13)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	393	#define ADC_CHANNEL_14 ((uint32_t)(ADC_CHSELR_CHSEL14)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1)
AnnaBridge	143:86740a56073b	394	#define ADC_CHANNEL_15 ((uint32_t)(ADC_CHSELR_CHSEL15)\| ADC_CFGR1_AWDCH_3\| ADC_CFGR1_AWDCH_2\| ADC_CFGR1_AWDCH_1\| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	395	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
AnnaBridge	143:86740a56073b	396	#define ADC_CHANNEL_16 ((uint32_t)(ADC_CHSELR_CHSEL16)\| ADC_CFGR1_AWDCH_4)
AnnaBridge	143:86740a56073b	397	#endif
AnnaBridge	143:86740a56073b	398	#define ADC_CHANNEL_17 ((uint32_t)(ADC_CHSELR_CHSEL17)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_0)
AnnaBridge	143:86740a56073b	399	#define ADC_CHANNEL_18 ((uint32_t)(ADC_CHSELR_CHSEL18)\| ADC_CFGR1_AWDCH_4\| ADC_CFGR1_AWDCH_1)
AnnaBridge	143:86740a56073b	400
AnnaBridge	143:86740a56073b	401	/* Internal channels */
AnnaBridge	143:86740a56073b	402	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
AnnaBridge	143:86740a56073b	403	#define ADC_CHANNEL_VLCD ADC_CHANNEL_16
AnnaBridge	143:86740a56073b	404	#endif
AnnaBridge	143:86740a56073b	405	#define ADC_CHANNEL_VREFINT ADC_CHANNEL_17
AnnaBridge	143:86740a56073b	406	#define ADC_CHANNEL_TEMPSENSOR ADC_CHANNEL_18
AnnaBridge	143:86740a56073b	407	/**
AnnaBridge	143:86740a56073b	408	* @}
AnnaBridge	143:86740a56073b	409	*/
AnnaBridge	143:86740a56073b	410
AnnaBridge	143:86740a56073b	411	/** @defgroup ADC_Channel_AWD_Masks ADC Channel Masks
AnnaBridge	143:86740a56073b	412	* @{
AnnaBridge	143:86740a56073b	413	*/
AnnaBridge	143:86740a56073b	414	#define ADC_CHANNEL_MASK ((uint32_t)0x0007FFFFU)
AnnaBridge	143:86740a56073b	415	#define ADC_CHANNEL_AWD_MASK ((uint32_t)0x7C000000U)
AnnaBridge	143:86740a56073b	416	/**
AnnaBridge	143:86740a56073b	417	* @}
AnnaBridge	143:86740a56073b	418	*/
AnnaBridge	143:86740a56073b	419
AnnaBridge	143:86740a56073b	420
AnnaBridge	143:86740a56073b	421	/** @defgroup ADC_sampling_times ADC Sampling Cycles
AnnaBridge	143:86740a56073b	422	* @{
AnnaBridge	143:86740a56073b	423	*/
AnnaBridge	143:86740a56073b	424
AnnaBridge	143:86740a56073b	425	#define ADC_SAMPLETIME_1CYCLE_5 ((uint32_t)0x00000000U) /!< ADC sampling time 1.5 cycle /
AnnaBridge	143:86740a56073b	426	#define ADC_SAMPLETIME_7CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_0) /!< ADC sampling time 7.5 CYCLES /
AnnaBridge	143:86740a56073b	427	#define ADC_SAMPLETIME_13CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_1) /!< ADC sampling time 13.5 CYCLES /
AnnaBridge	143:86740a56073b	428	#define ADC_SAMPLETIME_28CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_1 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 28.5 CYCLES /
AnnaBridge	143:86740a56073b	429	#define ADC_SAMPLETIME_41CYCLES_5 ((uint32_t)ADC_SMPR_SMPR_2) /!< ADC sampling time 41.5 CYCLES /
AnnaBridge	143:86740a56073b	430	#define ADC_SAMPLETIME_55CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_0)) /!< ADC sampling time 55.5 CYCLES /
AnnaBridge	143:86740a56073b	431	#define ADC_SAMPLETIME_71CYCLES_5 ((uint32_t)(ADC_SMPR_SMPR_2 \| ADC_SMPR_SMPR_1)) /!< ADC sampling time 71.5 CYCLES /
AnnaBridge	143:86740a56073b	432	#define ADC_SAMPLETIME_239CYCLES_5 ((uint32_t)ADC_SMPR_SMPR) /!< ADC sampling time 239.5 CYCLES /
AnnaBridge	143:86740a56073b	433	/**
AnnaBridge	143:86740a56073b	434	* @}
AnnaBridge	143:86740a56073b	435	*/
AnnaBridge	143:86740a56073b	436
AnnaBridge	143:86740a56073b	437
AnnaBridge	143:86740a56073b	438	/** @defgroup ADC_Scan_mode ADC Scan mode
AnnaBridge	143:86740a56073b	439	* @{
AnnaBridge	143:86740a56073b	440	*/
AnnaBridge	143:86740a56073b	441	/* Note: Scan mode values must be compatible with other STM32 devices having */
AnnaBridge	143:86740a56073b	442	/* a configurable sequencer. */
AnnaBridge	143:86740a56073b	443	/* Scan direction setting values are defined by taking in account */
AnnaBridge	143:86740a56073b	444	/* already defined values for other STM32 devices: */
AnnaBridge	143:86740a56073b	445	/* ADC_SCAN_DISABLE ((uint32_t)0x00000000) */
AnnaBridge	143:86740a56073b	446	/* ADC_SCAN_ENABLE ((uint32_t)0x00000001) */
AnnaBridge	143:86740a56073b	447	/* Scan direction forward is considered as default setting equivalent */
AnnaBridge	143:86740a56073b	448	/* to scan enable. */
AnnaBridge	143:86740a56073b	449	/* Scan direction backward is considered as additional setting. */
AnnaBridge	143:86740a56073b	450	/* In case of migration from another STM32 device, the user will be */
AnnaBridge	143:86740a56073b	451	/* warned of change of setting choices with assert check. */
AnnaBridge	143:86740a56073b	452	#define ADC_SCAN_DIRECTION_FORWARD ((uint32_t)0x00000001U) /!< Scan direction forward: from channel 0 to channel 18 /
AnnaBridge	143:86740a56073b	453	#define ADC_SCAN_DIRECTION_BACKWARD ((uint32_t)0x00000002U) /!< Scan direction backward: from channel 18 to channel 0 /
AnnaBridge	143:86740a56073b	454
AnnaBridge	143:86740a56073b	455	#define ADC_SCAN_ENABLE ADC_SCAN_DIRECTION_FORWARD /* For compatibility with other STM32 devices */
AnnaBridge	143:86740a56073b	456	/**
AnnaBridge	143:86740a56073b	457	* @}
AnnaBridge	143:86740a56073b	458	*/
AnnaBridge	143:86740a56073b	459
AnnaBridge	143:86740a56073b	460	/** @defgroup ADC_Oversampling_Ratio ADC Oversampling Ratio
AnnaBridge	143:86740a56073b	461	* @{
AnnaBridge	143:86740a56073b	462	*/
AnnaBridge	143:86740a56073b	463
AnnaBridge	143:86740a56073b	464	#define ADC_OVERSAMPLING_RATIO_2 ((uint32_t)0x00000000U) /!< ADC Oversampling ratio 2x /
AnnaBridge	143:86740a56073b	465	#define ADC_OVERSAMPLING_RATIO_4 ((uint32_t)0x00000004U) /!< ADC Oversampling ratio 4x /
AnnaBridge	143:86740a56073b	466	#define ADC_OVERSAMPLING_RATIO_8 ((uint32_t)0x00000008U) /!< ADC Oversampling ratio 8x /
AnnaBridge	143:86740a56073b	467	#define ADC_OVERSAMPLING_RATIO_16 ((uint32_t)0x0000000CU) /!< ADC Oversampling ratio 16x /
AnnaBridge	143:86740a56073b	468	#define ADC_OVERSAMPLING_RATIO_32 ((uint32_t)0x00000010U) /!< ADC Oversampling ratio 32x /
AnnaBridge	143:86740a56073b	469	#define ADC_OVERSAMPLING_RATIO_64 ((uint32_t)0x00000014U) /!< ADC Oversampling ratio 64x /
AnnaBridge	143:86740a56073b	470	#define ADC_OVERSAMPLING_RATIO_128 ((uint32_t)0x00000018U) /!< ADC Oversampling ratio 128x /
AnnaBridge	143:86740a56073b	471	#define ADC_OVERSAMPLING_RATIO_256 ((uint32_t)0x0000001CU) /!< ADC Oversampling ratio 256x /
AnnaBridge	143:86740a56073b	472	/**
AnnaBridge	143:86740a56073b	473	* @}
AnnaBridge	143:86740a56073b	474	*/
AnnaBridge	143:86740a56073b	475
AnnaBridge	143:86740a56073b	476	/** @defgroup ADC_Right_Bit_Shift ADC Right Bit Shift
AnnaBridge	143:86740a56073b	477	* @{
AnnaBridge	143:86740a56073b	478	*/
AnnaBridge	143:86740a56073b	479	#define ADC_RIGHTBITSHIFT_NONE ((uint32_t)0x00000000U) /!< ADC No bit shift for oversampling /
AnnaBridge	143:86740a56073b	480	#define ADC_RIGHTBITSHIFT_1 ((uint32_t)0x00000020U) /!< ADC 1 bit shift for oversampling /
AnnaBridge	143:86740a56073b	481	#define ADC_RIGHTBITSHIFT_2 ((uint32_t)0x00000040U) /!< ADC 2 bits shift for oversampling /
AnnaBridge	143:86740a56073b	482	#define ADC_RIGHTBITSHIFT_3 ((uint32_t)0x00000060U) /!< ADC 3 bits shift for oversampling /
AnnaBridge	143:86740a56073b	483	#define ADC_RIGHTBITSHIFT_4 ((uint32_t)0x00000080U) /!< ADC 4 bits shift for oversampling /
AnnaBridge	143:86740a56073b	484	#define ADC_RIGHTBITSHIFT_5 ((uint32_t)0x000000A0U) /!< ADC 5 bits shift for oversampling /
AnnaBridge	143:86740a56073b	485	#define ADC_RIGHTBITSHIFT_6 ((uint32_t)0x000000C0U) /!< ADC 6 bits shift for oversampling /
AnnaBridge	143:86740a56073b	486	#define ADC_RIGHTBITSHIFT_7 ((uint32_t)0x000000E0U) /!< ADC 7 bits shift for oversampling /
AnnaBridge	143:86740a56073b	487	#define ADC_RIGHTBITSHIFT_8 ((uint32_t)0x00000100U) /!< ADC 8 bits shift for oversampling /
AnnaBridge	143:86740a56073b	488	/**
AnnaBridge	143:86740a56073b	489	* @}
AnnaBridge	143:86740a56073b	490	*/
AnnaBridge	143:86740a56073b	491
AnnaBridge	143:86740a56073b	492	/** @defgroup ADC_Triggered_Oversampling_Mode ADC Triggered Oversampling Mode
AnnaBridge	143:86740a56073b	493	* @{
AnnaBridge	143:86740a56073b	494	*/
AnnaBridge	143:86740a56073b	495	#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER ((uint32_t)0x00000000U) /!< ADC No bit shift for oversampling /
AnnaBridge	143:86740a56073b	496	#define ADC_TRIGGEREDMODE_MULTI_TRIGGER ((uint32_t)0x00000200U) /!< ADC No bit shift for oversampling /
AnnaBridge	143:86740a56073b	497	/**
AnnaBridge	143:86740a56073b	498	* @}
AnnaBridge	143:86740a56073b	499	*/
AnnaBridge	143:86740a56073b	500
AnnaBridge	143:86740a56073b	501	/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
AnnaBridge	143:86740a56073b	502	* @{
AnnaBridge	143:86740a56073b	503	*/
AnnaBridge	143:86740a56073b	504	#define ADC_ANALOGWATCHDOG_NONE ((uint32_t) 0x00000000U)
AnnaBridge	143:86740a56073b	505	#define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CFGR1_AWDSGL \| ADC_CFGR1_AWDEN))
AnnaBridge	143:86740a56073b	506	#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t) ADC_CFGR1_AWDEN)
AnnaBridge	143:86740a56073b	507	/**
AnnaBridge	143:86740a56073b	508	* @}
AnnaBridge	143:86740a56073b	509	*/
AnnaBridge	143:86740a56073b	510
AnnaBridge	143:86740a56073b	511	/** @defgroup ADC_conversion_type ADC Conversion Group
AnnaBridge	143:86740a56073b	512	* @{
AnnaBridge	143:86740a56073b	513	*/
AnnaBridge	143:86740a56073b	514	#define ADC_REGULAR_GROUP ((uint32_t)(ADC_FLAG_EOC \| ADC_FLAG_EOS))
AnnaBridge	143:86740a56073b	515	/**
AnnaBridge	143:86740a56073b	516	* @}
AnnaBridge	143:86740a56073b	517	*/
AnnaBridge	143:86740a56073b	518
AnnaBridge	143:86740a56073b	519	/** @defgroup ADC_Event_type ADC Event
AnnaBridge	143:86740a56073b	520	* @{
AnnaBridge	143:86740a56073b	521	*/
AnnaBridge	143:86740a56073b	522	#define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
AnnaBridge	143:86740a56073b	523	#define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
AnnaBridge	143:86740a56073b	524	/**
AnnaBridge	143:86740a56073b	525	* @}
AnnaBridge	143:86740a56073b	526	*/
AnnaBridge	143:86740a56073b	527
AnnaBridge	143:86740a56073b	528	/** @defgroup ADC_interrupts_definition ADC Interrupts Definition
AnnaBridge	143:86740a56073b	529	* @{
AnnaBridge	143:86740a56073b	530	*/
AnnaBridge	143:86740a56073b	531	#define ADC_IT_RDY ADC_IER_ADRDYIE /!< ADC Ready (ADRDY) interrupt source /
AnnaBridge	143:86740a56073b	532	#define ADC_IT_EOSMP ADC_IER_EOSMPIE /!< ADC End of Sampling interrupt source /
AnnaBridge	143:86740a56073b	533	#define ADC_IT_EOC ADC_IER_EOCIE /!< ADC End of Regular Conversion interrupt source /
AnnaBridge	143:86740a56073b	534	#define ADC_IT_EOS ADC_IER_EOSEQIE /!< ADC End of Regular sequence of Conversions interrupt source /
AnnaBridge	143:86740a56073b	535	#define ADC_IT_OVR ADC_IER_OVRIE /!< ADC overrun interrupt source /
AnnaBridge	143:86740a56073b	536	#define ADC_IT_AWD ADC_IER_AWDIE /!< ADC Analog watchdog 1 interrupt source /
AnnaBridge	143:86740a56073b	537	#define ADC_IT_EOCAL ADC_IER_EOCALIE /!< ADC End of Calibration interrupt source /
AnnaBridge	143:86740a56073b	538	/**
AnnaBridge	143:86740a56073b	539	* @}
AnnaBridge	143:86740a56073b	540	*/
AnnaBridge	143:86740a56073b	541
AnnaBridge	143:86740a56073b	542
AnnaBridge	143:86740a56073b	543
AnnaBridge	143:86740a56073b	544	/** @defgroup ADC_flags_definition ADC Flags Definition
AnnaBridge	143:86740a56073b	545	* @{
AnnaBridge	143:86740a56073b	546	*/
AnnaBridge	143:86740a56073b	547	#define ADC_FLAG_RDY ADC_ISR_ADRDY /!< ADC Ready (ADRDY) flag /
AnnaBridge	143:86740a56073b	548	#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /!< ADC End of Sampling flag /
AnnaBridge	143:86740a56073b	549	#define ADC_FLAG_EOC ADC_ISR_EOC /!< ADC End of Regular Conversion flag /
AnnaBridge	143:86740a56073b	550	#define ADC_FLAG_EOS ADC_ISR_EOSEQ /!< ADC End of Regular sequence of Conversions flag /
AnnaBridge	143:86740a56073b	551	#define ADC_FLAG_OVR ADC_ISR_OVR /!< ADC overrun flag /
AnnaBridge	143:86740a56073b	552	#define ADC_FLAG_AWD ADC_ISR_AWD /!< ADC Analog watchdog flag /
AnnaBridge	143:86740a56073b	553	#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /!< ADC Enf Of Calibration flag /
AnnaBridge	143:86740a56073b	554
AnnaBridge	143:86740a56073b	555
AnnaBridge	143:86740a56073b	556	#define ADC_FLAG_ALL (ADC_FLAG_RDY \| ADC_FLAG_EOSMP \| ADC_FLAG_EOC \| ADC_FLAG_EOS \| \
AnnaBridge	143:86740a56073b	557	ADC_FLAG_OVR \| ADC_FLAG_AWD \| ADC_FLAG_EOCAL)
AnnaBridge	143:86740a56073b	558	/**
AnnaBridge	143:86740a56073b	559	* @}
AnnaBridge	143:86740a56073b	560	*/
AnnaBridge	143:86740a56073b	561
AnnaBridge	143:86740a56073b	562	/**
AnnaBridge	143:86740a56073b	563	* @}
AnnaBridge	143:86740a56073b	564	*/
AnnaBridge	143:86740a56073b	565	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	143:86740a56073b	566
AnnaBridge	143:86740a56073b	567	/** @defgroup ADC_Exported_Macro ADC Exported Macro
AnnaBridge	143:86740a56073b	568	* @{
AnnaBridge	143:86740a56073b	569	*/
AnnaBridge	143:86740a56073b	570	/** @brief Reset ADC handle state
AnnaBridge	143:86740a56073b	571	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	572	* @retval None
AnnaBridge	143:86740a56073b	573	*/
AnnaBridge	143:86740a56073b	574	#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
AnnaBridge	143:86740a56073b	575
AnnaBridge	143:86740a56073b	576	/**
AnnaBridge	143:86740a56073b	577	* @brief Enable the ADC peripheral
AnnaBridge	143:86740a56073b	578	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	579	* @retval None
AnnaBridge	143:86740a56073b	580	*/
AnnaBridge	143:86740a56073b	581	#define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
AnnaBridge	143:86740a56073b	582
AnnaBridge	143:86740a56073b	583	/**
AnnaBridge	143:86740a56073b	584	* @brief Verification of hardware constraints before ADC can be enabled
AnnaBridge	143:86740a56073b	585	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	586	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
AnnaBridge	143:86740a56073b	587	*/
AnnaBridge	143:86740a56073b	588	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
AnnaBridge	143:86740a56073b	589	(( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge	143:86740a56073b	590	(ADC_CR_ADCAL \| ADC_CR_ADSTP \| ADC_CR_ADSTART \| \
AnnaBridge	143:86740a56073b	591	ADC_CR_ADDIS \| ADC_CR_ADEN ) \
AnnaBridge	143:86740a56073b	592	) == RESET \
AnnaBridge	143:86740a56073b	593	) ? SET : RESET)
AnnaBridge	143:86740a56073b	594
AnnaBridge	143:86740a56073b	595	/**
AnnaBridge	143:86740a56073b	596	* @brief Disable the ADC peripheral
AnnaBridge	143:86740a56073b	597	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	598	* @retval None
AnnaBridge	143:86740a56073b	599	*/
AnnaBridge	143:86740a56073b	600	#define __HAL_ADC_DISABLE(__HANDLE__) \
AnnaBridge	143:86740a56073b	601	do{ \
AnnaBridge	143:86740a56073b	602	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
AnnaBridge	143:86740a56073b	603	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
AnnaBridge	143:86740a56073b	604	} while(0)
AnnaBridge	143:86740a56073b	605
AnnaBridge	143:86740a56073b	606	/**
AnnaBridge	143:86740a56073b	607	* @brief Verification of hardware constraints before ADC can be disabled
AnnaBridge	143:86740a56073b	608	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	609	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
AnnaBridge	143:86740a56073b	610	*/
AnnaBridge	143:86740a56073b	611	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
AnnaBridge	143:86740a56073b	612	(( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge	143:86740a56073b	613	(ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
AnnaBridge	143:86740a56073b	614	) ? SET : RESET)
AnnaBridge	143:86740a56073b	615
AnnaBridge	143:86740a56073b	616	/**
AnnaBridge	143:86740a56073b	617	* @brief Verification of ADC state: enabled or disabled
AnnaBridge	143:86740a56073b	618	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	619	* @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge	143:86740a56073b	620	*/
AnnaBridge	143:86740a56073b	621	#define ADC_IS_ENABLE(__HANDLE__) \
AnnaBridge	143:86740a56073b	622	(( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
AnnaBridge	143:86740a56073b	623	((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
AnnaBridge	143:86740a56073b	624	) ? SET : RESET)
AnnaBridge	143:86740a56073b	625
AnnaBridge	143:86740a56073b	626	/**
AnnaBridge	143:86740a56073b	627	* @brief Returns resolution bits in CFGR register: RES[1:0]. Return value among parameter to @ref ADC_Resolution.
AnnaBridge	143:86740a56073b	628	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	629	* @retval None
AnnaBridge	143:86740a56073b	630	*/
AnnaBridge	143:86740a56073b	631	#define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR1) & ADC_CFGR1_RES)
AnnaBridge	143:86740a56073b	632	/**
AnnaBridge	143:86740a56073b	633	* @brief Test if conversion trigger of regular group is software start
AnnaBridge	143:86740a56073b	634	* or external trigger.
AnnaBridge	143:86740a56073b	635	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	636	* @retval SET (software start) or RESET (external trigger)
AnnaBridge	143:86740a56073b	637	*/
AnnaBridge	143:86740a56073b	638	#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
AnnaBridge	143:86740a56073b	639	(((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == RESET)
AnnaBridge	143:86740a56073b	640
AnnaBridge	143:86740a56073b	641
AnnaBridge	143:86740a56073b	642
AnnaBridge	143:86740a56073b	643	/**
AnnaBridge	143:86740a56073b	644	* @brief Check if no conversion on going on regular group
AnnaBridge	143:86740a56073b	645	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	646	* @retval SET (conversion is on going) or RESET (no conversion is on going)
AnnaBridge	143:86740a56073b	647	*/
AnnaBridge	143:86740a56073b	648	#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \
AnnaBridge	143:86740a56073b	649	(( (((__HANDLE__)->Instance->CR) & ADC_CR_ADSTART) == RESET \
AnnaBridge	143:86740a56073b	650	) ? RESET : SET)
AnnaBridge	143:86740a56073b	651
AnnaBridge	143:86740a56073b	652	/**
AnnaBridge	143:86740a56073b	653	* @brief Enable ADC continuous conversion mode.
AnnaBridge	143:86740a56073b	654	* @param _CONTINUOUS_MODE_: Continuous mode.
AnnaBridge	143:86740a56073b	655	* @retval None
AnnaBridge	143:86740a56073b	656	*/
AnnaBridge	143:86740a56073b	657	#define ADC_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
AnnaBridge	143:86740a56073b	658
AnnaBridge	143:86740a56073b	659	/**
AnnaBridge	143:86740a56073b	660	* @brief Enable ADC scan mode to convert multiple ranks with sequencer.
AnnaBridge	143:86740a56073b	661	* @param _SCAN_MODE_: Scan conversion mode.
AnnaBridge	143:86740a56073b	662	* @retval None
AnnaBridge	143:86740a56073b	663	*/
AnnaBridge	143:86740a56073b	664	#define ADC_SCANDIR(_SCAN_MODE_) \
AnnaBridge	143:86740a56073b	665	( ( (_SCAN_MODE_) == (ADC_SCAN_DIRECTION_BACKWARD) \
AnnaBridge	143:86740a56073b	666	)? (ADC_CFGR1_SCANDIR) : (0x00000000U) \
AnnaBridge	143:86740a56073b	667	)
AnnaBridge	143:86740a56073b	668
AnnaBridge	143:86740a56073b	669	/**
AnnaBridge	143:86740a56073b	670	* @brief Configures the number of discontinuous conversions for the regular group channels.
AnnaBridge	143:86740a56073b	671	* @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
AnnaBridge	143:86740a56073b	672	* @retval None
AnnaBridge	143:86740a56073b	673	*/
AnnaBridge	143:86740a56073b	674	#define __HAL_ADC_CFGR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
AnnaBridge	143:86740a56073b	675
AnnaBridge	143:86740a56073b	676	/**
AnnaBridge	143:86740a56073b	677	* @brief Enable the ADC DMA continuous request.
AnnaBridge	143:86740a56073b	678	* @param _DMAContReq_MODE_: DMA continuous request mode.
AnnaBridge	143:86740a56073b	679	* @retval None
AnnaBridge	143:86740a56073b	680	*/
AnnaBridge	143:86740a56073b	681	#define ADC_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 1U)
AnnaBridge	143:86740a56073b	682
AnnaBridge	143:86740a56073b	683	/**
AnnaBridge	143:86740a56073b	684	* @brief Enable the ADC Auto Delay.
AnnaBridge	143:86740a56073b	685	* @param _AutoDelay_: Auto delay bit enable or disable.
AnnaBridge	143:86740a56073b	686	* @retval None
AnnaBridge	143:86740a56073b	687	*/
AnnaBridge	143:86740a56073b	688	#define __HAL_ADC_CFGR1_AutoDelay(_AutoDelay_) ((_AutoDelay_) << 14U)
AnnaBridge	143:86740a56073b	689
AnnaBridge	143:86740a56073b	690	/**
AnnaBridge	143:86740a56073b	691	* @brief Enable the ADC LowPowerAutoPowerOff.
AnnaBridge	143:86740a56073b	692	* @param _AUTOFF_: AutoOff bit enable or disable.
AnnaBridge	143:86740a56073b	693	* @retval None
AnnaBridge	143:86740a56073b	694	*/
AnnaBridge	143:86740a56073b	695	#define __HAL_ADC_CFGR1_AUTOFF(_AUTOFF_) ((_AUTOFF_) << 15U)
AnnaBridge	143:86740a56073b	696
AnnaBridge	143:86740a56073b	697	/**
AnnaBridge	143:86740a56073b	698	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
AnnaBridge	143:86740a56073b	699	* @param _Threshold_: Threshold value
AnnaBridge	143:86740a56073b	700	* @retval None
AnnaBridge	143:86740a56073b	701	*/
AnnaBridge	143:86740a56073b	702	#define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
AnnaBridge	143:86740a56073b	703
AnnaBridge	143:86740a56073b	704	/**
AnnaBridge	143:86740a56073b	705	* @brief Enable the ADC Low Frequency mode.
AnnaBridge	143:86740a56073b	706	* @param _LOW_FREQUENCY_MODE_: Low Frequency mode.
AnnaBridge	143:86740a56073b	707	* @retval None
AnnaBridge	143:86740a56073b	708	*/
AnnaBridge	143:86740a56073b	709	#define __HAL_ADC_CCR_LOWFREQUENCY(_LOW_FREQUENCY_MODE_) ((_LOW_FREQUENCY_MODE_) << 25U)
AnnaBridge	143:86740a56073b	710
AnnaBridge	143:86740a56073b	711	/**
AnnaBridge	143:86740a56073b	712	* @brief Shift the offset in function of the selected ADC resolution.
AnnaBridge	143:86740a56073b	713	* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0
AnnaBridge	143:86740a56073b	714	* If resolution 12 bits, no shift.
AnnaBridge	143:86740a56073b	715	* If resolution 10 bits, shift of 2 ranks on the right.
AnnaBridge	143:86740a56073b	716	* If resolution 8 bits, shift of 4 ranks on the right.
AnnaBridge	143:86740a56073b	717	* If resolution 6 bits, shift of 6 ranks on the right.
AnnaBridge	143:86740a56073b	718	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
AnnaBridge	143:86740a56073b	719	* @param __HANDLE__: ADC handle.
AnnaBridge	143:86740a56073b	720	* @param _Offset_: Value to be shifted
AnnaBridge	143:86740a56073b	721	* @retval None
AnnaBridge	143:86740a56073b	722	*/
AnnaBridge	143:86740a56073b	723	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_) \
AnnaBridge	143:86740a56073b	724	((_Offset_) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR1_RES) >> 3U)*2U))
AnnaBridge	143:86740a56073b	725
AnnaBridge	143:86740a56073b	726	/**
AnnaBridge	143:86740a56073b	727	* @brief Shift the AWD1 threshold in function of the selected ADC resolution.
AnnaBridge	143:86740a56073b	728	* Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0
AnnaBridge	143:86740a56073b	729	* If resolution 12 bits, no shift.
AnnaBridge	143:86740a56073b	730	* If resolution 10 bits, shift of 2 ranks on the right.
AnnaBridge	143:86740a56073b	731	* If resolution 8 bits, shift of 4 ranks on the right.
AnnaBridge	143:86740a56073b	732	* If resolution 6 bits, shift of 6 ranks on the right.
AnnaBridge	143:86740a56073b	733	* therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
AnnaBridge	143:86740a56073b	734	* @param __HANDLE__: ADC handle.
AnnaBridge	143:86740a56073b	735	* @param _Threshold_: Value to be shifted
AnnaBridge	143:86740a56073b	736	* @retval None
AnnaBridge	143:86740a56073b	737	*/
AnnaBridge	143:86740a56073b	738	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \
AnnaBridge	143:86740a56073b	739	((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
AnnaBridge	143:86740a56073b	740
AnnaBridge	143:86740a56073b	741	/**
AnnaBridge	143:86740a56073b	742	* @brief Shift the value on the left, less significant are set to 0.
AnnaBridge	143:86740a56073b	743	* @param _Value_: Value to be shifted
AnnaBridge	143:86740a56073b	744	* @param _Shift_: Number of shift to be done
AnnaBridge	143:86740a56073b	745	* @retval None
AnnaBridge	143:86740a56073b	746	*/
AnnaBridge	143:86740a56073b	747	#define __HAL_ADC_Value_Shift_left(_Value_, _Shift_) ((_Value_) << (_Shift_))
AnnaBridge	143:86740a56073b	748
AnnaBridge	143:86740a56073b	749
AnnaBridge	143:86740a56073b	750	/**
AnnaBridge	143:86740a56073b	751	* @brief Enable the ADC end of conversion interrupt.
AnnaBridge	143:86740a56073b	752	* @param __HANDLE__: ADC handle.
AnnaBridge	143:86740a56073b	753	* @param __INTERRUPT__: ADC Interrupt.
AnnaBridge	143:86740a56073b	754	* @retval None
AnnaBridge	143:86740a56073b	755	*/
AnnaBridge	143:86740a56073b	756	#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge	143:86740a56073b	757	(((__HANDLE__)->Instance->IER) \|= (__INTERRUPT__))
AnnaBridge	143:86740a56073b	758
AnnaBridge	143:86740a56073b	759	/**
AnnaBridge	143:86740a56073b	760	* @brief Disable the ADC end of conversion interrupt.
AnnaBridge	143:86740a56073b	761	* @param __HANDLE__: ADC handle.
AnnaBridge	143:86740a56073b	762	* @param __INTERRUPT__: ADC interrupt.
AnnaBridge	143:86740a56073b	763	* @retval None
AnnaBridge	143:86740a56073b	764	*/
AnnaBridge	143:86740a56073b	765	#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
AnnaBridge	143:86740a56073b	766	(((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
AnnaBridge	143:86740a56073b	767
AnnaBridge	143:86740a56073b	768	/** @brief Checks if the specified ADC interrupt source is enabled or disabled.
AnnaBridge	143:86740a56073b	769	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	770	* @param __INTERRUPT__: ADC interrupt source to check
AnnaBridge	143:86740a56073b	771	* @arg ...
AnnaBridge	143:86740a56073b	772	* @arg ...
AnnaBridge	143:86740a56073b	773	* @retval State of interruption (TRUE or FALSE)
AnnaBridge	143:86740a56073b	774	*/
AnnaBridge	143:86740a56073b	775	#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
AnnaBridge	143:86740a56073b	776	(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge	143:86740a56073b	777
AnnaBridge	143:86740a56073b	778	/**
AnnaBridge	143:86740a56073b	779	* @brief Clear the ADC's pending flags
AnnaBridge	143:86740a56073b	780	* @param __HANDLE__: ADC handle.
AnnaBridge	143:86740a56073b	781	* @param __FLAG__: ADC flag.
AnnaBridge	143:86740a56073b	782	* @retval None
AnnaBridge	143:86740a56073b	783	*/
AnnaBridge	143:86740a56073b	784	/* Note: bit cleared bit by writing 1 */
AnnaBridge	143:86740a56073b	785	#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge	143:86740a56073b	786	(((__HANDLE__)->Instance->ISR) = (__FLAG__))
AnnaBridge	143:86740a56073b	787
AnnaBridge	143:86740a56073b	788	/**
AnnaBridge	143:86740a56073b	789	* @brief Get the selected ADC's flag status.
AnnaBridge	143:86740a56073b	790	* @param __HANDLE__: ADC handle.
AnnaBridge	143:86740a56073b	791	* @param __FLAG__: ADC flag.
AnnaBridge	143:86740a56073b	792	* @retval None
AnnaBridge	143:86740a56073b	793	*/
AnnaBridge	143:86740a56073b	794	#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
AnnaBridge	143:86740a56073b	795	((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
AnnaBridge	143:86740a56073b	796
AnnaBridge	143:86740a56073b	797
AnnaBridge	143:86740a56073b	798	/**
AnnaBridge	143:86740a56073b	799	* @brief Simultaneously clears and sets specific bits of the handle State
AnnaBridge	143:86740a56073b	800	* @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
AnnaBridge	143:86740a56073b	801	* the first parameter is the ADC handle State, the second parameter is the
AnnaBridge	143:86740a56073b	802	* bit field to clear, the third and last parameter is the bit field to set.
AnnaBridge	143:86740a56073b	803	* @retval None
AnnaBridge	143:86740a56073b	804	*/
AnnaBridge	143:86740a56073b	805	#define ADC_STATE_CLR_SET MODIFY_REG
AnnaBridge	143:86740a56073b	806
AnnaBridge	143:86740a56073b	807	/**
AnnaBridge	143:86740a56073b	808	* @brief Clear ADC error code (set it to error code: "no error")
AnnaBridge	143:86740a56073b	809	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	810	* @retval None
AnnaBridge	143:86740a56073b	811	*/
AnnaBridge	143:86740a56073b	812	#define ADC_CLEAR_ERRORCODE(__HANDLE__) \
AnnaBridge	143:86740a56073b	813	((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
AnnaBridge	143:86740a56073b	814
AnnaBridge	143:86740a56073b	815
AnnaBridge	143:86740a56073b	816
AnnaBridge	143:86740a56073b	817
AnnaBridge	143:86740a56073b	818	/**
AnnaBridge	143:86740a56073b	819	* @brief Configuration of ADC clock & prescaler: clock source PCLK or Asynchronous with selectable prescaler
AnnaBridge	143:86740a56073b	820	* @param __HANDLE__: ADC handle
AnnaBridge	143:86740a56073b	821	* @retval None
AnnaBridge	143:86740a56073b	822	*/
AnnaBridge	143:86740a56073b	823
AnnaBridge	143:86740a56073b	824	#define __HAL_ADC_CLOCK_PRESCALER(__HANDLE__) \
AnnaBridge	143:86740a56073b	825	do{ \
AnnaBridge	143:86740a56073b	826	if ((((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\| \
AnnaBridge	143:86740a56073b	827	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\| \
AnnaBridge	143:86740a56073b	828	(((__HANDLE__)->Init.ClockPrescaler) == ADC_CLOCK_SYNC_PCLK_DIV4)) \
AnnaBridge	143:86740a56073b	829	{ \
AnnaBridge	143:86740a56073b	830	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
AnnaBridge	143:86740a56073b	831	(__HANDLE__)->Instance->CFGR2 \|= (__HANDLE__)->Init.ClockPrescaler; \
AnnaBridge	143:86740a56073b	832	} \
AnnaBridge	143:86740a56073b	833	else \
AnnaBridge	143:86740a56073b	834	{ \
AnnaBridge	143:86740a56073b	835	/* CKMOD bits must be reset */ \
AnnaBridge	143:86740a56073b	836	(__HANDLE__)->Instance->CFGR2 &= ~(ADC_CFGR2_CKMODE); \
AnnaBridge	143:86740a56073b	837	ADC->CCR &= ~(ADC_CCR_PRESC); \
AnnaBridge	143:86740a56073b	838	ADC->CCR \|= (__HANDLE__)->Init.ClockPrescaler; \
AnnaBridge	143:86740a56073b	839	} \
AnnaBridge	143:86740a56073b	840	} while(0)
AnnaBridge	143:86740a56073b	841
AnnaBridge	143:86740a56073b	842
AnnaBridge	143:86740a56073b	843	#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) \|\|\
AnnaBridge	143:86740a56073b	844	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) \|\|\
AnnaBridge	143:86740a56073b	845	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) \|\|\
AnnaBridge	143:86740a56073b	846	((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) \|\|\
AnnaBridge	143:86740a56073b	847	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) \|\|\
AnnaBridge	143:86740a56073b	848	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) \|\|\
AnnaBridge	143:86740a56073b	849	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) \|\|\
AnnaBridge	143:86740a56073b	850	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) \|\|\
AnnaBridge	143:86740a56073b	851	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) \|\|\
AnnaBridge	143:86740a56073b	852	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) \|\|\
AnnaBridge	143:86740a56073b	853	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) \|\|\
AnnaBridge	143:86740a56073b	854	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) \|\|\
AnnaBridge	143:86740a56073b	855	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) \|\|\
AnnaBridge	143:86740a56073b	856	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) \|\|\
AnnaBridge	143:86740a56073b	857	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) \|\|\
AnnaBridge	143:86740a56073b	858	((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
AnnaBridge	143:86740a56073b	859
AnnaBridge	143:86740a56073b	860	#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) \|\| \
AnnaBridge	143:86740a56073b	861	((RESOLUTION) == ADC_RESOLUTION_10B) \|\| \
AnnaBridge	143:86740a56073b	862	((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
AnnaBridge	143:86740a56073b	863	((RESOLUTION) == ADC_RESOLUTION_6B))
AnnaBridge	143:86740a56073b	864
AnnaBridge	143:86740a56073b	865	#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_8B) \|\| \
AnnaBridge	143:86740a56073b	866	((RESOLUTION) == ADC_RESOLUTION_6B))
AnnaBridge	143:86740a56073b	867
AnnaBridge	143:86740a56073b	868	#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) \|\| \
AnnaBridge	143:86740a56073b	869	((ALIGN) == ADC_DATAALIGN_LEFT))
AnnaBridge	143:86740a56073b	870
AnnaBridge	143:86740a56073b	871	#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) \|\| \
AnnaBridge	143:86740a56073b	872	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) \|\| \
AnnaBridge	143:86740a56073b	873	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) \|\| \
AnnaBridge	143:86740a56073b	874	((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
AnnaBridge	143:86740a56073b	875
AnnaBridge	143:86740a56073b	876	#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) \|\| \
AnnaBridge	143:86740a56073b	877	((EOC_SELECTION) == ADC_EOC_SEQ_CONV) \|\| \
AnnaBridge	143:86740a56073b	878	((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV))
AnnaBridge	143:86740a56073b	879
AnnaBridge	143:86740a56073b	880	#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) \|\| \
AnnaBridge	143:86740a56073b	881	((OVR) == ADC_OVR_DATA_OVERWRITTEN))
AnnaBridge	143:86740a56073b	882
AnnaBridge	143:86740a56073b	883	#define IS_ADC_RANK(WATCHDOG) (((WATCHDOG) == ADC_RANK_CHANNEL_NUMBER) \|\| \
AnnaBridge	143:86740a56073b	884	((WATCHDOG) == ADC_RANK_NONE))
AnnaBridge	143:86740a56073b	885
AnnaBridge	143:86740a56073b	886	#if defined (STM32L053xx) \|\| defined (STM32L063xx) \|\| defined (STM32L073xx) \|\| defined (STM32L083xx)
AnnaBridge	143:86740a56073b	887	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
AnnaBridge	143:86740a56073b	888	((CHANNEL) == ADC_CHANNEL_1) \|\| \
AnnaBridge	143:86740a56073b	889	((CHANNEL) == ADC_CHANNEL_2) \|\| \
AnnaBridge	143:86740a56073b	890	((CHANNEL) == ADC_CHANNEL_3) \|\| \
AnnaBridge	143:86740a56073b	891	((CHANNEL) == ADC_CHANNEL_4) \|\| \
AnnaBridge	143:86740a56073b	892	((CHANNEL) == ADC_CHANNEL_5) \|\| \
AnnaBridge	143:86740a56073b	893	((CHANNEL) == ADC_CHANNEL_6) \|\| \
AnnaBridge	143:86740a56073b	894	((CHANNEL) == ADC_CHANNEL_7) \|\| \
AnnaBridge	143:86740a56073b	895	((CHANNEL) == ADC_CHANNEL_8) \|\| \
AnnaBridge	143:86740a56073b	896	((CHANNEL) == ADC_CHANNEL_9) \|\| \
AnnaBridge	143:86740a56073b	897	((CHANNEL) == ADC_CHANNEL_10) \|\| \
AnnaBridge	143:86740a56073b	898	((CHANNEL) == ADC_CHANNEL_11) \|\| \
AnnaBridge	143:86740a56073b	899	((CHANNEL) == ADC_CHANNEL_12) \|\| \
AnnaBridge	143:86740a56073b	900	((CHANNEL) == ADC_CHANNEL_13) \|\| \
AnnaBridge	143:86740a56073b	901	((CHANNEL) == ADC_CHANNEL_14) \|\| \
AnnaBridge	143:86740a56073b	902	((CHANNEL) == ADC_CHANNEL_15) \|\| \
AnnaBridge	143:86740a56073b	903	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	143:86740a56073b	904	((CHANNEL) == ADC_CHANNEL_VREFINT) \|\| \
AnnaBridge	143:86740a56073b	905	((CHANNEL) == ADC_CHANNEL_VLCD))
AnnaBridge	143:86740a56073b	906	#else
AnnaBridge	143:86740a56073b	907	#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) \|\| \
AnnaBridge	143:86740a56073b	908	((CHANNEL) == ADC_CHANNEL_1) \|\| \
AnnaBridge	143:86740a56073b	909	((CHANNEL) == ADC_CHANNEL_2) \|\| \
AnnaBridge	143:86740a56073b	910	((CHANNEL) == ADC_CHANNEL_3) \|\| \
AnnaBridge	143:86740a56073b	911	((CHANNEL) == ADC_CHANNEL_4) \|\| \
AnnaBridge	143:86740a56073b	912	((CHANNEL) == ADC_CHANNEL_5) \|\| \
AnnaBridge	143:86740a56073b	913	((CHANNEL) == ADC_CHANNEL_6) \|\| \
AnnaBridge	143:86740a56073b	914	((CHANNEL) == ADC_CHANNEL_7) \|\| \
AnnaBridge	143:86740a56073b	915	((CHANNEL) == ADC_CHANNEL_8) \|\| \
AnnaBridge	143:86740a56073b	916	((CHANNEL) == ADC_CHANNEL_9) \|\| \
AnnaBridge	143:86740a56073b	917	((CHANNEL) == ADC_CHANNEL_10) \|\| \
AnnaBridge	143:86740a56073b	918	((CHANNEL) == ADC_CHANNEL_11) \|\| \
AnnaBridge	143:86740a56073b	919	((CHANNEL) == ADC_CHANNEL_12) \|\| \
AnnaBridge	143:86740a56073b	920	((CHANNEL) == ADC_CHANNEL_13) \|\| \
AnnaBridge	143:86740a56073b	921	((CHANNEL) == ADC_CHANNEL_14) \|\| \
AnnaBridge	143:86740a56073b	922	((CHANNEL) == ADC_CHANNEL_15) \|\| \
AnnaBridge	143:86740a56073b	923	((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	143:86740a56073b	924	((CHANNEL) == ADC_CHANNEL_VREFINT))
AnnaBridge	143:86740a56073b	925	#endif
AnnaBridge	143:86740a56073b	926
AnnaBridge	143:86740a56073b	927	#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5 ) \|\| \
AnnaBridge	143:86740a56073b	928	((TIME) == ADC_SAMPLETIME_7CYCLES_5 ) \|\| \
AnnaBridge	143:86740a56073b	929	((TIME) == ADC_SAMPLETIME_13CYCLES_5 ) \|\| \
AnnaBridge	143:86740a56073b	930	((TIME) == ADC_SAMPLETIME_28CYCLES_5 ) \|\| \
AnnaBridge	143:86740a56073b	931	((TIME) == ADC_SAMPLETIME_41CYCLES_5 ) \|\| \
AnnaBridge	143:86740a56073b	932	((TIME) == ADC_SAMPLETIME_55CYCLES_5 ) \|\| \
AnnaBridge	143:86740a56073b	933	((TIME) == ADC_SAMPLETIME_71CYCLES_5 ) \|\| \
AnnaBridge	143:86740a56073b	934	((TIME) == ADC_SAMPLETIME_239CYCLES_5))
AnnaBridge	143:86740a56073b	935
AnnaBridge	143:86740a56073b	936	#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DIRECTION_FORWARD) \|\| \
AnnaBridge	143:86740a56073b	937	((SCAN_MODE) == ADC_SCAN_DIRECTION_BACKWARD))
AnnaBridge	143:86740a56073b	938
AnnaBridge	143:86740a56073b	939	#define IS_ADC_OVERSAMPLING_RATIO(RATIO) (((RATIO) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
AnnaBridge	143:86740a56073b	940	((RATIO) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
AnnaBridge	143:86740a56073b	941	((RATIO) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
AnnaBridge	143:86740a56073b	942	((RATIO) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
AnnaBridge	143:86740a56073b	943	((RATIO) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
AnnaBridge	143:86740a56073b	944	((RATIO) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
AnnaBridge	143:86740a56073b	945	((RATIO) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
AnnaBridge	143:86740a56073b	946	((RATIO) == ADC_OVERSAMPLING_RATIO_256 ))
AnnaBridge	143:86740a56073b	947
AnnaBridge	143:86740a56073b	948	#define IS_ADC_RIGHT_BIT_SHIFT(SHIFT) (((SHIFT) == ADC_RIGHTBITSHIFT_NONE) \|\| \
AnnaBridge	143:86740a56073b	949	((SHIFT) == ADC_RIGHTBITSHIFT_1 ) \|\| \
AnnaBridge	143:86740a56073b	950	((SHIFT) == ADC_RIGHTBITSHIFT_2 ) \|\| \
AnnaBridge	143:86740a56073b	951	((SHIFT) == ADC_RIGHTBITSHIFT_3 ) \|\| \
AnnaBridge	143:86740a56073b	952	((SHIFT) == ADC_RIGHTBITSHIFT_4 ) \|\| \
AnnaBridge	143:86740a56073b	953	((SHIFT) == ADC_RIGHTBITSHIFT_5 ) \|\| \
AnnaBridge	143:86740a56073b	954	((SHIFT) == ADC_RIGHTBITSHIFT_6 ) \|\| \
AnnaBridge	143:86740a56073b	955	((SHIFT) == ADC_RIGHTBITSHIFT_7 ) \|\| \
AnnaBridge	143:86740a56073b	956	((SHIFT) == ADC_RIGHTBITSHIFT_8 ))
AnnaBridge	143:86740a56073b	957
AnnaBridge	143:86740a56073b	958	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(MODE) (((MODE) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
AnnaBridge	143:86740a56073b	959	((MODE) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
AnnaBridge	143:86740a56073b	960
AnnaBridge	143:86740a56073b	961	#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE ) \|\| \
AnnaBridge	143:86740a56073b	962	((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
AnnaBridge	143:86740a56073b	963	((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG ))
AnnaBridge	143:86740a56073b	964
AnnaBridge	143:86740a56073b	965	#define IS_ADC_CONVERSION_GROUP(CONVERSION) ((CONVERSION) == ADC_REGULAR_GROUP)
AnnaBridge	143:86740a56073b	966
AnnaBridge	143:86740a56073b	967	#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_AWD_EVENT) \|\| \
AnnaBridge	143:86740a56073b	968	((EVENT) == ADC_OVR_EVENT))
AnnaBridge	143:86740a56073b	969
AnnaBridge	143:86740a56073b	970
AnnaBridge	143:86740a56073b	971	/** @defgroup ADC_range_verification ADC Range Verification
AnnaBridge	143:86740a56073b	972	* in function of ADC resolution selected (12, 10, 8 or 6 bits)
AnnaBridge	143:86740a56073b	973	* @{
AnnaBridge	143:86740a56073b	974	*/
AnnaBridge	143:86740a56073b	975	#define IS_ADC_RANGE(RESOLUTION, ADC_VALUE) \
AnnaBridge	143:86740a56073b	976	((((RESOLUTION) == ADC_RESOLUTION_12B) && ((ADC_VALUE) <= ((uint32_t)0x0FFFU))) \|\| \
AnnaBridge	143:86740a56073b	977	(((RESOLUTION) == ADC_RESOLUTION_10B) && ((ADC_VALUE) <= ((uint32_t)0x03FFU))) \|\| \
AnnaBridge	143:86740a56073b	978	(((RESOLUTION) == ADC_RESOLUTION_8B) && ((ADC_VALUE) <= ((uint32_t)0x00FFU))) \|\| \
AnnaBridge	143:86740a56073b	979	(((RESOLUTION) == ADC_RESOLUTION_6B) && ((ADC_VALUE) <= ((uint32_t)0x003FU))))
AnnaBridge	143:86740a56073b	980	/**
AnnaBridge	143:86740a56073b	981	* @}
AnnaBridge	143:86740a56073b	982	*/
AnnaBridge	143:86740a56073b	983
AnnaBridge	143:86740a56073b	984	/** @defgroup ADC_regular_nb_conv_verification ADC Regular Nb Conversion Verification
AnnaBridge	143:86740a56073b	985	* @{
AnnaBridge	143:86740a56073b	986	*/
AnnaBridge	143:86740a56073b	987	#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1U)) && ((LENGTH) <= ((uint32_t)16U)))
AnnaBridge	143:86740a56073b	988	/**
AnnaBridge	143:86740a56073b	989	* @}
AnnaBridge	143:86740a56073b	990	*/
AnnaBridge	143:86740a56073b	991
AnnaBridge	143:86740a56073b	992	/**
AnnaBridge	143:86740a56073b	993	* @}
AnnaBridge	143:86740a56073b	994	*/
AnnaBridge	143:86740a56073b	995
AnnaBridge	143:86740a56073b	996	/* Include ADC HAL Extension module */
AnnaBridge	143:86740a56073b	997	#include "stm32l0xx_hal_adc_ex.h"
AnnaBridge	143:86740a56073b	998
AnnaBridge	143:86740a56073b	999	/* Exported functions --------------------------------------------------------*/
AnnaBridge	143:86740a56073b	1000	/** @defgroup ADC_Exported_Functions ADC Exported Functions
AnnaBridge	143:86740a56073b	1001	* @{
AnnaBridge	143:86740a56073b	1002	*/
AnnaBridge	143:86740a56073b	1003	/* Initialization and de-initialization functions **********************************/
AnnaBridge	143:86740a56073b	1004	/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
AnnaBridge	143:86740a56073b	1005	* @brief Initialization and de-initialization functions
AnnaBridge	143:86740a56073b	1006	* @{
AnnaBridge	143:86740a56073b	1007	*/
AnnaBridge	143:86740a56073b	1008	HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1009	HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
AnnaBridge	143:86740a56073b	1010	void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1011	void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1012	/**
AnnaBridge	143:86740a56073b	1013	* @}
AnnaBridge	143:86740a56073b	1014	*/
AnnaBridge	143:86740a56073b	1015
AnnaBridge	143:86740a56073b	1016	/* IO operation functions *****************************************************/
AnnaBridge	143:86740a56073b	1017	/** @defgroup ADC_Exported_Functions_Group2 I/O operation functions
AnnaBridge	143:86740a56073b	1018	* @{
AnnaBridge	143:86740a56073b	1019	*/
AnnaBridge	143:86740a56073b	1020	/* Blocking mode: Polling */
AnnaBridge	143:86740a56073b	1021	HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1022	HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1023	HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge	143:86740a56073b	1024	HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
AnnaBridge	143:86740a56073b	1025
AnnaBridge	143:86740a56073b	1026	/* Non-blocking mode: Interruption */
AnnaBridge	143:86740a56073b	1027	HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1028	HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1029
AnnaBridge	143:86740a56073b	1030	/* Non-blocking mode: DMA */
AnnaBridge	143:86740a56073b	1031	HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
AnnaBridge	143:86740a56073b	1032	HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1033
AnnaBridge	143:86740a56073b	1034	/* ADC retrieve conversion value intended to be used with polling or interruption */
AnnaBridge	143:86740a56073b	1035	uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1036
AnnaBridge	143:86740a56073b	1037	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
AnnaBridge	143:86740a56073b	1038	void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1039	void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1040	void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1041	void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1042	void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
AnnaBridge	143:86740a56073b	1043	/**
AnnaBridge	143:86740a56073b	1044	* @}
AnnaBridge	143:86740a56073b	1045	*/
AnnaBridge	143:86740a56073b	1046
AnnaBridge	143:86740a56073b	1047	/* Peripheral Control functions ***********************************************/
AnnaBridge	143:86740a56073b	1048	/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
AnnaBridge	143:86740a56073b	1049	* @{
AnnaBridge	143:86740a56073b	1050	*/
AnnaBridge	143:86740a56073b	1051	HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
AnnaBridge	143:86740a56073b	1052	HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
AnnaBridge	143:86740a56073b	1053	/**
AnnaBridge	143:86740a56073b	1054	* @}
AnnaBridge	143:86740a56073b	1055	*/
AnnaBridge	143:86740a56073b	1056
AnnaBridge	143:86740a56073b	1057	/* Peripheral State functions *************************************************/
AnnaBridge	143:86740a56073b	1058	/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
AnnaBridge	143:86740a56073b	1059	* @{
AnnaBridge	143:86740a56073b	1060	*/
AnnaBridge	143:86740a56073b	1061	uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
AnnaBridge	143:86740a56073b	1062	uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
AnnaBridge	143:86740a56073b	1063	/**
AnnaBridge	143:86740a56073b	1064	* @}
AnnaBridge	143:86740a56073b	1065	*/
AnnaBridge	143:86740a56073b	1066
AnnaBridge	143:86740a56073b	1067
AnnaBridge	143:86740a56073b	1068	/**
AnnaBridge	143:86740a56073b	1069	* @}
AnnaBridge	143:86740a56073b	1070	*/
AnnaBridge	143:86740a56073b	1071
AnnaBridge	143:86740a56073b	1072	/* Define the private group ***********************************/
AnnaBridge	143:86740a56073b	1073	/**************************************************************/
AnnaBridge	143:86740a56073b	1074	/** @defgroup ADC_Private ADC Private
AnnaBridge	143:86740a56073b	1075	* @{
AnnaBridge	143:86740a56073b	1076	*/
AnnaBridge	143:86740a56073b	1077	/**
AnnaBridge	143:86740a56073b	1078	* @}
AnnaBridge	143:86740a56073b	1079	*/
AnnaBridge	143:86740a56073b	1080	/**************************************************************/
AnnaBridge	143:86740a56073b	1081
AnnaBridge	143:86740a56073b	1082	/**
AnnaBridge	143:86740a56073b	1083	* @}
AnnaBridge	143:86740a56073b	1084	*/
AnnaBridge	143:86740a56073b	1085
AnnaBridge	143:86740a56073b	1086	/**
AnnaBridge	143:86740a56073b	1087	* @}
AnnaBridge	143:86740a56073b	1088	*/
AnnaBridge	143:86740a56073b	1089
AnnaBridge	143:86740a56073b	1090	#ifdef __cplusplus
AnnaBridge	143:86740a56073b	1091	}
AnnaBridge	143:86740a56073b	1092	#endif
AnnaBridge	143:86740a56073b	1093
AnnaBridge	143:86740a56073b	1094	#endif /__STM32L0xx_ADC_H /
AnnaBridge	143:86740a56073b	1095
AnnaBridge	143:86740a56073b	1096
AnnaBridge	143:86740a56073b	1097	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/