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TARGET_USENSE/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/drivers/fsl_mpu.h@145:64910690c574, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:31:38 2017 +0100
- Revision:
- 145:64910690c574
Release 145 of the mbed library.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 145:64910690c574 | 1 | /* |
AnnaBridge | 145:64910690c574 | 2 | * Copyright (c) 2015, Freescale Semiconductor, Inc. |
AnnaBridge | 145:64910690c574 | 3 | * All rights reserved. |
AnnaBridge | 145:64910690c574 | 4 | * |
AnnaBridge | 145:64910690c574 | 5 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 145:64910690c574 | 6 | * are permitted provided that the following conditions are met: |
AnnaBridge | 145:64910690c574 | 7 | * |
AnnaBridge | 145:64910690c574 | 8 | * o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 145:64910690c574 | 9 | * of conditions and the following disclaimer. |
AnnaBridge | 145:64910690c574 | 10 | * |
AnnaBridge | 145:64910690c574 | 11 | * o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 145:64910690c574 | 12 | * list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 145:64910690c574 | 13 | * other materials provided with the distribution. |
AnnaBridge | 145:64910690c574 | 14 | * |
AnnaBridge | 145:64910690c574 | 15 | * o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
AnnaBridge | 145:64910690c574 | 16 | * contributors may be used to endorse or promote products derived from this |
AnnaBridge | 145:64910690c574 | 17 | * software without specific prior written permission. |
AnnaBridge | 145:64910690c574 | 18 | * |
AnnaBridge | 145:64910690c574 | 19 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 145:64910690c574 | 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 145:64910690c574 | 21 | * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 145:64910690c574 | 22 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 145:64910690c574 | 23 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 145:64910690c574 | 24 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 145:64910690c574 | 25 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 145:64910690c574 | 26 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 145:64910690c574 | 27 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 145:64910690c574 | 28 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 145:64910690c574 | 29 | */ |
AnnaBridge | 145:64910690c574 | 30 | #ifndef _FSL_MPU_H_ |
AnnaBridge | 145:64910690c574 | 31 | #define _FSL_MPU_H_ |
AnnaBridge | 145:64910690c574 | 32 | |
AnnaBridge | 145:64910690c574 | 33 | #include "fsl_common.h" |
AnnaBridge | 145:64910690c574 | 34 | |
AnnaBridge | 145:64910690c574 | 35 | /*! |
AnnaBridge | 145:64910690c574 | 36 | * @addtogroup mpu |
AnnaBridge | 145:64910690c574 | 37 | * @{ |
AnnaBridge | 145:64910690c574 | 38 | */ |
AnnaBridge | 145:64910690c574 | 39 | |
AnnaBridge | 145:64910690c574 | 40 | |
AnnaBridge | 145:64910690c574 | 41 | /******************************************************************************* |
AnnaBridge | 145:64910690c574 | 42 | * Definitions |
AnnaBridge | 145:64910690c574 | 43 | ******************************************************************************/ |
AnnaBridge | 145:64910690c574 | 44 | |
AnnaBridge | 145:64910690c574 | 45 | /*! @name Driver version */ |
AnnaBridge | 145:64910690c574 | 46 | /*@{*/ |
AnnaBridge | 145:64910690c574 | 47 | /*! @brief MPU driver version 2.1.0. */ |
AnnaBridge | 145:64910690c574 | 48 | #define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 0)) |
AnnaBridge | 145:64910690c574 | 49 | /*@}*/ |
AnnaBridge | 145:64910690c574 | 50 | |
AnnaBridge | 145:64910690c574 | 51 | /*! @brief MPU the bit shift for masters with privilege rights: read write and execute. */ |
AnnaBridge | 145:64910690c574 | 52 | #define MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6) |
AnnaBridge | 145:64910690c574 | 53 | |
AnnaBridge | 145:64910690c574 | 54 | /*! @brief MPU masters with read, write and execute rights bit mask. */ |
AnnaBridge | 145:64910690c574 | 55 | #define MPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n)) |
AnnaBridge | 145:64910690c574 | 56 | |
AnnaBridge | 145:64910690c574 | 57 | /*! @brief MPU masters with read, write and execute rights bit width. */ |
AnnaBridge | 145:64910690c574 | 58 | #define MPU_REGION_RWXRIGHTS_MASTER_WIDTH 5 |
AnnaBridge | 145:64910690c574 | 59 | |
AnnaBridge | 145:64910690c574 | 60 | /*! @brief MPU masters with read, write and execute rights priority setting. */ |
AnnaBridge | 145:64910690c574 | 61 | #define MPU_REGION_RWXRIGHTS_MASTER(n, x) \ |
AnnaBridge | 145:64910690c574 | 62 | (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_MASK(n)) |
AnnaBridge | 145:64910690c574 | 63 | |
AnnaBridge | 145:64910690c574 | 64 | /*! @brief MPU masters with read, write and execute rights process enable bit shift. */ |
AnnaBridge | 145:64910690c574 | 65 | #define MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + MPU_REGION_RWXRIGHTS_MASTER_WIDTH) |
AnnaBridge | 145:64910690c574 | 66 | |
AnnaBridge | 145:64910690c574 | 67 | /*! @brief MPU masters with read, write and execute rights process enable bit mask. */ |
AnnaBridge | 145:64910690c574 | 68 | #define MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n)) |
AnnaBridge | 145:64910690c574 | 69 | |
AnnaBridge | 145:64910690c574 | 70 | /*! @brief MPU masters with read, write and execute rights process enable setting. */ |
AnnaBridge | 145:64910690c574 | 71 | #define MPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \ |
AnnaBridge | 145:64910690c574 | 72 | (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n)) |
AnnaBridge | 145:64910690c574 | 73 | |
AnnaBridge | 145:64910690c574 | 74 | /*! @brief MPU masters with normal read write permission bit shift. */ |
AnnaBridge | 145:64910690c574 | 75 | #define MPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT) * 2 + 24) |
AnnaBridge | 145:64910690c574 | 76 | |
AnnaBridge | 145:64910690c574 | 77 | /*! @brief MPU masters with normal read write rights bit mask. */ |
AnnaBridge | 145:64910690c574 | 78 | #define MPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n)) |
AnnaBridge | 145:64910690c574 | 79 | |
AnnaBridge | 145:64910690c574 | 80 | /*! @brief MPU masters with normal read write rights priority setting. */ |
AnnaBridge | 145:64910690c574 | 81 | #define MPU_REGION_RWRIGHTS_MASTER(n, x) \ |
AnnaBridge | 145:64910690c574 | 82 | (((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWRIGHTS_MASTER_MASK(n)) |
AnnaBridge | 145:64910690c574 | 83 | |
AnnaBridge | 145:64910690c574 | 84 | /*! @brief Describes the number of MPU regions. */ |
AnnaBridge | 145:64910690c574 | 85 | typedef enum _mpu_region_total_num |
AnnaBridge | 145:64910690c574 | 86 | { |
AnnaBridge | 145:64910690c574 | 87 | kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */ |
AnnaBridge | 145:64910690c574 | 88 | kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */ |
AnnaBridge | 145:64910690c574 | 89 | kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */ |
AnnaBridge | 145:64910690c574 | 90 | } mpu_region_total_num_t; |
AnnaBridge | 145:64910690c574 | 91 | |
AnnaBridge | 145:64910690c574 | 92 | /*! @brief MPU slave port number. */ |
AnnaBridge | 145:64910690c574 | 93 | typedef enum _mpu_slave |
AnnaBridge | 145:64910690c574 | 94 | { |
AnnaBridge | 145:64910690c574 | 95 | kMPU_Slave0 = 4U, /*!< MPU slave port 0. */ |
AnnaBridge | 145:64910690c574 | 96 | kMPU_Slave1 = 3U, /*!< MPU slave port 1. */ |
AnnaBridge | 145:64910690c574 | 97 | kMPU_Slave2 = 2U, /*!< MPU slave port 2. */ |
AnnaBridge | 145:64910690c574 | 98 | kMPU_Slave3 = 1U, /*!< MPU slave port 3. */ |
AnnaBridge | 145:64910690c574 | 99 | kMPU_Slave4 = 0U /*!< MPU slave port 4. */ |
AnnaBridge | 145:64910690c574 | 100 | } mpu_slave_t; |
AnnaBridge | 145:64910690c574 | 101 | |
AnnaBridge | 145:64910690c574 | 102 | /*! @brief MPU error access control detail. */ |
AnnaBridge | 145:64910690c574 | 103 | typedef enum _mpu_err_access_control |
AnnaBridge | 145:64910690c574 | 104 | { |
AnnaBridge | 145:64910690c574 | 105 | kMPU_NoRegionHit = 0U, /*!< No region hit error. */ |
AnnaBridge | 145:64910690c574 | 106 | kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */ |
AnnaBridge | 145:64910690c574 | 107 | kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */ |
AnnaBridge | 145:64910690c574 | 108 | } mpu_err_access_control_t; |
AnnaBridge | 145:64910690c574 | 109 | |
AnnaBridge | 145:64910690c574 | 110 | /*! @brief MPU error access type. */ |
AnnaBridge | 145:64910690c574 | 111 | typedef enum _mpu_err_access_type |
AnnaBridge | 145:64910690c574 | 112 | { |
AnnaBridge | 145:64910690c574 | 113 | kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */ |
AnnaBridge | 145:64910690c574 | 114 | kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */ |
AnnaBridge | 145:64910690c574 | 115 | } mpu_err_access_type_t; |
AnnaBridge | 145:64910690c574 | 116 | |
AnnaBridge | 145:64910690c574 | 117 | /*! @brief MPU access error attributes.*/ |
AnnaBridge | 145:64910690c574 | 118 | typedef enum _mpu_err_attributes |
AnnaBridge | 145:64910690c574 | 119 | { |
AnnaBridge | 145:64910690c574 | 120 | kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */ |
AnnaBridge | 145:64910690c574 | 121 | kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */ |
AnnaBridge | 145:64910690c574 | 122 | kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */ |
AnnaBridge | 145:64910690c574 | 123 | kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */ |
AnnaBridge | 145:64910690c574 | 124 | } mpu_err_attributes_t; |
AnnaBridge | 145:64910690c574 | 125 | |
AnnaBridge | 145:64910690c574 | 126 | /*! @brief MPU access rights in supervisor mode for bus master 0 ~ 3. */ |
AnnaBridge | 145:64910690c574 | 127 | typedef enum _mpu_supervisor_access_rights |
AnnaBridge | 145:64910690c574 | 128 | { |
AnnaBridge | 145:64910690c574 | 129 | kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */ |
AnnaBridge | 145:64910690c574 | 130 | kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */ |
AnnaBridge | 145:64910690c574 | 131 | kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */ |
AnnaBridge | 145:64910690c574 | 132 | kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */ |
AnnaBridge | 145:64910690c574 | 133 | } mpu_supervisor_access_rights_t; |
AnnaBridge | 145:64910690c574 | 134 | |
AnnaBridge | 145:64910690c574 | 135 | /*! @brief MPU access rights in user mode for bus master 0 ~ 3. */ |
AnnaBridge | 145:64910690c574 | 136 | typedef enum _mpu_user_access_rights |
AnnaBridge | 145:64910690c574 | 137 | { |
AnnaBridge | 145:64910690c574 | 138 | kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 139 | kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 140 | kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 141 | kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 142 | kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 143 | kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 144 | kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 145 | kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */ |
AnnaBridge | 145:64910690c574 | 146 | } mpu_user_access_rights_t; |
AnnaBridge | 145:64910690c574 | 147 | |
AnnaBridge | 145:64910690c574 | 148 | /*! @brief MPU hardware basic information. */ |
AnnaBridge | 145:64910690c574 | 149 | typedef struct _mpu_hardware_info |
AnnaBridge | 145:64910690c574 | 150 | { |
AnnaBridge | 145:64910690c574 | 151 | uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */ |
AnnaBridge | 145:64910690c574 | 152 | uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */ |
AnnaBridge | 145:64910690c574 | 153 | mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */ |
AnnaBridge | 145:64910690c574 | 154 | } mpu_hardware_info_t; |
AnnaBridge | 145:64910690c574 | 155 | |
AnnaBridge | 145:64910690c574 | 156 | /*! @brief MPU detail error access information. */ |
AnnaBridge | 145:64910690c574 | 157 | typedef struct _mpu_access_err_info |
AnnaBridge | 145:64910690c574 | 158 | { |
AnnaBridge | 145:64910690c574 | 159 | uint32_t master; /*!< Access error master. */ |
AnnaBridge | 145:64910690c574 | 160 | mpu_err_attributes_t attributes; /*!< Access error attributes. */ |
AnnaBridge | 145:64910690c574 | 161 | mpu_err_access_type_t accessType; /*!< Access error type. */ |
AnnaBridge | 145:64910690c574 | 162 | mpu_err_access_control_t accessControl; /*!< Access error control. */ |
AnnaBridge | 145:64910690c574 | 163 | uint32_t address; /*!< Access error address. */ |
AnnaBridge | 145:64910690c574 | 164 | #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER |
AnnaBridge | 145:64910690c574 | 165 | uint8_t processorIdentification; /*!< Access error processor identification. */ |
AnnaBridge | 145:64910690c574 | 166 | #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ |
AnnaBridge | 145:64910690c574 | 167 | } mpu_access_err_info_t; |
AnnaBridge | 145:64910690c574 | 168 | |
AnnaBridge | 145:64910690c574 | 169 | /*! @brief MPU read/write/execute rights control for bus master 0 ~ 3. */ |
AnnaBridge | 145:64910690c574 | 170 | typedef struct _mpu_rwxrights_master_access_control |
AnnaBridge | 145:64910690c574 | 171 | { |
AnnaBridge | 145:64910690c574 | 172 | mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */ |
AnnaBridge | 145:64910690c574 | 173 | mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */ |
AnnaBridge | 145:64910690c574 | 174 | #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER |
AnnaBridge | 145:64910690c574 | 175 | bool processIdentifierEnable; /*!< Enables or disables process identifier. */ |
AnnaBridge | 145:64910690c574 | 176 | #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ |
AnnaBridge | 145:64910690c574 | 177 | } mpu_rwxrights_master_access_control_t; |
AnnaBridge | 145:64910690c574 | 178 | |
AnnaBridge | 145:64910690c574 | 179 | /*! @brief MPU read/write access control for bus master 4 ~ 7. */ |
AnnaBridge | 145:64910690c574 | 180 | typedef struct _mpu_rwrights_master_access_control |
AnnaBridge | 145:64910690c574 | 181 | { |
AnnaBridge | 145:64910690c574 | 182 | bool writeEnable; /*!< Enables or disables write permission. */ |
AnnaBridge | 145:64910690c574 | 183 | bool readEnable; /*!< Enables or disables read permission. */ |
AnnaBridge | 145:64910690c574 | 184 | } mpu_rwrights_master_access_control_t; |
AnnaBridge | 145:64910690c574 | 185 | |
AnnaBridge | 145:64910690c574 | 186 | /*! |
AnnaBridge | 145:64910690c574 | 187 | * @brief MPU region configuration structure. |
AnnaBridge | 145:64910690c574 | 188 | * |
AnnaBridge | 145:64910690c574 | 189 | * This structure is used to configure the regionNum region. |
AnnaBridge | 145:64910690c574 | 190 | * The accessRights1[0] ~ accessRights1[3] are used to configure the bus master |
AnnaBridge | 145:64910690c574 | 191 | * 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3] |
AnnaBridge | 145:64910690c574 | 192 | * are used to configure the high master 4 ~ 7 with the normal read write permission. |
AnnaBridge | 145:64910690c574 | 193 | * The master port assignment is the chip configuration. Normally, the core is the |
AnnaBridge | 145:64910690c574 | 194 | * master 0, debugger is the master 1. |
AnnaBridge | 145:64910690c574 | 195 | * Note: MPU assigns a priority scheme where the debugger is treated as the highest |
AnnaBridge | 145:64910690c574 | 196 | * priority master followed by the core and then all the remaining masters. |
AnnaBridge | 145:64910690c574 | 197 | * MPU protection does not allow writes from the core to affect the "regionNum 0" start |
AnnaBridge | 145:64910690c574 | 198 | * and end address nor the permissions associated with the debugger. It can only write |
AnnaBridge | 145:64910690c574 | 199 | * the permission fields associated with the other masters. This protection guarantee |
AnnaBridge | 145:64910690c574 | 200 | * the debugger always has access to the entire address space and those rights can't |
AnnaBridge | 145:64910690c574 | 201 | * be changed by the core or any other bus master. Prepare |
AnnaBridge | 145:64910690c574 | 202 | * the region configuration when regionNum is 0. |
AnnaBridge | 145:64910690c574 | 203 | */ |
AnnaBridge | 145:64910690c574 | 204 | typedef struct _mpu_region_config |
AnnaBridge | 145:64910690c574 | 205 | { |
AnnaBridge | 145:64910690c574 | 206 | uint32_t regionNum; /*!< MPU region number, range form 0 ~ FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. */ |
AnnaBridge | 145:64910690c574 | 207 | uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual |
AnnaBridge | 145:64910690c574 | 208 | start address is 0-modulo-32 byte address. */ |
AnnaBridge | 145:64910690c574 | 209 | uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end |
AnnaBridge | 145:64910690c574 | 210 | address is 31-modulo-32 byte address. */ |
AnnaBridge | 145:64910690c574 | 211 | mpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */ |
AnnaBridge | 145:64910690c574 | 212 | mpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */ |
AnnaBridge | 145:64910690c574 | 213 | #if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER |
AnnaBridge | 145:64910690c574 | 214 | uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */ |
AnnaBridge | 145:64910690c574 | 215 | uint8_t |
AnnaBridge | 145:64910690c574 | 216 | processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */ |
AnnaBridge | 145:64910690c574 | 217 | #endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */ |
AnnaBridge | 145:64910690c574 | 218 | } mpu_region_config_t; |
AnnaBridge | 145:64910690c574 | 219 | |
AnnaBridge | 145:64910690c574 | 220 | /*! |
AnnaBridge | 145:64910690c574 | 221 | * @brief The configuration structure for the MPU initialization. |
AnnaBridge | 145:64910690c574 | 222 | * |
AnnaBridge | 145:64910690c574 | 223 | * This structure is used when calling the MPU_Init function. |
AnnaBridge | 145:64910690c574 | 224 | */ |
AnnaBridge | 145:64910690c574 | 225 | typedef struct _mpu_config |
AnnaBridge | 145:64910690c574 | 226 | { |
AnnaBridge | 145:64910690c574 | 227 | mpu_region_config_t regionConfig; /*!< region access permission. */ |
AnnaBridge | 145:64910690c574 | 228 | struct _mpu_config *next; /*!< pointer to the next structure. */ |
AnnaBridge | 145:64910690c574 | 229 | } mpu_config_t; |
AnnaBridge | 145:64910690c574 | 230 | |
AnnaBridge | 145:64910690c574 | 231 | /******************************************************************************* |
AnnaBridge | 145:64910690c574 | 232 | * API |
AnnaBridge | 145:64910690c574 | 233 | ******************************************************************************/ |
AnnaBridge | 145:64910690c574 | 234 | |
AnnaBridge | 145:64910690c574 | 235 | #if defined(__cplusplus) |
AnnaBridge | 145:64910690c574 | 236 | extern "C" { |
AnnaBridge | 145:64910690c574 | 237 | #endif /* _cplusplus */ |
AnnaBridge | 145:64910690c574 | 238 | |
AnnaBridge | 145:64910690c574 | 239 | /*! |
AnnaBridge | 145:64910690c574 | 240 | * @name Initialization and deinitialization |
AnnaBridge | 145:64910690c574 | 241 | * @{ |
AnnaBridge | 145:64910690c574 | 242 | */ |
AnnaBridge | 145:64910690c574 | 243 | |
AnnaBridge | 145:64910690c574 | 244 | /*! |
AnnaBridge | 145:64910690c574 | 245 | * @brief Initializes the MPU with the user configuration structure. |
AnnaBridge | 145:64910690c574 | 246 | * |
AnnaBridge | 145:64910690c574 | 247 | * This function configures the MPU module with the user-defined configuration. |
AnnaBridge | 145:64910690c574 | 248 | * |
AnnaBridge | 145:64910690c574 | 249 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 250 | * @param config The pointer to the configuration structure. |
AnnaBridge | 145:64910690c574 | 251 | */ |
AnnaBridge | 145:64910690c574 | 252 | void MPU_Init(MPU_Type *base, const mpu_config_t *config); |
AnnaBridge | 145:64910690c574 | 253 | |
AnnaBridge | 145:64910690c574 | 254 | /*! |
AnnaBridge | 145:64910690c574 | 255 | * @brief Deinitializes the MPU regions. |
AnnaBridge | 145:64910690c574 | 256 | * |
AnnaBridge | 145:64910690c574 | 257 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 258 | */ |
AnnaBridge | 145:64910690c574 | 259 | void MPU_Deinit(MPU_Type *base); |
AnnaBridge | 145:64910690c574 | 260 | |
AnnaBridge | 145:64910690c574 | 261 | /* @}*/ |
AnnaBridge | 145:64910690c574 | 262 | |
AnnaBridge | 145:64910690c574 | 263 | /*! |
AnnaBridge | 145:64910690c574 | 264 | * @name Basic Control Operations |
AnnaBridge | 145:64910690c574 | 265 | * @{ |
AnnaBridge | 145:64910690c574 | 266 | */ |
AnnaBridge | 145:64910690c574 | 267 | |
AnnaBridge | 145:64910690c574 | 268 | /*! |
AnnaBridge | 145:64910690c574 | 269 | * @brief Enables/disables the MPU globally. |
AnnaBridge | 145:64910690c574 | 270 | * |
AnnaBridge | 145:64910690c574 | 271 | * Call this API to enable or disable the MPU module. |
AnnaBridge | 145:64910690c574 | 272 | * |
AnnaBridge | 145:64910690c574 | 273 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 274 | * @param enable True enable MPU, false disable MPU. |
AnnaBridge | 145:64910690c574 | 275 | */ |
AnnaBridge | 145:64910690c574 | 276 | static inline void MPU_Enable(MPU_Type *base, bool enable) |
AnnaBridge | 145:64910690c574 | 277 | { |
AnnaBridge | 145:64910690c574 | 278 | if (enable) |
AnnaBridge | 145:64910690c574 | 279 | { |
AnnaBridge | 145:64910690c574 | 280 | /* Enable the MPU globally. */ |
AnnaBridge | 145:64910690c574 | 281 | base->CESR |= MPU_CESR_VLD_MASK; |
AnnaBridge | 145:64910690c574 | 282 | } |
AnnaBridge | 145:64910690c574 | 283 | else |
AnnaBridge | 145:64910690c574 | 284 | { /* Disable the MPU globally. */ |
AnnaBridge | 145:64910690c574 | 285 | base->CESR &= ~MPU_CESR_VLD_MASK; |
AnnaBridge | 145:64910690c574 | 286 | } |
AnnaBridge | 145:64910690c574 | 287 | } |
AnnaBridge | 145:64910690c574 | 288 | |
AnnaBridge | 145:64910690c574 | 289 | /*! |
AnnaBridge | 145:64910690c574 | 290 | * @brief Enables/disables the MPU for a special region. |
AnnaBridge | 145:64910690c574 | 291 | * |
AnnaBridge | 145:64910690c574 | 292 | * When MPU is enabled, call this API to disable an unused region |
AnnaBridge | 145:64910690c574 | 293 | * of an enabled MPU. Call this API to minimize the power dissipation. |
AnnaBridge | 145:64910690c574 | 294 | * |
AnnaBridge | 145:64910690c574 | 295 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 296 | * @param number MPU region number. |
AnnaBridge | 145:64910690c574 | 297 | * @param enable True enable the special region MPU, false disable the special region MPU. |
AnnaBridge | 145:64910690c574 | 298 | */ |
AnnaBridge | 145:64910690c574 | 299 | static inline void MPU_RegionEnable(MPU_Type *base, uint32_t number, bool enable) |
AnnaBridge | 145:64910690c574 | 300 | { |
AnnaBridge | 145:64910690c574 | 301 | if (enable) |
AnnaBridge | 145:64910690c574 | 302 | { |
AnnaBridge | 145:64910690c574 | 303 | /* Enable the #number region MPU. */ |
AnnaBridge | 145:64910690c574 | 304 | base->WORD[number][3] |= MPU_WORD_VLD_MASK; |
AnnaBridge | 145:64910690c574 | 305 | } |
AnnaBridge | 145:64910690c574 | 306 | else |
AnnaBridge | 145:64910690c574 | 307 | { /* Disable the #number region MPU. */ |
AnnaBridge | 145:64910690c574 | 308 | base->WORD[number][3] &= ~MPU_WORD_VLD_MASK; |
AnnaBridge | 145:64910690c574 | 309 | } |
AnnaBridge | 145:64910690c574 | 310 | } |
AnnaBridge | 145:64910690c574 | 311 | |
AnnaBridge | 145:64910690c574 | 312 | /*! |
AnnaBridge | 145:64910690c574 | 313 | * @brief Gets the MPU basic hardware information. |
AnnaBridge | 145:64910690c574 | 314 | * |
AnnaBridge | 145:64910690c574 | 315 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 316 | * @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t". |
AnnaBridge | 145:64910690c574 | 317 | */ |
AnnaBridge | 145:64910690c574 | 318 | void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform); |
AnnaBridge | 145:64910690c574 | 319 | |
AnnaBridge | 145:64910690c574 | 320 | /*! |
AnnaBridge | 145:64910690c574 | 321 | * @brief Sets the MPU region. |
AnnaBridge | 145:64910690c574 | 322 | * |
AnnaBridge | 145:64910690c574 | 323 | * Note: Due to the MPU protection, the Region number 0 does not allow writes from |
AnnaBridge | 145:64910690c574 | 324 | * core to affect the start and end address nor the permissions associated with |
AnnaBridge | 145:64910690c574 | 325 | * the debugger. It can only write the permission fields associated |
AnnaBridge | 145:64910690c574 | 326 | * with the other masters. |
AnnaBridge | 145:64910690c574 | 327 | * |
AnnaBridge | 145:64910690c574 | 328 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 329 | * @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t". |
AnnaBridge | 145:64910690c574 | 330 | */ |
AnnaBridge | 145:64910690c574 | 331 | void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig); |
AnnaBridge | 145:64910690c574 | 332 | |
AnnaBridge | 145:64910690c574 | 333 | /*! |
AnnaBridge | 145:64910690c574 | 334 | * @brief Sets the region start and end address. |
AnnaBridge | 145:64910690c574 | 335 | * |
AnnaBridge | 145:64910690c574 | 336 | * Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU. |
AnnaBridge | 145:64910690c574 | 337 | * The actual start address by MPU is 0-modulo-32 byte address. |
AnnaBridge | 145:64910690c574 | 338 | * Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. |
AnnaBridge | 145:64910690c574 | 339 | * The actual end address used by MPU is 31-modulo-32 byte address. |
AnnaBridge | 145:64910690c574 | 340 | * Note: Due to the MPU protection, the startAddr and endAddr can't be |
AnnaBridge | 145:64910690c574 | 341 | * changed by the core when regionNum is 0. |
AnnaBridge | 145:64910690c574 | 342 | * |
AnnaBridge | 145:64910690c574 | 343 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 344 | * @param regionNum MPU region number. The range is from 0 to |
AnnaBridge | 145:64910690c574 | 345 | * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. |
AnnaBridge | 145:64910690c574 | 346 | * @param startAddr Region start address. |
AnnaBridge | 145:64910690c574 | 347 | * @param endAddr Region end address. |
AnnaBridge | 145:64910690c574 | 348 | */ |
AnnaBridge | 145:64910690c574 | 349 | void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr); |
AnnaBridge | 145:64910690c574 | 350 | |
AnnaBridge | 145:64910690c574 | 351 | /*! |
AnnaBridge | 145:64910690c574 | 352 | * @brief Sets the MPU region access rights for masters with read, write and execute rights. |
AnnaBridge | 145:64910690c574 | 353 | * The MPU access rights depend on two board classifications of bus masters. |
AnnaBridge | 145:64910690c574 | 354 | * The privilege rights masters and the normal rights masters. |
AnnaBridge | 145:64910690c574 | 355 | * The privilege rights masters have the read, write and execute access rights. |
AnnaBridge | 145:64910690c574 | 356 | * So except the normal read and write rights, the execute rights is also |
AnnaBridge | 145:64910690c574 | 357 | * allowed for these masters. The privilege rights masters are normally range from |
AnnaBridge | 145:64910690c574 | 358 | * bus masters 0 - 3. However, the maximum master number is device-specific. |
AnnaBridge | 145:64910690c574 | 359 | * See the "FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX". |
AnnaBridge | 145:64910690c574 | 360 | * The normal rights masters access rights control see |
AnnaBridge | 145:64910690c574 | 361 | * "MPU_SetRegionRwMasterAccessRights()". |
AnnaBridge | 145:64910690c574 | 362 | * |
AnnaBridge | 145:64910690c574 | 363 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 364 | * @param regionNum MPU region number. Should range from 0 to |
AnnaBridge | 145:64910690c574 | 365 | * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. |
AnnaBridge | 145:64910690c574 | 366 | * @param masterNum MPU bus master number. Should range from 0 to |
AnnaBridge | 145:64910690c574 | 367 | * FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX. |
AnnaBridge | 145:64910690c574 | 368 | * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwxrights_master_access_control_t". |
AnnaBridge | 145:64910690c574 | 369 | */ |
AnnaBridge | 145:64910690c574 | 370 | void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base, |
AnnaBridge | 145:64910690c574 | 371 | uint32_t regionNum, |
AnnaBridge | 145:64910690c574 | 372 | uint32_t masterNum, |
AnnaBridge | 145:64910690c574 | 373 | const mpu_rwxrights_master_access_control_t *accessRights); |
AnnaBridge | 145:64910690c574 | 374 | |
AnnaBridge | 145:64910690c574 | 375 | /*! |
AnnaBridge | 145:64910690c574 | 376 | * @brief Sets the MPU region access rights for masters with read and write rights. |
AnnaBridge | 145:64910690c574 | 377 | * The MPU access rights depend on two board classifications of bus masters. |
AnnaBridge | 145:64910690c574 | 378 | * The privilege rights masters and the normal rights masters. |
AnnaBridge | 145:64910690c574 | 379 | * The normal rights masters only have the read and write access permissions. |
AnnaBridge | 145:64910690c574 | 380 | * The privilege rights access control see "MPU_SetRegionRwxMasterAccessRights". |
AnnaBridge | 145:64910690c574 | 381 | * |
AnnaBridge | 145:64910690c574 | 382 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 383 | * @param regionNum MPU region number. The range is from 0 to |
AnnaBridge | 145:64910690c574 | 384 | * FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. |
AnnaBridge | 145:64910690c574 | 385 | * @param masterNum MPU bus master number. Should range from FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT |
AnnaBridge | 145:64910690c574 | 386 | * to ~ FSL_FEATURE_MPU_MASTER_MAX_INDEX. |
AnnaBridge | 145:64910690c574 | 387 | * @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwrights_master_access_control_t". |
AnnaBridge | 145:64910690c574 | 388 | */ |
AnnaBridge | 145:64910690c574 | 389 | void MPU_SetRegionRwMasterAccessRights(MPU_Type *base, |
AnnaBridge | 145:64910690c574 | 390 | uint32_t regionNum, |
AnnaBridge | 145:64910690c574 | 391 | uint32_t masterNum, |
AnnaBridge | 145:64910690c574 | 392 | const mpu_rwrights_master_access_control_t *accessRights); |
AnnaBridge | 145:64910690c574 | 393 | |
AnnaBridge | 145:64910690c574 | 394 | /*! |
AnnaBridge | 145:64910690c574 | 395 | * @brief Gets the numbers of slave ports where errors occur. |
AnnaBridge | 145:64910690c574 | 396 | * |
AnnaBridge | 145:64910690c574 | 397 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 398 | * @param slaveNum MPU slave port number. |
AnnaBridge | 145:64910690c574 | 399 | * @return The slave ports error status. |
AnnaBridge | 145:64910690c574 | 400 | * true - error happens in this slave port. |
AnnaBridge | 145:64910690c574 | 401 | * false - error didn't happen in this slave port. |
AnnaBridge | 145:64910690c574 | 402 | */ |
AnnaBridge | 145:64910690c574 | 403 | bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum); |
AnnaBridge | 145:64910690c574 | 404 | |
AnnaBridge | 145:64910690c574 | 405 | /*! |
AnnaBridge | 145:64910690c574 | 406 | * @brief Gets the MPU detailed error access information. |
AnnaBridge | 145:64910690c574 | 407 | * |
AnnaBridge | 145:64910690c574 | 408 | * @param base MPU peripheral base address. |
AnnaBridge | 145:64910690c574 | 409 | * @param slaveNum MPU slave port number. |
AnnaBridge | 145:64910690c574 | 410 | * @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t". |
AnnaBridge | 145:64910690c574 | 411 | */ |
AnnaBridge | 145:64910690c574 | 412 | void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform); |
AnnaBridge | 145:64910690c574 | 413 | |
AnnaBridge | 145:64910690c574 | 414 | /* @} */ |
AnnaBridge | 145:64910690c574 | 415 | |
AnnaBridge | 145:64910690c574 | 416 | #if defined(__cplusplus) |
AnnaBridge | 145:64910690c574 | 417 | } |
AnnaBridge | 145:64910690c574 | 418 | #endif |
AnnaBridge | 145:64910690c574 | 419 | |
AnnaBridge | 145:64910690c574 | 420 | /*! @}*/ |
AnnaBridge | 145:64910690c574 | 421 | |
AnnaBridge | 145:64910690c574 | 422 | #endif /* _FSL_MPU_H_ */ |