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TARGET_RBLAB_NRF51822/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:: Anna Bridge
Date:: Fri Apr 20 11:08:29 2018 +0100
Revision:: 166:5aab5a7997ee
Parent:: 156:ff21514d8981

Updating mbed 2 version number

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	156:ff21514d8981	1	/*
AnnaBridge	156:ff21514d8981	2	* Copyright (c) Nordic Semiconductor ASA
AnnaBridge	156:ff21514d8981	3	* All rights reserved.
AnnaBridge	156:ff21514d8981	4	*
AnnaBridge	156:ff21514d8981	5	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	156:ff21514d8981	6	* are permitted provided that the following conditions are met:
AnnaBridge	156:ff21514d8981	7	*
AnnaBridge	156:ff21514d8981	8	* 1. Redistributions of source code must retain the above copyright notice, this
AnnaBridge	156:ff21514d8981	9	* list of conditions and the following disclaimer.
AnnaBridge	156:ff21514d8981	10	*
AnnaBridge	156:ff21514d8981	11	* 2. Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge	156:ff21514d8981	12	* list of conditions and the following disclaimer in the documentation and/or
AnnaBridge	156:ff21514d8981	13	* other materials provided with the distribution.
AnnaBridge	156:ff21514d8981	14	*
AnnaBridge	156:ff21514d8981	15	* 3. Neither the name of Nordic Semiconductor ASA nor the names of other
AnnaBridge	156:ff21514d8981	16	* contributors to this software may be used to endorse or promote products
AnnaBridge	156:ff21514d8981	17	* derived from this software without specific prior written permission.
AnnaBridge	156:ff21514d8981	18	*
AnnaBridge	156:ff21514d8981	19	*
AnnaBridge	156:ff21514d8981	20	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge	156:ff21514d8981	21	* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge	156:ff21514d8981	22	* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	156:ff21514d8981	23	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge	156:ff21514d8981	24	* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge	156:ff21514d8981	25	* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge	156:ff21514d8981	26	* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge	156:ff21514d8981	27	* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge	156:ff21514d8981	28	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge	156:ff21514d8981	29	* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	156:ff21514d8981	30	*
AnnaBridge	156:ff21514d8981	31	*/
AnnaBridge	156:ff21514d8981	32
AnnaBridge	156:ff21514d8981	33	#ifndef NRF51_H
AnnaBridge	156:ff21514d8981	34	#define NRF51_H
AnnaBridge	156:ff21514d8981	35
AnnaBridge	156:ff21514d8981	36	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	37	extern "C" {
AnnaBridge	156:ff21514d8981	38	#endif
AnnaBridge	156:ff21514d8981	39
AnnaBridge	156:ff21514d8981	40
AnnaBridge	156:ff21514d8981	41	/* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge	156:ff21514d8981	42
AnnaBridge	156:ff21514d8981	43	typedef enum {
AnnaBridge	156:ff21514d8981	44	/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
AnnaBridge	156:ff21514d8981	45	Reset_IRQn = -15, /!< 1 Reset Vector, invoked on Power up and warm reset /
AnnaBridge	156:ff21514d8981	46	NonMaskableInt_IRQn = -14, /!< 2 Non maskable Interrupt, cannot be stopped or preempted /
AnnaBridge	156:ff21514d8981	47	HardFault_IRQn = -13, /!< 3 Hard Fault, all classes of Fault /
AnnaBridge	156:ff21514d8981	48	SVCall_IRQn = -5, /!< 11 System Service Call via SVC instruction /
AnnaBridge	156:ff21514d8981	49	DebugMonitor_IRQn = -4, /!< 12 Debug Monitor /
AnnaBridge	156:ff21514d8981	50	PendSV_IRQn = -2, /!< 14 Pendable request for system service /
AnnaBridge	156:ff21514d8981	51	SysTick_IRQn = -1, /!< 15 System Tick Timer /
AnnaBridge	156:ff21514d8981	52	/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
AnnaBridge	156:ff21514d8981	53	POWER_CLOCK_IRQn = 0, /!< 0 POWER_CLOCK /
AnnaBridge	156:ff21514d8981	54	RADIO_IRQn = 1, /!< 1 RADIO /
AnnaBridge	156:ff21514d8981	55	UART0_IRQn = 2, /!< 2 UART0 /
AnnaBridge	156:ff21514d8981	56	SPI0_TWI0_IRQn = 3, /!< 3 SPI0_TWI0 /
AnnaBridge	156:ff21514d8981	57	SPI1_TWI1_IRQn = 4, /!< 4 SPI1_TWI1 /
AnnaBridge	156:ff21514d8981	58	GPIOTE_IRQn = 6, /!< 6 GPIOTE /
AnnaBridge	156:ff21514d8981	59	ADC_IRQn = 7, /!< 7 ADC /
AnnaBridge	156:ff21514d8981	60	TIMER0_IRQn = 8, /!< 8 TIMER0 /
AnnaBridge	156:ff21514d8981	61	TIMER1_IRQn = 9, /!< 9 TIMER1 /
AnnaBridge	156:ff21514d8981	62	TIMER2_IRQn = 10, /!< 10 TIMER2 /
AnnaBridge	156:ff21514d8981	63	RTC0_IRQn = 11, /!< 11 RTC0 /
AnnaBridge	156:ff21514d8981	64	TEMP_IRQn = 12, /!< 12 TEMP /
AnnaBridge	156:ff21514d8981	65	RNG_IRQn = 13, /!< 13 RNG /
AnnaBridge	156:ff21514d8981	66	ECB_IRQn = 14, /!< 14 ECB /
AnnaBridge	156:ff21514d8981	67	CCM_AAR_IRQn = 15, /!< 15 CCM_AAR /
AnnaBridge	156:ff21514d8981	68	WDT_IRQn = 16, /!< 16 WDT /
AnnaBridge	156:ff21514d8981	69	RTC1_IRQn = 17, /!< 17 RTC1 /
AnnaBridge	156:ff21514d8981	70	QDEC_IRQn = 18, /!< 18 QDEC /
AnnaBridge	156:ff21514d8981	71	LPCOMP_IRQn = 19, /!< 19 LPCOMP /
AnnaBridge	156:ff21514d8981	72	SWI0_IRQn = 20, /!< 20 SWI0 /
AnnaBridge	156:ff21514d8981	73	SWI1_IRQn = 21, /!< 21 SWI1 /
AnnaBridge	156:ff21514d8981	74	SWI2_IRQn = 22, /!< 22 SWI2 /
AnnaBridge	156:ff21514d8981	75	SWI3_IRQn = 23, /!< 23 SWI3 /
AnnaBridge	156:ff21514d8981	76	SWI4_IRQn = 24, /!< 24 SWI4 /
AnnaBridge	156:ff21514d8981	77	SWI5_IRQn = 25 /!< 25 SWI5 /
AnnaBridge	156:ff21514d8981	78	} IRQn_Type;
AnnaBridge	156:ff21514d8981	79
AnnaBridge	156:ff21514d8981	80
AnnaBridge	156:ff21514d8981	81	/** @addtogroup Configuration_of_CMSIS
AnnaBridge	156:ff21514d8981	82	* @{
AnnaBridge	156:ff21514d8981	83	*/
AnnaBridge	156:ff21514d8981	84
AnnaBridge	156:ff21514d8981	85
AnnaBridge	156:ff21514d8981	86	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	87	/* ================ Processor and Core Peripheral Section ================ */
AnnaBridge	156:ff21514d8981	88	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	89
AnnaBridge	156:ff21514d8981	90	/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
AnnaBridge	156:ff21514d8981	91	#define __CM0_REV 0x0301 /!< Cortex-M0 Core Revision /
AnnaBridge	156:ff21514d8981	92	#define __MPU_PRESENT 0 /!< MPU present or not /
AnnaBridge	156:ff21514d8981	93	#define __NVIC_PRIO_BITS 2 /!< Number of Bits used for Priority Levels /
AnnaBridge	156:ff21514d8981	94	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
AnnaBridge	156:ff21514d8981	95	/** @} / / End of group Configuration_of_CMSIS */
AnnaBridge	156:ff21514d8981	96
AnnaBridge	156:ff21514d8981	97	#include "core_cm0.h" /!< Cortex-M0 processor and core peripherals /
AnnaBridge	156:ff21514d8981	98	#include "system_nrf51.h" /!< nrf51 System /
AnnaBridge	156:ff21514d8981	99
AnnaBridge	156:ff21514d8981	100
AnnaBridge	156:ff21514d8981	101	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	102	/* ================ Device Specific Peripheral Section ================ */
AnnaBridge	156:ff21514d8981	103	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	104
AnnaBridge	156:ff21514d8981	105
AnnaBridge	156:ff21514d8981	106	/** @addtogroup Device_Peripheral_Registers
AnnaBridge	156:ff21514d8981	107	* @{
AnnaBridge	156:ff21514d8981	108	*/
AnnaBridge	156:ff21514d8981	109
AnnaBridge	156:ff21514d8981	110
AnnaBridge	156:ff21514d8981	111	/* ------------------- Start of section using anonymous unions ------------------ */
AnnaBridge	156:ff21514d8981	112	#if defined(__CC_ARM)
AnnaBridge	156:ff21514d8981	113	#pragma push
AnnaBridge	156:ff21514d8981	114	#pragma anon_unions
AnnaBridge	156:ff21514d8981	115	#elif defined(__ICCARM__)
AnnaBridge	156:ff21514d8981	116	#pragma language=extended
AnnaBridge	156:ff21514d8981	117	#elif defined(__GNUC__)
AnnaBridge	156:ff21514d8981	118	/* anonymous unions are enabled by default */
AnnaBridge	156:ff21514d8981	119	#elif defined(__TMS470__)
AnnaBridge	156:ff21514d8981	120	/* anonymous unions are enabled by default */
AnnaBridge	156:ff21514d8981	121	#elif defined(__TASKING__)
AnnaBridge	156:ff21514d8981	122	#pragma warning 586
AnnaBridge	156:ff21514d8981	123	#else
AnnaBridge	156:ff21514d8981	124	#warning Not supported compiler type
AnnaBridge	156:ff21514d8981	125	#endif
AnnaBridge	156:ff21514d8981	126
AnnaBridge	156:ff21514d8981	127
AnnaBridge	156:ff21514d8981	128	typedef struct {
AnnaBridge	156:ff21514d8981	129	__IO uint32_t CPU0; /!< Configurable priority configuration register for CPU0. /
AnnaBridge	156:ff21514d8981	130	__IO uint32_t SPIS1; /!< Configurable priority configuration register for SPIS1. /
AnnaBridge	156:ff21514d8981	131	__IO uint32_t RADIO; /!< Configurable priority configuration register for RADIO. /
AnnaBridge	156:ff21514d8981	132	__IO uint32_t ECB; /!< Configurable priority configuration register for ECB. /
AnnaBridge	156:ff21514d8981	133	__IO uint32_t CCM; /!< Configurable priority configuration register for CCM. /
AnnaBridge	156:ff21514d8981	134	__IO uint32_t AAR; /!< Configurable priority configuration register for AAR. /
AnnaBridge	156:ff21514d8981	135	} AMLI_RAMPRI_Type;
AnnaBridge	156:ff21514d8981	136
AnnaBridge	156:ff21514d8981	137	typedef struct {
AnnaBridge	156:ff21514d8981	138	__IO uint32_t SCK; /!< Pin select for SCK. /
AnnaBridge	156:ff21514d8981	139	__IO uint32_t MOSI; /!< Pin select for MOSI. /
AnnaBridge	156:ff21514d8981	140	__IO uint32_t MISO; /!< Pin select for MISO. /
AnnaBridge	156:ff21514d8981	141	} SPIM_PSEL_Type;
AnnaBridge	156:ff21514d8981	142
AnnaBridge	156:ff21514d8981	143	typedef struct {
AnnaBridge	156:ff21514d8981	144	__IO uint32_t PTR; /!< Data pointer. /
AnnaBridge	156:ff21514d8981	145	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to receive. /
AnnaBridge	156:ff21514d8981	146	__I uint32_t AMOUNT; /!< Number of bytes received in the last transaction. /
AnnaBridge	156:ff21514d8981	147	} SPIM_RXD_Type;
AnnaBridge	156:ff21514d8981	148
AnnaBridge	156:ff21514d8981	149	typedef struct {
AnnaBridge	156:ff21514d8981	150	__IO uint32_t PTR; /!< Data pointer. /
AnnaBridge	156:ff21514d8981	151	__IO uint32_t MAXCNT; /!< Maximum number of buffer bytes to send. /
AnnaBridge	156:ff21514d8981	152	__I uint32_t AMOUNT; /!< Number of bytes sent in the last transaction. /
AnnaBridge	156:ff21514d8981	153	} SPIM_TXD_Type;
AnnaBridge	156:ff21514d8981	154
AnnaBridge	156:ff21514d8981	155	typedef struct {
AnnaBridge	156:ff21514d8981	156	__O uint32_t EN; /!< Enable channel group. /
AnnaBridge	156:ff21514d8981	157	__O uint32_t DIS; /!< Disable channel group. /
AnnaBridge	156:ff21514d8981	158	} PPI_TASKS_CHG_Type;
AnnaBridge	156:ff21514d8981	159
AnnaBridge	156:ff21514d8981	160	typedef struct {
AnnaBridge	156:ff21514d8981	161	__IO uint32_t EEP; /!< Channel event end-point. /
AnnaBridge	156:ff21514d8981	162	__IO uint32_t TEP; /!< Channel task end-point. /
AnnaBridge	156:ff21514d8981	163	} PPI_CH_Type;
AnnaBridge	156:ff21514d8981	164
AnnaBridge	156:ff21514d8981	165
AnnaBridge	156:ff21514d8981	166	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	167	/* ================ POWER ================ */
AnnaBridge	156:ff21514d8981	168	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	169
AnnaBridge	156:ff21514d8981	170
AnnaBridge	156:ff21514d8981	171	/**
AnnaBridge	156:ff21514d8981	172	* @brief Power Control. (POWER)
AnnaBridge	156:ff21514d8981	173	*/
AnnaBridge	156:ff21514d8981	174
AnnaBridge	156:ff21514d8981	175	typedef struct { /!< POWER Structure /
AnnaBridge	156:ff21514d8981	176	__I uint32_t RESERVED0[30];
AnnaBridge	156:ff21514d8981	177	__O uint32_t TASKS_CONSTLAT; /!< Enable constant latency mode. /
AnnaBridge	156:ff21514d8981	178	__O uint32_t TASKS_LOWPWR; /!< Enable low power mode (variable latency). /
AnnaBridge	156:ff21514d8981	179	__I uint32_t RESERVED1[34];
AnnaBridge	156:ff21514d8981	180	__IO uint32_t EVENTS_POFWARN; /!< Power failure warning. /
AnnaBridge	156:ff21514d8981	181	__I uint32_t RESERVED2[126];
AnnaBridge	156:ff21514d8981	182	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	183	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	184	__I uint32_t RESERVED3[61];
AnnaBridge	156:ff21514d8981	185	__IO uint32_t RESETREAS; /!< Reset reason. /
AnnaBridge	156:ff21514d8981	186	__I uint32_t RESERVED4[9];
AnnaBridge	156:ff21514d8981	187	__I uint32_t RAMSTATUS; /!< Ram status register. /
AnnaBridge	156:ff21514d8981	188	__I uint32_t RESERVED5[53];
AnnaBridge	156:ff21514d8981	189	__O uint32_t SYSTEMOFF; /!< System off register. /
AnnaBridge	156:ff21514d8981	190	__I uint32_t RESERVED6[3];
AnnaBridge	156:ff21514d8981	191	__IO uint32_t POFCON; /!< Power failure configuration. /
AnnaBridge	156:ff21514d8981	192	__I uint32_t RESERVED7[2];
AnnaBridge	156:ff21514d8981	193	__IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
AnnaBridge	156:ff21514d8981	194	register. */
AnnaBridge	156:ff21514d8981	195	__I uint32_t RESERVED8;
AnnaBridge	156:ff21514d8981	196	__IO uint32_t RAMON; /!< Ram on/off. /
AnnaBridge	156:ff21514d8981	197	__I uint32_t RESERVED9[7];
AnnaBridge	156:ff21514d8981	198	__IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
AnnaBridge	156:ff21514d8981	199	is a retained register. */
AnnaBridge	156:ff21514d8981	200	__I uint32_t RESERVED10[3];
AnnaBridge	156:ff21514d8981	201	__IO uint32_t RAMONB; /!< Ram on/off. /
AnnaBridge	156:ff21514d8981	202	__I uint32_t RESERVED11[8];
AnnaBridge	156:ff21514d8981	203	__IO uint32_t DCDCEN; /!< DCDC converter enable configuration register. /
AnnaBridge	156:ff21514d8981	204	__I uint32_t RESERVED12[291];
AnnaBridge	156:ff21514d8981	205	__IO uint32_t DCDCFORCE; /!< DCDC power-up force register. /
AnnaBridge	156:ff21514d8981	206	} NRF_POWER_Type;
AnnaBridge	156:ff21514d8981	207
AnnaBridge	156:ff21514d8981	208
AnnaBridge	156:ff21514d8981	209	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	210	/* ================ CLOCK ================ */
AnnaBridge	156:ff21514d8981	211	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	212
AnnaBridge	156:ff21514d8981	213
AnnaBridge	156:ff21514d8981	214	/**
AnnaBridge	156:ff21514d8981	215	* @brief Clock control. (CLOCK)
AnnaBridge	156:ff21514d8981	216	*/
AnnaBridge	156:ff21514d8981	217
AnnaBridge	156:ff21514d8981	218	typedef struct { /!< CLOCK Structure /
AnnaBridge	156:ff21514d8981	219	__O uint32_t TASKS_HFCLKSTART; /!< Start HFCLK clock source. /
AnnaBridge	156:ff21514d8981	220	__O uint32_t TASKS_HFCLKSTOP; /!< Stop HFCLK clock source. /
AnnaBridge	156:ff21514d8981	221	__O uint32_t TASKS_LFCLKSTART; /!< Start LFCLK clock source. /
AnnaBridge	156:ff21514d8981	222	__O uint32_t TASKS_LFCLKSTOP; /!< Stop LFCLK clock source. /
AnnaBridge	156:ff21514d8981	223	__O uint32_t TASKS_CAL; /!< Start calibration of LFCLK RC oscillator. /
AnnaBridge	156:ff21514d8981	224	__O uint32_t TASKS_CTSTART; /!< Start calibration timer. /
AnnaBridge	156:ff21514d8981	225	__O uint32_t TASKS_CTSTOP; /!< Stop calibration timer. /
AnnaBridge	156:ff21514d8981	226	__I uint32_t RESERVED0[57];
AnnaBridge	156:ff21514d8981	227	__IO uint32_t EVENTS_HFCLKSTARTED; /!< HFCLK oscillator started. /
AnnaBridge	156:ff21514d8981	228	__IO uint32_t EVENTS_LFCLKSTARTED; /!< LFCLK oscillator started. /
AnnaBridge	156:ff21514d8981	229	__I uint32_t RESERVED1;
AnnaBridge	156:ff21514d8981	230	__IO uint32_t EVENTS_DONE; /!< Calibration of LFCLK RC oscillator completed. /
AnnaBridge	156:ff21514d8981	231	__IO uint32_t EVENTS_CTTO; /!< Calibration timer timeout. /
AnnaBridge	156:ff21514d8981	232	__I uint32_t RESERVED2[124];
AnnaBridge	156:ff21514d8981	233	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	234	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	235	__I uint32_t RESERVED3[63];
AnnaBridge	156:ff21514d8981	236	__I uint32_t HFCLKRUN; /!< Task HFCLKSTART trigger status. /
AnnaBridge	156:ff21514d8981	237	__I uint32_t HFCLKSTAT; /!< High frequency clock status. /
AnnaBridge	156:ff21514d8981	238	__I uint32_t RESERVED4;
AnnaBridge	156:ff21514d8981	239	__I uint32_t LFCLKRUN; /!< Task LFCLKSTART triggered status. /
AnnaBridge	156:ff21514d8981	240	__I uint32_t LFCLKSTAT; /!< Low frequency clock status. /
AnnaBridge	156:ff21514d8981	241	__I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
AnnaBridge	156:ff21514d8981	242	triggered. */
AnnaBridge	156:ff21514d8981	243	__I uint32_t RESERVED5[62];
AnnaBridge	156:ff21514d8981	244	__IO uint32_t LFCLKSRC; /!< Clock source for the LFCLK clock. /
AnnaBridge	156:ff21514d8981	245	__I uint32_t RESERVED6[7];
AnnaBridge	156:ff21514d8981	246	__IO uint32_t CTIV; /!< Calibration timer interval. /
AnnaBridge	156:ff21514d8981	247	__I uint32_t RESERVED7[5];
AnnaBridge	156:ff21514d8981	248	__IO uint32_t XTALFREQ; /!< Crystal frequency. /
AnnaBridge	156:ff21514d8981	249	} NRF_CLOCK_Type;
AnnaBridge	156:ff21514d8981	250
AnnaBridge	156:ff21514d8981	251
AnnaBridge	156:ff21514d8981	252	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	253	/* ================ MPU ================ */
AnnaBridge	156:ff21514d8981	254	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	255
AnnaBridge	156:ff21514d8981	256
AnnaBridge	156:ff21514d8981	257	/**
AnnaBridge	156:ff21514d8981	258	* @brief Memory Protection Unit. (MPU)
AnnaBridge	156:ff21514d8981	259	*/
AnnaBridge	156:ff21514d8981	260
AnnaBridge	156:ff21514d8981	261	typedef struct { /!< MPU Structure /
AnnaBridge	156:ff21514d8981	262	__I uint32_t RESERVED0[330];
AnnaBridge	156:ff21514d8981	263	__IO uint32_t PERR0; /!< Configuration of peripherals in mpu regions. /
AnnaBridge	156:ff21514d8981	264	__IO uint32_t RLENR0; /!< Length of RAM region 0. /
AnnaBridge	156:ff21514d8981	265	__I uint32_t RESERVED1[52];
AnnaBridge	156:ff21514d8981	266	__IO uint32_t PROTENSET0; /!< Erase and write protection bit enable set register. /
AnnaBridge	156:ff21514d8981	267	__IO uint32_t PROTENSET1; /!< Erase and write protection bit enable set register. /
AnnaBridge	156:ff21514d8981	268	__IO uint32_t DISABLEINDEBUG; /!< Disable erase and write protection mechanism in debug mode. /
AnnaBridge	156:ff21514d8981	269	__IO uint32_t PROTBLOCKSIZE; /!< Erase and write protection block size. /
AnnaBridge	156:ff21514d8981	270	} NRF_MPU_Type;
AnnaBridge	156:ff21514d8981	271
AnnaBridge	156:ff21514d8981	272
AnnaBridge	156:ff21514d8981	273	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	274	/* ================ AMLI ================ */
AnnaBridge	156:ff21514d8981	275	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	276
AnnaBridge	156:ff21514d8981	277
AnnaBridge	156:ff21514d8981	278	/**
AnnaBridge	156:ff21514d8981	279	* @brief AHB Multi-Layer Interface. (AMLI)
AnnaBridge	156:ff21514d8981	280	*/
AnnaBridge	156:ff21514d8981	281
AnnaBridge	156:ff21514d8981	282	typedef struct { /!< AMLI Structure /
AnnaBridge	156:ff21514d8981	283	__I uint32_t RESERVED0[896];
AnnaBridge	156:ff21514d8981	284	AMLI_RAMPRI_Type RAMPRI; /!< RAM configurable priority configuration structure. /
AnnaBridge	156:ff21514d8981	285	} NRF_AMLI_Type;
AnnaBridge	156:ff21514d8981	286
AnnaBridge	156:ff21514d8981	287
AnnaBridge	156:ff21514d8981	288	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	289	/* ================ RADIO ================ */
AnnaBridge	156:ff21514d8981	290	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	291
AnnaBridge	156:ff21514d8981	292
AnnaBridge	156:ff21514d8981	293	/**
AnnaBridge	156:ff21514d8981	294	* @brief The radio. (RADIO)
AnnaBridge	156:ff21514d8981	295	*/
AnnaBridge	156:ff21514d8981	296
AnnaBridge	156:ff21514d8981	297	typedef struct { /!< RADIO Structure /
AnnaBridge	156:ff21514d8981	298	__O uint32_t TASKS_TXEN; /!< Enable radio in TX mode. /
AnnaBridge	156:ff21514d8981	299	__O uint32_t TASKS_RXEN; /!< Enable radio in RX mode. /
AnnaBridge	156:ff21514d8981	300	__O uint32_t TASKS_START; /!< Start radio. /
AnnaBridge	156:ff21514d8981	301	__O uint32_t TASKS_STOP; /!< Stop radio. /
AnnaBridge	156:ff21514d8981	302	__O uint32_t TASKS_DISABLE; /!< Disable radio. /
AnnaBridge	156:ff21514d8981	303	__O uint32_t TASKS_RSSISTART; /!< Start the RSSI and take one sample of the receive signal strength. /
AnnaBridge	156:ff21514d8981	304	__O uint32_t TASKS_RSSISTOP; /!< Stop the RSSI measurement. /
AnnaBridge	156:ff21514d8981	305	__O uint32_t TASKS_BCSTART; /!< Start the bit counter. /
AnnaBridge	156:ff21514d8981	306	__O uint32_t TASKS_BCSTOP; /!< Stop the bit counter. /
AnnaBridge	156:ff21514d8981	307	__I uint32_t RESERVED0[55];
AnnaBridge	156:ff21514d8981	308	__IO uint32_t EVENTS_READY; /!< Ready event. /
AnnaBridge	156:ff21514d8981	309	__IO uint32_t EVENTS_ADDRESS; /!< Address event. /
AnnaBridge	156:ff21514d8981	310	__IO uint32_t EVENTS_PAYLOAD; /!< Payload event. /
AnnaBridge	156:ff21514d8981	311	__IO uint32_t EVENTS_END; /!< End event. /
AnnaBridge	156:ff21514d8981	312	__IO uint32_t EVENTS_DISABLED; /!< Disable event. /
AnnaBridge	156:ff21514d8981	313	__IO uint32_t EVENTS_DEVMATCH; /!< A device address match occurred on the last received packet. /
AnnaBridge	156:ff21514d8981	314	__IO uint32_t EVENTS_DEVMISS; /!< No device address match occurred on the last received packet. /
AnnaBridge	156:ff21514d8981	315	__IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
AnnaBridge	156:ff21514d8981	316	sample is ready for readout at the RSSISAMPLE register. */
AnnaBridge	156:ff21514d8981	317	__I uint32_t RESERVED1[2];
AnnaBridge	156:ff21514d8981	318	__IO uint32_t EVENTS_BCMATCH; /!< Bit counter reached bit count value specified in BCC register. /
AnnaBridge	156:ff21514d8981	319	__I uint32_t RESERVED2[53];
AnnaBridge	156:ff21514d8981	320	__IO uint32_t SHORTS; /!< Shortcuts for the radio. /
AnnaBridge	156:ff21514d8981	321	__I uint32_t RESERVED3[64];
AnnaBridge	156:ff21514d8981	322	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	323	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	324	__I uint32_t RESERVED4[61];
AnnaBridge	156:ff21514d8981	325	__I uint32_t CRCSTATUS; /!< CRC status of received packet. /
AnnaBridge	156:ff21514d8981	326	__I uint32_t RESERVED5;
AnnaBridge	156:ff21514d8981	327	__I uint32_t RXMATCH; /!< Received address. /
AnnaBridge	156:ff21514d8981	328	__I uint32_t RXCRC; /!< Received CRC. /
AnnaBridge	156:ff21514d8981	329	__I uint32_t DAI; /!< Device address match index. /
AnnaBridge	156:ff21514d8981	330	__I uint32_t RESERVED6[60];
AnnaBridge	156:ff21514d8981	331	__IO uint32_t PACKETPTR; /!< Packet pointer. Decision point: START task. /
AnnaBridge	156:ff21514d8981	332	__IO uint32_t FREQUENCY; /!< Frequency. /
AnnaBridge	156:ff21514d8981	333	__IO uint32_t TXPOWER; /!< Output power. /
AnnaBridge	156:ff21514d8981	334	__IO uint32_t MODE; /!< Data rate and modulation. /
AnnaBridge	156:ff21514d8981	335	__IO uint32_t PCNF0; /!< Packet configuration 0. /
AnnaBridge	156:ff21514d8981	336	__IO uint32_t PCNF1; /!< Packet configuration 1. /
AnnaBridge	156:ff21514d8981	337	__IO uint32_t BASE0; /!< Radio base address 0. Decision point: START task. /
AnnaBridge	156:ff21514d8981	338	__IO uint32_t BASE1; /!< Radio base address 1. Decision point: START task. /
AnnaBridge	156:ff21514d8981	339	__IO uint32_t PREFIX0; /!< Prefixes bytes for logical addresses 0 to 3. /
AnnaBridge	156:ff21514d8981	340	__IO uint32_t PREFIX1; /!< Prefixes bytes for logical addresses 4 to 7. /
AnnaBridge	156:ff21514d8981	341	__IO uint32_t TXADDRESS; /!< Transmit address select. /
AnnaBridge	156:ff21514d8981	342	__IO uint32_t RXADDRESSES; /!< Receive address select. /
AnnaBridge	156:ff21514d8981	343	__IO uint32_t CRCCNF; /!< CRC configuration. /
AnnaBridge	156:ff21514d8981	344	__IO uint32_t CRCPOLY; /!< CRC polynomial. /
AnnaBridge	156:ff21514d8981	345	__IO uint32_t CRCINIT; /!< CRC initial value. /
AnnaBridge	156:ff21514d8981	346	__IO uint32_t TEST; /!< Test features enable register. /
AnnaBridge	156:ff21514d8981	347	__IO uint32_t TIFS; /!< Inter Frame Spacing in microseconds. /
AnnaBridge	156:ff21514d8981	348	__I uint32_t RSSISAMPLE; /!< RSSI sample. /
AnnaBridge	156:ff21514d8981	349	__I uint32_t RESERVED7;
AnnaBridge	156:ff21514d8981	350	__I uint32_t STATE; /!< Current radio state. /
AnnaBridge	156:ff21514d8981	351	__IO uint32_t DATAWHITEIV; /!< Data whitening initial value. /
AnnaBridge	156:ff21514d8981	352	__I uint32_t RESERVED8[2];
AnnaBridge	156:ff21514d8981	353	__IO uint32_t BCC; /!< Bit counter compare. /
AnnaBridge	156:ff21514d8981	354	__I uint32_t RESERVED9[39];
AnnaBridge	156:ff21514d8981	355	__IO uint32_t DAB[8]; /!< Device address base segment. /
AnnaBridge	156:ff21514d8981	356	__IO uint32_t DAP[8]; /!< Device address prefix. /
AnnaBridge	156:ff21514d8981	357	__IO uint32_t DACNF; /!< Device address match configuration. /
AnnaBridge	156:ff21514d8981	358	__I uint32_t RESERVED10[56];
AnnaBridge	156:ff21514d8981	359	__IO uint32_t OVERRIDE0; /!< Trim value override register 0. /
AnnaBridge	156:ff21514d8981	360	__IO uint32_t OVERRIDE1; /!< Trim value override register 1. /
AnnaBridge	156:ff21514d8981	361	__IO uint32_t OVERRIDE2; /!< Trim value override register 2. /
AnnaBridge	156:ff21514d8981	362	__IO uint32_t OVERRIDE3; /!< Trim value override register 3. /
AnnaBridge	156:ff21514d8981	363	__IO uint32_t OVERRIDE4; /!< Trim value override register 4. /
AnnaBridge	156:ff21514d8981	364	__I uint32_t RESERVED11[561];
AnnaBridge	156:ff21514d8981	365	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	366	} NRF_RADIO_Type;
AnnaBridge	156:ff21514d8981	367
AnnaBridge	156:ff21514d8981	368
AnnaBridge	156:ff21514d8981	369	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	370	/* ================ UART ================ */
AnnaBridge	156:ff21514d8981	371	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	372
AnnaBridge	156:ff21514d8981	373
AnnaBridge	156:ff21514d8981	374	/**
AnnaBridge	156:ff21514d8981	375	* @brief Universal Asynchronous Receiver/Transmitter. (UART)
AnnaBridge	156:ff21514d8981	376	*/
AnnaBridge	156:ff21514d8981	377
AnnaBridge	156:ff21514d8981	378	typedef struct { /!< UART Structure /
AnnaBridge	156:ff21514d8981	379	__O uint32_t TASKS_STARTRX; /!< Start UART receiver. /
AnnaBridge	156:ff21514d8981	380	__O uint32_t TASKS_STOPRX; /!< Stop UART receiver. /
AnnaBridge	156:ff21514d8981	381	__O uint32_t TASKS_STARTTX; /!< Start UART transmitter. /
AnnaBridge	156:ff21514d8981	382	__O uint32_t TASKS_STOPTX; /!< Stop UART transmitter. /
AnnaBridge	156:ff21514d8981	383	__I uint32_t RESERVED0[3];
AnnaBridge	156:ff21514d8981	384	__O uint32_t TASKS_SUSPEND; /!< Suspend UART. /
AnnaBridge	156:ff21514d8981	385	__I uint32_t RESERVED1[56];
AnnaBridge	156:ff21514d8981	386	__IO uint32_t EVENTS_CTS; /!< CTS activated. /
AnnaBridge	156:ff21514d8981	387	__IO uint32_t EVENTS_NCTS; /!< CTS deactivated. /
AnnaBridge	156:ff21514d8981	388	__IO uint32_t EVENTS_RXDRDY; /!< Data received in RXD. /
AnnaBridge	156:ff21514d8981	389	__I uint32_t RESERVED2[4];
AnnaBridge	156:ff21514d8981	390	__IO uint32_t EVENTS_TXDRDY; /!< Data sent from TXD. /
AnnaBridge	156:ff21514d8981	391	__I uint32_t RESERVED3;
AnnaBridge	156:ff21514d8981	392	__IO uint32_t EVENTS_ERROR; /!< Error detected. /
AnnaBridge	156:ff21514d8981	393	__I uint32_t RESERVED4[7];
AnnaBridge	156:ff21514d8981	394	__IO uint32_t EVENTS_RXTO; /!< Receiver timeout. /
AnnaBridge	156:ff21514d8981	395	__I uint32_t RESERVED5[46];
AnnaBridge	156:ff21514d8981	396	__IO uint32_t SHORTS; /!< Shortcuts for UART. /
AnnaBridge	156:ff21514d8981	397	__I uint32_t RESERVED6[64];
AnnaBridge	156:ff21514d8981	398	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	399	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	400	__I uint32_t RESERVED7[93];
AnnaBridge	156:ff21514d8981	401	__IO uint32_t ERRORSRC; /!< Error source. Write error field to 1 to clear error. /
AnnaBridge	156:ff21514d8981	402	__I uint32_t RESERVED8[31];
AnnaBridge	156:ff21514d8981	403	__IO uint32_t ENABLE; /!< Enable UART and acquire IOs. /
AnnaBridge	156:ff21514d8981	404	__I uint32_t RESERVED9;
AnnaBridge	156:ff21514d8981	405	__IO uint32_t PSELRTS; /!< Pin select for RTS. /
AnnaBridge	156:ff21514d8981	406	__IO uint32_t PSELTXD; /!< Pin select for TXD. /
AnnaBridge	156:ff21514d8981	407	__IO uint32_t PSELCTS; /!< Pin select for CTS. /
AnnaBridge	156:ff21514d8981	408	__IO uint32_t PSELRXD; /!< Pin select for RXD. /
AnnaBridge	156:ff21514d8981	409	__I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
AnnaBridge	156:ff21514d8981	410	Once read the character is consumed. If read when no character
AnnaBridge	156:ff21514d8981	411	available, the UART will stop working. */
AnnaBridge	156:ff21514d8981	412	__O uint32_t TXD; /!< TXD register. /
AnnaBridge	156:ff21514d8981	413	__I uint32_t RESERVED10;
AnnaBridge	156:ff21514d8981	414	__IO uint32_t BAUDRATE; /!< UART Baudrate. /
AnnaBridge	156:ff21514d8981	415	__I uint32_t RESERVED11[17];
AnnaBridge	156:ff21514d8981	416	__IO uint32_t CONFIG; /!< Configuration of parity and hardware flow control register. /
AnnaBridge	156:ff21514d8981	417	__I uint32_t RESERVED12[675];
AnnaBridge	156:ff21514d8981	418	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	419	} NRF_UART_Type;
AnnaBridge	156:ff21514d8981	420
AnnaBridge	156:ff21514d8981	421
AnnaBridge	156:ff21514d8981	422	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	423	/* ================ SPI ================ */
AnnaBridge	156:ff21514d8981	424	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	425
AnnaBridge	156:ff21514d8981	426
AnnaBridge	156:ff21514d8981	427	/**
AnnaBridge	156:ff21514d8981	428	* @brief SPI master 0. (SPI)
AnnaBridge	156:ff21514d8981	429	*/
AnnaBridge	156:ff21514d8981	430
AnnaBridge	156:ff21514d8981	431	typedef struct { /!< SPI Structure /
AnnaBridge	156:ff21514d8981	432	__I uint32_t RESERVED0[66];
AnnaBridge	156:ff21514d8981	433	__IO uint32_t EVENTS_READY; /!< TXD byte sent and RXD byte received. /
AnnaBridge	156:ff21514d8981	434	__I uint32_t RESERVED1[126];
AnnaBridge	156:ff21514d8981	435	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	436	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	437	__I uint32_t RESERVED2[125];
AnnaBridge	156:ff21514d8981	438	__IO uint32_t ENABLE; /!< Enable SPI. /
AnnaBridge	156:ff21514d8981	439	__I uint32_t RESERVED3;
AnnaBridge	156:ff21514d8981	440	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
AnnaBridge	156:ff21514d8981	441	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
AnnaBridge	156:ff21514d8981	442	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
AnnaBridge	156:ff21514d8981	443	__I uint32_t RESERVED4;
AnnaBridge	156:ff21514d8981	444	__I uint32_t RXD; /!< RX data. /
AnnaBridge	156:ff21514d8981	445	__IO uint32_t TXD; /!< TX data. /
AnnaBridge	156:ff21514d8981	446	__I uint32_t RESERVED5;
AnnaBridge	156:ff21514d8981	447	__IO uint32_t FREQUENCY; /!< SPI frequency /
AnnaBridge	156:ff21514d8981	448	__I uint32_t RESERVED6[11];
AnnaBridge	156:ff21514d8981	449	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	156:ff21514d8981	450	__I uint32_t RESERVED7[681];
AnnaBridge	156:ff21514d8981	451	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	452	} NRF_SPI_Type;
AnnaBridge	156:ff21514d8981	453
AnnaBridge	156:ff21514d8981	454
AnnaBridge	156:ff21514d8981	455	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	456	/* ================ TWI ================ */
AnnaBridge	156:ff21514d8981	457	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	458
AnnaBridge	156:ff21514d8981	459
AnnaBridge	156:ff21514d8981	460	/**
AnnaBridge	156:ff21514d8981	461	* @brief Two-wire interface master 0. (TWI)
AnnaBridge	156:ff21514d8981	462	*/
AnnaBridge	156:ff21514d8981	463
AnnaBridge	156:ff21514d8981	464	typedef struct { /!< TWI Structure /
AnnaBridge	156:ff21514d8981	465	__O uint32_t TASKS_STARTRX; /!< Start 2-Wire master receive sequence. /
AnnaBridge	156:ff21514d8981	466	__I uint32_t RESERVED0;
AnnaBridge	156:ff21514d8981	467	__O uint32_t TASKS_STARTTX; /!< Start 2-Wire master transmit sequence. /
AnnaBridge	156:ff21514d8981	468	__I uint32_t RESERVED1[2];
AnnaBridge	156:ff21514d8981	469	__O uint32_t TASKS_STOP; /!< Stop 2-Wire transaction. /
AnnaBridge	156:ff21514d8981	470	__I uint32_t RESERVED2;
AnnaBridge	156:ff21514d8981	471	__O uint32_t TASKS_SUSPEND; /!< Suspend 2-Wire transaction. /
AnnaBridge	156:ff21514d8981	472	__O uint32_t TASKS_RESUME; /!< Resume 2-Wire transaction. /
AnnaBridge	156:ff21514d8981	473	__I uint32_t RESERVED3[56];
AnnaBridge	156:ff21514d8981	474	__IO uint32_t EVENTS_STOPPED; /!< Two-wire stopped. /
AnnaBridge	156:ff21514d8981	475	__IO uint32_t EVENTS_RXDREADY; /!< Two-wire ready to deliver new RXD byte received. /
AnnaBridge	156:ff21514d8981	476	__I uint32_t RESERVED4[4];
AnnaBridge	156:ff21514d8981	477	__IO uint32_t EVENTS_TXDSENT; /!< Two-wire finished sending last TXD byte. /
AnnaBridge	156:ff21514d8981	478	__I uint32_t RESERVED5;
AnnaBridge	156:ff21514d8981	479	__IO uint32_t EVENTS_ERROR; /!< Two-wire error detected. /
AnnaBridge	156:ff21514d8981	480	__I uint32_t RESERVED6[4];
AnnaBridge	156:ff21514d8981	481	__IO uint32_t EVENTS_BB; /!< Two-wire byte boundary. /
AnnaBridge	156:ff21514d8981	482	__I uint32_t RESERVED7[3];
AnnaBridge	156:ff21514d8981	483	__IO uint32_t EVENTS_SUSPENDED; /!< Two-wire suspended. /
AnnaBridge	156:ff21514d8981	484	__I uint32_t RESERVED8[45];
AnnaBridge	156:ff21514d8981	485	__IO uint32_t SHORTS; /!< Shortcuts for TWI. /
AnnaBridge	156:ff21514d8981	486	__I uint32_t RESERVED9[64];
AnnaBridge	156:ff21514d8981	487	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	488	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	489	__I uint32_t RESERVED10[110];
AnnaBridge	156:ff21514d8981	490	__IO uint32_t ERRORSRC; /!< Two-wire error source. Write error field to 1 to clear error. /
AnnaBridge	156:ff21514d8981	491	__I uint32_t RESERVED11[14];
AnnaBridge	156:ff21514d8981	492	__IO uint32_t ENABLE; /!< Enable two-wire master. /
AnnaBridge	156:ff21514d8981	493	__I uint32_t RESERVED12;
AnnaBridge	156:ff21514d8981	494	__IO uint32_t PSELSCL; /!< Pin select for SCL. /
AnnaBridge	156:ff21514d8981	495	__IO uint32_t PSELSDA; /!< Pin select for SDA. /
AnnaBridge	156:ff21514d8981	496	__I uint32_t RESERVED13[2];
AnnaBridge	156:ff21514d8981	497	__I uint32_t RXD; /!< RX data register. /
AnnaBridge	156:ff21514d8981	498	__IO uint32_t TXD; /!< TX data register. /
AnnaBridge	156:ff21514d8981	499	__I uint32_t RESERVED14;
AnnaBridge	156:ff21514d8981	500	__IO uint32_t FREQUENCY; /!< Two-wire frequency. /
AnnaBridge	156:ff21514d8981	501	__I uint32_t RESERVED15[24];
AnnaBridge	156:ff21514d8981	502	__IO uint32_t ADDRESS; /!< Address used in the two-wire transfer. /
AnnaBridge	156:ff21514d8981	503	__I uint32_t RESERVED16[668];
AnnaBridge	156:ff21514d8981	504	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	505	} NRF_TWI_Type;
AnnaBridge	156:ff21514d8981	506
AnnaBridge	156:ff21514d8981	507
AnnaBridge	156:ff21514d8981	508	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	509	/* ================ SPIS ================ */
AnnaBridge	156:ff21514d8981	510	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	511
AnnaBridge	156:ff21514d8981	512
AnnaBridge	156:ff21514d8981	513	/**
AnnaBridge	156:ff21514d8981	514	* @brief SPI slave 1. (SPIS)
AnnaBridge	156:ff21514d8981	515	*/
AnnaBridge	156:ff21514d8981	516
AnnaBridge	156:ff21514d8981	517	typedef struct { /!< SPIS Structure /
AnnaBridge	156:ff21514d8981	518	__I uint32_t RESERVED0[9];
AnnaBridge	156:ff21514d8981	519	__O uint32_t TASKS_ACQUIRE; /!< Acquire SPI semaphore. /
AnnaBridge	156:ff21514d8981	520	__O uint32_t TASKS_RELEASE; /!< Release SPI semaphore. /
AnnaBridge	156:ff21514d8981	521	__I uint32_t RESERVED1[54];
AnnaBridge	156:ff21514d8981	522	__IO uint32_t EVENTS_END; /!< Granted transaction completed. /
AnnaBridge	156:ff21514d8981	523	__I uint32_t RESERVED2[2];
AnnaBridge	156:ff21514d8981	524	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached /
AnnaBridge	156:ff21514d8981	525	__I uint32_t RESERVED3[5];
AnnaBridge	156:ff21514d8981	526	__IO uint32_t EVENTS_ACQUIRED; /!< Semaphore acquired. /
AnnaBridge	156:ff21514d8981	527	__I uint32_t RESERVED4[53];
AnnaBridge	156:ff21514d8981	528	__IO uint32_t SHORTS; /!< Shortcuts for SPIS. /
AnnaBridge	156:ff21514d8981	529	__I uint32_t RESERVED5[64];
AnnaBridge	156:ff21514d8981	530	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	531	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	532	__I uint32_t RESERVED6[61];
AnnaBridge	156:ff21514d8981	533	__I uint32_t SEMSTAT; /!< Semaphore status. /
AnnaBridge	156:ff21514d8981	534	__I uint32_t RESERVED7[15];
AnnaBridge	156:ff21514d8981	535	__IO uint32_t STATUS; /!< Status from last transaction. /
AnnaBridge	156:ff21514d8981	536	__I uint32_t RESERVED8[47];
AnnaBridge	156:ff21514d8981	537	__IO uint32_t ENABLE; /!< Enable SPIS. /
AnnaBridge	156:ff21514d8981	538	__I uint32_t RESERVED9;
AnnaBridge	156:ff21514d8981	539	__IO uint32_t PSELSCK; /!< Pin select for SCK. /
AnnaBridge	156:ff21514d8981	540	__IO uint32_t PSELMISO; /!< Pin select for MISO. /
AnnaBridge	156:ff21514d8981	541	__IO uint32_t PSELMOSI; /!< Pin select for MOSI. /
AnnaBridge	156:ff21514d8981	542	__IO uint32_t PSELCSN; /!< Pin select for CSN. /
AnnaBridge	156:ff21514d8981	543	__I uint32_t RESERVED10[7];
AnnaBridge	156:ff21514d8981	544	__IO uint32_t RXDPTR; /!< RX data pointer. /
AnnaBridge	156:ff21514d8981	545	__IO uint32_t MAXRX; /!< Maximum number of bytes in the receive buffer. /
AnnaBridge	156:ff21514d8981	546	__I uint32_t AMOUNTRX; /!< Number of bytes received in last granted transaction. /
AnnaBridge	156:ff21514d8981	547	__I uint32_t RESERVED11;
AnnaBridge	156:ff21514d8981	548	__IO uint32_t TXDPTR; /!< TX data pointer. /
AnnaBridge	156:ff21514d8981	549	__IO uint32_t MAXTX; /!< Maximum number of bytes in the transmit buffer. /
AnnaBridge	156:ff21514d8981	550	__I uint32_t AMOUNTTX; /!< Number of bytes transmitted in last granted transaction. /
AnnaBridge	156:ff21514d8981	551	__I uint32_t RESERVED12;
AnnaBridge	156:ff21514d8981	552	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	156:ff21514d8981	553	__I uint32_t RESERVED13;
AnnaBridge	156:ff21514d8981	554	__IO uint32_t DEF; /!< Default character. /
AnnaBridge	156:ff21514d8981	555	__I uint32_t RESERVED14[24];
AnnaBridge	156:ff21514d8981	556	__IO uint32_t ORC; /!< Over-read character. /
AnnaBridge	156:ff21514d8981	557	__I uint32_t RESERVED15[654];
AnnaBridge	156:ff21514d8981	558	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	559	} NRF_SPIS_Type;
AnnaBridge	156:ff21514d8981	560
AnnaBridge	156:ff21514d8981	561
AnnaBridge	156:ff21514d8981	562	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	563	/* ================ SPIM ================ */
AnnaBridge	156:ff21514d8981	564	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	565
AnnaBridge	156:ff21514d8981	566
AnnaBridge	156:ff21514d8981	567	/**
AnnaBridge	156:ff21514d8981	568	* @brief SPI master with easyDMA 1. (SPIM)
AnnaBridge	156:ff21514d8981	569	*/
AnnaBridge	156:ff21514d8981	570
AnnaBridge	156:ff21514d8981	571	typedef struct { /!< SPIM Structure /
AnnaBridge	156:ff21514d8981	572	__I uint32_t RESERVED0[4];
AnnaBridge	156:ff21514d8981	573	__O uint32_t TASKS_START; /!< Start SPI transaction. /
AnnaBridge	156:ff21514d8981	574	__O uint32_t TASKS_STOP; /!< Stop SPI transaction. /
AnnaBridge	156:ff21514d8981	575	__I uint32_t RESERVED1;
AnnaBridge	156:ff21514d8981	576	__O uint32_t TASKS_SUSPEND; /!< Suspend SPI transaction. /
AnnaBridge	156:ff21514d8981	577	__O uint32_t TASKS_RESUME; /!< Resume SPI transaction. /
AnnaBridge	156:ff21514d8981	578	__I uint32_t RESERVED2[56];
AnnaBridge	156:ff21514d8981	579	__IO uint32_t EVENTS_STOPPED; /!< SPI transaction has stopped. /
AnnaBridge	156:ff21514d8981	580	__I uint32_t RESERVED3[2];
AnnaBridge	156:ff21514d8981	581	__IO uint32_t EVENTS_ENDRX; /!< End of RXD buffer reached. /
AnnaBridge	156:ff21514d8981	582	__I uint32_t RESERVED4[3];
AnnaBridge	156:ff21514d8981	583	__IO uint32_t EVENTS_ENDTX; /!< End of TXD buffer reached. /
AnnaBridge	156:ff21514d8981	584	__I uint32_t RESERVED5[10];
AnnaBridge	156:ff21514d8981	585	__IO uint32_t EVENTS_STARTED; /!< Transaction started. /
AnnaBridge	156:ff21514d8981	586	__I uint32_t RESERVED6[109];
AnnaBridge	156:ff21514d8981	587	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	588	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	589	__I uint32_t RESERVED7[125];
AnnaBridge	156:ff21514d8981	590	__IO uint32_t ENABLE; /!< Enable SPIM. /
AnnaBridge	156:ff21514d8981	591	__I uint32_t RESERVED8;
AnnaBridge	156:ff21514d8981	592	SPIM_PSEL_Type PSEL; /!< Pin select configuration. /
AnnaBridge	156:ff21514d8981	593	__I uint32_t RESERVED9[4];
AnnaBridge	156:ff21514d8981	594	__IO uint32_t FREQUENCY; /!< SPI frequency. /
AnnaBridge	156:ff21514d8981	595	__I uint32_t RESERVED10[3];
AnnaBridge	156:ff21514d8981	596	SPIM_RXD_Type RXD; /!< RXD EasyDMA configuration and status. /
AnnaBridge	156:ff21514d8981	597	__I uint32_t RESERVED11;
AnnaBridge	156:ff21514d8981	598	SPIM_TXD_Type TXD; /!< TXD EasyDMA configuration and status. /
AnnaBridge	156:ff21514d8981	599	__I uint32_t RESERVED12;
AnnaBridge	156:ff21514d8981	600	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	156:ff21514d8981	601	__I uint32_t RESERVED13[26];
AnnaBridge	156:ff21514d8981	602	__IO uint32_t ORC; /!< Over-read character. /
AnnaBridge	156:ff21514d8981	603	__I uint32_t RESERVED14[654];
AnnaBridge	156:ff21514d8981	604	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	605	} NRF_SPIM_Type;
AnnaBridge	156:ff21514d8981	606
AnnaBridge	156:ff21514d8981	607
AnnaBridge	156:ff21514d8981	608	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	609	/* ================ GPIOTE ================ */
AnnaBridge	156:ff21514d8981	610	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	611
AnnaBridge	156:ff21514d8981	612
AnnaBridge	156:ff21514d8981	613	/**
AnnaBridge	156:ff21514d8981	614	* @brief GPIO tasks and events. (GPIOTE)
AnnaBridge	156:ff21514d8981	615	*/
AnnaBridge	156:ff21514d8981	616
AnnaBridge	156:ff21514d8981	617	typedef struct { /!< GPIOTE Structure /
AnnaBridge	156:ff21514d8981	618	__O uint32_t TASKS_OUT[4]; /!< Tasks asssociated with GPIOTE channels. /
AnnaBridge	156:ff21514d8981	619	__I uint32_t RESERVED0[60];
AnnaBridge	156:ff21514d8981	620	__IO uint32_t EVENTS_IN[4]; /!< Tasks asssociated with GPIOTE channels. /
AnnaBridge	156:ff21514d8981	621	__I uint32_t RESERVED1[27];
AnnaBridge	156:ff21514d8981	622	__IO uint32_t EVENTS_PORT; /!< Event generated from multiple pins. /
AnnaBridge	156:ff21514d8981	623	__I uint32_t RESERVED2[97];
AnnaBridge	156:ff21514d8981	624	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	625	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	626	__I uint32_t RESERVED3[129];
AnnaBridge	156:ff21514d8981	627	__IO uint32_t CONFIG[4]; /!< Channel configuration registers. /
AnnaBridge	156:ff21514d8981	628	__I uint32_t RESERVED4[695];
AnnaBridge	156:ff21514d8981	629	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	630	} NRF_GPIOTE_Type;
AnnaBridge	156:ff21514d8981	631
AnnaBridge	156:ff21514d8981	632
AnnaBridge	156:ff21514d8981	633	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	634	/* ================ ADC ================ */
AnnaBridge	156:ff21514d8981	635	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	636
AnnaBridge	156:ff21514d8981	637
AnnaBridge	156:ff21514d8981	638	/**
AnnaBridge	156:ff21514d8981	639	* @brief Analog to digital converter. (ADC)
AnnaBridge	156:ff21514d8981	640	*/
AnnaBridge	156:ff21514d8981	641
AnnaBridge	156:ff21514d8981	642	typedef struct { /!< ADC Structure /
AnnaBridge	156:ff21514d8981	643	__O uint32_t TASKS_START; /!< Start an ADC conversion. /
AnnaBridge	156:ff21514d8981	644	__O uint32_t TASKS_STOP; /!< Stop ADC. /
AnnaBridge	156:ff21514d8981	645	__I uint32_t RESERVED0[62];
AnnaBridge	156:ff21514d8981	646	__IO uint32_t EVENTS_END; /!< ADC conversion complete. /
AnnaBridge	156:ff21514d8981	647	__I uint32_t RESERVED1[128];
AnnaBridge	156:ff21514d8981	648	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	649	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	650	__I uint32_t RESERVED2[61];
AnnaBridge	156:ff21514d8981	651	__I uint32_t BUSY; /!< ADC busy register. /
AnnaBridge	156:ff21514d8981	652	__I uint32_t RESERVED3[63];
AnnaBridge	156:ff21514d8981	653	__IO uint32_t ENABLE; /!< ADC enable. /
AnnaBridge	156:ff21514d8981	654	__IO uint32_t CONFIG; /!< ADC configuration register. /
AnnaBridge	156:ff21514d8981	655	__I uint32_t RESULT; /!< Result of ADC conversion. /
AnnaBridge	156:ff21514d8981	656	__I uint32_t RESERVED4[700];
AnnaBridge	156:ff21514d8981	657	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	658	} NRF_ADC_Type;
AnnaBridge	156:ff21514d8981	659
AnnaBridge	156:ff21514d8981	660
AnnaBridge	156:ff21514d8981	661	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	662	/* ================ TIMER ================ */
AnnaBridge	156:ff21514d8981	663	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	664
AnnaBridge	156:ff21514d8981	665
AnnaBridge	156:ff21514d8981	666	/**
AnnaBridge	156:ff21514d8981	667	* @brief Timer 0. (TIMER)
AnnaBridge	156:ff21514d8981	668	*/
AnnaBridge	156:ff21514d8981	669
AnnaBridge	156:ff21514d8981	670	typedef struct { /!< TIMER Structure /
AnnaBridge	156:ff21514d8981	671	__O uint32_t TASKS_START; /!< Start Timer. /
AnnaBridge	156:ff21514d8981	672	__O uint32_t TASKS_STOP; /!< Stop Timer. /
AnnaBridge	156:ff21514d8981	673	__O uint32_t TASKS_COUNT; /!< Increment Timer (In counter mode). /
AnnaBridge	156:ff21514d8981	674	__O uint32_t TASKS_CLEAR; /!< Clear timer. /
AnnaBridge	156:ff21514d8981	675	__O uint32_t TASKS_SHUTDOWN; /!< Shutdown timer. /
AnnaBridge	156:ff21514d8981	676	__I uint32_t RESERVED0[11];
AnnaBridge	156:ff21514d8981	677	__O uint32_t TASKS_CAPTURE[4]; /!< Capture Timer value to CC[n] registers. /
AnnaBridge	156:ff21514d8981	678	__I uint32_t RESERVED1[60];
AnnaBridge	156:ff21514d8981	679	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
AnnaBridge	156:ff21514d8981	680	__I uint32_t RESERVED2[44];
AnnaBridge	156:ff21514d8981	681	__IO uint32_t SHORTS; /!< Shortcuts for Timer. /
AnnaBridge	156:ff21514d8981	682	__I uint32_t RESERVED3[64];
AnnaBridge	156:ff21514d8981	683	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	684	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	685	__I uint32_t RESERVED4[126];
AnnaBridge	156:ff21514d8981	686	__IO uint32_t MODE; /!< Timer Mode selection. /
AnnaBridge	156:ff21514d8981	687	__IO uint32_t BITMODE; /!< Sets timer behaviour. /
AnnaBridge	156:ff21514d8981	688	__I uint32_t RESERVED5;
AnnaBridge	156:ff21514d8981	689	__IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
AnnaBridge	156:ff21514d8981	690	clock frequency is divided by 2^SCALE. */
AnnaBridge	156:ff21514d8981	691	__I uint32_t RESERVED6[11];
AnnaBridge	156:ff21514d8981	692	__IO uint32_t CC[4]; /!< Capture/compare registers. /
AnnaBridge	156:ff21514d8981	693	__I uint32_t RESERVED7[683];
AnnaBridge	156:ff21514d8981	694	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	695	} NRF_TIMER_Type;
AnnaBridge	156:ff21514d8981	696
AnnaBridge	156:ff21514d8981	697
AnnaBridge	156:ff21514d8981	698	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	699	/* ================ RTC ================ */
AnnaBridge	156:ff21514d8981	700	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	701
AnnaBridge	156:ff21514d8981	702
AnnaBridge	156:ff21514d8981	703	/**
AnnaBridge	156:ff21514d8981	704	* @brief Real time counter 0. (RTC)
AnnaBridge	156:ff21514d8981	705	*/
AnnaBridge	156:ff21514d8981	706
AnnaBridge	156:ff21514d8981	707	typedef struct { /!< RTC Structure /
AnnaBridge	156:ff21514d8981	708	__O uint32_t TASKS_START; /!< Start RTC Counter. /
AnnaBridge	156:ff21514d8981	709	__O uint32_t TASKS_STOP; /!< Stop RTC Counter. /
AnnaBridge	156:ff21514d8981	710	__O uint32_t TASKS_CLEAR; /!< Clear RTC Counter. /
AnnaBridge	156:ff21514d8981	711	__O uint32_t TASKS_TRIGOVRFLW; /!< Set COUNTER to 0xFFFFFFF0. /
AnnaBridge	156:ff21514d8981	712	__I uint32_t RESERVED0[60];
AnnaBridge	156:ff21514d8981	713	__IO uint32_t EVENTS_TICK; /!< Event on COUNTER increment. /
AnnaBridge	156:ff21514d8981	714	__IO uint32_t EVENTS_OVRFLW; /!< Event on COUNTER overflow. /
AnnaBridge	156:ff21514d8981	715	__I uint32_t RESERVED1[14];
AnnaBridge	156:ff21514d8981	716	__IO uint32_t EVENTS_COMPARE[4]; /!< Compare event on CC[n] match. /
AnnaBridge	156:ff21514d8981	717	__I uint32_t RESERVED2[109];
AnnaBridge	156:ff21514d8981	718	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	719	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	720	__I uint32_t RESERVED3[13];
AnnaBridge	156:ff21514d8981	721	__IO uint32_t EVTEN; /!< Configures event enable routing to PPI for each RTC event. /
AnnaBridge	156:ff21514d8981	722	__IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
AnnaBridge	156:ff21514d8981	723	the value of EVTEN. */
AnnaBridge	156:ff21514d8981	724	__IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
AnnaBridge	156:ff21514d8981	725	gives the value of EVTEN. */
AnnaBridge	156:ff21514d8981	726	__I uint32_t RESERVED4[110];
AnnaBridge	156:ff21514d8981	727	__I uint32_t COUNTER; /!< Current COUNTER value. /
AnnaBridge	156:ff21514d8981	728	__IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
AnnaBridge	156:ff21514d8981	729	Must be written when RTC is STOPed. */
AnnaBridge	156:ff21514d8981	730	__I uint32_t RESERVED5[13];
AnnaBridge	156:ff21514d8981	731	__IO uint32_t CC[4]; /!< Capture/compare registers. /
AnnaBridge	156:ff21514d8981	732	__I uint32_t RESERVED6[683];
AnnaBridge	156:ff21514d8981	733	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	734	} NRF_RTC_Type;
AnnaBridge	156:ff21514d8981	735
AnnaBridge	156:ff21514d8981	736
AnnaBridge	156:ff21514d8981	737	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	738	/* ================ TEMP ================ */
AnnaBridge	156:ff21514d8981	739	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	740
AnnaBridge	156:ff21514d8981	741
AnnaBridge	156:ff21514d8981	742	/**
AnnaBridge	156:ff21514d8981	743	* @brief Temperature Sensor. (TEMP)
AnnaBridge	156:ff21514d8981	744	*/
AnnaBridge	156:ff21514d8981	745
AnnaBridge	156:ff21514d8981	746	typedef struct { /!< TEMP Structure /
AnnaBridge	156:ff21514d8981	747	__O uint32_t TASKS_START; /!< Start temperature measurement. /
AnnaBridge	156:ff21514d8981	748	__O uint32_t TASKS_STOP; /!< Stop temperature measurement. /
AnnaBridge	156:ff21514d8981	749	__I uint32_t RESERVED0[62];
AnnaBridge	156:ff21514d8981	750	__IO uint32_t EVENTS_DATARDY; /!< Temperature measurement complete, data ready event. /
AnnaBridge	156:ff21514d8981	751	__I uint32_t RESERVED1[128];
AnnaBridge	156:ff21514d8981	752	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	753	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	754	__I uint32_t RESERVED2[127];
AnnaBridge	156:ff21514d8981	755	__I int32_t TEMP; /!< Die temperature in degC, 2's complement format, 0.25 degC pecision. /
AnnaBridge	156:ff21514d8981	756	__I uint32_t RESERVED3[700];
AnnaBridge	156:ff21514d8981	757	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	758	} NRF_TEMP_Type;
AnnaBridge	156:ff21514d8981	759
AnnaBridge	156:ff21514d8981	760
AnnaBridge	156:ff21514d8981	761	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	762	/* ================ RNG ================ */
AnnaBridge	156:ff21514d8981	763	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	764
AnnaBridge	156:ff21514d8981	765
AnnaBridge	156:ff21514d8981	766	/**
AnnaBridge	156:ff21514d8981	767	* @brief Random Number Generator. (RNG)
AnnaBridge	156:ff21514d8981	768	*/
AnnaBridge	156:ff21514d8981	769
AnnaBridge	156:ff21514d8981	770	typedef struct { /!< RNG Structure /
AnnaBridge	156:ff21514d8981	771	__O uint32_t TASKS_START; /!< Start the random number generator. /
AnnaBridge	156:ff21514d8981	772	__O uint32_t TASKS_STOP; /!< Stop the random number generator. /
AnnaBridge	156:ff21514d8981	773	__I uint32_t RESERVED0[62];
AnnaBridge	156:ff21514d8981	774	__IO uint32_t EVENTS_VALRDY; /!< New random number generated and written to VALUE register. /
AnnaBridge	156:ff21514d8981	775	__I uint32_t RESERVED1[63];
AnnaBridge	156:ff21514d8981	776	__IO uint32_t SHORTS; /!< Shortcuts for the RNG. /
AnnaBridge	156:ff21514d8981	777	__I uint32_t RESERVED2[64];
AnnaBridge	156:ff21514d8981	778	__IO uint32_t INTENSET; /!< Interrupt enable set register /
AnnaBridge	156:ff21514d8981	779	__IO uint32_t INTENCLR; /!< Interrupt enable clear register /
AnnaBridge	156:ff21514d8981	780	__I uint32_t RESERVED3[126];
AnnaBridge	156:ff21514d8981	781	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	156:ff21514d8981	782	__I uint32_t VALUE; /!< RNG random number. /
AnnaBridge	156:ff21514d8981	783	__I uint32_t RESERVED4[700];
AnnaBridge	156:ff21514d8981	784	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	785	} NRF_RNG_Type;
AnnaBridge	156:ff21514d8981	786
AnnaBridge	156:ff21514d8981	787
AnnaBridge	156:ff21514d8981	788	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	789	/* ================ ECB ================ */
AnnaBridge	156:ff21514d8981	790	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	791
AnnaBridge	156:ff21514d8981	792
AnnaBridge	156:ff21514d8981	793	/**
AnnaBridge	156:ff21514d8981	794	* @brief AES ECB Mode Encryption. (ECB)
AnnaBridge	156:ff21514d8981	795	*/
AnnaBridge	156:ff21514d8981	796
AnnaBridge	156:ff21514d8981	797	typedef struct { /!< ECB Structure /
AnnaBridge	156:ff21514d8981	798	__O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
AnnaBridge	156:ff21514d8981	799	will not initiate a new encryption and the ERRORECB event will
AnnaBridge	156:ff21514d8981	800	be triggered. */
AnnaBridge	156:ff21514d8981	801	__O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
AnnaBridge	156:ff21514d8981	802	this will will trigger the ERRORECB event. */
AnnaBridge	156:ff21514d8981	803	__I uint32_t RESERVED0[62];
AnnaBridge	156:ff21514d8981	804	__IO uint32_t EVENTS_ENDECB; /!< ECB block encrypt complete. /
AnnaBridge	156:ff21514d8981	805	__IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
AnnaBridge	156:ff21514d8981	806	error. */
AnnaBridge	156:ff21514d8981	807	__I uint32_t RESERVED1[127];
AnnaBridge	156:ff21514d8981	808	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	809	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	810	__I uint32_t RESERVED2[126];
AnnaBridge	156:ff21514d8981	811	__IO uint32_t ECBDATAPTR; /!< ECB block encrypt memory pointer. /
AnnaBridge	156:ff21514d8981	812	__I uint32_t RESERVED3[701];
AnnaBridge	156:ff21514d8981	813	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	814	} NRF_ECB_Type;
AnnaBridge	156:ff21514d8981	815
AnnaBridge	156:ff21514d8981	816
AnnaBridge	156:ff21514d8981	817	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	818	/* ================ AAR ================ */
AnnaBridge	156:ff21514d8981	819	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	820
AnnaBridge	156:ff21514d8981	821
AnnaBridge	156:ff21514d8981	822	/**
AnnaBridge	156:ff21514d8981	823	* @brief Accelerated Address Resolver. (AAR)
AnnaBridge	156:ff21514d8981	824	*/
AnnaBridge	156:ff21514d8981	825
AnnaBridge	156:ff21514d8981	826	typedef struct { /!< AAR Structure /
AnnaBridge	156:ff21514d8981	827	__O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
AnnaBridge	156:ff21514d8981	828	data structure. */
AnnaBridge	156:ff21514d8981	829	__I uint32_t RESERVED0;
AnnaBridge	156:ff21514d8981	830	__O uint32_t TASKS_STOP; /!< Stop resolving addresses. /
AnnaBridge	156:ff21514d8981	831	__I uint32_t RESERVED1[61];
AnnaBridge	156:ff21514d8981	832	__IO uint32_t EVENTS_END; /!< Address resolution procedure completed. /
AnnaBridge	156:ff21514d8981	833	__IO uint32_t EVENTS_RESOLVED; /!< Address resolved. /
AnnaBridge	156:ff21514d8981	834	__IO uint32_t EVENTS_NOTRESOLVED; /!< Address not resolved. /
AnnaBridge	156:ff21514d8981	835	__I uint32_t RESERVED2[126];
AnnaBridge	156:ff21514d8981	836	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	837	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	838	__I uint32_t RESERVED3[61];
AnnaBridge	156:ff21514d8981	839	__I uint32_t STATUS; /!< Resolution status. /
AnnaBridge	156:ff21514d8981	840	__I uint32_t RESERVED4[63];
AnnaBridge	156:ff21514d8981	841	__IO uint32_t ENABLE; /!< Enable AAR. /
AnnaBridge	156:ff21514d8981	842	__IO uint32_t NIRK; /!< Number of Identity root Keys in the IRK data structure. /
AnnaBridge	156:ff21514d8981	843	__IO uint32_t IRKPTR; /!< Pointer to the IRK data structure. /
AnnaBridge	156:ff21514d8981	844	__I uint32_t RESERVED5;
AnnaBridge	156:ff21514d8981	845	__IO uint32_t ADDRPTR; /!< Pointer to the resolvable address (6 bytes). /
AnnaBridge	156:ff21514d8981	846	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
AnnaBridge	156:ff21514d8981	847	during resolution. A minimum of 3 bytes must be reserved. */
AnnaBridge	156:ff21514d8981	848	__I uint32_t RESERVED6[697];
AnnaBridge	156:ff21514d8981	849	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	850	} NRF_AAR_Type;
AnnaBridge	156:ff21514d8981	851
AnnaBridge	156:ff21514d8981	852
AnnaBridge	156:ff21514d8981	853	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	854	/* ================ CCM ================ */
AnnaBridge	156:ff21514d8981	855	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	856
AnnaBridge	156:ff21514d8981	857
AnnaBridge	156:ff21514d8981	858	/**
AnnaBridge	156:ff21514d8981	859	* @brief AES CCM Mode Encryption. (CCM)
AnnaBridge	156:ff21514d8981	860	*/
AnnaBridge	156:ff21514d8981	861
AnnaBridge	156:ff21514d8981	862	typedef struct { /!< CCM Structure /
AnnaBridge	156:ff21514d8981	863	__O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
AnnaBridge	156:ff21514d8981	864	itself when completed. */
AnnaBridge	156:ff21514d8981	865	__O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
AnnaBridge	156:ff21514d8981	866	completed. */
AnnaBridge	156:ff21514d8981	867	__O uint32_t TASKS_STOP; /!< Stop encrypt/decrypt. /
AnnaBridge	156:ff21514d8981	868	__I uint32_t RESERVED0[61];
AnnaBridge	156:ff21514d8981	869	__IO uint32_t EVENTS_ENDKSGEN; /!< Keystream generation completed. /
AnnaBridge	156:ff21514d8981	870	__IO uint32_t EVENTS_ENDCRYPT; /!< Encrypt/decrypt completed. /
AnnaBridge	156:ff21514d8981	871	__IO uint32_t EVENTS_ERROR; /!< Error happened. /
AnnaBridge	156:ff21514d8981	872	__I uint32_t RESERVED1[61];
AnnaBridge	156:ff21514d8981	873	__IO uint32_t SHORTS; /!< Shortcuts for the CCM. /
AnnaBridge	156:ff21514d8981	874	__I uint32_t RESERVED2[64];
AnnaBridge	156:ff21514d8981	875	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	876	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	877	__I uint32_t RESERVED3[61];
AnnaBridge	156:ff21514d8981	878	__I uint32_t MICSTATUS; /!< CCM RX MIC check result. /
AnnaBridge	156:ff21514d8981	879	__I uint32_t RESERVED4[63];
AnnaBridge	156:ff21514d8981	880	__IO uint32_t ENABLE; /!< CCM enable. /
AnnaBridge	156:ff21514d8981	881	__IO uint32_t MODE; /!< Operation mode. /
AnnaBridge	156:ff21514d8981	882	__IO uint32_t CNFPTR; /!< Pointer to a data structure holding AES key and NONCE vector. /
AnnaBridge	156:ff21514d8981	883	__IO uint32_t INPTR; /!< Pointer to the input packet. /
AnnaBridge	156:ff21514d8981	884	__IO uint32_t OUTPTR; /!< Pointer to the output packet. /
AnnaBridge	156:ff21514d8981	885	__IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
AnnaBridge	156:ff21514d8981	886	during resolution. A minimum of 43 bytes must be reserved. */
AnnaBridge	156:ff21514d8981	887	__I uint32_t RESERVED5[697];
AnnaBridge	156:ff21514d8981	888	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	889	} NRF_CCM_Type;
AnnaBridge	156:ff21514d8981	890
AnnaBridge	156:ff21514d8981	891
AnnaBridge	156:ff21514d8981	892	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	893	/* ================ WDT ================ */
AnnaBridge	156:ff21514d8981	894	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	895
AnnaBridge	156:ff21514d8981	896
AnnaBridge	156:ff21514d8981	897	/**
AnnaBridge	156:ff21514d8981	898	* @brief Watchdog Timer. (WDT)
AnnaBridge	156:ff21514d8981	899	*/
AnnaBridge	156:ff21514d8981	900
AnnaBridge	156:ff21514d8981	901	typedef struct { /!< WDT Structure /
AnnaBridge	156:ff21514d8981	902	__O uint32_t TASKS_START; /!< Start the watchdog. /
AnnaBridge	156:ff21514d8981	903	__I uint32_t RESERVED0[63];
AnnaBridge	156:ff21514d8981	904	__IO uint32_t EVENTS_TIMEOUT; /!< Watchdog timeout. /
AnnaBridge	156:ff21514d8981	905	__I uint32_t RESERVED1[128];
AnnaBridge	156:ff21514d8981	906	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	907	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	908	__I uint32_t RESERVED2[61];
AnnaBridge	156:ff21514d8981	909	__I uint32_t RUNSTATUS; /!< Watchdog running status. /
AnnaBridge	156:ff21514d8981	910	__I uint32_t REQSTATUS; /!< Request status. /
AnnaBridge	156:ff21514d8981	911	__I uint32_t RESERVED3[63];
AnnaBridge	156:ff21514d8981	912	__IO uint32_t CRV; /!< Counter reload value in number of 32kiHz clock cycles. /
AnnaBridge	156:ff21514d8981	913	__IO uint32_t RREN; /!< Reload request enable. /
AnnaBridge	156:ff21514d8981	914	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	156:ff21514d8981	915	__I uint32_t RESERVED4[60];
AnnaBridge	156:ff21514d8981	916	__O uint32_t RR[8]; /!< Reload requests registers. /
AnnaBridge	156:ff21514d8981	917	__I uint32_t RESERVED5[631];
AnnaBridge	156:ff21514d8981	918	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	919	} NRF_WDT_Type;
AnnaBridge	156:ff21514d8981	920
AnnaBridge	156:ff21514d8981	921
AnnaBridge	156:ff21514d8981	922	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	923	/* ================ QDEC ================ */
AnnaBridge	156:ff21514d8981	924	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	925
AnnaBridge	156:ff21514d8981	926
AnnaBridge	156:ff21514d8981	927	/**
AnnaBridge	156:ff21514d8981	928	* @brief Rotary decoder. (QDEC)
AnnaBridge	156:ff21514d8981	929	*/
AnnaBridge	156:ff21514d8981	930
AnnaBridge	156:ff21514d8981	931	typedef struct { /!< QDEC Structure /
AnnaBridge	156:ff21514d8981	932	__O uint32_t TASKS_START; /!< Start the quadrature decoder. /
AnnaBridge	156:ff21514d8981	933	__O uint32_t TASKS_STOP; /!< Stop the quadrature decoder. /
AnnaBridge	156:ff21514d8981	934	__O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
AnnaBridge	156:ff21514d8981	935	and clears the ACC registers. */
AnnaBridge	156:ff21514d8981	936	__I uint32_t RESERVED0[61];
AnnaBridge	156:ff21514d8981	937	__IO uint32_t EVENTS_SAMPLERDY; /!< A new sample is written to the sample register. /
AnnaBridge	156:ff21514d8981	938	__IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
AnnaBridge	156:ff21514d8981	939	ACC register different than zero. */
AnnaBridge	156:ff21514d8981	940	__IO uint32_t EVENTS_ACCOF; /!< ACC or ACCDBL register overflow. /
AnnaBridge	156:ff21514d8981	941	__I uint32_t RESERVED1[61];
AnnaBridge	156:ff21514d8981	942	__IO uint32_t SHORTS; /!< Shortcuts for the QDEC. /
AnnaBridge	156:ff21514d8981	943	__I uint32_t RESERVED2[64];
AnnaBridge	156:ff21514d8981	944	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	945	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	946	__I uint32_t RESERVED3[125];
AnnaBridge	156:ff21514d8981	947	__IO uint32_t ENABLE; /!< Enable the QDEC. /
AnnaBridge	156:ff21514d8981	948	__IO uint32_t LEDPOL; /!< LED output pin polarity. /
AnnaBridge	156:ff21514d8981	949	__IO uint32_t SAMPLEPER; /!< Sample period. /
AnnaBridge	156:ff21514d8981	950	__I int32_t SAMPLE; /!< Motion sample value. /
AnnaBridge	156:ff21514d8981	951	__IO uint32_t REPORTPER; /!< Number of samples to generate an EVENT_REPORTRDY. /
AnnaBridge	156:ff21514d8981	952	__I int32_t ACC; /!< Accumulated valid transitions register. /
AnnaBridge	156:ff21514d8981	953	__I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
AnnaBridge	156:ff21514d8981	954	task. */
AnnaBridge	156:ff21514d8981	955	__IO uint32_t PSELLED; /!< Pin select for LED output. /
AnnaBridge	156:ff21514d8981	956	__IO uint32_t PSELA; /!< Pin select for phase A input. /
AnnaBridge	156:ff21514d8981	957	__IO uint32_t PSELB; /!< Pin select for phase B input. /
AnnaBridge	156:ff21514d8981	958	__IO uint32_t DBFEN; /!< Enable debouncer input filters. /
AnnaBridge	156:ff21514d8981	959	__I uint32_t RESERVED4[5];
AnnaBridge	156:ff21514d8981	960	__IO uint32_t LEDPRE; /!< Time LED is switched ON before the sample. /
AnnaBridge	156:ff21514d8981	961	__I uint32_t ACCDBL; /!< Accumulated double (error) transitions register. /
AnnaBridge	156:ff21514d8981	962	__I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
AnnaBridge	156:ff21514d8981	963	task. */
AnnaBridge	156:ff21514d8981	964	__I uint32_t RESERVED5[684];
AnnaBridge	156:ff21514d8981	965	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	966	} NRF_QDEC_Type;
AnnaBridge	156:ff21514d8981	967
AnnaBridge	156:ff21514d8981	968
AnnaBridge	156:ff21514d8981	969	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	970	/* ================ LPCOMP ================ */
AnnaBridge	156:ff21514d8981	971	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	972
AnnaBridge	156:ff21514d8981	973
AnnaBridge	156:ff21514d8981	974	/**
AnnaBridge	156:ff21514d8981	975	* @brief Low power comparator. (LPCOMP)
AnnaBridge	156:ff21514d8981	976	*/
AnnaBridge	156:ff21514d8981	977
AnnaBridge	156:ff21514d8981	978	typedef struct { /!< LPCOMP Structure /
AnnaBridge	156:ff21514d8981	979	__O uint32_t TASKS_START; /!< Start the comparator. /
AnnaBridge	156:ff21514d8981	980	__O uint32_t TASKS_STOP; /!< Stop the comparator. /
AnnaBridge	156:ff21514d8981	981	__O uint32_t TASKS_SAMPLE; /!< Sample comparator value. /
AnnaBridge	156:ff21514d8981	982	__I uint32_t RESERVED0[61];
AnnaBridge	156:ff21514d8981	983	__IO uint32_t EVENTS_READY; /!< LPCOMP is ready and output is valid. /
AnnaBridge	156:ff21514d8981	984	__IO uint32_t EVENTS_DOWN; /!< Input voltage crossed the threshold going down. /
AnnaBridge	156:ff21514d8981	985	__IO uint32_t EVENTS_UP; /!< Input voltage crossed the threshold going up. /
AnnaBridge	156:ff21514d8981	986	__IO uint32_t EVENTS_CROSS; /!< Input voltage crossed the threshold in any direction. /
AnnaBridge	156:ff21514d8981	987	__I uint32_t RESERVED1[60];
AnnaBridge	156:ff21514d8981	988	__IO uint32_t SHORTS; /!< Shortcuts for the LPCOMP. /
AnnaBridge	156:ff21514d8981	989	__I uint32_t RESERVED2[64];
AnnaBridge	156:ff21514d8981	990	__IO uint32_t INTENSET; /!< Interrupt enable set register. /
AnnaBridge	156:ff21514d8981	991	__IO uint32_t INTENCLR; /!< Interrupt enable clear register. /
AnnaBridge	156:ff21514d8981	992	__I uint32_t RESERVED3[61];
AnnaBridge	156:ff21514d8981	993	__I uint32_t RESULT; /!< Result of last compare. /
AnnaBridge	156:ff21514d8981	994	__I uint32_t RESERVED4[63];
AnnaBridge	156:ff21514d8981	995	__IO uint32_t ENABLE; /!< Enable the LPCOMP. /
AnnaBridge	156:ff21514d8981	996	__IO uint32_t PSEL; /!< Input pin select. /
AnnaBridge	156:ff21514d8981	997	__IO uint32_t REFSEL; /!< Reference select. /
AnnaBridge	156:ff21514d8981	998	__IO uint32_t EXTREFSEL; /!< External reference select. /
AnnaBridge	156:ff21514d8981	999	__I uint32_t RESERVED5[4];
AnnaBridge	156:ff21514d8981	1000	__IO uint32_t ANADETECT; /!< Analog detect configuration. /
AnnaBridge	156:ff21514d8981	1001	__I uint32_t RESERVED6[694];
AnnaBridge	156:ff21514d8981	1002	__IO uint32_t POWER; /!< Peripheral power control. /
AnnaBridge	156:ff21514d8981	1003	} NRF_LPCOMP_Type;
AnnaBridge	156:ff21514d8981	1004
AnnaBridge	156:ff21514d8981	1005
AnnaBridge	156:ff21514d8981	1006	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1007	/* ================ SWI ================ */
AnnaBridge	156:ff21514d8981	1008	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1009
AnnaBridge	156:ff21514d8981	1010
AnnaBridge	156:ff21514d8981	1011	/**
AnnaBridge	156:ff21514d8981	1012	* @brief SW Interrupts. (SWI)
AnnaBridge	156:ff21514d8981	1013	*/
AnnaBridge	156:ff21514d8981	1014
AnnaBridge	156:ff21514d8981	1015	typedef struct { /!< SWI Structure /
AnnaBridge	156:ff21514d8981	1016	__I uint32_t UNUSED; /!< Unused. /
AnnaBridge	156:ff21514d8981	1017	} NRF_SWI_Type;
AnnaBridge	156:ff21514d8981	1018
AnnaBridge	156:ff21514d8981	1019
AnnaBridge	156:ff21514d8981	1020	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1021	/* ================ NVMC ================ */
AnnaBridge	156:ff21514d8981	1022	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1023
AnnaBridge	156:ff21514d8981	1024
AnnaBridge	156:ff21514d8981	1025	/**
AnnaBridge	156:ff21514d8981	1026	* @brief Non Volatile Memory Controller. (NVMC)
AnnaBridge	156:ff21514d8981	1027	*/
AnnaBridge	156:ff21514d8981	1028
AnnaBridge	156:ff21514d8981	1029	typedef struct { /!< NVMC Structure /
AnnaBridge	156:ff21514d8981	1030	__I uint32_t RESERVED0[256];
AnnaBridge	156:ff21514d8981	1031	__I uint32_t READY; /!< Ready flag. /
AnnaBridge	156:ff21514d8981	1032	__I uint32_t RESERVED1[64];
AnnaBridge	156:ff21514d8981	1033	__IO uint32_t CONFIG; /!< Configuration register. /
AnnaBridge	156:ff21514d8981	1034
AnnaBridge	156:ff21514d8981	1035	union {
AnnaBridge	156:ff21514d8981	1036	__IO uint32_t ERASEPCR1; /!< Register for erasing a non-protected non-volatile memory page. /
AnnaBridge	156:ff21514d8981	1037	__IO uint32_t ERASEPAGE; /!< Register for erasing a non-protected non-volatile memory page. /
AnnaBridge	156:ff21514d8981	1038	};
AnnaBridge	156:ff21514d8981	1039	__IO uint32_t ERASEALL; /!< Register for erasing all non-volatile user memory. /
AnnaBridge	156:ff21514d8981	1040	__IO uint32_t ERASEPCR0; /!< Register for erasing a protected non-volatile memory page. /
AnnaBridge	156:ff21514d8981	1041	__IO uint32_t ERASEUICR; /!< Register for start erasing User Information Congfiguration Registers. /
AnnaBridge	156:ff21514d8981	1042	} NRF_NVMC_Type;
AnnaBridge	156:ff21514d8981	1043
AnnaBridge	156:ff21514d8981	1044
AnnaBridge	156:ff21514d8981	1045	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1046	/* ================ PPI ================ */
AnnaBridge	156:ff21514d8981	1047	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1048
AnnaBridge	156:ff21514d8981	1049
AnnaBridge	156:ff21514d8981	1050	/**
AnnaBridge	156:ff21514d8981	1051	* @brief PPI controller. (PPI)
AnnaBridge	156:ff21514d8981	1052	*/
AnnaBridge	156:ff21514d8981	1053
AnnaBridge	156:ff21514d8981	1054	typedef struct { /!< PPI Structure /
AnnaBridge	156:ff21514d8981	1055	PPI_TASKS_CHG_Type TASKS_CHG[4]; /!< Channel group tasks. /
AnnaBridge	156:ff21514d8981	1056	__I uint32_t RESERVED0[312];
AnnaBridge	156:ff21514d8981	1057	__IO uint32_t CHEN; /!< Channel enable. /
AnnaBridge	156:ff21514d8981	1058	__IO uint32_t CHENSET; /!< Channel enable set. /
AnnaBridge	156:ff21514d8981	1059	__IO uint32_t CHENCLR; /!< Channel enable clear. /
AnnaBridge	156:ff21514d8981	1060	__I uint32_t RESERVED1;
AnnaBridge	156:ff21514d8981	1061	PPI_CH_Type CH[16]; /!< PPI Channel. /
AnnaBridge	156:ff21514d8981	1062	__I uint32_t RESERVED2[156];
AnnaBridge	156:ff21514d8981	1063	__IO uint32_t CHG[4]; /!< Channel group configuration. /
AnnaBridge	156:ff21514d8981	1064	} NRF_PPI_Type;
AnnaBridge	156:ff21514d8981	1065
AnnaBridge	156:ff21514d8981	1066
AnnaBridge	156:ff21514d8981	1067	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1068	/* ================ FICR ================ */
AnnaBridge	156:ff21514d8981	1069	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1070
AnnaBridge	156:ff21514d8981	1071
AnnaBridge	156:ff21514d8981	1072	/**
AnnaBridge	156:ff21514d8981	1073	* @brief Factory Information Configuration. (FICR)
AnnaBridge	156:ff21514d8981	1074	*/
AnnaBridge	156:ff21514d8981	1075
AnnaBridge	156:ff21514d8981	1076	typedef struct { /!< FICR Structure /
AnnaBridge	156:ff21514d8981	1077	__I uint32_t RESERVED0[4];
AnnaBridge	156:ff21514d8981	1078	__I uint32_t CODEPAGESIZE; /!< Code memory page size in bytes. /
AnnaBridge	156:ff21514d8981	1079	__I uint32_t CODESIZE; /!< Code memory size in pages. /
AnnaBridge	156:ff21514d8981	1080	__I uint32_t RESERVED1[4];
AnnaBridge	156:ff21514d8981	1081	__I uint32_t CLENR0; /!< Length of code region 0 in bytes. /
AnnaBridge	156:ff21514d8981	1082	__I uint32_t PPFC; /!< Pre-programmed factory code present. /
AnnaBridge	156:ff21514d8981	1083	__I uint32_t RESERVED2;
AnnaBridge	156:ff21514d8981	1084	__I uint32_t NUMRAMBLOCK; /!< Number of individualy controllable RAM blocks. /
AnnaBridge	156:ff21514d8981	1085
AnnaBridge	156:ff21514d8981	1086	union {
AnnaBridge	156:ff21514d8981	1087	__I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
AnnaBridge	156:ff21514d8981	1088	kept for backward compatinility purposes. Use SIZERAMBLOCKS
AnnaBridge	156:ff21514d8981	1089	instead. */
AnnaBridge	156:ff21514d8981	1090	__I uint32_t SIZERAMBLOCKS; /!< Size of RAM blocks in bytes. /
AnnaBridge	156:ff21514d8981	1091	};
AnnaBridge	156:ff21514d8981	1092	__I uint32_t RESERVED3[5];
AnnaBridge	156:ff21514d8981	1093	__I uint32_t CONFIGID; /!< Configuration identifier. /
AnnaBridge	156:ff21514d8981	1094	__I uint32_t DEVICEID[2]; /!< Device identifier. /
AnnaBridge	156:ff21514d8981	1095	__I uint32_t RESERVED4[6];
AnnaBridge	156:ff21514d8981	1096	__I uint32_t ER[4]; /!< Encryption root. /
AnnaBridge	156:ff21514d8981	1097	__I uint32_t IR[4]; /!< Identity root. /
AnnaBridge	156:ff21514d8981	1098	__I uint32_t DEVICEADDRTYPE; /!< Device address type. /
AnnaBridge	156:ff21514d8981	1099	__I uint32_t DEVICEADDR[2]; /!< Device address. /
AnnaBridge	156:ff21514d8981	1100	__I uint32_t OVERRIDEEN; /!< Radio calibration override enable. /
AnnaBridge	156:ff21514d8981	1101	__I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
AnnaBridge	156:ff21514d8981	1102	mode. */
AnnaBridge	156:ff21514d8981	1103	__I uint32_t RESERVED5[10];
AnnaBridge	156:ff21514d8981	1104	__I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
AnnaBridge	156:ff21514d8981	1105	mode. */
AnnaBridge	156:ff21514d8981	1106	} NRF_FICR_Type;
AnnaBridge	156:ff21514d8981	1107
AnnaBridge	156:ff21514d8981	1108
AnnaBridge	156:ff21514d8981	1109	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1110	/* ================ UICR ================ */
AnnaBridge	156:ff21514d8981	1111	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1112
AnnaBridge	156:ff21514d8981	1113
AnnaBridge	156:ff21514d8981	1114	/**
AnnaBridge	156:ff21514d8981	1115	* @brief User Information Configuration. (UICR)
AnnaBridge	156:ff21514d8981	1116	*/
AnnaBridge	156:ff21514d8981	1117
AnnaBridge	156:ff21514d8981	1118	typedef struct { /!< UICR Structure /
AnnaBridge	156:ff21514d8981	1119	__IO uint32_t CLENR0; /!< Length of code region 0. /
AnnaBridge	156:ff21514d8981	1120	__IO uint32_t RBPCONF; /!< Readback protection configuration. /
AnnaBridge	156:ff21514d8981	1121	__IO uint32_t XTALFREQ; /!< Reset value for CLOCK XTALFREQ register. /
AnnaBridge	156:ff21514d8981	1122	__I uint32_t RESERVED0;
AnnaBridge	156:ff21514d8981	1123	__I uint32_t FWID; /!< Firmware ID. /
AnnaBridge	156:ff21514d8981	1124
AnnaBridge	156:ff21514d8981	1125	union {
AnnaBridge	156:ff21514d8981	1126	__IO uint32_t NRFFW[15]; /!< Reserved for Nordic firmware design. /
AnnaBridge	156:ff21514d8981	1127	__IO uint32_t BOOTLOADERADDR; /!< Bootloader start address. /
AnnaBridge	156:ff21514d8981	1128	};
AnnaBridge	156:ff21514d8981	1129	__IO uint32_t NRFHW[12]; /!< Reserved for Nordic hardware design. /
AnnaBridge	156:ff21514d8981	1130	__IO uint32_t CUSTOMER[32]; /!< Reserved for customer. /
AnnaBridge	156:ff21514d8981	1131	} NRF_UICR_Type;
AnnaBridge	156:ff21514d8981	1132
AnnaBridge	156:ff21514d8981	1133
AnnaBridge	156:ff21514d8981	1134	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1135	/* ================ GPIO ================ */
AnnaBridge	156:ff21514d8981	1136	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1137
AnnaBridge	156:ff21514d8981	1138
AnnaBridge	156:ff21514d8981	1139	/**
AnnaBridge	156:ff21514d8981	1140	* @brief General purpose input and output. (GPIO)
AnnaBridge	156:ff21514d8981	1141	*/
AnnaBridge	156:ff21514d8981	1142
AnnaBridge	156:ff21514d8981	1143	typedef struct { /!< GPIO Structure /
AnnaBridge	156:ff21514d8981	1144	__I uint32_t RESERVED0[321];
AnnaBridge	156:ff21514d8981	1145	__IO uint32_t OUT; /!< Write GPIO port. /
AnnaBridge	156:ff21514d8981	1146	__IO uint32_t OUTSET; /!< Set individual bits in GPIO port. /
AnnaBridge	156:ff21514d8981	1147	__IO uint32_t OUTCLR; /!< Clear individual bits in GPIO port. /
AnnaBridge	156:ff21514d8981	1148	__I uint32_t IN; /!< Read GPIO port. /
AnnaBridge	156:ff21514d8981	1149	__IO uint32_t DIR; /!< Direction of GPIO pins. /
AnnaBridge	156:ff21514d8981	1150	__IO uint32_t DIRSET; /!< DIR set register. /
AnnaBridge	156:ff21514d8981	1151	__IO uint32_t DIRCLR; /!< DIR clear register. /
AnnaBridge	156:ff21514d8981	1152	__I uint32_t RESERVED1[120];
AnnaBridge	156:ff21514d8981	1153	__IO uint32_t PIN_CNF[32]; /!< Configuration of GPIO pins. /
AnnaBridge	156:ff21514d8981	1154	} NRF_GPIO_Type;
AnnaBridge	156:ff21514d8981	1155
AnnaBridge	156:ff21514d8981	1156
AnnaBridge	156:ff21514d8981	1157	/* -------------------- End of section using anonymous unions ------------------- */
AnnaBridge	156:ff21514d8981	1158	#if defined(__CC_ARM)
AnnaBridge	156:ff21514d8981	1159	#pragma pop
AnnaBridge	156:ff21514d8981	1160	#elif defined(__ICCARM__)
AnnaBridge	156:ff21514d8981	1161	/* leave anonymous unions enabled */
AnnaBridge	156:ff21514d8981	1162	#elif defined(__GNUC__)
AnnaBridge	156:ff21514d8981	1163	/* anonymous unions are enabled by default */
AnnaBridge	156:ff21514d8981	1164	#elif defined(__TMS470__)
AnnaBridge	156:ff21514d8981	1165	/* anonymous unions are enabled by default */
AnnaBridge	156:ff21514d8981	1166	#elif defined(__TASKING__)
AnnaBridge	156:ff21514d8981	1167	#pragma warning restore
AnnaBridge	156:ff21514d8981	1168	#else
AnnaBridge	156:ff21514d8981	1169	#warning Not supported compiler type
AnnaBridge	156:ff21514d8981	1170	#endif
AnnaBridge	156:ff21514d8981	1171
AnnaBridge	156:ff21514d8981	1172
AnnaBridge	156:ff21514d8981	1173
AnnaBridge	156:ff21514d8981	1174
AnnaBridge	156:ff21514d8981	1175	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1176	/* ================ Peripheral memory map ================ */
AnnaBridge	156:ff21514d8981	1177	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1178
AnnaBridge	156:ff21514d8981	1179	#define NRF_POWER_BASE 0x40000000UL
AnnaBridge	156:ff21514d8981	1180	#define NRF_CLOCK_BASE 0x40000000UL
AnnaBridge	156:ff21514d8981	1181	#define NRF_MPU_BASE 0x40000000UL
AnnaBridge	156:ff21514d8981	1182	#define NRF_AMLI_BASE 0x40000000UL
AnnaBridge	156:ff21514d8981	1183	#define NRF_RADIO_BASE 0x40001000UL
AnnaBridge	156:ff21514d8981	1184	#define NRF_UART0_BASE 0x40002000UL
AnnaBridge	156:ff21514d8981	1185	#define NRF_SPI0_BASE 0x40003000UL
AnnaBridge	156:ff21514d8981	1186	#define NRF_TWI0_BASE 0x40003000UL
AnnaBridge	156:ff21514d8981	1187	#define NRF_SPI1_BASE 0x40004000UL
AnnaBridge	156:ff21514d8981	1188	#define NRF_TWI1_BASE 0x40004000UL
AnnaBridge	156:ff21514d8981	1189	#define NRF_SPIS1_BASE 0x40004000UL
AnnaBridge	156:ff21514d8981	1190	#define NRF_SPIM1_BASE 0x40004000UL
AnnaBridge	156:ff21514d8981	1191	#define NRF_GPIOTE_BASE 0x40006000UL
AnnaBridge	156:ff21514d8981	1192	#define NRF_ADC_BASE 0x40007000UL
AnnaBridge	156:ff21514d8981	1193	#define NRF_TIMER0_BASE 0x40008000UL
AnnaBridge	156:ff21514d8981	1194	#define NRF_TIMER1_BASE 0x40009000UL
AnnaBridge	156:ff21514d8981	1195	#define NRF_TIMER2_BASE 0x4000A000UL
AnnaBridge	156:ff21514d8981	1196	#define NRF_RTC0_BASE 0x4000B000UL
AnnaBridge	156:ff21514d8981	1197	#define NRF_TEMP_BASE 0x4000C000UL
AnnaBridge	156:ff21514d8981	1198	#define NRF_RNG_BASE 0x4000D000UL
AnnaBridge	156:ff21514d8981	1199	#define NRF_ECB_BASE 0x4000E000UL
AnnaBridge	156:ff21514d8981	1200	#define NRF_AAR_BASE 0x4000F000UL
AnnaBridge	156:ff21514d8981	1201	#define NRF_CCM_BASE 0x4000F000UL
AnnaBridge	156:ff21514d8981	1202	#define NRF_WDT_BASE 0x40010000UL
AnnaBridge	156:ff21514d8981	1203	#define NRF_RTC1_BASE 0x40011000UL
AnnaBridge	156:ff21514d8981	1204	#define NRF_QDEC_BASE 0x40012000UL
AnnaBridge	156:ff21514d8981	1205	#define NRF_LPCOMP_BASE 0x40013000UL
AnnaBridge	156:ff21514d8981	1206	#define NRF_SWI_BASE 0x40014000UL
AnnaBridge	156:ff21514d8981	1207	#define NRF_NVMC_BASE 0x4001E000UL
AnnaBridge	156:ff21514d8981	1208	#define NRF_PPI_BASE 0x4001F000UL
AnnaBridge	156:ff21514d8981	1209	#define NRF_FICR_BASE 0x10000000UL
AnnaBridge	156:ff21514d8981	1210	#define NRF_UICR_BASE 0x10001000UL
AnnaBridge	156:ff21514d8981	1211	#define NRF_GPIO_BASE 0x50000000UL
AnnaBridge	156:ff21514d8981	1212
AnnaBridge	156:ff21514d8981	1213
AnnaBridge	156:ff21514d8981	1214	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1215	/* ================ Peripheral declaration ================ */
AnnaBridge	156:ff21514d8981	1216	/* ================================================================================ */
AnnaBridge	156:ff21514d8981	1217
AnnaBridge	156:ff21514d8981	1218	#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
AnnaBridge	156:ff21514d8981	1219	#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
AnnaBridge	156:ff21514d8981	1220	#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
AnnaBridge	156:ff21514d8981	1221	#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
AnnaBridge	156:ff21514d8981	1222	#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
AnnaBridge	156:ff21514d8981	1223	#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
AnnaBridge	156:ff21514d8981	1224	#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
AnnaBridge	156:ff21514d8981	1225	#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
AnnaBridge	156:ff21514d8981	1226	#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
AnnaBridge	156:ff21514d8981	1227	#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
AnnaBridge	156:ff21514d8981	1228	#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
AnnaBridge	156:ff21514d8981	1229	#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
AnnaBridge	156:ff21514d8981	1230	#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
AnnaBridge	156:ff21514d8981	1231	#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
AnnaBridge	156:ff21514d8981	1232	#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
AnnaBridge	156:ff21514d8981	1233	#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
AnnaBridge	156:ff21514d8981	1234	#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
AnnaBridge	156:ff21514d8981	1235	#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
AnnaBridge	156:ff21514d8981	1236	#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
AnnaBridge	156:ff21514d8981	1237	#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
AnnaBridge	156:ff21514d8981	1238	#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
AnnaBridge	156:ff21514d8981	1239	#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
AnnaBridge	156:ff21514d8981	1240	#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
AnnaBridge	156:ff21514d8981	1241	#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
AnnaBridge	156:ff21514d8981	1242	#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
AnnaBridge	156:ff21514d8981	1243	#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
AnnaBridge	156:ff21514d8981	1244	#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
AnnaBridge	156:ff21514d8981	1245	#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
AnnaBridge	156:ff21514d8981	1246	#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
AnnaBridge	156:ff21514d8981	1247	#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
AnnaBridge	156:ff21514d8981	1248	#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
AnnaBridge	156:ff21514d8981	1249	#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
AnnaBridge	156:ff21514d8981	1250	#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
AnnaBridge	156:ff21514d8981	1251
AnnaBridge	156:ff21514d8981	1252
AnnaBridge	156:ff21514d8981	1253	/** @} / / End of group Device_Peripheral_Registers */
AnnaBridge	156:ff21514d8981	1254	/** @} / / End of group nrf51 */
AnnaBridge	156:ff21514d8981	1255	/** @} / / End of group Nordic Semiconductor */
AnnaBridge	156:ff21514d8981	1256
AnnaBridge	156:ff21514d8981	1257	#ifdef __cplusplus
AnnaBridge	156:ff21514d8981	1258	}
AnnaBridge	156:ff21514d8981	1259	#endif
AnnaBridge	156:ff21514d8981	1260
AnnaBridge	156:ff21514d8981	1261
AnnaBridge	156:ff21514d8981	1262	#endif /* nrf51_H */