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TARGET_LPC1769/cmsis_gcc.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
160:5571c4ff569f
Child:
169:a7c7b631e539
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 157:e7ca05fa8600 1 /**************************************************************************//**
AnnaBridge 157:e7ca05fa8600 2 * @file cmsis_gcc.h
AnnaBridge 157:e7ca05fa8600 3 * @brief CMSIS compiler GCC header file
AnnaBridge 157:e7ca05fa8600 4 * @version V5.0.2
AnnaBridge 157:e7ca05fa8600 5 * @date 13. February 2017
AnnaBridge 157:e7ca05fa8600 6 ******************************************************************************/
AnnaBridge 157:e7ca05fa8600 7 /*
AnnaBridge 157:e7ca05fa8600 8 * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
AnnaBridge 157:e7ca05fa8600 9 *
AnnaBridge 157:e7ca05fa8600 10 * SPDX-License-Identifier: Apache-2.0
AnnaBridge 157:e7ca05fa8600 11 *
AnnaBridge 157:e7ca05fa8600 12 * Licensed under the Apache License, Version 2.0 (the License); you may
AnnaBridge 157:e7ca05fa8600 13 * not use this file except in compliance with the License.
AnnaBridge 157:e7ca05fa8600 14 * You may obtain a copy of the License at
AnnaBridge 157:e7ca05fa8600 15 *
AnnaBridge 157:e7ca05fa8600 16 * www.apache.org/licenses/LICENSE-2.0
AnnaBridge 157:e7ca05fa8600 17 *
AnnaBridge 157:e7ca05fa8600 18 * Unless required by applicable law or agreed to in writing, software
AnnaBridge 157:e7ca05fa8600 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
AnnaBridge 157:e7ca05fa8600 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
AnnaBridge 157:e7ca05fa8600 21 * See the License for the specific language governing permissions and
AnnaBridge 157:e7ca05fa8600 22 * limitations under the License.
AnnaBridge 157:e7ca05fa8600 23 */
AnnaBridge 157:e7ca05fa8600 24
AnnaBridge 157:e7ca05fa8600 25 #ifndef __CMSIS_GCC_H
AnnaBridge 157:e7ca05fa8600 26 #define __CMSIS_GCC_H
AnnaBridge 157:e7ca05fa8600 27
AnnaBridge 157:e7ca05fa8600 28 /* ignore some GCC warnings */
AnnaBridge 157:e7ca05fa8600 29 #pragma GCC diagnostic push
AnnaBridge 157:e7ca05fa8600 30 #pragma GCC diagnostic ignored "-Wsign-conversion"
AnnaBridge 157:e7ca05fa8600 31 #pragma GCC diagnostic ignored "-Wconversion"
AnnaBridge 157:e7ca05fa8600 32 #pragma GCC diagnostic ignored "-Wunused-parameter"
AnnaBridge 157:e7ca05fa8600 33
Anna Bridge 160:5571c4ff569f 34 /* Fallback for __has_builtin */
Anna Bridge 160:5571c4ff569f 35 #ifndef __has_builtin
Anna Bridge 160:5571c4ff569f 36 #define __has_builtin(x) (0)
Anna Bridge 160:5571c4ff569f 37 #endif
Anna Bridge 160:5571c4ff569f 38
AnnaBridge 157:e7ca05fa8600 39 /* CMSIS compiler specific defines */
AnnaBridge 157:e7ca05fa8600 40 #ifndef __ASM
AnnaBridge 157:e7ca05fa8600 41 #define __ASM __asm
AnnaBridge 157:e7ca05fa8600 42 #endif
AnnaBridge 157:e7ca05fa8600 43 #ifndef __INLINE
AnnaBridge 157:e7ca05fa8600 44 #define __INLINE inline
AnnaBridge 157:e7ca05fa8600 45 #endif
AnnaBridge 157:e7ca05fa8600 46 #ifndef __STATIC_INLINE
AnnaBridge 157:e7ca05fa8600 47 #define __STATIC_INLINE static inline
AnnaBridge 157:e7ca05fa8600 48 #endif
AnnaBridge 157:e7ca05fa8600 49 #ifndef __NO_RETURN
AnnaBridge 157:e7ca05fa8600 50 #define __NO_RETURN __attribute__((noreturn))
AnnaBridge 157:e7ca05fa8600 51 #endif
AnnaBridge 157:e7ca05fa8600 52 #ifndef __USED
AnnaBridge 157:e7ca05fa8600 53 #define __USED __attribute__((used))
AnnaBridge 157:e7ca05fa8600 54 #endif
AnnaBridge 157:e7ca05fa8600 55 #ifndef __WEAK
AnnaBridge 157:e7ca05fa8600 56 #define __WEAK __attribute__((weak))
AnnaBridge 157:e7ca05fa8600 57 #endif
AnnaBridge 157:e7ca05fa8600 58 #ifndef __PACKED
AnnaBridge 157:e7ca05fa8600 59 #define __PACKED __attribute__((packed, aligned(1)))
AnnaBridge 157:e7ca05fa8600 60 #endif
AnnaBridge 157:e7ca05fa8600 61 #ifndef __PACKED_STRUCT
AnnaBridge 157:e7ca05fa8600 62 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
AnnaBridge 157:e7ca05fa8600 63 #endif
Anna Bridge 160:5571c4ff569f 64 #ifndef __PACKED_UNION
Anna Bridge 160:5571c4ff569f 65 #define __PACKED_UNION union __attribute__((packed, aligned(1)))
Anna Bridge 160:5571c4ff569f 66 #endif
AnnaBridge 157:e7ca05fa8600 67 #ifndef __UNALIGNED_UINT32 /* deprecated */
AnnaBridge 157:e7ca05fa8600 68 #pragma GCC diagnostic push
AnnaBridge 157:e7ca05fa8600 69 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 70 #pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge 157:e7ca05fa8600 71 struct __attribute__((packed)) T_UINT32 { uint32_t v; };
AnnaBridge 157:e7ca05fa8600 72 #pragma GCC diagnostic pop
AnnaBridge 157:e7ca05fa8600 73 #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
AnnaBridge 157:e7ca05fa8600 74 #endif
AnnaBridge 157:e7ca05fa8600 75 #ifndef __UNALIGNED_UINT16_WRITE
AnnaBridge 157:e7ca05fa8600 76 #pragma GCC diagnostic push
AnnaBridge 157:e7ca05fa8600 77 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 78 #pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge 157:e7ca05fa8600 79 __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
AnnaBridge 157:e7ca05fa8600 80 #pragma GCC diagnostic pop
AnnaBridge 157:e7ca05fa8600 81 #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 157:e7ca05fa8600 82 #endif
AnnaBridge 157:e7ca05fa8600 83 #ifndef __UNALIGNED_UINT16_READ
AnnaBridge 157:e7ca05fa8600 84 #pragma GCC diagnostic push
AnnaBridge 157:e7ca05fa8600 85 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 86 #pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge 157:e7ca05fa8600 87 __PACKED_STRUCT T_UINT16_READ { uint16_t v; };
AnnaBridge 157:e7ca05fa8600 88 #pragma GCC diagnostic pop
AnnaBridge 157:e7ca05fa8600 89 #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
AnnaBridge 157:e7ca05fa8600 90 #endif
AnnaBridge 157:e7ca05fa8600 91 #ifndef __UNALIGNED_UINT32_WRITE
AnnaBridge 157:e7ca05fa8600 92 #pragma GCC diagnostic push
AnnaBridge 157:e7ca05fa8600 93 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 94 #pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge 157:e7ca05fa8600 95 __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
AnnaBridge 157:e7ca05fa8600 96 #pragma GCC diagnostic pop
AnnaBridge 157:e7ca05fa8600 97 #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
AnnaBridge 157:e7ca05fa8600 98 #endif
AnnaBridge 157:e7ca05fa8600 99 #ifndef __UNALIGNED_UINT32_READ
AnnaBridge 157:e7ca05fa8600 100 #pragma GCC diagnostic push
AnnaBridge 157:e7ca05fa8600 101 #pragma GCC diagnostic ignored "-Wpacked"
AnnaBridge 157:e7ca05fa8600 102 #pragma GCC diagnostic ignored "-Wattributes"
AnnaBridge 157:e7ca05fa8600 103 __PACKED_STRUCT T_UINT32_READ { uint32_t v; };
AnnaBridge 157:e7ca05fa8600 104 #pragma GCC diagnostic pop
AnnaBridge 157:e7ca05fa8600 105 #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
AnnaBridge 157:e7ca05fa8600 106 #endif
AnnaBridge 157:e7ca05fa8600 107 #ifndef __ALIGNED
AnnaBridge 157:e7ca05fa8600 108 #define __ALIGNED(x) __attribute__((aligned(x)))
AnnaBridge 157:e7ca05fa8600 109 #endif
Anna Bridge 160:5571c4ff569f 110 #ifndef __RESTRICT
Anna Bridge 160:5571c4ff569f 111 #define __RESTRICT __restrict
Anna Bridge 160:5571c4ff569f 112 #endif
AnnaBridge 157:e7ca05fa8600 113
AnnaBridge 157:e7ca05fa8600 114
AnnaBridge 157:e7ca05fa8600 115 /* ########################### Core Function Access ########################### */
AnnaBridge 157:e7ca05fa8600 116 /** \ingroup CMSIS_Core_FunctionInterface
AnnaBridge 157:e7ca05fa8600 117 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
AnnaBridge 157:e7ca05fa8600 118 @{
AnnaBridge 157:e7ca05fa8600 119 */
AnnaBridge 157:e7ca05fa8600 120
AnnaBridge 157:e7ca05fa8600 121 /**
AnnaBridge 157:e7ca05fa8600 122 \brief Enable IRQ Interrupts
AnnaBridge 157:e7ca05fa8600 123 \details Enables IRQ interrupts by clearing the I-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 124 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 125 */
AnnaBridge 157:e7ca05fa8600 126 __attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
AnnaBridge 157:e7ca05fa8600 127 {
AnnaBridge 157:e7ca05fa8600 128 __ASM volatile ("cpsie i" : : : "memory");
AnnaBridge 157:e7ca05fa8600 129 }
AnnaBridge 157:e7ca05fa8600 130
AnnaBridge 157:e7ca05fa8600 131
AnnaBridge 157:e7ca05fa8600 132 /**
AnnaBridge 157:e7ca05fa8600 133 \brief Disable IRQ Interrupts
AnnaBridge 157:e7ca05fa8600 134 \details Disables IRQ interrupts by setting the I-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 135 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 136 */
AnnaBridge 157:e7ca05fa8600 137 __attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
AnnaBridge 157:e7ca05fa8600 138 {
AnnaBridge 157:e7ca05fa8600 139 __ASM volatile ("cpsid i" : : : "memory");
AnnaBridge 157:e7ca05fa8600 140 }
AnnaBridge 157:e7ca05fa8600 141
AnnaBridge 157:e7ca05fa8600 142
AnnaBridge 157:e7ca05fa8600 143 /**
AnnaBridge 157:e7ca05fa8600 144 \brief Get Control Register
AnnaBridge 157:e7ca05fa8600 145 \details Returns the content of the Control Register.
AnnaBridge 157:e7ca05fa8600 146 \return Control Register value
AnnaBridge 157:e7ca05fa8600 147 */
AnnaBridge 157:e7ca05fa8600 148 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_CONTROL(void)
AnnaBridge 157:e7ca05fa8600 149 {
AnnaBridge 157:e7ca05fa8600 150 uint32_t result;
AnnaBridge 157:e7ca05fa8600 151
AnnaBridge 157:e7ca05fa8600 152 __ASM volatile ("MRS %0, control" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 153 return(result);
AnnaBridge 157:e7ca05fa8600 154 }
AnnaBridge 157:e7ca05fa8600 155
AnnaBridge 157:e7ca05fa8600 156
AnnaBridge 157:e7ca05fa8600 157 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 158 /**
AnnaBridge 157:e7ca05fa8600 159 \brief Get Control Register (non-secure)
AnnaBridge 157:e7ca05fa8600 160 \details Returns the content of the non-secure Control Register when in secure mode.
AnnaBridge 157:e7ca05fa8600 161 \return non-secure Control Register value
AnnaBridge 157:e7ca05fa8600 162 */
AnnaBridge 157:e7ca05fa8600 163 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_CONTROL_NS(void)
AnnaBridge 157:e7ca05fa8600 164 {
AnnaBridge 157:e7ca05fa8600 165 uint32_t result;
AnnaBridge 157:e7ca05fa8600 166
AnnaBridge 157:e7ca05fa8600 167 __ASM volatile ("MRS %0, control_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 168 return(result);
AnnaBridge 157:e7ca05fa8600 169 }
AnnaBridge 157:e7ca05fa8600 170 #endif
AnnaBridge 157:e7ca05fa8600 171
AnnaBridge 157:e7ca05fa8600 172
AnnaBridge 157:e7ca05fa8600 173 /**
AnnaBridge 157:e7ca05fa8600 174 \brief Set Control Register
AnnaBridge 157:e7ca05fa8600 175 \details Writes the given value to the Control Register.
AnnaBridge 157:e7ca05fa8600 176 \param [in] control Control Register value to set
AnnaBridge 157:e7ca05fa8600 177 */
AnnaBridge 157:e7ca05fa8600 178 __attribute__((always_inline)) __STATIC_INLINE void __set_CONTROL(uint32_t control)
AnnaBridge 157:e7ca05fa8600 179 {
AnnaBridge 157:e7ca05fa8600 180 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
AnnaBridge 157:e7ca05fa8600 181 }
AnnaBridge 157:e7ca05fa8600 182
AnnaBridge 157:e7ca05fa8600 183
AnnaBridge 157:e7ca05fa8600 184 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 185 /**
AnnaBridge 157:e7ca05fa8600 186 \brief Set Control Register (non-secure)
AnnaBridge 157:e7ca05fa8600 187 \details Writes the given value to the non-secure Control Register when in secure state.
AnnaBridge 157:e7ca05fa8600 188 \param [in] control Control Register value to set
AnnaBridge 157:e7ca05fa8600 189 */
AnnaBridge 157:e7ca05fa8600 190 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_CONTROL_NS(uint32_t control)
AnnaBridge 157:e7ca05fa8600 191 {
AnnaBridge 157:e7ca05fa8600 192 __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory");
AnnaBridge 157:e7ca05fa8600 193 }
AnnaBridge 157:e7ca05fa8600 194 #endif
AnnaBridge 157:e7ca05fa8600 195
AnnaBridge 157:e7ca05fa8600 196
AnnaBridge 157:e7ca05fa8600 197 /**
AnnaBridge 157:e7ca05fa8600 198 \brief Get IPSR Register
AnnaBridge 157:e7ca05fa8600 199 \details Returns the content of the IPSR Register.
AnnaBridge 157:e7ca05fa8600 200 \return IPSR Register value
AnnaBridge 157:e7ca05fa8600 201 */
AnnaBridge 157:e7ca05fa8600 202 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_IPSR(void)
AnnaBridge 157:e7ca05fa8600 203 {
AnnaBridge 157:e7ca05fa8600 204 uint32_t result;
AnnaBridge 157:e7ca05fa8600 205
AnnaBridge 157:e7ca05fa8600 206 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 207 return(result);
AnnaBridge 157:e7ca05fa8600 208 }
AnnaBridge 157:e7ca05fa8600 209
AnnaBridge 157:e7ca05fa8600 210
AnnaBridge 157:e7ca05fa8600 211 /**
AnnaBridge 157:e7ca05fa8600 212 \brief Get APSR Register
AnnaBridge 157:e7ca05fa8600 213 \details Returns the content of the APSR Register.
AnnaBridge 157:e7ca05fa8600 214 \return APSR Register value
AnnaBridge 157:e7ca05fa8600 215 */
AnnaBridge 157:e7ca05fa8600 216 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_APSR(void)
AnnaBridge 157:e7ca05fa8600 217 {
AnnaBridge 157:e7ca05fa8600 218 uint32_t result;
AnnaBridge 157:e7ca05fa8600 219
AnnaBridge 157:e7ca05fa8600 220 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 221 return(result);
AnnaBridge 157:e7ca05fa8600 222 }
AnnaBridge 157:e7ca05fa8600 223
AnnaBridge 157:e7ca05fa8600 224
AnnaBridge 157:e7ca05fa8600 225 /**
AnnaBridge 157:e7ca05fa8600 226 \brief Get xPSR Register
AnnaBridge 157:e7ca05fa8600 227 \details Returns the content of the xPSR Register.
AnnaBridge 157:e7ca05fa8600 228 \return xPSR Register value
AnnaBridge 157:e7ca05fa8600 229 */
AnnaBridge 157:e7ca05fa8600 230 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_xPSR(void)
AnnaBridge 157:e7ca05fa8600 231 {
AnnaBridge 157:e7ca05fa8600 232 uint32_t result;
AnnaBridge 157:e7ca05fa8600 233
AnnaBridge 157:e7ca05fa8600 234 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 235 return(result);
AnnaBridge 157:e7ca05fa8600 236 }
AnnaBridge 157:e7ca05fa8600 237
AnnaBridge 157:e7ca05fa8600 238
AnnaBridge 157:e7ca05fa8600 239 /**
AnnaBridge 157:e7ca05fa8600 240 \brief Get Process Stack Pointer
AnnaBridge 157:e7ca05fa8600 241 \details Returns the current value of the Process Stack Pointer (PSP).
AnnaBridge 157:e7ca05fa8600 242 \return PSP Register value
AnnaBridge 157:e7ca05fa8600 243 */
AnnaBridge 157:e7ca05fa8600 244 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSP(void)
AnnaBridge 157:e7ca05fa8600 245 {
AnnaBridge 157:e7ca05fa8600 246 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 247
AnnaBridge 157:e7ca05fa8600 248 __ASM volatile ("MRS %0, psp" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 249 return(result);
AnnaBridge 157:e7ca05fa8600 250 }
AnnaBridge 157:e7ca05fa8600 251
AnnaBridge 157:e7ca05fa8600 252
AnnaBridge 157:e7ca05fa8600 253 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 254 /**
AnnaBridge 157:e7ca05fa8600 255 \brief Get Process Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 256 \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 257 \return PSP Register value
AnnaBridge 157:e7ca05fa8600 258 */
AnnaBridge 157:e7ca05fa8600 259 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSP_NS(void)
AnnaBridge 157:e7ca05fa8600 260 {
AnnaBridge 157:e7ca05fa8600 261 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 262
AnnaBridge 157:e7ca05fa8600 263 __ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 264 return(result);
AnnaBridge 157:e7ca05fa8600 265 }
AnnaBridge 157:e7ca05fa8600 266 #endif
AnnaBridge 157:e7ca05fa8600 267
AnnaBridge 157:e7ca05fa8600 268
AnnaBridge 157:e7ca05fa8600 269 /**
AnnaBridge 157:e7ca05fa8600 270 \brief Set Process Stack Pointer
AnnaBridge 157:e7ca05fa8600 271 \details Assigns the given value to the Process Stack Pointer (PSP).
AnnaBridge 157:e7ca05fa8600 272 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 273 */
AnnaBridge 157:e7ca05fa8600 274 __attribute__((always_inline)) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
AnnaBridge 157:e7ca05fa8600 275 {
AnnaBridge 157:e7ca05fa8600 276 __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : );
AnnaBridge 157:e7ca05fa8600 277 }
AnnaBridge 157:e7ca05fa8600 278
AnnaBridge 157:e7ca05fa8600 279
AnnaBridge 157:e7ca05fa8600 280 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 281 /**
AnnaBridge 157:e7ca05fa8600 282 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 283 \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 284 \param [in] topOfProcStack Process Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 285 */
AnnaBridge 157:e7ca05fa8600 286 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
AnnaBridge 157:e7ca05fa8600 287 {
AnnaBridge 157:e7ca05fa8600 288 __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : );
AnnaBridge 157:e7ca05fa8600 289 }
AnnaBridge 157:e7ca05fa8600 290 #endif
AnnaBridge 157:e7ca05fa8600 291
AnnaBridge 157:e7ca05fa8600 292
AnnaBridge 157:e7ca05fa8600 293 /**
AnnaBridge 157:e7ca05fa8600 294 \brief Get Main Stack Pointer
AnnaBridge 157:e7ca05fa8600 295 \details Returns the current value of the Main Stack Pointer (MSP).
AnnaBridge 157:e7ca05fa8600 296 \return MSP Register value
AnnaBridge 157:e7ca05fa8600 297 */
AnnaBridge 157:e7ca05fa8600 298 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSP(void)
AnnaBridge 157:e7ca05fa8600 299 {
AnnaBridge 157:e7ca05fa8600 300 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 301
AnnaBridge 157:e7ca05fa8600 302 __ASM volatile ("MRS %0, msp" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 303 return(result);
AnnaBridge 157:e7ca05fa8600 304 }
AnnaBridge 157:e7ca05fa8600 305
AnnaBridge 157:e7ca05fa8600 306
AnnaBridge 157:e7ca05fa8600 307 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 308 /**
AnnaBridge 157:e7ca05fa8600 309 \brief Get Main Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 310 \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 311 \return MSP Register value
AnnaBridge 157:e7ca05fa8600 312 */
AnnaBridge 157:e7ca05fa8600 313 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSP_NS(void)
AnnaBridge 157:e7ca05fa8600 314 {
AnnaBridge 157:e7ca05fa8600 315 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 316
AnnaBridge 157:e7ca05fa8600 317 __ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 318 return(result);
AnnaBridge 157:e7ca05fa8600 319 }
AnnaBridge 157:e7ca05fa8600 320 #endif
AnnaBridge 157:e7ca05fa8600 321
AnnaBridge 157:e7ca05fa8600 322
AnnaBridge 157:e7ca05fa8600 323 /**
AnnaBridge 157:e7ca05fa8600 324 \brief Set Main Stack Pointer
AnnaBridge 157:e7ca05fa8600 325 \details Assigns the given value to the Main Stack Pointer (MSP).
AnnaBridge 157:e7ca05fa8600 326 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 327 */
AnnaBridge 157:e7ca05fa8600 328 __attribute__((always_inline)) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
AnnaBridge 157:e7ca05fa8600 329 {
AnnaBridge 157:e7ca05fa8600 330 __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : );
AnnaBridge 157:e7ca05fa8600 331 }
AnnaBridge 157:e7ca05fa8600 332
AnnaBridge 157:e7ca05fa8600 333
AnnaBridge 157:e7ca05fa8600 334 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 335 /**
AnnaBridge 157:e7ca05fa8600 336 \brief Set Main Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 337 \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state.
AnnaBridge 157:e7ca05fa8600 338 \param [in] topOfMainStack Main Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 339 */
AnnaBridge 157:e7ca05fa8600 340 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
AnnaBridge 157:e7ca05fa8600 341 {
AnnaBridge 157:e7ca05fa8600 342 __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : );
AnnaBridge 157:e7ca05fa8600 343 }
AnnaBridge 157:e7ca05fa8600 344 #endif
AnnaBridge 157:e7ca05fa8600 345
AnnaBridge 157:e7ca05fa8600 346
AnnaBridge 157:e7ca05fa8600 347 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 348 /**
AnnaBridge 157:e7ca05fa8600 349 \brief Get Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 350 \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 157:e7ca05fa8600 351 \return SP Register value
AnnaBridge 157:e7ca05fa8600 352 */
AnnaBridge 157:e7ca05fa8600 353 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_SP_NS(void)
AnnaBridge 157:e7ca05fa8600 354 {
AnnaBridge 157:e7ca05fa8600 355 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 356
AnnaBridge 157:e7ca05fa8600 357 __ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 358 return(result);
AnnaBridge 157:e7ca05fa8600 359 }
AnnaBridge 157:e7ca05fa8600 360
AnnaBridge 157:e7ca05fa8600 361
AnnaBridge 157:e7ca05fa8600 362 /**
AnnaBridge 157:e7ca05fa8600 363 \brief Set Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 364 \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state.
AnnaBridge 157:e7ca05fa8600 365 \param [in] topOfStack Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 366 */
AnnaBridge 157:e7ca05fa8600 367 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_SP_NS(uint32_t topOfStack)
AnnaBridge 157:e7ca05fa8600 368 {
AnnaBridge 157:e7ca05fa8600 369 __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : );
AnnaBridge 157:e7ca05fa8600 370 }
AnnaBridge 157:e7ca05fa8600 371 #endif
AnnaBridge 157:e7ca05fa8600 372
AnnaBridge 157:e7ca05fa8600 373
AnnaBridge 157:e7ca05fa8600 374 /**
AnnaBridge 157:e7ca05fa8600 375 \brief Get Priority Mask
AnnaBridge 157:e7ca05fa8600 376 \details Returns the current state of the priority mask bit from the Priority Mask Register.
AnnaBridge 157:e7ca05fa8600 377 \return Priority Mask value
AnnaBridge 157:e7ca05fa8600 378 */
AnnaBridge 157:e7ca05fa8600 379 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PRIMASK(void)
AnnaBridge 157:e7ca05fa8600 380 {
AnnaBridge 157:e7ca05fa8600 381 uint32_t result;
AnnaBridge 157:e7ca05fa8600 382
AnnaBridge 157:e7ca05fa8600 383 __ASM volatile ("MRS %0, primask" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 384 return(result);
AnnaBridge 157:e7ca05fa8600 385 }
AnnaBridge 157:e7ca05fa8600 386
AnnaBridge 157:e7ca05fa8600 387
AnnaBridge 157:e7ca05fa8600 388 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 389 /**
AnnaBridge 157:e7ca05fa8600 390 \brief Get Priority Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 391 \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state.
AnnaBridge 157:e7ca05fa8600 392 \return Priority Mask value
AnnaBridge 157:e7ca05fa8600 393 */
AnnaBridge 157:e7ca05fa8600 394 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PRIMASK_NS(void)
AnnaBridge 157:e7ca05fa8600 395 {
AnnaBridge 157:e7ca05fa8600 396 uint32_t result;
AnnaBridge 157:e7ca05fa8600 397
AnnaBridge 157:e7ca05fa8600 398 __ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 399 return(result);
AnnaBridge 157:e7ca05fa8600 400 }
AnnaBridge 157:e7ca05fa8600 401 #endif
AnnaBridge 157:e7ca05fa8600 402
AnnaBridge 157:e7ca05fa8600 403
AnnaBridge 157:e7ca05fa8600 404 /**
AnnaBridge 157:e7ca05fa8600 405 \brief Set Priority Mask
AnnaBridge 157:e7ca05fa8600 406 \details Assigns the given value to the Priority Mask Register.
AnnaBridge 157:e7ca05fa8600 407 \param [in] priMask Priority Mask
AnnaBridge 157:e7ca05fa8600 408 */
AnnaBridge 157:e7ca05fa8600 409 __attribute__((always_inline)) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
AnnaBridge 157:e7ca05fa8600 410 {
AnnaBridge 157:e7ca05fa8600 411 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
AnnaBridge 157:e7ca05fa8600 412 }
AnnaBridge 157:e7ca05fa8600 413
AnnaBridge 157:e7ca05fa8600 414
AnnaBridge 157:e7ca05fa8600 415 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 416 /**
AnnaBridge 157:e7ca05fa8600 417 \brief Set Priority Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 418 \details Assigns the given value to the non-secure Priority Mask Register when in secure state.
AnnaBridge 157:e7ca05fa8600 419 \param [in] priMask Priority Mask
AnnaBridge 157:e7ca05fa8600 420 */
AnnaBridge 157:e7ca05fa8600 421 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PRIMASK_NS(uint32_t priMask)
AnnaBridge 157:e7ca05fa8600 422 {
AnnaBridge 157:e7ca05fa8600 423 __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory");
AnnaBridge 157:e7ca05fa8600 424 }
AnnaBridge 157:e7ca05fa8600 425 #endif
AnnaBridge 157:e7ca05fa8600 426
AnnaBridge 157:e7ca05fa8600 427
AnnaBridge 157:e7ca05fa8600 428 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 429 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 430 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 431 /**
AnnaBridge 157:e7ca05fa8600 432 \brief Enable FIQ
AnnaBridge 157:e7ca05fa8600 433 \details Enables FIQ interrupts by clearing the F-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 434 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 435 */
AnnaBridge 157:e7ca05fa8600 436 __attribute__((always_inline)) __STATIC_INLINE void __enable_fault_irq(void)
AnnaBridge 157:e7ca05fa8600 437 {
AnnaBridge 157:e7ca05fa8600 438 __ASM volatile ("cpsie f" : : : "memory");
AnnaBridge 157:e7ca05fa8600 439 }
AnnaBridge 157:e7ca05fa8600 440
AnnaBridge 157:e7ca05fa8600 441
AnnaBridge 157:e7ca05fa8600 442 /**
AnnaBridge 157:e7ca05fa8600 443 \brief Disable FIQ
AnnaBridge 157:e7ca05fa8600 444 \details Disables FIQ interrupts by setting the F-bit in the CPSR.
AnnaBridge 157:e7ca05fa8600 445 Can only be executed in Privileged modes.
AnnaBridge 157:e7ca05fa8600 446 */
AnnaBridge 157:e7ca05fa8600 447 __attribute__((always_inline)) __STATIC_INLINE void __disable_fault_irq(void)
AnnaBridge 157:e7ca05fa8600 448 {
AnnaBridge 157:e7ca05fa8600 449 __ASM volatile ("cpsid f" : : : "memory");
AnnaBridge 157:e7ca05fa8600 450 }
AnnaBridge 157:e7ca05fa8600 451
AnnaBridge 157:e7ca05fa8600 452
AnnaBridge 157:e7ca05fa8600 453 /**
AnnaBridge 157:e7ca05fa8600 454 \brief Get Base Priority
AnnaBridge 157:e7ca05fa8600 455 \details Returns the current value of the Base Priority register.
AnnaBridge 157:e7ca05fa8600 456 \return Base Priority register value
AnnaBridge 157:e7ca05fa8600 457 */
AnnaBridge 157:e7ca05fa8600 458 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_BASEPRI(void)
AnnaBridge 157:e7ca05fa8600 459 {
AnnaBridge 157:e7ca05fa8600 460 uint32_t result;
AnnaBridge 157:e7ca05fa8600 461
AnnaBridge 157:e7ca05fa8600 462 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 463 return(result);
AnnaBridge 157:e7ca05fa8600 464 }
AnnaBridge 157:e7ca05fa8600 465
AnnaBridge 157:e7ca05fa8600 466
AnnaBridge 157:e7ca05fa8600 467 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 468 /**
AnnaBridge 157:e7ca05fa8600 469 \brief Get Base Priority (non-secure)
AnnaBridge 157:e7ca05fa8600 470 \details Returns the current value of the non-secure Base Priority register when in secure state.
AnnaBridge 157:e7ca05fa8600 471 \return Base Priority register value
AnnaBridge 157:e7ca05fa8600 472 */
AnnaBridge 157:e7ca05fa8600 473 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_BASEPRI_NS(void)
AnnaBridge 157:e7ca05fa8600 474 {
AnnaBridge 157:e7ca05fa8600 475 uint32_t result;
AnnaBridge 157:e7ca05fa8600 476
AnnaBridge 157:e7ca05fa8600 477 __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 478 return(result);
AnnaBridge 157:e7ca05fa8600 479 }
AnnaBridge 157:e7ca05fa8600 480 #endif
AnnaBridge 157:e7ca05fa8600 481
AnnaBridge 157:e7ca05fa8600 482
AnnaBridge 157:e7ca05fa8600 483 /**
AnnaBridge 157:e7ca05fa8600 484 \brief Set Base Priority
AnnaBridge 157:e7ca05fa8600 485 \details Assigns the given value to the Base Priority register.
AnnaBridge 157:e7ca05fa8600 486 \param [in] basePri Base Priority value to set
AnnaBridge 157:e7ca05fa8600 487 */
AnnaBridge 157:e7ca05fa8600 488 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
AnnaBridge 157:e7ca05fa8600 489 {
AnnaBridge 157:e7ca05fa8600 490 __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory");
AnnaBridge 157:e7ca05fa8600 491 }
AnnaBridge 157:e7ca05fa8600 492
AnnaBridge 157:e7ca05fa8600 493
AnnaBridge 157:e7ca05fa8600 494 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 495 /**
AnnaBridge 157:e7ca05fa8600 496 \brief Set Base Priority (non-secure)
AnnaBridge 157:e7ca05fa8600 497 \details Assigns the given value to the non-secure Base Priority register when in secure state.
AnnaBridge 157:e7ca05fa8600 498 \param [in] basePri Base Priority value to set
AnnaBridge 157:e7ca05fa8600 499 */
AnnaBridge 157:e7ca05fa8600 500 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_BASEPRI_NS(uint32_t basePri)
AnnaBridge 157:e7ca05fa8600 501 {
AnnaBridge 157:e7ca05fa8600 502 __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory");
AnnaBridge 157:e7ca05fa8600 503 }
AnnaBridge 157:e7ca05fa8600 504 #endif
AnnaBridge 157:e7ca05fa8600 505
AnnaBridge 157:e7ca05fa8600 506
AnnaBridge 157:e7ca05fa8600 507 /**
AnnaBridge 157:e7ca05fa8600 508 \brief Set Base Priority with condition
AnnaBridge 157:e7ca05fa8600 509 \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
AnnaBridge 157:e7ca05fa8600 510 or the new value increases the BASEPRI priority level.
AnnaBridge 157:e7ca05fa8600 511 \param [in] basePri Base Priority value to set
AnnaBridge 157:e7ca05fa8600 512 */
AnnaBridge 157:e7ca05fa8600 513 __attribute__((always_inline)) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
AnnaBridge 157:e7ca05fa8600 514 {
AnnaBridge 157:e7ca05fa8600 515 __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory");
AnnaBridge 157:e7ca05fa8600 516 }
AnnaBridge 157:e7ca05fa8600 517
AnnaBridge 157:e7ca05fa8600 518
AnnaBridge 157:e7ca05fa8600 519 /**
AnnaBridge 157:e7ca05fa8600 520 \brief Get Fault Mask
AnnaBridge 157:e7ca05fa8600 521 \details Returns the current value of the Fault Mask register.
AnnaBridge 157:e7ca05fa8600 522 \return Fault Mask register value
AnnaBridge 157:e7ca05fa8600 523 */
AnnaBridge 157:e7ca05fa8600 524 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
AnnaBridge 157:e7ca05fa8600 525 {
AnnaBridge 157:e7ca05fa8600 526 uint32_t result;
AnnaBridge 157:e7ca05fa8600 527
AnnaBridge 157:e7ca05fa8600 528 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 529 return(result);
AnnaBridge 157:e7ca05fa8600 530 }
AnnaBridge 157:e7ca05fa8600 531
AnnaBridge 157:e7ca05fa8600 532
AnnaBridge 157:e7ca05fa8600 533 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 534 /**
AnnaBridge 157:e7ca05fa8600 535 \brief Get Fault Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 536 \details Returns the current value of the non-secure Fault Mask register when in secure state.
AnnaBridge 157:e7ca05fa8600 537 \return Fault Mask register value
AnnaBridge 157:e7ca05fa8600 538 */
AnnaBridge 157:e7ca05fa8600 539 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_FAULTMASK_NS(void)
AnnaBridge 157:e7ca05fa8600 540 {
AnnaBridge 157:e7ca05fa8600 541 uint32_t result;
AnnaBridge 157:e7ca05fa8600 542
AnnaBridge 157:e7ca05fa8600 543 __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 544 return(result);
AnnaBridge 157:e7ca05fa8600 545 }
AnnaBridge 157:e7ca05fa8600 546 #endif
AnnaBridge 157:e7ca05fa8600 547
AnnaBridge 157:e7ca05fa8600 548
AnnaBridge 157:e7ca05fa8600 549 /**
AnnaBridge 157:e7ca05fa8600 550 \brief Set Fault Mask
AnnaBridge 157:e7ca05fa8600 551 \details Assigns the given value to the Fault Mask register.
AnnaBridge 157:e7ca05fa8600 552 \param [in] faultMask Fault Mask value to set
AnnaBridge 157:e7ca05fa8600 553 */
AnnaBridge 157:e7ca05fa8600 554 __attribute__((always_inline)) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
AnnaBridge 157:e7ca05fa8600 555 {
AnnaBridge 157:e7ca05fa8600 556 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
AnnaBridge 157:e7ca05fa8600 557 }
AnnaBridge 157:e7ca05fa8600 558
AnnaBridge 157:e7ca05fa8600 559
AnnaBridge 157:e7ca05fa8600 560 #if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3))
AnnaBridge 157:e7ca05fa8600 561 /**
AnnaBridge 157:e7ca05fa8600 562 \brief Set Fault Mask (non-secure)
AnnaBridge 157:e7ca05fa8600 563 \details Assigns the given value to the non-secure Fault Mask register when in secure state.
AnnaBridge 157:e7ca05fa8600 564 \param [in] faultMask Fault Mask value to set
AnnaBridge 157:e7ca05fa8600 565 */
AnnaBridge 157:e7ca05fa8600 566 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask)
AnnaBridge 157:e7ca05fa8600 567 {
AnnaBridge 157:e7ca05fa8600 568 __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory");
AnnaBridge 157:e7ca05fa8600 569 }
AnnaBridge 157:e7ca05fa8600 570 #endif
AnnaBridge 157:e7ca05fa8600 571
AnnaBridge 157:e7ca05fa8600 572 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 573 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 574 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 575
AnnaBridge 157:e7ca05fa8600 576
AnnaBridge 157:e7ca05fa8600 577 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 578 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 157:e7ca05fa8600 579
AnnaBridge 157:e7ca05fa8600 580 /**
AnnaBridge 157:e7ca05fa8600 581 \brief Get Process Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 582 \details Returns the current value of the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 157:e7ca05fa8600 583 \return PSPLIM Register value
AnnaBridge 157:e7ca05fa8600 584 */
AnnaBridge 157:e7ca05fa8600 585 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_PSPLIM(void)
AnnaBridge 157:e7ca05fa8600 586 {
AnnaBridge 157:e7ca05fa8600 587 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 588
AnnaBridge 157:e7ca05fa8600 589 __ASM volatile ("MRS %0, psplim" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 590 return(result);
AnnaBridge 157:e7ca05fa8600 591 }
AnnaBridge 157:e7ca05fa8600 592
AnnaBridge 157:e7ca05fa8600 593
AnnaBridge 157:e7ca05fa8600 594 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 595 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 596 /**
AnnaBridge 157:e7ca05fa8600 597 \brief Get Process Stack Pointer Limit (non-secure)
AnnaBridge 157:e7ca05fa8600 598 \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 599 \return PSPLIM Register value
AnnaBridge 157:e7ca05fa8600 600 */
AnnaBridge 157:e7ca05fa8600 601 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_PSPLIM_NS(void)
AnnaBridge 157:e7ca05fa8600 602 {
AnnaBridge 157:e7ca05fa8600 603 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 604
AnnaBridge 157:e7ca05fa8600 605 __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 606 return(result);
AnnaBridge 157:e7ca05fa8600 607 }
AnnaBridge 157:e7ca05fa8600 608 #endif
AnnaBridge 157:e7ca05fa8600 609
AnnaBridge 157:e7ca05fa8600 610
AnnaBridge 157:e7ca05fa8600 611 /**
AnnaBridge 157:e7ca05fa8600 612 \brief Set Process Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 613 \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM).
AnnaBridge 157:e7ca05fa8600 614 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 157:e7ca05fa8600 615 */
AnnaBridge 157:e7ca05fa8600 616 __attribute__((always_inline)) __STATIC_INLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 617 {
AnnaBridge 157:e7ca05fa8600 618 __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 619 }
AnnaBridge 157:e7ca05fa8600 620
AnnaBridge 157:e7ca05fa8600 621
AnnaBridge 157:e7ca05fa8600 622 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 623 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 624 /**
AnnaBridge 157:e7ca05fa8600 625 \brief Set Process Stack Pointer (non-secure)
AnnaBridge 157:e7ca05fa8600 626 \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 627 \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set
AnnaBridge 157:e7ca05fa8600 628 */
AnnaBridge 157:e7ca05fa8600 629 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 630 {
AnnaBridge 157:e7ca05fa8600 631 __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 632 }
AnnaBridge 157:e7ca05fa8600 633 #endif
AnnaBridge 157:e7ca05fa8600 634
AnnaBridge 157:e7ca05fa8600 635
AnnaBridge 157:e7ca05fa8600 636 /**
AnnaBridge 157:e7ca05fa8600 637 \brief Get Main Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 638 \details Returns the current value of the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 157:e7ca05fa8600 639 \return MSPLIM Register value
AnnaBridge 157:e7ca05fa8600 640 */
AnnaBridge 157:e7ca05fa8600 641 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_MSPLIM(void)
AnnaBridge 157:e7ca05fa8600 642 {
AnnaBridge 157:e7ca05fa8600 643 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 644
AnnaBridge 157:e7ca05fa8600 645 __ASM volatile ("MRS %0, msplim" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 646
AnnaBridge 157:e7ca05fa8600 647 return(result);
AnnaBridge 157:e7ca05fa8600 648 }
AnnaBridge 157:e7ca05fa8600 649
AnnaBridge 157:e7ca05fa8600 650
AnnaBridge 157:e7ca05fa8600 651 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 652 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 653 /**
AnnaBridge 157:e7ca05fa8600 654 \brief Get Main Stack Pointer Limit (non-secure)
AnnaBridge 157:e7ca05fa8600 655 \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 656 \return MSPLIM Register value
AnnaBridge 157:e7ca05fa8600 657 */
AnnaBridge 157:e7ca05fa8600 658 __attribute__((always_inline)) __STATIC_INLINE uint32_t __TZ_get_MSPLIM_NS(void)
AnnaBridge 157:e7ca05fa8600 659 {
AnnaBridge 157:e7ca05fa8600 660 register uint32_t result;
AnnaBridge 157:e7ca05fa8600 661
AnnaBridge 157:e7ca05fa8600 662 __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 663 return(result);
AnnaBridge 157:e7ca05fa8600 664 }
AnnaBridge 157:e7ca05fa8600 665 #endif
AnnaBridge 157:e7ca05fa8600 666
AnnaBridge 157:e7ca05fa8600 667
AnnaBridge 157:e7ca05fa8600 668 /**
AnnaBridge 157:e7ca05fa8600 669 \brief Set Main Stack Pointer Limit
AnnaBridge 157:e7ca05fa8600 670 \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM).
AnnaBridge 157:e7ca05fa8600 671 \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set
AnnaBridge 157:e7ca05fa8600 672 */
AnnaBridge 157:e7ca05fa8600 673 __attribute__((always_inline)) __STATIC_INLINE void __set_MSPLIM(uint32_t MainStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 674 {
AnnaBridge 157:e7ca05fa8600 675 __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 676 }
AnnaBridge 157:e7ca05fa8600 677
AnnaBridge 157:e7ca05fa8600 678
AnnaBridge 157:e7ca05fa8600 679 #if ((defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) && \
AnnaBridge 157:e7ca05fa8600 680 (defined (__ARM_ARCH_8M_MAIN__) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 681 /**
AnnaBridge 157:e7ca05fa8600 682 \brief Set Main Stack Pointer Limit (non-secure)
AnnaBridge 157:e7ca05fa8600 683 \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state.
AnnaBridge 157:e7ca05fa8600 684 \param [in] MainStackPtrLimit Main Stack Pointer value to set
AnnaBridge 157:e7ca05fa8600 685 */
AnnaBridge 157:e7ca05fa8600 686 __attribute__((always_inline)) __STATIC_INLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
AnnaBridge 157:e7ca05fa8600 687 {
AnnaBridge 157:e7ca05fa8600 688 __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit));
AnnaBridge 157:e7ca05fa8600 689 }
AnnaBridge 157:e7ca05fa8600 690 #endif
AnnaBridge 157:e7ca05fa8600 691
AnnaBridge 157:e7ca05fa8600 692 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 693 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 694
AnnaBridge 157:e7ca05fa8600 695
AnnaBridge 157:e7ca05fa8600 696 #if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 697 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 698
AnnaBridge 157:e7ca05fa8600 699 /**
AnnaBridge 157:e7ca05fa8600 700 \brief Get FPSCR
AnnaBridge 157:e7ca05fa8600 701 \details Returns the current value of the Floating Point Status/Control register.
AnnaBridge 157:e7ca05fa8600 702 \return Floating Point Status/Control register value
AnnaBridge 157:e7ca05fa8600 703 */
AnnaBridge 157:e7ca05fa8600 704 __attribute__((always_inline)) __STATIC_INLINE uint32_t __get_FPSCR(void)
AnnaBridge 157:e7ca05fa8600 705 {
AnnaBridge 157:e7ca05fa8600 706 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 157:e7ca05fa8600 707 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
Anna Bridge 160:5571c4ff569f 708 #if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
Anna Bridge 160:5571c4ff569f 709 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
Anna Bridge 160:5571c4ff569f 710 return __builtin_arm_get_fpscr();
Anna Bridge 160:5571c4ff569f 711 #else
AnnaBridge 157:e7ca05fa8600 712 uint32_t result;
AnnaBridge 157:e7ca05fa8600 713
AnnaBridge 157:e7ca05fa8600 714 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
AnnaBridge 157:e7ca05fa8600 715 return(result);
Anna Bridge 160:5571c4ff569f 716 #endif
AnnaBridge 157:e7ca05fa8600 717 #else
Anna Bridge 160:5571c4ff569f 718 return(0U);
AnnaBridge 157:e7ca05fa8600 719 #endif
AnnaBridge 157:e7ca05fa8600 720 }
AnnaBridge 157:e7ca05fa8600 721
AnnaBridge 157:e7ca05fa8600 722
AnnaBridge 157:e7ca05fa8600 723 /**
AnnaBridge 157:e7ca05fa8600 724 \brief Set FPSCR
AnnaBridge 157:e7ca05fa8600 725 \details Assigns the given value to the Floating Point Status/Control register.
AnnaBridge 157:e7ca05fa8600 726 \param [in] fpscr Floating Point Status/Control value to set
AnnaBridge 157:e7ca05fa8600 727 */
AnnaBridge 157:e7ca05fa8600 728 __attribute__((always_inline)) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
AnnaBridge 157:e7ca05fa8600 729 {
AnnaBridge 157:e7ca05fa8600 730 #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
AnnaBridge 157:e7ca05fa8600 731 (defined (__FPU_USED ) && (__FPU_USED == 1U)) )
Anna Bridge 160:5571c4ff569f 732 #if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
Anna Bridge 160:5571c4ff569f 733 /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
Anna Bridge 160:5571c4ff569f 734 __builtin_arm_set_fpscr(fpscr);
Anna Bridge 160:5571c4ff569f 735 #else
AnnaBridge 157:e7ca05fa8600 736 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory");
Anna Bridge 160:5571c4ff569f 737 #endif
AnnaBridge 157:e7ca05fa8600 738 #else
AnnaBridge 157:e7ca05fa8600 739 (void)fpscr;
AnnaBridge 157:e7ca05fa8600 740 #endif
AnnaBridge 157:e7ca05fa8600 741 }
AnnaBridge 157:e7ca05fa8600 742
AnnaBridge 157:e7ca05fa8600 743 #endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 744 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 745
AnnaBridge 157:e7ca05fa8600 746
AnnaBridge 157:e7ca05fa8600 747
AnnaBridge 157:e7ca05fa8600 748 /*@} end of CMSIS_Core_RegAccFunctions */
AnnaBridge 157:e7ca05fa8600 749
AnnaBridge 157:e7ca05fa8600 750
AnnaBridge 157:e7ca05fa8600 751 /* ########################## Core Instruction Access ######################### */
AnnaBridge 157:e7ca05fa8600 752 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
AnnaBridge 157:e7ca05fa8600 753 Access to dedicated instructions
AnnaBridge 157:e7ca05fa8600 754 @{
AnnaBridge 157:e7ca05fa8600 755 */
AnnaBridge 157:e7ca05fa8600 756
AnnaBridge 157:e7ca05fa8600 757 /* Define macros for porting to both thumb1 and thumb2.
AnnaBridge 157:e7ca05fa8600 758 * For thumb1, use low register (r0-r7), specified by constraint "l"
AnnaBridge 157:e7ca05fa8600 759 * Otherwise, use general registers, specified by constraint "r" */
AnnaBridge 157:e7ca05fa8600 760 #if defined (__thumb__) && !defined (__thumb2__)
AnnaBridge 157:e7ca05fa8600 761 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
AnnaBridge 157:e7ca05fa8600 762 #define __CMSIS_GCC_RW_REG(r) "+l" (r)
AnnaBridge 157:e7ca05fa8600 763 #define __CMSIS_GCC_USE_REG(r) "l" (r)
AnnaBridge 157:e7ca05fa8600 764 #else
AnnaBridge 157:e7ca05fa8600 765 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
AnnaBridge 157:e7ca05fa8600 766 #define __CMSIS_GCC_RW_REG(r) "+r" (r)
AnnaBridge 157:e7ca05fa8600 767 #define __CMSIS_GCC_USE_REG(r) "r" (r)
AnnaBridge 157:e7ca05fa8600 768 #endif
AnnaBridge 157:e7ca05fa8600 769
AnnaBridge 157:e7ca05fa8600 770 /**
AnnaBridge 157:e7ca05fa8600 771 \brief No Operation
AnnaBridge 157:e7ca05fa8600 772 \details No Operation does nothing. This instruction can be used for code alignment purposes.
AnnaBridge 157:e7ca05fa8600 773 */
AnnaBridge 157:e7ca05fa8600 774 //__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
AnnaBridge 157:e7ca05fa8600 775 //{
AnnaBridge 157:e7ca05fa8600 776 // __ASM volatile ("nop");
AnnaBridge 157:e7ca05fa8600 777 //}
AnnaBridge 157:e7ca05fa8600 778 #define __NOP() __ASM volatile ("nop") /* This implementation generates debug information */
AnnaBridge 157:e7ca05fa8600 779
AnnaBridge 157:e7ca05fa8600 780 /**
AnnaBridge 157:e7ca05fa8600 781 \brief Wait For Interrupt
AnnaBridge 157:e7ca05fa8600 782 \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
AnnaBridge 157:e7ca05fa8600 783 */
AnnaBridge 157:e7ca05fa8600 784 //__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
AnnaBridge 157:e7ca05fa8600 785 //{
AnnaBridge 157:e7ca05fa8600 786 // __ASM volatile ("wfi");
AnnaBridge 157:e7ca05fa8600 787 //}
AnnaBridge 157:e7ca05fa8600 788 #define __WFI() __ASM volatile ("wfi") /* This implementation generates debug information */
AnnaBridge 157:e7ca05fa8600 789
AnnaBridge 157:e7ca05fa8600 790
AnnaBridge 157:e7ca05fa8600 791 /**
AnnaBridge 157:e7ca05fa8600 792 \brief Wait For Event
AnnaBridge 157:e7ca05fa8600 793 \details Wait For Event is a hint instruction that permits the processor to enter
AnnaBridge 157:e7ca05fa8600 794 a low-power state until one of a number of events occurs.
AnnaBridge 157:e7ca05fa8600 795 */
AnnaBridge 157:e7ca05fa8600 796 //__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
AnnaBridge 157:e7ca05fa8600 797 //{
AnnaBridge 157:e7ca05fa8600 798 // __ASM volatile ("wfe");
AnnaBridge 157:e7ca05fa8600 799 //}
AnnaBridge 157:e7ca05fa8600 800 #define __WFE() __ASM volatile ("wfe") /* This implementation generates debug information */
AnnaBridge 157:e7ca05fa8600 801
AnnaBridge 157:e7ca05fa8600 802
AnnaBridge 157:e7ca05fa8600 803 /**
AnnaBridge 157:e7ca05fa8600 804 \brief Send Event
AnnaBridge 157:e7ca05fa8600 805 \details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
AnnaBridge 157:e7ca05fa8600 806 */
AnnaBridge 157:e7ca05fa8600 807 //__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
AnnaBridge 157:e7ca05fa8600 808 //{
AnnaBridge 157:e7ca05fa8600 809 // __ASM volatile ("sev");
AnnaBridge 157:e7ca05fa8600 810 //}
AnnaBridge 157:e7ca05fa8600 811 #define __SEV() __ASM volatile ("sev") /* This implementation generates debug information */
AnnaBridge 157:e7ca05fa8600 812
AnnaBridge 157:e7ca05fa8600 813
AnnaBridge 157:e7ca05fa8600 814 /**
AnnaBridge 157:e7ca05fa8600 815 \brief Instruction Synchronization Barrier
AnnaBridge 157:e7ca05fa8600 816 \details Instruction Synchronization Barrier flushes the pipeline in the processor,
AnnaBridge 157:e7ca05fa8600 817 so that all instructions following the ISB are fetched from cache or memory,
AnnaBridge 157:e7ca05fa8600 818 after the instruction has been completed.
AnnaBridge 157:e7ca05fa8600 819 */
AnnaBridge 157:e7ca05fa8600 820 __attribute__((always_inline)) __STATIC_INLINE void __ISB(void)
AnnaBridge 157:e7ca05fa8600 821 {
AnnaBridge 157:e7ca05fa8600 822 __ASM volatile ("isb 0xF":::"memory");
AnnaBridge 157:e7ca05fa8600 823 }
AnnaBridge 157:e7ca05fa8600 824
AnnaBridge 157:e7ca05fa8600 825
AnnaBridge 157:e7ca05fa8600 826 /**
AnnaBridge 157:e7ca05fa8600 827 \brief Data Synchronization Barrier
AnnaBridge 157:e7ca05fa8600 828 \details Acts as a special kind of Data Memory Barrier.
AnnaBridge 157:e7ca05fa8600 829 It completes when all explicit memory accesses before this instruction complete.
AnnaBridge 157:e7ca05fa8600 830 */
AnnaBridge 157:e7ca05fa8600 831 __attribute__((always_inline)) __STATIC_INLINE void __DSB(void)
AnnaBridge 157:e7ca05fa8600 832 {
AnnaBridge 157:e7ca05fa8600 833 __ASM volatile ("dsb 0xF":::"memory");
AnnaBridge 157:e7ca05fa8600 834 }
AnnaBridge 157:e7ca05fa8600 835
AnnaBridge 157:e7ca05fa8600 836
AnnaBridge 157:e7ca05fa8600 837 /**
AnnaBridge 157:e7ca05fa8600 838 \brief Data Memory Barrier
AnnaBridge 157:e7ca05fa8600 839 \details Ensures the apparent order of the explicit memory operations before
AnnaBridge 157:e7ca05fa8600 840 and after the instruction, without ensuring their completion.
AnnaBridge 157:e7ca05fa8600 841 */
AnnaBridge 157:e7ca05fa8600 842 __attribute__((always_inline)) __STATIC_INLINE void __DMB(void)
AnnaBridge 157:e7ca05fa8600 843 {
AnnaBridge 157:e7ca05fa8600 844 __ASM volatile ("dmb 0xF":::"memory");
AnnaBridge 157:e7ca05fa8600 845 }
AnnaBridge 157:e7ca05fa8600 846
AnnaBridge 157:e7ca05fa8600 847
AnnaBridge 157:e7ca05fa8600 848 /**
AnnaBridge 157:e7ca05fa8600 849 \brief Reverse byte order (32 bit)
Anna Bridge 160:5571c4ff569f 850 \details Reverses the byte order in unsigned integer value.
AnnaBridge 157:e7ca05fa8600 851 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 852 \return Reversed value
AnnaBridge 157:e7ca05fa8600 853 */
AnnaBridge 157:e7ca05fa8600 854 __attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
AnnaBridge 157:e7ca05fa8600 855 {
AnnaBridge 157:e7ca05fa8600 856 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
AnnaBridge 157:e7ca05fa8600 857 return __builtin_bswap32(value);
AnnaBridge 157:e7ca05fa8600 858 #else
AnnaBridge 157:e7ca05fa8600 859 uint32_t result;
AnnaBridge 157:e7ca05fa8600 860
AnnaBridge 157:e7ca05fa8600 861 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 157:e7ca05fa8600 862 return(result);
AnnaBridge 157:e7ca05fa8600 863 #endif
AnnaBridge 157:e7ca05fa8600 864 }
AnnaBridge 157:e7ca05fa8600 865
AnnaBridge 157:e7ca05fa8600 866
AnnaBridge 157:e7ca05fa8600 867 /**
AnnaBridge 157:e7ca05fa8600 868 \brief Reverse byte order (16 bit)
Anna Bridge 160:5571c4ff569f 869 \details Reverses the byte order in unsigned short value.
AnnaBridge 157:e7ca05fa8600 870 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 871 \return Reversed value
AnnaBridge 157:e7ca05fa8600 872 */
Anna Bridge 160:5571c4ff569f 873 __attribute__((always_inline)) __STATIC_INLINE uint16_t __REV16(uint16_t value)
AnnaBridge 157:e7ca05fa8600 874 {
Anna Bridge 160:5571c4ff569f 875 uint16_t result;
AnnaBridge 157:e7ca05fa8600 876
AnnaBridge 157:e7ca05fa8600 877 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 157:e7ca05fa8600 878 return(result);
AnnaBridge 157:e7ca05fa8600 879 }
AnnaBridge 157:e7ca05fa8600 880
AnnaBridge 157:e7ca05fa8600 881
AnnaBridge 157:e7ca05fa8600 882 /**
AnnaBridge 157:e7ca05fa8600 883 \brief Reverse byte order in signed short value
AnnaBridge 157:e7ca05fa8600 884 \details Reverses the byte order in a signed short value with sign extension to integer.
AnnaBridge 157:e7ca05fa8600 885 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 886 \return Reversed value
AnnaBridge 157:e7ca05fa8600 887 */
Anna Bridge 160:5571c4ff569f 888 __attribute__((always_inline)) __STATIC_INLINE int16_t __REVSH(int16_t value)
AnnaBridge 157:e7ca05fa8600 889 {
AnnaBridge 157:e7ca05fa8600 890 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
Anna Bridge 160:5571c4ff569f 891 return (int16_t)__builtin_bswap16(value);
AnnaBridge 157:e7ca05fa8600 892 #else
Anna Bridge 160:5571c4ff569f 893 int16_t result;
AnnaBridge 157:e7ca05fa8600 894
AnnaBridge 157:e7ca05fa8600 895 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
Anna Bridge 160:5571c4ff569f 896 return result;
AnnaBridge 157:e7ca05fa8600 897 #endif
AnnaBridge 157:e7ca05fa8600 898 }
AnnaBridge 157:e7ca05fa8600 899
AnnaBridge 157:e7ca05fa8600 900
AnnaBridge 157:e7ca05fa8600 901 /**
AnnaBridge 157:e7ca05fa8600 902 \brief Rotate Right in unsigned value (32 bit)
AnnaBridge 157:e7ca05fa8600 903 \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
AnnaBridge 157:e7ca05fa8600 904 \param [in] op1 Value to rotate
AnnaBridge 157:e7ca05fa8600 905 \param [in] op2 Number of Bits to rotate
AnnaBridge 157:e7ca05fa8600 906 \return Rotated value
AnnaBridge 157:e7ca05fa8600 907 */
AnnaBridge 157:e7ca05fa8600 908 __attribute__((always_inline)) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 909 {
AnnaBridge 157:e7ca05fa8600 910 return (op1 >> op2) | (op1 << (32U - op2));
AnnaBridge 157:e7ca05fa8600 911 }
AnnaBridge 157:e7ca05fa8600 912
AnnaBridge 157:e7ca05fa8600 913
AnnaBridge 157:e7ca05fa8600 914 /**
AnnaBridge 157:e7ca05fa8600 915 \brief Breakpoint
AnnaBridge 157:e7ca05fa8600 916 \details Causes the processor to enter Debug state.
AnnaBridge 157:e7ca05fa8600 917 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
AnnaBridge 157:e7ca05fa8600 918 \param [in] value is ignored by the processor.
AnnaBridge 157:e7ca05fa8600 919 If required, a debugger can use it to store additional information about the breakpoint.
AnnaBridge 157:e7ca05fa8600 920 */
AnnaBridge 157:e7ca05fa8600 921 #define __BKPT(value) __ASM volatile ("bkpt "#value)
AnnaBridge 157:e7ca05fa8600 922
AnnaBridge 157:e7ca05fa8600 923
AnnaBridge 157:e7ca05fa8600 924 /**
AnnaBridge 157:e7ca05fa8600 925 \brief Reverse bit order of value
AnnaBridge 157:e7ca05fa8600 926 \details Reverses the bit order of the given value.
AnnaBridge 157:e7ca05fa8600 927 \param [in] value Value to reverse
AnnaBridge 157:e7ca05fa8600 928 \return Reversed value
AnnaBridge 157:e7ca05fa8600 929 */
AnnaBridge 157:e7ca05fa8600 930 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
AnnaBridge 157:e7ca05fa8600 931 {
AnnaBridge 157:e7ca05fa8600 932 uint32_t result;
AnnaBridge 157:e7ca05fa8600 933
AnnaBridge 157:e7ca05fa8600 934 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 935 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 936 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 937 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
AnnaBridge 157:e7ca05fa8600 938 #else
Anna Bridge 160:5571c4ff569f 939 uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
AnnaBridge 157:e7ca05fa8600 940
AnnaBridge 157:e7ca05fa8600 941 result = value; /* r will be reversed bits of v; first get LSB of v */
Anna Bridge 160:5571c4ff569f 942 for (value >>= 1U; value != 0U; value >>= 1U)
AnnaBridge 157:e7ca05fa8600 943 {
AnnaBridge 157:e7ca05fa8600 944 result <<= 1U;
AnnaBridge 157:e7ca05fa8600 945 result |= value & 1U;
AnnaBridge 157:e7ca05fa8600 946 s--;
AnnaBridge 157:e7ca05fa8600 947 }
AnnaBridge 157:e7ca05fa8600 948 result <<= s; /* shift when v's highest bits are zero */
AnnaBridge 157:e7ca05fa8600 949 #endif
Anna Bridge 160:5571c4ff569f 950 return result;
AnnaBridge 157:e7ca05fa8600 951 }
AnnaBridge 157:e7ca05fa8600 952
AnnaBridge 157:e7ca05fa8600 953
AnnaBridge 157:e7ca05fa8600 954 /**
AnnaBridge 157:e7ca05fa8600 955 \brief Count leading zeros
AnnaBridge 157:e7ca05fa8600 956 \details Counts the number of leading zeros of a data value.
AnnaBridge 157:e7ca05fa8600 957 \param [in] value Value to count the leading zeros
AnnaBridge 157:e7ca05fa8600 958 \return number of leading zeros in value
AnnaBridge 157:e7ca05fa8600 959 */
AnnaBridge 157:e7ca05fa8600 960 #define __CLZ __builtin_clz
AnnaBridge 157:e7ca05fa8600 961
AnnaBridge 157:e7ca05fa8600 962
AnnaBridge 157:e7ca05fa8600 963 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 964 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 965 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 966 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 157:e7ca05fa8600 967 /**
AnnaBridge 157:e7ca05fa8600 968 \brief LDR Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 969 \details Executes a exclusive LDR instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 970 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 971 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 972 */
AnnaBridge 157:e7ca05fa8600 973 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
AnnaBridge 157:e7ca05fa8600 974 {
AnnaBridge 157:e7ca05fa8600 975 uint32_t result;
AnnaBridge 157:e7ca05fa8600 976
AnnaBridge 157:e7ca05fa8600 977 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 157:e7ca05fa8600 978 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 157:e7ca05fa8600 979 #else
AnnaBridge 157:e7ca05fa8600 980 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 157:e7ca05fa8600 981 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 157:e7ca05fa8600 982 */
AnnaBridge 157:e7ca05fa8600 983 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 157:e7ca05fa8600 984 #endif
AnnaBridge 157:e7ca05fa8600 985 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 157:e7ca05fa8600 986 }
AnnaBridge 157:e7ca05fa8600 987
AnnaBridge 157:e7ca05fa8600 988
AnnaBridge 157:e7ca05fa8600 989 /**
AnnaBridge 157:e7ca05fa8600 990 \brief LDR Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 991 \details Executes a exclusive LDR instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 992 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 993 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 994 */
AnnaBridge 157:e7ca05fa8600 995 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
AnnaBridge 157:e7ca05fa8600 996 {
AnnaBridge 157:e7ca05fa8600 997 uint32_t result;
AnnaBridge 157:e7ca05fa8600 998
AnnaBridge 157:e7ca05fa8600 999 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 157:e7ca05fa8600 1000 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 157:e7ca05fa8600 1001 #else
AnnaBridge 157:e7ca05fa8600 1002 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 157:e7ca05fa8600 1003 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 157:e7ca05fa8600 1004 */
AnnaBridge 157:e7ca05fa8600 1005 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
AnnaBridge 157:e7ca05fa8600 1006 #endif
AnnaBridge 157:e7ca05fa8600 1007 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 157:e7ca05fa8600 1008 }
AnnaBridge 157:e7ca05fa8600 1009
AnnaBridge 157:e7ca05fa8600 1010
AnnaBridge 157:e7ca05fa8600 1011 /**
AnnaBridge 157:e7ca05fa8600 1012 \brief LDR Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 1013 \details Executes a exclusive LDR instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1014 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1015 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1016 */
AnnaBridge 157:e7ca05fa8600 1017 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
AnnaBridge 157:e7ca05fa8600 1018 {
AnnaBridge 157:e7ca05fa8600 1019 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1020
AnnaBridge 157:e7ca05fa8600 1021 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
AnnaBridge 157:e7ca05fa8600 1022 return(result);
AnnaBridge 157:e7ca05fa8600 1023 }
AnnaBridge 157:e7ca05fa8600 1024
AnnaBridge 157:e7ca05fa8600 1025
AnnaBridge 157:e7ca05fa8600 1026 /**
AnnaBridge 157:e7ca05fa8600 1027 \brief STR Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 1028 \details Executes a exclusive STR instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1029 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1030 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1031 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1032 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1033 */
AnnaBridge 157:e7ca05fa8600 1034 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
AnnaBridge 157:e7ca05fa8600 1035 {
AnnaBridge 157:e7ca05fa8600 1036 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1037
AnnaBridge 157:e7ca05fa8600 1038 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1039 return(result);
AnnaBridge 157:e7ca05fa8600 1040 }
AnnaBridge 157:e7ca05fa8600 1041
AnnaBridge 157:e7ca05fa8600 1042
AnnaBridge 157:e7ca05fa8600 1043 /**
AnnaBridge 157:e7ca05fa8600 1044 \brief STR Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 1045 \details Executes a exclusive STR instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1046 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1047 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1048 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1049 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1050 */
AnnaBridge 157:e7ca05fa8600 1051 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
AnnaBridge 157:e7ca05fa8600 1052 {
AnnaBridge 157:e7ca05fa8600 1053 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1054
AnnaBridge 157:e7ca05fa8600 1055 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1056 return(result);
AnnaBridge 157:e7ca05fa8600 1057 }
AnnaBridge 157:e7ca05fa8600 1058
AnnaBridge 157:e7ca05fa8600 1059
AnnaBridge 157:e7ca05fa8600 1060 /**
AnnaBridge 157:e7ca05fa8600 1061 \brief STR Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 1062 \details Executes a exclusive STR instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1063 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1064 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1065 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1066 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1067 */
AnnaBridge 157:e7ca05fa8600 1068 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
AnnaBridge 157:e7ca05fa8600 1069 {
AnnaBridge 157:e7ca05fa8600 1070 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1071
AnnaBridge 157:e7ca05fa8600 1072 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
AnnaBridge 157:e7ca05fa8600 1073 return(result);
AnnaBridge 157:e7ca05fa8600 1074 }
AnnaBridge 157:e7ca05fa8600 1075
AnnaBridge 157:e7ca05fa8600 1076
AnnaBridge 157:e7ca05fa8600 1077 /**
AnnaBridge 157:e7ca05fa8600 1078 \brief Remove the exclusive lock
AnnaBridge 157:e7ca05fa8600 1079 \details Removes the exclusive lock which is created by LDREX.
AnnaBridge 157:e7ca05fa8600 1080 */
AnnaBridge 157:e7ca05fa8600 1081 __attribute__((always_inline)) __STATIC_INLINE void __CLREX(void)
AnnaBridge 157:e7ca05fa8600 1082 {
AnnaBridge 157:e7ca05fa8600 1083 __ASM volatile ("clrex" ::: "memory");
AnnaBridge 157:e7ca05fa8600 1084 }
AnnaBridge 157:e7ca05fa8600 1085
AnnaBridge 157:e7ca05fa8600 1086 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1087 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1088 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1089 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 1090
AnnaBridge 157:e7ca05fa8600 1091
AnnaBridge 157:e7ca05fa8600 1092 #if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1093 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1094 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
AnnaBridge 157:e7ca05fa8600 1095 /**
AnnaBridge 157:e7ca05fa8600 1096 \brief Signed Saturate
AnnaBridge 157:e7ca05fa8600 1097 \details Saturates a signed value.
Anna Bridge 160:5571c4ff569f 1098 \param [in] ARG1 Value to be saturated
Anna Bridge 160:5571c4ff569f 1099 \param [in] ARG2 Bit position to saturate to (1..32)
AnnaBridge 157:e7ca05fa8600 1100 \return Saturated value
AnnaBridge 157:e7ca05fa8600 1101 */
AnnaBridge 157:e7ca05fa8600 1102 #define __SSAT(ARG1,ARG2) \
Anna Bridge 160:5571c4ff569f 1103 __extension__ \
AnnaBridge 157:e7ca05fa8600 1104 ({ \
AnnaBridge 157:e7ca05fa8600 1105 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 157:e7ca05fa8600 1106 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 157:e7ca05fa8600 1107 __RES; \
AnnaBridge 157:e7ca05fa8600 1108 })
AnnaBridge 157:e7ca05fa8600 1109
AnnaBridge 157:e7ca05fa8600 1110
AnnaBridge 157:e7ca05fa8600 1111 /**
AnnaBridge 157:e7ca05fa8600 1112 \brief Unsigned Saturate
AnnaBridge 157:e7ca05fa8600 1113 \details Saturates an unsigned value.
Anna Bridge 160:5571c4ff569f 1114 \param [in] ARG1 Value to be saturated
Anna Bridge 160:5571c4ff569f 1115 \param [in] ARG2 Bit position to saturate to (0..31)
AnnaBridge 157:e7ca05fa8600 1116 \return Saturated value
AnnaBridge 157:e7ca05fa8600 1117 */
AnnaBridge 157:e7ca05fa8600 1118 #define __USAT(ARG1,ARG2) \
Anna Bridge 160:5571c4ff569f 1119 __extension__ \
AnnaBridge 157:e7ca05fa8600 1120 ({ \
AnnaBridge 157:e7ca05fa8600 1121 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 157:e7ca05fa8600 1122 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 157:e7ca05fa8600 1123 __RES; \
AnnaBridge 157:e7ca05fa8600 1124 })
AnnaBridge 157:e7ca05fa8600 1125
AnnaBridge 157:e7ca05fa8600 1126
AnnaBridge 157:e7ca05fa8600 1127 /**
AnnaBridge 157:e7ca05fa8600 1128 \brief Rotate Right with Extend (32 bit)
AnnaBridge 157:e7ca05fa8600 1129 \details Moves each bit of a bitstring right by one bit.
AnnaBridge 157:e7ca05fa8600 1130 The carry input is shifted in at the left end of the bitstring.
AnnaBridge 157:e7ca05fa8600 1131 \param [in] value Value to rotate
AnnaBridge 157:e7ca05fa8600 1132 \return Rotated value
AnnaBridge 157:e7ca05fa8600 1133 */
AnnaBridge 157:e7ca05fa8600 1134 __attribute__((always_inline)) __STATIC_INLINE uint32_t __RRX(uint32_t value)
AnnaBridge 157:e7ca05fa8600 1135 {
AnnaBridge 157:e7ca05fa8600 1136 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1137
AnnaBridge 157:e7ca05fa8600 1138 __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
AnnaBridge 157:e7ca05fa8600 1139 return(result);
AnnaBridge 157:e7ca05fa8600 1140 }
AnnaBridge 157:e7ca05fa8600 1141
AnnaBridge 157:e7ca05fa8600 1142
AnnaBridge 157:e7ca05fa8600 1143 /**
AnnaBridge 157:e7ca05fa8600 1144 \brief LDRT Unprivileged (8 bit)
AnnaBridge 157:e7ca05fa8600 1145 \details Executes a Unprivileged LDRT instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 1146 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1147 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1148 */
AnnaBridge 157:e7ca05fa8600 1149 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDRBT(volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1150 {
AnnaBridge 157:e7ca05fa8600 1151 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1152
AnnaBridge 157:e7ca05fa8600 1153 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 157:e7ca05fa8600 1154 __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1155 #else
AnnaBridge 157:e7ca05fa8600 1156 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 157:e7ca05fa8600 1157 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 157:e7ca05fa8600 1158 */
AnnaBridge 157:e7ca05fa8600 1159 __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge 157:e7ca05fa8600 1160 #endif
AnnaBridge 157:e7ca05fa8600 1161 return ((uint8_t) result); /* Add explicit type cast here */
AnnaBridge 157:e7ca05fa8600 1162 }
AnnaBridge 157:e7ca05fa8600 1163
AnnaBridge 157:e7ca05fa8600 1164
AnnaBridge 157:e7ca05fa8600 1165 /**
AnnaBridge 157:e7ca05fa8600 1166 \brief LDRT Unprivileged (16 bit)
AnnaBridge 157:e7ca05fa8600 1167 \details Executes a Unprivileged LDRT instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1168 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1169 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1170 */
AnnaBridge 157:e7ca05fa8600 1171 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDRHT(volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1172 {
AnnaBridge 157:e7ca05fa8600 1173 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1174
AnnaBridge 157:e7ca05fa8600 1175 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
AnnaBridge 157:e7ca05fa8600 1176 __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1177 #else
AnnaBridge 157:e7ca05fa8600 1178 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
AnnaBridge 157:e7ca05fa8600 1179 accepted by assembler. So has to use following less efficient pattern.
AnnaBridge 157:e7ca05fa8600 1180 */
AnnaBridge 157:e7ca05fa8600 1181 __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" );
AnnaBridge 157:e7ca05fa8600 1182 #endif
AnnaBridge 157:e7ca05fa8600 1183 return ((uint16_t) result); /* Add explicit type cast here */
AnnaBridge 157:e7ca05fa8600 1184 }
AnnaBridge 157:e7ca05fa8600 1185
AnnaBridge 157:e7ca05fa8600 1186
AnnaBridge 157:e7ca05fa8600 1187 /**
AnnaBridge 157:e7ca05fa8600 1188 \brief LDRT Unprivileged (32 bit)
AnnaBridge 157:e7ca05fa8600 1189 \details Executes a Unprivileged LDRT instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1190 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1191 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1192 */
AnnaBridge 157:e7ca05fa8600 1193 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDRT(volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1194 {
AnnaBridge 157:e7ca05fa8600 1195 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1196
AnnaBridge 157:e7ca05fa8600 1197 __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1198 return(result);
AnnaBridge 157:e7ca05fa8600 1199 }
AnnaBridge 157:e7ca05fa8600 1200
AnnaBridge 157:e7ca05fa8600 1201
AnnaBridge 157:e7ca05fa8600 1202 /**
AnnaBridge 157:e7ca05fa8600 1203 \brief STRT Unprivileged (8 bit)
AnnaBridge 157:e7ca05fa8600 1204 \details Executes a Unprivileged STRT instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1205 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1206 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1207 */
AnnaBridge 157:e7ca05fa8600 1208 __attribute__((always_inline)) __STATIC_INLINE void __STRBT(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1209 {
AnnaBridge 157:e7ca05fa8600 1210 __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1211 }
AnnaBridge 157:e7ca05fa8600 1212
AnnaBridge 157:e7ca05fa8600 1213
AnnaBridge 157:e7ca05fa8600 1214 /**
AnnaBridge 157:e7ca05fa8600 1215 \brief STRT Unprivileged (16 bit)
AnnaBridge 157:e7ca05fa8600 1216 \details Executes a Unprivileged STRT instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1217 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1218 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1219 */
AnnaBridge 157:e7ca05fa8600 1220 __attribute__((always_inline)) __STATIC_INLINE void __STRHT(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1221 {
AnnaBridge 157:e7ca05fa8600 1222 __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1223 }
AnnaBridge 157:e7ca05fa8600 1224
AnnaBridge 157:e7ca05fa8600 1225
AnnaBridge 157:e7ca05fa8600 1226 /**
AnnaBridge 157:e7ca05fa8600 1227 \brief STRT Unprivileged (32 bit)
AnnaBridge 157:e7ca05fa8600 1228 \details Executes a Unprivileged STRT instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1229 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1230 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1231 */
AnnaBridge 157:e7ca05fa8600 1232 __attribute__((always_inline)) __STATIC_INLINE void __STRT(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1233 {
AnnaBridge 157:e7ca05fa8600 1234 __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) );
AnnaBridge 157:e7ca05fa8600 1235 }
AnnaBridge 157:e7ca05fa8600 1236
Anna Bridge 160:5571c4ff569f 1237 #else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
Anna Bridge 160:5571c4ff569f 1238 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
Anna Bridge 160:5571c4ff569f 1239 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
Anna Bridge 160:5571c4ff569f 1240
Anna Bridge 160:5571c4ff569f 1241 /**
Anna Bridge 160:5571c4ff569f 1242 \brief Signed Saturate
Anna Bridge 160:5571c4ff569f 1243 \details Saturates a signed value.
Anna Bridge 160:5571c4ff569f 1244 \param [in] value Value to be saturated
Anna Bridge 160:5571c4ff569f 1245 \param [in] sat Bit position to saturate to (1..32)
Anna Bridge 160:5571c4ff569f 1246 \return Saturated value
Anna Bridge 160:5571c4ff569f 1247 */
Anna Bridge 160:5571c4ff569f 1248 __attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat)
Anna Bridge 160:5571c4ff569f 1249 {
Anna Bridge 160:5571c4ff569f 1250 if ((sat >= 1U) && (sat <= 32U)) {
Anna Bridge 160:5571c4ff569f 1251 const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U);
Anna Bridge 160:5571c4ff569f 1252 const int32_t min = -1 - max ;
Anna Bridge 160:5571c4ff569f 1253 if (val > max) {
Anna Bridge 160:5571c4ff569f 1254 return max;
Anna Bridge 160:5571c4ff569f 1255 } else if (val < min) {
Anna Bridge 160:5571c4ff569f 1256 return min;
Anna Bridge 160:5571c4ff569f 1257 }
Anna Bridge 160:5571c4ff569f 1258 }
Anna Bridge 160:5571c4ff569f 1259 return val;
Anna Bridge 160:5571c4ff569f 1260 }
Anna Bridge 160:5571c4ff569f 1261
Anna Bridge 160:5571c4ff569f 1262 /**
Anna Bridge 160:5571c4ff569f 1263 \brief Unsigned Saturate
Anna Bridge 160:5571c4ff569f 1264 \details Saturates an unsigned value.
Anna Bridge 160:5571c4ff569f 1265 \param [in] value Value to be saturated
Anna Bridge 160:5571c4ff569f 1266 \param [in] sat Bit position to saturate to (0..31)
Anna Bridge 160:5571c4ff569f 1267 \return Saturated value
Anna Bridge 160:5571c4ff569f 1268 */
Anna Bridge 160:5571c4ff569f 1269 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
Anna Bridge 160:5571c4ff569f 1270 {
Anna Bridge 160:5571c4ff569f 1271 if (sat <= 31U) {
Anna Bridge 160:5571c4ff569f 1272 const uint32_t max = ((1U << sat) - 1U);
Anna Bridge 160:5571c4ff569f 1273 if (val > (int32_t)max) {
Anna Bridge 160:5571c4ff569f 1274 return max;
Anna Bridge 160:5571c4ff569f 1275 } else if (val < 0) {
Anna Bridge 160:5571c4ff569f 1276 return 0U;
Anna Bridge 160:5571c4ff569f 1277 }
Anna Bridge 160:5571c4ff569f 1278 }
Anna Bridge 160:5571c4ff569f 1279 return (uint32_t)val;
Anna Bridge 160:5571c4ff569f 1280 }
Anna Bridge 160:5571c4ff569f 1281
AnnaBridge 157:e7ca05fa8600 1282 #endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1283 (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1284 (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 1285
AnnaBridge 157:e7ca05fa8600 1286
AnnaBridge 157:e7ca05fa8600 1287 #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1288 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) )
AnnaBridge 157:e7ca05fa8600 1289 /**
AnnaBridge 157:e7ca05fa8600 1290 \brief Load-Acquire (8 bit)
AnnaBridge 157:e7ca05fa8600 1291 \details Executes a LDAB instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 1292 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1293 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1294 */
AnnaBridge 157:e7ca05fa8600 1295 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAB(volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1296 {
AnnaBridge 157:e7ca05fa8600 1297 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1298
AnnaBridge 157:e7ca05fa8600 1299 __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1300 return ((uint8_t) result);
AnnaBridge 157:e7ca05fa8600 1301 }
AnnaBridge 157:e7ca05fa8600 1302
AnnaBridge 157:e7ca05fa8600 1303
AnnaBridge 157:e7ca05fa8600 1304 /**
AnnaBridge 157:e7ca05fa8600 1305 \brief Load-Acquire (16 bit)
AnnaBridge 157:e7ca05fa8600 1306 \details Executes a LDAH instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1307 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1308 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1309 */
AnnaBridge 157:e7ca05fa8600 1310 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAH(volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1311 {
AnnaBridge 157:e7ca05fa8600 1312 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1313
AnnaBridge 157:e7ca05fa8600 1314 __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1315 return ((uint16_t) result);
AnnaBridge 157:e7ca05fa8600 1316 }
AnnaBridge 157:e7ca05fa8600 1317
AnnaBridge 157:e7ca05fa8600 1318
AnnaBridge 157:e7ca05fa8600 1319 /**
AnnaBridge 157:e7ca05fa8600 1320 \brief Load-Acquire (32 bit)
AnnaBridge 157:e7ca05fa8600 1321 \details Executes a LDA instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1322 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1323 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1324 */
AnnaBridge 157:e7ca05fa8600 1325 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDA(volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1326 {
AnnaBridge 157:e7ca05fa8600 1327 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1328
AnnaBridge 157:e7ca05fa8600 1329 __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1330 return(result);
AnnaBridge 157:e7ca05fa8600 1331 }
AnnaBridge 157:e7ca05fa8600 1332
AnnaBridge 157:e7ca05fa8600 1333
AnnaBridge 157:e7ca05fa8600 1334 /**
AnnaBridge 157:e7ca05fa8600 1335 \brief Store-Release (8 bit)
AnnaBridge 157:e7ca05fa8600 1336 \details Executes a STLB instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1337 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1338 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1339 */
AnnaBridge 157:e7ca05fa8600 1340 __attribute__((always_inline)) __STATIC_INLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1341 {
AnnaBridge 157:e7ca05fa8600 1342 __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1343 }
AnnaBridge 157:e7ca05fa8600 1344
AnnaBridge 157:e7ca05fa8600 1345
AnnaBridge 157:e7ca05fa8600 1346 /**
AnnaBridge 157:e7ca05fa8600 1347 \brief Store-Release (16 bit)
AnnaBridge 157:e7ca05fa8600 1348 \details Executes a STLH instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1349 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1350 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1351 */
AnnaBridge 157:e7ca05fa8600 1352 __attribute__((always_inline)) __STATIC_INLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1353 {
AnnaBridge 157:e7ca05fa8600 1354 __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1355 }
AnnaBridge 157:e7ca05fa8600 1356
AnnaBridge 157:e7ca05fa8600 1357
AnnaBridge 157:e7ca05fa8600 1358 /**
AnnaBridge 157:e7ca05fa8600 1359 \brief Store-Release (32 bit)
AnnaBridge 157:e7ca05fa8600 1360 \details Executes a STL instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1361 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1362 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1363 */
AnnaBridge 157:e7ca05fa8600 1364 __attribute__((always_inline)) __STATIC_INLINE void __STL(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1365 {
AnnaBridge 157:e7ca05fa8600 1366 __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1367 }
AnnaBridge 157:e7ca05fa8600 1368
AnnaBridge 157:e7ca05fa8600 1369
AnnaBridge 157:e7ca05fa8600 1370 /**
AnnaBridge 157:e7ca05fa8600 1371 \brief Load-Acquire Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 1372 \details Executes a LDAB exclusive instruction for 8 bit value.
AnnaBridge 157:e7ca05fa8600 1373 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1374 \return value of type uint8_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1375 */
AnnaBridge 157:e7ca05fa8600 1376 __attribute__((always_inline)) __STATIC_INLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1377 {
AnnaBridge 157:e7ca05fa8600 1378 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1379
AnnaBridge 157:e7ca05fa8600 1380 __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1381 return ((uint8_t) result);
AnnaBridge 157:e7ca05fa8600 1382 }
AnnaBridge 157:e7ca05fa8600 1383
AnnaBridge 157:e7ca05fa8600 1384
AnnaBridge 157:e7ca05fa8600 1385 /**
AnnaBridge 157:e7ca05fa8600 1386 \brief Load-Acquire Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 1387 \details Executes a LDAH exclusive instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1388 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1389 \return value of type uint16_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1390 */
AnnaBridge 157:e7ca05fa8600 1391 __attribute__((always_inline)) __STATIC_INLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1392 {
AnnaBridge 157:e7ca05fa8600 1393 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1394
AnnaBridge 157:e7ca05fa8600 1395 __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1396 return ((uint16_t) result);
AnnaBridge 157:e7ca05fa8600 1397 }
AnnaBridge 157:e7ca05fa8600 1398
AnnaBridge 157:e7ca05fa8600 1399
AnnaBridge 157:e7ca05fa8600 1400 /**
AnnaBridge 157:e7ca05fa8600 1401 \brief Load-Acquire Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 1402 \details Executes a LDA exclusive instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1403 \param [in] ptr Pointer to data
AnnaBridge 157:e7ca05fa8600 1404 \return value of type uint32_t at (*ptr)
AnnaBridge 157:e7ca05fa8600 1405 */
AnnaBridge 157:e7ca05fa8600 1406 __attribute__((always_inline)) __STATIC_INLINE uint32_t __LDAEX(volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1407 {
AnnaBridge 157:e7ca05fa8600 1408 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1409
AnnaBridge 157:e7ca05fa8600 1410 __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
AnnaBridge 157:e7ca05fa8600 1411 return(result);
AnnaBridge 157:e7ca05fa8600 1412 }
AnnaBridge 157:e7ca05fa8600 1413
AnnaBridge 157:e7ca05fa8600 1414
AnnaBridge 157:e7ca05fa8600 1415 /**
AnnaBridge 157:e7ca05fa8600 1416 \brief Store-Release Exclusive (8 bit)
AnnaBridge 157:e7ca05fa8600 1417 \details Executes a STLB exclusive instruction for 8 bit values.
AnnaBridge 157:e7ca05fa8600 1418 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1419 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1420 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1421 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1422 */
AnnaBridge 157:e7ca05fa8600 1423 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
AnnaBridge 157:e7ca05fa8600 1424 {
AnnaBridge 157:e7ca05fa8600 1425 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1426
AnnaBridge 157:e7ca05fa8600 1427 __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1428 return(result);
AnnaBridge 157:e7ca05fa8600 1429 }
AnnaBridge 157:e7ca05fa8600 1430
AnnaBridge 157:e7ca05fa8600 1431
AnnaBridge 157:e7ca05fa8600 1432 /**
AnnaBridge 157:e7ca05fa8600 1433 \brief Store-Release Exclusive (16 bit)
AnnaBridge 157:e7ca05fa8600 1434 \details Executes a STLH exclusive instruction for 16 bit values.
AnnaBridge 157:e7ca05fa8600 1435 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1436 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1437 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1438 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1439 */
AnnaBridge 157:e7ca05fa8600 1440 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
AnnaBridge 157:e7ca05fa8600 1441 {
AnnaBridge 157:e7ca05fa8600 1442 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1443
AnnaBridge 157:e7ca05fa8600 1444 __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1445 return(result);
AnnaBridge 157:e7ca05fa8600 1446 }
AnnaBridge 157:e7ca05fa8600 1447
AnnaBridge 157:e7ca05fa8600 1448
AnnaBridge 157:e7ca05fa8600 1449 /**
AnnaBridge 157:e7ca05fa8600 1450 \brief Store-Release Exclusive (32 bit)
AnnaBridge 157:e7ca05fa8600 1451 \details Executes a STL exclusive instruction for 32 bit values.
AnnaBridge 157:e7ca05fa8600 1452 \param [in] value Value to store
AnnaBridge 157:e7ca05fa8600 1453 \param [in] ptr Pointer to location
AnnaBridge 157:e7ca05fa8600 1454 \return 0 Function succeeded
AnnaBridge 157:e7ca05fa8600 1455 \return 1 Function failed
AnnaBridge 157:e7ca05fa8600 1456 */
AnnaBridge 157:e7ca05fa8600 1457 __attribute__((always_inline)) __STATIC_INLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
AnnaBridge 157:e7ca05fa8600 1458 {
AnnaBridge 157:e7ca05fa8600 1459 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1460
AnnaBridge 157:e7ca05fa8600 1461 __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
AnnaBridge 157:e7ca05fa8600 1462 return(result);
AnnaBridge 157:e7ca05fa8600 1463 }
AnnaBridge 157:e7ca05fa8600 1464
AnnaBridge 157:e7ca05fa8600 1465 #endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \
AnnaBridge 157:e7ca05fa8600 1466 (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
AnnaBridge 157:e7ca05fa8600 1467
AnnaBridge 157:e7ca05fa8600 1468 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
AnnaBridge 157:e7ca05fa8600 1469
AnnaBridge 157:e7ca05fa8600 1470
AnnaBridge 157:e7ca05fa8600 1471 /* ################### Compiler specific Intrinsics ########################### */
AnnaBridge 157:e7ca05fa8600 1472 /** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
AnnaBridge 157:e7ca05fa8600 1473 Access to dedicated SIMD instructions
AnnaBridge 157:e7ca05fa8600 1474 @{
AnnaBridge 157:e7ca05fa8600 1475 */
AnnaBridge 157:e7ca05fa8600 1476
AnnaBridge 157:e7ca05fa8600 1477 #if (__ARM_FEATURE_DSP == 1) /* ToDo ARMCLANG: This should be ARCH >= ARMv7-M + SIMD */
AnnaBridge 157:e7ca05fa8600 1478
AnnaBridge 157:e7ca05fa8600 1479 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1480 {
AnnaBridge 157:e7ca05fa8600 1481 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1482
AnnaBridge 157:e7ca05fa8600 1483 __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1484 return(result);
AnnaBridge 157:e7ca05fa8600 1485 }
AnnaBridge 157:e7ca05fa8600 1486
AnnaBridge 157:e7ca05fa8600 1487 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1488 {
AnnaBridge 157:e7ca05fa8600 1489 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1490
AnnaBridge 157:e7ca05fa8600 1491 __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1492 return(result);
AnnaBridge 157:e7ca05fa8600 1493 }
AnnaBridge 157:e7ca05fa8600 1494
AnnaBridge 157:e7ca05fa8600 1495 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1496 {
AnnaBridge 157:e7ca05fa8600 1497 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1498
AnnaBridge 157:e7ca05fa8600 1499 __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1500 return(result);
AnnaBridge 157:e7ca05fa8600 1501 }
AnnaBridge 157:e7ca05fa8600 1502
AnnaBridge 157:e7ca05fa8600 1503 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1504 {
AnnaBridge 157:e7ca05fa8600 1505 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1506
AnnaBridge 157:e7ca05fa8600 1507 __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1508 return(result);
AnnaBridge 157:e7ca05fa8600 1509 }
AnnaBridge 157:e7ca05fa8600 1510
AnnaBridge 157:e7ca05fa8600 1511 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1512 {
AnnaBridge 157:e7ca05fa8600 1513 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1514
AnnaBridge 157:e7ca05fa8600 1515 __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1516 return(result);
AnnaBridge 157:e7ca05fa8600 1517 }
AnnaBridge 157:e7ca05fa8600 1518
AnnaBridge 157:e7ca05fa8600 1519 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1520 {
AnnaBridge 157:e7ca05fa8600 1521 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1522
AnnaBridge 157:e7ca05fa8600 1523 __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1524 return(result);
AnnaBridge 157:e7ca05fa8600 1525 }
AnnaBridge 157:e7ca05fa8600 1526
AnnaBridge 157:e7ca05fa8600 1527
AnnaBridge 157:e7ca05fa8600 1528 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1529 {
AnnaBridge 157:e7ca05fa8600 1530 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1531
AnnaBridge 157:e7ca05fa8600 1532 __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1533 return(result);
AnnaBridge 157:e7ca05fa8600 1534 }
AnnaBridge 157:e7ca05fa8600 1535
AnnaBridge 157:e7ca05fa8600 1536 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1537 {
AnnaBridge 157:e7ca05fa8600 1538 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1539
AnnaBridge 157:e7ca05fa8600 1540 __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1541 return(result);
AnnaBridge 157:e7ca05fa8600 1542 }
AnnaBridge 157:e7ca05fa8600 1543
AnnaBridge 157:e7ca05fa8600 1544 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1545 {
AnnaBridge 157:e7ca05fa8600 1546 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1547
AnnaBridge 157:e7ca05fa8600 1548 __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1549 return(result);
AnnaBridge 157:e7ca05fa8600 1550 }
AnnaBridge 157:e7ca05fa8600 1551
AnnaBridge 157:e7ca05fa8600 1552 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1553 {
AnnaBridge 157:e7ca05fa8600 1554 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1555
AnnaBridge 157:e7ca05fa8600 1556 __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1557 return(result);
AnnaBridge 157:e7ca05fa8600 1558 }
AnnaBridge 157:e7ca05fa8600 1559
AnnaBridge 157:e7ca05fa8600 1560 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1561 {
AnnaBridge 157:e7ca05fa8600 1562 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1563
AnnaBridge 157:e7ca05fa8600 1564 __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1565 return(result);
AnnaBridge 157:e7ca05fa8600 1566 }
AnnaBridge 157:e7ca05fa8600 1567
AnnaBridge 157:e7ca05fa8600 1568 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1569 {
AnnaBridge 157:e7ca05fa8600 1570 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1571
AnnaBridge 157:e7ca05fa8600 1572 __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1573 return(result);
AnnaBridge 157:e7ca05fa8600 1574 }
AnnaBridge 157:e7ca05fa8600 1575
AnnaBridge 157:e7ca05fa8600 1576
AnnaBridge 157:e7ca05fa8600 1577 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1578 {
AnnaBridge 157:e7ca05fa8600 1579 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1580
AnnaBridge 157:e7ca05fa8600 1581 __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1582 return(result);
AnnaBridge 157:e7ca05fa8600 1583 }
AnnaBridge 157:e7ca05fa8600 1584
AnnaBridge 157:e7ca05fa8600 1585 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1586 {
AnnaBridge 157:e7ca05fa8600 1587 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1588
AnnaBridge 157:e7ca05fa8600 1589 __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1590 return(result);
AnnaBridge 157:e7ca05fa8600 1591 }
AnnaBridge 157:e7ca05fa8600 1592
AnnaBridge 157:e7ca05fa8600 1593 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1594 {
AnnaBridge 157:e7ca05fa8600 1595 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1596
AnnaBridge 157:e7ca05fa8600 1597 __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1598 return(result);
AnnaBridge 157:e7ca05fa8600 1599 }
AnnaBridge 157:e7ca05fa8600 1600
AnnaBridge 157:e7ca05fa8600 1601 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1602 {
AnnaBridge 157:e7ca05fa8600 1603 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1604
AnnaBridge 157:e7ca05fa8600 1605 __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1606 return(result);
AnnaBridge 157:e7ca05fa8600 1607 }
AnnaBridge 157:e7ca05fa8600 1608
AnnaBridge 157:e7ca05fa8600 1609 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1610 {
AnnaBridge 157:e7ca05fa8600 1611 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1612
AnnaBridge 157:e7ca05fa8600 1613 __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1614 return(result);
AnnaBridge 157:e7ca05fa8600 1615 }
AnnaBridge 157:e7ca05fa8600 1616
AnnaBridge 157:e7ca05fa8600 1617 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1618 {
AnnaBridge 157:e7ca05fa8600 1619 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1620
AnnaBridge 157:e7ca05fa8600 1621 __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1622 return(result);
AnnaBridge 157:e7ca05fa8600 1623 }
AnnaBridge 157:e7ca05fa8600 1624
AnnaBridge 157:e7ca05fa8600 1625 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1626 {
AnnaBridge 157:e7ca05fa8600 1627 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1628
AnnaBridge 157:e7ca05fa8600 1629 __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1630 return(result);
AnnaBridge 157:e7ca05fa8600 1631 }
AnnaBridge 157:e7ca05fa8600 1632
AnnaBridge 157:e7ca05fa8600 1633 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1634 {
AnnaBridge 157:e7ca05fa8600 1635 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1636
AnnaBridge 157:e7ca05fa8600 1637 __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1638 return(result);
AnnaBridge 157:e7ca05fa8600 1639 }
AnnaBridge 157:e7ca05fa8600 1640
AnnaBridge 157:e7ca05fa8600 1641 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1642 {
AnnaBridge 157:e7ca05fa8600 1643 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1644
AnnaBridge 157:e7ca05fa8600 1645 __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1646 return(result);
AnnaBridge 157:e7ca05fa8600 1647 }
AnnaBridge 157:e7ca05fa8600 1648
AnnaBridge 157:e7ca05fa8600 1649 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1650 {
AnnaBridge 157:e7ca05fa8600 1651 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1652
AnnaBridge 157:e7ca05fa8600 1653 __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1654 return(result);
AnnaBridge 157:e7ca05fa8600 1655 }
AnnaBridge 157:e7ca05fa8600 1656
AnnaBridge 157:e7ca05fa8600 1657 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1658 {
AnnaBridge 157:e7ca05fa8600 1659 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1660
AnnaBridge 157:e7ca05fa8600 1661 __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1662 return(result);
AnnaBridge 157:e7ca05fa8600 1663 }
AnnaBridge 157:e7ca05fa8600 1664
AnnaBridge 157:e7ca05fa8600 1665 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1666 {
AnnaBridge 157:e7ca05fa8600 1667 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1668
AnnaBridge 157:e7ca05fa8600 1669 __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1670 return(result);
AnnaBridge 157:e7ca05fa8600 1671 }
AnnaBridge 157:e7ca05fa8600 1672
AnnaBridge 157:e7ca05fa8600 1673 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1674 {
AnnaBridge 157:e7ca05fa8600 1675 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1676
AnnaBridge 157:e7ca05fa8600 1677 __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1678 return(result);
AnnaBridge 157:e7ca05fa8600 1679 }
AnnaBridge 157:e7ca05fa8600 1680
AnnaBridge 157:e7ca05fa8600 1681 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1682 {
AnnaBridge 157:e7ca05fa8600 1683 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1684
AnnaBridge 157:e7ca05fa8600 1685 __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1686 return(result);
AnnaBridge 157:e7ca05fa8600 1687 }
AnnaBridge 157:e7ca05fa8600 1688
AnnaBridge 157:e7ca05fa8600 1689 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1690 {
AnnaBridge 157:e7ca05fa8600 1691 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1692
AnnaBridge 157:e7ca05fa8600 1693 __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1694 return(result);
AnnaBridge 157:e7ca05fa8600 1695 }
AnnaBridge 157:e7ca05fa8600 1696
AnnaBridge 157:e7ca05fa8600 1697 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1698 {
AnnaBridge 157:e7ca05fa8600 1699 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1700
AnnaBridge 157:e7ca05fa8600 1701 __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1702 return(result);
AnnaBridge 157:e7ca05fa8600 1703 }
AnnaBridge 157:e7ca05fa8600 1704
AnnaBridge 157:e7ca05fa8600 1705 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1706 {
AnnaBridge 157:e7ca05fa8600 1707 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1708
AnnaBridge 157:e7ca05fa8600 1709 __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1710 return(result);
AnnaBridge 157:e7ca05fa8600 1711 }
AnnaBridge 157:e7ca05fa8600 1712
AnnaBridge 157:e7ca05fa8600 1713 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1714 {
AnnaBridge 157:e7ca05fa8600 1715 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1716
AnnaBridge 157:e7ca05fa8600 1717 __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1718 return(result);
AnnaBridge 157:e7ca05fa8600 1719 }
AnnaBridge 157:e7ca05fa8600 1720
AnnaBridge 157:e7ca05fa8600 1721 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1722 {
AnnaBridge 157:e7ca05fa8600 1723 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1724
AnnaBridge 157:e7ca05fa8600 1725 __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1726 return(result);
AnnaBridge 157:e7ca05fa8600 1727 }
AnnaBridge 157:e7ca05fa8600 1728
AnnaBridge 157:e7ca05fa8600 1729 __attribute__((always_inline)) __STATIC_INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1730 {
AnnaBridge 157:e7ca05fa8600 1731 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1732
AnnaBridge 157:e7ca05fa8600 1733 __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1734 return(result);
AnnaBridge 157:e7ca05fa8600 1735 }
AnnaBridge 157:e7ca05fa8600 1736
AnnaBridge 157:e7ca05fa8600 1737 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1738 {
AnnaBridge 157:e7ca05fa8600 1739 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1740
AnnaBridge 157:e7ca05fa8600 1741 __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1742 return(result);
AnnaBridge 157:e7ca05fa8600 1743 }
AnnaBridge 157:e7ca05fa8600 1744
AnnaBridge 157:e7ca05fa8600 1745 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1746 {
AnnaBridge 157:e7ca05fa8600 1747 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1748
AnnaBridge 157:e7ca05fa8600 1749 __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1750 return(result);
AnnaBridge 157:e7ca05fa8600 1751 }
AnnaBridge 157:e7ca05fa8600 1752
AnnaBridge 157:e7ca05fa8600 1753 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1754 {
AnnaBridge 157:e7ca05fa8600 1755 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1756
AnnaBridge 157:e7ca05fa8600 1757 __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1758 return(result);
AnnaBridge 157:e7ca05fa8600 1759 }
AnnaBridge 157:e7ca05fa8600 1760
AnnaBridge 157:e7ca05fa8600 1761 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1762 {
AnnaBridge 157:e7ca05fa8600 1763 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1764
AnnaBridge 157:e7ca05fa8600 1765 __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1766 return(result);
AnnaBridge 157:e7ca05fa8600 1767 }
AnnaBridge 157:e7ca05fa8600 1768
AnnaBridge 157:e7ca05fa8600 1769 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1770 {
AnnaBridge 157:e7ca05fa8600 1771 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1772
AnnaBridge 157:e7ca05fa8600 1773 __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1774 return(result);
AnnaBridge 157:e7ca05fa8600 1775 }
AnnaBridge 157:e7ca05fa8600 1776
AnnaBridge 157:e7ca05fa8600 1777 __attribute__((always_inline)) __STATIC_INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1778 {
AnnaBridge 157:e7ca05fa8600 1779 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1780
AnnaBridge 157:e7ca05fa8600 1781 __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1782 return(result);
AnnaBridge 157:e7ca05fa8600 1783 }
AnnaBridge 157:e7ca05fa8600 1784
AnnaBridge 157:e7ca05fa8600 1785 #define __SSAT16(ARG1,ARG2) \
AnnaBridge 157:e7ca05fa8600 1786 ({ \
AnnaBridge 157:e7ca05fa8600 1787 int32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 157:e7ca05fa8600 1788 __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 157:e7ca05fa8600 1789 __RES; \
AnnaBridge 157:e7ca05fa8600 1790 })
AnnaBridge 157:e7ca05fa8600 1791
AnnaBridge 157:e7ca05fa8600 1792 #define __USAT16(ARG1,ARG2) \
AnnaBridge 157:e7ca05fa8600 1793 ({ \
AnnaBridge 157:e7ca05fa8600 1794 uint32_t __RES, __ARG1 = (ARG1); \
AnnaBridge 157:e7ca05fa8600 1795 __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
AnnaBridge 157:e7ca05fa8600 1796 __RES; \
AnnaBridge 157:e7ca05fa8600 1797 })
AnnaBridge 157:e7ca05fa8600 1798
AnnaBridge 157:e7ca05fa8600 1799 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTB16(uint32_t op1)
AnnaBridge 157:e7ca05fa8600 1800 {
AnnaBridge 157:e7ca05fa8600 1801 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1802
AnnaBridge 157:e7ca05fa8600 1803 __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 157:e7ca05fa8600 1804 return(result);
AnnaBridge 157:e7ca05fa8600 1805 }
AnnaBridge 157:e7ca05fa8600 1806
AnnaBridge 157:e7ca05fa8600 1807 __attribute__((always_inline)) __STATIC_INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1808 {
AnnaBridge 157:e7ca05fa8600 1809 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1810
AnnaBridge 157:e7ca05fa8600 1811 __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1812 return(result);
AnnaBridge 157:e7ca05fa8600 1813 }
AnnaBridge 157:e7ca05fa8600 1814
AnnaBridge 157:e7ca05fa8600 1815 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTB16(uint32_t op1)
AnnaBridge 157:e7ca05fa8600 1816 {
AnnaBridge 157:e7ca05fa8600 1817 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1818
AnnaBridge 157:e7ca05fa8600 1819 __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
AnnaBridge 157:e7ca05fa8600 1820 return(result);
AnnaBridge 157:e7ca05fa8600 1821 }
AnnaBridge 157:e7ca05fa8600 1822
AnnaBridge 157:e7ca05fa8600 1823 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1824 {
AnnaBridge 157:e7ca05fa8600 1825 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1826
AnnaBridge 157:e7ca05fa8600 1827 __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1828 return(result);
AnnaBridge 157:e7ca05fa8600 1829 }
AnnaBridge 157:e7ca05fa8600 1830
AnnaBridge 157:e7ca05fa8600 1831 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1832 {
AnnaBridge 157:e7ca05fa8600 1833 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1834
AnnaBridge 157:e7ca05fa8600 1835 __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1836 return(result);
AnnaBridge 157:e7ca05fa8600 1837 }
AnnaBridge 157:e7ca05fa8600 1838
AnnaBridge 157:e7ca05fa8600 1839 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1840 {
AnnaBridge 157:e7ca05fa8600 1841 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1842
AnnaBridge 157:e7ca05fa8600 1843 __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1844 return(result);
AnnaBridge 157:e7ca05fa8600 1845 }
AnnaBridge 157:e7ca05fa8600 1846
AnnaBridge 157:e7ca05fa8600 1847 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1848 {
AnnaBridge 157:e7ca05fa8600 1849 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1850
AnnaBridge 157:e7ca05fa8600 1851 __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1852 return(result);
AnnaBridge 157:e7ca05fa8600 1853 }
AnnaBridge 157:e7ca05fa8600 1854
AnnaBridge 157:e7ca05fa8600 1855 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1856 {
AnnaBridge 157:e7ca05fa8600 1857 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1858
AnnaBridge 157:e7ca05fa8600 1859 __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1860 return(result);
AnnaBridge 157:e7ca05fa8600 1861 }
AnnaBridge 157:e7ca05fa8600 1862
AnnaBridge 157:e7ca05fa8600 1863 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1864 {
AnnaBridge 157:e7ca05fa8600 1865 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1866 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1867 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1868 } llr;
AnnaBridge 157:e7ca05fa8600 1869 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1870
AnnaBridge 157:e7ca05fa8600 1871 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1872 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1873 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1874 __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1875 #endif
AnnaBridge 157:e7ca05fa8600 1876
AnnaBridge 157:e7ca05fa8600 1877 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1878 }
AnnaBridge 157:e7ca05fa8600 1879
AnnaBridge 157:e7ca05fa8600 1880 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1881 {
AnnaBridge 157:e7ca05fa8600 1882 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1883 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1884 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1885 } llr;
AnnaBridge 157:e7ca05fa8600 1886 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1887
AnnaBridge 157:e7ca05fa8600 1888 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1889 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1890 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1891 __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1892 #endif
AnnaBridge 157:e7ca05fa8600 1893
AnnaBridge 157:e7ca05fa8600 1894 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1895 }
AnnaBridge 157:e7ca05fa8600 1896
AnnaBridge 157:e7ca05fa8600 1897 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1898 {
AnnaBridge 157:e7ca05fa8600 1899 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1900
AnnaBridge 157:e7ca05fa8600 1901 __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1902 return(result);
AnnaBridge 157:e7ca05fa8600 1903 }
AnnaBridge 157:e7ca05fa8600 1904
AnnaBridge 157:e7ca05fa8600 1905 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1906 {
AnnaBridge 157:e7ca05fa8600 1907 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1908
AnnaBridge 157:e7ca05fa8600 1909 __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1910 return(result);
AnnaBridge 157:e7ca05fa8600 1911 }
AnnaBridge 157:e7ca05fa8600 1912
AnnaBridge 157:e7ca05fa8600 1913 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1914 {
AnnaBridge 157:e7ca05fa8600 1915 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1916
AnnaBridge 157:e7ca05fa8600 1917 __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1918 return(result);
AnnaBridge 157:e7ca05fa8600 1919 }
AnnaBridge 157:e7ca05fa8600 1920
AnnaBridge 157:e7ca05fa8600 1921 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
AnnaBridge 157:e7ca05fa8600 1922 {
AnnaBridge 157:e7ca05fa8600 1923 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1924
AnnaBridge 157:e7ca05fa8600 1925 __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 1926 return(result);
AnnaBridge 157:e7ca05fa8600 1927 }
AnnaBridge 157:e7ca05fa8600 1928
AnnaBridge 157:e7ca05fa8600 1929 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1930 {
AnnaBridge 157:e7ca05fa8600 1931 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1932 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1933 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1934 } llr;
AnnaBridge 157:e7ca05fa8600 1935 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1936
AnnaBridge 157:e7ca05fa8600 1937 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1938 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1939 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1940 __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1941 #endif
AnnaBridge 157:e7ca05fa8600 1942
AnnaBridge 157:e7ca05fa8600 1943 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1944 }
AnnaBridge 157:e7ca05fa8600 1945
AnnaBridge 157:e7ca05fa8600 1946 __attribute__((always_inline)) __STATIC_INLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc)
AnnaBridge 157:e7ca05fa8600 1947 {
AnnaBridge 157:e7ca05fa8600 1948 union llreg_u{
AnnaBridge 157:e7ca05fa8600 1949 uint32_t w32[2];
AnnaBridge 157:e7ca05fa8600 1950 uint64_t w64;
AnnaBridge 157:e7ca05fa8600 1951 } llr;
AnnaBridge 157:e7ca05fa8600 1952 llr.w64 = acc;
AnnaBridge 157:e7ca05fa8600 1953
AnnaBridge 157:e7ca05fa8600 1954 #ifndef __ARMEB__ /* Little endian */
AnnaBridge 157:e7ca05fa8600 1955 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) );
AnnaBridge 157:e7ca05fa8600 1956 #else /* Big endian */
AnnaBridge 157:e7ca05fa8600 1957 __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) );
AnnaBridge 157:e7ca05fa8600 1958 #endif
AnnaBridge 157:e7ca05fa8600 1959
AnnaBridge 157:e7ca05fa8600 1960 return(llr.w64);
AnnaBridge 157:e7ca05fa8600 1961 }
AnnaBridge 157:e7ca05fa8600 1962
AnnaBridge 157:e7ca05fa8600 1963 __attribute__((always_inline)) __STATIC_INLINE uint32_t __SEL (uint32_t op1, uint32_t op2)
AnnaBridge 157:e7ca05fa8600 1964 {
AnnaBridge 157:e7ca05fa8600 1965 uint32_t result;
AnnaBridge 157:e7ca05fa8600 1966
AnnaBridge 157:e7ca05fa8600 1967 __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1968 return(result);
AnnaBridge 157:e7ca05fa8600 1969 }
AnnaBridge 157:e7ca05fa8600 1970
AnnaBridge 157:e7ca05fa8600 1971 __attribute__((always_inline)) __STATIC_INLINE int32_t __QADD( int32_t op1, int32_t op2)
AnnaBridge 157:e7ca05fa8600 1972 {
AnnaBridge 157:e7ca05fa8600 1973 int32_t result;
AnnaBridge 157:e7ca05fa8600 1974
AnnaBridge 157:e7ca05fa8600 1975 __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1976 return(result);
AnnaBridge 157:e7ca05fa8600 1977 }
AnnaBridge 157:e7ca05fa8600 1978
AnnaBridge 157:e7ca05fa8600 1979 __attribute__((always_inline)) __STATIC_INLINE int32_t __QSUB( int32_t op1, int32_t op2)
AnnaBridge 157:e7ca05fa8600 1980 {
AnnaBridge 157:e7ca05fa8600 1981 int32_t result;
AnnaBridge 157:e7ca05fa8600 1982
AnnaBridge 157:e7ca05fa8600 1983 __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
AnnaBridge 157:e7ca05fa8600 1984 return(result);
AnnaBridge 157:e7ca05fa8600 1985 }
AnnaBridge 157:e7ca05fa8600 1986
AnnaBridge 157:e7ca05fa8600 1987 #if 0
AnnaBridge 157:e7ca05fa8600 1988 #define __PKHBT(ARG1,ARG2,ARG3) \
AnnaBridge 157:e7ca05fa8600 1989 ({ \
AnnaBridge 157:e7ca05fa8600 1990 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 157:e7ca05fa8600 1991 __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 157:e7ca05fa8600 1992 __RES; \
AnnaBridge 157:e7ca05fa8600 1993 })
AnnaBridge 157:e7ca05fa8600 1994
AnnaBridge 157:e7ca05fa8600 1995 #define __PKHTB(ARG1,ARG2,ARG3) \
AnnaBridge 157:e7ca05fa8600 1996 ({ \
AnnaBridge 157:e7ca05fa8600 1997 uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
AnnaBridge 157:e7ca05fa8600 1998 if (ARG3 == 0) \
AnnaBridge 157:e7ca05fa8600 1999 __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \
AnnaBridge 157:e7ca05fa8600 2000 else \
AnnaBridge 157:e7ca05fa8600 2001 __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \
AnnaBridge 157:e7ca05fa8600 2002 __RES; \
AnnaBridge 157:e7ca05fa8600 2003 })
AnnaBridge 157:e7ca05fa8600 2004 #endif
AnnaBridge 157:e7ca05fa8600 2005
AnnaBridge 157:e7ca05fa8600 2006 #define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \
AnnaBridge 157:e7ca05fa8600 2007 ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) )
AnnaBridge 157:e7ca05fa8600 2008
AnnaBridge 157:e7ca05fa8600 2009 #define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
AnnaBridge 157:e7ca05fa8600 2010 ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
AnnaBridge 157:e7ca05fa8600 2011
AnnaBridge 157:e7ca05fa8600 2012 __attribute__((always_inline)) __STATIC_INLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
AnnaBridge 157:e7ca05fa8600 2013 {
AnnaBridge 157:e7ca05fa8600 2014 int32_t result;
AnnaBridge 157:e7ca05fa8600 2015
AnnaBridge 157:e7ca05fa8600 2016 __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
AnnaBridge 157:e7ca05fa8600 2017 return(result);
AnnaBridge 157:e7ca05fa8600 2018 }
AnnaBridge 157:e7ca05fa8600 2019
AnnaBridge 157:e7ca05fa8600 2020 #endif /* (__ARM_FEATURE_DSP == 1) */
AnnaBridge 157:e7ca05fa8600 2021 /*@} end of group CMSIS_SIMD_intrinsics */
AnnaBridge 157:e7ca05fa8600 2022
AnnaBridge 157:e7ca05fa8600 2023
AnnaBridge 157:e7ca05fa8600 2024 #pragma GCC diagnostic pop
AnnaBridge 157:e7ca05fa8600 2025
AnnaBridge 157:e7ca05fa8600 2026 #endif /* __CMSIS_GCC_H */