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TARGET_EFM32WG_STK3800/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/efm32wg900f256.h@166:5aab5a7997ee, 2018-04-20 (annotated)

Committer:
Anna Bridge
Date:
Fri Apr 20 11:08:29 2018 +0100
Revision:
166:5aab5a7997ee
Parent:
156:ff21514d8981 
Updating mbed 2 version number

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 156:ff21514d8981 1 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 2 * @file efm32wg900f256.h
AnnaBridge 156:ff21514d8981 3 * @brief CMSIS Cortex-M Peripheral Access Layer Header File
AnnaBridge 156:ff21514d8981 4 * for EFM32WG900F256
AnnaBridge 156:ff21514d8981 5 * @version 5.1.2
AnnaBridge 156:ff21514d8981 6 ******************************************************************************
AnnaBridge 156:ff21514d8981 7 * @section License
AnnaBridge 156:ff21514d8981 8 * <b>Copyright 2017 Silicon Laboratories, Inc. http://www.silabs.com</b>
AnnaBridge 156:ff21514d8981 9 ******************************************************************************
AnnaBridge 156:ff21514d8981 10 *
AnnaBridge 156:ff21514d8981 11 * Permission is granted to anyone to use this software for any purpose,
AnnaBridge 156:ff21514d8981 12 * including commercial applications, and to alter it and redistribute it
AnnaBridge 156:ff21514d8981 13 * freely, subject to the following restrictions:
AnnaBridge 156:ff21514d8981 14 *
AnnaBridge 156:ff21514d8981 15 * 1. The origin of this software must not be misrepresented; you must not
AnnaBridge 156:ff21514d8981 16 * claim that you wrote the original software.@n
AnnaBridge 156:ff21514d8981 17 * 2. Altered source versions must be plainly marked as such, and must not be
AnnaBridge 156:ff21514d8981 18 * misrepresented as being the original software.@n
AnnaBridge 156:ff21514d8981 19 * 3. This notice may not be removed or altered from any source distribution.
AnnaBridge 156:ff21514d8981 20 *
AnnaBridge 156:ff21514d8981 21 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
AnnaBridge 156:ff21514d8981 22 * has no obligation to support this Software. Silicon Laboratories, Inc. is
AnnaBridge 156:ff21514d8981 23 * providing the Software "AS IS", with no express or implied warranties of any
AnnaBridge 156:ff21514d8981 24 * kind, including, but not limited to, any implied warranties of
AnnaBridge 156:ff21514d8981 25 * merchantability or fitness for any particular purpose or warranties against
AnnaBridge 156:ff21514d8981 26 * infringement of any proprietary rights of a third party.
AnnaBridge 156:ff21514d8981 27 *
AnnaBridge 156:ff21514d8981 28 * Silicon Laboratories, Inc. will not be liable for any consequential,
AnnaBridge 156:ff21514d8981 29 * incidental, or special damages, or any other relief, or for any claim by
AnnaBridge 156:ff21514d8981 30 * any third party, arising from your use of this Software.
AnnaBridge 156:ff21514d8981 31 *
AnnaBridge 156:ff21514d8981 32 *****************************************************************************/
AnnaBridge 156:ff21514d8981 33
AnnaBridge 156:ff21514d8981 34 #ifndef EFM32WG900F256_H
AnnaBridge 156:ff21514d8981 35 #define EFM32WG900F256_H
AnnaBridge 156:ff21514d8981 36
AnnaBridge 156:ff21514d8981 37 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 38 extern "C" {
AnnaBridge 156:ff21514d8981 39 #endif
AnnaBridge 156:ff21514d8981 40
AnnaBridge 156:ff21514d8981 41 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 42 * @addtogroup Parts
AnnaBridge 156:ff21514d8981 43 * @{
AnnaBridge 156:ff21514d8981 44 *****************************************************************************/
AnnaBridge 156:ff21514d8981 45
AnnaBridge 156:ff21514d8981 46 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 47 * @defgroup EFM32WG900F256 EFM32WG900F256
AnnaBridge 156:ff21514d8981 48 * @{
AnnaBridge 156:ff21514d8981 49 *****************************************************************************/
AnnaBridge 156:ff21514d8981 50
AnnaBridge 156:ff21514d8981 51 /** Interrupt Number Definition */
AnnaBridge 156:ff21514d8981 52 typedef enum IRQn
AnnaBridge 156:ff21514d8981 53 {
AnnaBridge 156:ff21514d8981 54 /****** Cortex-M4 Processor Exceptions Numbers ********************************************/
AnnaBridge 156:ff21514d8981 55 NonMaskableInt_IRQn = -14, /*!< -14 Cortex-M4 Non Maskable Interrupt */
AnnaBridge 156:ff21514d8981 56 HardFault_IRQn = -13, /*!< -13 Cortex-M4 Hard Fault Interrupt */
AnnaBridge 156:ff21514d8981 57 MemoryManagement_IRQn = -12, /*!< -12 Cortex-M4 Memory Management Interrupt */
AnnaBridge 156:ff21514d8981 58 BusFault_IRQn = -11, /*!< -11 Cortex-M4 Bus Fault Interrupt */
AnnaBridge 156:ff21514d8981 59 UsageFault_IRQn = -10, /*!< -10 Cortex-M4 Usage Fault Interrupt */
AnnaBridge 156:ff21514d8981 60 SVCall_IRQn = -5, /*!< -5 Cortex-M4 SV Call Interrupt */
AnnaBridge 156:ff21514d8981 61 DebugMonitor_IRQn = -4, /*!< -4 Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 156:ff21514d8981 62 PendSV_IRQn = -2, /*!< -2 Cortex-M4 Pend SV Interrupt */
AnnaBridge 156:ff21514d8981 63 SysTick_IRQn = -1, /*!< -1 Cortex-M4 System Tick Interrupt */
AnnaBridge 156:ff21514d8981 64
AnnaBridge 156:ff21514d8981 65 /****** EFM32WG Peripheral Interrupt Numbers **********************************************/
AnnaBridge 156:ff21514d8981 66 DMA_IRQn = 0, /*!< 0 EFM32 DMA Interrupt */
AnnaBridge 156:ff21514d8981 67 GPIO_EVEN_IRQn = 1, /*!< 1 EFM32 GPIO_EVEN Interrupt */
AnnaBridge 156:ff21514d8981 68 TIMER0_IRQn = 2, /*!< 2 EFM32 TIMER0 Interrupt */
AnnaBridge 156:ff21514d8981 69 USART0_RX_IRQn = 3, /*!< 3 EFM32 USART0_RX Interrupt */
AnnaBridge 156:ff21514d8981 70 USART0_TX_IRQn = 4, /*!< 4 EFM32 USART0_TX Interrupt */
AnnaBridge 156:ff21514d8981 71 USB_IRQn = 5, /*!< 5 EFM32 USB Interrupt */
AnnaBridge 156:ff21514d8981 72 ACMP0_IRQn = 6, /*!< 6 EFM32 ACMP0 Interrupt */
AnnaBridge 156:ff21514d8981 73 ADC0_IRQn = 7, /*!< 7 EFM32 ADC0 Interrupt */
AnnaBridge 156:ff21514d8981 74 DAC0_IRQn = 8, /*!< 8 EFM32 DAC0 Interrupt */
AnnaBridge 156:ff21514d8981 75 I2C0_IRQn = 9, /*!< 9 EFM32 I2C0 Interrupt */
AnnaBridge 156:ff21514d8981 76 I2C1_IRQn = 10, /*!< 10 EFM32 I2C1 Interrupt */
AnnaBridge 156:ff21514d8981 77 GPIO_ODD_IRQn = 11, /*!< 11 EFM32 GPIO_ODD Interrupt */
AnnaBridge 156:ff21514d8981 78 TIMER1_IRQn = 12, /*!< 12 EFM32 TIMER1 Interrupt */
AnnaBridge 156:ff21514d8981 79 TIMER2_IRQn = 13, /*!< 13 EFM32 TIMER2 Interrupt */
AnnaBridge 156:ff21514d8981 80 TIMER3_IRQn = 14, /*!< 14 EFM32 TIMER3 Interrupt */
AnnaBridge 156:ff21514d8981 81 USART1_RX_IRQn = 15, /*!< 15 EFM32 USART1_RX Interrupt */
AnnaBridge 156:ff21514d8981 82 USART1_TX_IRQn = 16, /*!< 16 EFM32 USART1_TX Interrupt */
AnnaBridge 156:ff21514d8981 83 LESENSE_IRQn = 17, /*!< 17 EFM32 LESENSE Interrupt */
AnnaBridge 156:ff21514d8981 84 USART2_RX_IRQn = 18, /*!< 18 EFM32 USART2_RX Interrupt */
AnnaBridge 156:ff21514d8981 85 USART2_TX_IRQn = 19, /*!< 19 EFM32 USART2_TX Interrupt */
AnnaBridge 156:ff21514d8981 86 UART0_RX_IRQn = 20, /*!< 20 EFM32 UART0_RX Interrupt */
AnnaBridge 156:ff21514d8981 87 UART0_TX_IRQn = 21, /*!< 21 EFM32 UART0_TX Interrupt */
AnnaBridge 156:ff21514d8981 88 UART1_RX_IRQn = 22, /*!< 22 EFM32 UART1_RX Interrupt */
AnnaBridge 156:ff21514d8981 89 UART1_TX_IRQn = 23, /*!< 23 EFM32 UART1_TX Interrupt */
AnnaBridge 156:ff21514d8981 90 LEUART0_IRQn = 24, /*!< 24 EFM32 LEUART0 Interrupt */
AnnaBridge 156:ff21514d8981 91 LEUART1_IRQn = 25, /*!< 25 EFM32 LEUART1 Interrupt */
AnnaBridge 156:ff21514d8981 92 LETIMER0_IRQn = 26, /*!< 26 EFM32 LETIMER0 Interrupt */
AnnaBridge 156:ff21514d8981 93 PCNT0_IRQn = 27, /*!< 27 EFM32 PCNT0 Interrupt */
AnnaBridge 156:ff21514d8981 94 PCNT1_IRQn = 28, /*!< 28 EFM32 PCNT1 Interrupt */
AnnaBridge 156:ff21514d8981 95 PCNT2_IRQn = 29, /*!< 29 EFM32 PCNT2 Interrupt */
AnnaBridge 156:ff21514d8981 96 RTC_IRQn = 30, /*!< 30 EFM32 RTC Interrupt */
AnnaBridge 156:ff21514d8981 97 BURTC_IRQn = 31, /*!< 31 EFM32 BURTC Interrupt */
AnnaBridge 156:ff21514d8981 98 CMU_IRQn = 32, /*!< 32 EFM32 CMU Interrupt */
AnnaBridge 156:ff21514d8981 99 VCMP_IRQn = 33, /*!< 33 EFM32 VCMP Interrupt */
AnnaBridge 156:ff21514d8981 100 LCD_IRQn = 34, /*!< 34 EFM32 LCD Interrupt */
AnnaBridge 156:ff21514d8981 101 MSC_IRQn = 35, /*!< 35 EFM32 MSC Interrupt */
AnnaBridge 156:ff21514d8981 102 AES_IRQn = 36, /*!< 36 EFM32 AES Interrupt */
AnnaBridge 156:ff21514d8981 103 EBI_IRQn = 37, /*!< 37 EFM32 EBI Interrupt */
AnnaBridge 156:ff21514d8981 104 EMU_IRQn = 38, /*!< 38 EFM32 EMU Interrupt */
AnnaBridge 156:ff21514d8981 105 FPUEH_IRQn = 39, /*!< 39 EFM32 FPUEH Interrupt */
AnnaBridge 156:ff21514d8981 106 } IRQn_Type;
AnnaBridge 156:ff21514d8981 107
AnnaBridge 156:ff21514d8981 108 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 109 * @defgroup EFM32WG900F256_Core EFM32WG900F256 Core
AnnaBridge 156:ff21514d8981 110 * @{
AnnaBridge 156:ff21514d8981 111 * @brief Processor and Core Peripheral Section
AnnaBridge 156:ff21514d8981 112 *****************************************************************************/
AnnaBridge 156:ff21514d8981 113 #define __MPU_PRESENT 1 /**< Presence of MPU */
AnnaBridge 156:ff21514d8981 114 #define __FPU_PRESENT 1 /**< Presence of FPU */
AnnaBridge 156:ff21514d8981 115 #define __VTOR_PRESENT 1 /**< Presence of VTOR register in SCB */
AnnaBridge 156:ff21514d8981 116 #define __NVIC_PRIO_BITS 3 /**< NVIC interrupt priority bits */
AnnaBridge 156:ff21514d8981 117 #define __Vendor_SysTickConfig 0 /**< Is 1 if different SysTick counter is used */
AnnaBridge 156:ff21514d8981 118
AnnaBridge 156:ff21514d8981 119 /** @} End of group EFM32WG900F256_Core */
AnnaBridge 156:ff21514d8981 120
AnnaBridge 156:ff21514d8981 121 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 122 * @defgroup EFM32WG900F256_Part EFM32WG900F256 Part
AnnaBridge 156:ff21514d8981 123 * @{
AnnaBridge 156:ff21514d8981 124 ******************************************************************************/
AnnaBridge 156:ff21514d8981 125
AnnaBridge 156:ff21514d8981 126 /** Part family */
AnnaBridge 156:ff21514d8981 127 #define _EFM32_WONDER_FAMILY 1 /**< Wonder Gecko EFM32WG MCU Family */
AnnaBridge 156:ff21514d8981 128 #define _EFM_DEVICE /**< Silicon Labs EFM-type microcontroller */
AnnaBridge 156:ff21514d8981 129 #define _SILICON_LABS_32B_SERIES_0 /**< Silicon Labs series number */
AnnaBridge 156:ff21514d8981 130 #define _SILICON_LABS_32B_SERIES 0 /**< Silicon Labs series number */
AnnaBridge 156:ff21514d8981 131 #define _SILICON_LABS_GECKO_INTERNAL_SDID 74 /** Silicon Labs internal use only, may change any time */
AnnaBridge 156:ff21514d8981 132 #define _SILICON_LABS_GECKO_INTERNAL_SDID_74 /** Silicon Labs internal use only, may change any time */
AnnaBridge 156:ff21514d8981 133 #define _SILICON_LABS_32B_PLATFORM_1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 156:ff21514d8981 134 #define _SILICON_LABS_32B_PLATFORM 1 /**< @deprecated Silicon Labs platform name */
AnnaBridge 156:ff21514d8981 135
AnnaBridge 156:ff21514d8981 136 /* If part number is not defined as compiler option, define it */
AnnaBridge 156:ff21514d8981 137 #if !defined(EFM32WG900F256)
AnnaBridge 156:ff21514d8981 138 #define EFM32WG900F256 1 /**< Wonder Gecko Part */
AnnaBridge 156:ff21514d8981 139 #endif
AnnaBridge 156:ff21514d8981 140
AnnaBridge 156:ff21514d8981 141 /** Configure part number */
AnnaBridge 156:ff21514d8981 142 #define PART_NUMBER "EFM32WG900F256" /**< Part Number */
AnnaBridge 156:ff21514d8981 143
AnnaBridge 156:ff21514d8981 144 /** Memory Base addresses and limits */
AnnaBridge 156:ff21514d8981 145 #define FLASH_MEM_BASE ((uint32_t) 0x0UL) /**< FLASH base address */
AnnaBridge 156:ff21514d8981 146 #define FLASH_MEM_SIZE ((uint32_t) 0x10000000UL) /**< FLASH available address space */
AnnaBridge 156:ff21514d8981 147 #define FLASH_MEM_END ((uint32_t) 0xFFFFFFFUL) /**< FLASH end address */
AnnaBridge 156:ff21514d8981 148 #define FLASH_MEM_BITS ((uint32_t) 0x28UL) /**< FLASH used bits */
AnnaBridge 156:ff21514d8981 149 #define AES_MEM_BASE ((uint32_t) 0x400E0000UL) /**< AES base address */
AnnaBridge 156:ff21514d8981 150 #define AES_MEM_SIZE ((uint32_t) 0x400UL) /**< AES available address space */
AnnaBridge 156:ff21514d8981 151 #define AES_MEM_END ((uint32_t) 0x400E03FFUL) /**< AES end address */
AnnaBridge 156:ff21514d8981 152 #define AES_MEM_BITS ((uint32_t) 0x10UL) /**< AES used bits */
AnnaBridge 156:ff21514d8981 153 #define USBC_MEM_BASE ((uint32_t) 0x40100000UL) /**< USBC base address */
AnnaBridge 156:ff21514d8981 154 #define USBC_MEM_SIZE ((uint32_t) 0x40000UL) /**< USBC available address space */
AnnaBridge 156:ff21514d8981 155 #define USBC_MEM_END ((uint32_t) 0x4013FFFFUL) /**< USBC end address */
AnnaBridge 156:ff21514d8981 156 #define USBC_MEM_BITS ((uint32_t) 0x18UL) /**< USBC used bits */
AnnaBridge 156:ff21514d8981 157 #define EBI_CODE_MEM_BASE ((uint32_t) 0x12000000UL) /**< EBI_CODE base address */
AnnaBridge 156:ff21514d8981 158 #define EBI_CODE_MEM_SIZE ((uint32_t) 0xE000000UL) /**< EBI_CODE available address space */
AnnaBridge 156:ff21514d8981 159 #define EBI_CODE_MEM_END ((uint32_t) 0x1FFFFFFFUL) /**< EBI_CODE end address */
AnnaBridge 156:ff21514d8981 160 #define EBI_CODE_MEM_BITS ((uint32_t) 0x28UL) /**< EBI_CODE used bits */
AnnaBridge 156:ff21514d8981 161 #define PER_MEM_BASE ((uint32_t) 0x40000000UL) /**< PER base address */
AnnaBridge 156:ff21514d8981 162 #define PER_MEM_SIZE ((uint32_t) 0xE0000UL) /**< PER available address space */
AnnaBridge 156:ff21514d8981 163 #define PER_MEM_END ((uint32_t) 0x400DFFFFUL) /**< PER end address */
AnnaBridge 156:ff21514d8981 164 #define PER_MEM_BITS ((uint32_t) 0x20UL) /**< PER used bits */
AnnaBridge 156:ff21514d8981 165 #define RAM_MEM_BASE ((uint32_t) 0x20000000UL) /**< RAM base address */
AnnaBridge 156:ff21514d8981 166 #define RAM_MEM_SIZE ((uint32_t) 0x40000UL) /**< RAM available address space */
AnnaBridge 156:ff21514d8981 167 #define RAM_MEM_END ((uint32_t) 0x2003FFFFUL) /**< RAM end address */
AnnaBridge 156:ff21514d8981 168 #define RAM_MEM_BITS ((uint32_t) 0x18UL) /**< RAM used bits */
AnnaBridge 156:ff21514d8981 169 #define RAM_CODE_MEM_BASE ((uint32_t) 0x10000000UL) /**< RAM_CODE base address */
AnnaBridge 156:ff21514d8981 170 #define RAM_CODE_MEM_SIZE ((uint32_t) 0x20000UL) /**< RAM_CODE available address space */
AnnaBridge 156:ff21514d8981 171 #define RAM_CODE_MEM_END ((uint32_t) 0x1001FFFFUL) /**< RAM_CODE end address */
AnnaBridge 156:ff21514d8981 172 #define RAM_CODE_MEM_BITS ((uint32_t) 0x17UL) /**< RAM_CODE used bits */
AnnaBridge 156:ff21514d8981 173 #define EBI_MEM_BASE ((uint32_t) 0x80000000UL) /**< EBI base address */
AnnaBridge 156:ff21514d8981 174 #define EBI_MEM_SIZE ((uint32_t) 0x40000000UL) /**< EBI available address space */
AnnaBridge 156:ff21514d8981 175 #define EBI_MEM_END ((uint32_t) 0xBFFFFFFFUL) /**< EBI end address */
AnnaBridge 156:ff21514d8981 176 #define EBI_MEM_BITS ((uint32_t) 0x30UL) /**< EBI used bits */
AnnaBridge 156:ff21514d8981 177
AnnaBridge 156:ff21514d8981 178 /** Bit banding area */
AnnaBridge 156:ff21514d8981 179 #define BITBAND_PER_BASE ((uint32_t) 0x42000000UL) /**< Peripheral Address Space bit-band area */
AnnaBridge 156:ff21514d8981 180 #define BITBAND_RAM_BASE ((uint32_t) 0x22000000UL) /**< SRAM Address Space bit-band area */
AnnaBridge 156:ff21514d8981 181
AnnaBridge 156:ff21514d8981 182 /** Flash and SRAM limits for EFM32WG900F256 */
AnnaBridge 156:ff21514d8981 183 #define FLASH_BASE (0x00000000UL) /**< Flash Base Address */
AnnaBridge 156:ff21514d8981 184 #define FLASH_SIZE (0x00040000UL) /**< Available Flash Memory */
AnnaBridge 156:ff21514d8981 185 #define FLASH_PAGE_SIZE 2048 /**< Flash Memory page size */
AnnaBridge 156:ff21514d8981 186 #define SRAM_BASE (0x20000000UL) /**< SRAM Base Address */
AnnaBridge 156:ff21514d8981 187 #define SRAM_SIZE (0x00008000UL) /**< Available SRAM Memory */
AnnaBridge 156:ff21514d8981 188 #define __CM4_REV 0x001 /**< Cortex-M4 Core revision r0p1 */
AnnaBridge 156:ff21514d8981 189 #define PRS_CHAN_COUNT 12 /**< Number of PRS channels */
AnnaBridge 156:ff21514d8981 190 #define DMA_CHAN_COUNT 12 /**< Number of DMA channels */
AnnaBridge 156:ff21514d8981 191 #define EXT_IRQ_COUNT 40 /**< Number of External (NVIC) interrupts */
AnnaBridge 156:ff21514d8981 192
AnnaBridge 156:ff21514d8981 193 /** AF channels connect the different on-chip peripherals with the af-mux */
AnnaBridge 156:ff21514d8981 194 #define AFCHAN_MAX 163
AnnaBridge 156:ff21514d8981 195 #define AFCHANLOC_MAX 7
AnnaBridge 156:ff21514d8981 196 /** Analog AF channels */
AnnaBridge 156:ff21514d8981 197 #define AFACHAN_MAX 53
AnnaBridge 156:ff21514d8981 198
AnnaBridge 156:ff21514d8981 199 /* Part number capabilities */
AnnaBridge 156:ff21514d8981 200
AnnaBridge 156:ff21514d8981 201 #define USART_PRESENT /**< USART is available in this part */
AnnaBridge 156:ff21514d8981 202 #define USART_COUNT 3 /**< 3 USARTs available */
AnnaBridge 156:ff21514d8981 203 #define UART_PRESENT /**< UART is available in this part */
AnnaBridge 156:ff21514d8981 204 #define UART_COUNT 2 /**< 2 UARTs available */
AnnaBridge 156:ff21514d8981 205 #define TIMER_PRESENT /**< TIMER is available in this part */
AnnaBridge 156:ff21514d8981 206 #define TIMER_COUNT 4 /**< 4 TIMERs available */
AnnaBridge 156:ff21514d8981 207 #define ACMP_PRESENT /**< ACMP is available in this part */
AnnaBridge 156:ff21514d8981 208 #define ACMP_COUNT 2 /**< 2 ACMPs available */
AnnaBridge 156:ff21514d8981 209 #define LEUART_PRESENT /**< LEUART is available in this part */
AnnaBridge 156:ff21514d8981 210 #define LEUART_COUNT 2 /**< 2 LEUARTs available */
AnnaBridge 156:ff21514d8981 211 #define LETIMER_PRESENT /**< LETIMER is available in this part */
AnnaBridge 156:ff21514d8981 212 #define LETIMER_COUNT 1 /**< 1 LETIMERs available */
AnnaBridge 156:ff21514d8981 213 #define PCNT_PRESENT /**< PCNT is available in this part */
AnnaBridge 156:ff21514d8981 214 #define PCNT_COUNT 3 /**< 3 PCNTs available */
AnnaBridge 156:ff21514d8981 215 #define I2C_PRESENT /**< I2C is available in this part */
AnnaBridge 156:ff21514d8981 216 #define I2C_COUNT 2 /**< 2 I2Cs available */
AnnaBridge 156:ff21514d8981 217 #define ADC_PRESENT /**< ADC is available in this part */
AnnaBridge 156:ff21514d8981 218 #define ADC_COUNT 1 /**< 1 ADCs available */
AnnaBridge 156:ff21514d8981 219 #define DAC_PRESENT /**< DAC is available in this part */
AnnaBridge 156:ff21514d8981 220 #define DAC_COUNT 1 /**< 1 DACs available */
AnnaBridge 156:ff21514d8981 221 #define DMA_PRESENT
AnnaBridge 156:ff21514d8981 222 #define DMA_COUNT 1
AnnaBridge 156:ff21514d8981 223 #define AES_PRESENT
AnnaBridge 156:ff21514d8981 224 #define AES_COUNT 1
AnnaBridge 156:ff21514d8981 225 #define USBC_PRESENT
AnnaBridge 156:ff21514d8981 226 #define USBC_COUNT 1
AnnaBridge 156:ff21514d8981 227 #define USB_PRESENT
AnnaBridge 156:ff21514d8981 228 #define USB_COUNT 1
AnnaBridge 156:ff21514d8981 229 #define LE_PRESENT
AnnaBridge 156:ff21514d8981 230 #define LE_COUNT 1
AnnaBridge 156:ff21514d8981 231 #define MSC_PRESENT
AnnaBridge 156:ff21514d8981 232 #define MSC_COUNT 1
AnnaBridge 156:ff21514d8981 233 #define EMU_PRESENT
AnnaBridge 156:ff21514d8981 234 #define EMU_COUNT 1
AnnaBridge 156:ff21514d8981 235 #define RMU_PRESENT
AnnaBridge 156:ff21514d8981 236 #define RMU_COUNT 1
AnnaBridge 156:ff21514d8981 237 #define CMU_PRESENT
AnnaBridge 156:ff21514d8981 238 #define CMU_COUNT 1
AnnaBridge 156:ff21514d8981 239 #define LESENSE_PRESENT
AnnaBridge 156:ff21514d8981 240 #define LESENSE_COUNT 1
AnnaBridge 156:ff21514d8981 241 #define EBI_PRESENT
AnnaBridge 156:ff21514d8981 242 #define EBI_COUNT 1
AnnaBridge 156:ff21514d8981 243 #define FPUEH_PRESENT
AnnaBridge 156:ff21514d8981 244 #define FPUEH_COUNT 1
AnnaBridge 156:ff21514d8981 245 #define RTC_PRESENT
AnnaBridge 156:ff21514d8981 246 #define RTC_COUNT 1
AnnaBridge 156:ff21514d8981 247 #define GPIO_PRESENT
AnnaBridge 156:ff21514d8981 248 #define GPIO_COUNT 1
AnnaBridge 156:ff21514d8981 249 #define VCMP_PRESENT
AnnaBridge 156:ff21514d8981 250 #define VCMP_COUNT 1
AnnaBridge 156:ff21514d8981 251 #define PRS_PRESENT
AnnaBridge 156:ff21514d8981 252 #define PRS_COUNT 1
AnnaBridge 156:ff21514d8981 253 #define OPAMP_PRESENT
AnnaBridge 156:ff21514d8981 254 #define OPAMP_COUNT 1
AnnaBridge 156:ff21514d8981 255 #define BU_PRESENT
AnnaBridge 156:ff21514d8981 256 #define BU_COUNT 1
AnnaBridge 156:ff21514d8981 257 #define LCD_PRESENT
AnnaBridge 156:ff21514d8981 258 #define LCD_COUNT 1
AnnaBridge 156:ff21514d8981 259 #define BURTC_PRESENT
AnnaBridge 156:ff21514d8981 260 #define BURTC_COUNT 1
AnnaBridge 156:ff21514d8981 261 #define HFXTAL_PRESENT
AnnaBridge 156:ff21514d8981 262 #define HFXTAL_COUNT 1
AnnaBridge 156:ff21514d8981 263 #define LFXTAL_PRESENT
AnnaBridge 156:ff21514d8981 264 #define LFXTAL_COUNT 1
AnnaBridge 156:ff21514d8981 265 #define WDOG_PRESENT
AnnaBridge 156:ff21514d8981 266 #define WDOG_COUNT 1
AnnaBridge 156:ff21514d8981 267 #define DBG_PRESENT
AnnaBridge 156:ff21514d8981 268 #define DBG_COUNT 1
AnnaBridge 156:ff21514d8981 269 #define ETM_PRESENT
AnnaBridge 156:ff21514d8981 270 #define ETM_COUNT 1
AnnaBridge 156:ff21514d8981 271 #define BOOTLOADER_PRESENT
AnnaBridge 156:ff21514d8981 272 #define BOOTLOADER_COUNT 1
AnnaBridge 156:ff21514d8981 273 #define ANALOG_PRESENT
AnnaBridge 156:ff21514d8981 274 #define ANALOG_COUNT 1
AnnaBridge 156:ff21514d8981 275
AnnaBridge 156:ff21514d8981 276 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
AnnaBridge 156:ff21514d8981 277 #include "system_efm32wg.h" /* System Header */
AnnaBridge 156:ff21514d8981 278
AnnaBridge 156:ff21514d8981 279 /** @} End of group EFM32WG900F256_Part */
AnnaBridge 156:ff21514d8981 280
AnnaBridge 156:ff21514d8981 281 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 282 * @defgroup EFM32WG900F256_Peripheral_TypeDefs EFM32WG900F256 Peripheral TypeDefs
AnnaBridge 156:ff21514d8981 283 * @{
AnnaBridge 156:ff21514d8981 284 * @brief Device Specific Peripheral Register Structures
AnnaBridge 156:ff21514d8981 285 *****************************************************************************/
AnnaBridge 156:ff21514d8981 286
AnnaBridge 156:ff21514d8981 287 #include "efm32wg_dma_ch.h"
AnnaBridge 156:ff21514d8981 288 #include "efm32wg_dma.h"
AnnaBridge 156:ff21514d8981 289 #include "efm32wg_aes.h"
AnnaBridge 156:ff21514d8981 290 #include "efm32wg_usb_hc.h"
AnnaBridge 156:ff21514d8981 291 #include "efm32wg_usb_diep.h"
AnnaBridge 156:ff21514d8981 292 #include "efm32wg_usb_doep.h"
AnnaBridge 156:ff21514d8981 293 #include "efm32wg_usb.h"
AnnaBridge 156:ff21514d8981 294 #include "efm32wg_msc.h"
AnnaBridge 156:ff21514d8981 295 #include "efm32wg_emu.h"
AnnaBridge 156:ff21514d8981 296 #include "efm32wg_rmu.h"
AnnaBridge 156:ff21514d8981 297 #include "efm32wg_cmu.h"
AnnaBridge 156:ff21514d8981 298 #include "efm32wg_lesense_st.h"
AnnaBridge 156:ff21514d8981 299 #include "efm32wg_lesense_buf.h"
AnnaBridge 156:ff21514d8981 300 #include "efm32wg_lesense_ch.h"
AnnaBridge 156:ff21514d8981 301 #include "efm32wg_lesense.h"
AnnaBridge 156:ff21514d8981 302 #include "efm32wg_ebi.h"
AnnaBridge 156:ff21514d8981 303 #include "efm32wg_fpueh.h"
AnnaBridge 156:ff21514d8981 304 #include "efm32wg_usart.h"
AnnaBridge 156:ff21514d8981 305 #include "efm32wg_timer_cc.h"
AnnaBridge 156:ff21514d8981 306 #include "efm32wg_timer.h"
AnnaBridge 156:ff21514d8981 307 #include "efm32wg_acmp.h"
AnnaBridge 156:ff21514d8981 308 #include "efm32wg_leuart.h"
AnnaBridge 156:ff21514d8981 309 #include "efm32wg_rtc.h"
AnnaBridge 156:ff21514d8981 310 #include "efm32wg_letimer.h"
AnnaBridge 156:ff21514d8981 311 #include "efm32wg_pcnt.h"
AnnaBridge 156:ff21514d8981 312 #include "efm32wg_i2c.h"
AnnaBridge 156:ff21514d8981 313 #include "efm32wg_gpio_p.h"
AnnaBridge 156:ff21514d8981 314 #include "efm32wg_gpio.h"
AnnaBridge 156:ff21514d8981 315 #include "efm32wg_vcmp.h"
AnnaBridge 156:ff21514d8981 316 #include "efm32wg_prs_ch.h"
AnnaBridge 156:ff21514d8981 317 #include "efm32wg_prs.h"
AnnaBridge 156:ff21514d8981 318 #include "efm32wg_adc.h"
AnnaBridge 156:ff21514d8981 319 #include "efm32wg_dac.h"
AnnaBridge 156:ff21514d8981 320 #include "efm32wg_lcd.h"
AnnaBridge 156:ff21514d8981 321 #include "efm32wg_burtc_ret.h"
AnnaBridge 156:ff21514d8981 322 #include "efm32wg_burtc.h"
AnnaBridge 156:ff21514d8981 323 #include "efm32wg_wdog.h"
AnnaBridge 156:ff21514d8981 324 #include "efm32wg_etm.h"
AnnaBridge 156:ff21514d8981 325 #include "efm32wg_dma_descriptor.h"
AnnaBridge 156:ff21514d8981 326 #include "efm32wg_devinfo.h"
AnnaBridge 156:ff21514d8981 327 #include "efm32wg_romtable.h"
AnnaBridge 156:ff21514d8981 328 #include "efm32wg_calibrate.h"
AnnaBridge 156:ff21514d8981 329
AnnaBridge 156:ff21514d8981 330 /** @} End of group EFM32WG900F256_Peripheral_TypeDefs */
AnnaBridge 156:ff21514d8981 331
AnnaBridge 156:ff21514d8981 332 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 333 * @defgroup EFM32WG900F256_Peripheral_Base EFM32WG900F256 Peripheral Memory Map
AnnaBridge 156:ff21514d8981 334 * @{
AnnaBridge 156:ff21514d8981 335 *****************************************************************************/
AnnaBridge 156:ff21514d8981 336
AnnaBridge 156:ff21514d8981 337 #define DMA_BASE (0x400C2000UL) /**< DMA base address */
AnnaBridge 156:ff21514d8981 338 #define AES_BASE (0x400E0000UL) /**< AES base address */
AnnaBridge 156:ff21514d8981 339 #define USB_BASE (0x400C4000UL) /**< USB base address */
AnnaBridge 156:ff21514d8981 340 #define MSC_BASE (0x400C0000UL) /**< MSC base address */
AnnaBridge 156:ff21514d8981 341 #define EMU_BASE (0x400C6000UL) /**< EMU base address */
AnnaBridge 156:ff21514d8981 342 #define RMU_BASE (0x400CA000UL) /**< RMU base address */
AnnaBridge 156:ff21514d8981 343 #define CMU_BASE (0x400C8000UL) /**< CMU base address */
AnnaBridge 156:ff21514d8981 344 #define LESENSE_BASE (0x4008C000UL) /**< LESENSE base address */
AnnaBridge 156:ff21514d8981 345 #define EBI_BASE (0x40008000UL) /**< EBI base address */
AnnaBridge 156:ff21514d8981 346 #define FPUEH_BASE (0x400C1C00UL) /**< FPUEH base address */
AnnaBridge 156:ff21514d8981 347 #define USART0_BASE (0x4000C000UL) /**< USART0 base address */
AnnaBridge 156:ff21514d8981 348 #define USART1_BASE (0x4000C400UL) /**< USART1 base address */
AnnaBridge 156:ff21514d8981 349 #define USART2_BASE (0x4000C800UL) /**< USART2 base address */
AnnaBridge 156:ff21514d8981 350 #define UART0_BASE (0x4000E000UL) /**< UART0 base address */
AnnaBridge 156:ff21514d8981 351 #define UART1_BASE (0x4000E400UL) /**< UART1 base address */
AnnaBridge 156:ff21514d8981 352 #define TIMER0_BASE (0x40010000UL) /**< TIMER0 base address */
AnnaBridge 156:ff21514d8981 353 #define TIMER1_BASE (0x40010400UL) /**< TIMER1 base address */
AnnaBridge 156:ff21514d8981 354 #define TIMER2_BASE (0x40010800UL) /**< TIMER2 base address */
AnnaBridge 156:ff21514d8981 355 #define TIMER3_BASE (0x40010C00UL) /**< TIMER3 base address */
AnnaBridge 156:ff21514d8981 356 #define ACMP0_BASE (0x40001000UL) /**< ACMP0 base address */
AnnaBridge 156:ff21514d8981 357 #define ACMP1_BASE (0x40001400UL) /**< ACMP1 base address */
AnnaBridge 156:ff21514d8981 358 #define LEUART0_BASE (0x40084000UL) /**< LEUART0 base address */
AnnaBridge 156:ff21514d8981 359 #define LEUART1_BASE (0x40084400UL) /**< LEUART1 base address */
AnnaBridge 156:ff21514d8981 360 #define RTC_BASE (0x40080000UL) /**< RTC base address */
AnnaBridge 156:ff21514d8981 361 #define LETIMER0_BASE (0x40082000UL) /**< LETIMER0 base address */
AnnaBridge 156:ff21514d8981 362 #define PCNT0_BASE (0x40086000UL) /**< PCNT0 base address */
AnnaBridge 156:ff21514d8981 363 #define PCNT1_BASE (0x40086400UL) /**< PCNT1 base address */
AnnaBridge 156:ff21514d8981 364 #define PCNT2_BASE (0x40086800UL) /**< PCNT2 base address */
AnnaBridge 156:ff21514d8981 365 #define I2C0_BASE (0x4000A000UL) /**< I2C0 base address */
AnnaBridge 156:ff21514d8981 366 #define I2C1_BASE (0x4000A400UL) /**< I2C1 base address */
AnnaBridge 156:ff21514d8981 367 #define GPIO_BASE (0x40006000UL) /**< GPIO base address */
AnnaBridge 156:ff21514d8981 368 #define VCMP_BASE (0x40000000UL) /**< VCMP base address */
AnnaBridge 156:ff21514d8981 369 #define PRS_BASE (0x400CC000UL) /**< PRS base address */
AnnaBridge 156:ff21514d8981 370 #define ADC0_BASE (0x40002000UL) /**< ADC0 base address */
AnnaBridge 156:ff21514d8981 371 #define DAC0_BASE (0x40004000UL) /**< DAC0 base address */
AnnaBridge 156:ff21514d8981 372 #define LCD_BASE (0x4008A000UL) /**< LCD base address */
AnnaBridge 156:ff21514d8981 373 #define BURTC_BASE (0x40081000UL) /**< BURTC base address */
AnnaBridge 156:ff21514d8981 374 #define WDOG_BASE (0x40088000UL) /**< WDOG base address */
AnnaBridge 156:ff21514d8981 375 #define ETM_BASE (0xE0041000UL) /**< ETM base address */
AnnaBridge 156:ff21514d8981 376 #define CALIBRATE_BASE (0x0FE08000UL) /**< CALIBRATE base address */
AnnaBridge 156:ff21514d8981 377 #define DEVINFO_BASE (0x0FE081B0UL) /**< DEVINFO base address */
AnnaBridge 156:ff21514d8981 378 #define ROMTABLE_BASE (0xE00FFFD0UL) /**< ROMTABLE base address */
AnnaBridge 156:ff21514d8981 379 #define LOCKBITS_BASE (0x0FE04000UL) /**< Lock-bits page base address */
AnnaBridge 156:ff21514d8981 380 #define USERDATA_BASE (0x0FE00000UL) /**< User data page base address */
AnnaBridge 156:ff21514d8981 381
AnnaBridge 156:ff21514d8981 382 /** @} End of group EFM32WG900F256_Peripheral_Base */
AnnaBridge 156:ff21514d8981 383
AnnaBridge 156:ff21514d8981 384 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 385 * @defgroup EFM32WG900F256_Peripheral_Declaration EFM32WG900F256 Peripheral Declarations
AnnaBridge 156:ff21514d8981 386 * @{
AnnaBridge 156:ff21514d8981 387 *****************************************************************************/
AnnaBridge 156:ff21514d8981 388
AnnaBridge 156:ff21514d8981 389 #define DMA ((DMA_TypeDef *) DMA_BASE) /**< DMA base pointer */
AnnaBridge 156:ff21514d8981 390 #define AES ((AES_TypeDef *) AES_BASE) /**< AES base pointer */
AnnaBridge 156:ff21514d8981 391 #define USB ((USB_TypeDef *) USB_BASE) /**< USB base pointer */
AnnaBridge 156:ff21514d8981 392 #define MSC ((MSC_TypeDef *) MSC_BASE) /**< MSC base pointer */
AnnaBridge 156:ff21514d8981 393 #define EMU ((EMU_TypeDef *) EMU_BASE) /**< EMU base pointer */
AnnaBridge 156:ff21514d8981 394 #define RMU ((RMU_TypeDef *) RMU_BASE) /**< RMU base pointer */
AnnaBridge 156:ff21514d8981 395 #define CMU ((CMU_TypeDef *) CMU_BASE) /**< CMU base pointer */
AnnaBridge 156:ff21514d8981 396 #define LESENSE ((LESENSE_TypeDef *) LESENSE_BASE) /**< LESENSE base pointer */
AnnaBridge 156:ff21514d8981 397 #define EBI ((EBI_TypeDef *) EBI_BASE) /**< EBI base pointer */
AnnaBridge 156:ff21514d8981 398 #define FPUEH ((FPUEH_TypeDef *) FPUEH_BASE) /**< FPUEH base pointer */
AnnaBridge 156:ff21514d8981 399 #define USART0 ((USART_TypeDef *) USART0_BASE) /**< USART0 base pointer */
AnnaBridge 156:ff21514d8981 400 #define USART1 ((USART_TypeDef *) USART1_BASE) /**< USART1 base pointer */
AnnaBridge 156:ff21514d8981 401 #define USART2 ((USART_TypeDef *) USART2_BASE) /**< USART2 base pointer */
AnnaBridge 156:ff21514d8981 402 #define UART0 ((USART_TypeDef *) UART0_BASE) /**< UART0 base pointer */
AnnaBridge 156:ff21514d8981 403 #define UART1 ((USART_TypeDef *) UART1_BASE) /**< UART1 base pointer */
AnnaBridge 156:ff21514d8981 404 #define TIMER0 ((TIMER_TypeDef *) TIMER0_BASE) /**< TIMER0 base pointer */
AnnaBridge 156:ff21514d8981 405 #define TIMER1 ((TIMER_TypeDef *) TIMER1_BASE) /**< TIMER1 base pointer */
AnnaBridge 156:ff21514d8981 406 #define TIMER2 ((TIMER_TypeDef *) TIMER2_BASE) /**< TIMER2 base pointer */
AnnaBridge 156:ff21514d8981 407 #define TIMER3 ((TIMER_TypeDef *) TIMER3_BASE) /**< TIMER3 base pointer */
AnnaBridge 156:ff21514d8981 408 #define ACMP0 ((ACMP_TypeDef *) ACMP0_BASE) /**< ACMP0 base pointer */
AnnaBridge 156:ff21514d8981 409 #define ACMP1 ((ACMP_TypeDef *) ACMP1_BASE) /**< ACMP1 base pointer */
AnnaBridge 156:ff21514d8981 410 #define LEUART0 ((LEUART_TypeDef *) LEUART0_BASE) /**< LEUART0 base pointer */
AnnaBridge 156:ff21514d8981 411 #define LEUART1 ((LEUART_TypeDef *) LEUART1_BASE) /**< LEUART1 base pointer */
AnnaBridge 156:ff21514d8981 412 #define RTC ((RTC_TypeDef *) RTC_BASE) /**< RTC base pointer */
AnnaBridge 156:ff21514d8981 413 #define LETIMER0 ((LETIMER_TypeDef *) LETIMER0_BASE) /**< LETIMER0 base pointer */
AnnaBridge 156:ff21514d8981 414 #define PCNT0 ((PCNT_TypeDef *) PCNT0_BASE) /**< PCNT0 base pointer */
AnnaBridge 156:ff21514d8981 415 #define PCNT1 ((PCNT_TypeDef *) PCNT1_BASE) /**< PCNT1 base pointer */
AnnaBridge 156:ff21514d8981 416 #define PCNT2 ((PCNT_TypeDef *) PCNT2_BASE) /**< PCNT2 base pointer */
AnnaBridge 156:ff21514d8981 417 #define I2C0 ((I2C_TypeDef *) I2C0_BASE) /**< I2C0 base pointer */
AnnaBridge 156:ff21514d8981 418 #define I2C1 ((I2C_TypeDef *) I2C1_BASE) /**< I2C1 base pointer */
AnnaBridge 156:ff21514d8981 419 #define GPIO ((GPIO_TypeDef *) GPIO_BASE) /**< GPIO base pointer */
AnnaBridge 156:ff21514d8981 420 #define VCMP ((VCMP_TypeDef *) VCMP_BASE) /**< VCMP base pointer */
AnnaBridge 156:ff21514d8981 421 #define PRS ((PRS_TypeDef *) PRS_BASE) /**< PRS base pointer */
AnnaBridge 156:ff21514d8981 422 #define ADC0 ((ADC_TypeDef *) ADC0_BASE) /**< ADC0 base pointer */
AnnaBridge 156:ff21514d8981 423 #define DAC0 ((DAC_TypeDef *) DAC0_BASE) /**< DAC0 base pointer */
AnnaBridge 156:ff21514d8981 424 #define LCD ((LCD_TypeDef *) LCD_BASE) /**< LCD base pointer */
AnnaBridge 156:ff21514d8981 425 #define BURTC ((BURTC_TypeDef *) BURTC_BASE) /**< BURTC base pointer */
AnnaBridge 156:ff21514d8981 426 #define WDOG ((WDOG_TypeDef *) WDOG_BASE) /**< WDOG base pointer */
AnnaBridge 156:ff21514d8981 427 #define ETM ((ETM_TypeDef *) ETM_BASE) /**< ETM base pointer */
AnnaBridge 156:ff21514d8981 428 #define CALIBRATE ((CALIBRATE_TypeDef *) CALIBRATE_BASE) /**< CALIBRATE base pointer */
AnnaBridge 156:ff21514d8981 429 #define DEVINFO ((DEVINFO_TypeDef *) DEVINFO_BASE) /**< DEVINFO base pointer */
AnnaBridge 156:ff21514d8981 430 #define ROMTABLE ((ROMTABLE_TypeDef *) ROMTABLE_BASE) /**< ROMTABLE base pointer */
AnnaBridge 156:ff21514d8981 431
AnnaBridge 156:ff21514d8981 432 /** @} End of group EFM32WG900F256_Peripheral_Declaration */
AnnaBridge 156:ff21514d8981 433
AnnaBridge 156:ff21514d8981 434 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 435 * @defgroup EFM32WG900F256_BitFields EFM32WG900F256 Bit Fields
AnnaBridge 156:ff21514d8981 436 * @{
AnnaBridge 156:ff21514d8981 437 *****************************************************************************/
AnnaBridge 156:ff21514d8981 438
AnnaBridge 156:ff21514d8981 439 #include "efm32wg_prs_signals.h"
AnnaBridge 156:ff21514d8981 440 #include "efm32wg_dmareq.h"
AnnaBridge 156:ff21514d8981 441 #include "efm32wg_dmactrl.h"
AnnaBridge 156:ff21514d8981 442 #include "efm32wg_uart.h"
AnnaBridge 156:ff21514d8981 443
AnnaBridge 156:ff21514d8981 444 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 445 * @defgroup EFM32WG900F256_UNLOCK EFM32WG900F256 Unlock Codes
AnnaBridge 156:ff21514d8981 446 * @{
AnnaBridge 156:ff21514d8981 447 *****************************************************************************/
AnnaBridge 156:ff21514d8981 448 #define MSC_UNLOCK_CODE 0x1B71 /**< MSC unlock code */
AnnaBridge 156:ff21514d8981 449 #define EMU_UNLOCK_CODE 0xADE8 /**< EMU unlock code */
AnnaBridge 156:ff21514d8981 450 #define CMU_UNLOCK_CODE 0x580E /**< CMU unlock code */
AnnaBridge 156:ff21514d8981 451 #define TIMER_UNLOCK_CODE 0xCE80 /**< TIMER unlock code */
AnnaBridge 156:ff21514d8981 452 #define GPIO_UNLOCK_CODE 0xA534 /**< GPIO unlock code */
AnnaBridge 156:ff21514d8981 453 #define BURTC_UNLOCK_CODE 0xAEE8 /**< BURTC unlock code */
AnnaBridge 156:ff21514d8981 454
AnnaBridge 156:ff21514d8981 455 /** @} End of group EFM32WG900F256_UNLOCK */
AnnaBridge 156:ff21514d8981 456
AnnaBridge 156:ff21514d8981 457 /** @} End of group EFM32WG900F256_BitFields */
AnnaBridge 156:ff21514d8981 458
AnnaBridge 156:ff21514d8981 459 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 460 * @defgroup EFM32WG900F256_Alternate_Function EFM32WG900F256 Alternate Function
AnnaBridge 156:ff21514d8981 461 * @{
AnnaBridge 156:ff21514d8981 462 *****************************************************************************/
AnnaBridge 156:ff21514d8981 463
AnnaBridge 156:ff21514d8981 464 #include "efm32wg_af_ports.h"
AnnaBridge 156:ff21514d8981 465 #include "efm32wg_af_pins.h"
AnnaBridge 156:ff21514d8981 466
AnnaBridge 156:ff21514d8981 467 /** @} End of group EFM32WG900F256_Alternate_Function */
AnnaBridge 156:ff21514d8981 468
AnnaBridge 156:ff21514d8981 469 /**************************************************************************//**
AnnaBridge 156:ff21514d8981 470 * @brief Set the value of a bit field within a register.
AnnaBridge 156:ff21514d8981 471 *
AnnaBridge 156:ff21514d8981 472 * @param REG
AnnaBridge 156:ff21514d8981 473 * The register to update
AnnaBridge 156:ff21514d8981 474 * @param MASK
AnnaBridge 156:ff21514d8981 475 * The mask for the bit field to update
AnnaBridge 156:ff21514d8981 476 * @param VALUE
AnnaBridge 156:ff21514d8981 477 * The value to write to the bit field
AnnaBridge 156:ff21514d8981 478 * @param OFFSET
AnnaBridge 156:ff21514d8981 479 * The number of bits that the field is offset within the register.
AnnaBridge 156:ff21514d8981 480 * 0 (zero) means LSB.
AnnaBridge 156:ff21514d8981 481 *****************************************************************************/
AnnaBridge 156:ff21514d8981 482 #define SET_BIT_FIELD(REG, MASK, VALUE, OFFSET) \
AnnaBridge 156:ff21514d8981 483 REG = ((REG) &~(MASK)) | (((VALUE) << (OFFSET)) & (MASK));
AnnaBridge 156:ff21514d8981 484
AnnaBridge 156:ff21514d8981 485 /** @} End of group EFM32WG900F256 */
AnnaBridge 156:ff21514d8981 486
AnnaBridge 156:ff21514d8981 487 /** @} End of group Parts */
AnnaBridge 156:ff21514d8981 488
AnnaBridge 156:ff21514d8981 489 #ifdef __cplusplus
AnnaBridge 156:ff21514d8981 490 }
AnnaBridge 156:ff21514d8981 491 #endif
AnnaBridge 156:ff21514d8981 492 #endif /* EFM32WG900F256_H */