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The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_TB_SENSE_12/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_mpu.h@142:4eea097334d6, 2017-05-10 (annotated)

Committer:
Anna Bridge
Date:
Wed May 10 11:31:27 2017 +0100
Revision:
142:4eea097334d6
Child:
159:7130f322cb7e
Release 142 of the mbed library



Ports for Upcoming Targets





Fixes and Changes



4059: [Silicon Labs] Rename targets https://github.com/ARMmbed/mbed-os/pull/4059

4187: [NCS36510] Reduce default heap size allocated by IAR to 1/4 of RAM https://github.com/ARMmbed/mbed-os/pull/4187

4225: fixed missing device_name for xDot and removed progen https://github.com/ARMmbed/mbed-os/pull/4225

4251: Fix C++11 build error w/ u-blox EVK-ODIN-W2 https://github.com/ARMmbed/mbed-os/pull/4251

4236: STM32 Fixed warning related to __packed redefinition https://github.com/ARMmbed/mbed-os/pull/4236

4190: LPC4088: Enable LWIP feature https://github.com/ARMmbed/mbed-os/pull/4190

4260: Inherit Xadow M0 target from LPC11U35_501 https://github.com/ARMmbed/mbed-os/pull/4260

4249: Add consistent button names across targets https://github.com/ARMmbed/mbed-os/pull/4249

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Anna Bridge 142:4eea097334d6 1 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 2 * @file em_mpu.h
Anna Bridge 142:4eea097334d6 3 * @brief Memory protection unit (MPU) peripheral API
Anna Bridge 142:4eea097334d6 4 * @version 5.1.2
Anna Bridge 142:4eea097334d6 5 *******************************************************************************
Anna Bridge 142:4eea097334d6 6 * @section License
Anna Bridge 142:4eea097334d6 7 * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b>
Anna Bridge 142:4eea097334d6 8 *******************************************************************************
Anna Bridge 142:4eea097334d6 9 *
Anna Bridge 142:4eea097334d6 10 * Permission is granted to anyone to use this software for any purpose,
Anna Bridge 142:4eea097334d6 11 * including commercial applications, and to alter it and redistribute it
Anna Bridge 142:4eea097334d6 12 * freely, subject to the following restrictions:
Anna Bridge 142:4eea097334d6 13 *
Anna Bridge 142:4eea097334d6 14 * 1. The origin of this software must not be misrepresented; you must not
Anna Bridge 142:4eea097334d6 15 * claim that you wrote the original software.
Anna Bridge 142:4eea097334d6 16 * 2. Altered source versions must be plainly marked as such, and must not be
Anna Bridge 142:4eea097334d6 17 * misrepresented as being the original software.
Anna Bridge 142:4eea097334d6 18 * 3. This notice may not be removed or altered from any source distribution.
Anna Bridge 142:4eea097334d6 19 *
Anna Bridge 142:4eea097334d6 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
Anna Bridge 142:4eea097334d6 21 * obligation to support this Software. Silicon Labs is providing the
Anna Bridge 142:4eea097334d6 22 * Software "AS IS", with no express or implied warranties of any kind,
Anna Bridge 142:4eea097334d6 23 * including, but not limited to, any implied warranties of merchantability
Anna Bridge 142:4eea097334d6 24 * or fitness for any particular purpose or warranties against infringement
Anna Bridge 142:4eea097334d6 25 * of any proprietary rights of a third party.
Anna Bridge 142:4eea097334d6 26 *
Anna Bridge 142:4eea097334d6 27 * Silicon Labs will not be liable for any consequential, incidental, or
Anna Bridge 142:4eea097334d6 28 * special damages, or any other relief, or for any claim by any third party,
Anna Bridge 142:4eea097334d6 29 * arising from your use of this Software.
Anna Bridge 142:4eea097334d6 30 *
Anna Bridge 142:4eea097334d6 31 ******************************************************************************/
Anna Bridge 142:4eea097334d6 32
Anna Bridge 142:4eea097334d6 33 #ifndef EM_MPU_H
Anna Bridge 142:4eea097334d6 34 #define EM_MPU_H
Anna Bridge 142:4eea097334d6 35
Anna Bridge 142:4eea097334d6 36 #include "em_device.h"
Anna Bridge 142:4eea097334d6 37
Anna Bridge 142:4eea097334d6 38 #if defined(__MPU_PRESENT) && (__MPU_PRESENT == 1)
Anna Bridge 142:4eea097334d6 39 #include "em_assert.h"
Anna Bridge 142:4eea097334d6 40
Anna Bridge 142:4eea097334d6 41 #include <stdbool.h>
Anna Bridge 142:4eea097334d6 42
Anna Bridge 142:4eea097334d6 43 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 44 extern "C" {
Anna Bridge 142:4eea097334d6 45 #endif
Anna Bridge 142:4eea097334d6 46
Anna Bridge 142:4eea097334d6 47 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 48 * @addtogroup emlib
Anna Bridge 142:4eea097334d6 49 * @{
Anna Bridge 142:4eea097334d6 50 ******************************************************************************/
Anna Bridge 142:4eea097334d6 51
Anna Bridge 142:4eea097334d6 52 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 53 * @addtogroup MPU
Anna Bridge 142:4eea097334d6 54 * @{
Anna Bridge 142:4eea097334d6 55 ******************************************************************************/
Anna Bridge 142:4eea097334d6 56
Anna Bridge 142:4eea097334d6 57 /** @anchor MPU_CTRL_PRIVDEFENA
Anna Bridge 142:4eea097334d6 58 * Argument to MPU_enable(). Enables priviledged
Anna Bridge 142:4eea097334d6 59 * access to default memory map. */
Anna Bridge 142:4eea097334d6 60 #define MPU_CTRL_PRIVDEFENA MPU_CTRL_PRIVDEFENA_Msk
Anna Bridge 142:4eea097334d6 61
Anna Bridge 142:4eea097334d6 62 /** @anchor MPU_CTRL_HFNMIENA
Anna Bridge 142:4eea097334d6 63 * Argument to MPU_enable(). Enables MPU during hard fault,
Anna Bridge 142:4eea097334d6 64 * NMI, and FAULTMASK handlers. */
Anna Bridge 142:4eea097334d6 65 #define MPU_CTRL_HFNMIENA MPU_CTRL_HFNMIENA_Msk
Anna Bridge 142:4eea097334d6 66
Anna Bridge 142:4eea097334d6 67 /*******************************************************************************
Anna Bridge 142:4eea097334d6 68 ******************************** ENUMS ************************************
Anna Bridge 142:4eea097334d6 69 ******************************************************************************/
Anna Bridge 142:4eea097334d6 70
Anna Bridge 142:4eea097334d6 71 /**
Anna Bridge 142:4eea097334d6 72 * Size of an MPU region.
Anna Bridge 142:4eea097334d6 73 */
Anna Bridge 142:4eea097334d6 74 typedef enum
Anna Bridge 142:4eea097334d6 75 {
Anna Bridge 142:4eea097334d6 76 mpuRegionSize32b = 4, /**< 32 byte region size. */
Anna Bridge 142:4eea097334d6 77 mpuRegionSize64b = 5, /**< 64 byte region size. */
Anna Bridge 142:4eea097334d6 78 mpuRegionSize128b = 6, /**< 128 byte region size. */
Anna Bridge 142:4eea097334d6 79 mpuRegionSize256b = 7, /**< 256 byte region size. */
Anna Bridge 142:4eea097334d6 80 mpuRegionSize512b = 8, /**< 512 byte region size. */
Anna Bridge 142:4eea097334d6 81 mpuRegionSize1Kb = 9, /**< 1K byte region size. */
Anna Bridge 142:4eea097334d6 82 mpuRegionSize2Kb = 10, /**< 2K byte region size. */
Anna Bridge 142:4eea097334d6 83 mpuRegionSize4Kb = 11, /**< 4K byte region size. */
Anna Bridge 142:4eea097334d6 84 mpuRegionSize8Kb = 12, /**< 8K byte region size. */
Anna Bridge 142:4eea097334d6 85 mpuRegionSize16Kb = 13, /**< 16K byte region size. */
Anna Bridge 142:4eea097334d6 86 mpuRegionSize32Kb = 14, /**< 32K byte region size. */
Anna Bridge 142:4eea097334d6 87 mpuRegionSize64Kb = 15, /**< 64K byte region size. */
Anna Bridge 142:4eea097334d6 88 mpuRegionSize128Kb = 16, /**< 128K byte region size. */
Anna Bridge 142:4eea097334d6 89 mpuRegionSize256Kb = 17, /**< 256K byte region size. */
Anna Bridge 142:4eea097334d6 90 mpuRegionSize512Kb = 18, /**< 512K byte region size. */
Anna Bridge 142:4eea097334d6 91 mpuRegionSize1Mb = 19, /**< 1M byte region size. */
Anna Bridge 142:4eea097334d6 92 mpuRegionSize2Mb = 20, /**< 2M byte region size. */
Anna Bridge 142:4eea097334d6 93 mpuRegionSize4Mb = 21, /**< 4M byte region size. */
Anna Bridge 142:4eea097334d6 94 mpuRegionSize8Mb = 22, /**< 8M byte region size. */
Anna Bridge 142:4eea097334d6 95 mpuRegionSize16Mb = 23, /**< 16M byte region size. */
Anna Bridge 142:4eea097334d6 96 mpuRegionSize32Mb = 24, /**< 32M byte region size. */
Anna Bridge 142:4eea097334d6 97 mpuRegionSize64Mb = 25, /**< 64M byte region size. */
Anna Bridge 142:4eea097334d6 98 mpuRegionSize128Mb = 26, /**< 128M byte region size. */
Anna Bridge 142:4eea097334d6 99 mpuRegionSize256Mb = 27, /**< 256M byte region size. */
Anna Bridge 142:4eea097334d6 100 mpuRegionSize512Mb = 28, /**< 512M byte region size. */
Anna Bridge 142:4eea097334d6 101 mpuRegionSize1Gb = 29, /**< 1G byte region size. */
Anna Bridge 142:4eea097334d6 102 mpuRegionSize2Gb = 30, /**< 2G byte region size. */
Anna Bridge 142:4eea097334d6 103 mpuRegionSize4Gb = 31 /**< 4G byte region size. */
Anna Bridge 142:4eea097334d6 104 } MPU_RegionSize_TypeDef;
Anna Bridge 142:4eea097334d6 105
Anna Bridge 142:4eea097334d6 106 /**
Anna Bridge 142:4eea097334d6 107 * MPU region access permission attributes.
Anna Bridge 142:4eea097334d6 108 */
Anna Bridge 142:4eea097334d6 109 typedef enum
Anna Bridge 142:4eea097334d6 110 {
Anna Bridge 142:4eea097334d6 111 mpuRegionNoAccess = 0, /**< No access what so ever. */
Anna Bridge 142:4eea097334d6 112 mpuRegionApPRw = 1, /**< Priviledged state R/W only. */
Anna Bridge 142:4eea097334d6 113 mpuRegionApPRwURo = 2, /**< Priviledged state R/W, User state R only. */
Anna Bridge 142:4eea097334d6 114 mpuRegionApFullAccess = 3, /**< R/W in Priviledged and User state. */
Anna Bridge 142:4eea097334d6 115 mpuRegionApPRo = 5, /**< Priviledged R only. */
Anna Bridge 142:4eea097334d6 116 mpuRegionApPRo_URo = 6 /**< R only in Priviledged and User state. */
Anna Bridge 142:4eea097334d6 117 } MPU_RegionAp_TypeDef;
Anna Bridge 142:4eea097334d6 118
Anna Bridge 142:4eea097334d6 119
Anna Bridge 142:4eea097334d6 120 /*******************************************************************************
Anna Bridge 142:4eea097334d6 121 ******************************* STRUCTS ***********************************
Anna Bridge 142:4eea097334d6 122 ******************************************************************************/
Anna Bridge 142:4eea097334d6 123
Anna Bridge 142:4eea097334d6 124 /** MPU Region init structure. */
Anna Bridge 142:4eea097334d6 125 typedef struct
Anna Bridge 142:4eea097334d6 126 {
Anna Bridge 142:4eea097334d6 127 bool regionEnable; /**< MPU region enable. */
Anna Bridge 142:4eea097334d6 128 uint8_t regionNo; /**< MPU region number. */
Anna Bridge 142:4eea097334d6 129 uint32_t baseAddress; /**< Region baseaddress. */
Anna Bridge 142:4eea097334d6 130 MPU_RegionSize_TypeDef size; /**< Memory region size. */
Anna Bridge 142:4eea097334d6 131 MPU_RegionAp_TypeDef accessPermission; /**< Memory access permissions. */
Anna Bridge 142:4eea097334d6 132 bool disableExec; /**< Disable execution. */
Anna Bridge 142:4eea097334d6 133 bool shareable; /**< Memory shareable attribute. */
Anna Bridge 142:4eea097334d6 134 bool cacheable; /**< Memory cacheable attribute. */
Anna Bridge 142:4eea097334d6 135 bool bufferable; /**< Memory bufferable attribute. */
Anna Bridge 142:4eea097334d6 136 uint8_t srd; /**< Memory subregion disable bits. */
Anna Bridge 142:4eea097334d6 137 uint8_t tex; /**< Memory type extension attributes. */
Anna Bridge 142:4eea097334d6 138 } MPU_RegionInit_TypeDef;
Anna Bridge 142:4eea097334d6 139
Anna Bridge 142:4eea097334d6 140 /** Default configuration of MPU region init structure for flash memory. */
Anna Bridge 142:4eea097334d6 141 #define MPU_INIT_FLASH_DEFAULT \
Anna Bridge 142:4eea097334d6 142 { \
Anna Bridge 142:4eea097334d6 143 true, /* Enable MPU region. */ \
Anna Bridge 142:4eea097334d6 144 0, /* MPU Region number. */ \
Anna Bridge 142:4eea097334d6 145 FLASH_MEM_BASE, /* Flash base address. */ \
Anna Bridge 142:4eea097334d6 146 mpuRegionSize1Mb, /* Size - Set to max. */ \
Anna Bridge 142:4eea097334d6 147 mpuRegionApFullAccess, /* Access permissions. */ \
Anna Bridge 142:4eea097334d6 148 false, /* Execution allowed. */ \
Anna Bridge 142:4eea097334d6 149 false, /* Not shareable. */ \
Anna Bridge 142:4eea097334d6 150 true, /* Cacheable. */ \
Anna Bridge 142:4eea097334d6 151 false, /* Not bufferable. */ \
Anna Bridge 142:4eea097334d6 152 0, /* No subregions. */ \
Anna Bridge 142:4eea097334d6 153 0 /* No TEX attributes. */ \
Anna Bridge 142:4eea097334d6 154 }
Anna Bridge 142:4eea097334d6 155
Anna Bridge 142:4eea097334d6 156
Anna Bridge 142:4eea097334d6 157 /** Default configuration of MPU region init structure for sram memory. */
Anna Bridge 142:4eea097334d6 158 #define MPU_INIT_SRAM_DEFAULT \
Anna Bridge 142:4eea097334d6 159 { \
Anna Bridge 142:4eea097334d6 160 true, /* Enable MPU region. */ \
Anna Bridge 142:4eea097334d6 161 1, /* MPU Region number. */ \
Anna Bridge 142:4eea097334d6 162 RAM_MEM_BASE, /* SRAM base address. */ \
Anna Bridge 142:4eea097334d6 163 mpuRegionSize128Kb, /* Size - Set to max. */ \
Anna Bridge 142:4eea097334d6 164 mpuRegionApFullAccess, /* Access permissions. */ \
Anna Bridge 142:4eea097334d6 165 false, /* Execution allowed. */ \
Anna Bridge 142:4eea097334d6 166 true, /* Shareable. */ \
Anna Bridge 142:4eea097334d6 167 true, /* Cacheable. */ \
Anna Bridge 142:4eea097334d6 168 false, /* Not bufferable. */ \
Anna Bridge 142:4eea097334d6 169 0, /* No subregions. */ \
Anna Bridge 142:4eea097334d6 170 0 /* No TEX attributes. */ \
Anna Bridge 142:4eea097334d6 171 }
Anna Bridge 142:4eea097334d6 172
Anna Bridge 142:4eea097334d6 173
Anna Bridge 142:4eea097334d6 174 /** Default configuration of MPU region init structure for onchip peripherals.*/
Anna Bridge 142:4eea097334d6 175 #define MPU_INIT_PERIPHERAL_DEFAULT \
Anna Bridge 142:4eea097334d6 176 { \
Anna Bridge 142:4eea097334d6 177 true, /* Enable MPU region. */ \
Anna Bridge 142:4eea097334d6 178 0, /* MPU Region number. */ \
Anna Bridge 142:4eea097334d6 179 0, /* Region base address. */ \
Anna Bridge 142:4eea097334d6 180 mpuRegionSize32b, /* Size - Set to minimum */ \
Anna Bridge 142:4eea097334d6 181 mpuRegionApFullAccess, /* Access permissions. */ \
Anna Bridge 142:4eea097334d6 182 true, /* Execution not allowed. */ \
Anna Bridge 142:4eea097334d6 183 true, /* Shareable. */ \
Anna Bridge 142:4eea097334d6 184 false, /* Not cacheable. */ \
Anna Bridge 142:4eea097334d6 185 true, /* Bufferable. */ \
Anna Bridge 142:4eea097334d6 186 0, /* No subregions. */ \
Anna Bridge 142:4eea097334d6 187 0 /* No TEX attributes. */ \
Anna Bridge 142:4eea097334d6 188 }
Anna Bridge 142:4eea097334d6 189
Anna Bridge 142:4eea097334d6 190
Anna Bridge 142:4eea097334d6 191 /*******************************************************************************
Anna Bridge 142:4eea097334d6 192 ***************************** PROTOTYPES **********************************
Anna Bridge 142:4eea097334d6 193 ******************************************************************************/
Anna Bridge 142:4eea097334d6 194
Anna Bridge 142:4eea097334d6 195
Anna Bridge 142:4eea097334d6 196 void MPU_ConfigureRegion(const MPU_RegionInit_TypeDef *init);
Anna Bridge 142:4eea097334d6 197
Anna Bridge 142:4eea097334d6 198
Anna Bridge 142:4eea097334d6 199 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 200 * @brief
Anna Bridge 142:4eea097334d6 201 * Disable the MPU
Anna Bridge 142:4eea097334d6 202 * @details
Anna Bridge 142:4eea097334d6 203 * Disable MPU and MPU fault exceptions.
Anna Bridge 142:4eea097334d6 204 ******************************************************************************/
Anna Bridge 142:4eea097334d6 205 __STATIC_INLINE void MPU_Disable(void)
Anna Bridge 142:4eea097334d6 206 {
Anna Bridge 142:4eea097334d6 207 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; /* Disable fault exceptions */
Anna Bridge 142:4eea097334d6 208 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; /* Disable the MPU */
Anna Bridge 142:4eea097334d6 209 }
Anna Bridge 142:4eea097334d6 210
Anna Bridge 142:4eea097334d6 211
Anna Bridge 142:4eea097334d6 212 /***************************************************************************//**
Anna Bridge 142:4eea097334d6 213 * @brief
Anna Bridge 142:4eea097334d6 214 * Enable the MPU
Anna Bridge 142:4eea097334d6 215 * @details
Anna Bridge 142:4eea097334d6 216 * Enable MPU and MPU fault exceptions.
Anna Bridge 142:4eea097334d6 217 * @param[in] flags
Anna Bridge 142:4eea097334d6 218 * Use a logical OR of @ref MPU_CTRL_PRIVDEFENA and
Anna Bridge 142:4eea097334d6 219 * @ref MPU_CTRL_HFNMIENA as needed.
Anna Bridge 142:4eea097334d6 220 ******************************************************************************/
Anna Bridge 142:4eea097334d6 221 __STATIC_INLINE void MPU_Enable(uint32_t flags)
Anna Bridge 142:4eea097334d6 222 {
Anna Bridge 142:4eea097334d6 223 EFM_ASSERT(!(flags & ~(MPU_CTRL_PRIVDEFENA_Msk
Anna Bridge 142:4eea097334d6 224 | MPU_CTRL_HFNMIENA_Msk
Anna Bridge 142:4eea097334d6 225 | MPU_CTRL_ENABLE_Msk)));
Anna Bridge 142:4eea097334d6 226
Anna Bridge 142:4eea097334d6 227 MPU->CTRL = flags | MPU_CTRL_ENABLE_Msk; /* Enable the MPU */
Anna Bridge 142:4eea097334d6 228 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; /* Enable fault exceptions */
Anna Bridge 142:4eea097334d6 229 }
Anna Bridge 142:4eea097334d6 230
Anna Bridge 142:4eea097334d6 231
Anna Bridge 142:4eea097334d6 232 /** @} (end addtogroup MPU) */
Anna Bridge 142:4eea097334d6 233 /** @} (end addtogroup emlib) */
Anna Bridge 142:4eea097334d6 234
Anna Bridge 142:4eea097334d6 235 #ifdef __cplusplus
Anna Bridge 142:4eea097334d6 236 }
Anna Bridge 142:4eea097334d6 237 #endif
Anna Bridge 142:4eea097334d6 238
Anna Bridge 142:4eea097334d6 239 #endif /* defined(__MPU_PRESENT) && (__MPU_PRESENT == 1) */
Anna Bridge 142:4eea097334d6 240
Anna Bridge 142:4eea097334d6 241 #endif /* EM_MPU_H */