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mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_NRF51_DONGLE/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_11/device/nrf52.h@169:a7c7b631e539
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 148:fd96258d940d 1
Kojto 148:fd96258d940d 2 /****************************************************************************************************//**
Kojto 148:fd96258d940d 3 * @file nrf52.h
Kojto 148:fd96258d940d 4 *
Kojto 148:fd96258d940d 5 * @brief CMSIS Cortex-M4 Peripheral Access Layer Header File for
Kojto 148:fd96258d940d 6 * nrf52 from Nordic Semiconductor.
Kojto 148:fd96258d940d 7 *
Kojto 148:fd96258d940d 8 * @version V1
Kojto 148:fd96258d940d 9 * @date 23. February 2016
Kojto 148:fd96258d940d 10 *
Kojto 148:fd96258d940d 11 * @note Generated with SVDConv V2.81d
Kojto 148:fd96258d940d 12 * from CMSIS SVD File 'nrf52.svd' Version 1,
Kojto 148:fd96258d940d 13 *
Kojto 148:fd96258d940d 14 * @par Copyright (c) 2015, Nordic Semiconductor ASA
Kojto 148:fd96258d940d 15 * All rights reserved.
Kojto 148:fd96258d940d 16 *
Kojto 148:fd96258d940d 17 * Redistribution and use in source and binary forms, with or without
Kojto 148:fd96258d940d 18 * modification, are permitted provided that the following conditions are met:
Kojto 148:fd96258d940d 19 *
Kojto 148:fd96258d940d 20 * * Redistributions of source code must retain the above copyright notice, this
Kojto 148:fd96258d940d 21 * list of conditions and the following disclaimer.
Kojto 148:fd96258d940d 22 *
Kojto 148:fd96258d940d 23 * * Redistributions in binary form must reproduce the above copyright notice,
Kojto 148:fd96258d940d 24 * this list of conditions and the following disclaimer in the documentation
Kojto 148:fd96258d940d 25 * and/or other materials provided with the distribution.
Kojto 148:fd96258d940d 26 *
Kojto 148:fd96258d940d 27 * * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto 148:fd96258d940d 28 * contributors may be used to endorse or promote products derived from
Kojto 148:fd96258d940d 29 * this software without specific prior written permission.
Kojto 148:fd96258d940d 30 *
Kojto 148:fd96258d940d 31 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 148:fd96258d940d 32 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 148:fd96258d940d 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 148:fd96258d940d 34 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 148:fd96258d940d 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 148:fd96258d940d 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 148:fd96258d940d 37 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 148:fd96258d940d 38 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 148:fd96258d940d 39 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 148:fd96258d940d 40 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 148:fd96258d940d 41 *
Kojto 148:fd96258d940d 42 *
Kojto 148:fd96258d940d 43 *******************************************************************************************************/
Kojto 148:fd96258d940d 44
Kojto 148:fd96258d940d 45
Kojto 148:fd96258d940d 46
Kojto 148:fd96258d940d 47 /** @addtogroup Nordic Semiconductor
Kojto 148:fd96258d940d 48 * @{
Kojto 148:fd96258d940d 49 */
Kojto 148:fd96258d940d 50
Kojto 148:fd96258d940d 51 /** @addtogroup nrf52
Kojto 148:fd96258d940d 52 * @{
Kojto 148:fd96258d940d 53 */
Kojto 148:fd96258d940d 54
Kojto 148:fd96258d940d 55 #ifndef NRF52_H
Kojto 148:fd96258d940d 56 #define NRF52_H
Kojto 148:fd96258d940d 57
Kojto 148:fd96258d940d 58 #ifdef __cplusplus
Kojto 148:fd96258d940d 59 extern "C" {
Kojto 148:fd96258d940d 60 #endif
Kojto 148:fd96258d940d 61
Kojto 148:fd96258d940d 62
Kojto 148:fd96258d940d 63 /* ------------------------- Interrupt Number Definition ------------------------ */
Kojto 148:fd96258d940d 64
Kojto 148:fd96258d940d 65 typedef enum {
Kojto 148:fd96258d940d 66 /* ------------------- Cortex-M4 Processor Exceptions Numbers ------------------- */
Kojto 148:fd96258d940d 67 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
Kojto 148:fd96258d940d 68 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
Kojto 148:fd96258d940d 69 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
Kojto 148:fd96258d940d 70 MemoryManagement_IRQn = -12, /*!< 4 Memory Management, MPU mismatch, including Access Violation
Kojto 148:fd96258d940d 71 and No Match */
Kojto 148:fd96258d940d 72 BusFault_IRQn = -11, /*!< 5 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
Kojto 148:fd96258d940d 73 related Fault */
Kojto 148:fd96258d940d 74 UsageFault_IRQn = -10, /*!< 6 Usage Fault, i.e. Undef Instruction, Illegal State Transition */
Kojto 148:fd96258d940d 75 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
Kojto 148:fd96258d940d 76 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
Kojto 148:fd96258d940d 77 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
Kojto 148:fd96258d940d 78 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Kojto 148:fd96258d940d 79 /* ---------------------- nrf52 Specific Interrupt Numbers ---------------------- */
Kojto 148:fd96258d940d 80 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
Kojto 148:fd96258d940d 81 RADIO_IRQn = 1, /*!< 1 RADIO */
Kojto 148:fd96258d940d 82 UARTE0_UART0_IRQn = 2, /*!< 2 UARTE0_UART0 */
Kojto 148:fd96258d940d 83 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn= 3, /*!< 3 SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0 */
Kojto 148:fd96258d940d 84 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn= 4, /*!< 4 SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1 */
Kojto 148:fd96258d940d 85 NFCT_IRQn = 5, /*!< 5 NFCT */
Kojto 148:fd96258d940d 86 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
Kojto 148:fd96258d940d 87 SAADC_IRQn = 7, /*!< 7 SAADC */
Kojto 148:fd96258d940d 88 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
Kojto 148:fd96258d940d 89 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
Kojto 148:fd96258d940d 90 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
Kojto 148:fd96258d940d 91 RTC0_IRQn = 11, /*!< 11 RTC0 */
Kojto 148:fd96258d940d 92 TEMP_IRQn = 12, /*!< 12 TEMP */
Kojto 148:fd96258d940d 93 RNG_IRQn = 13, /*!< 13 RNG */
Kojto 148:fd96258d940d 94 ECB_IRQn = 14, /*!< 14 ECB */
Kojto 148:fd96258d940d 95 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
Kojto 148:fd96258d940d 96 WDT_IRQn = 16, /*!< 16 WDT */
Kojto 148:fd96258d940d 97 RTC1_IRQn = 17, /*!< 17 RTC1 */
Kojto 148:fd96258d940d 98 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 148:fd96258d940d 99 COMP_LPCOMP_IRQn = 19, /*!< 19 COMP_LPCOMP */
Kojto 148:fd96258d940d 100 SWI0_EGU0_IRQn = 20, /*!< 20 SWI0_EGU0 */
Kojto 148:fd96258d940d 101 SWI1_EGU1_IRQn = 21, /*!< 21 SWI1_EGU1 */
Kojto 148:fd96258d940d 102 SWI2_EGU2_IRQn = 22, /*!< 22 SWI2_EGU2 */
Kojto 148:fd96258d940d 103 SWI3_EGU3_IRQn = 23, /*!< 23 SWI3_EGU3 */
Kojto 148:fd96258d940d 104 SWI4_EGU4_IRQn = 24, /*!< 24 SWI4_EGU4 */
Kojto 148:fd96258d940d 105 SWI5_EGU5_IRQn = 25, /*!< 25 SWI5_EGU5 */
Kojto 148:fd96258d940d 106 TIMER3_IRQn = 26, /*!< 26 TIMER3 */
Kojto 148:fd96258d940d 107 TIMER4_IRQn = 27, /*!< 27 TIMER4 */
Kojto 148:fd96258d940d 108 PWM0_IRQn = 28, /*!< 28 PWM0 */
Kojto 148:fd96258d940d 109 PDM_IRQn = 29, /*!< 29 PDM */
Kojto 148:fd96258d940d 110 MWU_IRQn = 32, /*!< 32 MWU */
Kojto 148:fd96258d940d 111 PWM1_IRQn = 33, /*!< 33 PWM1 */
Kojto 148:fd96258d940d 112 PWM2_IRQn = 34, /*!< 34 PWM2 */
Kojto 148:fd96258d940d 113 SPIM2_SPIS2_SPI2_IRQn = 35, /*!< 35 SPIM2_SPIS2_SPI2 */
Kojto 148:fd96258d940d 114 RTC2_IRQn = 36, /*!< 36 RTC2 */
Kojto 148:fd96258d940d 115 I2S_IRQn = 37, /*!< 37 I2S */
Kojto 148:fd96258d940d 116 FPU_IRQn = 38 /*!< 38 FPU */
Kojto 148:fd96258d940d 117 } IRQn_Type;
Kojto 148:fd96258d940d 118
Kojto 148:fd96258d940d 119
Kojto 148:fd96258d940d 120 /** @addtogroup Configuration_of_CMSIS
Kojto 148:fd96258d940d 121 * @{
Kojto 148:fd96258d940d 122 */
Kojto 148:fd96258d940d 123
Kojto 148:fd96258d940d 124
Kojto 148:fd96258d940d 125 /* ================================================================================ */
Kojto 148:fd96258d940d 126 /* ================ Processor and Core Peripheral Section ================ */
Kojto 148:fd96258d940d 127 /* ================================================================================ */
Kojto 148:fd96258d940d 128
Kojto 148:fd96258d940d 129 /* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
Kojto 148:fd96258d940d 130 #define __CM4_REV 0x0001 /*!< Cortex-M4 Core Revision */
Kojto 148:fd96258d940d 131 #define __MPU_PRESENT 1 /*!< MPU present or not */
Kojto 148:fd96258d940d 132 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
Kojto 148:fd96258d940d 133 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 148:fd96258d940d 134 #define __FPU_PRESENT 1 /*!< FPU present or not */
Kojto 148:fd96258d940d 135 /** @} */ /* End of group Configuration_of_CMSIS */
Kojto 148:fd96258d940d 136
Kojto 148:fd96258d940d 137 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
Kojto 148:fd96258d940d 138 #include "system_nrf52.h" /*!< nrf52 System */
Kojto 148:fd96258d940d 139
Kojto 148:fd96258d940d 140
Kojto 148:fd96258d940d 141 /* ================================================================================ */
Kojto 148:fd96258d940d 142 /* ================ Device Specific Peripheral Section ================ */
Kojto 148:fd96258d940d 143 /* ================================================================================ */
Kojto 148:fd96258d940d 144
Kojto 148:fd96258d940d 145
Kojto 148:fd96258d940d 146 /** @addtogroup Device_Peripheral_Registers
Kojto 148:fd96258d940d 147 * @{
Kojto 148:fd96258d940d 148 */
Kojto 148:fd96258d940d 149
Kojto 148:fd96258d940d 150
Kojto 148:fd96258d940d 151 /* ------------------- Start of section using anonymous unions ------------------ */
Kojto 148:fd96258d940d 152 #if defined(__CC_ARM)
Kojto 148:fd96258d940d 153 #pragma push
Kojto 148:fd96258d940d 154 #pragma anon_unions
Kojto 148:fd96258d940d 155 #elif defined(__ICCARM__)
Kojto 148:fd96258d940d 156 #pragma language=extended
Kojto 148:fd96258d940d 157 #elif defined(__GNUC__)
Kojto 148:fd96258d940d 158 /* anonymous unions are enabled by default */
Kojto 148:fd96258d940d 159 #elif defined(__TMS470__)
Kojto 148:fd96258d940d 160 /* anonymous unions are enabled by default */
Kojto 148:fd96258d940d 161 #elif defined(__TASKING__)
Kojto 148:fd96258d940d 162 #pragma warning 586
Kojto 148:fd96258d940d 163 #else
Kojto 148:fd96258d940d 164 #warning Not supported compiler type
Kojto 148:fd96258d940d 165 #endif
Kojto 148:fd96258d940d 166
Kojto 148:fd96258d940d 167
Kojto 148:fd96258d940d 168 typedef struct {
Kojto 148:fd96258d940d 169 __I uint32_t PART; /*!< Part code */
Kojto 148:fd96258d940d 170 __I uint32_t VARIANT; /*!< Part Variant, Hardware version and Production configuration */
Kojto 148:fd96258d940d 171 __I uint32_t PACKAGE; /*!< Package option */
Kojto 148:fd96258d940d 172 __I uint32_t RAM; /*!< RAM variant */
Kojto 148:fd96258d940d 173 __I uint32_t FLASH; /*!< Flash variant */
Kojto 148:fd96258d940d 174 __IO uint32_t UNUSED0[3]; /*!< Description collection[0]: Unspecified */
Kojto 148:fd96258d940d 175 } FICR_INFO_Type;
Kojto 148:fd96258d940d 176
Kojto 148:fd96258d940d 177 typedef struct {
Kojto 148:fd96258d940d 178 __I uint32_t A0; /*!< Slope definition A0. */
Kojto 148:fd96258d940d 179 __I uint32_t A1; /*!< Slope definition A1. */
Kojto 148:fd96258d940d 180 __I uint32_t A2; /*!< Slope definition A2. */
Kojto 148:fd96258d940d 181 __I uint32_t A3; /*!< Slope definition A3. */
Kojto 148:fd96258d940d 182 __I uint32_t A4; /*!< Slope definition A4. */
Kojto 148:fd96258d940d 183 __I uint32_t A5; /*!< Slope definition A5. */
Kojto 148:fd96258d940d 184 __I uint32_t B0; /*!< y-intercept B0. */
Kojto 148:fd96258d940d 185 __I uint32_t B1; /*!< y-intercept B1. */
Kojto 148:fd96258d940d 186 __I uint32_t B2; /*!< y-intercept B2. */
Kojto 148:fd96258d940d 187 __I uint32_t B3; /*!< y-intercept B3. */
Kojto 148:fd96258d940d 188 __I uint32_t B4; /*!< y-intercept B4. */
Kojto 148:fd96258d940d 189 __I uint32_t B5; /*!< y-intercept B5. */
Kojto 148:fd96258d940d 190 __I uint32_t T0; /*!< Segment end T0. */
Kojto 148:fd96258d940d 191 __I uint32_t T1; /*!< Segment end T1. */
Kojto 148:fd96258d940d 192 __I uint32_t T2; /*!< Segment end T2. */
Kojto 148:fd96258d940d 193 __I uint32_t T3; /*!< Segment end T3. */
Kojto 148:fd96258d940d 194 __I uint32_t T4; /*!< Segment end T4. */
Kojto 148:fd96258d940d 195 } FICR_TEMP_Type;
Kojto 148:fd96258d940d 196
Kojto 148:fd96258d940d 197 typedef struct {
Kojto 148:fd96258d940d 198 __I uint32_t TAGHEADER0; /*!< Default header for NFC Tag. Software can read these values to
Kojto 148:fd96258d940d 199 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Kojto 148:fd96258d940d 200 __I uint32_t TAGHEADER1; /*!< Default header for NFC Tag. Software can read these values to
Kojto 148:fd96258d940d 201 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Kojto 148:fd96258d940d 202 __I uint32_t TAGHEADER2; /*!< Default header for NFC Tag. Software can read these values to
Kojto 148:fd96258d940d 203 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Kojto 148:fd96258d940d 204 __I uint32_t TAGHEADER3; /*!< Default header for NFC Tag. Software can read these values to
Kojto 148:fd96258d940d 205 populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
Kojto 148:fd96258d940d 206 } FICR_NFC_Type;
Kojto 148:fd96258d940d 207
Kojto 148:fd96258d940d 208 typedef struct {
Kojto 148:fd96258d940d 209 __IO uint32_t POWER; /*!< Description cluster[0]: RAM0 power control register */
Kojto 148:fd96258d940d 210 __O uint32_t POWERSET; /*!< Description cluster[0]: RAM0 power control set register */
Kojto 148:fd96258d940d 211 __O uint32_t POWERCLR; /*!< Description cluster[0]: RAM0 power control clear register */
Kojto 148:fd96258d940d 212 __I uint32_t RESERVED0;
Kojto 148:fd96258d940d 213 } POWER_RAM_Type;
Kojto 148:fd96258d940d 214
Kojto 148:fd96258d940d 215 typedef struct {
Kojto 148:fd96258d940d 216 __IO uint32_t CPU0; /*!< AHB bus master priority register for CPU0 */
Kojto 148:fd96258d940d 217 __IO uint32_t SPIS1; /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and
Kojto 148:fd96258d940d 218 TWIS1 */
Kojto 148:fd96258d940d 219 __IO uint32_t RADIO; /*!< AHB bus master priority register for RADIO */
Kojto 148:fd96258d940d 220 __IO uint32_t ECB; /*!< AHB bus master priority register for ECB */
Kojto 148:fd96258d940d 221 __IO uint32_t CCM; /*!< AHB bus master priority register for CCM */
Kojto 148:fd96258d940d 222 __IO uint32_t AAR; /*!< AHB bus master priority register for AAR */
Kojto 148:fd96258d940d 223 __IO uint32_t SAADC; /*!< AHB bus master priority register for SAADC */
Kojto 148:fd96258d940d 224 __IO uint32_t UARTE; /*!< AHB bus master priority register for UARTE */
Kojto 148:fd96258d940d 225 __IO uint32_t SERIAL0; /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and
Kojto 148:fd96258d940d 226 TWIS0 */
Kojto 148:fd96258d940d 227 __IO uint32_t SERIAL2; /*!< AHB bus master priority register for SPIM2 and SPIS2 */
Kojto 148:fd96258d940d 228 __IO uint32_t NFCT; /*!< AHB bus master priority register for NFCT */
Kojto 148:fd96258d940d 229 __IO uint32_t I2S; /*!< AHB bus master priority register for I2S */
Kojto 148:fd96258d940d 230 __IO uint32_t PDM; /*!< AHB bus master priority register for PDM */
Kojto 148:fd96258d940d 231 __IO uint32_t PWM; /*!< AHB bus master priority register for PWM0, PWM1 and PWM2 */
Kojto 148:fd96258d940d 232 } AMLI_RAMPRI_Type;
Kojto 148:fd96258d940d 233
Kojto 148:fd96258d940d 234 typedef struct {
Kojto 148:fd96258d940d 235 __IO uint32_t RTS; /*!< Pin select for RTS signal */
Kojto 148:fd96258d940d 236 __IO uint32_t TXD; /*!< Pin select for TXD signal */
Kojto 148:fd96258d940d 237 __IO uint32_t CTS; /*!< Pin select for CTS signal */
Kojto 148:fd96258d940d 238 __IO uint32_t RXD; /*!< Pin select for RXD signal */
Kojto 148:fd96258d940d 239 } UARTE_PSEL_Type;
Kojto 148:fd96258d940d 240
Kojto 148:fd96258d940d 241 typedef struct {
Kojto 148:fd96258d940d 242 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 243 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
Kojto 148:fd96258d940d 244 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
Kojto 148:fd96258d940d 245 } UARTE_RXD_Type;
Kojto 148:fd96258d940d 246
Kojto 148:fd96258d940d 247 typedef struct {
Kojto 148:fd96258d940d 248 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 249 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
Kojto 148:fd96258d940d 250 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
Kojto 148:fd96258d940d 251 } UARTE_TXD_Type;
Kojto 148:fd96258d940d 252
Kojto 148:fd96258d940d 253 typedef struct {
Kojto 148:fd96258d940d 254 __IO uint32_t SCK; /*!< Pin select for SCK */
Kojto 148:fd96258d940d 255 __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
Kojto 148:fd96258d940d 256 __IO uint32_t MISO; /*!< Pin select for MISO signal */
Kojto 148:fd96258d940d 257 } SPIM_PSEL_Type;
Kojto 148:fd96258d940d 258
Kojto 148:fd96258d940d 259 typedef struct {
Kojto 148:fd96258d940d 260 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 261 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
Kojto 148:fd96258d940d 262 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
Kojto 148:fd96258d940d 263 __IO uint32_t LIST; /*!< EasyDMA list type */
Kojto 148:fd96258d940d 264 } SPIM_RXD_Type;
Kojto 148:fd96258d940d 265
Kojto 148:fd96258d940d 266 typedef struct {
Kojto 148:fd96258d940d 267 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 268 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
Kojto 148:fd96258d940d 269 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
Kojto 148:fd96258d940d 270 __IO uint32_t LIST; /*!< EasyDMA list type */
Kojto 148:fd96258d940d 271 } SPIM_TXD_Type;
Kojto 148:fd96258d940d 272
Kojto 148:fd96258d940d 273 typedef struct {
Kojto 148:fd96258d940d 274 __IO uint32_t SCK; /*!< Pin select for SCK */
Kojto 148:fd96258d940d 275 __IO uint32_t MISO; /*!< Pin select for MISO signal */
Kojto 148:fd96258d940d 276 __IO uint32_t MOSI; /*!< Pin select for MOSI signal */
Kojto 148:fd96258d940d 277 __IO uint32_t CSN; /*!< Pin select for CSN signal */
Kojto 148:fd96258d940d 278 } SPIS_PSEL_Type;
Kojto 148:fd96258d940d 279
Kojto 148:fd96258d940d 280 typedef struct {
Kojto 148:fd96258d940d 281 __IO uint32_t PTR; /*!< RXD data pointer */
Kojto 148:fd96258d940d 282 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
Kojto 148:fd96258d940d 283 __I uint32_t AMOUNT; /*!< Number of bytes received in last granted transaction */
Kojto 148:fd96258d940d 284 } SPIS_RXD_Type;
Kojto 148:fd96258d940d 285
Kojto 148:fd96258d940d 286 typedef struct {
Kojto 148:fd96258d940d 287 __IO uint32_t PTR; /*!< TXD data pointer */
Kojto 148:fd96258d940d 288 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
Kojto 148:fd96258d940d 289 __I uint32_t AMOUNT; /*!< Number of bytes transmitted in last granted transaction */
Kojto 148:fd96258d940d 290 } SPIS_TXD_Type;
Kojto 148:fd96258d940d 291
Kojto 148:fd96258d940d 292 typedef struct {
Kojto 148:fd96258d940d 293 __IO uint32_t SCL; /*!< Pin select for SCL signal */
Kojto 148:fd96258d940d 294 __IO uint32_t SDA; /*!< Pin select for SDA signal */
Kojto 148:fd96258d940d 295 } TWIM_PSEL_Type;
Kojto 148:fd96258d940d 296
Kojto 148:fd96258d940d 297 typedef struct {
Kojto 148:fd96258d940d 298 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 299 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in receive buffer */
Kojto 148:fd96258d940d 300 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
Kojto 148:fd96258d940d 301 __IO uint32_t LIST; /*!< EasyDMA list type */
Kojto 148:fd96258d940d 302 } TWIM_RXD_Type;
Kojto 148:fd96258d940d 303
Kojto 148:fd96258d940d 304 typedef struct {
Kojto 148:fd96258d940d 305 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 306 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in transmit buffer */
Kojto 148:fd96258d940d 307 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last transaction */
Kojto 148:fd96258d940d 308 __IO uint32_t LIST; /*!< EasyDMA list type */
Kojto 148:fd96258d940d 309 } TWIM_TXD_Type;
Kojto 148:fd96258d940d 310
Kojto 148:fd96258d940d 311 typedef struct {
Kojto 148:fd96258d940d 312 __IO uint32_t SCL; /*!< Pin select for SCL signal */
Kojto 148:fd96258d940d 313 __IO uint32_t SDA; /*!< Pin select for SDA signal */
Kojto 148:fd96258d940d 314 } TWIS_PSEL_Type;
Kojto 148:fd96258d940d 315
Kojto 148:fd96258d940d 316 typedef struct {
Kojto 148:fd96258d940d 317 __IO uint32_t PTR; /*!< RXD Data pointer */
Kojto 148:fd96258d940d 318 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in RXD buffer */
Kojto 148:fd96258d940d 319 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last RXD transaction */
Kojto 148:fd96258d940d 320 } TWIS_RXD_Type;
Kojto 148:fd96258d940d 321
Kojto 148:fd96258d940d 322 typedef struct {
Kojto 148:fd96258d940d 323 __IO uint32_t PTR; /*!< TXD Data pointer */
Kojto 148:fd96258d940d 324 __IO uint32_t MAXCNT; /*!< Maximum number of bytes in TXD buffer */
Kojto 148:fd96258d940d 325 __I uint32_t AMOUNT; /*!< Number of bytes transferred in the last TXD transaction */
Kojto 148:fd96258d940d 326 } TWIS_TXD_Type;
Kojto 148:fd96258d940d 327
Kojto 148:fd96258d940d 328 typedef struct {
Kojto 148:fd96258d940d 329 __IO uint32_t SCK; /*!< Pin select for SCK */
Kojto 148:fd96258d940d 330 __IO uint32_t MOSI; /*!< Pin select for MOSI */
Kojto 148:fd96258d940d 331 __IO uint32_t MISO; /*!< Pin select for MISO */
Kojto 148:fd96258d940d 332 } SPI_PSEL_Type;
Kojto 148:fd96258d940d 333
Kojto 148:fd96258d940d 334 typedef struct {
Kojto 148:fd96258d940d 335 __IO uint32_t RX; /*!< Result of last incoming frames */
Kojto 148:fd96258d940d 336 } NFCT_FRAMESTATUS_Type;
Kojto 148:fd96258d940d 337
Kojto 148:fd96258d940d 338 typedef struct {
Kojto 148:fd96258d940d 339 __IO uint32_t FRAMECONFIG; /*!< Configuration of outgoing frames */
Kojto 148:fd96258d940d 340 __IO uint32_t AMOUNT; /*!< Size of outgoing frame */
Kojto 148:fd96258d940d 341 } NFCT_TXD_Type;
Kojto 148:fd96258d940d 342
Kojto 148:fd96258d940d 343 typedef struct {
Kojto 148:fd96258d940d 344 __IO uint32_t FRAMECONFIG; /*!< Configuration of incoming frames */
Kojto 148:fd96258d940d 345 __I uint32_t AMOUNT; /*!< Size of last incoming frame */
Kojto 148:fd96258d940d 346 } NFCT_RXD_Type;
Kojto 148:fd96258d940d 347
Kojto 148:fd96258d940d 348 typedef struct {
Kojto 148:fd96258d940d 349 __IO uint32_t LIMITH; /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
Kojto 148:fd96258d940d 350 __IO uint32_t LIMITL; /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
Kojto 148:fd96258d940d 351 } SAADC_EVENTS_CH_Type;
Kojto 148:fd96258d940d 352
Kojto 148:fd96258d940d 353 typedef struct {
Kojto 148:fd96258d940d 354 __IO uint32_t PSELP; /*!< Description cluster[0]: Input positive pin selection for CH[0] */
Kojto 148:fd96258d940d 355 __IO uint32_t PSELN; /*!< Description cluster[0]: Input negative pin selection for CH[0] */
Kojto 148:fd96258d940d 356 __IO uint32_t CONFIG; /*!< Description cluster[0]: Input configuration for CH[0] */
Kojto 148:fd96258d940d 357 __IO uint32_t LIMIT; /*!< Description cluster[0]: High/low limits for event monitoring
Kojto 148:fd96258d940d 358 a channel */
Kojto 148:fd96258d940d 359 } SAADC_CH_Type;
Kojto 148:fd96258d940d 360
Kojto 148:fd96258d940d 361 typedef struct {
Kojto 148:fd96258d940d 362 __IO uint32_t PTR; /*!< Data pointer */
Kojto 148:fd96258d940d 363 __IO uint32_t MAXCNT; /*!< Maximum number of buffer words to transfer */
Kojto 148:fd96258d940d 364 __I uint32_t AMOUNT; /*!< Number of buffer words transferred since last START */
Kojto 148:fd96258d940d 365 } SAADC_RESULT_Type;
Kojto 148:fd96258d940d 366
Kojto 148:fd96258d940d 367 typedef struct {
Kojto 148:fd96258d940d 368 __IO uint32_t LED; /*!< Pin select for LED signal */
Kojto 148:fd96258d940d 369 __IO uint32_t A; /*!< Pin select for A signal */
Kojto 148:fd96258d940d 370 __IO uint32_t B; /*!< Pin select for B signal */
Kojto 148:fd96258d940d 371 } QDEC_PSEL_Type;
Kojto 148:fd96258d940d 372
Kojto 148:fd96258d940d 373 typedef struct {
Kojto 148:fd96258d940d 374 __IO uint32_t PTR; /*!< Description cluster[0]: Beginning address in Data RAM of sequence
Kojto 148:fd96258d940d 375 A */
Kojto 148:fd96258d940d 376 __IO uint32_t CNT; /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
Kojto 148:fd96258d940d 377 A */
Kojto 148:fd96258d940d 378 __IO uint32_t REFRESH; /*!< Description cluster[0]: Amount of additional PWM periods between
Kojto 148:fd96258d940d 379 samples loaded to compare register (load every CNT+1 PWM periods) */
Kojto 148:fd96258d940d 380 __IO uint32_t ENDDELAY; /*!< Description cluster[0]: Time added after the sequence */
Kojto 148:fd96258d940d 381 __I uint32_t RESERVED1[4];
Kojto 148:fd96258d940d 382 } PWM_SEQ_Type;
Kojto 148:fd96258d940d 383
Kojto 148:fd96258d940d 384 typedef struct {
Kojto 148:fd96258d940d 385 __IO uint32_t OUT[4]; /*!< Description collection[0]: Output pin select for PWM channel
Kojto 148:fd96258d940d 386 0 */
Kojto 148:fd96258d940d 387 } PWM_PSEL_Type;
Kojto 148:fd96258d940d 388
Kojto 148:fd96258d940d 389 typedef struct {
Kojto 148:fd96258d940d 390 __IO uint32_t CLK; /*!< Pin number configuration for PDM CLK signal */
Kojto 148:fd96258d940d 391 __IO uint32_t DIN; /*!< Pin number configuration for PDM DIN signal */
Kojto 148:fd96258d940d 392 } PDM_PSEL_Type;
Kojto 148:fd96258d940d 393
Kojto 148:fd96258d940d 394 typedef struct {
Kojto 148:fd96258d940d 395 __IO uint32_t PTR; /*!< RAM address pointer to write samples to with EasyDMA */
Kojto 148:fd96258d940d 396 __IO uint32_t MAXCNT; /*!< Number of samples to allocate memory for in EasyDMA mode */
Kojto 148:fd96258d940d 397 } PDM_SAMPLE_Type;
Kojto 148:fd96258d940d 398
Kojto 148:fd96258d940d 399 typedef struct {
Kojto 148:fd96258d940d 400 __O uint32_t EN; /*!< Description cluster[0]: Enable channel group 0 */
Kojto 148:fd96258d940d 401 __O uint32_t DIS; /*!< Description cluster[0]: Disable channel group 0 */
Kojto 148:fd96258d940d 402 } PPI_TASKS_CHG_Type;
Kojto 148:fd96258d940d 403
Kojto 148:fd96258d940d 404 typedef struct {
Kojto 148:fd96258d940d 405 __IO uint32_t EEP; /*!< Description cluster[0]: Channel 0 event end-point */
Kojto 148:fd96258d940d 406 __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
Kojto 148:fd96258d940d 407 } PPI_CH_Type;
Kojto 148:fd96258d940d 408
Kojto 148:fd96258d940d 409 typedef struct {
Kojto 148:fd96258d940d 410 __IO uint32_t TEP; /*!< Description cluster[0]: Channel 0 task end-point */
Kojto 148:fd96258d940d 411 } PPI_FORK_Type;
Kojto 148:fd96258d940d 412
Kojto 148:fd96258d940d 413 typedef struct {
Kojto 148:fd96258d940d 414 __IO uint32_t WA; /*!< Description cluster[0]: Write access to region 0 detected */
Kojto 148:fd96258d940d 415 __IO uint32_t RA; /*!< Description cluster[0]: Read access to region 0 detected */
Kojto 148:fd96258d940d 416 } MWU_EVENTS_REGION_Type;
Kojto 148:fd96258d940d 417
Kojto 148:fd96258d940d 418 typedef struct {
Kojto 148:fd96258d940d 419 __IO uint32_t WA; /*!< Description cluster[0]: Write access to peripheral region 0
Kojto 148:fd96258d940d 420 detected */
Kojto 148:fd96258d940d 421 __IO uint32_t RA; /*!< Description cluster[0]: Read access to peripheral region 0 detected */
Kojto 148:fd96258d940d 422 } MWU_EVENTS_PREGION_Type;
Kojto 148:fd96258d940d 423
Kojto 148:fd96258d940d 424 typedef struct {
Kojto 148:fd96258d940d 425 __IO uint32_t SUBSTATWA; /*!< Description cluster[0]: Source of event/interrupt in region
Kojto 148:fd96258d940d 426 0, write access detected while corresponding subregion was enabled
Kojto 148:fd96258d940d 427 for watching */
Kojto 148:fd96258d940d 428 __IO uint32_t SUBSTATRA; /*!< Description cluster[0]: Source of event/interrupt in region
Kojto 148:fd96258d940d 429 0, read access detected while corresponding subregion was enabled
Kojto 148:fd96258d940d 430 for watching */
Kojto 148:fd96258d940d 431 } MWU_PERREGION_Type;
Kojto 148:fd96258d940d 432
Kojto 148:fd96258d940d 433 typedef struct {
Kojto 148:fd96258d940d 434 __IO uint32_t START; /*!< Description cluster[0]: Start address for region 0 */
Kojto 148:fd96258d940d 435 __IO uint32_t END; /*!< Description cluster[0]: End address of region 0 */
Kojto 148:fd96258d940d 436 __I uint32_t RESERVED2[2];
Kojto 148:fd96258d940d 437 } MWU_REGION_Type;
Kojto 148:fd96258d940d 438
Kojto 148:fd96258d940d 439 typedef struct {
Kojto 148:fd96258d940d 440 __I uint32_t START; /*!< Description cluster[0]: Reserved for future use */
Kojto 148:fd96258d940d 441 __I uint32_t END; /*!< Description cluster[0]: Reserved for future use */
Kojto 148:fd96258d940d 442 __IO uint32_t SUBS; /*!< Description cluster[0]: Subregions of region 0 */
Kojto 148:fd96258d940d 443 __I uint32_t RESERVED3;
Kojto 148:fd96258d940d 444 } MWU_PREGION_Type;
Kojto 148:fd96258d940d 445
Kojto 148:fd96258d940d 446 typedef struct {
Kojto 148:fd96258d940d 447 __IO uint32_t MODE; /*!< I2S mode. */
Kojto 148:fd96258d940d 448 __IO uint32_t RXEN; /*!< Reception (RX) enable. */
Kojto 148:fd96258d940d 449 __IO uint32_t TXEN; /*!< Transmission (TX) enable. */
Kojto 148:fd96258d940d 450 __IO uint32_t MCKEN; /*!< Master clock generator enable. */
Kojto 148:fd96258d940d 451 __IO uint32_t MCKFREQ; /*!< Master clock generator frequency. */
Kojto 148:fd96258d940d 452 __IO uint32_t RATIO; /*!< MCK / LRCK ratio. */
Kojto 148:fd96258d940d 453 __IO uint32_t SWIDTH; /*!< Sample width. */
Kojto 148:fd96258d940d 454 __IO uint32_t ALIGN; /*!< Alignment of sample within a frame. */
Kojto 148:fd96258d940d 455 __IO uint32_t FORMAT; /*!< Frame format. */
Kojto 148:fd96258d940d 456 __IO uint32_t CHANNELS; /*!< Enable channels. */
Kojto 148:fd96258d940d 457 } I2S_CONFIG_Type;
Kojto 148:fd96258d940d 458
Kojto 148:fd96258d940d 459 typedef struct {
Kojto 148:fd96258d940d 460 __IO uint32_t PTR; /*!< Receive buffer RAM start address. */
Kojto 148:fd96258d940d 461 } I2S_RXD_Type;
Kojto 148:fd96258d940d 462
Kojto 148:fd96258d940d 463 typedef struct {
Kojto 148:fd96258d940d 464 __IO uint32_t PTR; /*!< Transmit buffer RAM start address. */
Kojto 148:fd96258d940d 465 } I2S_TXD_Type;
Kojto 148:fd96258d940d 466
Kojto 148:fd96258d940d 467 typedef struct {
Kojto 148:fd96258d940d 468 __IO uint32_t MAXCNT; /*!< Size of RXD and TXD buffers. */
Kojto 148:fd96258d940d 469 } I2S_RXTXD_Type;
Kojto 148:fd96258d940d 470
Kojto 148:fd96258d940d 471 typedef struct {
Kojto 148:fd96258d940d 472 __IO uint32_t MCK; /*!< Pin select for MCK signal. */
Kojto 148:fd96258d940d 473 __IO uint32_t SCK; /*!< Pin select for SCK signal. */
Kojto 148:fd96258d940d 474 __IO uint32_t LRCK; /*!< Pin select for LRCK signal. */
Kojto 148:fd96258d940d 475 __IO uint32_t SDIN; /*!< Pin select for SDIN signal. */
Kojto 148:fd96258d940d 476 __IO uint32_t SDOUT; /*!< Pin select for SDOUT signal. */
Kojto 148:fd96258d940d 477 } I2S_PSEL_Type;
Kojto 148:fd96258d940d 478
Kojto 148:fd96258d940d 479
Kojto 148:fd96258d940d 480 /* ================================================================================ */
Kojto 148:fd96258d940d 481 /* ================ FICR ================ */
Kojto 148:fd96258d940d 482 /* ================================================================================ */
Kojto 148:fd96258d940d 483
Kojto 148:fd96258d940d 484
Kojto 148:fd96258d940d 485 /**
Kojto 148:fd96258d940d 486 * @brief Factory Information Configuration Registers (FICR)
Kojto 148:fd96258d940d 487 */
Kojto 148:fd96258d940d 488
Kojto 148:fd96258d940d 489 typedef struct { /*!< FICR Structure */
Kojto 148:fd96258d940d 490 __I uint32_t RESERVED0[4];
Kojto 148:fd96258d940d 491 __I uint32_t CODEPAGESIZE; /*!< Code memory page size */
Kojto 148:fd96258d940d 492 __I uint32_t CODESIZE; /*!< Code memory size */
Kojto 148:fd96258d940d 493 __I uint32_t RESERVED1[18];
Kojto 148:fd96258d940d 494 __I uint32_t DEVICEID[2]; /*!< Description collection[0]: Device identifier */
Kojto 148:fd96258d940d 495 __I uint32_t RESERVED2[6];
Kojto 148:fd96258d940d 496 __I uint32_t ER[4]; /*!< Description collection[0]: Encryption Root, word 0 */
Kojto 148:fd96258d940d 497 __I uint32_t IR[4]; /*!< Description collection[0]: Identity Root, word 0 */
Kojto 148:fd96258d940d 498 __I uint32_t DEVICEADDRTYPE; /*!< Device address type */
Kojto 148:fd96258d940d 499 __I uint32_t DEVICEADDR[2]; /*!< Description collection[0]: Device address 0 */
Kojto 148:fd96258d940d 500 __I uint32_t RESERVED3[21];
Kojto 148:fd96258d940d 501 FICR_INFO_Type INFO; /*!< Device info */
Kojto 148:fd96258d940d 502 __I uint32_t RESERVED4[185];
Kojto 148:fd96258d940d 503 FICR_TEMP_Type TEMP; /*!< Registers storing factory TEMP module linearization coefficients */
Kojto 148:fd96258d940d 504 __I uint32_t RESERVED5[2];
Kojto 148:fd96258d940d 505 FICR_NFC_Type NFC; /*!< Unspecified */
Kojto 148:fd96258d940d 506 } NRF_FICR_Type;
Kojto 148:fd96258d940d 507
Kojto 148:fd96258d940d 508
Kojto 148:fd96258d940d 509 /* ================================================================================ */
Kojto 148:fd96258d940d 510 /* ================ UICR ================ */
Kojto 148:fd96258d940d 511 /* ================================================================================ */
Kojto 148:fd96258d940d 512
Kojto 148:fd96258d940d 513
Kojto 148:fd96258d940d 514 /**
Kojto 148:fd96258d940d 515 * @brief User Information Configuration Registers (UICR)
Kojto 148:fd96258d940d 516 */
Kojto 148:fd96258d940d 517
Kojto 148:fd96258d940d 518 typedef struct { /*!< UICR Structure */
Kojto 148:fd96258d940d 519 __IO uint32_t UNUSED0; /*!< Unspecified */
Kojto 148:fd96258d940d 520 __IO uint32_t UNUSED1; /*!< Unspecified */
Kojto 148:fd96258d940d 521 __IO uint32_t UNUSED2; /*!< Unspecified */
Kojto 148:fd96258d940d 522 __I uint32_t RESERVED0;
Kojto 148:fd96258d940d 523 __IO uint32_t UNUSED3; /*!< Unspecified */
Kojto 148:fd96258d940d 524 __IO uint32_t NRFFW[15]; /*!< Description collection[0]: Reserved for Nordic firmware design */
Kojto 148:fd96258d940d 525 __IO uint32_t NRFHW[12]; /*!< Description collection[0]: Reserved for Nordic hardware design */
Kojto 148:fd96258d940d 526 __IO uint32_t CUSTOMER[32]; /*!< Description collection[0]: Reserved for customer */
Kojto 148:fd96258d940d 527 __I uint32_t RESERVED1[64];
Kojto 148:fd96258d940d 528 __IO uint32_t PSELRESET[2]; /*!< Description collection[0]: Mapping of the nRESET function (see
Kojto 148:fd96258d940d 529 POWER chapter for details) */
Kojto 148:fd96258d940d 530 __IO uint32_t APPROTECT; /*!< Access Port protection */
Kojto 148:fd96258d940d 531 __IO uint32_t NFCPINS; /*!< Setting of pins dedicated to NFC functionality: NFC antenna
Kojto 148:fd96258d940d 532 or GPIO */
Kojto 148:fd96258d940d 533 } NRF_UICR_Type;
Kojto 148:fd96258d940d 534
Kojto 148:fd96258d940d 535
Kojto 148:fd96258d940d 536 /* ================================================================================ */
Kojto 148:fd96258d940d 537 /* ================ BPROT ================ */
Kojto 148:fd96258d940d 538 /* ================================================================================ */
Kojto 148:fd96258d940d 539
Kojto 148:fd96258d940d 540
Kojto 148:fd96258d940d 541 /**
Kojto 148:fd96258d940d 542 * @brief Block Protect (BPROT)
Kojto 148:fd96258d940d 543 */
Kojto 148:fd96258d940d 544
Kojto 148:fd96258d940d 545 typedef struct { /*!< BPROT Structure */
Kojto 148:fd96258d940d 546 __I uint32_t RESERVED0[384];
Kojto 148:fd96258d940d 547 __IO uint32_t CONFIG0; /*!< Block protect configuration register 0 */
Kojto 148:fd96258d940d 548 __IO uint32_t CONFIG1; /*!< Block protect configuration register 1 */
Kojto 148:fd96258d940d 549 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug interface mode */
Kojto 148:fd96258d940d 550 __IO uint32_t UNUSED0; /*!< Unspecified */
Kojto 148:fd96258d940d 551 __IO uint32_t CONFIG2; /*!< Block protect configuration register 2 */
Kojto 148:fd96258d940d 552 __IO uint32_t CONFIG3; /*!< Block protect configuration register 3 */
Kojto 148:fd96258d940d 553 } NRF_BPROT_Type;
Kojto 148:fd96258d940d 554
Kojto 148:fd96258d940d 555
Kojto 148:fd96258d940d 556 /* ================================================================================ */
Kojto 148:fd96258d940d 557 /* ================ POWER ================ */
Kojto 148:fd96258d940d 558 /* ================================================================================ */
Kojto 148:fd96258d940d 559
Kojto 148:fd96258d940d 560
Kojto 148:fd96258d940d 561 /**
Kojto 148:fd96258d940d 562 * @brief Power control (POWER)
Kojto 148:fd96258d940d 563 */
Kojto 148:fd96258d940d 564
Kojto 148:fd96258d940d 565 typedef struct { /*!< POWER Structure */
Kojto 148:fd96258d940d 566 __I uint32_t RESERVED0[30];
Kojto 148:fd96258d940d 567 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode */
Kojto 148:fd96258d940d 568 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency) */
Kojto 148:fd96258d940d 569 __I uint32_t RESERVED1[34];
Kojto 148:fd96258d940d 570 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning */
Kojto 148:fd96258d940d 571 __I uint32_t RESERVED2[2];
Kojto 148:fd96258d940d 572 __IO uint32_t EVENTS_SLEEPENTER; /*!< CPU entered WFI/WFE sleep */
Kojto 148:fd96258d940d 573 __IO uint32_t EVENTS_SLEEPEXIT; /*!< CPU exited WFI/WFE sleep */
Kojto 148:fd96258d940d 574 __I uint32_t RESERVED3[122];
Kojto 148:fd96258d940d 575 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 576 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 577 __I uint32_t RESERVED4[61];
Kojto 148:fd96258d940d 578 __IO uint32_t RESETREAS; /*!< Reset reason */
Kojto 148:fd96258d940d 579 __I uint32_t RESERVED5[9];
Kojto 148:fd96258d940d 580 __I uint32_t RAMSTATUS; /*!< Deprecated register - RAM status register */
Kojto 148:fd96258d940d 581 __I uint32_t RESERVED6[53];
Kojto 148:fd96258d940d 582 __O uint32_t SYSTEMOFF; /*!< System OFF register */
Kojto 148:fd96258d940d 583 __I uint32_t RESERVED7[3];
Kojto 148:fd96258d940d 584 __IO uint32_t POFCON; /*!< Power failure comparator configuration */
Kojto 148:fd96258d940d 585 __I uint32_t RESERVED8[2];
Kojto 148:fd96258d940d 586 __IO uint32_t GPREGRET; /*!< General purpose retention register */
Kojto 148:fd96258d940d 587 __IO uint32_t GPREGRET2; /*!< General purpose retention register */
Kojto 148:fd96258d940d 588 __IO uint32_t RAMON; /*!< Deprecated register - RAM on/off register (this register is
Kojto 148:fd96258d940d 589 retained) */
Kojto 148:fd96258d940d 590 __I uint32_t RESERVED9[11];
Kojto 148:fd96258d940d 591 __IO uint32_t RAMONB; /*!< Deprecated register - RAM on/off register (this register is
Kojto 148:fd96258d940d 592 retained) */
Kojto 148:fd96258d940d 593 __I uint32_t RESERVED10[8];
Kojto 148:fd96258d940d 594 __IO uint32_t DCDCEN; /*!< DC/DC enable register */
Kojto 148:fd96258d940d 595 __I uint32_t RESERVED11[225];
Kojto 148:fd96258d940d 596 POWER_RAM_Type RAM[8]; /*!< Unspecified */
Kojto 148:fd96258d940d 597 } NRF_POWER_Type;
Kojto 148:fd96258d940d 598
Kojto 148:fd96258d940d 599
Kojto 148:fd96258d940d 600 /* ================================================================================ */
Kojto 148:fd96258d940d 601 /* ================ CLOCK ================ */
Kojto 148:fd96258d940d 602 /* ================================================================================ */
Kojto 148:fd96258d940d 603
Kojto 148:fd96258d940d 604
Kojto 148:fd96258d940d 605 /**
Kojto 148:fd96258d940d 606 * @brief Clock control (CLOCK)
Kojto 148:fd96258d940d 607 */
Kojto 148:fd96258d940d 608
Kojto 148:fd96258d940d 609 typedef struct { /*!< CLOCK Structure */
Kojto 148:fd96258d940d 610 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK crystal oscillator */
Kojto 148:fd96258d940d 611 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK crystal oscillator */
Kojto 148:fd96258d940d 612 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK source */
Kojto 148:fd96258d940d 613 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK source */
Kojto 148:fd96258d940d 614 __O uint32_t TASKS_CAL; /*!< Start calibration of LFRC oscillator */
Kojto 148:fd96258d940d 615 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer */
Kojto 148:fd96258d940d 616 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer */
Kojto 148:fd96258d940d 617 __I uint32_t RESERVED0[57];
Kojto 148:fd96258d940d 618 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started */
Kojto 148:fd96258d940d 619 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK started */
Kojto 148:fd96258d940d 620 __I uint32_t RESERVED1;
Kojto 148:fd96258d940d 621 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator complete event */
Kojto 148:fd96258d940d 622 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout */
Kojto 148:fd96258d940d 623 __I uint32_t RESERVED2[124];
Kojto 148:fd96258d940d 624 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 625 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 626 __I uint32_t RESERVED3[63];
Kojto 148:fd96258d940d 627 __I uint32_t HFCLKRUN; /*!< Status indicating that HFCLKSTART task has been triggered */
Kojto 148:fd96258d940d 628 __I uint32_t HFCLKSTAT; /*!< HFCLK status */
Kojto 148:fd96258d940d 629 __I uint32_t RESERVED4;
Kojto 148:fd96258d940d 630 __I uint32_t LFCLKRUN; /*!< Status indicating that LFCLKSTART task has been triggered */
Kojto 148:fd96258d940d 631 __I uint32_t LFCLKSTAT; /*!< LFCLK status */
Kojto 148:fd96258d940d 632 __I uint32_t LFCLKSRCCOPY; /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
Kojto 148:fd96258d940d 633 __I uint32_t RESERVED5[62];
Kojto 148:fd96258d940d 634 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK */
Kojto 148:fd96258d940d 635 __I uint32_t RESERVED6[7];
Kojto 148:fd96258d940d 636 __IO uint32_t CTIV; /*!< Calibration timer interval (retained register, same reset behaviour
Kojto 148:fd96258d940d 637 as RESETREAS) */
Kojto 148:fd96258d940d 638 __I uint32_t RESERVED7[8];
Kojto 148:fd96258d940d 639 __IO uint32_t TRACECONFIG; /*!< Clocking options for the Trace Port debug interface */
Kojto 148:fd96258d940d 640 } NRF_CLOCK_Type;
Kojto 148:fd96258d940d 641
Kojto 148:fd96258d940d 642
Kojto 148:fd96258d940d 643 /* ================================================================================ */
Kojto 148:fd96258d940d 644 /* ================ AMLI ================ */
Kojto 148:fd96258d940d 645 /* ================================================================================ */
Kojto 148:fd96258d940d 646
Kojto 148:fd96258d940d 647
Kojto 148:fd96258d940d 648 /**
Kojto 148:fd96258d940d 649 * @brief AHB Multi-Layer Interface (AMLI)
Kojto 148:fd96258d940d 650 */
Kojto 148:fd96258d940d 651
Kojto 148:fd96258d940d 652 typedef struct { /*!< AMLI Structure */
Kojto 148:fd96258d940d 653 __I uint32_t RESERVED0[896];
Kojto 148:fd96258d940d 654 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure */
Kojto 148:fd96258d940d 655 } NRF_AMLI_Type;
Kojto 148:fd96258d940d 656
Kojto 148:fd96258d940d 657
Kojto 148:fd96258d940d 658 /* ================================================================================ */
Kojto 148:fd96258d940d 659 /* ================ RADIO ================ */
Kojto 148:fd96258d940d 660 /* ================================================================================ */
Kojto 148:fd96258d940d 661
Kojto 148:fd96258d940d 662
Kojto 148:fd96258d940d 663 /**
Kojto 148:fd96258d940d 664 * @brief 2.4 GHz Radio (RADIO)
Kojto 148:fd96258d940d 665 */
Kojto 148:fd96258d940d 666
Kojto 148:fd96258d940d 667 typedef struct { /*!< RADIO Structure */
Kojto 148:fd96258d940d 668 __O uint32_t TASKS_TXEN; /*!< Enable RADIO in TX mode */
Kojto 148:fd96258d940d 669 __O uint32_t TASKS_RXEN; /*!< Enable RADIO in RX mode */
Kojto 148:fd96258d940d 670 __O uint32_t TASKS_START; /*!< Start RADIO */
Kojto 148:fd96258d940d 671 __O uint32_t TASKS_STOP; /*!< Stop RADIO */
Kojto 148:fd96258d940d 672 __O uint32_t TASKS_DISABLE; /*!< Disable RADIO */
Kojto 148:fd96258d940d 673 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one single sample of the receive signal
Kojto 148:fd96258d940d 674 strength. */
Kojto 148:fd96258d940d 675 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement */
Kojto 148:fd96258d940d 676 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter */
Kojto 148:fd96258d940d 677 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter */
Kojto 148:fd96258d940d 678 __I uint32_t RESERVED0[55];
Kojto 148:fd96258d940d 679 __IO uint32_t EVENTS_READY; /*!< RADIO has ramped up and is ready to be started */
Kojto 148:fd96258d940d 680 __IO uint32_t EVENTS_ADDRESS; /*!< Address sent or received */
Kojto 148:fd96258d940d 681 __IO uint32_t EVENTS_PAYLOAD; /*!< Packet payload sent or received */
Kojto 148:fd96258d940d 682 __IO uint32_t EVENTS_END; /*!< Packet sent or received */
Kojto 148:fd96258d940d 683 __IO uint32_t EVENTS_DISABLED; /*!< RADIO has been disabled */
Kojto 148:fd96258d940d 684 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet */
Kojto 148:fd96258d940d 685 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet */
Kojto 148:fd96258d940d 686 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of receive signal strength complete. */
Kojto 148:fd96258d940d 687 __I uint32_t RESERVED1[2];
Kojto 148:fd96258d940d 688 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value. */
Kojto 148:fd96258d940d 689 __I uint32_t RESERVED2;
Kojto 148:fd96258d940d 690 __IO uint32_t EVENTS_CRCOK; /*!< Packet received with CRC ok */
Kojto 148:fd96258d940d 691 __IO uint32_t EVENTS_CRCERROR; /*!< Packet received with CRC error */
Kojto 148:fd96258d940d 692 __I uint32_t RESERVED3[50];
Kojto 148:fd96258d940d 693 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 694 __I uint32_t RESERVED4[64];
Kojto 148:fd96258d940d 695 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 696 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 697 __I uint32_t RESERVED5[61];
Kojto 148:fd96258d940d 698 __I uint32_t CRCSTATUS; /*!< CRC status */
Kojto 148:fd96258d940d 699 __I uint32_t RESERVED6;
Kojto 148:fd96258d940d 700 __I uint32_t RXMATCH; /*!< Received address */
Kojto 148:fd96258d940d 701 __I uint32_t RXCRC; /*!< CRC field of previously received packet */
Kojto 148:fd96258d940d 702 __I uint32_t DAI; /*!< Device address match index */
Kojto 148:fd96258d940d 703 __I uint32_t RESERVED7[60];
Kojto 148:fd96258d940d 704 __IO uint32_t PACKETPTR; /*!< Packet pointer */
Kojto 148:fd96258d940d 705 __IO uint32_t FREQUENCY; /*!< Frequency */
Kojto 148:fd96258d940d 706 __IO uint32_t TXPOWER; /*!< Output power */
Kojto 148:fd96258d940d 707 __IO uint32_t MODE; /*!< Data rate and modulation */
Kojto 148:fd96258d940d 708 __IO uint32_t PCNF0; /*!< Packet configuration register 0 */
Kojto 148:fd96258d940d 709 __IO uint32_t PCNF1; /*!< Packet configuration register 1 */
Kojto 148:fd96258d940d 710 __IO uint32_t BASE0; /*!< Base address 0 */
Kojto 148:fd96258d940d 711 __IO uint32_t BASE1; /*!< Base address 1 */
Kojto 148:fd96258d940d 712 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0-3 */
Kojto 148:fd96258d940d 713 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4-7 */
Kojto 148:fd96258d940d 714 __IO uint32_t TXADDRESS; /*!< Transmit address select */
Kojto 148:fd96258d940d 715 __IO uint32_t RXADDRESSES; /*!< Receive address select */
Kojto 148:fd96258d940d 716 __IO uint32_t CRCCNF; /*!< CRC configuration */
Kojto 148:fd96258d940d 717 __IO uint32_t CRCPOLY; /*!< CRC polynomial */
Kojto 148:fd96258d940d 718 __IO uint32_t CRCINIT; /*!< CRC initial value */
Kojto 148:fd96258d940d 719 __IO uint32_t UNUSED0; /*!< Unspecified */
Kojto 148:fd96258d940d 720 __IO uint32_t TIFS; /*!< Inter Frame Spacing in us */
Kojto 148:fd96258d940d 721 __I uint32_t RSSISAMPLE; /*!< RSSI sample */
Kojto 148:fd96258d940d 722 __I uint32_t RESERVED8;
Kojto 148:fd96258d940d 723 __I uint32_t STATE; /*!< Current radio state */
Kojto 148:fd96258d940d 724 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value */
Kojto 148:fd96258d940d 725 __I uint32_t RESERVED9[2];
Kojto 148:fd96258d940d 726 __IO uint32_t BCC; /*!< Bit counter compare */
Kojto 148:fd96258d940d 727 __I uint32_t RESERVED10[39];
Kojto 148:fd96258d940d 728 __IO uint32_t DAB[8]; /*!< Description collection[0]: Device address base segment 0 */
Kojto 148:fd96258d940d 729 __IO uint32_t DAP[8]; /*!< Description collection[0]: Device address prefix 0 */
Kojto 148:fd96258d940d 730 __IO uint32_t DACNF; /*!< Device address match configuration */
Kojto 148:fd96258d940d 731 __I uint32_t RESERVED11[3];
Kojto 148:fd96258d940d 732 __IO uint32_t MODECNF0; /*!< Radio mode configuration register 0 */
Kojto 148:fd96258d940d 733 __I uint32_t RESERVED12[618];
Kojto 148:fd96258d940d 734 __IO uint32_t POWER; /*!< Peripheral power control */
Kojto 148:fd96258d940d 735 } NRF_RADIO_Type;
Kojto 148:fd96258d940d 736
Kojto 148:fd96258d940d 737
Kojto 148:fd96258d940d 738 /* ================================================================================ */
Kojto 148:fd96258d940d 739 /* ================ UARTE ================ */
Kojto 148:fd96258d940d 740 /* ================================================================================ */
Kojto 148:fd96258d940d 741
Kojto 148:fd96258d940d 742
Kojto 148:fd96258d940d 743 /**
Kojto 148:fd96258d940d 744 * @brief UART with EasyDMA (UARTE)
Kojto 148:fd96258d940d 745 */
Kojto 148:fd96258d940d 746
Kojto 148:fd96258d940d 747 typedef struct { /*!< UARTE Structure */
Kojto 148:fd96258d940d 748 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
Kojto 148:fd96258d940d 749 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
Kojto 148:fd96258d940d 750 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
Kojto 148:fd96258d940d 751 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
Kojto 148:fd96258d940d 752 __I uint32_t RESERVED0[7];
Kojto 148:fd96258d940d 753 __O uint32_t TASKS_FLUSHRX; /*!< Flush RX FIFO into RX buffer */
Kojto 148:fd96258d940d 754 __I uint32_t RESERVED1[52];
Kojto 148:fd96258d940d 755 __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
Kojto 148:fd96258d940d 756 __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
Kojto 148:fd96258d940d 757 __I uint32_t RESERVED2[2];
Kojto 148:fd96258d940d 758 __IO uint32_t EVENTS_ENDRX; /*!< Receive buffer is filled up */
Kojto 148:fd96258d940d 759 __I uint32_t RESERVED3[3];
Kojto 148:fd96258d940d 760 __IO uint32_t EVENTS_ENDTX; /*!< Last TX byte transmitted */
Kojto 148:fd96258d940d 761 __IO uint32_t EVENTS_ERROR; /*!< Error detected */
Kojto 148:fd96258d940d 762 __I uint32_t RESERVED4[7];
Kojto 148:fd96258d940d 763 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
Kojto 148:fd96258d940d 764 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 765 __IO uint32_t EVENTS_RXSTARTED; /*!< UART receiver has started */
Kojto 148:fd96258d940d 766 __IO uint32_t EVENTS_TXSTARTED; /*!< UART transmitter has started */
Kojto 148:fd96258d940d 767 __I uint32_t RESERVED6;
Kojto 148:fd96258d940d 768 __IO uint32_t EVENTS_TXSTOPPED; /*!< Transmitter stopped */
Kojto 148:fd96258d940d 769 __I uint32_t RESERVED7[41];
Kojto 148:fd96258d940d 770 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 771 __I uint32_t RESERVED8[63];
Kojto 148:fd96258d940d 772 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 773 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 774 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 775 __I uint32_t RESERVED9[93];
Kojto 148:fd96258d940d 776 __IO uint32_t ERRORSRC; /*!< Error source */
Kojto 148:fd96258d940d 777 __I uint32_t RESERVED10[31];
Kojto 148:fd96258d940d 778 __IO uint32_t ENABLE; /*!< Enable UART */
Kojto 148:fd96258d940d 779 __I uint32_t RESERVED11;
Kojto 148:fd96258d940d 780 UARTE_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 781 __I uint32_t RESERVED12[3];
Kojto 148:fd96258d940d 782 __IO uint32_t BAUDRATE; /*!< Baud rate */
Kojto 148:fd96258d940d 783 __I uint32_t RESERVED13[3];
Kojto 148:fd96258d940d 784 UARTE_RXD_Type RXD; /*!< RXD EasyDMA channel */
Kojto 148:fd96258d940d 785 __I uint32_t RESERVED14;
Kojto 148:fd96258d940d 786 UARTE_TXD_Type TXD; /*!< TXD EasyDMA channel */
Kojto 148:fd96258d940d 787 __I uint32_t RESERVED15[7];
Kojto 148:fd96258d940d 788 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
Kojto 148:fd96258d940d 789 } NRF_UARTE_Type;
Kojto 148:fd96258d940d 790
Kojto 148:fd96258d940d 791
Kojto 148:fd96258d940d 792 /* ================================================================================ */
Kojto 148:fd96258d940d 793 /* ================ UART ================ */
Kojto 148:fd96258d940d 794 /* ================================================================================ */
Kojto 148:fd96258d940d 795
Kojto 148:fd96258d940d 796
Kojto 148:fd96258d940d 797 /**
Kojto 148:fd96258d940d 798 * @brief Universal Asynchronous Receiver/Transmitter (UART)
Kojto 148:fd96258d940d 799 */
Kojto 148:fd96258d940d 800
Kojto 148:fd96258d940d 801 typedef struct { /*!< UART Structure */
Kojto 148:fd96258d940d 802 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver */
Kojto 148:fd96258d940d 803 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver */
Kojto 148:fd96258d940d 804 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter */
Kojto 148:fd96258d940d 805 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter */
Kojto 148:fd96258d940d 806 __I uint32_t RESERVED0[3];
Kojto 148:fd96258d940d 807 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART */
Kojto 148:fd96258d940d 808 __I uint32_t RESERVED1[56];
Kojto 148:fd96258d940d 809 __IO uint32_t EVENTS_CTS; /*!< CTS is activated (set low). Clear To Send. */
Kojto 148:fd96258d940d 810 __IO uint32_t EVENTS_NCTS; /*!< CTS is deactivated (set high). Not Clear To Send. */
Kojto 148:fd96258d940d 811 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD */
Kojto 148:fd96258d940d 812 __I uint32_t RESERVED2[4];
Kojto 148:fd96258d940d 813 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD */
Kojto 148:fd96258d940d 814 __I uint32_t RESERVED3;
Kojto 148:fd96258d940d 815 __IO uint32_t EVENTS_ERROR; /*!< Error detected */
Kojto 148:fd96258d940d 816 __I uint32_t RESERVED4[7];
Kojto 148:fd96258d940d 817 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout */
Kojto 148:fd96258d940d 818 __I uint32_t RESERVED5[46];
Kojto 148:fd96258d940d 819 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 820 __I uint32_t RESERVED6[64];
Kojto 148:fd96258d940d 821 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 822 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 823 __I uint32_t RESERVED7[93];
Kojto 148:fd96258d940d 824 __IO uint32_t ERRORSRC; /*!< Error source */
Kojto 148:fd96258d940d 825 __I uint32_t RESERVED8[31];
Kojto 148:fd96258d940d 826 __IO uint32_t ENABLE; /*!< Enable UART */
Kojto 148:fd96258d940d 827 __I uint32_t RESERVED9;
Kojto 148:fd96258d940d 828 __IO uint32_t PSELRTS; /*!< Pin select for RTS */
Kojto 148:fd96258d940d 829 __IO uint32_t PSELTXD; /*!< Pin select for TXD */
Kojto 148:fd96258d940d 830 __IO uint32_t PSELCTS; /*!< Pin select for CTS */
Kojto 148:fd96258d940d 831 __IO uint32_t PSELRXD; /*!< Pin select for RXD */
Kojto 148:fd96258d940d 832 __I uint32_t RXD; /*!< RXD register */
Kojto 148:fd96258d940d 833 __O uint32_t TXD; /*!< TXD register */
Kojto 148:fd96258d940d 834 __I uint32_t RESERVED10;
Kojto 148:fd96258d940d 835 __IO uint32_t BAUDRATE; /*!< Baud rate */
Kojto 148:fd96258d940d 836 __I uint32_t RESERVED11[17];
Kojto 148:fd96258d940d 837 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control */
Kojto 148:fd96258d940d 838 } NRF_UART_Type;
Kojto 148:fd96258d940d 839
Kojto 148:fd96258d940d 840
Kojto 148:fd96258d940d 841 /* ================================================================================ */
Kojto 148:fd96258d940d 842 /* ================ SPIM ================ */
Kojto 148:fd96258d940d 843 /* ================================================================================ */
Kojto 148:fd96258d940d 844
Kojto 148:fd96258d940d 845
Kojto 148:fd96258d940d 846 /**
Kojto 148:fd96258d940d 847 * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
Kojto 148:fd96258d940d 848 */
Kojto 148:fd96258d940d 849
Kojto 148:fd96258d940d 850 typedef struct { /*!< SPIM Structure */
Kojto 148:fd96258d940d 851 __I uint32_t RESERVED0[4];
Kojto 148:fd96258d940d 852 __O uint32_t TASKS_START; /*!< Start SPI transaction */
Kojto 148:fd96258d940d 853 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction */
Kojto 148:fd96258d940d 854 __I uint32_t RESERVED1;
Kojto 148:fd96258d940d 855 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction */
Kojto 148:fd96258d940d 856 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction */
Kojto 148:fd96258d940d 857 __I uint32_t RESERVED2[56];
Kojto 148:fd96258d940d 858 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped */
Kojto 148:fd96258d940d 859 __I uint32_t RESERVED3[2];
Kojto 148:fd96258d940d 860 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Kojto 148:fd96258d940d 861 __I uint32_t RESERVED4;
Kojto 148:fd96258d940d 862 __IO uint32_t EVENTS_END; /*!< End of RXD buffer and TXD buffer reached */
Kojto 148:fd96258d940d 863 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 864 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached */
Kojto 148:fd96258d940d 865 __I uint32_t RESERVED6[10];
Kojto 148:fd96258d940d 866 __IO uint32_t EVENTS_STARTED; /*!< Transaction started */
Kojto 148:fd96258d940d 867 __I uint32_t RESERVED7[44];
Kojto 148:fd96258d940d 868 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 869 __I uint32_t RESERVED8[64];
Kojto 148:fd96258d940d 870 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 871 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 872 __I uint32_t RESERVED9[125];
Kojto 148:fd96258d940d 873 __IO uint32_t ENABLE; /*!< Enable SPIM */
Kojto 148:fd96258d940d 874 __I uint32_t RESERVED10;
Kojto 148:fd96258d940d 875 SPIM_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 876 __I uint32_t RESERVED11[4];
Kojto 148:fd96258d940d 877 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Kojto 148:fd96258d940d 878 __I uint32_t RESERVED12[3];
Kojto 148:fd96258d940d 879 SPIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
Kojto 148:fd96258d940d 880 SPIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
Kojto 148:fd96258d940d 881 __IO uint32_t CONFIG; /*!< Configuration register */
Kojto 148:fd96258d940d 882 __I uint32_t RESERVED13[26];
Kojto 148:fd96258d940d 883 __IO uint32_t ORC; /*!< Over-read character. Character clocked out in case and over-read
Kojto 148:fd96258d940d 884 of the TXD buffer. */
Kojto 148:fd96258d940d 885 } NRF_SPIM_Type;
Kojto 148:fd96258d940d 886
Kojto 148:fd96258d940d 887
Kojto 148:fd96258d940d 888 /* ================================================================================ */
Kojto 148:fd96258d940d 889 /* ================ SPIS ================ */
Kojto 148:fd96258d940d 890 /* ================================================================================ */
Kojto 148:fd96258d940d 891
Kojto 148:fd96258d940d 892
Kojto 148:fd96258d940d 893 /**
Kojto 148:fd96258d940d 894 * @brief SPI Slave 0 (SPIS)
Kojto 148:fd96258d940d 895 */
Kojto 148:fd96258d940d 896
Kojto 148:fd96258d940d 897 typedef struct { /*!< SPIS Structure */
Kojto 148:fd96258d940d 898 __I uint32_t RESERVED0[9];
Kojto 148:fd96258d940d 899 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore */
Kojto 148:fd96258d940d 900 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore, enabling the SPI slave to acquire it */
Kojto 148:fd96258d940d 901 __I uint32_t RESERVED1[54];
Kojto 148:fd96258d940d 902 __IO uint32_t EVENTS_END; /*!< Granted transaction completed */
Kojto 148:fd96258d940d 903 __I uint32_t RESERVED2[2];
Kojto 148:fd96258d940d 904 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Kojto 148:fd96258d940d 905 __I uint32_t RESERVED3[5];
Kojto 148:fd96258d940d 906 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired */
Kojto 148:fd96258d940d 907 __I uint32_t RESERVED4[53];
Kojto 148:fd96258d940d 908 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 909 __I uint32_t RESERVED5[64];
Kojto 148:fd96258d940d 910 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 911 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 912 __I uint32_t RESERVED6[61];
Kojto 148:fd96258d940d 913 __I uint32_t SEMSTAT; /*!< Semaphore status register */
Kojto 148:fd96258d940d 914 __I uint32_t RESERVED7[15];
Kojto 148:fd96258d940d 915 __IO uint32_t STATUS; /*!< Status from last transaction */
Kojto 148:fd96258d940d 916 __I uint32_t RESERVED8[47];
Kojto 148:fd96258d940d 917 __IO uint32_t ENABLE; /*!< Enable SPI slave */
Kojto 148:fd96258d940d 918 __I uint32_t RESERVED9;
Kojto 148:fd96258d940d 919 SPIS_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 920 __I uint32_t RESERVED10[7];
Kojto 148:fd96258d940d 921 SPIS_RXD_Type RXD; /*!< Unspecified */
Kojto 148:fd96258d940d 922 __I uint32_t RESERVED11;
Kojto 148:fd96258d940d 923 SPIS_TXD_Type TXD; /*!< Unspecified */
Kojto 148:fd96258d940d 924 __I uint32_t RESERVED12;
Kojto 148:fd96258d940d 925 __IO uint32_t CONFIG; /*!< Configuration register */
Kojto 148:fd96258d940d 926 __I uint32_t RESERVED13;
Kojto 148:fd96258d940d 927 __IO uint32_t DEF; /*!< Default character. Character clocked out in case of an ignored
Kojto 148:fd96258d940d 928 transaction. */
Kojto 148:fd96258d940d 929 __I uint32_t RESERVED14[24];
Kojto 148:fd96258d940d 930 __IO uint32_t ORC; /*!< Over-read character */
Kojto 148:fd96258d940d 931 } NRF_SPIS_Type;
Kojto 148:fd96258d940d 932
Kojto 148:fd96258d940d 933
Kojto 148:fd96258d940d 934 /* ================================================================================ */
Kojto 148:fd96258d940d 935 /* ================ TWIM ================ */
Kojto 148:fd96258d940d 936 /* ================================================================================ */
Kojto 148:fd96258d940d 937
Kojto 148:fd96258d940d 938
Kojto 148:fd96258d940d 939 /**
Kojto 148:fd96258d940d 940 * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
Kojto 148:fd96258d940d 941 */
Kojto 148:fd96258d940d 942
Kojto 148:fd96258d940d 943 typedef struct { /*!< TWIM Structure */
Kojto 148:fd96258d940d 944 __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
Kojto 148:fd96258d940d 945 __I uint32_t RESERVED0;
Kojto 148:fd96258d940d 946 __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
Kojto 148:fd96258d940d 947 __I uint32_t RESERVED1[2];
Kojto 148:fd96258d940d 948 __O uint32_t TASKS_STOP; /*!< Stop TWI transaction. Must be issued while the TWI master is
Kojto 148:fd96258d940d 949 not suspended. */
Kojto 148:fd96258d940d 950 __I uint32_t RESERVED2;
Kojto 148:fd96258d940d 951 __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
Kojto 148:fd96258d940d 952 __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
Kojto 148:fd96258d940d 953 __I uint32_t RESERVED3[56];
Kojto 148:fd96258d940d 954 __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
Kojto 148:fd96258d940d 955 __I uint32_t RESERVED4[7];
Kojto 148:fd96258d940d 956 __IO uint32_t EVENTS_ERROR; /*!< TWI error */
Kojto 148:fd96258d940d 957 __I uint32_t RESERVED5[8];
Kojto 148:fd96258d940d 958 __IO uint32_t EVENTS_SUSPENDED; /*!< Last byte has been sent out after the SUSPEND task has been
Kojto 148:fd96258d940d 959 issued, TWI traffic is now suspended. */
Kojto 148:fd96258d940d 960 __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
Kojto 148:fd96258d940d 961 __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
Kojto 148:fd96258d940d 962 __I uint32_t RESERVED6[2];
Kojto 148:fd96258d940d 963 __IO uint32_t EVENTS_LASTRX; /*!< Byte boundary, starting to receive the last byte */
Kojto 148:fd96258d940d 964 __IO uint32_t EVENTS_LASTTX; /*!< Byte boundary, starting to transmit the last byte */
Kojto 148:fd96258d940d 965 __I uint32_t RESERVED7[39];
Kojto 148:fd96258d940d 966 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 967 __I uint32_t RESERVED8[63];
Kojto 148:fd96258d940d 968 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 969 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 970 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 971 __I uint32_t RESERVED9[110];
Kojto 148:fd96258d940d 972 __IO uint32_t ERRORSRC; /*!< Error source */
Kojto 148:fd96258d940d 973 __I uint32_t RESERVED10[14];
Kojto 148:fd96258d940d 974 __IO uint32_t ENABLE; /*!< Enable TWIM */
Kojto 148:fd96258d940d 975 __I uint32_t RESERVED11;
Kojto 148:fd96258d940d 976 TWIM_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 977 __I uint32_t RESERVED12[5];
Kojto 148:fd96258d940d 978 __IO uint32_t FREQUENCY; /*!< TWI frequency */
Kojto 148:fd96258d940d 979 __I uint32_t RESERVED13[3];
Kojto 148:fd96258d940d 980 TWIM_RXD_Type RXD; /*!< RXD EasyDMA channel */
Kojto 148:fd96258d940d 981 TWIM_TXD_Type TXD; /*!< TXD EasyDMA channel */
Kojto 148:fd96258d940d 982 __I uint32_t RESERVED14[13];
Kojto 148:fd96258d940d 983 __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
Kojto 148:fd96258d940d 984 } NRF_TWIM_Type;
Kojto 148:fd96258d940d 985
Kojto 148:fd96258d940d 986
Kojto 148:fd96258d940d 987 /* ================================================================================ */
Kojto 148:fd96258d940d 988 /* ================ TWIS ================ */
Kojto 148:fd96258d940d 989 /* ================================================================================ */
Kojto 148:fd96258d940d 990
Kojto 148:fd96258d940d 991
Kojto 148:fd96258d940d 992 /**
Kojto 148:fd96258d940d 993 * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
Kojto 148:fd96258d940d 994 */
Kojto 148:fd96258d940d 995
Kojto 148:fd96258d940d 996 typedef struct { /*!< TWIS Structure */
Kojto 148:fd96258d940d 997 __I uint32_t RESERVED0[5];
Kojto 148:fd96258d940d 998 __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
Kojto 148:fd96258d940d 999 __I uint32_t RESERVED1;
Kojto 148:fd96258d940d 1000 __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
Kojto 148:fd96258d940d 1001 __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
Kojto 148:fd96258d940d 1002 __I uint32_t RESERVED2[3];
Kojto 148:fd96258d940d 1003 __O uint32_t TASKS_PREPARERX; /*!< Prepare the TWI slave to respond to a write command */
Kojto 148:fd96258d940d 1004 __O uint32_t TASKS_PREPARETX; /*!< Prepare the TWI slave to respond to a read command */
Kojto 148:fd96258d940d 1005 __I uint32_t RESERVED3[51];
Kojto 148:fd96258d940d 1006 __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
Kojto 148:fd96258d940d 1007 __I uint32_t RESERVED4[7];
Kojto 148:fd96258d940d 1008 __IO uint32_t EVENTS_ERROR; /*!< TWI error */
Kojto 148:fd96258d940d 1009 __I uint32_t RESERVED5[9];
Kojto 148:fd96258d940d 1010 __IO uint32_t EVENTS_RXSTARTED; /*!< Receive sequence started */
Kojto 148:fd96258d940d 1011 __IO uint32_t EVENTS_TXSTARTED; /*!< Transmit sequence started */
Kojto 148:fd96258d940d 1012 __I uint32_t RESERVED6[4];
Kojto 148:fd96258d940d 1013 __IO uint32_t EVENTS_WRITE; /*!< Write command received */
Kojto 148:fd96258d940d 1014 __IO uint32_t EVENTS_READ; /*!< Read command received */
Kojto 148:fd96258d940d 1015 __I uint32_t RESERVED7[37];
Kojto 148:fd96258d940d 1016 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1017 __I uint32_t RESERVED8[63];
Kojto 148:fd96258d940d 1018 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1019 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1020 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1021 __I uint32_t RESERVED9[113];
Kojto 148:fd96258d940d 1022 __IO uint32_t ERRORSRC; /*!< Error source */
Kojto 148:fd96258d940d 1023 __I uint32_t MATCH; /*!< Status register indicating which address had a match */
Kojto 148:fd96258d940d 1024 __I uint32_t RESERVED10[10];
Kojto 148:fd96258d940d 1025 __IO uint32_t ENABLE; /*!< Enable TWIS */
Kojto 148:fd96258d940d 1026 __I uint32_t RESERVED11;
Kojto 148:fd96258d940d 1027 TWIS_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 1028 __I uint32_t RESERVED12[9];
Kojto 148:fd96258d940d 1029 TWIS_RXD_Type RXD; /*!< RXD EasyDMA channel */
Kojto 148:fd96258d940d 1030 __I uint32_t RESERVED13;
Kojto 148:fd96258d940d 1031 TWIS_TXD_Type TXD; /*!< TXD EasyDMA channel */
Kojto 148:fd96258d940d 1032 __I uint32_t RESERVED14[14];
Kojto 148:fd96258d940d 1033 __IO uint32_t ADDRESS[2]; /*!< Description collection[0]: TWI slave address 0 */
Kojto 148:fd96258d940d 1034 __I uint32_t RESERVED15;
Kojto 148:fd96258d940d 1035 __IO uint32_t CONFIG; /*!< Configuration register for the address match mechanism */
Kojto 148:fd96258d940d 1036 __I uint32_t RESERVED16[10];
Kojto 148:fd96258d940d 1037 __IO uint32_t ORC; /*!< Over-read character. Character sent out in case of an over-read
Kojto 148:fd96258d940d 1038 of the transmit buffer. */
Kojto 148:fd96258d940d 1039 } NRF_TWIS_Type;
Kojto 148:fd96258d940d 1040
Kojto 148:fd96258d940d 1041
Kojto 148:fd96258d940d 1042 /* ================================================================================ */
Kojto 148:fd96258d940d 1043 /* ================ SPI ================ */
Kojto 148:fd96258d940d 1044 /* ================================================================================ */
Kojto 148:fd96258d940d 1045
Kojto 148:fd96258d940d 1046
Kojto 148:fd96258d940d 1047 /**
Kojto 148:fd96258d940d 1048 * @brief Serial Peripheral Interface 0 (SPI)
Kojto 148:fd96258d940d 1049 */
Kojto 148:fd96258d940d 1050
Kojto 148:fd96258d940d 1051 typedef struct { /*!< SPI Structure */
Kojto 148:fd96258d940d 1052 __I uint32_t RESERVED0[66];
Kojto 148:fd96258d940d 1053 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received */
Kojto 148:fd96258d940d 1054 __I uint32_t RESERVED1[126];
Kojto 148:fd96258d940d 1055 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1056 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1057 __I uint32_t RESERVED2[125];
Kojto 148:fd96258d940d 1058 __IO uint32_t ENABLE; /*!< Enable SPI */
Kojto 148:fd96258d940d 1059 __I uint32_t RESERVED3;
Kojto 148:fd96258d940d 1060 SPI_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 1061 __I uint32_t RESERVED4;
Kojto 148:fd96258d940d 1062 __I uint32_t RXD; /*!< RXD register */
Kojto 148:fd96258d940d 1063 __IO uint32_t TXD; /*!< TXD register */
Kojto 148:fd96258d940d 1064 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 1065 __IO uint32_t FREQUENCY; /*!< SPI frequency */
Kojto 148:fd96258d940d 1066 __I uint32_t RESERVED6[11];
Kojto 148:fd96258d940d 1067 __IO uint32_t CONFIG; /*!< Configuration register */
Kojto 148:fd96258d940d 1068 } NRF_SPI_Type;
Kojto 148:fd96258d940d 1069
Kojto 148:fd96258d940d 1070
Kojto 148:fd96258d940d 1071 /* ================================================================================ */
Kojto 148:fd96258d940d 1072 /* ================ TWI ================ */
Kojto 148:fd96258d940d 1073 /* ================================================================================ */
Kojto 148:fd96258d940d 1074
Kojto 148:fd96258d940d 1075
Kojto 148:fd96258d940d 1076 /**
Kojto 148:fd96258d940d 1077 * @brief I2C compatible Two-Wire Interface 0 (TWI)
Kojto 148:fd96258d940d 1078 */
Kojto 148:fd96258d940d 1079
Kojto 148:fd96258d940d 1080 typedef struct { /*!< TWI Structure */
Kojto 148:fd96258d940d 1081 __O uint32_t TASKS_STARTRX; /*!< Start TWI receive sequence */
Kojto 148:fd96258d940d 1082 __I uint32_t RESERVED0;
Kojto 148:fd96258d940d 1083 __O uint32_t TASKS_STARTTX; /*!< Start TWI transmit sequence */
Kojto 148:fd96258d940d 1084 __I uint32_t RESERVED1[2];
Kojto 148:fd96258d940d 1085 __O uint32_t TASKS_STOP; /*!< Stop TWI transaction */
Kojto 148:fd96258d940d 1086 __I uint32_t RESERVED2;
Kojto 148:fd96258d940d 1087 __O uint32_t TASKS_SUSPEND; /*!< Suspend TWI transaction */
Kojto 148:fd96258d940d 1088 __O uint32_t TASKS_RESUME; /*!< Resume TWI transaction */
Kojto 148:fd96258d940d 1089 __I uint32_t RESERVED3[56];
Kojto 148:fd96258d940d 1090 __IO uint32_t EVENTS_STOPPED; /*!< TWI stopped */
Kojto 148:fd96258d940d 1091 __IO uint32_t EVENTS_RXDREADY; /*!< TWI RXD byte received */
Kojto 148:fd96258d940d 1092 __I uint32_t RESERVED4[4];
Kojto 148:fd96258d940d 1093 __IO uint32_t EVENTS_TXDSENT; /*!< TWI TXD byte sent */
Kojto 148:fd96258d940d 1094 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 1095 __IO uint32_t EVENTS_ERROR; /*!< TWI error */
Kojto 148:fd96258d940d 1096 __I uint32_t RESERVED6[4];
Kojto 148:fd96258d940d 1097 __IO uint32_t EVENTS_BB; /*!< TWI byte boundary, generated before each byte that is sent or
Kojto 148:fd96258d940d 1098 received */
Kojto 148:fd96258d940d 1099 __I uint32_t RESERVED7[3];
Kojto 148:fd96258d940d 1100 __IO uint32_t EVENTS_SUSPENDED; /*!< TWI entered the suspended state */
Kojto 148:fd96258d940d 1101 __I uint32_t RESERVED8[45];
Kojto 148:fd96258d940d 1102 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1103 __I uint32_t RESERVED9[64];
Kojto 148:fd96258d940d 1104 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1105 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1106 __I uint32_t RESERVED10[110];
Kojto 148:fd96258d940d 1107 __IO uint32_t ERRORSRC; /*!< Error source */
Kojto 148:fd96258d940d 1108 __I uint32_t RESERVED11[14];
Kojto 148:fd96258d940d 1109 __IO uint32_t ENABLE; /*!< Enable TWI */
Kojto 148:fd96258d940d 1110 __I uint32_t RESERVED12;
Kojto 148:fd96258d940d 1111 __IO uint32_t PSELSCL; /*!< Pin select for SCL */
Kojto 148:fd96258d940d 1112 __IO uint32_t PSELSDA; /*!< Pin select for SDA */
Kojto 148:fd96258d940d 1113 __I uint32_t RESERVED13[2];
Kojto 148:fd96258d940d 1114 __I uint32_t RXD; /*!< RXD register */
Kojto 148:fd96258d940d 1115 __IO uint32_t TXD; /*!< TXD register */
Kojto 148:fd96258d940d 1116 __I uint32_t RESERVED14;
Kojto 148:fd96258d940d 1117 __IO uint32_t FREQUENCY; /*!< TWI frequency */
Kojto 148:fd96258d940d 1118 __I uint32_t RESERVED15[24];
Kojto 148:fd96258d940d 1119 __IO uint32_t ADDRESS; /*!< Address used in the TWI transfer */
Kojto 148:fd96258d940d 1120 } NRF_TWI_Type;
Kojto 148:fd96258d940d 1121
Kojto 148:fd96258d940d 1122
Kojto 148:fd96258d940d 1123 /* ================================================================================ */
Kojto 148:fd96258d940d 1124 /* ================ NFCT ================ */
Kojto 148:fd96258d940d 1125 /* ================================================================================ */
Kojto 148:fd96258d940d 1126
Kojto 148:fd96258d940d 1127
Kojto 148:fd96258d940d 1128 /**
Kojto 148:fd96258d940d 1129 * @brief NFC-A compatible radio (NFCT)
Kojto 148:fd96258d940d 1130 */
Kojto 148:fd96258d940d 1131
Kojto 148:fd96258d940d 1132 typedef struct { /*!< NFCT Structure */
Kojto 148:fd96258d940d 1133 __O uint32_t TASKS_ACTIVATE; /*!< Activate NFC peripheral for incoming and outgoing frames, change
Kojto 148:fd96258d940d 1134 state to activated */
Kojto 148:fd96258d940d 1135 __O uint32_t TASKS_DISABLE; /*!< Disable NFC peripheral */
Kojto 148:fd96258d940d 1136 __O uint32_t TASKS_SENSE; /*!< Enable NFC sense field mode, change state to sense mode */
Kojto 148:fd96258d940d 1137 __O uint32_t TASKS_STARTTX; /*!< Start transmission of a outgoing frame, change state to transmit */
Kojto 148:fd96258d940d 1138 __I uint32_t RESERVED0[3];
Kojto 148:fd96258d940d 1139 __O uint32_t TASKS_ENABLERXDATA; /*!< Initializes the EasyDMA for receive. */
Kojto 148:fd96258d940d 1140 __I uint32_t RESERVED1;
Kojto 148:fd96258d940d 1141 __O uint32_t TASKS_GOIDLE; /*!< Force state machine to IDLE state */
Kojto 148:fd96258d940d 1142 __O uint32_t TASKS_GOSLEEP; /*!< Force state machine to SLEEP_A state */
Kojto 148:fd96258d940d 1143 __I uint32_t RESERVED2[53];
Kojto 148:fd96258d940d 1144 __IO uint32_t EVENTS_READY; /*!< The NFC peripheral is ready to receive and send frames */
Kojto 148:fd96258d940d 1145 __IO uint32_t EVENTS_FIELDDETECTED; /*!< Remote NFC field detected */
Kojto 148:fd96258d940d 1146 __IO uint32_t EVENTS_FIELDLOST; /*!< Remote NFC field lost */
Kojto 148:fd96258d940d 1147 __IO uint32_t EVENTS_TXFRAMESTART; /*!< Marks the start of the first symbol of a transmitted frame */
Kojto 148:fd96258d940d 1148 __IO uint32_t EVENTS_TXFRAMEEND; /*!< Marks the end of the last transmitted on-air symbol of a frame */
Kojto 148:fd96258d940d 1149 __IO uint32_t EVENTS_RXFRAMESTART; /*!< Marks the end of the first symbol of a received frame */
Kojto 148:fd96258d940d 1150 __IO uint32_t EVENTS_RXFRAMEEND; /*!< Received data have been checked (CRC, parity) and transferred
Kojto 148:fd96258d940d 1151 to RAM, and EasyDMA has ended accessing the RX buffer */
Kojto 148:fd96258d940d 1152 __IO uint32_t EVENTS_ERROR; /*!< NFC error reported. The ERRORSTATUS register contains details
Kojto 148:fd96258d940d 1153 on the source of the error. */
Kojto 148:fd96258d940d 1154 __I uint32_t RESERVED3[2];
Kojto 148:fd96258d940d 1155 __IO uint32_t EVENTS_RXERROR; /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
Kojto 148:fd96258d940d 1156 details on the source of the error. */
Kojto 148:fd96258d940d 1157 __IO uint32_t EVENTS_ENDRX; /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full. */
Kojto 148:fd96258d940d 1158 __IO uint32_t EVENTS_ENDTX; /*!< Transmission of data in RAM has ended, and EasyDMA has ended
Kojto 148:fd96258d940d 1159 accessing the TX buffer */
Kojto 148:fd96258d940d 1160 __I uint32_t RESERVED4;
Kojto 148:fd96258d940d 1161 __IO uint32_t EVENTS_AUTOCOLRESSTARTED; /*!< Auto collision resolution process has started */
Kojto 148:fd96258d940d 1162 __I uint32_t RESERVED5[3];
Kojto 148:fd96258d940d 1163 __IO uint32_t EVENTS_COLLISION; /*!< NFC Auto collision resolution error reported. */
Kojto 148:fd96258d940d 1164 __IO uint32_t EVENTS_SELECTED; /*!< NFC Auto collision resolution successfully completed */
Kojto 148:fd96258d940d 1165 __IO uint32_t EVENTS_STARTED; /*!< EasyDMA is ready to receive or send frames. */
Kojto 148:fd96258d940d 1166 __I uint32_t RESERVED6[43];
Kojto 148:fd96258d940d 1167 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1168 __I uint32_t RESERVED7[63];
Kojto 148:fd96258d940d 1169 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1170 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1171 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1172 __I uint32_t RESERVED8[62];
Kojto 148:fd96258d940d 1173 __IO uint32_t ERRORSTATUS; /*!< NFC Error Status register */
Kojto 148:fd96258d940d 1174 __I uint32_t RESERVED9;
Kojto 148:fd96258d940d 1175 NFCT_FRAMESTATUS_Type FRAMESTATUS; /*!< Unspecified */
Kojto 148:fd96258d940d 1176 __I uint32_t RESERVED10[8];
Kojto 148:fd96258d940d 1177 __I uint32_t CURRENTLOADCTRL; /*!< Current value driven to the NFC Load Control */
Kojto 148:fd96258d940d 1178 __I uint32_t RESERVED11[2];
Kojto 148:fd96258d940d 1179 __I uint32_t FIELDPRESENT; /*!< Indicates the presence or not of a valid field */
Kojto 148:fd96258d940d 1180 __I uint32_t RESERVED12[49];
Kojto 148:fd96258d940d 1181 __IO uint32_t FRAMEDELAYMIN; /*!< Minimum frame delay */
Kojto 148:fd96258d940d 1182 __IO uint32_t FRAMEDELAYMAX; /*!< Maximum frame delay */
Kojto 148:fd96258d940d 1183 __IO uint32_t FRAMEDELAYMODE; /*!< Configuration register for the Frame Delay Timer */
Kojto 148:fd96258d940d 1184 __IO uint32_t PACKETPTR; /*!< Packet pointer for TXD and RXD data storage in Data RAM */
Kojto 148:fd96258d940d 1185 __IO uint32_t MAXLEN; /*!< Size of allocated for TXD and RXD data storage buffer in Data
Kojto 148:fd96258d940d 1186 RAM */
Kojto 148:fd96258d940d 1187 NFCT_TXD_Type TXD; /*!< Unspecified */
Kojto 148:fd96258d940d 1188 NFCT_RXD_Type RXD; /*!< Unspecified */
Kojto 148:fd96258d940d 1189 __I uint32_t RESERVED13[26];
Kojto 148:fd96258d940d 1190 __IO uint32_t NFCID1_LAST; /*!< Last NFCID1 part (4, 7 or 10 bytes ID) */
Kojto 148:fd96258d940d 1191 __IO uint32_t NFCID1_2ND_LAST; /*!< Second last NFCID1 part (7 or 10 bytes ID) */
Kojto 148:fd96258d940d 1192 __IO uint32_t NFCID1_3RD_LAST; /*!< Third last NFCID1 part (10 bytes ID) */
Kojto 148:fd96258d940d 1193 __I uint32_t RESERVED14;
Kojto 148:fd96258d940d 1194 __IO uint32_t SENSRES; /*!< NFC-A SENS_RES auto-response settings */
Kojto 148:fd96258d940d 1195 __IO uint32_t SELRES; /*!< NFC-A SEL_RES auto-response settings */
Kojto 148:fd96258d940d 1196 } NRF_NFCT_Type;
Kojto 148:fd96258d940d 1197
Kojto 148:fd96258d940d 1198
Kojto 148:fd96258d940d 1199 /* ================================================================================ */
Kojto 148:fd96258d940d 1200 /* ================ GPIOTE ================ */
Kojto 148:fd96258d940d 1201 /* ================================================================================ */
Kojto 148:fd96258d940d 1202
Kojto 148:fd96258d940d 1203
Kojto 148:fd96258d940d 1204 /**
Kojto 148:fd96258d940d 1205 * @brief GPIO Tasks and Events (GPIOTE)
Kojto 148:fd96258d940d 1206 */
Kojto 148:fd96258d940d 1207
Kojto 148:fd96258d940d 1208 typedef struct { /*!< GPIOTE Structure */
Kojto 148:fd96258d940d 1209 __O uint32_t TASKS_OUT[8]; /*!< Description collection[0]: Task for writing to pin specified
Kojto 148:fd96258d940d 1210 in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
Kojto 148:fd96258d940d 1211 __I uint32_t RESERVED0[4];
Kojto 148:fd96258d940d 1212 __O uint32_t TASKS_SET[8]; /*!< Description collection[0]: Task for writing to pin specified
Kojto 148:fd96258d940d 1213 in CONFIG[0].PSEL. Action on pin is to set it high. */
Kojto 148:fd96258d940d 1214 __I uint32_t RESERVED1[4];
Kojto 148:fd96258d940d 1215 __O uint32_t TASKS_CLR[8]; /*!< Description collection[0]: Task for writing to pin specified
Kojto 148:fd96258d940d 1216 in CONFIG[0].PSEL. Action on pin is to set it low. */
Kojto 148:fd96258d940d 1217 __I uint32_t RESERVED2[32];
Kojto 148:fd96258d940d 1218 __IO uint32_t EVENTS_IN[8]; /*!< Description collection[0]: Event generated from pin specified
Kojto 148:fd96258d940d 1219 in CONFIG[0].PSEL */
Kojto 148:fd96258d940d 1220 __I uint32_t RESERVED3[23];
Kojto 148:fd96258d940d 1221 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple input GPIO pins with SENSE mechanism
Kojto 148:fd96258d940d 1222 enabled */
Kojto 148:fd96258d940d 1223 __I uint32_t RESERVED4[97];
Kojto 148:fd96258d940d 1224 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1225 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1226 __I uint32_t RESERVED5[129];
Kojto 148:fd96258d940d 1227 __IO uint32_t CONFIG[8]; /*!< Description collection[0]: Configuration for OUT[n], SET[n]
Kojto 148:fd96258d940d 1228 and CLR[n] tasks and IN[n] event */
Kojto 148:fd96258d940d 1229 } NRF_GPIOTE_Type;
Kojto 148:fd96258d940d 1230
Kojto 148:fd96258d940d 1231
Kojto 148:fd96258d940d 1232 /* ================================================================================ */
Kojto 148:fd96258d940d 1233 /* ================ SAADC ================ */
Kojto 148:fd96258d940d 1234 /* ================================================================================ */
Kojto 148:fd96258d940d 1235
Kojto 148:fd96258d940d 1236
Kojto 148:fd96258d940d 1237 /**
Kojto 148:fd96258d940d 1238 * @brief Analog to Digital Converter (SAADC)
Kojto 148:fd96258d940d 1239 */
Kojto 148:fd96258d940d 1240
Kojto 148:fd96258d940d 1241 typedef struct { /*!< SAADC Structure */
Kojto 148:fd96258d940d 1242 __O uint32_t TASKS_START; /*!< Start the ADC and prepare the result buffer in RAM */
Kojto 148:fd96258d940d 1243 __O uint32_t TASKS_SAMPLE; /*!< Take one ADC sample, if scan is enabled all channels are sampled */
Kojto 148:fd96258d940d 1244 __O uint32_t TASKS_STOP; /*!< Stop the ADC and terminate any on-going conversion */
Kojto 148:fd96258d940d 1245 __O uint32_t TASKS_CALIBRATEOFFSET; /*!< Starts offset auto-calibration */
Kojto 148:fd96258d940d 1246 __I uint32_t RESERVED0[60];
Kojto 148:fd96258d940d 1247 __IO uint32_t EVENTS_STARTED; /*!< The ADC has started */
Kojto 148:fd96258d940d 1248 __IO uint32_t EVENTS_END; /*!< The ADC has filled up the Result buffer */
Kojto 148:fd96258d940d 1249 __IO uint32_t EVENTS_DONE; /*!< A conversion task has been completed. Depending on the mode,
Kojto 148:fd96258d940d 1250 multiple conversions might be needed for a result to be transferred
Kojto 148:fd96258d940d 1251 to RAM. */
Kojto 148:fd96258d940d 1252 __IO uint32_t EVENTS_RESULTDONE; /*!< A result is ready to get transferred to RAM. */
Kojto 148:fd96258d940d 1253 __IO uint32_t EVENTS_CALIBRATEDONE; /*!< Calibration is complete */
Kojto 148:fd96258d940d 1254 __IO uint32_t EVENTS_STOPPED; /*!< The ADC has stopped */
Kojto 148:fd96258d940d 1255 SAADC_EVENTS_CH_Type EVENTS_CH[8]; /*!< Unspecified */
Kojto 148:fd96258d940d 1256 __I uint32_t RESERVED1[106];
Kojto 148:fd96258d940d 1257 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1258 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1259 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1260 __I uint32_t RESERVED2[61];
Kojto 148:fd96258d940d 1261 __I uint32_t STATUS; /*!< Status */
Kojto 148:fd96258d940d 1262 __I uint32_t RESERVED3[63];
Kojto 148:fd96258d940d 1263 __IO uint32_t ENABLE; /*!< Enable or disable ADC */
Kojto 148:fd96258d940d 1264 __I uint32_t RESERVED4[3];
Kojto 148:fd96258d940d 1265 SAADC_CH_Type CH[8]; /*!< Unspecified */
Kojto 148:fd96258d940d 1266 __I uint32_t RESERVED5[24];
Kojto 148:fd96258d940d 1267 __IO uint32_t RESOLUTION; /*!< Resolution configuration */
Kojto 148:fd96258d940d 1268 __IO uint32_t OVERSAMPLE; /*!< Oversampling configuration. OVERSAMPLE should not be combined
Kojto 148:fd96258d940d 1269 with SCAN. The RESOLUTION is applied before averaging, thus
Kojto 148:fd96258d940d 1270 for high OVERSAMPLE a higher RESOLUTION should be used. */
Kojto 148:fd96258d940d 1271 __IO uint32_t SAMPLERATE; /*!< Controls normal or continuous sample rate */
Kojto 148:fd96258d940d 1272 __I uint32_t RESERVED6[12];
Kojto 148:fd96258d940d 1273 SAADC_RESULT_Type RESULT; /*!< RESULT EasyDMA channel */
Kojto 148:fd96258d940d 1274 } NRF_SAADC_Type;
Kojto 148:fd96258d940d 1275
Kojto 148:fd96258d940d 1276
Kojto 148:fd96258d940d 1277 /* ================================================================================ */
Kojto 148:fd96258d940d 1278 /* ================ TIMER ================ */
Kojto 148:fd96258d940d 1279 /* ================================================================================ */
Kojto 148:fd96258d940d 1280
Kojto 148:fd96258d940d 1281
Kojto 148:fd96258d940d 1282 /**
Kojto 148:fd96258d940d 1283 * @brief Timer/Counter 0 (TIMER)
Kojto 148:fd96258d940d 1284 */
Kojto 148:fd96258d940d 1285
Kojto 148:fd96258d940d 1286 typedef struct { /*!< TIMER Structure */
Kojto 148:fd96258d940d 1287 __O uint32_t TASKS_START; /*!< Start Timer */
Kojto 148:fd96258d940d 1288 __O uint32_t TASKS_STOP; /*!< Stop Timer */
Kojto 148:fd96258d940d 1289 __O uint32_t TASKS_COUNT; /*!< Increment Timer (Counter mode only) */
Kojto 148:fd96258d940d 1290 __O uint32_t TASKS_CLEAR; /*!< Clear time */
Kojto 148:fd96258d940d 1291 __O uint32_t TASKS_SHUTDOWN; /*!< Deprecated register - Shut down timer */
Kojto 148:fd96258d940d 1292 __I uint32_t RESERVED0[11];
Kojto 148:fd96258d940d 1293 __O uint32_t TASKS_CAPTURE[6]; /*!< Description collection[0]: Capture Timer value to CC[0] register */
Kojto 148:fd96258d940d 1294 __I uint32_t RESERVED1[58];
Kojto 148:fd96258d940d 1295 __IO uint32_t EVENTS_COMPARE[6]; /*!< Description collection[0]: Compare event on CC[0] match */
Kojto 148:fd96258d940d 1296 __I uint32_t RESERVED2[42];
Kojto 148:fd96258d940d 1297 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1298 __I uint32_t RESERVED3[64];
Kojto 148:fd96258d940d 1299 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1300 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1301 __I uint32_t RESERVED4[126];
Kojto 148:fd96258d940d 1302 __IO uint32_t MODE; /*!< Timer mode selection */
Kojto 148:fd96258d940d 1303 __IO uint32_t BITMODE; /*!< Configure the number of bits used by the TIMER */
Kojto 148:fd96258d940d 1304 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 1305 __IO uint32_t PRESCALER; /*!< Timer prescaler register */
Kojto 148:fd96258d940d 1306 __I uint32_t RESERVED6[11];
Kojto 148:fd96258d940d 1307 __IO uint32_t CC[6]; /*!< Description collection[0]: Capture/Compare register 0 */
Kojto 148:fd96258d940d 1308 } NRF_TIMER_Type;
Kojto 148:fd96258d940d 1309
Kojto 148:fd96258d940d 1310
Kojto 148:fd96258d940d 1311 /* ================================================================================ */
Kojto 148:fd96258d940d 1312 /* ================ RTC ================ */
Kojto 148:fd96258d940d 1313 /* ================================================================================ */
Kojto 148:fd96258d940d 1314
Kojto 148:fd96258d940d 1315
Kojto 148:fd96258d940d 1316 /**
Kojto 148:fd96258d940d 1317 * @brief Real time counter 0 (RTC)
Kojto 148:fd96258d940d 1318 */
Kojto 148:fd96258d940d 1319
Kojto 148:fd96258d940d 1320 typedef struct { /*!< RTC Structure */
Kojto 148:fd96258d940d 1321 __O uint32_t TASKS_START; /*!< Start RTC COUNTER */
Kojto 148:fd96258d940d 1322 __O uint32_t TASKS_STOP; /*!< Stop RTC COUNTER */
Kojto 148:fd96258d940d 1323 __O uint32_t TASKS_CLEAR; /*!< Clear RTC COUNTER */
Kojto 148:fd96258d940d 1324 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFF0 */
Kojto 148:fd96258d940d 1325 __I uint32_t RESERVED0[60];
Kojto 148:fd96258d940d 1326 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment */
Kojto 148:fd96258d940d 1327 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow */
Kojto 148:fd96258d940d 1328 __I uint32_t RESERVED1[14];
Kojto 148:fd96258d940d 1329 __IO uint32_t EVENTS_COMPARE[4]; /*!< Description collection[0]: Compare event on CC[0] match */
Kojto 148:fd96258d940d 1330 __I uint32_t RESERVED2[109];
Kojto 148:fd96258d940d 1331 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1332 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1333 __I uint32_t RESERVED3[13];
Kojto 148:fd96258d940d 1334 __IO uint32_t EVTEN; /*!< Enable or disable event routing */
Kojto 148:fd96258d940d 1335 __IO uint32_t EVTENSET; /*!< Enable event routing */
Kojto 148:fd96258d940d 1336 __IO uint32_t EVTENCLR; /*!< Disable event routing */
Kojto 148:fd96258d940d 1337 __I uint32_t RESERVED4[110];
Kojto 148:fd96258d940d 1338 __I uint32_t COUNTER; /*!< Current COUNTER value */
Kojto 148:fd96258d940d 1339 __IO uint32_t PRESCALER; /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
Kojto 148:fd96258d940d 1340 be written when RTC is stopped */
Kojto 148:fd96258d940d 1341 __I uint32_t RESERVED5[13];
Kojto 148:fd96258d940d 1342 __IO uint32_t CC[4]; /*!< Description collection[0]: Compare register 0 */
Kojto 148:fd96258d940d 1343 } NRF_RTC_Type;
Kojto 148:fd96258d940d 1344
Kojto 148:fd96258d940d 1345
Kojto 148:fd96258d940d 1346 /* ================================================================================ */
Kojto 148:fd96258d940d 1347 /* ================ TEMP ================ */
Kojto 148:fd96258d940d 1348 /* ================================================================================ */
Kojto 148:fd96258d940d 1349
Kojto 148:fd96258d940d 1350
Kojto 148:fd96258d940d 1351 /**
Kojto 148:fd96258d940d 1352 * @brief Temperature Sensor (TEMP)
Kojto 148:fd96258d940d 1353 */
Kojto 148:fd96258d940d 1354
Kojto 148:fd96258d940d 1355 typedef struct { /*!< TEMP Structure */
Kojto 148:fd96258d940d 1356 __O uint32_t TASKS_START; /*!< Start temperature measurement */
Kojto 148:fd96258d940d 1357 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement */
Kojto 148:fd96258d940d 1358 __I uint32_t RESERVED0[62];
Kojto 148:fd96258d940d 1359 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready */
Kojto 148:fd96258d940d 1360 __I uint32_t RESERVED1[128];
Kojto 148:fd96258d940d 1361 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1362 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1363 __I uint32_t RESERVED2[127];
Kojto 148:fd96258d940d 1364 __I int32_t TEMP; /*!< Temperature in degC (0.25deg steps) */
Kojto 148:fd96258d940d 1365 __I uint32_t RESERVED3[5];
Kojto 148:fd96258d940d 1366 __IO uint32_t A0; /*!< Slope of 1st piece wise linear function */
Kojto 148:fd96258d940d 1367 __IO uint32_t A1; /*!< Slope of 2nd piece wise linear function */
Kojto 148:fd96258d940d 1368 __IO uint32_t A2; /*!< Slope of 3rd piece wise linear function */
Kojto 148:fd96258d940d 1369 __IO uint32_t A3; /*!< Slope of 4th piece wise linear function */
Kojto 148:fd96258d940d 1370 __IO uint32_t A4; /*!< Slope of 5th piece wise linear function */
Kojto 148:fd96258d940d 1371 __IO uint32_t A5; /*!< Slope of 6th piece wise linear function */
Kojto 148:fd96258d940d 1372 __I uint32_t RESERVED4[2];
Kojto 148:fd96258d940d 1373 __IO uint32_t B0; /*!< y-intercept of 1st piece wise linear function */
Kojto 148:fd96258d940d 1374 __IO uint32_t B1; /*!< y-intercept of 2nd piece wise linear function */
Kojto 148:fd96258d940d 1375 __IO uint32_t B2; /*!< y-intercept of 3rd piece wise linear function */
Kojto 148:fd96258d940d 1376 __IO uint32_t B3; /*!< y-intercept of 4th piece wise linear function */
Kojto 148:fd96258d940d 1377 __IO uint32_t B4; /*!< y-intercept of 5th piece wise linear function */
Kojto 148:fd96258d940d 1378 __IO uint32_t B5; /*!< y-intercept of 6th piece wise linear function */
Kojto 148:fd96258d940d 1379 __I uint32_t RESERVED5[2];
Kojto 148:fd96258d940d 1380 __IO uint32_t T0; /*!< End point of 1st piece wise linear function */
Kojto 148:fd96258d940d 1381 __IO uint32_t T1; /*!< End point of 2nd piece wise linear function */
Kojto 148:fd96258d940d 1382 __IO uint32_t T2; /*!< End point of 3rd piece wise linear function */
Kojto 148:fd96258d940d 1383 __IO uint32_t T3; /*!< End point of 4th piece wise linear function */
Kojto 148:fd96258d940d 1384 __IO uint32_t T4; /*!< End point of 5th piece wise linear function */
Kojto 148:fd96258d940d 1385 } NRF_TEMP_Type;
Kojto 148:fd96258d940d 1386
Kojto 148:fd96258d940d 1387
Kojto 148:fd96258d940d 1388 /* ================================================================================ */
Kojto 148:fd96258d940d 1389 /* ================ RNG ================ */
Kojto 148:fd96258d940d 1390 /* ================================================================================ */
Kojto 148:fd96258d940d 1391
Kojto 148:fd96258d940d 1392
Kojto 148:fd96258d940d 1393 /**
Kojto 148:fd96258d940d 1394 * @brief Random Number Generator (RNG)
Kojto 148:fd96258d940d 1395 */
Kojto 148:fd96258d940d 1396
Kojto 148:fd96258d940d 1397 typedef struct { /*!< RNG Structure */
Kojto 148:fd96258d940d 1398 __O uint32_t TASKS_START; /*!< Task starting the random number generator */
Kojto 148:fd96258d940d 1399 __O uint32_t TASKS_STOP; /*!< Task stopping the random number generator */
Kojto 148:fd96258d940d 1400 __I uint32_t RESERVED0[62];
Kojto 148:fd96258d940d 1401 __IO uint32_t EVENTS_VALRDY; /*!< Event being generated for every new random number written to
Kojto 148:fd96258d940d 1402 the VALUE register */
Kojto 148:fd96258d940d 1403 __I uint32_t RESERVED1[63];
Kojto 148:fd96258d940d 1404 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1405 __I uint32_t RESERVED2[64];
Kojto 148:fd96258d940d 1406 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1407 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1408 __I uint32_t RESERVED3[126];
Kojto 148:fd96258d940d 1409 __IO uint32_t CONFIG; /*!< Configuration register */
Kojto 148:fd96258d940d 1410 __I uint32_t VALUE; /*!< Output random number */
Kojto 148:fd96258d940d 1411 } NRF_RNG_Type;
Kojto 148:fd96258d940d 1412
Kojto 148:fd96258d940d 1413
Kojto 148:fd96258d940d 1414 /* ================================================================================ */
Kojto 148:fd96258d940d 1415 /* ================ ECB ================ */
Kojto 148:fd96258d940d 1416 /* ================================================================================ */
Kojto 148:fd96258d940d 1417
Kojto 148:fd96258d940d 1418
Kojto 148:fd96258d940d 1419 /**
Kojto 148:fd96258d940d 1420 * @brief AES ECB Mode Encryption (ECB)
Kojto 148:fd96258d940d 1421 */
Kojto 148:fd96258d940d 1422
Kojto 148:fd96258d940d 1423 typedef struct { /*!< ECB Structure */
Kojto 148:fd96258d940d 1424 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt */
Kojto 148:fd96258d940d 1425 __O uint32_t TASKS_STOPECB; /*!< Abort a possible executing ECB operation */
Kojto 148:fd96258d940d 1426 __I uint32_t RESERVED0[62];
Kojto 148:fd96258d940d 1427 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete */
Kojto 148:fd96258d940d 1428 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted because of a STOPECB task or due to
Kojto 148:fd96258d940d 1429 an error */
Kojto 148:fd96258d940d 1430 __I uint32_t RESERVED1[127];
Kojto 148:fd96258d940d 1431 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1432 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1433 __I uint32_t RESERVED2[126];
Kojto 148:fd96258d940d 1434 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointers */
Kojto 148:fd96258d940d 1435 } NRF_ECB_Type;
Kojto 148:fd96258d940d 1436
Kojto 148:fd96258d940d 1437
Kojto 148:fd96258d940d 1438 /* ================================================================================ */
Kojto 148:fd96258d940d 1439 /* ================ CCM ================ */
Kojto 148:fd96258d940d 1440 /* ================================================================================ */
Kojto 148:fd96258d940d 1441
Kojto 148:fd96258d940d 1442
Kojto 148:fd96258d940d 1443 /**
Kojto 148:fd96258d940d 1444 * @brief AES CCM Mode Encryption (CCM)
Kojto 148:fd96258d940d 1445 */
Kojto 148:fd96258d940d 1446
Kojto 148:fd96258d940d 1447 typedef struct { /*!< CCM Structure */
Kojto 148:fd96258d940d 1448 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
Kojto 148:fd96258d940d 1449 itself when completed. */
Kojto 148:fd96258d940d 1450 __O uint32_t TASKS_CRYPT; /*!< Start encryption/decryption. This operation will stop by itself
Kojto 148:fd96258d940d 1451 when completed. */
Kojto 148:fd96258d940d 1452 __O uint32_t TASKS_STOP; /*!< Stop encryption/decryption */
Kojto 148:fd96258d940d 1453 __I uint32_t RESERVED0[61];
Kojto 148:fd96258d940d 1454 __IO uint32_t EVENTS_ENDKSGEN; /*!< Key-stream generation complete */
Kojto 148:fd96258d940d 1455 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt complete */
Kojto 148:fd96258d940d 1456 __IO uint32_t EVENTS_ERROR; /*!< CCM error event */
Kojto 148:fd96258d940d 1457 __I uint32_t RESERVED1[61];
Kojto 148:fd96258d940d 1458 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1459 __I uint32_t RESERVED2[64];
Kojto 148:fd96258d940d 1460 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1461 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1462 __I uint32_t RESERVED3[61];
Kojto 148:fd96258d940d 1463 __I uint32_t MICSTATUS; /*!< MIC check result */
Kojto 148:fd96258d940d 1464 __I uint32_t RESERVED4[63];
Kojto 148:fd96258d940d 1465 __IO uint32_t ENABLE; /*!< Enable */
Kojto 148:fd96258d940d 1466 __IO uint32_t MODE; /*!< Operation mode */
Kojto 148:fd96258d940d 1467 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector */
Kojto 148:fd96258d940d 1468 __IO uint32_t INPTR; /*!< Input pointer */
Kojto 148:fd96258d940d 1469 __IO uint32_t OUTPTR; /*!< Output pointer */
Kojto 148:fd96258d940d 1470 __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */
Kojto 148:fd96258d940d 1471 } NRF_CCM_Type;
Kojto 148:fd96258d940d 1472
Kojto 148:fd96258d940d 1473
Kojto 148:fd96258d940d 1474 /* ================================================================================ */
Kojto 148:fd96258d940d 1475 /* ================ AAR ================ */
Kojto 148:fd96258d940d 1476 /* ================================================================================ */
Kojto 148:fd96258d940d 1477
Kojto 148:fd96258d940d 1478
Kojto 148:fd96258d940d 1479 /**
Kojto 148:fd96258d940d 1480 * @brief Accelerated Address Resolver (AAR)
Kojto 148:fd96258d940d 1481 */
Kojto 148:fd96258d940d 1482
Kojto 148:fd96258d940d 1483 typedef struct { /*!< AAR Structure */
Kojto 148:fd96258d940d 1484 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
Kojto 148:fd96258d940d 1485 data structure */
Kojto 148:fd96258d940d 1486 __I uint32_t RESERVED0;
Kojto 148:fd96258d940d 1487 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses */
Kojto 148:fd96258d940d 1488 __I uint32_t RESERVED1[61];
Kojto 148:fd96258d940d 1489 __IO uint32_t EVENTS_END; /*!< Address resolution procedure complete */
Kojto 148:fd96258d940d 1490 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved */
Kojto 148:fd96258d940d 1491 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved */
Kojto 148:fd96258d940d 1492 __I uint32_t RESERVED2[126];
Kojto 148:fd96258d940d 1493 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1494 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1495 __I uint32_t RESERVED3[61];
Kojto 148:fd96258d940d 1496 __I uint32_t STATUS; /*!< Resolution status */
Kojto 148:fd96258d940d 1497 __I uint32_t RESERVED4[63];
Kojto 148:fd96258d940d 1498 __IO uint32_t ENABLE; /*!< Enable AAR */
Kojto 148:fd96258d940d 1499 __IO uint32_t NIRK; /*!< Number of IRKs */
Kojto 148:fd96258d940d 1500 __IO uint32_t IRKPTR; /*!< Pointer to IRK data structure */
Kojto 148:fd96258d940d 1501 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 1502 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address */
Kojto 148:fd96258d940d 1503 __IO uint32_t SCRATCHPTR; /*!< Pointer to data area used for temporary storage */
Kojto 148:fd96258d940d 1504 } NRF_AAR_Type;
Kojto 148:fd96258d940d 1505
Kojto 148:fd96258d940d 1506
Kojto 148:fd96258d940d 1507 /* ================================================================================ */
Kojto 148:fd96258d940d 1508 /* ================ WDT ================ */
Kojto 148:fd96258d940d 1509 /* ================================================================================ */
Kojto 148:fd96258d940d 1510
Kojto 148:fd96258d940d 1511
Kojto 148:fd96258d940d 1512 /**
Kojto 148:fd96258d940d 1513 * @brief Watchdog Timer (WDT)
Kojto 148:fd96258d940d 1514 */
Kojto 148:fd96258d940d 1515
Kojto 148:fd96258d940d 1516 typedef struct { /*!< WDT Structure */
Kojto 148:fd96258d940d 1517 __O uint32_t TASKS_START; /*!< Start the watchdog */
Kojto 148:fd96258d940d 1518 __I uint32_t RESERVED0[63];
Kojto 148:fd96258d940d 1519 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout */
Kojto 148:fd96258d940d 1520 __I uint32_t RESERVED1[128];
Kojto 148:fd96258d940d 1521 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1522 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1523 __I uint32_t RESERVED2[61];
Kojto 148:fd96258d940d 1524 __I uint32_t RUNSTATUS; /*!< Run status */
Kojto 148:fd96258d940d 1525 __I uint32_t REQSTATUS; /*!< Request status */
Kojto 148:fd96258d940d 1526 __I uint32_t RESERVED3[63];
Kojto 148:fd96258d940d 1527 __IO uint32_t CRV; /*!< Counter reload value */
Kojto 148:fd96258d940d 1528 __IO uint32_t RREN; /*!< Enable register for reload request registers */
Kojto 148:fd96258d940d 1529 __IO uint32_t CONFIG; /*!< Configuration register */
Kojto 148:fd96258d940d 1530 __I uint32_t RESERVED4[60];
Kojto 148:fd96258d940d 1531 __O uint32_t RR[8]; /*!< Description collection[0]: Reload request 0 */
Kojto 148:fd96258d940d 1532 } NRF_WDT_Type;
Kojto 148:fd96258d940d 1533
Kojto 148:fd96258d940d 1534
Kojto 148:fd96258d940d 1535 /* ================================================================================ */
Kojto 148:fd96258d940d 1536 /* ================ QDEC ================ */
Kojto 148:fd96258d940d 1537 /* ================================================================================ */
Kojto 148:fd96258d940d 1538
Kojto 148:fd96258d940d 1539
Kojto 148:fd96258d940d 1540 /**
Kojto 148:fd96258d940d 1541 * @brief Quadrature Decoder (QDEC)
Kojto 148:fd96258d940d 1542 */
Kojto 148:fd96258d940d 1543
Kojto 148:fd96258d940d 1544 typedef struct { /*!< QDEC Structure */
Kojto 148:fd96258d940d 1545 __O uint32_t TASKS_START; /*!< Task starting the quadrature decoder */
Kojto 148:fd96258d940d 1546 __O uint32_t TASKS_STOP; /*!< Task stopping the quadrature decoder */
Kojto 148:fd96258d940d 1547 __O uint32_t TASKS_READCLRACC; /*!< Read and clear ACC and ACCDBL */
Kojto 148:fd96258d940d 1548 __O uint32_t TASKS_RDCLRACC; /*!< Read and clear ACC */
Kojto 148:fd96258d940d 1549 __O uint32_t TASKS_RDCLRDBL; /*!< Read and clear ACCDBL */
Kojto 148:fd96258d940d 1550 __I uint32_t RESERVED0[59];
Kojto 148:fd96258d940d 1551 __IO uint32_t EVENTS_SAMPLERDY; /*!< Event being generated for every new sample value written to
Kojto 148:fd96258d940d 1552 the SAMPLE register */
Kojto 148:fd96258d940d 1553 __IO uint32_t EVENTS_REPORTRDY; /*!< Non-null report ready */
Kojto 148:fd96258d940d 1554 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow */
Kojto 148:fd96258d940d 1555 __IO uint32_t EVENTS_DBLRDY; /*!< Double displacement(s) detected */
Kojto 148:fd96258d940d 1556 __IO uint32_t EVENTS_STOPPED; /*!< QDEC has been stopped */
Kojto 148:fd96258d940d 1557 __I uint32_t RESERVED1[59];
Kojto 148:fd96258d940d 1558 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1559 __I uint32_t RESERVED2[64];
Kojto 148:fd96258d940d 1560 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1561 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1562 __I uint32_t RESERVED3[125];
Kojto 148:fd96258d940d 1563 __IO uint32_t ENABLE; /*!< Enable the quadrature decoder */
Kojto 148:fd96258d940d 1564 __IO uint32_t LEDPOL; /*!< LED output pin polarity */
Kojto 148:fd96258d940d 1565 __IO uint32_t SAMPLEPER; /*!< Sample period */
Kojto 148:fd96258d940d 1566 __I int32_t SAMPLE; /*!< Motion sample value */
Kojto 148:fd96258d940d 1567 __IO uint32_t REPORTPER; /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
Kojto 148:fd96258d940d 1568 can be generated */
Kojto 148:fd96258d940d 1569 __I int32_t ACC; /*!< Register accumulating the valid transitions */
Kojto 148:fd96258d940d 1570 __I int32_t ACCREAD; /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
Kojto 148:fd96258d940d 1571 task */
Kojto 148:fd96258d940d 1572 QDEC_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 1573 __IO uint32_t DBFEN; /*!< Enable input debounce filters */
Kojto 148:fd96258d940d 1574 __I uint32_t RESERVED4[5];
Kojto 148:fd96258d940d 1575 __IO uint32_t LEDPRE; /*!< Time period the LED is switched ON prior to sampling */
Kojto 148:fd96258d940d 1576 __I uint32_t ACCDBL; /*!< Register accumulating the number of detected double transitions */
Kojto 148:fd96258d940d 1577 __I uint32_t ACCDBLREAD; /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
Kojto 148:fd96258d940d 1578 task */
Kojto 148:fd96258d940d 1579 } NRF_QDEC_Type;
Kojto 148:fd96258d940d 1580
Kojto 148:fd96258d940d 1581
Kojto 148:fd96258d940d 1582 /* ================================================================================ */
Kojto 148:fd96258d940d 1583 /* ================ COMP ================ */
Kojto 148:fd96258d940d 1584 /* ================================================================================ */
Kojto 148:fd96258d940d 1585
Kojto 148:fd96258d940d 1586
Kojto 148:fd96258d940d 1587 /**
Kojto 148:fd96258d940d 1588 * @brief Comparator (COMP)
Kojto 148:fd96258d940d 1589 */
Kojto 148:fd96258d940d 1590
Kojto 148:fd96258d940d 1591 typedef struct { /*!< COMP Structure */
Kojto 148:fd96258d940d 1592 __O uint32_t TASKS_START; /*!< Start comparator */
Kojto 148:fd96258d940d 1593 __O uint32_t TASKS_STOP; /*!< Stop comparator */
Kojto 148:fd96258d940d 1594 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */
Kojto 148:fd96258d940d 1595 __I uint32_t RESERVED0[61];
Kojto 148:fd96258d940d 1596 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid */
Kojto 148:fd96258d940d 1597 __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */
Kojto 148:fd96258d940d 1598 __IO uint32_t EVENTS_UP; /*!< Upward crossing */
Kojto 148:fd96258d940d 1599 __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */
Kojto 148:fd96258d940d 1600 __I uint32_t RESERVED1[60];
Kojto 148:fd96258d940d 1601 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1602 __I uint32_t RESERVED2[63];
Kojto 148:fd96258d940d 1603 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1604 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1605 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1606 __I uint32_t RESERVED3[61];
Kojto 148:fd96258d940d 1607 __I uint32_t RESULT; /*!< Compare result */
Kojto 148:fd96258d940d 1608 __I uint32_t RESERVED4[63];
Kojto 148:fd96258d940d 1609 __IO uint32_t ENABLE; /*!< COMP enable */
Kojto 148:fd96258d940d 1610 __IO uint32_t PSEL; /*!< Pin select */
Kojto 148:fd96258d940d 1611 __IO uint32_t REFSEL; /*!< Reference source select */
Kojto 148:fd96258d940d 1612 __IO uint32_t EXTREFSEL; /*!< External reference select */
Kojto 148:fd96258d940d 1613 __I uint32_t RESERVED5[8];
Kojto 148:fd96258d940d 1614 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit */
Kojto 148:fd96258d940d 1615 __IO uint32_t MODE; /*!< Mode configuration */
Kojto 148:fd96258d940d 1616 __IO uint32_t HYST; /*!< Comparator hysteresis enable */
Kojto 148:fd96258d940d 1617 __IO uint32_t ISOURCE; /*!< Current source select on analog input */
Kojto 148:fd96258d940d 1618 } NRF_COMP_Type;
Kojto 148:fd96258d940d 1619
Kojto 148:fd96258d940d 1620
Kojto 148:fd96258d940d 1621 /* ================================================================================ */
Kojto 148:fd96258d940d 1622 /* ================ LPCOMP ================ */
Kojto 148:fd96258d940d 1623 /* ================================================================================ */
Kojto 148:fd96258d940d 1624
Kojto 148:fd96258d940d 1625
Kojto 148:fd96258d940d 1626 /**
Kojto 148:fd96258d940d 1627 * @brief Low Power Comparator (LPCOMP)
Kojto 148:fd96258d940d 1628 */
Kojto 148:fd96258d940d 1629
Kojto 148:fd96258d940d 1630 typedef struct { /*!< LPCOMP Structure */
Kojto 148:fd96258d940d 1631 __O uint32_t TASKS_START; /*!< Start comparator */
Kojto 148:fd96258d940d 1632 __O uint32_t TASKS_STOP; /*!< Stop comparator */
Kojto 148:fd96258d940d 1633 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value */
Kojto 148:fd96258d940d 1634 __I uint32_t RESERVED0[61];
Kojto 148:fd96258d940d 1635 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid */
Kojto 148:fd96258d940d 1636 __IO uint32_t EVENTS_DOWN; /*!< Downward crossing */
Kojto 148:fd96258d940d 1637 __IO uint32_t EVENTS_UP; /*!< Upward crossing */
Kojto 148:fd96258d940d 1638 __IO uint32_t EVENTS_CROSS; /*!< Downward or upward crossing */
Kojto 148:fd96258d940d 1639 __I uint32_t RESERVED1[60];
Kojto 148:fd96258d940d 1640 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1641 __I uint32_t RESERVED2[64];
Kojto 148:fd96258d940d 1642 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1643 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1644 __I uint32_t RESERVED3[61];
Kojto 148:fd96258d940d 1645 __I uint32_t RESULT; /*!< Compare result */
Kojto 148:fd96258d940d 1646 __I uint32_t RESERVED4[63];
Kojto 148:fd96258d940d 1647 __IO uint32_t ENABLE; /*!< Enable LPCOMP */
Kojto 148:fd96258d940d 1648 __IO uint32_t PSEL; /*!< Input pin select */
Kojto 148:fd96258d940d 1649 __IO uint32_t REFSEL; /*!< Reference select */
Kojto 148:fd96258d940d 1650 __IO uint32_t EXTREFSEL; /*!< External reference select */
Kojto 148:fd96258d940d 1651 __I uint32_t RESERVED5[4];
Kojto 148:fd96258d940d 1652 __IO uint32_t ANADETECT; /*!< Analog detect configuration */
Kojto 148:fd96258d940d 1653 __I uint32_t RESERVED6[5];
Kojto 148:fd96258d940d 1654 __IO uint32_t HYST; /*!< Comparator hysteresis enable */
Kojto 148:fd96258d940d 1655 } NRF_LPCOMP_Type;
Kojto 148:fd96258d940d 1656
Kojto 148:fd96258d940d 1657
Kojto 148:fd96258d940d 1658 /* ================================================================================ */
Kojto 148:fd96258d940d 1659 /* ================ SWI ================ */
Kojto 148:fd96258d940d 1660 /* ================================================================================ */
Kojto 148:fd96258d940d 1661
Kojto 148:fd96258d940d 1662
Kojto 148:fd96258d940d 1663 /**
Kojto 148:fd96258d940d 1664 * @brief Software interrupt 0 (SWI)
Kojto 148:fd96258d940d 1665 */
Kojto 148:fd96258d940d 1666
Kojto 148:fd96258d940d 1667 typedef struct { /*!< SWI Structure */
Kojto 148:fd96258d940d 1668 __I uint32_t UNUSED; /*!< Unused. */
Kojto 148:fd96258d940d 1669 } NRF_SWI_Type;
Kojto 148:fd96258d940d 1670
Kojto 148:fd96258d940d 1671
Kojto 148:fd96258d940d 1672 /* ================================================================================ */
Kojto 148:fd96258d940d 1673 /* ================ EGU ================ */
Kojto 148:fd96258d940d 1674 /* ================================================================================ */
Kojto 148:fd96258d940d 1675
Kojto 148:fd96258d940d 1676
Kojto 148:fd96258d940d 1677 /**
Kojto 148:fd96258d940d 1678 * @brief Event Generator Unit 0 (EGU)
Kojto 148:fd96258d940d 1679 */
Kojto 148:fd96258d940d 1680
Kojto 148:fd96258d940d 1681 typedef struct { /*!< EGU Structure */
Kojto 148:fd96258d940d 1682 __O uint32_t TASKS_TRIGGER[16]; /*!< Description collection[0]: Trigger 0 for triggering the corresponding
Kojto 148:fd96258d940d 1683 TRIGGERED[0] event */
Kojto 148:fd96258d940d 1684 __I uint32_t RESERVED0[48];
Kojto 148:fd96258d940d 1685 __IO uint32_t EVENTS_TRIGGERED[16]; /*!< Description collection[0]: Event number 0 generated by triggering
Kojto 148:fd96258d940d 1686 the corresponding TRIGGER[0] task */
Kojto 148:fd96258d940d 1687 __I uint32_t RESERVED1[112];
Kojto 148:fd96258d940d 1688 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1689 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1690 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1691 } NRF_EGU_Type;
Kojto 148:fd96258d940d 1692
Kojto 148:fd96258d940d 1693
Kojto 148:fd96258d940d 1694 /* ================================================================================ */
Kojto 148:fd96258d940d 1695 /* ================ PWM ================ */
Kojto 148:fd96258d940d 1696 /* ================================================================================ */
Kojto 148:fd96258d940d 1697
Kojto 148:fd96258d940d 1698
Kojto 148:fd96258d940d 1699 /**
Kojto 148:fd96258d940d 1700 * @brief Pulse Width Modulation Unit 0 (PWM)
Kojto 148:fd96258d940d 1701 */
Kojto 148:fd96258d940d 1702
Kojto 148:fd96258d940d 1703 typedef struct { /*!< PWM Structure */
Kojto 148:fd96258d940d 1704 __I uint32_t RESERVED0;
Kojto 148:fd96258d940d 1705 __O uint32_t TASKS_STOP; /*!< Stops PWM pulse generation on all channels at the end of current
Kojto 148:fd96258d940d 1706 PWM period, and stops sequence playback */
Kojto 148:fd96258d940d 1707 __O uint32_t TASKS_SEQSTART[2]; /*!< Description collection[0]: Loads the first PWM value on all
Kojto 148:fd96258d940d 1708 enabled channels from sequence 0, and starts playing that sequence
Kojto 148:fd96258d940d 1709 at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
Kojto 148:fd96258d940d 1710 PWM generation to start it was not running. */
Kojto 148:fd96258d940d 1711 __O uint32_t TASKS_NEXTSTEP; /*!< Steps by one value in the current sequence on all enabled channels
Kojto 148:fd96258d940d 1712 if DECODER.MODE=NextStep. Does not cause PWM generation to start
Kojto 148:fd96258d940d 1713 it was not running. */
Kojto 148:fd96258d940d 1714 __I uint32_t RESERVED1[60];
Kojto 148:fd96258d940d 1715 __IO uint32_t EVENTS_STOPPED; /*!< Response to STOP task, emitted when PWM pulses are no longer
Kojto 148:fd96258d940d 1716 generated */
Kojto 148:fd96258d940d 1717 __IO uint32_t EVENTS_SEQSTARTED[2]; /*!< Description collection[0]: First PWM period started on sequence
Kojto 148:fd96258d940d 1718 0 */
Kojto 148:fd96258d940d 1719 __IO uint32_t EVENTS_SEQEND[2]; /*!< Description collection[0]: Emitted at end of every sequence
Kojto 148:fd96258d940d 1720 0, when last value from RAM has been applied to wave counter */
Kojto 148:fd96258d940d 1721 __IO uint32_t EVENTS_PWMPERIODEND; /*!< Emitted at the end of each PWM period */
Kojto 148:fd96258d940d 1722 __IO uint32_t EVENTS_LOOPSDONE; /*!< Concatenated sequences have been played the amount of times
Kojto 148:fd96258d940d 1723 defined in LOOP.CNT */
Kojto 148:fd96258d940d 1724 __I uint32_t RESERVED2[56];
Kojto 148:fd96258d940d 1725 __IO uint32_t SHORTS; /*!< Shortcut register */
Kojto 148:fd96258d940d 1726 __I uint32_t RESERVED3[63];
Kojto 148:fd96258d940d 1727 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1728 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1729 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1730 __I uint32_t RESERVED4[125];
Kojto 148:fd96258d940d 1731 __IO uint32_t ENABLE; /*!< PWM module enable register */
Kojto 148:fd96258d940d 1732 __IO uint32_t MODE; /*!< Selects operating mode of the wave counter */
Kojto 148:fd96258d940d 1733 __IO uint32_t COUNTERTOP; /*!< Value up to which the pulse generator counter counts */
Kojto 148:fd96258d940d 1734 __IO uint32_t PRESCALER; /*!< Configuration for PWM_CLK */
Kojto 148:fd96258d940d 1735 __IO uint32_t DECODER; /*!< Configuration of the decoder */
Kojto 148:fd96258d940d 1736 __IO uint32_t LOOP; /*!< Amount of playback of a loop */
Kojto 148:fd96258d940d 1737 __I uint32_t RESERVED5[2];
Kojto 148:fd96258d940d 1738 PWM_SEQ_Type SEQ[2]; /*!< Unspecified */
Kojto 148:fd96258d940d 1739 PWM_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 1740 } NRF_PWM_Type;
Kojto 148:fd96258d940d 1741
Kojto 148:fd96258d940d 1742
Kojto 148:fd96258d940d 1743 /* ================================================================================ */
Kojto 148:fd96258d940d 1744 /* ================ PDM ================ */
Kojto 148:fd96258d940d 1745 /* ================================================================================ */
Kojto 148:fd96258d940d 1746
Kojto 148:fd96258d940d 1747
Kojto 148:fd96258d940d 1748 /**
Kojto 148:fd96258d940d 1749 * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
Kojto 148:fd96258d940d 1750 */
Kojto 148:fd96258d940d 1751
Kojto 148:fd96258d940d 1752 typedef struct { /*!< PDM Structure */
Kojto 148:fd96258d940d 1753 __O uint32_t TASKS_START; /*!< Starts continuous PDM transfer */
Kojto 148:fd96258d940d 1754 __O uint32_t TASKS_STOP; /*!< Stops PDM transfer */
Kojto 148:fd96258d940d 1755 __I uint32_t RESERVED0[62];
Kojto 148:fd96258d940d 1756 __IO uint32_t EVENTS_STARTED; /*!< PDM transfer has started */
Kojto 148:fd96258d940d 1757 __IO uint32_t EVENTS_STOPPED; /*!< PDM transfer has finished */
Kojto 148:fd96258d940d 1758 __IO uint32_t EVENTS_END; /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
Kojto 148:fd96258d940d 1759 (or the last sample after a STOP task has been received) to
Kojto 148:fd96258d940d 1760 Data RAM */
Kojto 148:fd96258d940d 1761 __I uint32_t RESERVED1[125];
Kojto 148:fd96258d940d 1762 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1763 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1764 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1765 __I uint32_t RESERVED2[125];
Kojto 148:fd96258d940d 1766 __IO uint32_t ENABLE; /*!< PDM module enable register */
Kojto 148:fd96258d940d 1767 __IO uint32_t PDMCLKCTRL; /*!< PDM clock generator control */
Kojto 148:fd96258d940d 1768 __IO uint32_t MODE; /*!< Defines the routing of the connected PDM microphones' signals */
Kojto 148:fd96258d940d 1769 __I uint32_t RESERVED3[3];
Kojto 148:fd96258d940d 1770 __IO uint32_t GAINL; /*!< Left output gain adjustment */
Kojto 148:fd96258d940d 1771 __IO uint32_t GAINR; /*!< Right output gain adjustment */
Kojto 148:fd96258d940d 1772 __I uint32_t RESERVED4[8];
Kojto 148:fd96258d940d 1773 PDM_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 1774 __I uint32_t RESERVED5[6];
Kojto 148:fd96258d940d 1775 PDM_SAMPLE_Type SAMPLE; /*!< Unspecified */
Kojto 148:fd96258d940d 1776 } NRF_PDM_Type;
Kojto 148:fd96258d940d 1777
Kojto 148:fd96258d940d 1778
Kojto 148:fd96258d940d 1779 /* ================================================================================ */
Kojto 148:fd96258d940d 1780 /* ================ NVMC ================ */
Kojto 148:fd96258d940d 1781 /* ================================================================================ */
Kojto 148:fd96258d940d 1782
Kojto 148:fd96258d940d 1783
Kojto 148:fd96258d940d 1784 /**
Kojto 148:fd96258d940d 1785 * @brief Non Volatile Memory Controller (NVMC)
Kojto 148:fd96258d940d 1786 */
Kojto 148:fd96258d940d 1787
Kojto 148:fd96258d940d 1788 typedef struct { /*!< NVMC Structure */
Kojto 148:fd96258d940d 1789 __I uint32_t RESERVED0[256];
Kojto 148:fd96258d940d 1790 __I uint32_t READY; /*!< Ready flag */
Kojto 148:fd96258d940d 1791 __I uint32_t RESERVED1[64];
Kojto 148:fd96258d940d 1792 __IO uint32_t CONFIG; /*!< Configuration register */
Kojto 148:fd96258d940d 1793
Kojto 148:fd96258d940d 1794 union {
Kojto 148:fd96258d940d 1795 __IO uint32_t ERASEPCR1; /*!< Deprecated register - Register for erasing a page in Code area.
Kojto 148:fd96258d940d 1796 Equivalent to ERASEPAGE. */
Kojto 148:fd96258d940d 1797 __IO uint32_t ERASEPAGE; /*!< Register for erasing a page in Code area */
Kojto 148:fd96258d940d 1798 };
Kojto 148:fd96258d940d 1799 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory */
Kojto 148:fd96258d940d 1800 __IO uint32_t ERASEPCR0; /*!< Deprecated register - Register for erasing a page in Code area.
Kojto 148:fd96258d940d 1801 Equivalent to ERASEPAGE. */
Kojto 148:fd96258d940d 1802 __IO uint32_t ERASEUICR; /*!< Register for erasing User Information Configuration Registers */
Kojto 148:fd96258d940d 1803 __I uint32_t RESERVED2[10];
Kojto 148:fd96258d940d 1804 __IO uint32_t ICACHECNF; /*!< I-Code cache configuration register. */
Kojto 148:fd96258d940d 1805 __I uint32_t RESERVED3;
Kojto 148:fd96258d940d 1806 __IO uint32_t IHIT; /*!< I-Code cache hit counter. */
Kojto 148:fd96258d940d 1807 __IO uint32_t IMISS; /*!< I-Code cache miss counter. */
Kojto 148:fd96258d940d 1808 } NRF_NVMC_Type;
Kojto 148:fd96258d940d 1809
Kojto 148:fd96258d940d 1810
Kojto 148:fd96258d940d 1811 /* ================================================================================ */
Kojto 148:fd96258d940d 1812 /* ================ PPI ================ */
Kojto 148:fd96258d940d 1813 /* ================================================================================ */
Kojto 148:fd96258d940d 1814
Kojto 148:fd96258d940d 1815
Kojto 148:fd96258d940d 1816 /**
Kojto 148:fd96258d940d 1817 * @brief Programmable Peripheral Interconnect (PPI)
Kojto 148:fd96258d940d 1818 */
Kojto 148:fd96258d940d 1819
Kojto 148:fd96258d940d 1820 typedef struct { /*!< PPI Structure */
Kojto 148:fd96258d940d 1821 PPI_TASKS_CHG_Type TASKS_CHG[6]; /*!< Channel group tasks */
Kojto 148:fd96258d940d 1822 __I uint32_t RESERVED0[308];
Kojto 148:fd96258d940d 1823 __IO uint32_t CHEN; /*!< Channel enable register */
Kojto 148:fd96258d940d 1824 __IO uint32_t CHENSET; /*!< Channel enable set register */
Kojto 148:fd96258d940d 1825 __IO uint32_t CHENCLR; /*!< Channel enable clear register */
Kojto 148:fd96258d940d 1826 __I uint32_t RESERVED1;
Kojto 148:fd96258d940d 1827 PPI_CH_Type CH[20]; /*!< PPI Channel */
Kojto 148:fd96258d940d 1828 __I uint32_t RESERVED2[148];
Kojto 148:fd96258d940d 1829 __IO uint32_t CHG[6]; /*!< Description collection[0]: Channel group 0 */
Kojto 148:fd96258d940d 1830 __I uint32_t RESERVED3[62];
Kojto 148:fd96258d940d 1831 PPI_FORK_Type FORK[32]; /*!< Fork */
Kojto 148:fd96258d940d 1832 } NRF_PPI_Type;
Kojto 148:fd96258d940d 1833
Kojto 148:fd96258d940d 1834
Kojto 148:fd96258d940d 1835 /* ================================================================================ */
Kojto 148:fd96258d940d 1836 /* ================ MWU ================ */
Kojto 148:fd96258d940d 1837 /* ================================================================================ */
Kojto 148:fd96258d940d 1838
Kojto 148:fd96258d940d 1839
Kojto 148:fd96258d940d 1840 /**
Kojto 148:fd96258d940d 1841 * @brief Memory Watch Unit (MWU)
Kojto 148:fd96258d940d 1842 */
Kojto 148:fd96258d940d 1843
Kojto 148:fd96258d940d 1844 typedef struct { /*!< MWU Structure */
Kojto 148:fd96258d940d 1845 __I uint32_t RESERVED0[64];
Kojto 148:fd96258d940d 1846 MWU_EVENTS_REGION_Type EVENTS_REGION[4]; /*!< Unspecified */
Kojto 148:fd96258d940d 1847 __I uint32_t RESERVED1[16];
Kojto 148:fd96258d940d 1848 MWU_EVENTS_PREGION_Type EVENTS_PREGION[2]; /*!< Unspecified */
Kojto 148:fd96258d940d 1849 __I uint32_t RESERVED2[100];
Kojto 148:fd96258d940d 1850 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1851 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1852 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1853 __I uint32_t RESERVED3[5];
Kojto 148:fd96258d940d 1854 __IO uint32_t NMIEN; /*!< Enable or disable non-maskable interrupt */
Kojto 148:fd96258d940d 1855 __IO uint32_t NMIENSET; /*!< Enable non-maskable interrupt */
Kojto 148:fd96258d940d 1856 __IO uint32_t NMIENCLR; /*!< Disable non-maskable interrupt */
Kojto 148:fd96258d940d 1857 __I uint32_t RESERVED4[53];
Kojto 148:fd96258d940d 1858 MWU_PERREGION_Type PERREGION[2]; /*!< Unspecified */
Kojto 148:fd96258d940d 1859 __I uint32_t RESERVED5[64];
Kojto 148:fd96258d940d 1860 __IO uint32_t REGIONEN; /*!< Enable/disable regions watch */
Kojto 148:fd96258d940d 1861 __IO uint32_t REGIONENSET; /*!< Enable regions watch */
Kojto 148:fd96258d940d 1862 __IO uint32_t REGIONENCLR; /*!< Disable regions watch */
Kojto 148:fd96258d940d 1863 __I uint32_t RESERVED6[57];
Kojto 148:fd96258d940d 1864 MWU_REGION_Type REGION[4]; /*!< Unspecified */
Kojto 148:fd96258d940d 1865 __I uint32_t RESERVED7[32];
Kojto 148:fd96258d940d 1866 MWU_PREGION_Type PREGION[2]; /*!< Unspecified */
Kojto 148:fd96258d940d 1867 } NRF_MWU_Type;
Kojto 148:fd96258d940d 1868
Kojto 148:fd96258d940d 1869
Kojto 148:fd96258d940d 1870 /* ================================================================================ */
Kojto 148:fd96258d940d 1871 /* ================ I2S ================ */
Kojto 148:fd96258d940d 1872 /* ================================================================================ */
Kojto 148:fd96258d940d 1873
Kojto 148:fd96258d940d 1874
Kojto 148:fd96258d940d 1875 /**
Kojto 148:fd96258d940d 1876 * @brief Inter-IC Sound (I2S)
Kojto 148:fd96258d940d 1877 */
Kojto 148:fd96258d940d 1878
Kojto 148:fd96258d940d 1879 typedef struct { /*!< I2S Structure */
Kojto 148:fd96258d940d 1880 __O uint32_t TASKS_START; /*!< Starts continuous I2S transfer. Also starts MCK generator when
Kojto 148:fd96258d940d 1881 this is enabled. */
Kojto 148:fd96258d940d 1882 __O uint32_t TASKS_STOP; /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
Kojto 148:fd96258d940d 1883 task will cause the {event:STOPPED} event to be generated. */
Kojto 148:fd96258d940d 1884 __I uint32_t RESERVED0[63];
Kojto 148:fd96258d940d 1885 __IO uint32_t EVENTS_RXPTRUPD; /*!< The RXD.PTR register has been copied to internal double-buffers.
Kojto 148:fd96258d940d 1886 When the I2S module is started and RX is enabled, this event
Kojto 148:fd96258d940d 1887 will be generated for every RXTXD.MAXCNT words that are received
Kojto 148:fd96258d940d 1888 on the SDIN pin. */
Kojto 148:fd96258d940d 1889 __IO uint32_t EVENTS_STOPPED; /*!< I2S transfer stopped. */
Kojto 148:fd96258d940d 1890 __I uint32_t RESERVED1[2];
Kojto 148:fd96258d940d 1891 __IO uint32_t EVENTS_TXPTRUPD; /*!< The TDX.PTR register has been copied to internal double-buffers.
Kojto 148:fd96258d940d 1892 When the I2S module is started and TX is enabled, this event
Kojto 148:fd96258d940d 1893 will be generated for every RXTXD.MAXCNT words that are sent
Kojto 148:fd96258d940d 1894 on the SDOUT pin. */
Kojto 148:fd96258d940d 1895 __I uint32_t RESERVED2[122];
Kojto 148:fd96258d940d 1896 __IO uint32_t INTEN; /*!< Enable or disable interrupt */
Kojto 148:fd96258d940d 1897 __IO uint32_t INTENSET; /*!< Enable interrupt */
Kojto 148:fd96258d940d 1898 __IO uint32_t INTENCLR; /*!< Disable interrupt */
Kojto 148:fd96258d940d 1899 __I uint32_t RESERVED3[125];
Kojto 148:fd96258d940d 1900 __IO uint32_t ENABLE; /*!< Enable I2S module. */
Kojto 148:fd96258d940d 1901 I2S_CONFIG_Type CONFIG; /*!< Unspecified */
Kojto 148:fd96258d940d 1902 __I uint32_t RESERVED4[3];
Kojto 148:fd96258d940d 1903 I2S_RXD_Type RXD; /*!< Unspecified */
Kojto 148:fd96258d940d 1904 __I uint32_t RESERVED5;
Kojto 148:fd96258d940d 1905 I2S_TXD_Type TXD; /*!< Unspecified */
Kojto 148:fd96258d940d 1906 __I uint32_t RESERVED6[3];
Kojto 148:fd96258d940d 1907 I2S_RXTXD_Type RXTXD; /*!< Unspecified */
Kojto 148:fd96258d940d 1908 __I uint32_t RESERVED7[3];
Kojto 148:fd96258d940d 1909 I2S_PSEL_Type PSEL; /*!< Unspecified */
Kojto 148:fd96258d940d 1910 } NRF_I2S_Type;
Kojto 148:fd96258d940d 1911
Kojto 148:fd96258d940d 1912
Kojto 148:fd96258d940d 1913 /* ================================================================================ */
Kojto 148:fd96258d940d 1914 /* ================ FPU ================ */
Kojto 148:fd96258d940d 1915 /* ================================================================================ */
Kojto 148:fd96258d940d 1916
Kojto 148:fd96258d940d 1917
Kojto 148:fd96258d940d 1918 /**
Kojto 148:fd96258d940d 1919 * @brief FPU (FPU)
Kojto 148:fd96258d940d 1920 */
Kojto 148:fd96258d940d 1921
Kojto 148:fd96258d940d 1922 typedef struct { /*!< FPU Structure */
Kojto 148:fd96258d940d 1923 __I uint32_t UNUSED; /*!< Unused. */
Kojto 148:fd96258d940d 1924 } NRF_FPU_Type;
Kojto 148:fd96258d940d 1925
Kojto 148:fd96258d940d 1926
Kojto 148:fd96258d940d 1927 /* ================================================================================ */
Kojto 148:fd96258d940d 1928 /* ================ GPIO ================ */
Kojto 148:fd96258d940d 1929 /* ================================================================================ */
Kojto 148:fd96258d940d 1930
Kojto 148:fd96258d940d 1931
Kojto 148:fd96258d940d 1932 /**
Kojto 148:fd96258d940d 1933 * @brief GPIO Port 1 (GPIO)
Kojto 148:fd96258d940d 1934 */
Kojto 148:fd96258d940d 1935
Kojto 148:fd96258d940d 1936 typedef struct { /*!< GPIO Structure */
Kojto 148:fd96258d940d 1937 __I uint32_t RESERVED0[321];
Kojto 148:fd96258d940d 1938 __IO uint32_t OUT; /*!< Write GPIO port */
Kojto 148:fd96258d940d 1939 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port */
Kojto 148:fd96258d940d 1940 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port */
Kojto 148:fd96258d940d 1941 __I uint32_t IN; /*!< Read GPIO port */
Kojto 148:fd96258d940d 1942 __IO uint32_t DIR; /*!< Direction of GPIO pins */
Kojto 148:fd96258d940d 1943 __IO uint32_t DIRSET; /*!< DIR set register */
Kojto 148:fd96258d940d 1944 __IO uint32_t DIRCLR; /*!< DIR clear register */
Kojto 148:fd96258d940d 1945 __IO uint32_t LATCH; /*!< Latch register indicating what GPIO pins that have met the criteria
Kojto 148:fd96258d940d 1946 set in the PIN_CNF[n].SENSE registers */
Kojto 148:fd96258d940d 1947 __IO uint32_t DETECTMODE; /*!< Select between default DETECT signal behaviour and LDETECT mode */
Kojto 148:fd96258d940d 1948 __I uint32_t RESERVED1[118];
Kojto 148:fd96258d940d 1949 __IO uint32_t PIN_CNF[32]; /*!< Description collection[0]: Configuration of GPIO pins */
Kojto 148:fd96258d940d 1950 } NRF_GPIO_Type;
Kojto 148:fd96258d940d 1951
Kojto 148:fd96258d940d 1952
Kojto 148:fd96258d940d 1953 /* -------------------- End of section using anonymous unions ------------------- */
Kojto 148:fd96258d940d 1954 #if defined(__CC_ARM)
Kojto 148:fd96258d940d 1955 #pragma pop
Kojto 148:fd96258d940d 1956 #elif defined(__ICCARM__)
Kojto 148:fd96258d940d 1957 /* leave anonymous unions enabled */
Kojto 148:fd96258d940d 1958 #elif defined(__GNUC__)
Kojto 148:fd96258d940d 1959 /* anonymous unions are enabled by default */
Kojto 148:fd96258d940d 1960 #elif defined(__TMS470__)
Kojto 148:fd96258d940d 1961 /* anonymous unions are enabled by default */
Kojto 148:fd96258d940d 1962 #elif defined(__TASKING__)
Kojto 148:fd96258d940d 1963 #pragma warning restore
Kojto 148:fd96258d940d 1964 #else
Kojto 148:fd96258d940d 1965 #warning Not supported compiler type
Kojto 148:fd96258d940d 1966 #endif
Kojto 148:fd96258d940d 1967
Kojto 148:fd96258d940d 1968
Kojto 148:fd96258d940d 1969
Kojto 148:fd96258d940d 1970
Kojto 148:fd96258d940d 1971 /* ================================================================================ */
Kojto 148:fd96258d940d 1972 /* ================ Peripheral memory map ================ */
Kojto 148:fd96258d940d 1973 /* ================================================================================ */
Kojto 148:fd96258d940d 1974
Kojto 148:fd96258d940d 1975 #define NRF_FICR_BASE 0x10000000UL
Kojto 148:fd96258d940d 1976 #define NRF_UICR_BASE 0x10001000UL
Kojto 148:fd96258d940d 1977 #define NRF_BPROT_BASE 0x40000000UL
Kojto 148:fd96258d940d 1978 #define NRF_POWER_BASE 0x40000000UL
Kojto 148:fd96258d940d 1979 #define NRF_CLOCK_BASE 0x40000000UL
Kojto 148:fd96258d940d 1980 #define NRF_AMLI_BASE 0x40000000UL
Kojto 148:fd96258d940d 1981 #define NRF_RADIO_BASE 0x40001000UL
Kojto 148:fd96258d940d 1982 #define NRF_UARTE0_BASE 0x40002000UL
Kojto 148:fd96258d940d 1983 #define NRF_UART0_BASE 0x40002000UL
Kojto 148:fd96258d940d 1984 #define NRF_SPIM0_BASE 0x40003000UL
Kojto 148:fd96258d940d 1985 #define NRF_SPIS0_BASE 0x40003000UL
Kojto 148:fd96258d940d 1986 #define NRF_TWIM0_BASE 0x40003000UL
Kojto 148:fd96258d940d 1987 #define NRF_TWIS0_BASE 0x40003000UL
Kojto 148:fd96258d940d 1988 #define NRF_SPI0_BASE 0x40003000UL
Kojto 148:fd96258d940d 1989 #define NRF_TWI0_BASE 0x40003000UL
Kojto 148:fd96258d940d 1990 #define NRF_SPIM1_BASE 0x40004000UL
Kojto 148:fd96258d940d 1991 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 148:fd96258d940d 1992 #define NRF_TWIM1_BASE 0x40004000UL
Kojto 148:fd96258d940d 1993 #define NRF_TWIS1_BASE 0x40004000UL
Kojto 148:fd96258d940d 1994 #define NRF_SPI1_BASE 0x40004000UL
Kojto 148:fd96258d940d 1995 #define NRF_TWI1_BASE 0x40004000UL
Kojto 148:fd96258d940d 1996 #define NRF_NFCT_BASE 0x40005000UL
Kojto 148:fd96258d940d 1997 #define NRF_GPIOTE_BASE 0x40006000UL
Kojto 148:fd96258d940d 1998 #define NRF_SAADC_BASE 0x40007000UL
Kojto 148:fd96258d940d 1999 #define NRF_TIMER0_BASE 0x40008000UL
Kojto 148:fd96258d940d 2000 #define NRF_TIMER1_BASE 0x40009000UL
Kojto 148:fd96258d940d 2001 #define NRF_TIMER2_BASE 0x4000A000UL
Kojto 148:fd96258d940d 2002 #define NRF_RTC0_BASE 0x4000B000UL
Kojto 148:fd96258d940d 2003 #define NRF_TEMP_BASE 0x4000C000UL
Kojto 148:fd96258d940d 2004 #define NRF_RNG_BASE 0x4000D000UL
Kojto 148:fd96258d940d 2005 #define NRF_ECB_BASE 0x4000E000UL
Kojto 148:fd96258d940d 2006 #define NRF_CCM_BASE 0x4000F000UL
Kojto 148:fd96258d940d 2007 #define NRF_AAR_BASE 0x4000F000UL
Kojto 148:fd96258d940d 2008 #define NRF_WDT_BASE 0x40010000UL
Kojto 148:fd96258d940d 2009 #define NRF_RTC1_BASE 0x40011000UL
Kojto 148:fd96258d940d 2010 #define NRF_QDEC_BASE 0x40012000UL
Kojto 148:fd96258d940d 2011 #define NRF_COMP_BASE 0x40013000UL
Kojto 148:fd96258d940d 2012 #define NRF_LPCOMP_BASE 0x40013000UL
Kojto 148:fd96258d940d 2013 #define NRF_SWI0_BASE 0x40014000UL
Kojto 148:fd96258d940d 2014 #define NRF_EGU0_BASE 0x40014000UL
Kojto 148:fd96258d940d 2015 #define NRF_SWI1_BASE 0x40015000UL
Kojto 148:fd96258d940d 2016 #define NRF_EGU1_BASE 0x40015000UL
Kojto 148:fd96258d940d 2017 #define NRF_SWI2_BASE 0x40016000UL
Kojto 148:fd96258d940d 2018 #define NRF_EGU2_BASE 0x40016000UL
Kojto 148:fd96258d940d 2019 #define NRF_SWI3_BASE 0x40017000UL
Kojto 148:fd96258d940d 2020 #define NRF_EGU3_BASE 0x40017000UL
Kojto 148:fd96258d940d 2021 #define NRF_SWI4_BASE 0x40018000UL
Kojto 148:fd96258d940d 2022 #define NRF_EGU4_BASE 0x40018000UL
Kojto 148:fd96258d940d 2023 #define NRF_SWI5_BASE 0x40019000UL
Kojto 148:fd96258d940d 2024 #define NRF_EGU5_BASE 0x40019000UL
Kojto 148:fd96258d940d 2025 #define NRF_TIMER3_BASE 0x4001A000UL
Kojto 148:fd96258d940d 2026 #define NRF_TIMER4_BASE 0x4001B000UL
Kojto 148:fd96258d940d 2027 #define NRF_PWM0_BASE 0x4001C000UL
Kojto 148:fd96258d940d 2028 #define NRF_PDM_BASE 0x4001D000UL
Kojto 148:fd96258d940d 2029 #define NRF_NVMC_BASE 0x4001E000UL
Kojto 148:fd96258d940d 2030 #define NRF_PPI_BASE 0x4001F000UL
Kojto 148:fd96258d940d 2031 #define NRF_MWU_BASE 0x40020000UL
Kojto 148:fd96258d940d 2032 #define NRF_PWM1_BASE 0x40021000UL
Kojto 148:fd96258d940d 2033 #define NRF_PWM2_BASE 0x40022000UL
Kojto 148:fd96258d940d 2034 #define NRF_SPIM2_BASE 0x40023000UL
Kojto 148:fd96258d940d 2035 #define NRF_SPIS2_BASE 0x40023000UL
Kojto 148:fd96258d940d 2036 #define NRF_SPI2_BASE 0x40023000UL
Kojto 148:fd96258d940d 2037 #define NRF_RTC2_BASE 0x40024000UL
Kojto 148:fd96258d940d 2038 #define NRF_I2S_BASE 0x40025000UL
Kojto 148:fd96258d940d 2039 #define NRF_FPU_BASE 0x40026000UL
Kojto 148:fd96258d940d 2040 #define NRF_P0_BASE 0x50000000UL
Kojto 148:fd96258d940d 2041
Kojto 148:fd96258d940d 2042
Kojto 148:fd96258d940d 2043 /* ================================================================================ */
Kojto 148:fd96258d940d 2044 /* ================ Peripheral declaration ================ */
Kojto 148:fd96258d940d 2045 /* ================================================================================ */
Kojto 148:fd96258d940d 2046
Kojto 148:fd96258d940d 2047 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
Kojto 148:fd96258d940d 2048 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
Kojto 148:fd96258d940d 2049 #define NRF_BPROT ((NRF_BPROT_Type *) NRF_BPROT_BASE)
Kojto 148:fd96258d940d 2050 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
Kojto 148:fd96258d940d 2051 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
Kojto 148:fd96258d940d 2052 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
Kojto 148:fd96258d940d 2053 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
Kojto 148:fd96258d940d 2054 #define NRF_UARTE0 ((NRF_UARTE_Type *) NRF_UARTE0_BASE)
Kojto 148:fd96258d940d 2055 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
Kojto 148:fd96258d940d 2056 #define NRF_SPIM0 ((NRF_SPIM_Type *) NRF_SPIM0_BASE)
Kojto 148:fd96258d940d 2057 #define NRF_SPIS0 ((NRF_SPIS_Type *) NRF_SPIS0_BASE)
Kojto 148:fd96258d940d 2058 #define NRF_TWIM0 ((NRF_TWIM_Type *) NRF_TWIM0_BASE)
Kojto 148:fd96258d940d 2059 #define NRF_TWIS0 ((NRF_TWIS_Type *) NRF_TWIS0_BASE)
Kojto 148:fd96258d940d 2060 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
Kojto 148:fd96258d940d 2061 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
Kojto 148:fd96258d940d 2062 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
Kojto 148:fd96258d940d 2063 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 148:fd96258d940d 2064 #define NRF_TWIM1 ((NRF_TWIM_Type *) NRF_TWIM1_BASE)
Kojto 148:fd96258d940d 2065 #define NRF_TWIS1 ((NRF_TWIS_Type *) NRF_TWIS1_BASE)
Kojto 148:fd96258d940d 2066 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
Kojto 148:fd96258d940d 2067 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
Kojto 148:fd96258d940d 2068 #define NRF_NFCT ((NRF_NFCT_Type *) NRF_NFCT_BASE)
Kojto 148:fd96258d940d 2069 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
Kojto 148:fd96258d940d 2070 #define NRF_SAADC ((NRF_SAADC_Type *) NRF_SAADC_BASE)
Kojto 148:fd96258d940d 2071 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
Kojto 148:fd96258d940d 2072 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
Kojto 148:fd96258d940d 2073 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
Kojto 148:fd96258d940d 2074 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
Kojto 148:fd96258d940d 2075 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
Kojto 148:fd96258d940d 2076 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
Kojto 148:fd96258d940d 2077 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
Kojto 148:fd96258d940d 2078 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
Kojto 148:fd96258d940d 2079 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
Kojto 148:fd96258d940d 2080 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
Kojto 148:fd96258d940d 2081 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
Kojto 148:fd96258d940d 2082 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
Kojto 148:fd96258d940d 2083 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
Kojto 148:fd96258d940d 2084 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
Kojto 148:fd96258d940d 2085 #define NRF_SWI0 ((NRF_SWI_Type *) NRF_SWI0_BASE)
Kojto 148:fd96258d940d 2086 #define NRF_EGU0 ((NRF_EGU_Type *) NRF_EGU0_BASE)
Kojto 148:fd96258d940d 2087 #define NRF_SWI1 ((NRF_SWI_Type *) NRF_SWI1_BASE)
Kojto 148:fd96258d940d 2088 #define NRF_EGU1 ((NRF_EGU_Type *) NRF_EGU1_BASE)
Kojto 148:fd96258d940d 2089 #define NRF_SWI2 ((NRF_SWI_Type *) NRF_SWI2_BASE)
Kojto 148:fd96258d940d 2090 #define NRF_EGU2 ((NRF_EGU_Type *) NRF_EGU2_BASE)
Kojto 148:fd96258d940d 2091 #define NRF_SWI3 ((NRF_SWI_Type *) NRF_SWI3_BASE)
Kojto 148:fd96258d940d 2092 #define NRF_EGU3 ((NRF_EGU_Type *) NRF_EGU3_BASE)
Kojto 148:fd96258d940d 2093 #define NRF_SWI4 ((NRF_SWI_Type *) NRF_SWI4_BASE)
Kojto 148:fd96258d940d 2094 #define NRF_EGU4 ((NRF_EGU_Type *) NRF_EGU4_BASE)
Kojto 148:fd96258d940d 2095 #define NRF_SWI5 ((NRF_SWI_Type *) NRF_SWI5_BASE)
Kojto 148:fd96258d940d 2096 #define NRF_EGU5 ((NRF_EGU_Type *) NRF_EGU5_BASE)
Kojto 148:fd96258d940d 2097 #define NRF_TIMER3 ((NRF_TIMER_Type *) NRF_TIMER3_BASE)
Kojto 148:fd96258d940d 2098 #define NRF_TIMER4 ((NRF_TIMER_Type *) NRF_TIMER4_BASE)
Kojto 148:fd96258d940d 2099 #define NRF_PWM0 ((NRF_PWM_Type *) NRF_PWM0_BASE)
Kojto 148:fd96258d940d 2100 #define NRF_PDM ((NRF_PDM_Type *) NRF_PDM_BASE)
Kojto 148:fd96258d940d 2101 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
Kojto 148:fd96258d940d 2102 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
Kojto 148:fd96258d940d 2103 #define NRF_MWU ((NRF_MWU_Type *) NRF_MWU_BASE)
Kojto 148:fd96258d940d 2104 #define NRF_PWM1 ((NRF_PWM_Type *) NRF_PWM1_BASE)
Kojto 148:fd96258d940d 2105 #define NRF_PWM2 ((NRF_PWM_Type *) NRF_PWM2_BASE)
Kojto 148:fd96258d940d 2106 #define NRF_SPIM2 ((NRF_SPIM_Type *) NRF_SPIM2_BASE)
Kojto 148:fd96258d940d 2107 #define NRF_SPIS2 ((NRF_SPIS_Type *) NRF_SPIS2_BASE)
Kojto 148:fd96258d940d 2108 #define NRF_SPI2 ((NRF_SPI_Type *) NRF_SPI2_BASE)
Kojto 148:fd96258d940d 2109 #define NRF_RTC2 ((NRF_RTC_Type *) NRF_RTC2_BASE)
Kojto 148:fd96258d940d 2110 #define NRF_I2S ((NRF_I2S_Type *) NRF_I2S_BASE)
Kojto 148:fd96258d940d 2111 #define NRF_FPU ((NRF_FPU_Type *) NRF_FPU_BASE)
Kojto 148:fd96258d940d 2112 #define NRF_P0 ((NRF_GPIO_Type *) NRF_P0_BASE)
Kojto 148:fd96258d940d 2113
Kojto 148:fd96258d940d 2114
Kojto 148:fd96258d940d 2115 /** @} */ /* End of group Device_Peripheral_Registers */
Kojto 148:fd96258d940d 2116 /** @} */ /* End of group nrf52 */
Kojto 148:fd96258d940d 2117 /** @} */ /* End of group Nordic Semiconductor */
Kojto 148:fd96258d940d 2118
Kojto 148:fd96258d940d 2119 #ifdef __cplusplus
Kojto 148:fd96258d940d 2120 }
Kojto 148:fd96258d940d 2121 #endif
Kojto 148:fd96258d940d 2122
Kojto 148:fd96258d940d 2123
Kojto 148:fd96258d940d 2124 #endif /* nrf52_H */
Kojto 148:fd96258d940d 2125