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TARGET_USENSE/TOOLCHAIN_ARM_STD/MKL82Z7.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /* |
AnnaBridge | 171:3a7713b1edbc | 2 | ** ################################################################### |
AnnaBridge | 171:3a7713b1edbc | 3 | ** Processors: MKL82Z128VLH7 |
AnnaBridge | 171:3a7713b1edbc | 4 | ** MKL82Z128VLK7 |
AnnaBridge | 171:3a7713b1edbc | 5 | ** MKL82Z128VLL7 |
AnnaBridge | 171:3a7713b1edbc | 6 | ** MKL82Z128VMC7 |
AnnaBridge | 171:3a7713b1edbc | 7 | ** MKL82Z128VMP7 |
AnnaBridge | 171:3a7713b1edbc | 8 | ** |
AnnaBridge | 171:3a7713b1edbc | 9 | ** Compilers: Keil ARM C/C++ Compiler |
AnnaBridge | 171:3a7713b1edbc | 10 | ** Freescale C/C++ for Embedded ARM |
AnnaBridge | 171:3a7713b1edbc | 11 | ** GNU C Compiler |
AnnaBridge | 171:3a7713b1edbc | 12 | ** IAR ANSI C/C++ Compiler for ARM |
AnnaBridge | 171:3a7713b1edbc | 13 | ** |
AnnaBridge | 171:3a7713b1edbc | 14 | ** Reference manual: KL82P121M72SF0RM, Rev.2 November 2015 |
AnnaBridge | 171:3a7713b1edbc | 15 | ** Version: rev. 1.5, 2015-09-24 |
AnnaBridge | 171:3a7713b1edbc | 16 | ** Build: b160201 |
AnnaBridge | 171:3a7713b1edbc | 17 | ** |
AnnaBridge | 171:3a7713b1edbc | 18 | ** Abstract: |
AnnaBridge | 171:3a7713b1edbc | 19 | ** CMSIS Peripheral Access Layer for MKL82Z7 |
AnnaBridge | 171:3a7713b1edbc | 20 | ** |
AnnaBridge | 171:3a7713b1edbc | 21 | ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc. |
AnnaBridge | 171:3a7713b1edbc | 22 | ** All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 23 | ** |
AnnaBridge | 171:3a7713b1edbc | 24 | ** Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 171:3a7713b1edbc | 25 | ** are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 26 | ** |
AnnaBridge | 171:3a7713b1edbc | 27 | ** o Redistributions of source code must retain the above copyright notice, this list |
AnnaBridge | 171:3a7713b1edbc | 28 | ** of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 29 | ** |
AnnaBridge | 171:3a7713b1edbc | 30 | ** o Redistributions in binary form must reproduce the above copyright notice, this |
AnnaBridge | 171:3a7713b1edbc | 31 | ** list of conditions and the following disclaimer in the documentation and/or |
AnnaBridge | 171:3a7713b1edbc | 32 | ** other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 33 | ** |
AnnaBridge | 171:3a7713b1edbc | 34 | ** o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
AnnaBridge | 171:3a7713b1edbc | 35 | ** contributors may be used to endorse or promote products derived from this |
AnnaBridge | 171:3a7713b1edbc | 36 | ** software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 37 | ** |
AnnaBridge | 171:3a7713b1edbc | 38 | ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
AnnaBridge | 171:3a7713b1edbc | 39 | ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 40 | ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 171:3a7713b1edbc | 41 | ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 42 | ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
AnnaBridge | 171:3a7713b1edbc | 43 | ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
AnnaBridge | 171:3a7713b1edbc | 44 | ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
AnnaBridge | 171:3a7713b1edbc | 45 | ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
AnnaBridge | 171:3a7713b1edbc | 46 | ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
AnnaBridge | 171:3a7713b1edbc | 47 | ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 48 | ** |
AnnaBridge | 171:3a7713b1edbc | 49 | ** http: www.freescale.com |
AnnaBridge | 171:3a7713b1edbc | 50 | ** mail: support@freescale.com |
AnnaBridge | 171:3a7713b1edbc | 51 | ** |
AnnaBridge | 171:3a7713b1edbc | 52 | ** Revisions: |
AnnaBridge | 171:3a7713b1edbc | 53 | ** - rev. 1.0 (2015-04-18) |
AnnaBridge | 171:3a7713b1edbc | 54 | ** Initial version. |
AnnaBridge | 171:3a7713b1edbc | 55 | ** - rev. 1.1 (2015-05-04) |
AnnaBridge | 171:3a7713b1edbc | 56 | ** Update SIM, EVMSIM, QuadSPI, and I2C based on Rev0 document. |
AnnaBridge | 171:3a7713b1edbc | 57 | ** - rev. 1.2 (2015-08-11) |
AnnaBridge | 171:3a7713b1edbc | 58 | ** Correct clock configuration. |
AnnaBridge | 171:3a7713b1edbc | 59 | ** - rev. 1.3 (2015-08-20) |
AnnaBridge | 171:3a7713b1edbc | 60 | ** Align with RM Rev.1. |
AnnaBridge | 171:3a7713b1edbc | 61 | ** - rev. 1.4 (2015-08-28) |
AnnaBridge | 171:3a7713b1edbc | 62 | ** Update LPUART to add FIFO. |
AnnaBridge | 171:3a7713b1edbc | 63 | ** - rev. 1.5 (2015-09-24) |
AnnaBridge | 171:3a7713b1edbc | 64 | ** Update to align with RM Rev.1.2. |
AnnaBridge | 171:3a7713b1edbc | 65 | ** |
AnnaBridge | 171:3a7713b1edbc | 66 | ** ################################################################### |
AnnaBridge | 171:3a7713b1edbc | 67 | */ |
AnnaBridge | 171:3a7713b1edbc | 68 | |
AnnaBridge | 171:3a7713b1edbc | 69 | /*! |
AnnaBridge | 171:3a7713b1edbc | 70 | * @file MKL82Z7.h |
AnnaBridge | 171:3a7713b1edbc | 71 | * @version 1.5 |
AnnaBridge | 171:3a7713b1edbc | 72 | * @date 2015-09-24 |
AnnaBridge | 171:3a7713b1edbc | 73 | * @brief CMSIS Peripheral Access Layer for MKL82Z7 |
AnnaBridge | 171:3a7713b1edbc | 74 | * |
AnnaBridge | 171:3a7713b1edbc | 75 | * CMSIS Peripheral Access Layer for MKL82Z7 |
AnnaBridge | 171:3a7713b1edbc | 76 | */ |
AnnaBridge | 171:3a7713b1edbc | 77 | |
AnnaBridge | 171:3a7713b1edbc | 78 | #ifndef _MKL82Z7_H_ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define _MKL82Z7_H_ /**< Symbol preventing repeated inclusion */ |
AnnaBridge | 171:3a7713b1edbc | 80 | |
AnnaBridge | 171:3a7713b1edbc | 81 | /** Memory map major version (memory maps with equal major version number are |
AnnaBridge | 171:3a7713b1edbc | 82 | * compatible) */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define MCU_MEM_MAP_VERSION 0x0100U |
AnnaBridge | 171:3a7713b1edbc | 84 | /** Memory map minor version */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define MCU_MEM_MAP_VERSION_MINOR 0x0005U |
AnnaBridge | 171:3a7713b1edbc | 86 | |
AnnaBridge | 171:3a7713b1edbc | 87 | |
AnnaBridge | 171:3a7713b1edbc | 88 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 89 | -- Interrupt vector numbers |
AnnaBridge | 171:3a7713b1edbc | 90 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 91 | |
AnnaBridge | 171:3a7713b1edbc | 92 | /*! |
AnnaBridge | 171:3a7713b1edbc | 93 | * @addtogroup Interrupt_vector_numbers Interrupt vector numbers |
AnnaBridge | 171:3a7713b1edbc | 94 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 95 | */ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | /** Interrupt Number Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define NUMBER_OF_INT_VECTORS 80 /**< Number of interrupts in the Vector table */ |
AnnaBridge | 171:3a7713b1edbc | 99 | |
AnnaBridge | 171:3a7713b1edbc | 100 | typedef enum IRQn { |
AnnaBridge | 171:3a7713b1edbc | 101 | /* Auxiliary constants */ |
AnnaBridge | 171:3a7713b1edbc | 102 | NotAvail_IRQn = -128, /**< Not available device specific interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 103 | |
AnnaBridge | 171:3a7713b1edbc | 104 | /* Core interrupts */ |
AnnaBridge | 171:3a7713b1edbc | 105 | NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 106 | HardFault_IRQn = -13, /**< Cortex-M0 SV Hard Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 107 | SVCall_IRQn = -5, /**< Cortex-M0 SV Call Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 108 | PendSV_IRQn = -2, /**< Cortex-M0 Pend SV Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 109 | SysTick_IRQn = -1, /**< Cortex-M0 System Tick Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | /* Device specific interrupts */ |
AnnaBridge | 171:3a7713b1edbc | 112 | DMA0_DMA4_IRQn = 0, /**< DMA channel 0, 4 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 113 | DMA1_DMA5_IRQn = 1, /**< DMA channel 1, 5 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 114 | DMA2_DMA6_IRQn = 2, /**< DMA channel 2, 6 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 115 | DMA3_DMA7_IRQn = 3, /**< DMA channel 3, 7 transfer complete */ |
AnnaBridge | 171:3a7713b1edbc | 116 | DMA_Error_IRQn = 4, /**< DMA channel 0 - 7 error */ |
AnnaBridge | 171:3a7713b1edbc | 117 | FLEXIO0_IRQn = 5, /**< Flexible IO */ |
AnnaBridge | 171:3a7713b1edbc | 118 | TPM0_IRQn = 6, /**< Timer/PWM module 0 */ |
AnnaBridge | 171:3a7713b1edbc | 119 | TPM1_IRQn = 7, /**< Timer/PWM module 1 */ |
AnnaBridge | 171:3a7713b1edbc | 120 | TPM2_IRQn = 8, /**< Timer/PWM module 2 */ |
AnnaBridge | 171:3a7713b1edbc | 121 | PIT0_IRQn = 9, /**< Periodic Interrupt Timer 0 */ |
AnnaBridge | 171:3a7713b1edbc | 122 | SPI0_IRQn = 10, /**< Serial Peripheral Interface 0 */ |
AnnaBridge | 171:3a7713b1edbc | 123 | EMVSIM0_IRQn = 11, /**< EMVSIM0 common interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 124 | LPUART0_IRQn = 12, /**< LPUART0 status and error */ |
AnnaBridge | 171:3a7713b1edbc | 125 | LPUART1_IRQn = 13, /**< LPUART1 status and error */ |
AnnaBridge | 171:3a7713b1edbc | 126 | I2C0_IRQn = 14, /**< Inter-Integrated Circuit 0 */ |
AnnaBridge | 171:3a7713b1edbc | 127 | QSPI0_IRQn = 15, /**< QuadSPI0 interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 128 | Reserved32_IRQn = 16, /**< DryIce tamper detect */ |
AnnaBridge | 171:3a7713b1edbc | 129 | PORTA_IRQn = 17, /**< Pin detect Port A */ |
AnnaBridge | 171:3a7713b1edbc | 130 | PORTB_IRQn = 18, /**< Pin detect Port B */ |
AnnaBridge | 171:3a7713b1edbc | 131 | PORTC_IRQn = 19, /**< Pin detect Port C */ |
AnnaBridge | 171:3a7713b1edbc | 132 | PORTD_IRQn = 20, /**< Pin detect Port D */ |
AnnaBridge | 171:3a7713b1edbc | 133 | PORTE_IRQn = 21, /**< Pin detect Port E */ |
AnnaBridge | 171:3a7713b1edbc | 134 | LLWU_IRQn = 22, /**< Low Leakage Wakeup */ |
AnnaBridge | 171:3a7713b1edbc | 135 | LTC0_IRQn = 23, /**< Low power trusted cryptographic */ |
AnnaBridge | 171:3a7713b1edbc | 136 | USB0_IRQn = 24, /**< USB OTG interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 137 | ADC0_IRQn = 25, /**< Analog-to-Digital Converter 0 */ |
AnnaBridge | 171:3a7713b1edbc | 138 | LPTMR0_IRQn = 26, /**< Low-Power Timer 0 */ |
AnnaBridge | 171:3a7713b1edbc | 139 | RTC_Seconds_IRQn = 27, /**< RTC seconds */ |
AnnaBridge | 171:3a7713b1edbc | 140 | INTMUX0_0_IRQn = 28, /**< Selectable peripheral interrupt INTMUX0-0 */ |
AnnaBridge | 171:3a7713b1edbc | 141 | INTMUX0_1_IRQn = 29, /**< Selectable peripheral interrupt INTMUX0-1 */ |
AnnaBridge | 171:3a7713b1edbc | 142 | INTMUX0_2_IRQn = 30, /**< Selectable peripheral interrupt INTMUX0-2 */ |
AnnaBridge | 171:3a7713b1edbc | 143 | INTMUX0_3_IRQn = 31, /**< Selectable peripheral interrupt INTMUX0-3 */ |
AnnaBridge | 171:3a7713b1edbc | 144 | LPTMR1_IRQn = 32, /**< Low-Power Timer 1 (INTMUX source IRQ0) */ |
AnnaBridge | 171:3a7713b1edbc | 145 | Reserved49_IRQn = 33, /**< Reserved interrupt (INTMUX source IRQ1) */ |
AnnaBridge | 171:3a7713b1edbc | 146 | Reserved50_IRQn = 34, /**< Reserved interrupt (INTMUX source IRQ2) */ |
AnnaBridge | 171:3a7713b1edbc | 147 | Reserved51_IRQn = 35, /**< Reserved interrupt (INTMUX source IRQ3) */ |
AnnaBridge | 171:3a7713b1edbc | 148 | SPI1_IRQn = 36, /**< Serial Peripheral Interface 1 (INTMUX source IRQ4) */ |
AnnaBridge | 171:3a7713b1edbc | 149 | LPUART2_IRQn = 37, /**< LPUART2 status and error (INTMUX source IRQ5) */ |
AnnaBridge | 171:3a7713b1edbc | 150 | EMVSIM1_IRQn = 38, /**< EMVSIM1 common interrupt (INTMUX source IRQ6) */ |
AnnaBridge | 171:3a7713b1edbc | 151 | I2C1_IRQn = 39, /**< Inter-Integrated Circuit 1 (INTMUX source IRQ7) */ |
AnnaBridge | 171:3a7713b1edbc | 152 | TSI0_IRQn = 40, /**< Touch Sensing Input 0 (INTMUX source IRQ8) */ |
AnnaBridge | 171:3a7713b1edbc | 153 | PMC_IRQn = 41, /**< PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) */ |
AnnaBridge | 171:3a7713b1edbc | 154 | FTFA_IRQn = 42, /**< FTFA command complete/read collision (INTMUX source IRQ10) */ |
AnnaBridge | 171:3a7713b1edbc | 155 | MCG_IRQn = 43, /**< Multipurpose clock generator (INTMUX source IRQ11) */ |
AnnaBridge | 171:3a7713b1edbc | 156 | WDOG_EWM_IRQn = 44, /**< Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) */ |
AnnaBridge | 171:3a7713b1edbc | 157 | DAC0_IRQn = 45, /**< Digital-to-analog converter 0 (INTMUX source IRQ13) */ |
AnnaBridge | 171:3a7713b1edbc | 158 | TRNG0_IRQn = 46, /**< True randon number generator (INTMUX source IRQ14) */ |
AnnaBridge | 171:3a7713b1edbc | 159 | Reserved63_IRQn = 47, /**< Reserved interrupt (INTMUX source IRQ15) */ |
AnnaBridge | 171:3a7713b1edbc | 160 | CMP0_IRQn = 48, /**< Comparator 0 (INTMUX source IRQ16) */ |
AnnaBridge | 171:3a7713b1edbc | 161 | Reserved65_IRQn = 49, /**< Reserved interrupt (INTMUX source IRQ17) */ |
AnnaBridge | 171:3a7713b1edbc | 162 | RTC_Alarm_IRQn = 50, /**< Real time clock (INTMUX source IRQ18) */ |
AnnaBridge | 171:3a7713b1edbc | 163 | Reserved67_IRQn = 51, /**< Reserved interrupt (INTMUX source IRQ19) */ |
AnnaBridge | 171:3a7713b1edbc | 164 | Reserved68_IRQn = 52, /**< Reserved interrupt (INTMUX source IRQ20) */ |
AnnaBridge | 171:3a7713b1edbc | 165 | Reserved69_IRQn = 53, /**< Reserved interrupt (INTMUX source IRQ21) */ |
AnnaBridge | 171:3a7713b1edbc | 166 | Reserved70_IRQn = 54, /**< Reserved interrupt (INTMUX source IRQ22) */ |
AnnaBridge | 171:3a7713b1edbc | 167 | Reserved71_IRQn = 55, /**< Reserved interrupt (INTMUX source IRQ23) */ |
AnnaBridge | 171:3a7713b1edbc | 168 | DMA4_IRQn = 56, /**< DMA channel 4 transfer complete (INTMUX source IRQ24) */ |
AnnaBridge | 171:3a7713b1edbc | 169 | DMA5_IRQn = 57, /**< DMA channel 5 transfer complete (INTMUX source IRQ25) */ |
AnnaBridge | 171:3a7713b1edbc | 170 | DMA6_IRQn = 58, /**< DMA channel 6 transfer complete (INTMUX source IRQ26) */ |
AnnaBridge | 171:3a7713b1edbc | 171 | DMA7_IRQn = 59, /**< DMA channel 7 transfer complete (INTMUX source IRQ27) */ |
AnnaBridge | 171:3a7713b1edbc | 172 | Reserved76_IRQn = 60, /**< Reserved interrupt (INTMUX source IRQ28) */ |
AnnaBridge | 171:3a7713b1edbc | 173 | Reserved77_IRQn = 61, /**< Reserved interrupt (INTMUX source IRQ29) */ |
AnnaBridge | 171:3a7713b1edbc | 174 | Reserved78_IRQn = 62, /**< Reserved interrupt (INTMUX source IRQ30) */ |
AnnaBridge | 171:3a7713b1edbc | 175 | Reserved79_IRQn = 63 /**< Reserved interrupt (INTMUX source IRQ31) */ |
AnnaBridge | 171:3a7713b1edbc | 176 | } IRQn_Type; |
AnnaBridge | 171:3a7713b1edbc | 177 | |
AnnaBridge | 171:3a7713b1edbc | 178 | /*! |
AnnaBridge | 171:3a7713b1edbc | 179 | * @} |
AnnaBridge | 171:3a7713b1edbc | 180 | */ /* end of group Interrupt_vector_numbers */ |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | |
AnnaBridge | 171:3a7713b1edbc | 183 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 184 | -- Cortex M0 Core Configuration |
AnnaBridge | 171:3a7713b1edbc | 185 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 186 | |
AnnaBridge | 171:3a7713b1edbc | 187 | /*! |
AnnaBridge | 171:3a7713b1edbc | 188 | * @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration |
AnnaBridge | 171:3a7713b1edbc | 189 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 190 | */ |
AnnaBridge | 171:3a7713b1edbc | 191 | |
AnnaBridge | 171:3a7713b1edbc | 192 | #define __CM0PLUS_REV 0x0000 /**< Core revision r0p0 */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define __VTOR_PRESENT 1 /**< Defines if VTOR is present or not */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define __NVIC_PRIO_BITS 2 /**< Number of priority bits implemented in the NVIC */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ |
AnnaBridge | 171:3a7713b1edbc | 197 | |
AnnaBridge | 171:3a7713b1edbc | 198 | #include "core_cm0plus.h" /* Core Peripheral Access Layer */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #include "system_MKL82Z7.h" /* Device specific configuration file */ |
AnnaBridge | 171:3a7713b1edbc | 200 | |
AnnaBridge | 171:3a7713b1edbc | 201 | /*! |
AnnaBridge | 171:3a7713b1edbc | 202 | * @} |
AnnaBridge | 171:3a7713b1edbc | 203 | */ /* end of group Cortex_Core_Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 204 | |
AnnaBridge | 171:3a7713b1edbc | 205 | |
AnnaBridge | 171:3a7713b1edbc | 206 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 207 | -- Mapping Information |
AnnaBridge | 171:3a7713b1edbc | 208 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 209 | |
AnnaBridge | 171:3a7713b1edbc | 210 | /*! |
AnnaBridge | 171:3a7713b1edbc | 211 | * @addtogroup Mapping_Information Mapping Information |
AnnaBridge | 171:3a7713b1edbc | 212 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 213 | */ |
AnnaBridge | 171:3a7713b1edbc | 214 | |
AnnaBridge | 171:3a7713b1edbc | 215 | /** Mapping Information */ |
AnnaBridge | 171:3a7713b1edbc | 216 | /*! |
AnnaBridge | 171:3a7713b1edbc | 217 | * @addtogroup edma_request |
AnnaBridge | 171:3a7713b1edbc | 218 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 219 | */ |
AnnaBridge | 171:3a7713b1edbc | 220 | |
AnnaBridge | 171:3a7713b1edbc | 221 | /******************************************************************************* |
AnnaBridge | 171:3a7713b1edbc | 222 | * Definitions |
AnnaBridge | 171:3a7713b1edbc | 223 | ******************************************************************************/ |
AnnaBridge | 171:3a7713b1edbc | 224 | |
AnnaBridge | 171:3a7713b1edbc | 225 | /*! |
AnnaBridge | 171:3a7713b1edbc | 226 | * @brief Structure for the DMA hardware request |
AnnaBridge | 171:3a7713b1edbc | 227 | * |
AnnaBridge | 171:3a7713b1edbc | 228 | * Defines the structure for the DMA hardware request collections. The user can configure the |
AnnaBridge | 171:3a7713b1edbc | 229 | * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index |
AnnaBridge | 171:3a7713b1edbc | 230 | * of the hardware request varies according to the to SoC. |
AnnaBridge | 171:3a7713b1edbc | 231 | */ |
AnnaBridge | 171:3a7713b1edbc | 232 | typedef enum _dma_request_source |
AnnaBridge | 171:3a7713b1edbc | 233 | { |
AnnaBridge | 171:3a7713b1edbc | 234 | kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */ |
AnnaBridge | 171:3a7713b1edbc | 235 | kDmaRequestMux0FlexIO0Channel0 = 1|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 236 | kDmaRequestMux0FlexIO0Channel1 = 2|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 237 | kDmaRequestMux0FlexIO0Channel2 = 3|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 238 | kDmaRequestMux0FlexIO0Channel3 = 4|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 239 | kDmaRequestMux0FlexIO0Channel4 = 5|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 240 | kDmaRequestMux0FlexIO0Channel5 = 6|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 241 | kDmaRequestMux0FlexIO0Channel6 = 7|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 242 | kDmaRequestMux0FlexIO0Channel7 = 8|0x100U, /**< FLEXIO0. */ |
AnnaBridge | 171:3a7713b1edbc | 243 | kDmaRequestMux0I2C0 = 9|0x100U, /**< I2C0 Transmit or Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 244 | kDmaRequestMux0I2C1 = 10|0x100U, /**< I2C1 Transmit or Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 245 | kDmaRequestMux0Reserved11 = 11|0x100U, /**< Reserved11 */ |
AnnaBridge | 171:3a7713b1edbc | 246 | kDmaRequestMux0Reserved12 = 12|0x100U, /**< Reserved12 */ |
AnnaBridge | 171:3a7713b1edbc | 247 | kDmaRequestMux0Reserved13 = 13|0x100U, /**< Reserved13 */ |
AnnaBridge | 171:3a7713b1edbc | 248 | kDmaRequestMux0Reserved14 = 14|0x100U, /**< Reserved14 */ |
AnnaBridge | 171:3a7713b1edbc | 249 | kDmaRequestMux0LPUART0Rx = 15|0x100U, /**< LPUART0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 250 | kDmaRequestMux0LPUART0Tx = 16|0x100U, /**< LPUART0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 251 | kDmaRequestMux0LPUART1Rx = 17|0x100U, /**< LPUART1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 252 | kDmaRequestMux0LPUART1Tx = 18|0x100U, /**< LPUART1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 253 | kDmaRequestMux0LPUART2Rx = 19|0x100U, /**< LPUART2 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 254 | kDmaRequestMux0LPUART2Tx = 20|0x100U, /**< LPUART2 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 255 | kDmaRequestMux0SPI0Rx = 21|0x100U, /**< SPI0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 256 | kDmaRequestMux0SPI0Tx = 22|0x100U, /**< SPI0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 257 | kDmaRequestMux0SPI1Rx = 23|0x100U, /**< SPI1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 258 | kDmaRequestMux0SPI1Tx = 24|0x100U, /**< SPI1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 259 | kDmaRequestMux0QSPI0Rx = 25|0x100U, /**< QuadSPI0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 260 | kDmaRequestMux0QSPI0Tx = 26|0x100U, /**< QuadSPI0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 261 | kDmaRequestMux0TPM0Channel0 = 27|0x100U, /**< TPM0 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 262 | kDmaRequestMux0TPM0Channel1 = 28|0x100U, /**< TPM0 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 263 | kDmaRequestMux0TPM0Channel2 = 29|0x100U, /**< TPM0 C2V. */ |
AnnaBridge | 171:3a7713b1edbc | 264 | kDmaRequestMux0TPM0Channel3 = 30|0x100U, /**< TPM0 C3V. */ |
AnnaBridge | 171:3a7713b1edbc | 265 | kDmaRequestMux0TPM0Channel4 = 31|0x100U, /**< TPM0 C4V. */ |
AnnaBridge | 171:3a7713b1edbc | 266 | kDmaRequestMux0TPM0Channel5 = 32|0x100U, /**< TPM0 C5V. */ |
AnnaBridge | 171:3a7713b1edbc | 267 | kDmaRequestMux0Reserved33 = 33|0x100U, /**< Reserved33 */ |
AnnaBridge | 171:3a7713b1edbc | 268 | kDmaRequestMux0Reserved34 = 34|0x100U, /**< Reserved34 */ |
AnnaBridge | 171:3a7713b1edbc | 269 | kDmaRequestMux0TPM0Overflow = 35|0x100U, /**< TPM0. */ |
AnnaBridge | 171:3a7713b1edbc | 270 | kDmaRequestMux0TPM1Channel0 = 36|0x100U, /**< TPM1 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 271 | kDmaRequestMux0TPM1Channel1 = 37|0x100U, /**< TPM1 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 272 | kDmaRequestMux0TPM1Overflow = 38|0x100U, /**< TPM1. */ |
AnnaBridge | 171:3a7713b1edbc | 273 | kDmaRequestMux0TPM2Channel0 = 39|0x100U, /**< TPM2 C0V. */ |
AnnaBridge | 171:3a7713b1edbc | 274 | kDmaRequestMux0TPM2Channel1 = 40|0x100U, /**< TPM2 C1V. */ |
AnnaBridge | 171:3a7713b1edbc | 275 | kDmaRequestMux0TPM2Overflow = 41|0x100U, /**< TPM2. */ |
AnnaBridge | 171:3a7713b1edbc | 276 | kDmaRequestMux0TSI0 = 42|0x100U, /**< TSI0. */ |
AnnaBridge | 171:3a7713b1edbc | 277 | kDmaRequestMux0EMVSIM0Rx = 43|0x100U, /**< EMVSIM0 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 278 | kDmaRequestMux0EMVSIM0Tx = 44|0x100U, /**< EMVSIM0 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 279 | kDmaRequestMux0EMVSIM1Rx = 45|0x100U, /**< EMVSIM1 Receive. */ |
AnnaBridge | 171:3a7713b1edbc | 280 | kDmaRequestMux0EMVSIM1Tx = 46|0x100U, /**< EMVSIM1 Transmit. */ |
AnnaBridge | 171:3a7713b1edbc | 281 | kDmaRequestMux0PortA = 47|0x100U, /**< PTA. */ |
AnnaBridge | 171:3a7713b1edbc | 282 | kDmaRequestMux0PortB = 48|0x100U, /**< PTB. */ |
AnnaBridge | 171:3a7713b1edbc | 283 | kDmaRequestMux0PortC = 49|0x100U, /**< PTC. */ |
AnnaBridge | 171:3a7713b1edbc | 284 | kDmaRequestMux0PortD = 50|0x100U, /**< PTD. */ |
AnnaBridge | 171:3a7713b1edbc | 285 | kDmaRequestMux0PortE = 51|0x100U, /**< PTE. */ |
AnnaBridge | 171:3a7713b1edbc | 286 | kDmaRequestMux0ADC0 = 52|0x100U, /**< ADC0. */ |
AnnaBridge | 171:3a7713b1edbc | 287 | kDmaRequestMux0Reserved53 = 53|0x100U, /**< Reserved53 */ |
AnnaBridge | 171:3a7713b1edbc | 288 | kDmaRequestMux0DAC0 = 54|0x100U, /**< DAC0. */ |
AnnaBridge | 171:3a7713b1edbc | 289 | kDmaRequestMux0LTC0PKHA = 55|0x100U, /**< LTC0 PKHA. */ |
AnnaBridge | 171:3a7713b1edbc | 290 | kDmaRequestMux0CMP0 = 56|0x100U, /**< CMP0. */ |
AnnaBridge | 171:3a7713b1edbc | 291 | kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */ |
AnnaBridge | 171:3a7713b1edbc | 292 | kDmaRequestMux0LTC0InputFIFO = 58|0x100U, /**< LTC0 Input FIFO. */ |
AnnaBridge | 171:3a7713b1edbc | 293 | kDmaRequestMux0LTC0OutputFIFO = 59|0x100U, /**< LTC0 Output FIFO. */ |
AnnaBridge | 171:3a7713b1edbc | 294 | kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 295 | kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 296 | kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 297 | kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */ |
AnnaBridge | 171:3a7713b1edbc | 298 | } dma_request_source_t; |
AnnaBridge | 171:3a7713b1edbc | 299 | |
AnnaBridge | 171:3a7713b1edbc | 300 | /* @} */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | |
AnnaBridge | 171:3a7713b1edbc | 303 | /*! |
AnnaBridge | 171:3a7713b1edbc | 304 | * @} |
AnnaBridge | 171:3a7713b1edbc | 305 | */ /* end of group Mapping_Information */ |
AnnaBridge | 171:3a7713b1edbc | 306 | |
AnnaBridge | 171:3a7713b1edbc | 307 | |
AnnaBridge | 171:3a7713b1edbc | 308 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 309 | -- Device Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 310 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 311 | |
AnnaBridge | 171:3a7713b1edbc | 312 | /*! |
AnnaBridge | 171:3a7713b1edbc | 313 | * @addtogroup Peripheral_access_layer Device Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 314 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 315 | */ |
AnnaBridge | 171:3a7713b1edbc | 316 | |
AnnaBridge | 171:3a7713b1edbc | 317 | |
AnnaBridge | 171:3a7713b1edbc | 318 | /* |
AnnaBridge | 171:3a7713b1edbc | 319 | ** Start of section using anonymous unions |
AnnaBridge | 171:3a7713b1edbc | 320 | */ |
AnnaBridge | 171:3a7713b1edbc | 321 | |
AnnaBridge | 171:3a7713b1edbc | 322 | #if defined(__ARMCC_VERSION) |
AnnaBridge | 171:3a7713b1edbc | 323 | #pragma push |
AnnaBridge | 171:3a7713b1edbc | 324 | #pragma anon_unions |
AnnaBridge | 171:3a7713b1edbc | 325 | #elif defined(__CWCC__) |
AnnaBridge | 171:3a7713b1edbc | 326 | #pragma push |
AnnaBridge | 171:3a7713b1edbc | 327 | #pragma cpp_extensions on |
AnnaBridge | 171:3a7713b1edbc | 328 | #elif defined(__GNUC__) |
AnnaBridge | 171:3a7713b1edbc | 329 | /* anonymous unions are enabled by default */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #elif defined(__IAR_SYSTEMS_ICC__) |
AnnaBridge | 171:3a7713b1edbc | 331 | #pragma language=extended |
AnnaBridge | 171:3a7713b1edbc | 332 | #else |
AnnaBridge | 171:3a7713b1edbc | 333 | #error Not supported compiler type |
AnnaBridge | 171:3a7713b1edbc | 334 | #endif |
AnnaBridge | 171:3a7713b1edbc | 335 | |
AnnaBridge | 171:3a7713b1edbc | 336 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 337 | -- ADC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 338 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 339 | |
AnnaBridge | 171:3a7713b1edbc | 340 | /*! |
AnnaBridge | 171:3a7713b1edbc | 341 | * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 342 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 343 | */ |
AnnaBridge | 171:3a7713b1edbc | 344 | |
AnnaBridge | 171:3a7713b1edbc | 345 | /** ADC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 346 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 347 | __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 348 | __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 349 | __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 350 | __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 351 | __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 352 | __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 353 | __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 354 | __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 355 | __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 356 | __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 357 | __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 358 | __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 359 | __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 360 | __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 361 | __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 362 | __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 363 | __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 364 | __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 365 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 366 | __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */ |
AnnaBridge | 171:3a7713b1edbc | 367 | __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 368 | __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */ |
AnnaBridge | 171:3a7713b1edbc | 369 | __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 370 | __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 371 | __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 372 | __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */ |
AnnaBridge | 171:3a7713b1edbc | 373 | } ADC_Type; |
AnnaBridge | 171:3a7713b1edbc | 374 | |
AnnaBridge | 171:3a7713b1edbc | 375 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 376 | -- ADC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 377 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 378 | |
AnnaBridge | 171:3a7713b1edbc | 379 | /*! |
AnnaBridge | 171:3a7713b1edbc | 380 | * @addtogroup ADC_Register_Masks ADC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 381 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 382 | */ |
AnnaBridge | 171:3a7713b1edbc | 383 | |
AnnaBridge | 171:3a7713b1edbc | 384 | /*! @name SC1 - ADC Status and Control Registers 1 */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define ADC_SC1_ADCH_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 386 | #define ADC_SC1_ADCH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 387 | #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 388 | #define ADC_SC1_DIFF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 389 | #define ADC_SC1_DIFF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 390 | #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 391 | #define ADC_SC1_AIEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 392 | #define ADC_SC1_AIEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 393 | #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 394 | #define ADC_SC1_COCO_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 395 | #define ADC_SC1_COCO_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 396 | #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 397 | |
AnnaBridge | 171:3a7713b1edbc | 398 | /* The count of ADC_SC1 */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define ADC_SC1_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 400 | |
AnnaBridge | 171:3a7713b1edbc | 401 | /*! @name CFG1 - ADC Configuration Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define ADC_CFG1_ADICLK_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 403 | #define ADC_CFG1_ADICLK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 404 | #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 405 | #define ADC_CFG1_MODE_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 406 | #define ADC_CFG1_MODE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 407 | #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 408 | #define ADC_CFG1_ADLSMP_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 409 | #define ADC_CFG1_ADLSMP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 410 | #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 411 | #define ADC_CFG1_ADIV_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 412 | #define ADC_CFG1_ADIV_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 413 | #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 414 | #define ADC_CFG1_ADLPC_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 415 | #define ADC_CFG1_ADLPC_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 416 | #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 417 | |
AnnaBridge | 171:3a7713b1edbc | 418 | /*! @name CFG2 - ADC Configuration Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define ADC_CFG2_ADLSTS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 420 | #define ADC_CFG2_ADLSTS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 421 | #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 422 | #define ADC_CFG2_ADHSC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 423 | #define ADC_CFG2_ADHSC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 424 | #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 425 | #define ADC_CFG2_ADACKEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 426 | #define ADC_CFG2_ADACKEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 427 | #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 428 | #define ADC_CFG2_MUXSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 429 | #define ADC_CFG2_MUXSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 430 | #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 431 | |
AnnaBridge | 171:3a7713b1edbc | 432 | /*! @name R - ADC Data Result Register */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define ADC_R_D_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 434 | #define ADC_R_D_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 435 | #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK) |
AnnaBridge | 171:3a7713b1edbc | 436 | |
AnnaBridge | 171:3a7713b1edbc | 437 | /* The count of ADC_R */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define ADC_R_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 439 | |
AnnaBridge | 171:3a7713b1edbc | 440 | /*! @name CV1 - Compare Value Registers */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define ADC_CV1_CV_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 442 | #define ADC_CV1_CV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 443 | #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 444 | |
AnnaBridge | 171:3a7713b1edbc | 445 | /*! @name CV2 - Compare Value Registers */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #define ADC_CV2_CV_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 447 | #define ADC_CV2_CV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 448 | #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 449 | |
AnnaBridge | 171:3a7713b1edbc | 450 | /*! @name SC2 - Status and Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 451 | #define ADC_SC2_REFSEL_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 452 | #define ADC_SC2_REFSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 453 | #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 454 | #define ADC_SC2_DMAEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 455 | #define ADC_SC2_DMAEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 456 | #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 457 | #define ADC_SC2_ACREN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 458 | #define ADC_SC2_ACREN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 459 | #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 460 | #define ADC_SC2_ACFGT_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 461 | #define ADC_SC2_ACFGT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 462 | #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 463 | #define ADC_SC2_ACFE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 464 | #define ADC_SC2_ACFE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 465 | #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 466 | #define ADC_SC2_ADTRG_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 467 | #define ADC_SC2_ADTRG_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 468 | #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 469 | #define ADC_SC2_ADACT_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 470 | #define ADC_SC2_ADACT_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 471 | #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 472 | |
AnnaBridge | 171:3a7713b1edbc | 473 | /*! @name SC3 - Status and Control Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #define ADC_SC3_AVGS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 475 | #define ADC_SC3_AVGS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 476 | #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 477 | #define ADC_SC3_AVGE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 478 | #define ADC_SC3_AVGE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 479 | #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 480 | #define ADC_SC3_ADCO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 481 | #define ADC_SC3_ADCO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 482 | #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 483 | #define ADC_SC3_CALF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 484 | #define ADC_SC3_CALF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 485 | #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 486 | #define ADC_SC3_CAL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 487 | #define ADC_SC3_CAL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 488 | #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 489 | |
AnnaBridge | 171:3a7713b1edbc | 490 | /*! @name OFS - ADC Offset Correction Register */ |
AnnaBridge | 171:3a7713b1edbc | 491 | #define ADC_OFS_OFS_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 492 | #define ADC_OFS_OFS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 493 | #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 494 | |
AnnaBridge | 171:3a7713b1edbc | 495 | /*! @name PG - ADC Plus-Side Gain Register */ |
AnnaBridge | 171:3a7713b1edbc | 496 | #define ADC_PG_PG_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 497 | #define ADC_PG_PG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 498 | #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 499 | |
AnnaBridge | 171:3a7713b1edbc | 500 | /*! @name MG - ADC Minus-Side Gain Register */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #define ADC_MG_MG_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 502 | #define ADC_MG_MG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 503 | #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 504 | |
AnnaBridge | 171:3a7713b1edbc | 505 | /*! @name CLPD - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define ADC_CLPD_CLPD_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 507 | #define ADC_CLPD_CLPD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 508 | #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 509 | |
AnnaBridge | 171:3a7713b1edbc | 510 | /*! @name CLPS - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 511 | #define ADC_CLPS_CLPS_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 512 | #define ADC_CLPS_CLPS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 513 | #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 514 | |
AnnaBridge | 171:3a7713b1edbc | 515 | /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define ADC_CLP4_CLP4_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 517 | #define ADC_CLP4_CLP4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 518 | #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 519 | |
AnnaBridge | 171:3a7713b1edbc | 520 | /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 521 | #define ADC_CLP3_CLP3_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 522 | #define ADC_CLP3_CLP3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 523 | #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 524 | |
AnnaBridge | 171:3a7713b1edbc | 525 | /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 526 | #define ADC_CLP2_CLP2_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 527 | #define ADC_CLP2_CLP2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 528 | #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 529 | |
AnnaBridge | 171:3a7713b1edbc | 530 | /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define ADC_CLP1_CLP1_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 532 | #define ADC_CLP1_CLP1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 533 | #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 534 | |
AnnaBridge | 171:3a7713b1edbc | 535 | /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 536 | #define ADC_CLP0_CLP0_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 537 | #define ADC_CLP0_CLP0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 538 | #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 539 | |
AnnaBridge | 171:3a7713b1edbc | 540 | /*! @name CLMD - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 541 | #define ADC_CLMD_CLMD_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 542 | #define ADC_CLMD_CLMD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 543 | #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 544 | |
AnnaBridge | 171:3a7713b1edbc | 545 | /*! @name CLMS - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 546 | #define ADC_CLMS_CLMS_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 547 | #define ADC_CLMS_CLMS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 548 | #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 549 | |
AnnaBridge | 171:3a7713b1edbc | 550 | /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 551 | #define ADC_CLM4_CLM4_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 552 | #define ADC_CLM4_CLM4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 553 | #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 554 | |
AnnaBridge | 171:3a7713b1edbc | 555 | /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 556 | #define ADC_CLM3_CLM3_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 557 | #define ADC_CLM3_CLM3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 558 | #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 559 | |
AnnaBridge | 171:3a7713b1edbc | 560 | /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 561 | #define ADC_CLM2_CLM2_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 562 | #define ADC_CLM2_CLM2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 563 | #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 564 | |
AnnaBridge | 171:3a7713b1edbc | 565 | /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 566 | #define ADC_CLM1_CLM1_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 567 | #define ADC_CLM1_CLM1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 568 | #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 569 | |
AnnaBridge | 171:3a7713b1edbc | 570 | /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 571 | #define ADC_CLM0_CLM0_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 572 | #define ADC_CLM0_CLM0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 573 | #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 574 | |
AnnaBridge | 171:3a7713b1edbc | 575 | |
AnnaBridge | 171:3a7713b1edbc | 576 | /*! |
AnnaBridge | 171:3a7713b1edbc | 577 | * @} |
AnnaBridge | 171:3a7713b1edbc | 578 | */ /* end of group ADC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 579 | |
AnnaBridge | 171:3a7713b1edbc | 580 | |
AnnaBridge | 171:3a7713b1edbc | 581 | /* ADC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 582 | /** Peripheral ADC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 583 | #define ADC0_BASE (0x4003B000u) |
AnnaBridge | 171:3a7713b1edbc | 584 | /** Peripheral ADC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 585 | #define ADC0 ((ADC_Type *)ADC0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 586 | /** Array initializer of ADC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 587 | #define ADC_BASE_ADDRS { ADC0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 588 | /** Array initializer of ADC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 589 | #define ADC_BASE_PTRS { ADC0 } |
AnnaBridge | 171:3a7713b1edbc | 590 | /** Interrupt vectors for the ADC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 591 | #define ADC_IRQS { ADC0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 592 | |
AnnaBridge | 171:3a7713b1edbc | 593 | /*! |
AnnaBridge | 171:3a7713b1edbc | 594 | * @} |
AnnaBridge | 171:3a7713b1edbc | 595 | */ /* end of group ADC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 596 | |
AnnaBridge | 171:3a7713b1edbc | 597 | |
AnnaBridge | 171:3a7713b1edbc | 598 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 599 | -- AIPS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 600 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 601 | |
AnnaBridge | 171:3a7713b1edbc | 602 | /*! |
AnnaBridge | 171:3a7713b1edbc | 603 | * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 604 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 605 | */ |
AnnaBridge | 171:3a7713b1edbc | 606 | |
AnnaBridge | 171:3a7713b1edbc | 607 | /** AIPS - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 608 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 609 | __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 610 | uint8_t RESERVED_0[28]; |
AnnaBridge | 171:3a7713b1edbc | 611 | __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 612 | __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 613 | __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 614 | __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 615 | uint8_t RESERVED_1[16]; |
AnnaBridge | 171:3a7713b1edbc | 616 | __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 617 | __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 618 | __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 619 | __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 620 | __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */ |
AnnaBridge | 171:3a7713b1edbc | 621 | __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */ |
AnnaBridge | 171:3a7713b1edbc | 622 | __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 623 | __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */ |
AnnaBridge | 171:3a7713b1edbc | 624 | __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 625 | __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 626 | __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 627 | __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */ |
AnnaBridge | 171:3a7713b1edbc | 628 | } AIPS_Type; |
AnnaBridge | 171:3a7713b1edbc | 629 | |
AnnaBridge | 171:3a7713b1edbc | 630 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 631 | -- AIPS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 632 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 633 | |
AnnaBridge | 171:3a7713b1edbc | 634 | /*! |
AnnaBridge | 171:3a7713b1edbc | 635 | * @addtogroup AIPS_Register_Masks AIPS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 636 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 637 | */ |
AnnaBridge | 171:3a7713b1edbc | 638 | |
AnnaBridge | 171:3a7713b1edbc | 639 | /*! @name MPRA - Master Privilege Register A */ |
AnnaBridge | 171:3a7713b1edbc | 640 | #define AIPS_MPRA_MPL4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 641 | #define AIPS_MPRA_MPL4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 642 | #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 643 | #define AIPS_MPRA_MTW4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 644 | #define AIPS_MPRA_MTW4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 645 | #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 646 | #define AIPS_MPRA_MTR4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 647 | #define AIPS_MPRA_MTR4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 648 | #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 649 | #define AIPS_MPRA_MPL3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 650 | #define AIPS_MPRA_MPL3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 651 | #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 652 | #define AIPS_MPRA_MTW3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 653 | #define AIPS_MPRA_MTW3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 654 | #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 655 | #define AIPS_MPRA_MTR3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 656 | #define AIPS_MPRA_MTR3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 657 | #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 658 | #define AIPS_MPRA_MPL2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 659 | #define AIPS_MPRA_MPL2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 660 | #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 661 | #define AIPS_MPRA_MTW2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 662 | #define AIPS_MPRA_MTW2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 663 | #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 664 | #define AIPS_MPRA_MTR2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 665 | #define AIPS_MPRA_MTR2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 666 | #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 667 | #define AIPS_MPRA_MPL1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 668 | #define AIPS_MPRA_MPL1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 669 | #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 670 | #define AIPS_MPRA_MTW1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 671 | #define AIPS_MPRA_MTW1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 672 | #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 673 | #define AIPS_MPRA_MTR1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 674 | #define AIPS_MPRA_MTR1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 675 | #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 676 | #define AIPS_MPRA_MPL0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 677 | #define AIPS_MPRA_MPL0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 678 | #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 679 | #define AIPS_MPRA_MTW0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 680 | #define AIPS_MPRA_MTW0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 681 | #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 682 | #define AIPS_MPRA_MTR0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 683 | #define AIPS_MPRA_MTR0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 684 | #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 685 | |
AnnaBridge | 171:3a7713b1edbc | 686 | /*! @name PACRA - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 687 | #define AIPS_PACRA_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 688 | #define AIPS_PACRA_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 689 | #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 690 | #define AIPS_PACRA_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 691 | #define AIPS_PACRA_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 692 | #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 693 | #define AIPS_PACRA_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 694 | #define AIPS_PACRA_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 695 | #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 696 | #define AIPS_PACRA_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 697 | #define AIPS_PACRA_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 698 | #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 699 | #define AIPS_PACRA_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 700 | #define AIPS_PACRA_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 701 | #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 702 | #define AIPS_PACRA_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 703 | #define AIPS_PACRA_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 704 | #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 705 | #define AIPS_PACRA_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 706 | #define AIPS_PACRA_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 707 | #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 708 | #define AIPS_PACRA_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 709 | #define AIPS_PACRA_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 710 | #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 711 | #define AIPS_PACRA_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 712 | #define AIPS_PACRA_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 713 | #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 714 | #define AIPS_PACRA_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 715 | #define AIPS_PACRA_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 716 | #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 717 | #define AIPS_PACRA_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 718 | #define AIPS_PACRA_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 719 | #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 720 | #define AIPS_PACRA_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 721 | #define AIPS_PACRA_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 722 | #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 723 | #define AIPS_PACRA_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 724 | #define AIPS_PACRA_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 725 | #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 726 | #define AIPS_PACRA_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 727 | #define AIPS_PACRA_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 728 | #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 729 | #define AIPS_PACRA_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 730 | #define AIPS_PACRA_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 731 | #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 732 | #define AIPS_PACRA_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 733 | #define AIPS_PACRA_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 734 | #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 735 | #define AIPS_PACRA_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 736 | #define AIPS_PACRA_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 737 | #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 738 | #define AIPS_PACRA_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 739 | #define AIPS_PACRA_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 740 | #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 741 | #define AIPS_PACRA_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 742 | #define AIPS_PACRA_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 743 | #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 744 | #define AIPS_PACRA_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 745 | #define AIPS_PACRA_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 746 | #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 747 | #define AIPS_PACRA_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 748 | #define AIPS_PACRA_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 749 | #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 750 | #define AIPS_PACRA_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 751 | #define AIPS_PACRA_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 752 | #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 753 | #define AIPS_PACRA_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 754 | #define AIPS_PACRA_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 755 | #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 756 | #define AIPS_PACRA_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 757 | #define AIPS_PACRA_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 758 | #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 759 | |
AnnaBridge | 171:3a7713b1edbc | 760 | /*! @name PACRB - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 761 | #define AIPS_PACRB_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 762 | #define AIPS_PACRB_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 763 | #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 764 | #define AIPS_PACRB_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 765 | #define AIPS_PACRB_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 766 | #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 767 | #define AIPS_PACRB_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 768 | #define AIPS_PACRB_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 769 | #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 770 | #define AIPS_PACRB_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 771 | #define AIPS_PACRB_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 772 | #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 773 | #define AIPS_PACRB_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 774 | #define AIPS_PACRB_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 775 | #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 776 | #define AIPS_PACRB_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 777 | #define AIPS_PACRB_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 778 | #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 779 | #define AIPS_PACRB_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 780 | #define AIPS_PACRB_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 781 | #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 782 | #define AIPS_PACRB_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 783 | #define AIPS_PACRB_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 784 | #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 785 | #define AIPS_PACRB_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 786 | #define AIPS_PACRB_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 787 | #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 788 | #define AIPS_PACRB_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 789 | #define AIPS_PACRB_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 790 | #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 791 | #define AIPS_PACRB_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 792 | #define AIPS_PACRB_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 793 | #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 794 | #define AIPS_PACRB_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 795 | #define AIPS_PACRB_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 796 | #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 797 | #define AIPS_PACRB_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 798 | #define AIPS_PACRB_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 799 | #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 800 | #define AIPS_PACRB_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 801 | #define AIPS_PACRB_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 802 | #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 803 | #define AIPS_PACRB_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 804 | #define AIPS_PACRB_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 805 | #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 806 | #define AIPS_PACRB_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 807 | #define AIPS_PACRB_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 808 | #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 809 | #define AIPS_PACRB_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 810 | #define AIPS_PACRB_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 811 | #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 812 | #define AIPS_PACRB_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 813 | #define AIPS_PACRB_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 814 | #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 815 | #define AIPS_PACRB_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 816 | #define AIPS_PACRB_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 817 | #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 818 | #define AIPS_PACRB_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 819 | #define AIPS_PACRB_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 820 | #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 821 | #define AIPS_PACRB_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 822 | #define AIPS_PACRB_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 823 | #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 824 | #define AIPS_PACRB_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 825 | #define AIPS_PACRB_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 826 | #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 827 | #define AIPS_PACRB_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 828 | #define AIPS_PACRB_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 829 | #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 830 | #define AIPS_PACRB_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 831 | #define AIPS_PACRB_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 832 | #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 833 | |
AnnaBridge | 171:3a7713b1edbc | 834 | /*! @name PACRC - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 835 | #define AIPS_PACRC_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 836 | #define AIPS_PACRC_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 837 | #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 838 | #define AIPS_PACRC_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 839 | #define AIPS_PACRC_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 840 | #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 841 | #define AIPS_PACRC_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 842 | #define AIPS_PACRC_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 843 | #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 844 | #define AIPS_PACRC_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 845 | #define AIPS_PACRC_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 846 | #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 847 | #define AIPS_PACRC_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 848 | #define AIPS_PACRC_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 849 | #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 850 | #define AIPS_PACRC_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 851 | #define AIPS_PACRC_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 852 | #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 853 | #define AIPS_PACRC_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 854 | #define AIPS_PACRC_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 855 | #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 856 | #define AIPS_PACRC_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 857 | #define AIPS_PACRC_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 858 | #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 859 | #define AIPS_PACRC_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 860 | #define AIPS_PACRC_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 861 | #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 862 | #define AIPS_PACRC_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 863 | #define AIPS_PACRC_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 864 | #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 865 | #define AIPS_PACRC_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 866 | #define AIPS_PACRC_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 867 | #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 868 | #define AIPS_PACRC_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 869 | #define AIPS_PACRC_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 870 | #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 871 | #define AIPS_PACRC_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 872 | #define AIPS_PACRC_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 873 | #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 874 | #define AIPS_PACRC_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 875 | #define AIPS_PACRC_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 876 | #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 877 | #define AIPS_PACRC_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 878 | #define AIPS_PACRC_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 879 | #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 880 | #define AIPS_PACRC_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 881 | #define AIPS_PACRC_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 882 | #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 883 | #define AIPS_PACRC_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 884 | #define AIPS_PACRC_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 885 | #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 886 | #define AIPS_PACRC_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 887 | #define AIPS_PACRC_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 888 | #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 889 | #define AIPS_PACRC_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 890 | #define AIPS_PACRC_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 891 | #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 892 | #define AIPS_PACRC_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 893 | #define AIPS_PACRC_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 894 | #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 895 | #define AIPS_PACRC_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 896 | #define AIPS_PACRC_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 897 | #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 898 | #define AIPS_PACRC_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 899 | #define AIPS_PACRC_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 900 | #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 901 | #define AIPS_PACRC_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 902 | #define AIPS_PACRC_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 903 | #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 904 | #define AIPS_PACRC_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 905 | #define AIPS_PACRC_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 906 | #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 907 | |
AnnaBridge | 171:3a7713b1edbc | 908 | /*! @name PACRD - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 909 | #define AIPS_PACRD_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 910 | #define AIPS_PACRD_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 911 | #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 912 | #define AIPS_PACRD_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 913 | #define AIPS_PACRD_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 914 | #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 915 | #define AIPS_PACRD_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 916 | #define AIPS_PACRD_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 917 | #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 918 | #define AIPS_PACRD_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 919 | #define AIPS_PACRD_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 920 | #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 921 | #define AIPS_PACRD_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 922 | #define AIPS_PACRD_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 923 | #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 924 | #define AIPS_PACRD_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 925 | #define AIPS_PACRD_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 926 | #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 927 | #define AIPS_PACRD_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 928 | #define AIPS_PACRD_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 929 | #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 930 | #define AIPS_PACRD_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 931 | #define AIPS_PACRD_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 932 | #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 933 | #define AIPS_PACRD_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 934 | #define AIPS_PACRD_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 935 | #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 936 | #define AIPS_PACRD_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 937 | #define AIPS_PACRD_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 938 | #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 939 | #define AIPS_PACRD_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 940 | #define AIPS_PACRD_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 941 | #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 942 | #define AIPS_PACRD_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 943 | #define AIPS_PACRD_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 944 | #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 945 | #define AIPS_PACRD_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 946 | #define AIPS_PACRD_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 947 | #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 948 | #define AIPS_PACRD_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 949 | #define AIPS_PACRD_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 950 | #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 951 | #define AIPS_PACRD_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 952 | #define AIPS_PACRD_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 953 | #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 954 | #define AIPS_PACRD_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 955 | #define AIPS_PACRD_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 956 | #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 957 | #define AIPS_PACRD_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 958 | #define AIPS_PACRD_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 959 | #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 960 | #define AIPS_PACRD_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 961 | #define AIPS_PACRD_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 962 | #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 963 | #define AIPS_PACRD_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 964 | #define AIPS_PACRD_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 965 | #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 966 | #define AIPS_PACRD_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 967 | #define AIPS_PACRD_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 968 | #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 969 | #define AIPS_PACRD_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 970 | #define AIPS_PACRD_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 971 | #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 972 | #define AIPS_PACRD_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 973 | #define AIPS_PACRD_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 974 | #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 975 | #define AIPS_PACRD_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 976 | #define AIPS_PACRD_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 977 | #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 978 | #define AIPS_PACRD_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 979 | #define AIPS_PACRD_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 980 | #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 981 | |
AnnaBridge | 171:3a7713b1edbc | 982 | /*! @name PACRE - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 983 | #define AIPS_PACRE_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 984 | #define AIPS_PACRE_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 985 | #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 986 | #define AIPS_PACRE_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 987 | #define AIPS_PACRE_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 988 | #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 989 | #define AIPS_PACRE_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 990 | #define AIPS_PACRE_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 991 | #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 992 | #define AIPS_PACRE_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 993 | #define AIPS_PACRE_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 994 | #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 995 | #define AIPS_PACRE_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 996 | #define AIPS_PACRE_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 997 | #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 998 | #define AIPS_PACRE_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 999 | #define AIPS_PACRE_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1000 | #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define AIPS_PACRE_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1002 | #define AIPS_PACRE_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1003 | #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1004 | #define AIPS_PACRE_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1005 | #define AIPS_PACRE_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1006 | #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1007 | #define AIPS_PACRE_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1008 | #define AIPS_PACRE_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1009 | #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1010 | #define AIPS_PACRE_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1011 | #define AIPS_PACRE_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1012 | #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1013 | #define AIPS_PACRE_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1014 | #define AIPS_PACRE_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1015 | #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1016 | #define AIPS_PACRE_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1017 | #define AIPS_PACRE_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1018 | #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1019 | #define AIPS_PACRE_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1020 | #define AIPS_PACRE_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1021 | #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1022 | #define AIPS_PACRE_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1023 | #define AIPS_PACRE_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1024 | #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1025 | #define AIPS_PACRE_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1026 | #define AIPS_PACRE_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1027 | #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1028 | #define AIPS_PACRE_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define AIPS_PACRE_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1030 | #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1031 | #define AIPS_PACRE_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1032 | #define AIPS_PACRE_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1034 | #define AIPS_PACRE_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define AIPS_PACRE_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1036 | #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1037 | #define AIPS_PACRE_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1038 | #define AIPS_PACRE_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1040 | #define AIPS_PACRE_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define AIPS_PACRE_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1042 | #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define AIPS_PACRE_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1044 | #define AIPS_PACRE_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1046 | #define AIPS_PACRE_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1047 | #define AIPS_PACRE_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1048 | #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1049 | #define AIPS_PACRE_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1050 | #define AIPS_PACRE_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1051 | #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1052 | #define AIPS_PACRE_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1053 | #define AIPS_PACRE_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1054 | #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1055 | |
AnnaBridge | 171:3a7713b1edbc | 1056 | /*! @name PACRF - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1057 | #define AIPS_PACRF_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1058 | #define AIPS_PACRF_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1059 | #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1060 | #define AIPS_PACRF_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1061 | #define AIPS_PACRF_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1062 | #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1063 | #define AIPS_PACRF_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1064 | #define AIPS_PACRF_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1065 | #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1066 | #define AIPS_PACRF_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define AIPS_PACRF_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1068 | #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1069 | #define AIPS_PACRF_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1070 | #define AIPS_PACRF_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1072 | #define AIPS_PACRF_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define AIPS_PACRF_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1074 | #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define AIPS_PACRF_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define AIPS_PACRF_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1078 | #define AIPS_PACRF_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1079 | #define AIPS_PACRF_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1080 | #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1081 | #define AIPS_PACRF_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1082 | #define AIPS_PACRF_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1083 | #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1084 | #define AIPS_PACRF_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1085 | #define AIPS_PACRF_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1086 | #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1087 | #define AIPS_PACRF_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1088 | #define AIPS_PACRF_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1089 | #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1090 | #define AIPS_PACRF_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1091 | #define AIPS_PACRF_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1092 | #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1093 | #define AIPS_PACRF_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1094 | #define AIPS_PACRF_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1095 | #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1096 | #define AIPS_PACRF_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1097 | #define AIPS_PACRF_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1098 | #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1099 | #define AIPS_PACRF_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1100 | #define AIPS_PACRF_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1101 | #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1102 | #define AIPS_PACRF_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1103 | #define AIPS_PACRF_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1104 | #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define AIPS_PACRF_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define AIPS_PACRF_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1108 | #define AIPS_PACRF_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define AIPS_PACRF_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1110 | #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define AIPS_PACRF_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1112 | #define AIPS_PACRF_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1113 | #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1114 | #define AIPS_PACRF_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define AIPS_PACRF_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1116 | #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1117 | #define AIPS_PACRF_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1118 | #define AIPS_PACRF_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1120 | #define AIPS_PACRF_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define AIPS_PACRF_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1122 | #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1123 | #define AIPS_PACRF_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1124 | #define AIPS_PACRF_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1125 | #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1126 | #define AIPS_PACRF_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1127 | #define AIPS_PACRF_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1128 | #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1129 | |
AnnaBridge | 171:3a7713b1edbc | 1130 | /*! @name PACRG - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | #define AIPS_PACRG_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1132 | #define AIPS_PACRG_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1133 | #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1134 | #define AIPS_PACRG_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1135 | #define AIPS_PACRG_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1136 | #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1137 | #define AIPS_PACRG_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1138 | #define AIPS_PACRG_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1139 | #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1140 | #define AIPS_PACRG_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1141 | #define AIPS_PACRG_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1142 | #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1143 | #define AIPS_PACRG_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1144 | #define AIPS_PACRG_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1146 | #define AIPS_PACRG_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define AIPS_PACRG_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1148 | #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define AIPS_PACRG_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1150 | #define AIPS_PACRG_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1152 | #define AIPS_PACRG_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1153 | #define AIPS_PACRG_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1154 | #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1155 | #define AIPS_PACRG_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1156 | #define AIPS_PACRG_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1157 | #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1158 | #define AIPS_PACRG_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1159 | #define AIPS_PACRG_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1160 | #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1161 | #define AIPS_PACRG_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1162 | #define AIPS_PACRG_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1163 | #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1164 | #define AIPS_PACRG_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1165 | #define AIPS_PACRG_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1166 | #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1167 | #define AIPS_PACRG_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1168 | #define AIPS_PACRG_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1169 | #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1170 | #define AIPS_PACRG_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1171 | #define AIPS_PACRG_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1172 | #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1173 | #define AIPS_PACRG_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1174 | #define AIPS_PACRG_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1175 | #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1176 | #define AIPS_PACRG_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1177 | #define AIPS_PACRG_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1178 | #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define AIPS_PACRG_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1180 | #define AIPS_PACRG_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1181 | #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1182 | #define AIPS_PACRG_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define AIPS_PACRG_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1184 | #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1185 | #define AIPS_PACRG_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1186 | #define AIPS_PACRG_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1188 | #define AIPS_PACRG_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define AIPS_PACRG_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1190 | #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define AIPS_PACRG_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1192 | #define AIPS_PACRG_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1194 | #define AIPS_PACRG_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define AIPS_PACRG_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1196 | #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define AIPS_PACRG_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1198 | #define AIPS_PACRG_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1199 | #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1200 | #define AIPS_PACRG_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define AIPS_PACRG_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1202 | #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1203 | |
AnnaBridge | 171:3a7713b1edbc | 1204 | /*! @name PACRH - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1205 | #define AIPS_PACRH_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1206 | #define AIPS_PACRH_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1207 | #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1208 | #define AIPS_PACRH_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1209 | #define AIPS_PACRH_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1210 | #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1211 | #define AIPS_PACRH_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1212 | #define AIPS_PACRH_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1213 | #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1214 | #define AIPS_PACRH_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1215 | #define AIPS_PACRH_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1216 | #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1217 | #define AIPS_PACRH_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1218 | #define AIPS_PACRH_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1219 | #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1220 | #define AIPS_PACRH_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1221 | #define AIPS_PACRH_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1222 | #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1223 | #define AIPS_PACRH_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1224 | #define AIPS_PACRH_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1225 | #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1226 | #define AIPS_PACRH_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1227 | #define AIPS_PACRH_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1228 | #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1229 | #define AIPS_PACRH_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1230 | #define AIPS_PACRH_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1231 | #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1232 | #define AIPS_PACRH_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1233 | #define AIPS_PACRH_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1234 | #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1235 | #define AIPS_PACRH_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1236 | #define AIPS_PACRH_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1237 | #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1238 | #define AIPS_PACRH_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1239 | #define AIPS_PACRH_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1240 | #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1241 | #define AIPS_PACRH_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1242 | #define AIPS_PACRH_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1243 | #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1244 | #define AIPS_PACRH_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1245 | #define AIPS_PACRH_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1246 | #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1247 | #define AIPS_PACRH_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1248 | #define AIPS_PACRH_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1249 | #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1250 | #define AIPS_PACRH_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1251 | #define AIPS_PACRH_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1252 | #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1253 | #define AIPS_PACRH_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1254 | #define AIPS_PACRH_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1255 | #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1256 | #define AIPS_PACRH_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1257 | #define AIPS_PACRH_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1258 | #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1259 | #define AIPS_PACRH_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1260 | #define AIPS_PACRH_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1261 | #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1262 | #define AIPS_PACRH_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1263 | #define AIPS_PACRH_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1264 | #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1265 | #define AIPS_PACRH_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1266 | #define AIPS_PACRH_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1267 | #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1268 | #define AIPS_PACRH_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1269 | #define AIPS_PACRH_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1270 | #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1271 | #define AIPS_PACRH_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1272 | #define AIPS_PACRH_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1273 | #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1274 | #define AIPS_PACRH_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1275 | #define AIPS_PACRH_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1276 | #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1277 | |
AnnaBridge | 171:3a7713b1edbc | 1278 | /*! @name PACRI - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1279 | #define AIPS_PACRI_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1280 | #define AIPS_PACRI_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1281 | #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1282 | #define AIPS_PACRI_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1283 | #define AIPS_PACRI_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1284 | #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1285 | #define AIPS_PACRI_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1286 | #define AIPS_PACRI_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1287 | #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1288 | #define AIPS_PACRI_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1289 | #define AIPS_PACRI_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1290 | #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1291 | #define AIPS_PACRI_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1292 | #define AIPS_PACRI_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1293 | #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1294 | #define AIPS_PACRI_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1295 | #define AIPS_PACRI_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1296 | #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1297 | #define AIPS_PACRI_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1298 | #define AIPS_PACRI_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1299 | #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1300 | #define AIPS_PACRI_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1301 | #define AIPS_PACRI_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1302 | #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1303 | #define AIPS_PACRI_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1304 | #define AIPS_PACRI_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1305 | #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1306 | #define AIPS_PACRI_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1307 | #define AIPS_PACRI_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1308 | #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1309 | #define AIPS_PACRI_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1310 | #define AIPS_PACRI_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1311 | #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1312 | #define AIPS_PACRI_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1313 | #define AIPS_PACRI_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1314 | #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1315 | #define AIPS_PACRI_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1316 | #define AIPS_PACRI_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1317 | #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1318 | #define AIPS_PACRI_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1319 | #define AIPS_PACRI_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1320 | #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1321 | #define AIPS_PACRI_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1322 | #define AIPS_PACRI_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1323 | #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1324 | #define AIPS_PACRI_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1325 | #define AIPS_PACRI_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1326 | #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1327 | #define AIPS_PACRI_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1328 | #define AIPS_PACRI_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1329 | #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1330 | #define AIPS_PACRI_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1331 | #define AIPS_PACRI_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1332 | #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1333 | #define AIPS_PACRI_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1334 | #define AIPS_PACRI_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1335 | #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1336 | #define AIPS_PACRI_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1337 | #define AIPS_PACRI_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1338 | #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1339 | #define AIPS_PACRI_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1340 | #define AIPS_PACRI_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1341 | #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1342 | #define AIPS_PACRI_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1343 | #define AIPS_PACRI_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1344 | #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1345 | #define AIPS_PACRI_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1346 | #define AIPS_PACRI_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1347 | #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1348 | #define AIPS_PACRI_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1349 | #define AIPS_PACRI_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1350 | #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1351 | |
AnnaBridge | 171:3a7713b1edbc | 1352 | /*! @name PACRJ - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1353 | #define AIPS_PACRJ_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1354 | #define AIPS_PACRJ_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1355 | #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1356 | #define AIPS_PACRJ_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1357 | #define AIPS_PACRJ_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1358 | #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1359 | #define AIPS_PACRJ_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1360 | #define AIPS_PACRJ_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1361 | #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1362 | #define AIPS_PACRJ_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1363 | #define AIPS_PACRJ_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1364 | #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1365 | #define AIPS_PACRJ_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1366 | #define AIPS_PACRJ_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1367 | #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1368 | #define AIPS_PACRJ_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1369 | #define AIPS_PACRJ_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1370 | #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1371 | #define AIPS_PACRJ_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1372 | #define AIPS_PACRJ_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1373 | #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1374 | #define AIPS_PACRJ_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1375 | #define AIPS_PACRJ_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1376 | #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1377 | #define AIPS_PACRJ_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1378 | #define AIPS_PACRJ_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1379 | #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1380 | #define AIPS_PACRJ_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1381 | #define AIPS_PACRJ_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1382 | #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1383 | #define AIPS_PACRJ_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1384 | #define AIPS_PACRJ_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1385 | #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1386 | #define AIPS_PACRJ_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define AIPS_PACRJ_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1388 | #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1389 | #define AIPS_PACRJ_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1390 | #define AIPS_PACRJ_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1391 | #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1392 | #define AIPS_PACRJ_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1393 | #define AIPS_PACRJ_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1394 | #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1395 | #define AIPS_PACRJ_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1396 | #define AIPS_PACRJ_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1397 | #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1398 | #define AIPS_PACRJ_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1399 | #define AIPS_PACRJ_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1400 | #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1401 | #define AIPS_PACRJ_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1402 | #define AIPS_PACRJ_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1403 | #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1404 | #define AIPS_PACRJ_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1405 | #define AIPS_PACRJ_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1406 | #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1407 | #define AIPS_PACRJ_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1408 | #define AIPS_PACRJ_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1409 | #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1410 | #define AIPS_PACRJ_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1411 | #define AIPS_PACRJ_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1412 | #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1413 | #define AIPS_PACRJ_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1414 | #define AIPS_PACRJ_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1415 | #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1416 | #define AIPS_PACRJ_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1417 | #define AIPS_PACRJ_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1418 | #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1419 | #define AIPS_PACRJ_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1420 | #define AIPS_PACRJ_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1421 | #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1422 | #define AIPS_PACRJ_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1423 | #define AIPS_PACRJ_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1424 | #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1425 | |
AnnaBridge | 171:3a7713b1edbc | 1426 | /*! @name PACRK - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define AIPS_PACRK_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1428 | #define AIPS_PACRK_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1429 | #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1430 | #define AIPS_PACRK_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1431 | #define AIPS_PACRK_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1432 | #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1433 | #define AIPS_PACRK_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1434 | #define AIPS_PACRK_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1435 | #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1436 | #define AIPS_PACRK_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1437 | #define AIPS_PACRK_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1438 | #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1439 | #define AIPS_PACRK_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1440 | #define AIPS_PACRK_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1441 | #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1442 | #define AIPS_PACRK_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1443 | #define AIPS_PACRK_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1444 | #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1445 | #define AIPS_PACRK_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1446 | #define AIPS_PACRK_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1447 | #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1448 | #define AIPS_PACRK_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1449 | #define AIPS_PACRK_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1450 | #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1451 | #define AIPS_PACRK_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1452 | #define AIPS_PACRK_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1453 | #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1454 | #define AIPS_PACRK_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1455 | #define AIPS_PACRK_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1456 | #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1457 | #define AIPS_PACRK_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1458 | #define AIPS_PACRK_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1459 | #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1460 | #define AIPS_PACRK_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1461 | #define AIPS_PACRK_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1462 | #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1463 | #define AIPS_PACRK_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1464 | #define AIPS_PACRK_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1465 | #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1466 | #define AIPS_PACRK_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1467 | #define AIPS_PACRK_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1468 | #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1469 | #define AIPS_PACRK_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1470 | #define AIPS_PACRK_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1471 | #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1472 | #define AIPS_PACRK_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1473 | #define AIPS_PACRK_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1474 | #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1475 | #define AIPS_PACRK_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1476 | #define AIPS_PACRK_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1477 | #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1478 | #define AIPS_PACRK_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1479 | #define AIPS_PACRK_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1480 | #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define AIPS_PACRK_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1482 | #define AIPS_PACRK_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1484 | #define AIPS_PACRK_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1485 | #define AIPS_PACRK_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1486 | #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1487 | #define AIPS_PACRK_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1488 | #define AIPS_PACRK_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1489 | #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1490 | #define AIPS_PACRK_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1491 | #define AIPS_PACRK_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1492 | #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1493 | #define AIPS_PACRK_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1494 | #define AIPS_PACRK_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1495 | #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1496 | #define AIPS_PACRK_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1497 | #define AIPS_PACRK_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1498 | #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1499 | |
AnnaBridge | 171:3a7713b1edbc | 1500 | /*! @name PACRL - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1501 | #define AIPS_PACRL_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1502 | #define AIPS_PACRL_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1503 | #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1504 | #define AIPS_PACRL_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1505 | #define AIPS_PACRL_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1506 | #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1507 | #define AIPS_PACRL_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1508 | #define AIPS_PACRL_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1509 | #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1510 | #define AIPS_PACRL_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1511 | #define AIPS_PACRL_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1512 | #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define AIPS_PACRL_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1514 | #define AIPS_PACRL_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1515 | #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1516 | #define AIPS_PACRL_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1517 | #define AIPS_PACRL_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1518 | #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define AIPS_PACRL_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1520 | #define AIPS_PACRL_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1521 | #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1522 | #define AIPS_PACRL_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1523 | #define AIPS_PACRL_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1524 | #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1525 | #define AIPS_PACRL_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1526 | #define AIPS_PACRL_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1527 | #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1528 | #define AIPS_PACRL_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1529 | #define AIPS_PACRL_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1530 | #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1531 | #define AIPS_PACRL_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1532 | #define AIPS_PACRL_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1533 | #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1534 | #define AIPS_PACRL_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1535 | #define AIPS_PACRL_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1536 | #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1537 | #define AIPS_PACRL_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1538 | #define AIPS_PACRL_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1540 | #define AIPS_PACRL_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define AIPS_PACRL_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1542 | #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1543 | #define AIPS_PACRL_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1544 | #define AIPS_PACRL_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1545 | #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1546 | #define AIPS_PACRL_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1547 | #define AIPS_PACRL_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1548 | #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1549 | #define AIPS_PACRL_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1550 | #define AIPS_PACRL_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1551 | #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1552 | #define AIPS_PACRL_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1553 | #define AIPS_PACRL_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1554 | #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1555 | #define AIPS_PACRL_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1556 | #define AIPS_PACRL_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1557 | #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1558 | #define AIPS_PACRL_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1559 | #define AIPS_PACRL_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1560 | #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1561 | #define AIPS_PACRL_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1562 | #define AIPS_PACRL_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1564 | #define AIPS_PACRL_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1565 | #define AIPS_PACRL_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1566 | #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1567 | #define AIPS_PACRL_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1568 | #define AIPS_PACRL_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1569 | #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1570 | #define AIPS_PACRL_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1571 | #define AIPS_PACRL_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1572 | #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1573 | |
AnnaBridge | 171:3a7713b1edbc | 1574 | /*! @name PACRM - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1575 | #define AIPS_PACRM_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1576 | #define AIPS_PACRM_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1577 | #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1578 | #define AIPS_PACRM_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1579 | #define AIPS_PACRM_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1580 | #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1581 | #define AIPS_PACRM_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1582 | #define AIPS_PACRM_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1584 | #define AIPS_PACRM_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1585 | #define AIPS_PACRM_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1586 | #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1587 | #define AIPS_PACRM_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1588 | #define AIPS_PACRM_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1589 | #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1590 | #define AIPS_PACRM_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1591 | #define AIPS_PACRM_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1592 | #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1593 | #define AIPS_PACRM_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1594 | #define AIPS_PACRM_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1595 | #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1596 | #define AIPS_PACRM_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1597 | #define AIPS_PACRM_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1598 | #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1599 | #define AIPS_PACRM_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1600 | #define AIPS_PACRM_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1601 | #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define AIPS_PACRM_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1603 | #define AIPS_PACRM_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1604 | #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1605 | #define AIPS_PACRM_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1606 | #define AIPS_PACRM_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1607 | #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1608 | #define AIPS_PACRM_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1609 | #define AIPS_PACRM_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1610 | #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1611 | #define AIPS_PACRM_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1612 | #define AIPS_PACRM_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1613 | #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1614 | #define AIPS_PACRM_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1615 | #define AIPS_PACRM_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1616 | #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1617 | #define AIPS_PACRM_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define AIPS_PACRM_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1619 | #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1620 | #define AIPS_PACRM_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1621 | #define AIPS_PACRM_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1622 | #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1623 | #define AIPS_PACRM_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1624 | #define AIPS_PACRM_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1625 | #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define AIPS_PACRM_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1627 | #define AIPS_PACRM_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1628 | #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1629 | #define AIPS_PACRM_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1630 | #define AIPS_PACRM_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1631 | #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1632 | #define AIPS_PACRM_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1633 | #define AIPS_PACRM_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1634 | #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1635 | #define AIPS_PACRM_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1636 | #define AIPS_PACRM_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1637 | #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1638 | #define AIPS_PACRM_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1639 | #define AIPS_PACRM_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1640 | #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1641 | #define AIPS_PACRM_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1642 | #define AIPS_PACRM_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1643 | #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1644 | #define AIPS_PACRM_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1645 | #define AIPS_PACRM_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1646 | #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1647 | |
AnnaBridge | 171:3a7713b1edbc | 1648 | /*! @name PACRN - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1649 | #define AIPS_PACRN_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1650 | #define AIPS_PACRN_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1651 | #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1652 | #define AIPS_PACRN_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1653 | #define AIPS_PACRN_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1654 | #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1655 | #define AIPS_PACRN_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1656 | #define AIPS_PACRN_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1657 | #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1658 | #define AIPS_PACRN_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1659 | #define AIPS_PACRN_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1660 | #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1661 | #define AIPS_PACRN_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1662 | #define AIPS_PACRN_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1663 | #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1664 | #define AIPS_PACRN_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1665 | #define AIPS_PACRN_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1666 | #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1667 | #define AIPS_PACRN_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1668 | #define AIPS_PACRN_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1669 | #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1670 | #define AIPS_PACRN_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1671 | #define AIPS_PACRN_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1672 | #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1673 | #define AIPS_PACRN_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1674 | #define AIPS_PACRN_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1675 | #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1676 | #define AIPS_PACRN_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1677 | #define AIPS_PACRN_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1678 | #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1679 | #define AIPS_PACRN_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1680 | #define AIPS_PACRN_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1681 | #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1682 | #define AIPS_PACRN_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1683 | #define AIPS_PACRN_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1684 | #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1685 | #define AIPS_PACRN_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1686 | #define AIPS_PACRN_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1687 | #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1688 | #define AIPS_PACRN_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1689 | #define AIPS_PACRN_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1690 | #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1691 | #define AIPS_PACRN_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1692 | #define AIPS_PACRN_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1693 | #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1694 | #define AIPS_PACRN_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1695 | #define AIPS_PACRN_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1696 | #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1697 | #define AIPS_PACRN_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1698 | #define AIPS_PACRN_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1699 | #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1700 | #define AIPS_PACRN_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1701 | #define AIPS_PACRN_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1702 | #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1703 | #define AIPS_PACRN_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1704 | #define AIPS_PACRN_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1705 | #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1706 | #define AIPS_PACRN_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1707 | #define AIPS_PACRN_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1708 | #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1709 | #define AIPS_PACRN_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1710 | #define AIPS_PACRN_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1711 | #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1712 | #define AIPS_PACRN_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1713 | #define AIPS_PACRN_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1714 | #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1715 | #define AIPS_PACRN_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1716 | #define AIPS_PACRN_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1717 | #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1718 | #define AIPS_PACRN_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1719 | #define AIPS_PACRN_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1720 | #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1721 | |
AnnaBridge | 171:3a7713b1edbc | 1722 | /*! @name PACRO - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1723 | #define AIPS_PACRO_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1724 | #define AIPS_PACRO_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1725 | #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1726 | #define AIPS_PACRO_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1727 | #define AIPS_PACRO_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1728 | #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1729 | #define AIPS_PACRO_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1730 | #define AIPS_PACRO_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1731 | #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1732 | #define AIPS_PACRO_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1733 | #define AIPS_PACRO_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1734 | #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1735 | #define AIPS_PACRO_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1736 | #define AIPS_PACRO_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1737 | #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1738 | #define AIPS_PACRO_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1739 | #define AIPS_PACRO_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1740 | #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1741 | #define AIPS_PACRO_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1742 | #define AIPS_PACRO_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1743 | #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1744 | #define AIPS_PACRO_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1745 | #define AIPS_PACRO_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1746 | #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1747 | #define AIPS_PACRO_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1748 | #define AIPS_PACRO_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1749 | #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1750 | #define AIPS_PACRO_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1751 | #define AIPS_PACRO_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1752 | #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1753 | #define AIPS_PACRO_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1754 | #define AIPS_PACRO_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1755 | #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1756 | #define AIPS_PACRO_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1757 | #define AIPS_PACRO_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1758 | #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1759 | #define AIPS_PACRO_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1760 | #define AIPS_PACRO_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1761 | #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1762 | #define AIPS_PACRO_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1763 | #define AIPS_PACRO_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1764 | #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1765 | #define AIPS_PACRO_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1766 | #define AIPS_PACRO_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1767 | #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1768 | #define AIPS_PACRO_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1769 | #define AIPS_PACRO_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1770 | #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1771 | #define AIPS_PACRO_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1772 | #define AIPS_PACRO_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1773 | #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1774 | #define AIPS_PACRO_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1775 | #define AIPS_PACRO_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1776 | #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1777 | #define AIPS_PACRO_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1778 | #define AIPS_PACRO_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1779 | #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1780 | #define AIPS_PACRO_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1781 | #define AIPS_PACRO_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1782 | #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1783 | #define AIPS_PACRO_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1784 | #define AIPS_PACRO_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1785 | #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1786 | #define AIPS_PACRO_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1787 | #define AIPS_PACRO_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1788 | #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1789 | #define AIPS_PACRO_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1790 | #define AIPS_PACRO_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1791 | #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1792 | #define AIPS_PACRO_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1793 | #define AIPS_PACRO_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1794 | #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1795 | |
AnnaBridge | 171:3a7713b1edbc | 1796 | /*! @name PACRP - Peripheral Access Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1797 | #define AIPS_PACRP_TP7_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1798 | #define AIPS_PACRP_TP7_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1799 | #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1800 | #define AIPS_PACRP_WP7_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1801 | #define AIPS_PACRP_WP7_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1802 | #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1803 | #define AIPS_PACRP_SP7_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1804 | #define AIPS_PACRP_SP7_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1805 | #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1806 | #define AIPS_PACRP_TP6_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1807 | #define AIPS_PACRP_TP6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1808 | #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1809 | #define AIPS_PACRP_WP6_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1810 | #define AIPS_PACRP_WP6_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1811 | #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1812 | #define AIPS_PACRP_SP6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1813 | #define AIPS_PACRP_SP6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1814 | #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1815 | #define AIPS_PACRP_TP5_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 1816 | #define AIPS_PACRP_TP5_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 1817 | #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1818 | #define AIPS_PACRP_WP5_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 1819 | #define AIPS_PACRP_WP5_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 1820 | #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1821 | #define AIPS_PACRP_SP5_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 1822 | #define AIPS_PACRP_SP5_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 1823 | #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1824 | #define AIPS_PACRP_TP4_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 1825 | #define AIPS_PACRP_TP4_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 1826 | #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1827 | #define AIPS_PACRP_WP4_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 1828 | #define AIPS_PACRP_WP4_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 1829 | #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1830 | #define AIPS_PACRP_SP4_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 1831 | #define AIPS_PACRP_SP4_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 1832 | #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1833 | #define AIPS_PACRP_TP3_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 1834 | #define AIPS_PACRP_TP3_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 1835 | #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1836 | #define AIPS_PACRP_WP3_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 1837 | #define AIPS_PACRP_WP3_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 1838 | #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1839 | #define AIPS_PACRP_SP3_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 1840 | #define AIPS_PACRP_SP3_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 1841 | #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1842 | #define AIPS_PACRP_TP2_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 1843 | #define AIPS_PACRP_TP2_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 1844 | #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1845 | #define AIPS_PACRP_WP2_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 1846 | #define AIPS_PACRP_WP2_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 1847 | #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1848 | #define AIPS_PACRP_SP2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 1849 | #define AIPS_PACRP_SP2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 1850 | #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1851 | #define AIPS_PACRP_TP1_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 1852 | #define AIPS_PACRP_TP1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 1853 | #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1854 | #define AIPS_PACRP_WP1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 1855 | #define AIPS_PACRP_WP1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 1856 | #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1857 | #define AIPS_PACRP_SP1_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 1858 | #define AIPS_PACRP_SP1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 1859 | #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1860 | #define AIPS_PACRP_TP0_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 1861 | #define AIPS_PACRP_TP0_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 1862 | #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1863 | #define AIPS_PACRP_WP0_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 1864 | #define AIPS_PACRP_WP0_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 1865 | #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1866 | #define AIPS_PACRP_SP0_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 1867 | #define AIPS_PACRP_SP0_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 1868 | #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1869 | |
AnnaBridge | 171:3a7713b1edbc | 1870 | |
AnnaBridge | 171:3a7713b1edbc | 1871 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1872 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1873 | */ /* end of group AIPS_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 1874 | |
AnnaBridge | 171:3a7713b1edbc | 1875 | |
AnnaBridge | 171:3a7713b1edbc | 1876 | /* AIPS - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 1877 | /** Peripheral AIPS base address */ |
AnnaBridge | 171:3a7713b1edbc | 1878 | #define AIPS_BASE (0x40000000u) |
AnnaBridge | 171:3a7713b1edbc | 1879 | /** Peripheral AIPS base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 1880 | #define AIPS ((AIPS_Type *)AIPS_BASE) |
AnnaBridge | 171:3a7713b1edbc | 1881 | /** Array initializer of AIPS peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 1882 | #define AIPS_BASE_ADDRS { AIPS_BASE } |
AnnaBridge | 171:3a7713b1edbc | 1883 | /** Array initializer of AIPS peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 1884 | #define AIPS_BASE_PTRS { AIPS } |
AnnaBridge | 171:3a7713b1edbc | 1885 | |
AnnaBridge | 171:3a7713b1edbc | 1886 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1887 | * @} |
AnnaBridge | 171:3a7713b1edbc | 1888 | */ /* end of group AIPS_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 1889 | |
AnnaBridge | 171:3a7713b1edbc | 1890 | |
AnnaBridge | 171:3a7713b1edbc | 1891 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 1892 | -- CMP Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 1893 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 1894 | |
AnnaBridge | 171:3a7713b1edbc | 1895 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1896 | * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 1897 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1898 | */ |
AnnaBridge | 171:3a7713b1edbc | 1899 | |
AnnaBridge | 171:3a7713b1edbc | 1900 | /** CMP - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 1901 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 1902 | __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 1903 | __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 1904 | __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 1905 | __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 1906 | __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 1907 | __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 1908 | } CMP_Type; |
AnnaBridge | 171:3a7713b1edbc | 1909 | |
AnnaBridge | 171:3a7713b1edbc | 1910 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 1911 | -- CMP Register Masks |
AnnaBridge | 171:3a7713b1edbc | 1912 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 1913 | |
AnnaBridge | 171:3a7713b1edbc | 1914 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1915 | * @addtogroup CMP_Register_Masks CMP Register Masks |
AnnaBridge | 171:3a7713b1edbc | 1916 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 1917 | */ |
AnnaBridge | 171:3a7713b1edbc | 1918 | |
AnnaBridge | 171:3a7713b1edbc | 1919 | /*! @name CR0 - CMP Control Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 1920 | #define CMP_CR0_HYSTCTR_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 1921 | #define CMP_CR0_HYSTCTR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1922 | #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1923 | #define CMP_CR0_FILTER_CNT_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 1924 | #define CMP_CR0_FILTER_CNT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1925 | #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1926 | |
AnnaBridge | 171:3a7713b1edbc | 1927 | /*! @name CR1 - CMP Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 1928 | #define CMP_CR1_EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1929 | #define CMP_CR1_EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1930 | #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1931 | #define CMP_CR1_OPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1932 | #define CMP_CR1_OPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1933 | #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1934 | #define CMP_CR1_COS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1935 | #define CMP_CR1_COS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1936 | #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1937 | #define CMP_CR1_INV_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 1938 | #define CMP_CR1_INV_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 1939 | #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1940 | #define CMP_CR1_PMODE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1941 | #define CMP_CR1_PMODE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1942 | #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1943 | #define CMP_CR1_TRIGM_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 1944 | #define CMP_CR1_TRIGM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 1945 | #define CMP_CR1_TRIGM(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1946 | #define CMP_CR1_WE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1947 | #define CMP_CR1_WE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1948 | #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1949 | #define CMP_CR1_SE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 1950 | #define CMP_CR1_SE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 1951 | #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1952 | |
AnnaBridge | 171:3a7713b1edbc | 1953 | /*! @name FPR - CMP Filter Period Register */ |
AnnaBridge | 171:3a7713b1edbc | 1954 | #define CMP_FPR_FILT_PER_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 1955 | #define CMP_FPR_FILT_PER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1956 | #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1957 | |
AnnaBridge | 171:3a7713b1edbc | 1958 | /*! @name SCR - CMP Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1959 | #define CMP_SCR_COUT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 1960 | #define CMP_SCR_COUT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1961 | #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1962 | #define CMP_SCR_CFF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 1963 | #define CMP_SCR_CFF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 1964 | #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1965 | #define CMP_SCR_CFR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 1966 | #define CMP_SCR_CFR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 1967 | #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1968 | #define CMP_SCR_IEF_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 1969 | #define CMP_SCR_IEF_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 1970 | #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1971 | #define CMP_SCR_IER_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 1972 | #define CMP_SCR_IER_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 1973 | #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1974 | #define CMP_SCR_DMAEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1975 | #define CMP_SCR_DMAEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1976 | #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1977 | |
AnnaBridge | 171:3a7713b1edbc | 1978 | /*! @name DACCR - DAC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1979 | #define CMP_DACCR_VOSEL_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 1980 | #define CMP_DACCR_VOSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1981 | #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1982 | #define CMP_DACCR_VRSEL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 1983 | #define CMP_DACCR_VRSEL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 1984 | #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1985 | #define CMP_DACCR_DACEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 1986 | #define CMP_DACCR_DACEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 1987 | #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1988 | |
AnnaBridge | 171:3a7713b1edbc | 1989 | /*! @name MUXCR - MUX Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 1990 | #define CMP_MUXCR_MSEL_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 1991 | #define CMP_MUXCR_MSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 1992 | #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1993 | #define CMP_MUXCR_PSEL_MASK (0x38U) |
AnnaBridge | 171:3a7713b1edbc | 1994 | #define CMP_MUXCR_PSEL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 1995 | #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 1996 | |
AnnaBridge | 171:3a7713b1edbc | 1997 | |
AnnaBridge | 171:3a7713b1edbc | 1998 | /*! |
AnnaBridge | 171:3a7713b1edbc | 1999 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2000 | */ /* end of group CMP_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2001 | |
AnnaBridge | 171:3a7713b1edbc | 2002 | |
AnnaBridge | 171:3a7713b1edbc | 2003 | /* CMP - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2004 | /** Peripheral CMP0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 2005 | #define CMP0_BASE (0x40073000u) |
AnnaBridge | 171:3a7713b1edbc | 2006 | /** Peripheral CMP0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2007 | #define CMP0 ((CMP_Type *)CMP0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2008 | /** Array initializer of CMP peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2009 | #define CMP_BASE_ADDRS { CMP0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2010 | /** Array initializer of CMP peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2011 | #define CMP_BASE_PTRS { CMP0 } |
AnnaBridge | 171:3a7713b1edbc | 2012 | /** Interrupt vectors for the CMP peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 2013 | #define CMP_IRQS { CMP0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 2014 | |
AnnaBridge | 171:3a7713b1edbc | 2015 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2016 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2017 | */ /* end of group CMP_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2018 | |
AnnaBridge | 171:3a7713b1edbc | 2019 | |
AnnaBridge | 171:3a7713b1edbc | 2020 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2021 | -- CRC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2022 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2023 | |
AnnaBridge | 171:3a7713b1edbc | 2024 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2025 | * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2026 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2027 | */ |
AnnaBridge | 171:3a7713b1edbc | 2028 | |
AnnaBridge | 171:3a7713b1edbc | 2029 | /** CRC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2030 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2031 | union { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2032 | struct { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2033 | __IO uint16_t CRCL; /**< CRC_CRCL register., offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2034 | __IO uint16_t CRCH; /**< CRC_CRCH register., offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2035 | } ACCESS16BIT; |
AnnaBridge | 171:3a7713b1edbc | 2036 | __IO uint32_t CRC; /**< CRC Data register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2037 | struct { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2038 | __IO uint8_t CRCLL; /**< CRC_CRCLL register., offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2039 | __IO uint8_t CRCLU; /**< CRC_CRCLU register., offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 2040 | __IO uint8_t CRCHL; /**< CRC_CRCHL register., offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2041 | __IO uint8_t CRCHU; /**< CRC_CRCHU register., offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 2042 | } ACCESS8BIT; |
AnnaBridge | 171:3a7713b1edbc | 2043 | }; |
AnnaBridge | 171:3a7713b1edbc | 2044 | union { /* offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2045 | struct { /* offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2046 | __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2047 | __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 2048 | } GPOLY_ACCESS16BIT; |
AnnaBridge | 171:3a7713b1edbc | 2049 | __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2050 | struct { /* offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2051 | __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2052 | __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 2053 | __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 2054 | __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 2055 | } GPOLY_ACCESS8BIT; |
AnnaBridge | 171:3a7713b1edbc | 2056 | }; |
AnnaBridge | 171:3a7713b1edbc | 2057 | union { /* offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2058 | __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2059 | struct { /* offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 2060 | uint8_t RESERVED_0[3]; |
AnnaBridge | 171:3a7713b1edbc | 2061 | __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 2062 | } CTRL_ACCESS8BIT; |
AnnaBridge | 171:3a7713b1edbc | 2063 | }; |
AnnaBridge | 171:3a7713b1edbc | 2064 | } CRC_Type; |
AnnaBridge | 171:3a7713b1edbc | 2065 | |
AnnaBridge | 171:3a7713b1edbc | 2066 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2067 | -- CRC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2068 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2069 | |
AnnaBridge | 171:3a7713b1edbc | 2070 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2071 | * @addtogroup CRC_Register_Masks CRC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2072 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2073 | */ |
AnnaBridge | 171:3a7713b1edbc | 2074 | |
AnnaBridge | 171:3a7713b1edbc | 2075 | /*! @name CRCL - CRC_CRCL register. */ |
AnnaBridge | 171:3a7713b1edbc | 2076 | #define CRC_CRCL_CRCL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2077 | #define CRC_CRCL_CRCL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2078 | #define CRC_CRCL_CRCL(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCL_CRCL_SHIFT)) & CRC_CRCL_CRCL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2079 | |
AnnaBridge | 171:3a7713b1edbc | 2080 | /*! @name CRCH - CRC_CRCH register. */ |
AnnaBridge | 171:3a7713b1edbc | 2081 | #define CRC_CRCH_CRCH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2082 | #define CRC_CRCH_CRCH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2083 | #define CRC_CRCH_CRCH(x) (((uint16_t)(((uint16_t)(x)) << CRC_CRCH_CRCH_SHIFT)) & CRC_CRCH_CRCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2084 | |
AnnaBridge | 171:3a7713b1edbc | 2085 | /*! @name CRC - CRC Data register */ |
AnnaBridge | 171:3a7713b1edbc | 2086 | #define CRC_CRC_LL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2087 | #define CRC_CRC_LL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2088 | #define CRC_CRC_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LL_SHIFT)) & CRC_CRC_LL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2089 | #define CRC_CRC_LU_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 2090 | #define CRC_CRC_LU_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2091 | #define CRC_CRC_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_LU_SHIFT)) & CRC_CRC_LU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2092 | #define CRC_CRC_HL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 2093 | #define CRC_CRC_HL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2094 | #define CRC_CRC_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HL_SHIFT)) & CRC_CRC_HL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2095 | #define CRC_CRC_HU_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 2096 | #define CRC_CRC_HU_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 2097 | #define CRC_CRC_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_CRC_HU_SHIFT)) & CRC_CRC_HU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2098 | |
AnnaBridge | 171:3a7713b1edbc | 2099 | /*! @name CRCLL - CRC_CRCLL register. */ |
AnnaBridge | 171:3a7713b1edbc | 2100 | #define CRC_CRCLL_CRCLL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2101 | #define CRC_CRCLL_CRCLL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2102 | #define CRC_CRCLL_CRCLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLL_CRCLL_SHIFT)) & CRC_CRCLL_CRCLL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2103 | |
AnnaBridge | 171:3a7713b1edbc | 2104 | /*! @name CRCLU - CRC_CRCLU register. */ |
AnnaBridge | 171:3a7713b1edbc | 2105 | #define CRC_CRCLU_CRCLU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2106 | #define CRC_CRCLU_CRCLU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2107 | #define CRC_CRCLU_CRCLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCLU_CRCLU_SHIFT)) & CRC_CRCLU_CRCLU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2108 | |
AnnaBridge | 171:3a7713b1edbc | 2109 | /*! @name CRCHL - CRC_CRCHL register. */ |
AnnaBridge | 171:3a7713b1edbc | 2110 | #define CRC_CRCHL_CRCHL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2111 | #define CRC_CRCHL_CRCHL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2112 | #define CRC_CRCHL_CRCHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHL_CRCHL_SHIFT)) & CRC_CRCHL_CRCHL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2113 | |
AnnaBridge | 171:3a7713b1edbc | 2114 | /*! @name CRCHU - CRC_CRCHU register. */ |
AnnaBridge | 171:3a7713b1edbc | 2115 | #define CRC_CRCHU_CRCHU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2116 | #define CRC_CRCHU_CRCHU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2117 | #define CRC_CRCHU_CRCHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_CRCHU_CRCHU_SHIFT)) & CRC_CRCHU_CRCHU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2118 | |
AnnaBridge | 171:3a7713b1edbc | 2119 | /*! @name GPOLYL - CRC_GPOLYL register. */ |
AnnaBridge | 171:3a7713b1edbc | 2120 | #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2121 | #define CRC_GPOLYL_GPOLYL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2122 | #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2123 | |
AnnaBridge | 171:3a7713b1edbc | 2124 | /*! @name GPOLYH - CRC_GPOLYH register. */ |
AnnaBridge | 171:3a7713b1edbc | 2125 | #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2126 | #define CRC_GPOLYH_GPOLYH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2127 | #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2128 | |
AnnaBridge | 171:3a7713b1edbc | 2129 | /*! @name GPOLY - CRC Polynomial register */ |
AnnaBridge | 171:3a7713b1edbc | 2130 | #define CRC_GPOLY_LOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2131 | #define CRC_GPOLY_LOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2132 | #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2133 | #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 2134 | #define CRC_GPOLY_HIGH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2135 | #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2136 | |
AnnaBridge | 171:3a7713b1edbc | 2137 | /*! @name GPOLYLL - CRC_GPOLYLL register. */ |
AnnaBridge | 171:3a7713b1edbc | 2138 | #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2139 | #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2140 | #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2141 | |
AnnaBridge | 171:3a7713b1edbc | 2142 | /*! @name GPOLYLU - CRC_GPOLYLU register. */ |
AnnaBridge | 171:3a7713b1edbc | 2143 | #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2144 | #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2145 | #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2146 | |
AnnaBridge | 171:3a7713b1edbc | 2147 | /*! @name GPOLYHL - CRC_GPOLYHL register. */ |
AnnaBridge | 171:3a7713b1edbc | 2148 | #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2149 | #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2150 | #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2151 | |
AnnaBridge | 171:3a7713b1edbc | 2152 | /*! @name GPOLYHU - CRC_GPOLYHU register. */ |
AnnaBridge | 171:3a7713b1edbc | 2153 | #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2154 | #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2155 | #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2156 | |
AnnaBridge | 171:3a7713b1edbc | 2157 | /*! @name CTRL - CRC Control register */ |
AnnaBridge | 171:3a7713b1edbc | 2158 | #define CRC_CTRL_TCRC_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 2159 | #define CRC_CTRL_TCRC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 2160 | #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2161 | #define CRC_CTRL_WAS_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 2162 | #define CRC_CTRL_WAS_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 2163 | #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2164 | #define CRC_CTRL_FXOR_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 2165 | #define CRC_CTRL_FXOR_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 2166 | #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2167 | #define CRC_CTRL_TOTR_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 2168 | #define CRC_CTRL_TOTR_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 2169 | #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2170 | #define CRC_CTRL_TOT_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 2171 | #define CRC_CTRL_TOT_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 2172 | #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2173 | |
AnnaBridge | 171:3a7713b1edbc | 2174 | /*! @name CTRLHU - CRC_CTRLHU register. */ |
AnnaBridge | 171:3a7713b1edbc | 2175 | #define CRC_CTRLHU_TCRC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2176 | #define CRC_CTRLHU_TCRC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2177 | #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2178 | #define CRC_CTRLHU_WAS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2179 | #define CRC_CTRLHU_WAS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2180 | #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2181 | #define CRC_CTRLHU_FXOR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2182 | #define CRC_CTRLHU_FXOR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2183 | #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2184 | #define CRC_CTRLHU_TOTR_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 2185 | #define CRC_CTRLHU_TOTR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2186 | #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2187 | #define CRC_CTRLHU_TOT_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 2188 | #define CRC_CTRLHU_TOT_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2189 | #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2190 | |
AnnaBridge | 171:3a7713b1edbc | 2191 | |
AnnaBridge | 171:3a7713b1edbc | 2192 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2193 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2194 | */ /* end of group CRC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2195 | |
AnnaBridge | 171:3a7713b1edbc | 2196 | |
AnnaBridge | 171:3a7713b1edbc | 2197 | /* CRC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2198 | /** Peripheral CRC base address */ |
AnnaBridge | 171:3a7713b1edbc | 2199 | #define CRC_BASE (0x40032000u) |
AnnaBridge | 171:3a7713b1edbc | 2200 | /** Peripheral CRC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2201 | #define CRC0 ((CRC_Type *)CRC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2202 | /** Array initializer of CRC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2203 | #define CRC_BASE_ADDRS { CRC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2204 | /** Array initializer of CRC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2205 | #define CRC_BASE_PTRS { CRC0 } |
AnnaBridge | 171:3a7713b1edbc | 2206 | |
AnnaBridge | 171:3a7713b1edbc | 2207 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2208 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2209 | */ /* end of group CRC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2210 | |
AnnaBridge | 171:3a7713b1edbc | 2211 | |
AnnaBridge | 171:3a7713b1edbc | 2212 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2213 | -- DAC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2214 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2215 | |
AnnaBridge | 171:3a7713b1edbc | 2216 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2217 | * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2218 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2219 | */ |
AnnaBridge | 171:3a7713b1edbc | 2220 | |
AnnaBridge | 171:3a7713b1edbc | 2221 | /** DAC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2222 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2223 | struct { /* offset: 0x0, array step: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2224 | __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2225 | __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 2226 | } DAT[16]; |
AnnaBridge | 171:3a7713b1edbc | 2227 | __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2228 | __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */ |
AnnaBridge | 171:3a7713b1edbc | 2229 | __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */ |
AnnaBridge | 171:3a7713b1edbc | 2230 | __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */ |
AnnaBridge | 171:3a7713b1edbc | 2231 | } DAC_Type; |
AnnaBridge | 171:3a7713b1edbc | 2232 | |
AnnaBridge | 171:3a7713b1edbc | 2233 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2234 | -- DAC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2235 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2236 | |
AnnaBridge | 171:3a7713b1edbc | 2237 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2238 | * @addtogroup DAC_Register_Masks DAC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2239 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2240 | */ |
AnnaBridge | 171:3a7713b1edbc | 2241 | |
AnnaBridge | 171:3a7713b1edbc | 2242 | /*! @name DATL - DAC Data Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 2243 | #define DAC_DATL_DATA0_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 2244 | #define DAC_DATL_DATA0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2245 | #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2246 | |
AnnaBridge | 171:3a7713b1edbc | 2247 | /* The count of DAC_DATL */ |
AnnaBridge | 171:3a7713b1edbc | 2248 | #define DAC_DATL_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2249 | |
AnnaBridge | 171:3a7713b1edbc | 2250 | /*! @name DATH - DAC Data High Register */ |
AnnaBridge | 171:3a7713b1edbc | 2251 | #define DAC_DATH_DATA1_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 2252 | #define DAC_DATH_DATA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2253 | #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2254 | |
AnnaBridge | 171:3a7713b1edbc | 2255 | /* The count of DAC_DATH */ |
AnnaBridge | 171:3a7713b1edbc | 2256 | #define DAC_DATH_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2257 | |
AnnaBridge | 171:3a7713b1edbc | 2258 | /*! @name SR - DAC Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 2259 | #define DAC_SR_DACBFRPBF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2260 | #define DAC_SR_DACBFRPBF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2261 | #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2262 | #define DAC_SR_DACBFRPTF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2263 | #define DAC_SR_DACBFRPTF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2264 | #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2265 | #define DAC_SR_DACBFWMF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2266 | #define DAC_SR_DACBFWMF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2267 | #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2268 | |
AnnaBridge | 171:3a7713b1edbc | 2269 | /*! @name C0 - DAC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2270 | #define DAC_C0_DACBBIEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2271 | #define DAC_C0_DACBBIEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2272 | #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2273 | #define DAC_C0_DACBTIEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2274 | #define DAC_C0_DACBTIEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2275 | #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2276 | #define DAC_C0_DACBWIEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2277 | #define DAC_C0_DACBWIEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2278 | #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2279 | #define DAC_C0_LPEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2280 | #define DAC_C0_LPEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2281 | #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2282 | #define DAC_C0_DACSWTRG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2283 | #define DAC_C0_DACSWTRG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2284 | #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2285 | #define DAC_C0_DACTRGSEL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2286 | #define DAC_C0_DACTRGSEL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2287 | #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2288 | #define DAC_C0_DACRFS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2289 | #define DAC_C0_DACRFS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2290 | #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2291 | #define DAC_C0_DACEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2292 | #define DAC_C0_DACEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2293 | #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2294 | |
AnnaBridge | 171:3a7713b1edbc | 2295 | /*! @name C1 - DAC Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 2296 | #define DAC_C1_DACBFEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2297 | #define DAC_C1_DACBFEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2298 | #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2299 | #define DAC_C1_DACBFMD_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 2300 | #define DAC_C1_DACBFMD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2301 | #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2302 | #define DAC_C1_DACBFWM_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 2303 | #define DAC_C1_DACBFWM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2304 | #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2305 | #define DAC_C1_DMAEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2306 | #define DAC_C1_DMAEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2307 | #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2308 | |
AnnaBridge | 171:3a7713b1edbc | 2309 | /*! @name C2 - DAC Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 2310 | #define DAC_C2_DACBFUP_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 2311 | #define DAC_C2_DACBFUP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2312 | #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2313 | #define DAC_C2_DACBFRP_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 2314 | #define DAC_C2_DACBFRP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2315 | #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2316 | |
AnnaBridge | 171:3a7713b1edbc | 2317 | |
AnnaBridge | 171:3a7713b1edbc | 2318 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2319 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2320 | */ /* end of group DAC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 2321 | |
AnnaBridge | 171:3a7713b1edbc | 2322 | |
AnnaBridge | 171:3a7713b1edbc | 2323 | /* DAC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2324 | /** Peripheral DAC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 2325 | #define DAC0_BASE (0x4003F000u) |
AnnaBridge | 171:3a7713b1edbc | 2326 | /** Peripheral DAC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 2327 | #define DAC0 ((DAC_Type *)DAC0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 2328 | /** Array initializer of DAC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 2329 | #define DAC_BASE_ADDRS { DAC0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 2330 | /** Array initializer of DAC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 2331 | #define DAC_BASE_PTRS { DAC0 } |
AnnaBridge | 171:3a7713b1edbc | 2332 | /** Interrupt vectors for the DAC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 2333 | #define DAC_IRQS { DAC0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 2334 | |
AnnaBridge | 171:3a7713b1edbc | 2335 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2336 | * @} |
AnnaBridge | 171:3a7713b1edbc | 2337 | */ /* end of group DAC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 2338 | |
AnnaBridge | 171:3a7713b1edbc | 2339 | |
AnnaBridge | 171:3a7713b1edbc | 2340 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2341 | -- DMA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2342 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2343 | |
AnnaBridge | 171:3a7713b1edbc | 2344 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2345 | * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 2346 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2347 | */ |
AnnaBridge | 171:3a7713b1edbc | 2348 | |
AnnaBridge | 171:3a7713b1edbc | 2349 | /** DMA - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 2350 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 2351 | __IO uint32_t CR; /**< Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 2352 | __I uint32_t ES; /**< Error Status Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 2353 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 2354 | __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 2355 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 2356 | __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 2357 | __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 2358 | __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */ |
AnnaBridge | 171:3a7713b1edbc | 2359 | __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */ |
AnnaBridge | 171:3a7713b1edbc | 2360 | __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */ |
AnnaBridge | 171:3a7713b1edbc | 2361 | __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 2362 | __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */ |
AnnaBridge | 171:3a7713b1edbc | 2363 | __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */ |
AnnaBridge | 171:3a7713b1edbc | 2364 | __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */ |
AnnaBridge | 171:3a7713b1edbc | 2365 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 2366 | __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 2367 | uint8_t RESERVED_3[4]; |
AnnaBridge | 171:3a7713b1edbc | 2368 | __IO uint32_t ERR; /**< Error Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 2369 | uint8_t RESERVED_4[4]; |
AnnaBridge | 171:3a7713b1edbc | 2370 | __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 2371 | uint8_t RESERVED_5[12]; |
AnnaBridge | 171:3a7713b1edbc | 2372 | __IO uint32_t EARS; /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 2373 | uint8_t RESERVED_6[184]; |
AnnaBridge | 171:3a7713b1edbc | 2374 | __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 2375 | __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */ |
AnnaBridge | 171:3a7713b1edbc | 2376 | __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */ |
AnnaBridge | 171:3a7713b1edbc | 2377 | __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */ |
AnnaBridge | 171:3a7713b1edbc | 2378 | __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 2379 | __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */ |
AnnaBridge | 171:3a7713b1edbc | 2380 | __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */ |
AnnaBridge | 171:3a7713b1edbc | 2381 | __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */ |
AnnaBridge | 171:3a7713b1edbc | 2382 | uint8_t RESERVED_7[3832]; |
AnnaBridge | 171:3a7713b1edbc | 2383 | struct { /* offset: 0x1000, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2384 | __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2385 | __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2386 | __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2387 | union { /* offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2388 | __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2389 | __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2390 | __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2391 | }; |
AnnaBridge | 171:3a7713b1edbc | 2392 | __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2393 | __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2394 | __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2395 | union { /* offset: 0x1016, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2396 | __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2397 | __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2398 | }; |
AnnaBridge | 171:3a7713b1edbc | 2399 | __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2400 | __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2401 | union { /* offset: 0x101E, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2402 | __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2403 | __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 2404 | }; |
AnnaBridge | 171:3a7713b1edbc | 2405 | } TCD[8]; |
AnnaBridge | 171:3a7713b1edbc | 2406 | } DMA_Type; |
AnnaBridge | 171:3a7713b1edbc | 2407 | |
AnnaBridge | 171:3a7713b1edbc | 2408 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 2409 | -- DMA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2410 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 2411 | |
AnnaBridge | 171:3a7713b1edbc | 2412 | /*! |
AnnaBridge | 171:3a7713b1edbc | 2413 | * @addtogroup DMA_Register_Masks DMA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 2414 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 2415 | */ |
AnnaBridge | 171:3a7713b1edbc | 2416 | |
AnnaBridge | 171:3a7713b1edbc | 2417 | /*! @name CR - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 2418 | #define DMA_CR_EDBG_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2419 | #define DMA_CR_EDBG_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2420 | #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2421 | #define DMA_CR_ERCA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2422 | #define DMA_CR_ERCA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2423 | #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2424 | #define DMA_CR_HOE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2425 | #define DMA_CR_HOE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2426 | #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2427 | #define DMA_CR_HALT_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2428 | #define DMA_CR_HALT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2429 | #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2430 | #define DMA_CR_CLM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2431 | #define DMA_CR_CLM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2432 | #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2433 | #define DMA_CR_EMLM_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2434 | #define DMA_CR_EMLM_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2435 | #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2436 | #define DMA_CR_ECX_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 2437 | #define DMA_CR_ECX_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2438 | #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2439 | #define DMA_CR_CX_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 2440 | #define DMA_CR_CX_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 2441 | #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2442 | #define DMA_CR_ACTIVE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 2443 | #define DMA_CR_ACTIVE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 2444 | #define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2445 | |
AnnaBridge | 171:3a7713b1edbc | 2446 | /*! @name ES - Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 2447 | #define DMA_ES_DBE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2448 | #define DMA_ES_DBE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2449 | #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2450 | #define DMA_ES_SBE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2451 | #define DMA_ES_SBE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2452 | #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2453 | #define DMA_ES_SGE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2454 | #define DMA_ES_SGE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2455 | #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2456 | #define DMA_ES_NCE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2457 | #define DMA_ES_NCE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2458 | #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2459 | #define DMA_ES_DOE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2460 | #define DMA_ES_DOE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2461 | #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2462 | #define DMA_ES_DAE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2463 | #define DMA_ES_DAE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2464 | #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2465 | #define DMA_ES_SOE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2466 | #define DMA_ES_SOE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2467 | #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2468 | #define DMA_ES_SAE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2469 | #define DMA_ES_SAE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2470 | #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2471 | #define DMA_ES_ERRCHN_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 2472 | #define DMA_ES_ERRCHN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2473 | #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2474 | #define DMA_ES_CPE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 2475 | #define DMA_ES_CPE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 2476 | #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2477 | #define DMA_ES_ECX_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 2478 | #define DMA_ES_ECX_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 2479 | #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2480 | #define DMA_ES_VLD_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 2481 | #define DMA_ES_VLD_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 2482 | #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2483 | |
AnnaBridge | 171:3a7713b1edbc | 2484 | /*! @name ERQ - Enable Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 2485 | #define DMA_ERQ_ERQ0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2486 | #define DMA_ERQ_ERQ0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2487 | #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2488 | #define DMA_ERQ_ERQ1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2489 | #define DMA_ERQ_ERQ1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2490 | #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2491 | #define DMA_ERQ_ERQ2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2492 | #define DMA_ERQ_ERQ2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2493 | #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2494 | #define DMA_ERQ_ERQ3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2495 | #define DMA_ERQ_ERQ3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2496 | #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2497 | #define DMA_ERQ_ERQ4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2498 | #define DMA_ERQ_ERQ4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2499 | #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2500 | #define DMA_ERQ_ERQ5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2501 | #define DMA_ERQ_ERQ5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2502 | #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2503 | #define DMA_ERQ_ERQ6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2504 | #define DMA_ERQ_ERQ6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2505 | #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2506 | #define DMA_ERQ_ERQ7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2507 | #define DMA_ERQ_ERQ7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2508 | #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2509 | |
AnnaBridge | 171:3a7713b1edbc | 2510 | /*! @name EEI - Enable Error Interrupt Register */ |
AnnaBridge | 171:3a7713b1edbc | 2511 | #define DMA_EEI_EEI0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2512 | #define DMA_EEI_EEI0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2513 | #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2514 | #define DMA_EEI_EEI1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2515 | #define DMA_EEI_EEI1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2516 | #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2517 | #define DMA_EEI_EEI2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2518 | #define DMA_EEI_EEI2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2519 | #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2520 | #define DMA_EEI_EEI3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2521 | #define DMA_EEI_EEI3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2522 | #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2523 | #define DMA_EEI_EEI4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2524 | #define DMA_EEI_EEI4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2525 | #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2526 | #define DMA_EEI_EEI5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2527 | #define DMA_EEI_EEI5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2528 | #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2529 | #define DMA_EEI_EEI6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2530 | #define DMA_EEI_EEI6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2531 | #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2532 | #define DMA_EEI_EEI7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2533 | #define DMA_EEI_EEI7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2534 | #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2535 | |
AnnaBridge | 171:3a7713b1edbc | 2536 | /*! @name CEEI - Clear Enable Error Interrupt Register */ |
AnnaBridge | 171:3a7713b1edbc | 2537 | #define DMA_CEEI_CEEI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2538 | #define DMA_CEEI_CEEI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2539 | #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2540 | #define DMA_CEEI_CAEE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2541 | #define DMA_CEEI_CAEE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2542 | #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2543 | #define DMA_CEEI_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2544 | #define DMA_CEEI_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2545 | #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2546 | |
AnnaBridge | 171:3a7713b1edbc | 2547 | /*! @name SEEI - Set Enable Error Interrupt Register */ |
AnnaBridge | 171:3a7713b1edbc | 2548 | #define DMA_SEEI_SEEI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2549 | #define DMA_SEEI_SEEI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2550 | #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2551 | #define DMA_SEEI_SAEE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2552 | #define DMA_SEEI_SAEE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2553 | #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2554 | #define DMA_SEEI_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2555 | #define DMA_SEEI_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2556 | #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2557 | |
AnnaBridge | 171:3a7713b1edbc | 2558 | /*! @name CERQ - Clear Enable Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 2559 | #define DMA_CERQ_CERQ_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2560 | #define DMA_CERQ_CERQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2561 | #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2562 | #define DMA_CERQ_CAER_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2563 | #define DMA_CERQ_CAER_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2564 | #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2565 | #define DMA_CERQ_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2566 | #define DMA_CERQ_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2567 | #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2568 | |
AnnaBridge | 171:3a7713b1edbc | 2569 | /*! @name SERQ - Set Enable Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 2570 | #define DMA_SERQ_SERQ_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2571 | #define DMA_SERQ_SERQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2572 | #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2573 | #define DMA_SERQ_SAER_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2574 | #define DMA_SERQ_SAER_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2575 | #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2576 | #define DMA_SERQ_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2577 | #define DMA_SERQ_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2578 | #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2579 | |
AnnaBridge | 171:3a7713b1edbc | 2580 | /*! @name CDNE - Clear DONE Status Bit Register */ |
AnnaBridge | 171:3a7713b1edbc | 2581 | #define DMA_CDNE_CDNE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2582 | #define DMA_CDNE_CDNE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2583 | #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2584 | #define DMA_CDNE_CADN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2585 | #define DMA_CDNE_CADN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2586 | #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2587 | #define DMA_CDNE_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2588 | #define DMA_CDNE_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2589 | #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2590 | |
AnnaBridge | 171:3a7713b1edbc | 2591 | /*! @name SSRT - Set START Bit Register */ |
AnnaBridge | 171:3a7713b1edbc | 2592 | #define DMA_SSRT_SSRT_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2593 | #define DMA_SSRT_SSRT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2594 | #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2595 | #define DMA_SSRT_SAST_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2596 | #define DMA_SSRT_SAST_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2597 | #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2598 | #define DMA_SSRT_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2599 | #define DMA_SSRT_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2600 | #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2601 | |
AnnaBridge | 171:3a7713b1edbc | 2602 | /*! @name CERR - Clear Error Register */ |
AnnaBridge | 171:3a7713b1edbc | 2603 | #define DMA_CERR_CERR_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2604 | #define DMA_CERR_CERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2605 | #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2606 | #define DMA_CERR_CAEI_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2607 | #define DMA_CERR_CAEI_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2608 | #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2609 | #define DMA_CERR_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2610 | #define DMA_CERR_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2611 | #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2612 | |
AnnaBridge | 171:3a7713b1edbc | 2613 | /*! @name CINT - Clear Interrupt Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 2614 | #define DMA_CINT_CINT_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2615 | #define DMA_CINT_CINT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2616 | #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2617 | #define DMA_CINT_CAIR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2618 | #define DMA_CINT_CAIR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2619 | #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2620 | #define DMA_CINT_NOP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2621 | #define DMA_CINT_NOP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2622 | #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2623 | |
AnnaBridge | 171:3a7713b1edbc | 2624 | /*! @name INT - Interrupt Request Register */ |
AnnaBridge | 171:3a7713b1edbc | 2625 | #define DMA_INT_INT0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2626 | #define DMA_INT_INT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2627 | #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2628 | #define DMA_INT_INT1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2629 | #define DMA_INT_INT1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2630 | #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2631 | #define DMA_INT_INT2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2632 | #define DMA_INT_INT2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2633 | #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2634 | #define DMA_INT_INT3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2635 | #define DMA_INT_INT3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2636 | #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2637 | #define DMA_INT_INT4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2638 | #define DMA_INT_INT4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2639 | #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2640 | #define DMA_INT_INT5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2641 | #define DMA_INT_INT5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2642 | #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2643 | #define DMA_INT_INT6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2644 | #define DMA_INT_INT6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2645 | #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2646 | #define DMA_INT_INT7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2647 | #define DMA_INT_INT7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2648 | #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2649 | |
AnnaBridge | 171:3a7713b1edbc | 2650 | /*! @name ERR - Error Register */ |
AnnaBridge | 171:3a7713b1edbc | 2651 | #define DMA_ERR_ERR0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2652 | #define DMA_ERR_ERR0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2653 | #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2654 | #define DMA_ERR_ERR1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2655 | #define DMA_ERR_ERR1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2656 | #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2657 | #define DMA_ERR_ERR2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2658 | #define DMA_ERR_ERR2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2659 | #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2660 | #define DMA_ERR_ERR3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2661 | #define DMA_ERR_ERR3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2662 | #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2663 | #define DMA_ERR_ERR4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2664 | #define DMA_ERR_ERR4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2665 | #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2666 | #define DMA_ERR_ERR5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2667 | #define DMA_ERR_ERR5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2668 | #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2669 | #define DMA_ERR_ERR6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2670 | #define DMA_ERR_ERR6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2671 | #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2672 | #define DMA_ERR_ERR7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2673 | #define DMA_ERR_ERR7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2674 | #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2675 | |
AnnaBridge | 171:3a7713b1edbc | 2676 | /*! @name HRS - Hardware Request Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 2677 | #define DMA_HRS_HRS0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2678 | #define DMA_HRS_HRS0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2679 | #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2680 | #define DMA_HRS_HRS1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2681 | #define DMA_HRS_HRS1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2682 | #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2683 | #define DMA_HRS_HRS2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2684 | #define DMA_HRS_HRS2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2685 | #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2686 | #define DMA_HRS_HRS3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2687 | #define DMA_HRS_HRS3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2688 | #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2689 | #define DMA_HRS_HRS4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2690 | #define DMA_HRS_HRS4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2691 | #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2692 | #define DMA_HRS_HRS5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2693 | #define DMA_HRS_HRS5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2694 | #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2695 | #define DMA_HRS_HRS6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2696 | #define DMA_HRS_HRS6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2697 | #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2698 | #define DMA_HRS_HRS7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2699 | #define DMA_HRS_HRS7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2700 | #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2701 | |
AnnaBridge | 171:3a7713b1edbc | 2702 | /*! @name EARS - Enable Asynchronous Request in Stop Register */ |
AnnaBridge | 171:3a7713b1edbc | 2703 | #define DMA_EARS_EDREQ_0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2704 | #define DMA_EARS_EDREQ_0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2705 | #define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2706 | #define DMA_EARS_EDREQ_1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2707 | #define DMA_EARS_EDREQ_1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2708 | #define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2709 | #define DMA_EARS_EDREQ_2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2710 | #define DMA_EARS_EDREQ_2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2711 | #define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2712 | #define DMA_EARS_EDREQ_3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2713 | #define DMA_EARS_EDREQ_3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2714 | #define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2715 | #define DMA_EARS_EDREQ_4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2716 | #define DMA_EARS_EDREQ_4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2717 | #define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2718 | #define DMA_EARS_EDREQ_5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2719 | #define DMA_EARS_EDREQ_5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2720 | #define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2721 | #define DMA_EARS_EDREQ_6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2722 | #define DMA_EARS_EDREQ_6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2723 | #define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2724 | #define DMA_EARS_EDREQ_7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2725 | #define DMA_EARS_EDREQ_7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2726 | #define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2727 | |
AnnaBridge | 171:3a7713b1edbc | 2728 | /*! @name DCHPRI3 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2729 | #define DMA_DCHPRI3_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2730 | #define DMA_DCHPRI3_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2731 | #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2732 | #define DMA_DCHPRI3_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2733 | #define DMA_DCHPRI3_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2734 | #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2735 | #define DMA_DCHPRI3_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2736 | #define DMA_DCHPRI3_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2737 | #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2738 | |
AnnaBridge | 171:3a7713b1edbc | 2739 | /*! @name DCHPRI2 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2740 | #define DMA_DCHPRI2_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2741 | #define DMA_DCHPRI2_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2742 | #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2743 | #define DMA_DCHPRI2_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2744 | #define DMA_DCHPRI2_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2745 | #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2746 | #define DMA_DCHPRI2_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2747 | #define DMA_DCHPRI2_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2748 | #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2749 | |
AnnaBridge | 171:3a7713b1edbc | 2750 | /*! @name DCHPRI1 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2751 | #define DMA_DCHPRI1_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2752 | #define DMA_DCHPRI1_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2753 | #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2754 | #define DMA_DCHPRI1_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2755 | #define DMA_DCHPRI1_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2756 | #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2757 | #define DMA_DCHPRI1_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2758 | #define DMA_DCHPRI1_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2759 | #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2760 | |
AnnaBridge | 171:3a7713b1edbc | 2761 | /*! @name DCHPRI0 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2762 | #define DMA_DCHPRI0_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2763 | #define DMA_DCHPRI0_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2764 | #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2765 | #define DMA_DCHPRI0_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2766 | #define DMA_DCHPRI0_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2767 | #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2768 | #define DMA_DCHPRI0_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2769 | #define DMA_DCHPRI0_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2770 | #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2771 | |
AnnaBridge | 171:3a7713b1edbc | 2772 | /*! @name DCHPRI7 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2773 | #define DMA_DCHPRI7_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2774 | #define DMA_DCHPRI7_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2775 | #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2776 | #define DMA_DCHPRI7_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2777 | #define DMA_DCHPRI7_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2778 | #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2779 | #define DMA_DCHPRI7_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2780 | #define DMA_DCHPRI7_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2781 | #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2782 | |
AnnaBridge | 171:3a7713b1edbc | 2783 | /*! @name DCHPRI6 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2784 | #define DMA_DCHPRI6_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2785 | #define DMA_DCHPRI6_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2786 | #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2787 | #define DMA_DCHPRI6_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2788 | #define DMA_DCHPRI6_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2789 | #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2790 | #define DMA_DCHPRI6_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2791 | #define DMA_DCHPRI6_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2792 | #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2793 | |
AnnaBridge | 171:3a7713b1edbc | 2794 | /*! @name DCHPRI5 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2795 | #define DMA_DCHPRI5_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2796 | #define DMA_DCHPRI5_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2797 | #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2798 | #define DMA_DCHPRI5_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2799 | #define DMA_DCHPRI5_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2800 | #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2801 | #define DMA_DCHPRI5_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2802 | #define DMA_DCHPRI5_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2803 | #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2804 | |
AnnaBridge | 171:3a7713b1edbc | 2805 | /*! @name DCHPRI4 - Channel n Priority Register */ |
AnnaBridge | 171:3a7713b1edbc | 2806 | #define DMA_DCHPRI4_CHPRI_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2807 | #define DMA_DCHPRI4_CHPRI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2808 | #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2809 | #define DMA_DCHPRI4_DPA_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2810 | #define DMA_DCHPRI4_DPA_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2811 | #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2812 | #define DMA_DCHPRI4_ECP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2813 | #define DMA_DCHPRI4_ECP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2814 | #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2815 | |
AnnaBridge | 171:3a7713b1edbc | 2816 | /*! @name SADDR - TCD Source Address */ |
AnnaBridge | 171:3a7713b1edbc | 2817 | #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2818 | #define DMA_SADDR_SADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2819 | #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2820 | |
AnnaBridge | 171:3a7713b1edbc | 2821 | /* The count of DMA_SADDR */ |
AnnaBridge | 171:3a7713b1edbc | 2822 | #define DMA_SADDR_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2823 | |
AnnaBridge | 171:3a7713b1edbc | 2824 | /*! @name SOFF - TCD Signed Source Address Offset */ |
AnnaBridge | 171:3a7713b1edbc | 2825 | #define DMA_SOFF_SOFF_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2826 | #define DMA_SOFF_SOFF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2827 | #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2828 | |
AnnaBridge | 171:3a7713b1edbc | 2829 | /* The count of DMA_SOFF */ |
AnnaBridge | 171:3a7713b1edbc | 2830 | #define DMA_SOFF_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2831 | |
AnnaBridge | 171:3a7713b1edbc | 2832 | /*! @name ATTR - TCD Transfer Attributes */ |
AnnaBridge | 171:3a7713b1edbc | 2833 | #define DMA_ATTR_DSIZE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 2834 | #define DMA_ATTR_DSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2835 | #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2836 | #define DMA_ATTR_DMOD_MASK (0xF8U) |
AnnaBridge | 171:3a7713b1edbc | 2837 | #define DMA_ATTR_DMOD_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2838 | #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2839 | #define DMA_ATTR_SSIZE_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 2840 | #define DMA_ATTR_SSIZE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2841 | #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2842 | #define DMA_ATTR_SMOD_MASK (0xF800U) |
AnnaBridge | 171:3a7713b1edbc | 2843 | #define DMA_ATTR_SMOD_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 2844 | #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2845 | |
AnnaBridge | 171:3a7713b1edbc | 2846 | /* The count of DMA_ATTR */ |
AnnaBridge | 171:3a7713b1edbc | 2847 | #define DMA_ATTR_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2848 | |
AnnaBridge | 171:3a7713b1edbc | 2849 | /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2850 | #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2851 | #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2852 | #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2853 | |
AnnaBridge | 171:3a7713b1edbc | 2854 | /* The count of DMA_NBYTES_MLNO */ |
AnnaBridge | 171:3a7713b1edbc | 2855 | #define DMA_NBYTES_MLNO_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2856 | |
AnnaBridge | 171:3a7713b1edbc | 2857 | /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2858 | #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2859 | #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2860 | #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2861 | #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 2862 | #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 2863 | #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2864 | #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 2865 | #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 2866 | #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2867 | |
AnnaBridge | 171:3a7713b1edbc | 2868 | /* The count of DMA_NBYTES_MLOFFNO */ |
AnnaBridge | 171:3a7713b1edbc | 2869 | #define DMA_NBYTES_MLOFFNO_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2870 | |
AnnaBridge | 171:3a7713b1edbc | 2871 | /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2872 | #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 2873 | #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2874 | #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2875 | #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 2876 | #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 2877 | #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2878 | #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 2879 | #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 2880 | #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2881 | #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 2882 | #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 2883 | #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2884 | |
AnnaBridge | 171:3a7713b1edbc | 2885 | /* The count of DMA_NBYTES_MLOFFYES */ |
AnnaBridge | 171:3a7713b1edbc | 2886 | #define DMA_NBYTES_MLOFFYES_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2887 | |
AnnaBridge | 171:3a7713b1edbc | 2888 | /*! @name SLAST - TCD Last Source Address Adjustment */ |
AnnaBridge | 171:3a7713b1edbc | 2889 | #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2890 | #define DMA_SLAST_SLAST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2891 | #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2892 | |
AnnaBridge | 171:3a7713b1edbc | 2893 | /* The count of DMA_SLAST */ |
AnnaBridge | 171:3a7713b1edbc | 2894 | #define DMA_SLAST_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2895 | |
AnnaBridge | 171:3a7713b1edbc | 2896 | /*! @name DADDR - TCD Destination Address */ |
AnnaBridge | 171:3a7713b1edbc | 2897 | #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2898 | #define DMA_DADDR_DADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2899 | #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2900 | |
AnnaBridge | 171:3a7713b1edbc | 2901 | /* The count of DMA_DADDR */ |
AnnaBridge | 171:3a7713b1edbc | 2902 | #define DMA_DADDR_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2903 | |
AnnaBridge | 171:3a7713b1edbc | 2904 | /*! @name DOFF - TCD Signed Destination Address Offset */ |
AnnaBridge | 171:3a7713b1edbc | 2905 | #define DMA_DOFF_DOFF_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2906 | #define DMA_DOFF_DOFF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2907 | #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2908 | |
AnnaBridge | 171:3a7713b1edbc | 2909 | /* The count of DMA_DOFF */ |
AnnaBridge | 171:3a7713b1edbc | 2910 | #define DMA_DOFF_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2911 | |
AnnaBridge | 171:3a7713b1edbc | 2912 | /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2913 | #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 2914 | #define DMA_CITER_ELINKNO_CITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2915 | #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2916 | #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 2917 | #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 2918 | #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2919 | |
AnnaBridge | 171:3a7713b1edbc | 2920 | /* The count of DMA_CITER_ELINKNO */ |
AnnaBridge | 171:3a7713b1edbc | 2921 | #define DMA_CITER_ELINKNO_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2922 | |
AnnaBridge | 171:3a7713b1edbc | 2923 | /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2924 | #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 2925 | #define DMA_CITER_ELINKYES_CITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2926 | #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2927 | #define DMA_CITER_ELINKYES_LINKCH_MASK (0xE00U) |
AnnaBridge | 171:3a7713b1edbc | 2928 | #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2929 | #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2930 | #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 2931 | #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 2932 | #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2933 | |
AnnaBridge | 171:3a7713b1edbc | 2934 | /* The count of DMA_CITER_ELINKYES */ |
AnnaBridge | 171:3a7713b1edbc | 2935 | #define DMA_CITER_ELINKYES_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2936 | |
AnnaBridge | 171:3a7713b1edbc | 2937 | /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */ |
AnnaBridge | 171:3a7713b1edbc | 2938 | #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 2939 | #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2940 | #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2941 | |
AnnaBridge | 171:3a7713b1edbc | 2942 | /* The count of DMA_DLAST_SGA */ |
AnnaBridge | 171:3a7713b1edbc | 2943 | #define DMA_DLAST_SGA_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2944 | |
AnnaBridge | 171:3a7713b1edbc | 2945 | /*! @name CSR - TCD Control and Status */ |
AnnaBridge | 171:3a7713b1edbc | 2946 | #define DMA_CSR_START_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 2947 | #define DMA_CSR_START_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2948 | #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2949 | #define DMA_CSR_INTMAJOR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 2950 | #define DMA_CSR_INTMAJOR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 2951 | #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2952 | #define DMA_CSR_INTHALF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 2953 | #define DMA_CSR_INTHALF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 2954 | #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2955 | #define DMA_CSR_DREQ_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 2956 | #define DMA_CSR_DREQ_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 2957 | #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2958 | #define DMA_CSR_ESG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 2959 | #define DMA_CSR_ESG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 2960 | #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2961 | #define DMA_CSR_MAJORELINK_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 2962 | #define DMA_CSR_MAJORELINK_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 2963 | #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2964 | #define DMA_CSR_ACTIVE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 2965 | #define DMA_CSR_ACTIVE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 2966 | #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2967 | #define DMA_CSR_DONE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 2968 | #define DMA_CSR_DONE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 2969 | #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2970 | #define DMA_CSR_MAJORLINKCH_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 2971 | #define DMA_CSR_MAJORLINKCH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2972 | #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2973 | #define DMA_CSR_BWC_MASK (0xC000U) |
AnnaBridge | 171:3a7713b1edbc | 2974 | #define DMA_CSR_BWC_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 2975 | #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2976 | |
AnnaBridge | 171:3a7713b1edbc | 2977 | /* The count of DMA_CSR */ |
AnnaBridge | 171:3a7713b1edbc | 2978 | #define DMA_CSR_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2979 | |
AnnaBridge | 171:3a7713b1edbc | 2980 | /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2981 | #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 2982 | #define DMA_BITER_ELINKNO_BITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2983 | #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2984 | #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 2985 | #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 2986 | #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2987 | |
AnnaBridge | 171:3a7713b1edbc | 2988 | /* The count of DMA_BITER_ELINKNO */ |
AnnaBridge | 171:3a7713b1edbc | 2989 | #define DMA_BITER_ELINKNO_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 2990 | |
AnnaBridge | 171:3a7713b1edbc | 2991 | /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ |
AnnaBridge | 171:3a7713b1edbc | 2992 | #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 2993 | #define DMA_BITER_ELINKYES_BITER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 2994 | #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2995 | #define DMA_BITER_ELINKYES_LINKCH_MASK (0xE00U) |
AnnaBridge | 171:3a7713b1edbc | 2996 | #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 2997 | #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 2998 | #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 2999 | #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3000 | #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3001 | |
AnnaBridge | 171:3a7713b1edbc | 3002 | /* The count of DMA_BITER_ELINKYES */ |
AnnaBridge | 171:3a7713b1edbc | 3003 | #define DMA_BITER_ELINKYES_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3004 | |
AnnaBridge | 171:3a7713b1edbc | 3005 | |
AnnaBridge | 171:3a7713b1edbc | 3006 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3007 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3008 | */ /* end of group DMA_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3009 | |
AnnaBridge | 171:3a7713b1edbc | 3010 | |
AnnaBridge | 171:3a7713b1edbc | 3011 | /* DMA - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3012 | /** Peripheral DMA base address */ |
AnnaBridge | 171:3a7713b1edbc | 3013 | #define DMA_BASE (0x40008000u) |
AnnaBridge | 171:3a7713b1edbc | 3014 | /** Peripheral DMA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3015 | #define DMA0 ((DMA_Type *)DMA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3016 | /** Array initializer of DMA peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3017 | #define DMA_BASE_ADDRS { DMA_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3018 | /** Array initializer of DMA peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3019 | #define DMA_BASE_PTRS { DMA0 } |
AnnaBridge | 171:3a7713b1edbc | 3020 | /** Interrupt vectors for the DMA peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 3021 | #define DMA_CHN_IRQS { DMA0_DMA4_IRQn, DMA1_DMA5_IRQn, DMA2_DMA6_IRQn, DMA3_DMA7_IRQn, DMA0_DMA4_IRQn, DMA1_DMA5_IRQn, DMA2_DMA6_IRQn, DMA3_DMA7_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 3022 | #define DMA_ERROR_IRQS { DMA_Error_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 3023 | |
AnnaBridge | 171:3a7713b1edbc | 3024 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3025 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3026 | */ /* end of group DMA_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3027 | |
AnnaBridge | 171:3a7713b1edbc | 3028 | |
AnnaBridge | 171:3a7713b1edbc | 3029 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3030 | -- DMAMUX Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3031 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3032 | |
AnnaBridge | 171:3a7713b1edbc | 3033 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3034 | * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3035 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3036 | */ |
AnnaBridge | 171:3a7713b1edbc | 3037 | |
AnnaBridge | 171:3a7713b1edbc | 3038 | /** DMAMUX - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3039 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3040 | __IO uint8_t CHCFG[8]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 3041 | } DMAMUX_Type; |
AnnaBridge | 171:3a7713b1edbc | 3042 | |
AnnaBridge | 171:3a7713b1edbc | 3043 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3044 | -- DMAMUX Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3045 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3046 | |
AnnaBridge | 171:3a7713b1edbc | 3047 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3048 | * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3049 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3050 | */ |
AnnaBridge | 171:3a7713b1edbc | 3051 | |
AnnaBridge | 171:3a7713b1edbc | 3052 | /*! @name CHCFG - Channel Configuration register */ |
AnnaBridge | 171:3a7713b1edbc | 3053 | #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 3054 | #define DMAMUX_CHCFG_SOURCE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3055 | #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3056 | #define DMAMUX_CHCFG_TRIG_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3057 | #define DMAMUX_CHCFG_TRIG_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3058 | #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3059 | #define DMAMUX_CHCFG_ENBL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3060 | #define DMAMUX_CHCFG_ENBL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3061 | #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3062 | |
AnnaBridge | 171:3a7713b1edbc | 3063 | /* The count of DMAMUX_CHCFG */ |
AnnaBridge | 171:3a7713b1edbc | 3064 | #define DMAMUX_CHCFG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3065 | |
AnnaBridge | 171:3a7713b1edbc | 3066 | |
AnnaBridge | 171:3a7713b1edbc | 3067 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3068 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3069 | */ /* end of group DMAMUX_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3070 | |
AnnaBridge | 171:3a7713b1edbc | 3071 | |
AnnaBridge | 171:3a7713b1edbc | 3072 | /* DMAMUX - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3073 | /** Peripheral DMAMUX base address */ |
AnnaBridge | 171:3a7713b1edbc | 3074 | #define DMAMUX_BASE (0x40021000u) |
AnnaBridge | 171:3a7713b1edbc | 3075 | /** Peripheral DMAMUX base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3076 | #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3077 | /** Array initializer of DMAMUX peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3078 | #define DMAMUX_BASE_ADDRS { DMAMUX_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3079 | /** Array initializer of DMAMUX peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3080 | #define DMAMUX_BASE_PTRS { DMAMUX } |
AnnaBridge | 171:3a7713b1edbc | 3081 | |
AnnaBridge | 171:3a7713b1edbc | 3082 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3083 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3084 | */ /* end of group DMAMUX_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3085 | |
AnnaBridge | 171:3a7713b1edbc | 3086 | |
AnnaBridge | 171:3a7713b1edbc | 3087 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3088 | -- EMVSIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3089 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3090 | |
AnnaBridge | 171:3a7713b1edbc | 3091 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3092 | * @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3093 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3094 | */ |
AnnaBridge | 171:3a7713b1edbc | 3095 | |
AnnaBridge | 171:3a7713b1edbc | 3096 | /** EMVSIM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3097 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3098 | __I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 3099 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3100 | __IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 3101 | __IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 3102 | __IO uint32_t CTRL; /**< Control Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 3103 | __IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 3104 | __IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 3105 | __IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 3106 | __IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3107 | __IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 3108 | __IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 3109 | __I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 3110 | __IO uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 3111 | __IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 3112 | __IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 3113 | __IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 3114 | __IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 3115 | __IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 3116 | __IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 3117 | } EMVSIM_Type; |
AnnaBridge | 171:3a7713b1edbc | 3118 | |
AnnaBridge | 171:3a7713b1edbc | 3119 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3120 | -- EMVSIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3121 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3122 | |
AnnaBridge | 171:3a7713b1edbc | 3123 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3124 | * @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3125 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3126 | */ |
AnnaBridge | 171:3a7713b1edbc | 3127 | |
AnnaBridge | 171:3a7713b1edbc | 3128 | /*! @name VER_ID - Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 3129 | #define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3130 | #define EMVSIM_VER_ID_VER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3131 | #define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3132 | |
AnnaBridge | 171:3a7713b1edbc | 3133 | /*! @name PARAM - Parameter Register */ |
AnnaBridge | 171:3a7713b1edbc | 3134 | #define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3135 | #define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3136 | #define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3137 | #define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 3138 | #define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3139 | #define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3140 | |
AnnaBridge | 171:3a7713b1edbc | 3141 | /*! @name CLKCFG - Clock Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 3142 | #define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3143 | #define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3144 | #define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3145 | #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 3146 | #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3147 | #define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3148 | #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 3149 | #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3150 | #define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3151 | |
AnnaBridge | 171:3a7713b1edbc | 3152 | /*! @name DIVISOR - Baud Rate Divisor Register */ |
AnnaBridge | 171:3a7713b1edbc | 3153 | #define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 3154 | #define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3155 | #define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3156 | |
AnnaBridge | 171:3a7713b1edbc | 3157 | /*! @name CTRL - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 3158 | #define EMVSIM_CTRL_IC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3159 | #define EMVSIM_CTRL_IC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3160 | #define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3161 | #define EMVSIM_CTRL_ICM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3162 | #define EMVSIM_CTRL_ICM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3163 | #define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3164 | #define EMVSIM_CTRL_ANACK_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3165 | #define EMVSIM_CTRL_ANACK_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3166 | #define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3167 | #define EMVSIM_CTRL_ONACK_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3168 | #define EMVSIM_CTRL_ONACK_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3169 | #define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3170 | #define EMVSIM_CTRL_FLSH_RX_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3171 | #define EMVSIM_CTRL_FLSH_RX_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3172 | #define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3173 | #define EMVSIM_CTRL_FLSH_TX_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3174 | #define EMVSIM_CTRL_FLSH_TX_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3175 | #define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3176 | #define EMVSIM_CTRL_SW_RST_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3177 | #define EMVSIM_CTRL_SW_RST_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3178 | #define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3179 | #define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3180 | #define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3181 | #define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3182 | #define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3183 | #define EMVSIM_CTRL_DOZE_EN_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3184 | #define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3185 | #define EMVSIM_CTRL_STOP_EN_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3186 | #define EMVSIM_CTRL_STOP_EN_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3187 | #define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3188 | #define EMVSIM_CTRL_RCV_EN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 3189 | #define EMVSIM_CTRL_RCV_EN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3190 | #define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3191 | #define EMVSIM_CTRL_XMT_EN_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 3192 | #define EMVSIM_CTRL_XMT_EN_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 3193 | #define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3194 | #define EMVSIM_CTRL_RCVR_11_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 3195 | #define EMVSIM_CTRL_RCVR_11_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 3196 | #define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3197 | #define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 3198 | #define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 3199 | #define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3200 | #define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 3201 | #define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3202 | #define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3203 | #define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3204 | #define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3205 | #define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3206 | #define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3207 | #define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3208 | #define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3209 | #define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3210 | #define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3211 | #define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3212 | #define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 3213 | #define EMVSIM_CTRL_CWT_EN_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 3214 | #define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3215 | #define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 3216 | #define EMVSIM_CTRL_LRC_EN_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 3217 | #define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3218 | #define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 3219 | #define EMVSIM_CTRL_CRC_EN_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 3220 | #define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3221 | #define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 3222 | #define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3223 | #define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3224 | #define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3225 | #define EMVSIM_CTRL_BWT_EN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3226 | #define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3227 | |
AnnaBridge | 171:3a7713b1edbc | 3228 | /*! @name INT_MASK - Interrupt Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 3229 | #define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3230 | #define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3231 | #define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3232 | #define EMVSIM_INT_MASK_TC_IM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3233 | #define EMVSIM_INT_MASK_TC_IM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3234 | #define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3235 | #define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3236 | #define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3237 | #define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3238 | #define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3239 | #define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3240 | #define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3241 | #define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3242 | #define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3243 | #define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3244 | #define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3245 | #define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3246 | #define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3247 | #define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3248 | #define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3249 | #define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3250 | #define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3251 | #define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3252 | #define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3253 | #define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3254 | #define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3255 | #define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3256 | #define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3257 | #define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3258 | #define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3259 | #define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3260 | #define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3261 | #define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3262 | #define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3263 | #define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3264 | #define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3265 | #define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3266 | #define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3267 | #define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3268 | #define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3269 | #define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3270 | #define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3271 | #define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 3272 | #define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 3273 | #define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3274 | #define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 3275 | #define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 3276 | #define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3277 | |
AnnaBridge | 171:3a7713b1edbc | 3278 | /*! @name RX_THD - Receiver Threshold Register */ |
AnnaBridge | 171:3a7713b1edbc | 3279 | #define EMVSIM_RX_THD_RDT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 3280 | #define EMVSIM_RX_THD_RDT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3281 | #define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3282 | #define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 3283 | #define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3284 | #define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3285 | |
AnnaBridge | 171:3a7713b1edbc | 3286 | /*! @name TX_THD - Transmitter Threshold Register */ |
AnnaBridge | 171:3a7713b1edbc | 3287 | #define EMVSIM_TX_THD_TDT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 3288 | #define EMVSIM_TX_THD_TDT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3289 | #define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3290 | #define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 3291 | #define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3292 | #define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3293 | |
AnnaBridge | 171:3a7713b1edbc | 3294 | /*! @name RX_STATUS - Receive Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3295 | #define EMVSIM_RX_STATUS_RFO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3296 | #define EMVSIM_RX_STATUS_RFO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3297 | #define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3298 | #define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3299 | #define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3300 | #define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3301 | #define EMVSIM_RX_STATUS_RDTF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3302 | #define EMVSIM_RX_STATUS_RDTF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3303 | #define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3304 | #define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3305 | #define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3306 | #define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3307 | #define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3308 | #define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3309 | #define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3310 | #define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3311 | #define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3312 | #define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3313 | #define EMVSIM_RX_STATUS_RTE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3314 | #define EMVSIM_RX_STATUS_RTE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3315 | #define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3316 | #define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 3317 | #define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 3318 | #define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3319 | #define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 3320 | #define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 3321 | #define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3322 | #define EMVSIM_RX_STATUS_PEF_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 3323 | #define EMVSIM_RX_STATUS_PEF_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3324 | #define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3325 | #define EMVSIM_RX_STATUS_FEF_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 3326 | #define EMVSIM_RX_STATUS_FEF_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 3327 | #define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3328 | #define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 3329 | #define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3330 | #define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3331 | #define EMVSIM_RX_STATUS_RX_CNT_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 3332 | #define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3333 | #define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3334 | |
AnnaBridge | 171:3a7713b1edbc | 3335 | /*! @name TX_STATUS - Transmitter Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3336 | #define EMVSIM_TX_STATUS_TNTE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3337 | #define EMVSIM_TX_STATUS_TNTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3338 | #define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3339 | #define EMVSIM_TX_STATUS_TFE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3340 | #define EMVSIM_TX_STATUS_TFE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3341 | #define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3342 | #define EMVSIM_TX_STATUS_ETCF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3343 | #define EMVSIM_TX_STATUS_ETCF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3344 | #define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3345 | #define EMVSIM_TX_STATUS_TCF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3346 | #define EMVSIM_TX_STATUS_TCF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3347 | #define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3348 | #define EMVSIM_TX_STATUS_TFF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 3349 | #define EMVSIM_TX_STATUS_TFF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 3350 | #define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3351 | #define EMVSIM_TX_STATUS_TDTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3352 | #define EMVSIM_TX_STATUS_TDTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3353 | #define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3354 | #define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3355 | #define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3356 | #define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3357 | #define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 3358 | #define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 3359 | #define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3360 | #define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 3361 | #define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3362 | #define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3363 | #define EMVSIM_TX_STATUS_TX_CNT_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 3364 | #define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3365 | #define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3366 | |
AnnaBridge | 171:3a7713b1edbc | 3367 | /*! @name PCSR - Port Control and Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3368 | #define EMVSIM_PCSR_SAPD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3369 | #define EMVSIM_PCSR_SAPD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3370 | #define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3371 | #define EMVSIM_PCSR_SVCC_EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3372 | #define EMVSIM_PCSR_SVCC_EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3373 | #define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3374 | #define EMVSIM_PCSR_VCCENP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3375 | #define EMVSIM_PCSR_VCCENP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3376 | #define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3377 | #define EMVSIM_PCSR_SRST_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3378 | #define EMVSIM_PCSR_SRST_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3379 | #define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3380 | #define EMVSIM_PCSR_SCEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 3381 | #define EMVSIM_PCSR_SCEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3382 | #define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3383 | #define EMVSIM_PCSR_SCSP_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 3384 | #define EMVSIM_PCSR_SCSP_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 3385 | #define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3386 | #define EMVSIM_PCSR_SPD_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3387 | #define EMVSIM_PCSR_SPD_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3388 | #define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3389 | #define EMVSIM_PCSR_SPDIM_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 3390 | #define EMVSIM_PCSR_SPDIM_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3391 | #define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3392 | #define EMVSIM_PCSR_SPDIF_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 3393 | #define EMVSIM_PCSR_SPDIF_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 3394 | #define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3395 | #define EMVSIM_PCSR_SPDP_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 3396 | #define EMVSIM_PCSR_SPDP_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 3397 | #define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3398 | #define EMVSIM_PCSR_SPDES_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 3399 | #define EMVSIM_PCSR_SPDES_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 3400 | #define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3401 | |
AnnaBridge | 171:3a7713b1edbc | 3402 | /*! @name RX_BUF - Receive Data Read Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 3403 | #define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3404 | #define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3405 | #define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3406 | |
AnnaBridge | 171:3a7713b1edbc | 3407 | /*! @name TX_BUF - Transmit Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 3408 | #define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3409 | #define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3410 | #define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3411 | |
AnnaBridge | 171:3a7713b1edbc | 3412 | /*! @name TX_GETU - Transmitter Guard ETU Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 3413 | #define EMVSIM_TX_GETU_GETU_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3414 | #define EMVSIM_TX_GETU_GETU_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3415 | #define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3416 | |
AnnaBridge | 171:3a7713b1edbc | 3417 | /*! @name CWT_VAL - Character Wait Time Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 3418 | #define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3419 | #define EMVSIM_CWT_VAL_CWT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3420 | #define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3421 | |
AnnaBridge | 171:3a7713b1edbc | 3422 | /*! @name BWT_VAL - Block Wait Time Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 3423 | #define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3424 | #define EMVSIM_BWT_VAL_BWT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3425 | #define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3426 | |
AnnaBridge | 171:3a7713b1edbc | 3427 | /*! @name BGT_VAL - Block Guard Time Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 3428 | #define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3429 | #define EMVSIM_BGT_VAL_BGT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3430 | #define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3431 | |
AnnaBridge | 171:3a7713b1edbc | 3432 | /*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 3433 | #define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3434 | #define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3435 | #define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3436 | |
AnnaBridge | 171:3a7713b1edbc | 3437 | /*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */ |
AnnaBridge | 171:3a7713b1edbc | 3438 | #define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3439 | #define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3440 | #define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3441 | |
AnnaBridge | 171:3a7713b1edbc | 3442 | |
AnnaBridge | 171:3a7713b1edbc | 3443 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3444 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3445 | */ /* end of group EMVSIM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3446 | |
AnnaBridge | 171:3a7713b1edbc | 3447 | |
AnnaBridge | 171:3a7713b1edbc | 3448 | /* EMVSIM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3449 | /** Peripheral EMVSIM0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 3450 | #define EMVSIM0_BASE (0x4004E000u) |
AnnaBridge | 171:3a7713b1edbc | 3451 | /** Peripheral EMVSIM0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3452 | #define EMVSIM0 ((EMVSIM_Type *)EMVSIM0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3453 | /** Peripheral EMVSIM1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 3454 | #define EMVSIM1_BASE (0x4004F000u) |
AnnaBridge | 171:3a7713b1edbc | 3455 | /** Peripheral EMVSIM1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3456 | #define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3457 | /** Array initializer of EMVSIM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3458 | #define EMVSIM_BASE_ADDRS { EMVSIM0_BASE, EMVSIM1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3459 | /** Array initializer of EMVSIM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3460 | #define EMVSIM_BASE_PTRS { EMVSIM0, EMVSIM1 } |
AnnaBridge | 171:3a7713b1edbc | 3461 | /** Interrupt vectors for the EMVSIM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 3462 | #define EMVSIM_IRQS { EMVSIM0_IRQn, EMVSIM1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 3463 | |
AnnaBridge | 171:3a7713b1edbc | 3464 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3465 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3466 | */ /* end of group EMVSIM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3467 | |
AnnaBridge | 171:3a7713b1edbc | 3468 | |
AnnaBridge | 171:3a7713b1edbc | 3469 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3470 | -- EWM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3471 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3472 | |
AnnaBridge | 171:3a7713b1edbc | 3473 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3474 | * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3475 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3476 | */ |
AnnaBridge | 171:3a7713b1edbc | 3477 | |
AnnaBridge | 171:3a7713b1edbc | 3478 | /** EWM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3479 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3480 | __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 3481 | __O uint8_t SERV; /**< Service Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 3482 | __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 3483 | __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 3484 | uint8_t RESERVED_0[1]; |
AnnaBridge | 171:3a7713b1edbc | 3485 | __IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 3486 | } EWM_Type; |
AnnaBridge | 171:3a7713b1edbc | 3487 | |
AnnaBridge | 171:3a7713b1edbc | 3488 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3489 | -- EWM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3490 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3491 | |
AnnaBridge | 171:3a7713b1edbc | 3492 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3493 | * @addtogroup EWM_Register_Masks EWM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3494 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3495 | */ |
AnnaBridge | 171:3a7713b1edbc | 3496 | |
AnnaBridge | 171:3a7713b1edbc | 3497 | /*! @name CTRL - Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 3498 | #define EWM_CTRL_EWMEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3499 | #define EWM_CTRL_EWMEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3500 | #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3501 | #define EWM_CTRL_ASSIN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3502 | #define EWM_CTRL_ASSIN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3503 | #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3504 | #define EWM_CTRL_INEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3505 | #define EWM_CTRL_INEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3506 | #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3507 | #define EWM_CTRL_INTEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 3508 | #define EWM_CTRL_INTEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 3509 | #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3510 | |
AnnaBridge | 171:3a7713b1edbc | 3511 | /*! @name SERV - Service Register */ |
AnnaBridge | 171:3a7713b1edbc | 3512 | #define EWM_SERV_SERVICE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3513 | #define EWM_SERV_SERVICE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3514 | #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3515 | |
AnnaBridge | 171:3a7713b1edbc | 3516 | /*! @name CMPL - Compare Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 3517 | #define EWM_CMPL_COMPAREL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3518 | #define EWM_CMPL_COMPAREL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3519 | #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3520 | |
AnnaBridge | 171:3a7713b1edbc | 3521 | /*! @name CMPH - Compare High Register */ |
AnnaBridge | 171:3a7713b1edbc | 3522 | #define EWM_CMPH_COMPAREH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3523 | #define EWM_CMPH_COMPAREH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3524 | #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3525 | |
AnnaBridge | 171:3a7713b1edbc | 3526 | /*! @name CLKPRESCALER - Clock Prescaler Register */ |
AnnaBridge | 171:3a7713b1edbc | 3527 | #define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3528 | #define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3529 | #define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3530 | |
AnnaBridge | 171:3a7713b1edbc | 3531 | |
AnnaBridge | 171:3a7713b1edbc | 3532 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3533 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3534 | */ /* end of group EWM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3535 | |
AnnaBridge | 171:3a7713b1edbc | 3536 | |
AnnaBridge | 171:3a7713b1edbc | 3537 | /* EWM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3538 | /** Peripheral EWM base address */ |
AnnaBridge | 171:3a7713b1edbc | 3539 | #define EWM_BASE (0x40061000u) |
AnnaBridge | 171:3a7713b1edbc | 3540 | /** Peripheral EWM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3541 | #define EWM ((EWM_Type *)EWM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3542 | /** Array initializer of EWM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3543 | #define EWM_BASE_ADDRS { EWM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3544 | /** Array initializer of EWM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3545 | #define EWM_BASE_PTRS { EWM } |
AnnaBridge | 171:3a7713b1edbc | 3546 | /** Interrupt vectors for the EWM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 3547 | #define EWM_IRQS { WDOG_EWM_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 3548 | |
AnnaBridge | 171:3a7713b1edbc | 3549 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3550 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3551 | */ /* end of group EWM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3552 | |
AnnaBridge | 171:3a7713b1edbc | 3553 | |
AnnaBridge | 171:3a7713b1edbc | 3554 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3555 | -- FGPIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3556 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3557 | |
AnnaBridge | 171:3a7713b1edbc | 3558 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3559 | * @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3560 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3561 | */ |
AnnaBridge | 171:3a7713b1edbc | 3562 | |
AnnaBridge | 171:3a7713b1edbc | 3563 | /** FGPIO - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3564 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3565 | __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 3566 | __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3567 | __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 3568 | __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 3569 | __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 3570 | __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 3571 | } FGPIO_Type; |
AnnaBridge | 171:3a7713b1edbc | 3572 | |
AnnaBridge | 171:3a7713b1edbc | 3573 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3574 | -- FGPIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3575 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3576 | |
AnnaBridge | 171:3a7713b1edbc | 3577 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3578 | * @addtogroup FGPIO_Register_Masks FGPIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3579 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3580 | */ |
AnnaBridge | 171:3a7713b1edbc | 3581 | |
AnnaBridge | 171:3a7713b1edbc | 3582 | /*! @name PDOR - Port Data Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 3583 | #define FGPIO_PDOR_PDO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3584 | #define FGPIO_PDOR_PDO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3585 | #define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDOR_PDO_SHIFT)) & FGPIO_PDOR_PDO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3586 | |
AnnaBridge | 171:3a7713b1edbc | 3587 | /*! @name PSOR - Port Set Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 3588 | #define FGPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3589 | #define FGPIO_PSOR_PTSO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3590 | #define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PSOR_PTSO_SHIFT)) & FGPIO_PSOR_PTSO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3591 | |
AnnaBridge | 171:3a7713b1edbc | 3592 | /*! @name PCOR - Port Clear Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 3593 | #define FGPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3594 | #define FGPIO_PCOR_PTCO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3595 | #define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PCOR_PTCO_SHIFT)) & FGPIO_PCOR_PTCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3596 | |
AnnaBridge | 171:3a7713b1edbc | 3597 | /*! @name PTOR - Port Toggle Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 3598 | #define FGPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3599 | #define FGPIO_PTOR_PTTO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3600 | #define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PTOR_PTTO_SHIFT)) & FGPIO_PTOR_PTTO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3601 | |
AnnaBridge | 171:3a7713b1edbc | 3602 | /*! @name PDIR - Port Data Input Register */ |
AnnaBridge | 171:3a7713b1edbc | 3603 | #define FGPIO_PDIR_PDI_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3604 | #define FGPIO_PDIR_PDI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3605 | #define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDIR_PDI_SHIFT)) & FGPIO_PDIR_PDI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3606 | |
AnnaBridge | 171:3a7713b1edbc | 3607 | /*! @name PDDR - Port Data Direction Register */ |
AnnaBridge | 171:3a7713b1edbc | 3608 | #define FGPIO_PDDR_PDD_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3609 | #define FGPIO_PDDR_PDD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3610 | #define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << FGPIO_PDDR_PDD_SHIFT)) & FGPIO_PDDR_PDD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3611 | |
AnnaBridge | 171:3a7713b1edbc | 3612 | |
AnnaBridge | 171:3a7713b1edbc | 3613 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3614 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3615 | */ /* end of group FGPIO_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3616 | |
AnnaBridge | 171:3a7713b1edbc | 3617 | |
AnnaBridge | 171:3a7713b1edbc | 3618 | /* FGPIO - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3619 | /** Peripheral FGPIOA base address */ |
AnnaBridge | 171:3a7713b1edbc | 3620 | #define FGPIOA_BASE (0xF8000000u) |
AnnaBridge | 171:3a7713b1edbc | 3621 | /** Peripheral FGPIOA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3622 | #define FGPIOA ((FGPIO_Type *)FGPIOA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3623 | /** Peripheral FGPIOB base address */ |
AnnaBridge | 171:3a7713b1edbc | 3624 | #define FGPIOB_BASE (0xF8000040u) |
AnnaBridge | 171:3a7713b1edbc | 3625 | /** Peripheral FGPIOB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3626 | #define FGPIOB ((FGPIO_Type *)FGPIOB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3627 | /** Peripheral FGPIOC base address */ |
AnnaBridge | 171:3a7713b1edbc | 3628 | #define FGPIOC_BASE (0xF8000080u) |
AnnaBridge | 171:3a7713b1edbc | 3629 | /** Peripheral FGPIOC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3630 | #define FGPIOC ((FGPIO_Type *)FGPIOC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3631 | /** Peripheral FGPIOD base address */ |
AnnaBridge | 171:3a7713b1edbc | 3632 | #define FGPIOD_BASE (0xF80000C0u) |
AnnaBridge | 171:3a7713b1edbc | 3633 | /** Peripheral FGPIOD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3634 | #define FGPIOD ((FGPIO_Type *)FGPIOD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3635 | /** Peripheral FGPIOE base address */ |
AnnaBridge | 171:3a7713b1edbc | 3636 | #define FGPIOE_BASE (0xF8000100u) |
AnnaBridge | 171:3a7713b1edbc | 3637 | /** Peripheral FGPIOE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3638 | #define FGPIOE ((FGPIO_Type *)FGPIOE_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3639 | /** Array initializer of FGPIO peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3640 | #define FGPIO_BASE_ADDRS { FGPIOA_BASE, FGPIOB_BASE, FGPIOC_BASE, FGPIOD_BASE, FGPIOE_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3641 | /** Array initializer of FGPIO peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3642 | #define FGPIO_BASE_PTRS { FGPIOA, FGPIOB, FGPIOC, FGPIOD, FGPIOE } |
AnnaBridge | 171:3a7713b1edbc | 3643 | |
AnnaBridge | 171:3a7713b1edbc | 3644 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3645 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3646 | */ /* end of group FGPIO_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3647 | |
AnnaBridge | 171:3a7713b1edbc | 3648 | |
AnnaBridge | 171:3a7713b1edbc | 3649 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3650 | -- FLEXIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3651 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3652 | |
AnnaBridge | 171:3a7713b1edbc | 3653 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3654 | * @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3655 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3656 | */ |
AnnaBridge | 171:3a7713b1edbc | 3657 | |
AnnaBridge | 171:3a7713b1edbc | 3658 | /** FLEXIO - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3659 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3660 | __I uint32_t VERID; /**< Version ID Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 3661 | __I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3662 | __IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 3663 | __I uint32_t PIN; /**< Pin State Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 3664 | __IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 3665 | __IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 3666 | __IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 3667 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 3668 | __IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 3669 | __IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 3670 | __IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 3671 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 3672 | __IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 3673 | uint8_t RESERVED_2[12]; |
AnnaBridge | 171:3a7713b1edbc | 3674 | __IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 3675 | uint8_t RESERVED_3[60]; |
AnnaBridge | 171:3a7713b1edbc | 3676 | __IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3677 | uint8_t RESERVED_4[96]; |
AnnaBridge | 171:3a7713b1edbc | 3678 | __IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3679 | uint8_t RESERVED_5[224]; |
AnnaBridge | 171:3a7713b1edbc | 3680 | __IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3681 | uint8_t RESERVED_6[96]; |
AnnaBridge | 171:3a7713b1edbc | 3682 | __IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3683 | uint8_t RESERVED_7[96]; |
AnnaBridge | 171:3a7713b1edbc | 3684 | __IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3685 | uint8_t RESERVED_8[96]; |
AnnaBridge | 171:3a7713b1edbc | 3686 | __IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3687 | uint8_t RESERVED_9[96]; |
AnnaBridge | 171:3a7713b1edbc | 3688 | __IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3689 | uint8_t RESERVED_10[96]; |
AnnaBridge | 171:3a7713b1edbc | 3690 | __IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3691 | uint8_t RESERVED_11[96]; |
AnnaBridge | 171:3a7713b1edbc | 3692 | __IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3693 | uint8_t RESERVED_12[352]; |
AnnaBridge | 171:3a7713b1edbc | 3694 | __IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3695 | uint8_t RESERVED_13[96]; |
AnnaBridge | 171:3a7713b1edbc | 3696 | __IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3697 | uint8_t RESERVED_14[96]; |
AnnaBridge | 171:3a7713b1edbc | 3698 | __IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3699 | } FLEXIO_Type; |
AnnaBridge | 171:3a7713b1edbc | 3700 | |
AnnaBridge | 171:3a7713b1edbc | 3701 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3702 | -- FLEXIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3703 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3704 | |
AnnaBridge | 171:3a7713b1edbc | 3705 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3706 | * @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 3707 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3708 | */ |
AnnaBridge | 171:3a7713b1edbc | 3709 | |
AnnaBridge | 171:3a7713b1edbc | 3710 | /*! @name VERID - Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 3711 | #define FLEXIO_VERID_FEATURE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3712 | #define FLEXIO_VERID_FEATURE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3713 | #define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3714 | #define FLEXIO_VERID_MINOR_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 3715 | #define FLEXIO_VERID_MINOR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3716 | #define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3717 | #define FLEXIO_VERID_MAJOR_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 3718 | #define FLEXIO_VERID_MAJOR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3719 | #define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3720 | |
AnnaBridge | 171:3a7713b1edbc | 3721 | /*! @name PARAM - Parameter Register */ |
AnnaBridge | 171:3a7713b1edbc | 3722 | #define FLEXIO_PARAM_SHIFTER_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3723 | #define FLEXIO_PARAM_SHIFTER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3724 | #define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3725 | #define FLEXIO_PARAM_TIMER_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 3726 | #define FLEXIO_PARAM_TIMER_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3727 | #define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3728 | #define FLEXIO_PARAM_PIN_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 3729 | #define FLEXIO_PARAM_PIN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3730 | #define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3731 | #define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 3732 | #define FLEXIO_PARAM_TRIGGER_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3733 | #define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3734 | |
AnnaBridge | 171:3a7713b1edbc | 3735 | /*! @name CTRL - FlexIO Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 3736 | #define FLEXIO_CTRL_FLEXEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 3737 | #define FLEXIO_CTRL_FLEXEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3738 | #define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3739 | #define FLEXIO_CTRL_SWRST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3740 | #define FLEXIO_CTRL_SWRST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3741 | #define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3742 | #define FLEXIO_CTRL_FASTACC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 3743 | #define FLEXIO_CTRL_FASTACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 3744 | #define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3745 | #define FLEXIO_CTRL_DBGE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 3746 | #define FLEXIO_CTRL_DBGE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 3747 | #define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3748 | #define FLEXIO_CTRL_DOZEN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 3749 | #define FLEXIO_CTRL_DOZEN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 3750 | #define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3751 | |
AnnaBridge | 171:3a7713b1edbc | 3752 | /*! @name PIN - Pin State Register */ |
AnnaBridge | 171:3a7713b1edbc | 3753 | #define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3754 | #define FLEXIO_PIN_PDI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3755 | #define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3756 | |
AnnaBridge | 171:3a7713b1edbc | 3757 | /*! @name SHIFTSTAT - Shifter Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3758 | #define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3759 | #define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3760 | #define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3761 | |
AnnaBridge | 171:3a7713b1edbc | 3762 | /*! @name SHIFTERR - Shifter Error Register */ |
AnnaBridge | 171:3a7713b1edbc | 3763 | #define FLEXIO_SHIFTERR_SEF_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3764 | #define FLEXIO_SHIFTERR_SEF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3765 | #define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3766 | |
AnnaBridge | 171:3a7713b1edbc | 3767 | /*! @name TIMSTAT - Timer Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 3768 | #define FLEXIO_TIMSTAT_TSF_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3769 | #define FLEXIO_TIMSTAT_TSF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3770 | #define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3771 | |
AnnaBridge | 171:3a7713b1edbc | 3772 | /*! @name SHIFTSIEN - Shifter Status Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 3773 | #define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3774 | #define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3775 | #define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3776 | |
AnnaBridge | 171:3a7713b1edbc | 3777 | /*! @name SHIFTEIEN - Shifter Error Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 3778 | #define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3779 | #define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3780 | #define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3781 | |
AnnaBridge | 171:3a7713b1edbc | 3782 | /*! @name TIMIEN - Timer Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 3783 | #define FLEXIO_TIMIEN_TEIE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3784 | #define FLEXIO_TIMIEN_TEIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3785 | #define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3786 | |
AnnaBridge | 171:3a7713b1edbc | 3787 | /*! @name SHIFTSDEN - Shifter Status DMA Enable */ |
AnnaBridge | 171:3a7713b1edbc | 3788 | #define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 3789 | #define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3790 | #define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3791 | |
AnnaBridge | 171:3a7713b1edbc | 3792 | /*! @name SHIFTSTATE - Shifter State Register */ |
AnnaBridge | 171:3a7713b1edbc | 3793 | #define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 3794 | #define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3795 | #define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3796 | |
AnnaBridge | 171:3a7713b1edbc | 3797 | /*! @name SHIFTCTL - Shifter Control N Register */ |
AnnaBridge | 171:3a7713b1edbc | 3798 | #define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 3799 | #define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3800 | #define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3801 | #define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3802 | #define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3803 | #define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3804 | #define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 3805 | #define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3806 | #define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3807 | #define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 3808 | #define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3809 | #define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3810 | #define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3811 | #define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3812 | #define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3813 | #define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U) |
AnnaBridge | 171:3a7713b1edbc | 3814 | #define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3815 | #define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3816 | |
AnnaBridge | 171:3a7713b1edbc | 3817 | /* The count of FLEXIO_SHIFTCTL */ |
AnnaBridge | 171:3a7713b1edbc | 3818 | #define FLEXIO_SHIFTCTL_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3819 | |
AnnaBridge | 171:3a7713b1edbc | 3820 | /*! @name SHIFTCFG - Shifter Configuration N Register */ |
AnnaBridge | 171:3a7713b1edbc | 3821 | #define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 3822 | #define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3823 | #define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3824 | #define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 3825 | #define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3826 | #define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3827 | #define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 3828 | #define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3829 | #define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3830 | #define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U) |
AnnaBridge | 171:3a7713b1edbc | 3831 | #define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3832 | #define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3833 | |
AnnaBridge | 171:3a7713b1edbc | 3834 | /* The count of FLEXIO_SHIFTCFG */ |
AnnaBridge | 171:3a7713b1edbc | 3835 | #define FLEXIO_SHIFTCFG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3836 | |
AnnaBridge | 171:3a7713b1edbc | 3837 | /*! @name SHIFTBUF - Shifter Buffer N Register */ |
AnnaBridge | 171:3a7713b1edbc | 3838 | #define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3839 | #define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3840 | #define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3841 | |
AnnaBridge | 171:3a7713b1edbc | 3842 | /* The count of FLEXIO_SHIFTBUF */ |
AnnaBridge | 171:3a7713b1edbc | 3843 | #define FLEXIO_SHIFTBUF_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3844 | |
AnnaBridge | 171:3a7713b1edbc | 3845 | /*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 3846 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3847 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3848 | #define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3849 | |
AnnaBridge | 171:3a7713b1edbc | 3850 | /* The count of FLEXIO_SHIFTBUFBIS */ |
AnnaBridge | 171:3a7713b1edbc | 3851 | #define FLEXIO_SHIFTBUFBIS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3852 | |
AnnaBridge | 171:3a7713b1edbc | 3853 | /*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 3854 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3855 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3856 | #define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3857 | |
AnnaBridge | 171:3a7713b1edbc | 3858 | /* The count of FLEXIO_SHIFTBUFBYS */ |
AnnaBridge | 171:3a7713b1edbc | 3859 | #define FLEXIO_SHIFTBUFBYS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3860 | |
AnnaBridge | 171:3a7713b1edbc | 3861 | /*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 3862 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3863 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3864 | #define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3865 | |
AnnaBridge | 171:3a7713b1edbc | 3866 | /* The count of FLEXIO_SHIFTBUFBBS */ |
AnnaBridge | 171:3a7713b1edbc | 3867 | #define FLEXIO_SHIFTBUFBBS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3868 | |
AnnaBridge | 171:3a7713b1edbc | 3869 | /*! @name TIMCTL - Timer Control N Register */ |
AnnaBridge | 171:3a7713b1edbc | 3870 | #define FLEXIO_TIMCTL_TIMOD_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 3871 | #define FLEXIO_TIMCTL_TIMOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3872 | #define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3873 | #define FLEXIO_TIMCTL_PINPOL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 3874 | #define FLEXIO_TIMCTL_PINPOL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 3875 | #define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3876 | #define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 3877 | #define FLEXIO_TIMCTL_PINSEL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3878 | #define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3879 | #define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 3880 | #define FLEXIO_TIMCTL_PINCFG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3881 | #define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3882 | #define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 3883 | #define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 3884 | #define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3885 | #define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 3886 | #define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 3887 | #define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3888 | #define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U) |
AnnaBridge | 171:3a7713b1edbc | 3889 | #define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3890 | #define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3891 | |
AnnaBridge | 171:3a7713b1edbc | 3892 | /* The count of FLEXIO_TIMCTL */ |
AnnaBridge | 171:3a7713b1edbc | 3893 | #define FLEXIO_TIMCTL_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3894 | |
AnnaBridge | 171:3a7713b1edbc | 3895 | /*! @name TIMCFG - Timer Configuration N Register */ |
AnnaBridge | 171:3a7713b1edbc | 3896 | #define FLEXIO_TIMCFG_TSTART_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 3897 | #define FLEXIO_TIMCFG_TSTART_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 3898 | #define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3899 | #define FLEXIO_TIMCFG_TSTOP_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 3900 | #define FLEXIO_TIMCFG_TSTOP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 3901 | #define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3902 | #define FLEXIO_TIMCFG_TIMENA_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 3903 | #define FLEXIO_TIMCFG_TIMENA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3904 | #define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3905 | #define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 3906 | #define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 3907 | #define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3908 | #define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 3909 | #define FLEXIO_TIMCFG_TIMRST_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 3910 | #define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3911 | #define FLEXIO_TIMCFG_TIMDEC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 3912 | #define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 3913 | #define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3914 | #define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 3915 | #define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 3916 | #define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3917 | |
AnnaBridge | 171:3a7713b1edbc | 3918 | /* The count of FLEXIO_TIMCFG */ |
AnnaBridge | 171:3a7713b1edbc | 3919 | #define FLEXIO_TIMCFG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3920 | |
AnnaBridge | 171:3a7713b1edbc | 3921 | /*! @name TIMCMP - Timer Compare N Register */ |
AnnaBridge | 171:3a7713b1edbc | 3922 | #define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3923 | #define FLEXIO_TIMCMP_CMP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3924 | #define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3925 | |
AnnaBridge | 171:3a7713b1edbc | 3926 | /* The count of FLEXIO_TIMCMP */ |
AnnaBridge | 171:3a7713b1edbc | 3927 | #define FLEXIO_TIMCMP_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3928 | |
AnnaBridge | 171:3a7713b1edbc | 3929 | /*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 3930 | #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3931 | #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3932 | #define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3933 | |
AnnaBridge | 171:3a7713b1edbc | 3934 | /* The count of FLEXIO_SHIFTBUFNBS */ |
AnnaBridge | 171:3a7713b1edbc | 3935 | #define FLEXIO_SHIFTBUFNBS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3936 | |
AnnaBridge | 171:3a7713b1edbc | 3937 | /*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 3938 | #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3939 | #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3940 | #define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3941 | |
AnnaBridge | 171:3a7713b1edbc | 3942 | /* The count of FLEXIO_SHIFTBUFHWS */ |
AnnaBridge | 171:3a7713b1edbc | 3943 | #define FLEXIO_SHIFTBUFHWS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3944 | |
AnnaBridge | 171:3a7713b1edbc | 3945 | /*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */ |
AnnaBridge | 171:3a7713b1edbc | 3946 | #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 3947 | #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 3948 | #define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 3949 | |
AnnaBridge | 171:3a7713b1edbc | 3950 | /* The count of FLEXIO_SHIFTBUFNIS */ |
AnnaBridge | 171:3a7713b1edbc | 3951 | #define FLEXIO_SHIFTBUFNIS_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 3952 | |
AnnaBridge | 171:3a7713b1edbc | 3953 | |
AnnaBridge | 171:3a7713b1edbc | 3954 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3955 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3956 | */ /* end of group FLEXIO_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 3957 | |
AnnaBridge | 171:3a7713b1edbc | 3958 | |
AnnaBridge | 171:3a7713b1edbc | 3959 | /* FLEXIO - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3960 | /** Peripheral FLEXIO0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 3961 | #define FLEXIO0_BASE (0x4005F000u) |
AnnaBridge | 171:3a7713b1edbc | 3962 | /** Peripheral FLEXIO0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 3963 | #define FLEXIO0 ((FLEXIO_Type *)FLEXIO0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 3964 | /** Array initializer of FLEXIO peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 3965 | #define FLEXIO_BASE_ADDRS { FLEXIO0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 3966 | /** Array initializer of FLEXIO peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 3967 | #define FLEXIO_BASE_PTRS { FLEXIO0 } |
AnnaBridge | 171:3a7713b1edbc | 3968 | /** Interrupt vectors for the FLEXIO peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 3969 | #define FLEXIO_IRQS { FLEXIO0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 3970 | |
AnnaBridge | 171:3a7713b1edbc | 3971 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3972 | * @} |
AnnaBridge | 171:3a7713b1edbc | 3973 | */ /* end of group FLEXIO_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 3974 | |
AnnaBridge | 171:3a7713b1edbc | 3975 | |
AnnaBridge | 171:3a7713b1edbc | 3976 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 3977 | -- FTFA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3978 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 3979 | |
AnnaBridge | 171:3a7713b1edbc | 3980 | /*! |
AnnaBridge | 171:3a7713b1edbc | 3981 | * @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 3982 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 3983 | */ |
AnnaBridge | 171:3a7713b1edbc | 3984 | |
AnnaBridge | 171:3a7713b1edbc | 3985 | /** FTFA - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 3986 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 3987 | __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 3988 | __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 3989 | __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 3990 | __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 3991 | __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 3992 | __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 3993 | __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 3994 | __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 3995 | __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 3996 | __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 3997 | __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 3998 | __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 3999 | __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 4000 | __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 4001 | __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */ |
AnnaBridge | 171:3a7713b1edbc | 4002 | __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 4003 | __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 4004 | __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */ |
AnnaBridge | 171:3a7713b1edbc | 4005 | __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */ |
AnnaBridge | 171:3a7713b1edbc | 4006 | __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */ |
AnnaBridge | 171:3a7713b1edbc | 4007 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 4008 | __I uint8_t XACCH3; /**< Execute-only Access Registers, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 4009 | __I uint8_t XACCH2; /**< Execute-only Access Registers, offset: 0x19 */ |
AnnaBridge | 171:3a7713b1edbc | 4010 | __I uint8_t XACCH1; /**< Execute-only Access Registers, offset: 0x1A */ |
AnnaBridge | 171:3a7713b1edbc | 4011 | __I uint8_t XACCH0; /**< Execute-only Access Registers, offset: 0x1B */ |
AnnaBridge | 171:3a7713b1edbc | 4012 | __I uint8_t XACCL3; /**< Execute-only Access Registers, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 4013 | __I uint8_t XACCL2; /**< Execute-only Access Registers, offset: 0x1D */ |
AnnaBridge | 171:3a7713b1edbc | 4014 | __I uint8_t XACCL1; /**< Execute-only Access Registers, offset: 0x1E */ |
AnnaBridge | 171:3a7713b1edbc | 4015 | __I uint8_t XACCL0; /**< Execute-only Access Registers, offset: 0x1F */ |
AnnaBridge | 171:3a7713b1edbc | 4016 | __I uint8_t SACCH3; /**< Supervisor-only Access Registers, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 4017 | __I uint8_t SACCH2; /**< Supervisor-only Access Registers, offset: 0x21 */ |
AnnaBridge | 171:3a7713b1edbc | 4018 | __I uint8_t SACCH1; /**< Supervisor-only Access Registers, offset: 0x22 */ |
AnnaBridge | 171:3a7713b1edbc | 4019 | __I uint8_t SACCH0; /**< Supervisor-only Access Registers, offset: 0x23 */ |
AnnaBridge | 171:3a7713b1edbc | 4020 | __I uint8_t SACCL3; /**< Supervisor-only Access Registers, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 4021 | __I uint8_t SACCL2; /**< Supervisor-only Access Registers, offset: 0x25 */ |
AnnaBridge | 171:3a7713b1edbc | 4022 | __I uint8_t SACCL1; /**< Supervisor-only Access Registers, offset: 0x26 */ |
AnnaBridge | 171:3a7713b1edbc | 4023 | __I uint8_t SACCL0; /**< Supervisor-only Access Registers, offset: 0x27 */ |
AnnaBridge | 171:3a7713b1edbc | 4024 | __I uint8_t FACSS; /**< Flash Access Segment Size Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 4025 | uint8_t RESERVED_1[2]; |
AnnaBridge | 171:3a7713b1edbc | 4026 | __I uint8_t FACSN; /**< Flash Access Segment Number Register, offset: 0x2B */ |
AnnaBridge | 171:3a7713b1edbc | 4027 | } FTFA_Type; |
AnnaBridge | 171:3a7713b1edbc | 4028 | |
AnnaBridge | 171:3a7713b1edbc | 4029 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4030 | -- FTFA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4031 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4032 | |
AnnaBridge | 171:3a7713b1edbc | 4033 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4034 | * @addtogroup FTFA_Register_Masks FTFA Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4035 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4036 | */ |
AnnaBridge | 171:3a7713b1edbc | 4037 | |
AnnaBridge | 171:3a7713b1edbc | 4038 | /*! @name FSTAT - Flash Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 4039 | #define FTFA_FSTAT_MGSTAT0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4040 | #define FTFA_FSTAT_MGSTAT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4041 | #define FTFA_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_MGSTAT0_SHIFT)) & FTFA_FSTAT_MGSTAT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4042 | #define FTFA_FSTAT_FPVIOL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4043 | #define FTFA_FSTAT_FPVIOL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4044 | #define FTFA_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_FPVIOL_SHIFT)) & FTFA_FSTAT_FPVIOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4045 | #define FTFA_FSTAT_ACCERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4046 | #define FTFA_FSTAT_ACCERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4047 | #define FTFA_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_ACCERR_SHIFT)) & FTFA_FSTAT_ACCERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4048 | #define FTFA_FSTAT_RDCOLERR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4049 | #define FTFA_FSTAT_RDCOLERR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4050 | #define FTFA_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_RDCOLERR_SHIFT)) & FTFA_FSTAT_RDCOLERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4051 | #define FTFA_FSTAT_CCIF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4052 | #define FTFA_FSTAT_CCIF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4053 | #define FTFA_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSTAT_CCIF_SHIFT)) & FTFA_FSTAT_CCIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4054 | |
AnnaBridge | 171:3a7713b1edbc | 4055 | /*! @name FCNFG - Flash Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 4056 | #define FTFA_FCNFG_ERSSUSP_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4057 | #define FTFA_FCNFG_ERSSUSP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4058 | #define FTFA_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSSUSP_SHIFT)) & FTFA_FCNFG_ERSSUSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4059 | #define FTFA_FCNFG_ERSAREQ_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4060 | #define FTFA_FCNFG_ERSAREQ_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4061 | #define FTFA_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_ERSAREQ_SHIFT)) & FTFA_FCNFG_ERSAREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4062 | #define FTFA_FCNFG_RDCOLLIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4063 | #define FTFA_FCNFG_RDCOLLIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4064 | #define FTFA_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_RDCOLLIE_SHIFT)) & FTFA_FCNFG_RDCOLLIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4065 | #define FTFA_FCNFG_CCIE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4066 | #define FTFA_FCNFG_CCIE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4067 | #define FTFA_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCNFG_CCIE_SHIFT)) & FTFA_FCNFG_CCIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4068 | |
AnnaBridge | 171:3a7713b1edbc | 4069 | /*! @name FSEC - Flash Security Register */ |
AnnaBridge | 171:3a7713b1edbc | 4070 | #define FTFA_FSEC_SEC_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4071 | #define FTFA_FSEC_SEC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4072 | #define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_SEC_SHIFT)) & FTFA_FSEC_SEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4073 | #define FTFA_FSEC_FSLACC_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4074 | #define FTFA_FSEC_FSLACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4075 | #define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_FSLACC_SHIFT)) & FTFA_FSEC_FSLACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4076 | #define FTFA_FSEC_MEEN_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4077 | #define FTFA_FSEC_MEEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4078 | #define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_MEEN_SHIFT)) & FTFA_FSEC_MEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4079 | #define FTFA_FSEC_KEYEN_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4080 | #define FTFA_FSEC_KEYEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4081 | #define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FSEC_KEYEN_SHIFT)) & FTFA_FSEC_KEYEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4082 | |
AnnaBridge | 171:3a7713b1edbc | 4083 | /*! @name FOPT - Flash Option Register */ |
AnnaBridge | 171:3a7713b1edbc | 4084 | #define FTFA_FOPT_OPT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4085 | #define FTFA_FOPT_OPT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4086 | #define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FOPT_OPT_SHIFT)) & FTFA_FOPT_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4087 | |
AnnaBridge | 171:3a7713b1edbc | 4088 | /*! @name FCCOB3 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4089 | #define FTFA_FCCOB3_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4090 | #define FTFA_FCCOB3_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4091 | #define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB3_CCOBn_SHIFT)) & FTFA_FCCOB3_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4092 | |
AnnaBridge | 171:3a7713b1edbc | 4093 | /*! @name FCCOB2 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4094 | #define FTFA_FCCOB2_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4095 | #define FTFA_FCCOB2_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4096 | #define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB2_CCOBn_SHIFT)) & FTFA_FCCOB2_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4097 | |
AnnaBridge | 171:3a7713b1edbc | 4098 | /*! @name FCCOB1 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4099 | #define FTFA_FCCOB1_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4100 | #define FTFA_FCCOB1_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4101 | #define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB1_CCOBn_SHIFT)) & FTFA_FCCOB1_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4102 | |
AnnaBridge | 171:3a7713b1edbc | 4103 | /*! @name FCCOB0 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4104 | #define FTFA_FCCOB0_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4105 | #define FTFA_FCCOB0_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4106 | #define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB0_CCOBn_SHIFT)) & FTFA_FCCOB0_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4107 | |
AnnaBridge | 171:3a7713b1edbc | 4108 | /*! @name FCCOB7 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4109 | #define FTFA_FCCOB7_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4110 | #define FTFA_FCCOB7_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4111 | #define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB7_CCOBn_SHIFT)) & FTFA_FCCOB7_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4112 | |
AnnaBridge | 171:3a7713b1edbc | 4113 | /*! @name FCCOB6 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4114 | #define FTFA_FCCOB6_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4115 | #define FTFA_FCCOB6_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4116 | #define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB6_CCOBn_SHIFT)) & FTFA_FCCOB6_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4117 | |
AnnaBridge | 171:3a7713b1edbc | 4118 | /*! @name FCCOB5 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4119 | #define FTFA_FCCOB5_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4120 | #define FTFA_FCCOB5_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4121 | #define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB5_CCOBn_SHIFT)) & FTFA_FCCOB5_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4122 | |
AnnaBridge | 171:3a7713b1edbc | 4123 | /*! @name FCCOB4 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4124 | #define FTFA_FCCOB4_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4125 | #define FTFA_FCCOB4_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4126 | #define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB4_CCOBn_SHIFT)) & FTFA_FCCOB4_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4127 | |
AnnaBridge | 171:3a7713b1edbc | 4128 | /*! @name FCCOBB - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4129 | #define FTFA_FCCOBB_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4130 | #define FTFA_FCCOBB_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4131 | #define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBB_CCOBn_SHIFT)) & FTFA_FCCOBB_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4132 | |
AnnaBridge | 171:3a7713b1edbc | 4133 | /*! @name FCCOBA - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4134 | #define FTFA_FCCOBA_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4135 | #define FTFA_FCCOBA_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4136 | #define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOBA_CCOBn_SHIFT)) & FTFA_FCCOBA_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4137 | |
AnnaBridge | 171:3a7713b1edbc | 4138 | /*! @name FCCOB9 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4139 | #define FTFA_FCCOB9_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4140 | #define FTFA_FCCOB9_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4141 | #define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB9_CCOBn_SHIFT)) & FTFA_FCCOB9_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4142 | |
AnnaBridge | 171:3a7713b1edbc | 4143 | /*! @name FCCOB8 - Flash Common Command Object Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4144 | #define FTFA_FCCOB8_CCOBn_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4145 | #define FTFA_FCCOB8_CCOBn_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4146 | #define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FCCOB8_CCOBn_SHIFT)) & FTFA_FCCOB8_CCOBn_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4147 | |
AnnaBridge | 171:3a7713b1edbc | 4148 | /*! @name FPROT3 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4149 | #define FTFA_FPROT3_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4150 | #define FTFA_FPROT3_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4151 | #define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT3_PROT_SHIFT)) & FTFA_FPROT3_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4152 | |
AnnaBridge | 171:3a7713b1edbc | 4153 | /*! @name FPROT2 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4154 | #define FTFA_FPROT2_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4155 | #define FTFA_FPROT2_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4156 | #define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT2_PROT_SHIFT)) & FTFA_FPROT2_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4157 | |
AnnaBridge | 171:3a7713b1edbc | 4158 | /*! @name FPROT1 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4159 | #define FTFA_FPROT1_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4160 | #define FTFA_FPROT1_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4161 | #define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT1_PROT_SHIFT)) & FTFA_FPROT1_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4162 | |
AnnaBridge | 171:3a7713b1edbc | 4163 | /*! @name FPROT0 - Program Flash Protection Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4164 | #define FTFA_FPROT0_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4165 | #define FTFA_FPROT0_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4166 | #define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FPROT0_PROT_SHIFT)) & FTFA_FPROT0_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4167 | |
AnnaBridge | 171:3a7713b1edbc | 4168 | /*! @name XACCH3 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4169 | #define FTFA_XACCH3_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4170 | #define FTFA_XACCH3_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4171 | #define FTFA_XACCH3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH3_XA_SHIFT)) & FTFA_XACCH3_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4172 | |
AnnaBridge | 171:3a7713b1edbc | 4173 | /*! @name XACCH2 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4174 | #define FTFA_XACCH2_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4175 | #define FTFA_XACCH2_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4176 | #define FTFA_XACCH2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH2_XA_SHIFT)) & FTFA_XACCH2_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4177 | |
AnnaBridge | 171:3a7713b1edbc | 4178 | /*! @name XACCH1 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4179 | #define FTFA_XACCH1_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4180 | #define FTFA_XACCH1_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4181 | #define FTFA_XACCH1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH1_XA_SHIFT)) & FTFA_XACCH1_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4182 | |
AnnaBridge | 171:3a7713b1edbc | 4183 | /*! @name XACCH0 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4184 | #define FTFA_XACCH0_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4185 | #define FTFA_XACCH0_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4186 | #define FTFA_XACCH0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCH0_XA_SHIFT)) & FTFA_XACCH0_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4187 | |
AnnaBridge | 171:3a7713b1edbc | 4188 | /*! @name XACCL3 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4189 | #define FTFA_XACCL3_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4190 | #define FTFA_XACCL3_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4191 | #define FTFA_XACCL3_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL3_XA_SHIFT)) & FTFA_XACCL3_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4192 | |
AnnaBridge | 171:3a7713b1edbc | 4193 | /*! @name XACCL2 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4194 | #define FTFA_XACCL2_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4195 | #define FTFA_XACCL2_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4196 | #define FTFA_XACCL2_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL2_XA_SHIFT)) & FTFA_XACCL2_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4197 | |
AnnaBridge | 171:3a7713b1edbc | 4198 | /*! @name XACCL1 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4199 | #define FTFA_XACCL1_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4200 | #define FTFA_XACCL1_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4201 | #define FTFA_XACCL1_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL1_XA_SHIFT)) & FTFA_XACCL1_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4202 | |
AnnaBridge | 171:3a7713b1edbc | 4203 | /*! @name XACCL0 - Execute-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4204 | #define FTFA_XACCL0_XA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4205 | #define FTFA_XACCL0_XA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4206 | #define FTFA_XACCL0_XA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_XACCL0_XA_SHIFT)) & FTFA_XACCL0_XA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4207 | |
AnnaBridge | 171:3a7713b1edbc | 4208 | /*! @name SACCH3 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4209 | #define FTFA_SACCH3_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4210 | #define FTFA_SACCH3_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4211 | #define FTFA_SACCH3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH3_SA_SHIFT)) & FTFA_SACCH3_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4212 | |
AnnaBridge | 171:3a7713b1edbc | 4213 | /*! @name SACCH2 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4214 | #define FTFA_SACCH2_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4215 | #define FTFA_SACCH2_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4216 | #define FTFA_SACCH2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH2_SA_SHIFT)) & FTFA_SACCH2_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4217 | |
AnnaBridge | 171:3a7713b1edbc | 4218 | /*! @name SACCH1 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4219 | #define FTFA_SACCH1_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4220 | #define FTFA_SACCH1_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4221 | #define FTFA_SACCH1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH1_SA_SHIFT)) & FTFA_SACCH1_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4222 | |
AnnaBridge | 171:3a7713b1edbc | 4223 | /*! @name SACCH0 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4224 | #define FTFA_SACCH0_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4225 | #define FTFA_SACCH0_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4226 | #define FTFA_SACCH0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCH0_SA_SHIFT)) & FTFA_SACCH0_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4227 | |
AnnaBridge | 171:3a7713b1edbc | 4228 | /*! @name SACCL3 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4229 | #define FTFA_SACCL3_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4230 | #define FTFA_SACCL3_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4231 | #define FTFA_SACCL3_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL3_SA_SHIFT)) & FTFA_SACCL3_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4232 | |
AnnaBridge | 171:3a7713b1edbc | 4233 | /*! @name SACCL2 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4234 | #define FTFA_SACCL2_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4235 | #define FTFA_SACCL2_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4236 | #define FTFA_SACCL2_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL2_SA_SHIFT)) & FTFA_SACCL2_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4237 | |
AnnaBridge | 171:3a7713b1edbc | 4238 | /*! @name SACCL1 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4239 | #define FTFA_SACCL1_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4240 | #define FTFA_SACCL1_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4241 | #define FTFA_SACCL1_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL1_SA_SHIFT)) & FTFA_SACCL1_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4242 | |
AnnaBridge | 171:3a7713b1edbc | 4243 | /*! @name SACCL0 - Supervisor-only Access Registers */ |
AnnaBridge | 171:3a7713b1edbc | 4244 | #define FTFA_SACCL0_SA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4245 | #define FTFA_SACCL0_SA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4246 | #define FTFA_SACCL0_SA(x) (((uint8_t)(((uint8_t)(x)) << FTFA_SACCL0_SA_SHIFT)) & FTFA_SACCL0_SA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4247 | |
AnnaBridge | 171:3a7713b1edbc | 4248 | /*! @name FACSS - Flash Access Segment Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 4249 | #define FTFA_FACSS_SGSIZE_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4250 | #define FTFA_FACSS_SGSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4251 | #define FTFA_FACSS_SGSIZE(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSS_SGSIZE_SHIFT)) & FTFA_FACSS_SGSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4252 | |
AnnaBridge | 171:3a7713b1edbc | 4253 | /*! @name FACSN - Flash Access Segment Number Register */ |
AnnaBridge | 171:3a7713b1edbc | 4254 | #define FTFA_FACSN_NUMSG_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4255 | #define FTFA_FACSN_NUMSG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4256 | #define FTFA_FACSN_NUMSG(x) (((uint8_t)(((uint8_t)(x)) << FTFA_FACSN_NUMSG_SHIFT)) & FTFA_FACSN_NUMSG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4257 | |
AnnaBridge | 171:3a7713b1edbc | 4258 | |
AnnaBridge | 171:3a7713b1edbc | 4259 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4260 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4261 | */ /* end of group FTFA_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 4262 | |
AnnaBridge | 171:3a7713b1edbc | 4263 | |
AnnaBridge | 171:3a7713b1edbc | 4264 | /* FTFA - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4265 | /** Peripheral FTFA base address */ |
AnnaBridge | 171:3a7713b1edbc | 4266 | #define FTFA_BASE (0x40020000u) |
AnnaBridge | 171:3a7713b1edbc | 4267 | /** Peripheral FTFA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4268 | #define FTFA ((FTFA_Type *)FTFA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4269 | /** Array initializer of FTFA peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4270 | #define FTFA_BASE_ADDRS { FTFA_BASE } |
AnnaBridge | 171:3a7713b1edbc | 4271 | /** Array initializer of FTFA peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 4272 | #define FTFA_BASE_PTRS { FTFA } |
AnnaBridge | 171:3a7713b1edbc | 4273 | /** Interrupt vectors for the FTFA peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 4274 | #define FTFA_COMMAND_COMPLETE_IRQS { FTFA_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 4275 | #define FTFA_READ_COLLISION_IRQS { FTFA_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 4276 | |
AnnaBridge | 171:3a7713b1edbc | 4277 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4278 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4279 | */ /* end of group FTFA_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 4280 | |
AnnaBridge | 171:3a7713b1edbc | 4281 | |
AnnaBridge | 171:3a7713b1edbc | 4282 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4283 | -- GPIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4284 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4285 | |
AnnaBridge | 171:3a7713b1edbc | 4286 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4287 | * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4288 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4289 | */ |
AnnaBridge | 171:3a7713b1edbc | 4290 | |
AnnaBridge | 171:3a7713b1edbc | 4291 | /** GPIO - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 4292 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 4293 | __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 4294 | __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 4295 | __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 4296 | __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 4297 | __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 4298 | __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 4299 | } GPIO_Type; |
AnnaBridge | 171:3a7713b1edbc | 4300 | |
AnnaBridge | 171:3a7713b1edbc | 4301 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4302 | -- GPIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4303 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4304 | |
AnnaBridge | 171:3a7713b1edbc | 4305 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4306 | * @addtogroup GPIO_Register_Masks GPIO Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4307 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4308 | */ |
AnnaBridge | 171:3a7713b1edbc | 4309 | |
AnnaBridge | 171:3a7713b1edbc | 4310 | /*! @name PDOR - Port Data Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 4311 | #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4312 | #define GPIO_PDOR_PDO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4313 | #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4314 | |
AnnaBridge | 171:3a7713b1edbc | 4315 | /*! @name PSOR - Port Set Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 4316 | #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4317 | #define GPIO_PSOR_PTSO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4318 | #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4319 | |
AnnaBridge | 171:3a7713b1edbc | 4320 | /*! @name PCOR - Port Clear Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 4321 | #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4322 | #define GPIO_PCOR_PTCO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4323 | #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4324 | |
AnnaBridge | 171:3a7713b1edbc | 4325 | /*! @name PTOR - Port Toggle Output Register */ |
AnnaBridge | 171:3a7713b1edbc | 4326 | #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4327 | #define GPIO_PTOR_PTTO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4328 | #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4329 | |
AnnaBridge | 171:3a7713b1edbc | 4330 | /*! @name PDIR - Port Data Input Register */ |
AnnaBridge | 171:3a7713b1edbc | 4331 | #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4332 | #define GPIO_PDIR_PDI_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4333 | #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4334 | |
AnnaBridge | 171:3a7713b1edbc | 4335 | /*! @name PDDR - Port Data Direction Register */ |
AnnaBridge | 171:3a7713b1edbc | 4336 | #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4337 | #define GPIO_PDDR_PDD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4338 | #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4339 | |
AnnaBridge | 171:3a7713b1edbc | 4340 | |
AnnaBridge | 171:3a7713b1edbc | 4341 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4342 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4343 | */ /* end of group GPIO_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 4344 | |
AnnaBridge | 171:3a7713b1edbc | 4345 | |
AnnaBridge | 171:3a7713b1edbc | 4346 | /* GPIO - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4347 | /** Peripheral GPIOA base address */ |
AnnaBridge | 171:3a7713b1edbc | 4348 | #define GPIOA_BASE (0x400FF000u) |
AnnaBridge | 171:3a7713b1edbc | 4349 | /** Peripheral GPIOA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4350 | #define GPIOA ((GPIO_Type *)GPIOA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4351 | /** Peripheral GPIOB base address */ |
AnnaBridge | 171:3a7713b1edbc | 4352 | #define GPIOB_BASE (0x400FF040u) |
AnnaBridge | 171:3a7713b1edbc | 4353 | /** Peripheral GPIOB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4354 | #define GPIOB ((GPIO_Type *)GPIOB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4355 | /** Peripheral GPIOC base address */ |
AnnaBridge | 171:3a7713b1edbc | 4356 | #define GPIOC_BASE (0x400FF080u) |
AnnaBridge | 171:3a7713b1edbc | 4357 | /** Peripheral GPIOC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4358 | #define GPIOC ((GPIO_Type *)GPIOC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4359 | /** Peripheral GPIOD base address */ |
AnnaBridge | 171:3a7713b1edbc | 4360 | #define GPIOD_BASE (0x400FF0C0u) |
AnnaBridge | 171:3a7713b1edbc | 4361 | /** Peripheral GPIOD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4362 | #define GPIOD ((GPIO_Type *)GPIOD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4363 | /** Peripheral GPIOE base address */ |
AnnaBridge | 171:3a7713b1edbc | 4364 | #define GPIOE_BASE (0x400FF100u) |
AnnaBridge | 171:3a7713b1edbc | 4365 | /** Peripheral GPIOE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4366 | #define GPIOE ((GPIO_Type *)GPIOE_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4367 | /** Array initializer of GPIO peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4368 | #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE } |
AnnaBridge | 171:3a7713b1edbc | 4369 | /** Array initializer of GPIO peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 4370 | #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE } |
AnnaBridge | 171:3a7713b1edbc | 4371 | |
AnnaBridge | 171:3a7713b1edbc | 4372 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4373 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4374 | */ /* end of group GPIO_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 4375 | |
AnnaBridge | 171:3a7713b1edbc | 4376 | |
AnnaBridge | 171:3a7713b1edbc | 4377 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4378 | -- I2C Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4379 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4380 | |
AnnaBridge | 171:3a7713b1edbc | 4381 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4382 | * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4383 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4384 | */ |
AnnaBridge | 171:3a7713b1edbc | 4385 | |
AnnaBridge | 171:3a7713b1edbc | 4386 | /** I2C - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 4387 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 4388 | __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 4389 | __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 4390 | __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 4391 | __IO uint8_t S; /**< I2C Status register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 4392 | __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 4393 | __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 4394 | __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 4395 | __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 4396 | __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 4397 | __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 4398 | __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 4399 | __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 4400 | __IO uint8_t S2; /**< I2C Status register 2, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 4401 | } I2C_Type; |
AnnaBridge | 171:3a7713b1edbc | 4402 | |
AnnaBridge | 171:3a7713b1edbc | 4403 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4404 | -- I2C Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4405 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4406 | |
AnnaBridge | 171:3a7713b1edbc | 4407 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4408 | * @addtogroup I2C_Register_Masks I2C Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4409 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4410 | */ |
AnnaBridge | 171:3a7713b1edbc | 4411 | |
AnnaBridge | 171:3a7713b1edbc | 4412 | /*! @name A1 - I2C Address Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 4413 | #define I2C_A1_AD_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 4414 | #define I2C_A1_AD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4415 | #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4416 | |
AnnaBridge | 171:3a7713b1edbc | 4417 | /*! @name F - I2C Frequency Divider register */ |
AnnaBridge | 171:3a7713b1edbc | 4418 | #define I2C_F_ICR_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 4419 | #define I2C_F_ICR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4420 | #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4421 | #define I2C_F_MULT_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4422 | #define I2C_F_MULT_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4423 | #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4424 | |
AnnaBridge | 171:3a7713b1edbc | 4425 | /*! @name C1 - I2C Control Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 4426 | #define I2C_C1_DMAEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4427 | #define I2C_C1_DMAEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4428 | #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4429 | #define I2C_C1_WUEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4430 | #define I2C_C1_WUEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4431 | #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4432 | #define I2C_C1_RSTA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4433 | #define I2C_C1_RSTA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4434 | #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4435 | #define I2C_C1_TXAK_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4436 | #define I2C_C1_TXAK_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4437 | #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4438 | #define I2C_C1_TX_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4439 | #define I2C_C1_TX_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4440 | #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4441 | #define I2C_C1_MST_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4442 | #define I2C_C1_MST_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4443 | #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4444 | #define I2C_C1_IICIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4445 | #define I2C_C1_IICIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4446 | #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4447 | #define I2C_C1_IICEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4448 | #define I2C_C1_IICEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4449 | #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4450 | |
AnnaBridge | 171:3a7713b1edbc | 4451 | /*! @name S - I2C Status register */ |
AnnaBridge | 171:3a7713b1edbc | 4452 | #define I2C_S_RXAK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4453 | #define I2C_S_RXAK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4454 | #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4455 | #define I2C_S_IICIF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4456 | #define I2C_S_IICIF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4457 | #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4458 | #define I2C_S_SRW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4459 | #define I2C_S_SRW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4460 | #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4461 | #define I2C_S_RAM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4462 | #define I2C_S_RAM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4463 | #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4464 | #define I2C_S_ARBL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4465 | #define I2C_S_ARBL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4466 | #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4467 | #define I2C_S_BUSY_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4468 | #define I2C_S_BUSY_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4469 | #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4470 | #define I2C_S_IAAS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4471 | #define I2C_S_IAAS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4472 | #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4473 | #define I2C_S_TCF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4474 | #define I2C_S_TCF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4475 | #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4476 | |
AnnaBridge | 171:3a7713b1edbc | 4477 | /*! @name D - I2C Data I/O register */ |
AnnaBridge | 171:3a7713b1edbc | 4478 | #define I2C_D_DATA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4479 | #define I2C_D_DATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4480 | #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4481 | |
AnnaBridge | 171:3a7713b1edbc | 4482 | /*! @name C2 - I2C Control Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 4483 | #define I2C_C2_AD_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 4484 | #define I2C_C2_AD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4485 | #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4486 | #define I2C_C2_RMEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4487 | #define I2C_C2_RMEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4488 | #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4489 | #define I2C_C2_SBRC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4490 | #define I2C_C2_SBRC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4491 | #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4492 | #define I2C_C2_HDRS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4493 | #define I2C_C2_HDRS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4494 | #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4495 | #define I2C_C2_ADEXT_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4496 | #define I2C_C2_ADEXT_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4497 | #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4498 | #define I2C_C2_GCAEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4499 | #define I2C_C2_GCAEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4500 | #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4501 | |
AnnaBridge | 171:3a7713b1edbc | 4502 | /*! @name FLT - I2C Programmable Input Glitch Filter Register */ |
AnnaBridge | 171:3a7713b1edbc | 4503 | #define I2C_FLT_FLT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 4504 | #define I2C_FLT_FLT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4505 | #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4506 | #define I2C_FLT_STARTF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4507 | #define I2C_FLT_STARTF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4508 | #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4509 | #define I2C_FLT_SSIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4510 | #define I2C_FLT_SSIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4511 | #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4512 | #define I2C_FLT_STOPF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4513 | #define I2C_FLT_STOPF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4514 | #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4515 | #define I2C_FLT_SHEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4516 | #define I2C_FLT_SHEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4517 | #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4518 | |
AnnaBridge | 171:3a7713b1edbc | 4519 | /*! @name RA - I2C Range Address register */ |
AnnaBridge | 171:3a7713b1edbc | 4520 | #define I2C_RA_RAD_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 4521 | #define I2C_RA_RAD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4522 | #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4523 | |
AnnaBridge | 171:3a7713b1edbc | 4524 | /*! @name SMB - I2C SMBus Control and Status register */ |
AnnaBridge | 171:3a7713b1edbc | 4525 | #define I2C_SMB_SHTF2IE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4526 | #define I2C_SMB_SHTF2IE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4527 | #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4528 | #define I2C_SMB_SHTF2_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4529 | #define I2C_SMB_SHTF2_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4530 | #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4531 | #define I2C_SMB_SHTF1_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4532 | #define I2C_SMB_SHTF1_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4533 | #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4534 | #define I2C_SMB_SLTF_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4535 | #define I2C_SMB_SLTF_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4536 | #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4537 | #define I2C_SMB_TCKSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4538 | #define I2C_SMB_TCKSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4539 | #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4540 | #define I2C_SMB_SIICAEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4541 | #define I2C_SMB_SIICAEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4542 | #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4543 | #define I2C_SMB_ALERTEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4544 | #define I2C_SMB_ALERTEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4545 | #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4546 | #define I2C_SMB_FACK_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4547 | #define I2C_SMB_FACK_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4548 | #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4549 | |
AnnaBridge | 171:3a7713b1edbc | 4550 | /*! @name A2 - I2C Address Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 4551 | #define I2C_A2_SAD_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 4552 | #define I2C_A2_SAD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4553 | #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4554 | |
AnnaBridge | 171:3a7713b1edbc | 4555 | /*! @name SLTH - I2C SCL Low Timeout Register High */ |
AnnaBridge | 171:3a7713b1edbc | 4556 | #define I2C_SLTH_SSLT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4557 | #define I2C_SLTH_SSLT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4558 | #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4559 | |
AnnaBridge | 171:3a7713b1edbc | 4560 | /*! @name SLTL - I2C SCL Low Timeout Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 4561 | #define I2C_SLTL_SSLT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 4562 | #define I2C_SLTL_SSLT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4563 | #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4564 | |
AnnaBridge | 171:3a7713b1edbc | 4565 | /*! @name S2 - I2C Status register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 4566 | #define I2C_S2_EMPTY_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4567 | #define I2C_S2_EMPTY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4568 | #define I2C_S2_EMPTY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_EMPTY_SHIFT)) & I2C_S2_EMPTY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4569 | #define I2C_S2_ERROR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4570 | #define I2C_S2_ERROR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4571 | #define I2C_S2_ERROR(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_ERROR_SHIFT)) & I2C_S2_ERROR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4572 | #define I2C_S2_DFEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4573 | #define I2C_S2_DFEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4574 | #define I2C_S2_DFEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_S2_DFEN_SHIFT)) & I2C_S2_DFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4575 | |
AnnaBridge | 171:3a7713b1edbc | 4576 | |
AnnaBridge | 171:3a7713b1edbc | 4577 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4578 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4579 | */ /* end of group I2C_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 4580 | |
AnnaBridge | 171:3a7713b1edbc | 4581 | |
AnnaBridge | 171:3a7713b1edbc | 4582 | /* I2C - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4583 | /** Peripheral I2C0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 4584 | #define I2C0_BASE (0x40066000u) |
AnnaBridge | 171:3a7713b1edbc | 4585 | /** Peripheral I2C0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4586 | #define I2C0 ((I2C_Type *)I2C0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4587 | /** Peripheral I2C1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 4588 | #define I2C1_BASE (0x40067000u) |
AnnaBridge | 171:3a7713b1edbc | 4589 | /** Peripheral I2C1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4590 | #define I2C1 ((I2C_Type *)I2C1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4591 | /** Array initializer of I2C peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4592 | #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 4593 | /** Array initializer of I2C peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 4594 | #define I2C_BASE_PTRS { I2C0, I2C1 } |
AnnaBridge | 171:3a7713b1edbc | 4595 | /** Interrupt vectors for the I2C peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 4596 | #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 4597 | |
AnnaBridge | 171:3a7713b1edbc | 4598 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4599 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4600 | */ /* end of group I2C_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 4601 | |
AnnaBridge | 171:3a7713b1edbc | 4602 | |
AnnaBridge | 171:3a7713b1edbc | 4603 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4604 | -- INTMUX Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4605 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4606 | |
AnnaBridge | 171:3a7713b1edbc | 4607 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4608 | * @addtogroup INTMUX_Peripheral_Access_Layer INTMUX Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4609 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4610 | */ |
AnnaBridge | 171:3a7713b1edbc | 4611 | |
AnnaBridge | 171:3a7713b1edbc | 4612 | /** INTMUX - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 4613 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 4614 | struct { /* offset: 0x0, array step: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 4615 | __IO uint32_t CHn_CSR; /**< Channel n Control Status Register, array offset: 0x0, array step: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 4616 | __I uint32_t CHn_VEC; /**< Channel n Vector Number Register, array offset: 0x4, array step: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 4617 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 4618 | __IO uint32_t CHn_IER_31_0; /**< Channel n Interrupt Enable Register, array offset: 0x10, array step: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 4619 | uint8_t RESERVED_1[12]; |
AnnaBridge | 171:3a7713b1edbc | 4620 | __I uint32_t CHn_IPR_31_0; /**< Channel n Interrupt Pending Register, array offset: 0x20, array step: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 4621 | uint8_t RESERVED_2[28]; |
AnnaBridge | 171:3a7713b1edbc | 4622 | } CHANNEL[4]; |
AnnaBridge | 171:3a7713b1edbc | 4623 | } INTMUX_Type; |
AnnaBridge | 171:3a7713b1edbc | 4624 | |
AnnaBridge | 171:3a7713b1edbc | 4625 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4626 | -- INTMUX Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4627 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4628 | |
AnnaBridge | 171:3a7713b1edbc | 4629 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4630 | * @addtogroup INTMUX_Register_Masks INTMUX Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4631 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4632 | */ |
AnnaBridge | 171:3a7713b1edbc | 4633 | |
AnnaBridge | 171:3a7713b1edbc | 4634 | /*! @name CHn_CSR - Channel n Control Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 4635 | #define INTMUX_CHn_CSR_RST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4636 | #define INTMUX_CHn_CSR_RST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4637 | #define INTMUX_CHn_CSR_RST(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_RST_SHIFT)) & INTMUX_CHn_CSR_RST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4638 | #define INTMUX_CHn_CSR_AND_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4639 | #define INTMUX_CHn_CSR_AND_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4640 | #define INTMUX_CHn_CSR_AND(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_AND_SHIFT)) & INTMUX_CHn_CSR_AND_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4641 | #define INTMUX_CHn_CSR_IRQN_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4642 | #define INTMUX_CHn_CSR_IRQN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4643 | #define INTMUX_CHn_CSR_IRQN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQN_SHIFT)) & INTMUX_CHn_CSR_IRQN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4644 | #define INTMUX_CHn_CSR_CHIN_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 4645 | #define INTMUX_CHn_CSR_CHIN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 4646 | #define INTMUX_CHn_CSR_CHIN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_CHIN_SHIFT)) & INTMUX_CHn_CSR_CHIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4647 | #define INTMUX_CHn_CSR_IRQP_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 4648 | #define INTMUX_CHn_CSR_IRQP_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 4649 | #define INTMUX_CHn_CSR_IRQP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_CSR_IRQP_SHIFT)) & INTMUX_CHn_CSR_IRQP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4650 | |
AnnaBridge | 171:3a7713b1edbc | 4651 | /* The count of INTMUX_CHn_CSR */ |
AnnaBridge | 171:3a7713b1edbc | 4652 | #define INTMUX_CHn_CSR_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4653 | |
AnnaBridge | 171:3a7713b1edbc | 4654 | /*! @name CHn_VEC - Channel n Vector Number Register */ |
AnnaBridge | 171:3a7713b1edbc | 4655 | #define INTMUX_CHn_VEC_VECN_MASK (0x3FFCU) |
AnnaBridge | 171:3a7713b1edbc | 4656 | #define INTMUX_CHn_VEC_VECN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4657 | #define INTMUX_CHn_VEC_VECN(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_VEC_VECN_SHIFT)) & INTMUX_CHn_VEC_VECN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4658 | |
AnnaBridge | 171:3a7713b1edbc | 4659 | /* The count of INTMUX_CHn_VEC */ |
AnnaBridge | 171:3a7713b1edbc | 4660 | #define INTMUX_CHn_VEC_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4661 | |
AnnaBridge | 171:3a7713b1edbc | 4662 | /*! @name CHn_IER_31_0 - Channel n Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 4663 | #define INTMUX_CHn_IER_31_0_INTE_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4664 | #define INTMUX_CHn_IER_31_0_INTE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4665 | #define INTMUX_CHn_IER_31_0_INTE(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IER_31_0_INTE_SHIFT)) & INTMUX_CHn_IER_31_0_INTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4666 | |
AnnaBridge | 171:3a7713b1edbc | 4667 | /* The count of INTMUX_CHn_IER_31_0 */ |
AnnaBridge | 171:3a7713b1edbc | 4668 | #define INTMUX_CHn_IER_31_0_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4669 | |
AnnaBridge | 171:3a7713b1edbc | 4670 | /*! @name CHn_IPR_31_0 - Channel n Interrupt Pending Register */ |
AnnaBridge | 171:3a7713b1edbc | 4671 | #define INTMUX_CHn_IPR_31_0_INTP_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 4672 | #define INTMUX_CHn_IPR_31_0_INTP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4673 | #define INTMUX_CHn_IPR_31_0_INTP(x) (((uint32_t)(((uint32_t)(x)) << INTMUX_CHn_IPR_31_0_INTP_SHIFT)) & INTMUX_CHn_IPR_31_0_INTP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4674 | |
AnnaBridge | 171:3a7713b1edbc | 4675 | /* The count of INTMUX_CHn_IPR_31_0 */ |
AnnaBridge | 171:3a7713b1edbc | 4676 | #define INTMUX_CHn_IPR_31_0_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4677 | |
AnnaBridge | 171:3a7713b1edbc | 4678 | |
AnnaBridge | 171:3a7713b1edbc | 4679 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4680 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4681 | */ /* end of group INTMUX_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 4682 | |
AnnaBridge | 171:3a7713b1edbc | 4683 | |
AnnaBridge | 171:3a7713b1edbc | 4684 | /* INTMUX - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4685 | /** Peripheral INTMUX0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 4686 | #define INTMUX0_BASE (0x40024000u) |
AnnaBridge | 171:3a7713b1edbc | 4687 | /** Peripheral INTMUX0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 4688 | #define INTMUX0 ((INTMUX_Type *)INTMUX0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 4689 | /** Array initializer of INTMUX peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 4690 | #define INTMUX_BASE_ADDRS { INTMUX0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 4691 | /** Array initializer of INTMUX peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 4692 | #define INTMUX_BASE_PTRS { INTMUX0 } |
AnnaBridge | 171:3a7713b1edbc | 4693 | /** Interrupt vectors for the INTMUX peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 4694 | #define INTMUX_IRQS { INTMUX0_0_IRQn, INTMUX0_1_IRQn, INTMUX0_2_IRQn, INTMUX0_3_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 4695 | |
AnnaBridge | 171:3a7713b1edbc | 4696 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4697 | * @} |
AnnaBridge | 171:3a7713b1edbc | 4698 | */ /* end of group INTMUX_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 4699 | |
AnnaBridge | 171:3a7713b1edbc | 4700 | |
AnnaBridge | 171:3a7713b1edbc | 4701 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4702 | -- LLWU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4703 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4704 | |
AnnaBridge | 171:3a7713b1edbc | 4705 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4706 | * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 4707 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4708 | */ |
AnnaBridge | 171:3a7713b1edbc | 4709 | |
AnnaBridge | 171:3a7713b1edbc | 4710 | /** LLWU - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 4711 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 4712 | __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 4713 | __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 4714 | __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 4715 | __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 4716 | __IO uint8_t PE5; /**< LLWU Pin Enable 5 register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 4717 | __IO uint8_t PE6; /**< LLWU Pin Enable 6 register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 4718 | __IO uint8_t PE7; /**< LLWU Pin Enable 7 register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 4719 | __IO uint8_t PE8; /**< LLWU Pin Enable 8 register, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 4720 | __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 4721 | __IO uint8_t PF1; /**< LLWU Pin Flag 1 register, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 4722 | __IO uint8_t PF2; /**< LLWU Pin Flag 2 register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 4723 | __IO uint8_t PF3; /**< LLWU Pin Flag 3 register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 4724 | __IO uint8_t PF4; /**< LLWU Pin Flag 4 register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 4725 | __I uint8_t MF5; /**< LLWU Module Flag 5 register, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 4726 | __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0xE */ |
AnnaBridge | 171:3a7713b1edbc | 4727 | __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0xF */ |
AnnaBridge | 171:3a7713b1edbc | 4728 | __IO uint8_t FILT3; /**< LLWU Pin Filter 3 register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 4729 | __IO uint8_t FILT4; /**< LLWU Pin Filter 4 register, offset: 0x11 */ |
AnnaBridge | 171:3a7713b1edbc | 4730 | } LLWU_Type; |
AnnaBridge | 171:3a7713b1edbc | 4731 | |
AnnaBridge | 171:3a7713b1edbc | 4732 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 4733 | -- LLWU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4734 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 4735 | |
AnnaBridge | 171:3a7713b1edbc | 4736 | /*! |
AnnaBridge | 171:3a7713b1edbc | 4737 | * @addtogroup LLWU_Register_Masks LLWU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 4738 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 4739 | */ |
AnnaBridge | 171:3a7713b1edbc | 4740 | |
AnnaBridge | 171:3a7713b1edbc | 4741 | /*! @name PE1 - LLWU Pin Enable 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 4742 | #define LLWU_PE1_WUPE0_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4743 | #define LLWU_PE1_WUPE0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4744 | #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4745 | #define LLWU_PE1_WUPE1_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4746 | #define LLWU_PE1_WUPE1_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4747 | #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4748 | #define LLWU_PE1_WUPE2_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4749 | #define LLWU_PE1_WUPE2_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4750 | #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4751 | #define LLWU_PE1_WUPE3_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4752 | #define LLWU_PE1_WUPE3_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4753 | #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4754 | |
AnnaBridge | 171:3a7713b1edbc | 4755 | /*! @name PE2 - LLWU Pin Enable 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 4756 | #define LLWU_PE2_WUPE4_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4757 | #define LLWU_PE2_WUPE4_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4758 | #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4759 | #define LLWU_PE2_WUPE5_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4760 | #define LLWU_PE2_WUPE5_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4761 | #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4762 | #define LLWU_PE2_WUPE6_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4763 | #define LLWU_PE2_WUPE6_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4764 | #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4765 | #define LLWU_PE2_WUPE7_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4766 | #define LLWU_PE2_WUPE7_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4767 | #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4768 | |
AnnaBridge | 171:3a7713b1edbc | 4769 | /*! @name PE3 - LLWU Pin Enable 3 register */ |
AnnaBridge | 171:3a7713b1edbc | 4770 | #define LLWU_PE3_WUPE8_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4771 | #define LLWU_PE3_WUPE8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4772 | #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4773 | #define LLWU_PE3_WUPE9_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4774 | #define LLWU_PE3_WUPE9_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4775 | #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4776 | #define LLWU_PE3_WUPE10_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4777 | #define LLWU_PE3_WUPE10_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4778 | #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4779 | #define LLWU_PE3_WUPE11_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4780 | #define LLWU_PE3_WUPE11_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4781 | #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4782 | |
AnnaBridge | 171:3a7713b1edbc | 4783 | /*! @name PE4 - LLWU Pin Enable 4 register */ |
AnnaBridge | 171:3a7713b1edbc | 4784 | #define LLWU_PE4_WUPE12_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4785 | #define LLWU_PE4_WUPE12_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4786 | #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4787 | #define LLWU_PE4_WUPE13_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4788 | #define LLWU_PE4_WUPE13_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4789 | #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4790 | #define LLWU_PE4_WUPE14_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4791 | #define LLWU_PE4_WUPE14_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4792 | #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4793 | #define LLWU_PE4_WUPE15_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4794 | #define LLWU_PE4_WUPE15_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4795 | #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4796 | |
AnnaBridge | 171:3a7713b1edbc | 4797 | /*! @name PE5 - LLWU Pin Enable 5 register */ |
AnnaBridge | 171:3a7713b1edbc | 4798 | #define LLWU_PE5_WUPE16_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4799 | #define LLWU_PE5_WUPE16_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4800 | #define LLWU_PE5_WUPE16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4801 | #define LLWU_PE5_WUPE17_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4802 | #define LLWU_PE5_WUPE17_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4803 | #define LLWU_PE5_WUPE17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4804 | #define LLWU_PE5_WUPE18_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4805 | #define LLWU_PE5_WUPE18_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4806 | #define LLWU_PE5_WUPE18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4807 | #define LLWU_PE5_WUPE19_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4808 | #define LLWU_PE5_WUPE19_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4809 | #define LLWU_PE5_WUPE19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4810 | |
AnnaBridge | 171:3a7713b1edbc | 4811 | /*! @name PE6 - LLWU Pin Enable 6 register */ |
AnnaBridge | 171:3a7713b1edbc | 4812 | #define LLWU_PE6_WUPE20_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4813 | #define LLWU_PE6_WUPE20_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4814 | #define LLWU_PE6_WUPE20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4815 | #define LLWU_PE6_WUPE21_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4816 | #define LLWU_PE6_WUPE21_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4817 | #define LLWU_PE6_WUPE21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4818 | #define LLWU_PE6_WUPE22_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4819 | #define LLWU_PE6_WUPE22_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4820 | #define LLWU_PE6_WUPE22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4821 | #define LLWU_PE6_WUPE23_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4822 | #define LLWU_PE6_WUPE23_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4823 | #define LLWU_PE6_WUPE23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4824 | |
AnnaBridge | 171:3a7713b1edbc | 4825 | /*! @name PE7 - LLWU Pin Enable 7 register */ |
AnnaBridge | 171:3a7713b1edbc | 4826 | #define LLWU_PE7_WUPE24_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4827 | #define LLWU_PE7_WUPE24_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4828 | #define LLWU_PE7_WUPE24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4829 | #define LLWU_PE7_WUPE25_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4830 | #define LLWU_PE7_WUPE25_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4831 | #define LLWU_PE7_WUPE25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4832 | #define LLWU_PE7_WUPE26_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4833 | #define LLWU_PE7_WUPE26_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4834 | #define LLWU_PE7_WUPE26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4835 | #define LLWU_PE7_WUPE27_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4836 | #define LLWU_PE7_WUPE27_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4837 | #define LLWU_PE7_WUPE27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4838 | |
AnnaBridge | 171:3a7713b1edbc | 4839 | /*! @name PE8 - LLWU Pin Enable 8 register */ |
AnnaBridge | 171:3a7713b1edbc | 4840 | #define LLWU_PE8_WUPE28_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 4841 | #define LLWU_PE8_WUPE28_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4842 | #define LLWU_PE8_WUPE28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4843 | #define LLWU_PE8_WUPE29_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 4844 | #define LLWU_PE8_WUPE29_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4845 | #define LLWU_PE8_WUPE29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4846 | #define LLWU_PE8_WUPE30_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 4847 | #define LLWU_PE8_WUPE30_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4848 | #define LLWU_PE8_WUPE30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4849 | #define LLWU_PE8_WUPE31_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 4850 | #define LLWU_PE8_WUPE31_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4851 | #define LLWU_PE8_WUPE31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4852 | |
AnnaBridge | 171:3a7713b1edbc | 4853 | /*! @name ME - LLWU Module Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 4854 | #define LLWU_ME_WUME0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4855 | #define LLWU_ME_WUME0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4856 | #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4857 | #define LLWU_ME_WUME1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4858 | #define LLWU_ME_WUME1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4859 | #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4860 | #define LLWU_ME_WUME2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4861 | #define LLWU_ME_WUME2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4862 | #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4863 | #define LLWU_ME_WUME3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4864 | #define LLWU_ME_WUME3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4865 | #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4866 | #define LLWU_ME_WUME4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4867 | #define LLWU_ME_WUME4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4868 | #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4869 | #define LLWU_ME_WUME5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4870 | #define LLWU_ME_WUME5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4871 | #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4872 | #define LLWU_ME_WUME6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4873 | #define LLWU_ME_WUME6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4874 | #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4875 | #define LLWU_ME_WUME7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4876 | #define LLWU_ME_WUME7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4877 | #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4878 | |
AnnaBridge | 171:3a7713b1edbc | 4879 | /*! @name PF1 - LLWU Pin Flag 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 4880 | #define LLWU_PF1_WUF0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4881 | #define LLWU_PF1_WUF0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4882 | #define LLWU_PF1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4883 | #define LLWU_PF1_WUF1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4884 | #define LLWU_PF1_WUF1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4885 | #define LLWU_PF1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4886 | #define LLWU_PF1_WUF2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4887 | #define LLWU_PF1_WUF2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4888 | #define LLWU_PF1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4889 | #define LLWU_PF1_WUF3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4890 | #define LLWU_PF1_WUF3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4891 | #define LLWU_PF1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4892 | #define LLWU_PF1_WUF4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4893 | #define LLWU_PF1_WUF4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4894 | #define LLWU_PF1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4895 | #define LLWU_PF1_WUF5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4896 | #define LLWU_PF1_WUF5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4897 | #define LLWU_PF1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4898 | #define LLWU_PF1_WUF6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4899 | #define LLWU_PF1_WUF6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4900 | #define LLWU_PF1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4901 | #define LLWU_PF1_WUF7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4902 | #define LLWU_PF1_WUF7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4903 | #define LLWU_PF1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4904 | |
AnnaBridge | 171:3a7713b1edbc | 4905 | /*! @name PF2 - LLWU Pin Flag 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 4906 | #define LLWU_PF2_WUF8_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4907 | #define LLWU_PF2_WUF8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4908 | #define LLWU_PF2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4909 | #define LLWU_PF2_WUF9_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4910 | #define LLWU_PF2_WUF9_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4911 | #define LLWU_PF2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4912 | #define LLWU_PF2_WUF10_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4913 | #define LLWU_PF2_WUF10_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4914 | #define LLWU_PF2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4915 | #define LLWU_PF2_WUF11_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4916 | #define LLWU_PF2_WUF11_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4917 | #define LLWU_PF2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4918 | #define LLWU_PF2_WUF12_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4919 | #define LLWU_PF2_WUF12_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4920 | #define LLWU_PF2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4921 | #define LLWU_PF2_WUF13_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4922 | #define LLWU_PF2_WUF13_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4923 | #define LLWU_PF2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4924 | #define LLWU_PF2_WUF14_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4925 | #define LLWU_PF2_WUF14_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4926 | #define LLWU_PF2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4927 | #define LLWU_PF2_WUF15_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4928 | #define LLWU_PF2_WUF15_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4929 | #define LLWU_PF2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4930 | |
AnnaBridge | 171:3a7713b1edbc | 4931 | /*! @name PF3 - LLWU Pin Flag 3 register */ |
AnnaBridge | 171:3a7713b1edbc | 4932 | #define LLWU_PF3_WUF16_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4933 | #define LLWU_PF3_WUF16_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4934 | #define LLWU_PF3_WUF16(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4935 | #define LLWU_PF3_WUF17_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4936 | #define LLWU_PF3_WUF17_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4937 | #define LLWU_PF3_WUF17(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4938 | #define LLWU_PF3_WUF18_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4939 | #define LLWU_PF3_WUF18_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4940 | #define LLWU_PF3_WUF18(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4941 | #define LLWU_PF3_WUF19_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4942 | #define LLWU_PF3_WUF19_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4943 | #define LLWU_PF3_WUF19(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4944 | #define LLWU_PF3_WUF20_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4945 | #define LLWU_PF3_WUF20_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4946 | #define LLWU_PF3_WUF20(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4947 | #define LLWU_PF3_WUF21_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4948 | #define LLWU_PF3_WUF21_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4949 | #define LLWU_PF3_WUF21(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4950 | #define LLWU_PF3_WUF22_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4951 | #define LLWU_PF3_WUF22_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4952 | #define LLWU_PF3_WUF22(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4953 | #define LLWU_PF3_WUF23_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4954 | #define LLWU_PF3_WUF23_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4955 | #define LLWU_PF3_WUF23(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4956 | |
AnnaBridge | 171:3a7713b1edbc | 4957 | /*! @name PF4 - LLWU Pin Flag 4 register */ |
AnnaBridge | 171:3a7713b1edbc | 4958 | #define LLWU_PF4_WUF24_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4959 | #define LLWU_PF4_WUF24_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4960 | #define LLWU_PF4_WUF24(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4961 | #define LLWU_PF4_WUF25_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4962 | #define LLWU_PF4_WUF25_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4963 | #define LLWU_PF4_WUF25(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4964 | #define LLWU_PF4_WUF26_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4965 | #define LLWU_PF4_WUF26_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4966 | #define LLWU_PF4_WUF26(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4967 | #define LLWU_PF4_WUF27_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4968 | #define LLWU_PF4_WUF27_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4969 | #define LLWU_PF4_WUF27(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4970 | #define LLWU_PF4_WUF28_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4971 | #define LLWU_PF4_WUF28_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4972 | #define LLWU_PF4_WUF28(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4973 | #define LLWU_PF4_WUF29_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 4974 | #define LLWU_PF4_WUF29_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 4975 | #define LLWU_PF4_WUF29(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4976 | #define LLWU_PF4_WUF30_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 4977 | #define LLWU_PF4_WUF30_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 4978 | #define LLWU_PF4_WUF30(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4979 | #define LLWU_PF4_WUF31_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 4980 | #define LLWU_PF4_WUF31_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 4981 | #define LLWU_PF4_WUF31(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4982 | |
AnnaBridge | 171:3a7713b1edbc | 4983 | /*! @name MF5 - LLWU Module Flag 5 register */ |
AnnaBridge | 171:3a7713b1edbc | 4984 | #define LLWU_MF5_MWUF0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 4985 | #define LLWU_MF5_MWUF0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 4986 | #define LLWU_MF5_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4987 | #define LLWU_MF5_MWUF1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 4988 | #define LLWU_MF5_MWUF1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 4989 | #define LLWU_MF5_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4990 | #define LLWU_MF5_MWUF2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 4991 | #define LLWU_MF5_MWUF2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 4992 | #define LLWU_MF5_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4993 | #define LLWU_MF5_MWUF3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 4994 | #define LLWU_MF5_MWUF3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 4995 | #define LLWU_MF5_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4996 | #define LLWU_MF5_MWUF4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 4997 | #define LLWU_MF5_MWUF4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 4998 | #define LLWU_MF5_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 4999 | #define LLWU_MF5_MWUF5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5000 | #define LLWU_MF5_MWUF5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5001 | #define LLWU_MF5_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5002 | #define LLWU_MF5_MWUF6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5003 | #define LLWU_MF5_MWUF6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5004 | #define LLWU_MF5_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5005 | #define LLWU_MF5_MWUF7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5006 | #define LLWU_MF5_MWUF7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5007 | #define LLWU_MF5_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5008 | |
AnnaBridge | 171:3a7713b1edbc | 5009 | /*! @name FILT1 - LLWU Pin Filter 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 5010 | #define LLWU_FILT1_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 5011 | #define LLWU_FILT1_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5012 | #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5013 | #define LLWU_FILT1_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 5014 | #define LLWU_FILT1_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5015 | #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5016 | #define LLWU_FILT1_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5017 | #define LLWU_FILT1_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5018 | #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5019 | |
AnnaBridge | 171:3a7713b1edbc | 5020 | /*! @name FILT2 - LLWU Pin Filter 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 5021 | #define LLWU_FILT2_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 5022 | #define LLWU_FILT2_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5023 | #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5024 | #define LLWU_FILT2_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 5025 | #define LLWU_FILT2_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5026 | #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5027 | #define LLWU_FILT2_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5028 | #define LLWU_FILT2_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5029 | #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5030 | |
AnnaBridge | 171:3a7713b1edbc | 5031 | /*! @name FILT3 - LLWU Pin Filter 3 register */ |
AnnaBridge | 171:3a7713b1edbc | 5032 | #define LLWU_FILT3_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 5033 | #define LLWU_FILT3_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5034 | #define LLWU_FILT3_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5035 | #define LLWU_FILT3_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 5036 | #define LLWU_FILT3_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5037 | #define LLWU_FILT3_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5038 | #define LLWU_FILT3_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5039 | #define LLWU_FILT3_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5040 | #define LLWU_FILT3_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5041 | |
AnnaBridge | 171:3a7713b1edbc | 5042 | /*! @name FILT4 - LLWU Pin Filter 4 register */ |
AnnaBridge | 171:3a7713b1edbc | 5043 | #define LLWU_FILT4_FILTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 5044 | #define LLWU_FILT4_FILTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5045 | #define LLWU_FILT4_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5046 | #define LLWU_FILT4_FILTE_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 5047 | #define LLWU_FILT4_FILTE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5048 | #define LLWU_FILT4_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5049 | #define LLWU_FILT4_FILTF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5050 | #define LLWU_FILT4_FILTF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5051 | #define LLWU_FILT4_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5052 | |
AnnaBridge | 171:3a7713b1edbc | 5053 | |
AnnaBridge | 171:3a7713b1edbc | 5054 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5055 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5056 | */ /* end of group LLWU_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5057 | |
AnnaBridge | 171:3a7713b1edbc | 5058 | |
AnnaBridge | 171:3a7713b1edbc | 5059 | /* LLWU - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5060 | /** Peripheral LLWU base address */ |
AnnaBridge | 171:3a7713b1edbc | 5061 | #define LLWU_BASE (0x4007C000u) |
AnnaBridge | 171:3a7713b1edbc | 5062 | /** Peripheral LLWU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5063 | #define LLWU ((LLWU_Type *)LLWU_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5064 | /** Array initializer of LLWU peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5065 | #define LLWU_BASE_ADDRS { LLWU_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5066 | /** Array initializer of LLWU peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5067 | #define LLWU_BASE_PTRS { LLWU } |
AnnaBridge | 171:3a7713b1edbc | 5068 | /** Interrupt vectors for the LLWU peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 5069 | #define LLWU_IRQS { LLWU_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5070 | |
AnnaBridge | 171:3a7713b1edbc | 5071 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5072 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5073 | */ /* end of group LLWU_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5074 | |
AnnaBridge | 171:3a7713b1edbc | 5075 | |
AnnaBridge | 171:3a7713b1edbc | 5076 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5077 | -- LPTMR Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5078 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5079 | |
AnnaBridge | 171:3a7713b1edbc | 5080 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5081 | * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5082 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5083 | */ |
AnnaBridge | 171:3a7713b1edbc | 5084 | |
AnnaBridge | 171:3a7713b1edbc | 5085 | /** LPTMR - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5086 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5087 | __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5088 | __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5089 | __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 5090 | __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5091 | } LPTMR_Type; |
AnnaBridge | 171:3a7713b1edbc | 5092 | |
AnnaBridge | 171:3a7713b1edbc | 5093 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5094 | -- LPTMR Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5095 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5096 | |
AnnaBridge | 171:3a7713b1edbc | 5097 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5098 | * @addtogroup LPTMR_Register_Masks LPTMR Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5099 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5100 | */ |
AnnaBridge | 171:3a7713b1edbc | 5101 | |
AnnaBridge | 171:3a7713b1edbc | 5102 | /*! @name CSR - Low Power Timer Control Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5103 | #define LPTMR_CSR_TEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5104 | #define LPTMR_CSR_TEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5105 | #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5106 | #define LPTMR_CSR_TMS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5107 | #define LPTMR_CSR_TMS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5108 | #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5109 | #define LPTMR_CSR_TFC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5110 | #define LPTMR_CSR_TFC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5111 | #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5112 | #define LPTMR_CSR_TPP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5113 | #define LPTMR_CSR_TPP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5114 | #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5115 | #define LPTMR_CSR_TPS_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 5116 | #define LPTMR_CSR_TPS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5117 | #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5118 | #define LPTMR_CSR_TIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5119 | #define LPTMR_CSR_TIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5120 | #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5121 | #define LPTMR_CSR_TCF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5122 | #define LPTMR_CSR_TCF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5123 | #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5124 | |
AnnaBridge | 171:3a7713b1edbc | 5125 | /*! @name PSR - Low Power Timer Prescale Register */ |
AnnaBridge | 171:3a7713b1edbc | 5126 | #define LPTMR_PSR_PCS_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 5127 | #define LPTMR_PSR_PCS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5128 | #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5129 | #define LPTMR_PSR_PBYP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5130 | #define LPTMR_PSR_PBYP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5131 | #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5132 | #define LPTMR_PSR_PRESCALE_MASK (0x78U) |
AnnaBridge | 171:3a7713b1edbc | 5133 | #define LPTMR_PSR_PRESCALE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5134 | #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5135 | |
AnnaBridge | 171:3a7713b1edbc | 5136 | /*! @name CMR - Low Power Timer Compare Register */ |
AnnaBridge | 171:3a7713b1edbc | 5137 | #define LPTMR_CMR_COMPARE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5138 | #define LPTMR_CMR_COMPARE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5139 | #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5140 | |
AnnaBridge | 171:3a7713b1edbc | 5141 | /*! @name CNR - Low Power Timer Counter Register */ |
AnnaBridge | 171:3a7713b1edbc | 5142 | #define LPTMR_CNR_COUNTER_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5143 | #define LPTMR_CNR_COUNTER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5144 | #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5145 | |
AnnaBridge | 171:3a7713b1edbc | 5146 | |
AnnaBridge | 171:3a7713b1edbc | 5147 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5148 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5149 | */ /* end of group LPTMR_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5150 | |
AnnaBridge | 171:3a7713b1edbc | 5151 | |
AnnaBridge | 171:3a7713b1edbc | 5152 | /* LPTMR - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5153 | /** Peripheral LPTMR0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5154 | #define LPTMR0_BASE (0x40040000u) |
AnnaBridge | 171:3a7713b1edbc | 5155 | /** Peripheral LPTMR0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5156 | #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5157 | /** Peripheral LPTMR1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5158 | #define LPTMR1_BASE (0x40044000u) |
AnnaBridge | 171:3a7713b1edbc | 5159 | /** Peripheral LPTMR1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5160 | #define LPTMR1 ((LPTMR_Type *)LPTMR1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5161 | /** Array initializer of LPTMR peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5162 | #define LPTMR_BASE_ADDRS { LPTMR0_BASE, LPTMR1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5163 | /** Array initializer of LPTMR peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5164 | #define LPTMR_BASE_PTRS { LPTMR0, LPTMR1 } |
AnnaBridge | 171:3a7713b1edbc | 5165 | /** Interrupt vectors for the LPTMR peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 5166 | #define LPTMR_IRQS { LPTMR0_IRQn, LPTMR1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5167 | |
AnnaBridge | 171:3a7713b1edbc | 5168 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5169 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5170 | */ /* end of group LPTMR_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5171 | |
AnnaBridge | 171:3a7713b1edbc | 5172 | |
AnnaBridge | 171:3a7713b1edbc | 5173 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5174 | -- LPUART Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5175 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5176 | |
AnnaBridge | 171:3a7713b1edbc | 5177 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5178 | * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5179 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5180 | */ |
AnnaBridge | 171:3a7713b1edbc | 5181 | |
AnnaBridge | 171:3a7713b1edbc | 5182 | /** LPUART - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5183 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5184 | __IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5185 | __IO uint32_t STAT; /**< LPUART Status Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5186 | __IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 5187 | __IO uint32_t DATA; /**< LPUART Data Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 5188 | __IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5189 | __IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 5190 | __IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 5191 | __IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 5192 | } LPUART_Type; |
AnnaBridge | 171:3a7713b1edbc | 5193 | |
AnnaBridge | 171:3a7713b1edbc | 5194 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5195 | -- LPUART Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5196 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5197 | |
AnnaBridge | 171:3a7713b1edbc | 5198 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5199 | * @addtogroup LPUART_Register_Masks LPUART Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5200 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5201 | */ |
AnnaBridge | 171:3a7713b1edbc | 5202 | |
AnnaBridge | 171:3a7713b1edbc | 5203 | /*! @name BAUD - LPUART Baud Rate Register */ |
AnnaBridge | 171:3a7713b1edbc | 5204 | #define LPUART_BAUD_SBR_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 5205 | #define LPUART_BAUD_SBR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5206 | #define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5207 | #define LPUART_BAUD_SBNS_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 5208 | #define LPUART_BAUD_SBNS_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 5209 | #define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5210 | #define LPUART_BAUD_RXEDGIE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5211 | #define LPUART_BAUD_RXEDGIE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5212 | #define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5213 | #define LPUART_BAUD_LBKDIE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5214 | #define LPUART_BAUD_LBKDIE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5215 | #define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5216 | #define LPUART_BAUD_RESYNCDIS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5217 | #define LPUART_BAUD_RESYNCDIS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5218 | #define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5219 | #define LPUART_BAUD_BOTHEDGE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 5220 | #define LPUART_BAUD_BOTHEDGE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5221 | #define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5222 | #define LPUART_BAUD_MATCFG_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 5223 | #define LPUART_BAUD_MATCFG_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 5224 | #define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5225 | #define LPUART_BAUD_RDMAE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 5226 | #define LPUART_BAUD_RDMAE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 5227 | #define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5228 | #define LPUART_BAUD_TDMAE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5229 | #define LPUART_BAUD_TDMAE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5230 | #define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5231 | #define LPUART_BAUD_OSR_MASK (0x1F000000U) |
AnnaBridge | 171:3a7713b1edbc | 5232 | #define LPUART_BAUD_OSR_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5233 | #define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5234 | #define LPUART_BAUD_M10_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 5235 | #define LPUART_BAUD_M10_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 5236 | #define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5237 | #define LPUART_BAUD_MAEN2_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 5238 | #define LPUART_BAUD_MAEN2_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 5239 | #define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5240 | #define LPUART_BAUD_MAEN1_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5241 | #define LPUART_BAUD_MAEN1_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5242 | #define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5243 | |
AnnaBridge | 171:3a7713b1edbc | 5244 | /*! @name STAT - LPUART Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5245 | #define LPUART_STAT_MA2F_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5246 | #define LPUART_STAT_MA2F_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5247 | #define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5248 | #define LPUART_STAT_MA1F_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5249 | #define LPUART_STAT_MA1F_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5250 | #define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5251 | #define LPUART_STAT_PF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5252 | #define LPUART_STAT_PF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5253 | #define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5254 | #define LPUART_STAT_FE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 5255 | #define LPUART_STAT_FE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5256 | #define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5257 | #define LPUART_STAT_NF_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 5258 | #define LPUART_STAT_NF_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 5259 | #define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5260 | #define LPUART_STAT_OR_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 5261 | #define LPUART_STAT_OR_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 5262 | #define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5263 | #define LPUART_STAT_IDLE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 5264 | #define LPUART_STAT_IDLE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5265 | #define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5266 | #define LPUART_STAT_RDRF_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 5267 | #define LPUART_STAT_RDRF_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 5268 | #define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5269 | #define LPUART_STAT_TC_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 5270 | #define LPUART_STAT_TC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 5271 | #define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5272 | #define LPUART_STAT_TDRE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5273 | #define LPUART_STAT_TDRE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5274 | #define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5275 | #define LPUART_STAT_RAF_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 5276 | #define LPUART_STAT_RAF_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5277 | #define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5278 | #define LPUART_STAT_LBKDE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 5279 | #define LPUART_STAT_LBKDE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 5280 | #define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5281 | #define LPUART_STAT_BRK13_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 5282 | #define LPUART_STAT_BRK13_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 5283 | #define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5284 | #define LPUART_STAT_RWUID_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 5285 | #define LPUART_STAT_RWUID_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 5286 | #define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5287 | #define LPUART_STAT_RXINV_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 5288 | #define LPUART_STAT_RXINV_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 5289 | #define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5290 | #define LPUART_STAT_MSBF_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 5291 | #define LPUART_STAT_MSBF_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 5292 | #define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5293 | #define LPUART_STAT_RXEDGIF_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 5294 | #define LPUART_STAT_RXEDGIF_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 5295 | #define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5296 | #define LPUART_STAT_LBKDIF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5297 | #define LPUART_STAT_LBKDIF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5298 | #define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5299 | |
AnnaBridge | 171:3a7713b1edbc | 5300 | /*! @name CTRL - LPUART Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5301 | #define LPUART_CTRL_PT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5302 | #define LPUART_CTRL_PT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5303 | #define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5304 | #define LPUART_CTRL_PE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5305 | #define LPUART_CTRL_PE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5306 | #define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5307 | #define LPUART_CTRL_ILT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5308 | #define LPUART_CTRL_ILT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5309 | #define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5310 | #define LPUART_CTRL_WAKE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5311 | #define LPUART_CTRL_WAKE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5312 | #define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5313 | #define LPUART_CTRL_M_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5314 | #define LPUART_CTRL_M_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5315 | #define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5316 | #define LPUART_CTRL_RSRC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5317 | #define LPUART_CTRL_RSRC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5318 | #define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5319 | #define LPUART_CTRL_DOZEEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5320 | #define LPUART_CTRL_DOZEEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5321 | #define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5322 | #define LPUART_CTRL_LOOPS_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5323 | #define LPUART_CTRL_LOOPS_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5324 | #define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5325 | #define LPUART_CTRL_IDLECFG_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 5326 | #define LPUART_CTRL_IDLECFG_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5327 | #define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5328 | #define LPUART_CTRL_MA2IE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5329 | #define LPUART_CTRL_MA2IE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5330 | #define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5331 | #define LPUART_CTRL_MA1IE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5332 | #define LPUART_CTRL_MA1IE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5333 | #define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5334 | #define LPUART_CTRL_SBK_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5335 | #define LPUART_CTRL_SBK_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5336 | #define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5337 | #define LPUART_CTRL_RWU_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 5338 | #define LPUART_CTRL_RWU_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5339 | #define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5340 | #define LPUART_CTRL_RE_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 5341 | #define LPUART_CTRL_RE_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 5342 | #define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5343 | #define LPUART_CTRL_TE_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 5344 | #define LPUART_CTRL_TE_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 5345 | #define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5346 | #define LPUART_CTRL_ILIE_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 5347 | #define LPUART_CTRL_ILIE_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5348 | #define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5349 | #define LPUART_CTRL_RIE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 5350 | #define LPUART_CTRL_RIE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 5351 | #define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5352 | #define LPUART_CTRL_TCIE_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 5353 | #define LPUART_CTRL_TCIE_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 5354 | #define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5355 | #define LPUART_CTRL_TIE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5356 | #define LPUART_CTRL_TIE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5357 | #define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5358 | #define LPUART_CTRL_PEIE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 5359 | #define LPUART_CTRL_PEIE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5360 | #define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5361 | #define LPUART_CTRL_FEIE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 5362 | #define LPUART_CTRL_FEIE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 5363 | #define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5364 | #define LPUART_CTRL_NEIE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 5365 | #define LPUART_CTRL_NEIE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 5366 | #define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5367 | #define LPUART_CTRL_ORIE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 5368 | #define LPUART_CTRL_ORIE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 5369 | #define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5370 | #define LPUART_CTRL_TXINV_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 5371 | #define LPUART_CTRL_TXINV_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 5372 | #define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5373 | #define LPUART_CTRL_TXDIR_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 5374 | #define LPUART_CTRL_TXDIR_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 5375 | #define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5376 | #define LPUART_CTRL_R9T8_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 5377 | #define LPUART_CTRL_R9T8_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 5378 | #define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5379 | #define LPUART_CTRL_R8T9_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5380 | #define LPUART_CTRL_R8T9_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5381 | #define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5382 | |
AnnaBridge | 171:3a7713b1edbc | 5383 | /*! @name DATA - LPUART Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 5384 | #define LPUART_DATA_R0T0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5385 | #define LPUART_DATA_R0T0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5386 | #define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5387 | #define LPUART_DATA_R1T1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5388 | #define LPUART_DATA_R1T1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5389 | #define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5390 | #define LPUART_DATA_R2T2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5391 | #define LPUART_DATA_R2T2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5392 | #define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5393 | #define LPUART_DATA_R3T3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5394 | #define LPUART_DATA_R3T3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5395 | #define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5396 | #define LPUART_DATA_R4T4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5397 | #define LPUART_DATA_R4T4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5398 | #define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5399 | #define LPUART_DATA_R5T5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5400 | #define LPUART_DATA_R5T5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5401 | #define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5402 | #define LPUART_DATA_R6T6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5403 | #define LPUART_DATA_R6T6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5404 | #define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5405 | #define LPUART_DATA_R7T7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5406 | #define LPUART_DATA_R7T7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5407 | #define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5408 | #define LPUART_DATA_R8T8_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5409 | #define LPUART_DATA_R8T8_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5410 | #define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5411 | #define LPUART_DATA_R9T9_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5412 | #define LPUART_DATA_R9T9_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5413 | #define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5414 | #define LPUART_DATA_IDLINE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 5415 | #define LPUART_DATA_IDLINE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 5416 | #define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5417 | #define LPUART_DATA_RXEMPT_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 5418 | #define LPUART_DATA_RXEMPT_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5419 | #define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5420 | #define LPUART_DATA_FRETSC_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 5421 | #define LPUART_DATA_FRETSC_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 5422 | #define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5423 | #define LPUART_DATA_PARITYE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5424 | #define LPUART_DATA_PARITYE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5425 | #define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5426 | #define LPUART_DATA_NOISY_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5427 | #define LPUART_DATA_NOISY_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5428 | #define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5429 | |
AnnaBridge | 171:3a7713b1edbc | 5430 | /*! @name MATCH - LPUART Match Address Register */ |
AnnaBridge | 171:3a7713b1edbc | 5431 | #define LPUART_MATCH_MA1_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 5432 | #define LPUART_MATCH_MA1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5433 | #define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5434 | #define LPUART_MATCH_MA2_MASK (0x3FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5435 | #define LPUART_MATCH_MA2_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5436 | #define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5437 | |
AnnaBridge | 171:3a7713b1edbc | 5438 | /*! @name MODIR - LPUART Modem IrDA Register */ |
AnnaBridge | 171:3a7713b1edbc | 5439 | #define LPUART_MODIR_TXCTSE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5440 | #define LPUART_MODIR_TXCTSE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5441 | #define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5442 | #define LPUART_MODIR_TXRTSE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5443 | #define LPUART_MODIR_TXRTSE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5444 | #define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5445 | #define LPUART_MODIR_TXRTSPOL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5446 | #define LPUART_MODIR_TXRTSPOL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5447 | #define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5448 | #define LPUART_MODIR_RXRTSE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5449 | #define LPUART_MODIR_RXRTSE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5450 | #define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5451 | #define LPUART_MODIR_TXCTSC_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5452 | #define LPUART_MODIR_TXCTSC_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5453 | #define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5454 | #define LPUART_MODIR_TXCTSSRC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5455 | #define LPUART_MODIR_TXCTSSRC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5456 | #define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5457 | #define LPUART_MODIR_RTSWATER_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 5458 | #define LPUART_MODIR_RTSWATER_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5459 | #define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5460 | #define LPUART_MODIR_TNP_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 5461 | #define LPUART_MODIR_TNP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5462 | #define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5463 | #define LPUART_MODIR_IREN_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 5464 | #define LPUART_MODIR_IREN_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 5465 | #define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5466 | |
AnnaBridge | 171:3a7713b1edbc | 5467 | /*! @name FIFO - LPUART FIFO Register */ |
AnnaBridge | 171:3a7713b1edbc | 5468 | #define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 5469 | #define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5470 | #define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5471 | #define LPUART_FIFO_RXFE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5472 | #define LPUART_FIFO_RXFE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5473 | #define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5474 | #define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 5475 | #define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5476 | #define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5477 | #define LPUART_FIFO_TXFE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5478 | #define LPUART_FIFO_TXFE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5479 | #define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5480 | #define LPUART_FIFO_RXUFE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5481 | #define LPUART_FIFO_RXUFE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5482 | #define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5483 | #define LPUART_FIFO_TXOFE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5484 | #define LPUART_FIFO_TXOFE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5485 | #define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5486 | #define LPUART_FIFO_RXIDEN_MASK (0x1C00U) |
AnnaBridge | 171:3a7713b1edbc | 5487 | #define LPUART_FIFO_RXIDEN_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 5488 | #define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5489 | #define LPUART_FIFO_RXFLUSH_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5490 | #define LPUART_FIFO_RXFLUSH_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5491 | #define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5492 | #define LPUART_FIFO_TXFLUSH_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5493 | #define LPUART_FIFO_TXFLUSH_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5494 | #define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5495 | #define LPUART_FIFO_RXUF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5496 | #define LPUART_FIFO_RXUF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5497 | #define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5498 | #define LPUART_FIFO_TXOF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 5499 | #define LPUART_FIFO_TXOF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5500 | #define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5501 | #define LPUART_FIFO_RXEMPT_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 5502 | #define LPUART_FIFO_RXEMPT_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 5503 | #define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5504 | #define LPUART_FIFO_TXEMPT_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5505 | #define LPUART_FIFO_TXEMPT_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5506 | #define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5507 | |
AnnaBridge | 171:3a7713b1edbc | 5508 | /*! @name WATER - LPUART Watermark Register */ |
AnnaBridge | 171:3a7713b1edbc | 5509 | #define LPUART_WATER_TXWATER_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5510 | #define LPUART_WATER_TXWATER_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5511 | #define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5512 | #define LPUART_WATER_TXCOUNT_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 5513 | #define LPUART_WATER_TXCOUNT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5514 | #define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5515 | #define LPUART_WATER_RXWATER_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5516 | #define LPUART_WATER_RXWATER_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5517 | #define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5518 | #define LPUART_WATER_RXCOUNT_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 5519 | #define LPUART_WATER_RXCOUNT_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5520 | #define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5521 | |
AnnaBridge | 171:3a7713b1edbc | 5522 | |
AnnaBridge | 171:3a7713b1edbc | 5523 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5524 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5525 | */ /* end of group LPUART_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 5526 | |
AnnaBridge | 171:3a7713b1edbc | 5527 | |
AnnaBridge | 171:3a7713b1edbc | 5528 | /* LPUART - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5529 | /** Peripheral LPUART0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5530 | #define LPUART0_BASE (0x40054000u) |
AnnaBridge | 171:3a7713b1edbc | 5531 | /** Peripheral LPUART0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5532 | #define LPUART0 ((LPUART_Type *)LPUART0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5533 | /** Peripheral LPUART1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5534 | #define LPUART1_BASE (0x40055000u) |
AnnaBridge | 171:3a7713b1edbc | 5535 | /** Peripheral LPUART1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5536 | #define LPUART1 ((LPUART_Type *)LPUART1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5537 | /** Peripheral LPUART2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 5538 | #define LPUART2_BASE (0x40056000u) |
AnnaBridge | 171:3a7713b1edbc | 5539 | /** Peripheral LPUART2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 5540 | #define LPUART2 ((LPUART_Type *)LPUART2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 5541 | /** Array initializer of LPUART peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 5542 | #define LPUART_BASE_ADDRS { LPUART0_BASE, LPUART1_BASE, LPUART2_BASE } |
AnnaBridge | 171:3a7713b1edbc | 5543 | /** Array initializer of LPUART peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 5544 | #define LPUART_BASE_PTRS { LPUART0, LPUART1, LPUART2 } |
AnnaBridge | 171:3a7713b1edbc | 5545 | /** Interrupt vectors for the LPUART peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 5546 | #define LPUART_RX_TX_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5547 | #define LPUART_ERR_IRQS { LPUART0_IRQn, LPUART1_IRQn, LPUART2_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 5548 | |
AnnaBridge | 171:3a7713b1edbc | 5549 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5550 | * @} |
AnnaBridge | 171:3a7713b1edbc | 5551 | */ /* end of group LPUART_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 5552 | |
AnnaBridge | 171:3a7713b1edbc | 5553 | |
AnnaBridge | 171:3a7713b1edbc | 5554 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5555 | -- LTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5556 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5557 | |
AnnaBridge | 171:3a7713b1edbc | 5558 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5559 | * @addtogroup LTC_Peripheral_Access_Layer LTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 5560 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5561 | */ |
AnnaBridge | 171:3a7713b1edbc | 5562 | |
AnnaBridge | 171:3a7713b1edbc | 5563 | /** LTC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 5564 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 5565 | union { /* offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5566 | __IO uint32_t MD; /**< LTC Mode Register (non-PKHA/non-RNG use), offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5567 | __IO uint32_t MDPK; /**< LTC Mode Register (PublicKey), offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 5568 | }; |
AnnaBridge | 171:3a7713b1edbc | 5569 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 5570 | __IO uint32_t KS; /**< LTC Key Size Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 5571 | uint8_t RESERVED_1[4]; |
AnnaBridge | 171:3a7713b1edbc | 5572 | __IO uint32_t DS; /**< LTC Data Size Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 5573 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 5574 | __IO uint32_t ICVS; /**< LTC ICV Size Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 5575 | uint8_t RESERVED_3[20]; |
AnnaBridge | 171:3a7713b1edbc | 5576 | __IO uint32_t COM; /**< LTC Command Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 5577 | __IO uint32_t CTL; /**< LTC Control Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 5578 | uint8_t RESERVED_4[8]; |
AnnaBridge | 171:3a7713b1edbc | 5579 | __IO uint32_t CW; /**< LTC Clear Written Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 5580 | uint8_t RESERVED_5[4]; |
AnnaBridge | 171:3a7713b1edbc | 5581 | __IO uint32_t STA; /**< LTC Status Register, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 5582 | __I uint32_t ESTA; /**< LTC Error Status Register, offset: 0x4C */ |
AnnaBridge | 171:3a7713b1edbc | 5583 | uint8_t RESERVED_6[8]; |
AnnaBridge | 171:3a7713b1edbc | 5584 | __IO uint32_t AADSZ; /**< LTC AAD Size Register, offset: 0x58 */ |
AnnaBridge | 171:3a7713b1edbc | 5585 | uint8_t RESERVED_7[4]; |
AnnaBridge | 171:3a7713b1edbc | 5586 | __IO uint32_t IVSZ; /**< LTC IV Size Register, offset: 0x60 */ |
AnnaBridge | 171:3a7713b1edbc | 5587 | uint8_t RESERVED_8[4]; |
AnnaBridge | 171:3a7713b1edbc | 5588 | __O uint32_t DPAMS; /**< LTC DPA Mask Seed Register, offset: 0x68 */ |
AnnaBridge | 171:3a7713b1edbc | 5589 | uint8_t RESERVED_9[20]; |
AnnaBridge | 171:3a7713b1edbc | 5590 | __IO uint32_t PKASZ; /**< LTC PKHA A Size Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 5591 | uint8_t RESERVED_10[4]; |
AnnaBridge | 171:3a7713b1edbc | 5592 | __IO uint32_t PKBSZ; /**< LTC PKHA B Size Register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 5593 | uint8_t RESERVED_11[4]; |
AnnaBridge | 171:3a7713b1edbc | 5594 | __IO uint32_t PKNSZ; /**< LTC PKHA N Size Register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 5595 | uint8_t RESERVED_12[4]; |
AnnaBridge | 171:3a7713b1edbc | 5596 | __IO uint32_t PKESZ; /**< LTC PKHA E Size Register, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 5597 | uint8_t RESERVED_13[100]; |
AnnaBridge | 171:3a7713b1edbc | 5598 | __IO uint32_t CTX[16]; /**< LTC Context Register, array offset: 0x100, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5599 | uint8_t RESERVED_14[192]; |
AnnaBridge | 171:3a7713b1edbc | 5600 | __IO uint32_t KEY[8]; /**< LTC Key Registers, array offset: 0x200, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5601 | uint8_t RESERVED_15[720]; |
AnnaBridge | 171:3a7713b1edbc | 5602 | __I uint32_t VID1; /**< LTC Version ID Register, offset: 0x4F0 */ |
AnnaBridge | 171:3a7713b1edbc | 5603 | __I uint32_t VID2; /**< LTC Version ID 2 Register, offset: 0x4F4 */ |
AnnaBridge | 171:3a7713b1edbc | 5604 | __I uint32_t CHAVID; /**< LTC CHA Version ID Register, offset: 0x4F8 */ |
AnnaBridge | 171:3a7713b1edbc | 5605 | uint8_t RESERVED_16[708]; |
AnnaBridge | 171:3a7713b1edbc | 5606 | __I uint32_t FIFOSTA; /**< LTC FIFO Status Register, offset: 0x7C0 */ |
AnnaBridge | 171:3a7713b1edbc | 5607 | uint8_t RESERVED_17[28]; |
AnnaBridge | 171:3a7713b1edbc | 5608 | __O uint32_t IFIFO; /**< LTC Input Data FIFO, offset: 0x7E0 */ |
AnnaBridge | 171:3a7713b1edbc | 5609 | uint8_t RESERVED_18[12]; |
AnnaBridge | 171:3a7713b1edbc | 5610 | __I uint32_t OFIFO; /**< LTC Output Data FIFO, offset: 0x7F0 */ |
AnnaBridge | 171:3a7713b1edbc | 5611 | uint8_t RESERVED_19[12]; |
AnnaBridge | 171:3a7713b1edbc | 5612 | union { /* offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 5613 | __IO uint32_t PKA[64]; /**< LTC PKHA A 0 Register..LTC PKHA A 63 Register, array offset: 0x800, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5614 | struct { /* offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 5615 | __IO uint32_t PKA0[16]; /**< LTC PKHA A0 0 Register..LTC PKHA A0 15 Register, array offset: 0x800, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5616 | __IO uint32_t PKA1[16]; /**< LTC PKHA A1 0 Register..LTC PKHA A1 15 Register, array offset: 0x840, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5617 | __IO uint32_t PKA2[16]; /**< LTC PKHA A2 0 Register..LTC PKHA A2 15 Register, array offset: 0x880, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5618 | __IO uint32_t PKA3[16]; /**< LTC PKHA A3 0 Register..LTC PKHA A3 15 Register, array offset: 0x8C0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5619 | } PKA_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 5620 | }; |
AnnaBridge | 171:3a7713b1edbc | 5621 | uint8_t RESERVED_20[256]; |
AnnaBridge | 171:3a7713b1edbc | 5622 | union { /* offset: 0xA00 */ |
AnnaBridge | 171:3a7713b1edbc | 5623 | __IO uint32_t PKB[64]; /**< LTC PKHA B 0 Register..LTC PKHA B 63 Register, array offset: 0xA00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5624 | struct { /* offset: 0xA00 */ |
AnnaBridge | 171:3a7713b1edbc | 5625 | __IO uint32_t PKB0[16]; /**< LTC PKHA B0 0 Register..LTC PKHA B0 15 Register, array offset: 0xA00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5626 | __IO uint32_t PKB1[16]; /**< LTC PKHA B1 0 Register..LTC PKHA B1 15 Register, array offset: 0xA40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5627 | __IO uint32_t PKB2[16]; /**< LTC PKHA B2 0 Register..LTC PKHA B2 15 Register, array offset: 0xA80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5628 | __IO uint32_t PKB3[16]; /**< LTC PKHA B3 0 Register..LTC PKHA B3 15 Register, array offset: 0xAC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5629 | } PKB_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 5630 | }; |
AnnaBridge | 171:3a7713b1edbc | 5631 | uint8_t RESERVED_21[256]; |
AnnaBridge | 171:3a7713b1edbc | 5632 | union { /* offset: 0xC00 */ |
AnnaBridge | 171:3a7713b1edbc | 5633 | __IO uint32_t PKN[64]; /**< LTC PKHA N 0 Register..LTC PKHA N 63 Register, array offset: 0xC00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5634 | struct { /* offset: 0xC00 */ |
AnnaBridge | 171:3a7713b1edbc | 5635 | __IO uint32_t PKN0[16]; /**< LTC PKHA N0 0 Register..LTC PKHA N0 15 Register, array offset: 0xC00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5636 | __IO uint32_t PKN1[16]; /**< LTC PKHA N1 0 Register..LTC PKHA N1 15 Register, array offset: 0xC40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5637 | __IO uint32_t PKN2[16]; /**< LTC PKHA N2 0 Register..LTC PKHA N2 15 Register, array offset: 0xC80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5638 | __IO uint32_t PKN3[16]; /**< LTC PKHA N3 0 Register..LTC PKHA N3 15 Register, array offset: 0xCC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5639 | } PKN_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 5640 | }; |
AnnaBridge | 171:3a7713b1edbc | 5641 | uint8_t RESERVED_22[256]; |
AnnaBridge | 171:3a7713b1edbc | 5642 | union { /* offset: 0xE00 */ |
AnnaBridge | 171:3a7713b1edbc | 5643 | __IO uint32_t PKE[64]; /**< LTC PKHA E 0 Register..LTC PKHA E 63 Register, array offset: 0xE00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5644 | struct { /* offset: 0xE00 */ |
AnnaBridge | 171:3a7713b1edbc | 5645 | __IO uint32_t PKE0[16]; /**< LTC PKHA E0 0 Register..LTC PKHA E0 15 Register, array offset: 0xE00, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5646 | __IO uint32_t PKE1[16]; /**< LTC PKHA E1 0 Register..LTC PKHA E1 15 Register, array offset: 0xE40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5647 | __IO uint32_t PKE2[16]; /**< LTC PKHA E2 0 Register..LTC PKHA E2 15 Register, array offset: 0xE80, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5648 | __IO uint32_t PKE3[16]; /**< LTC PKHA E3 0 Register..LTC PKHA E3 15 Register, array offset: 0xEC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 5649 | } PKE_SHORT; |
AnnaBridge | 171:3a7713b1edbc | 5650 | }; |
AnnaBridge | 171:3a7713b1edbc | 5651 | } LTC_Type; |
AnnaBridge | 171:3a7713b1edbc | 5652 | |
AnnaBridge | 171:3a7713b1edbc | 5653 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 5654 | -- LTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5655 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 5656 | |
AnnaBridge | 171:3a7713b1edbc | 5657 | /*! |
AnnaBridge | 171:3a7713b1edbc | 5658 | * @addtogroup LTC_Register_Masks LTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 5659 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 5660 | */ |
AnnaBridge | 171:3a7713b1edbc | 5661 | |
AnnaBridge | 171:3a7713b1edbc | 5662 | /*! @name MD - LTC Mode Register (non-PKHA/non-RNG use) */ |
AnnaBridge | 171:3a7713b1edbc | 5663 | #define LTC_MD_ENC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5664 | #define LTC_MD_ENC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5665 | #define LTC_MD_ENC(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ENC_SHIFT)) & LTC_MD_ENC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5666 | #define LTC_MD_ICV_TEST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5667 | #define LTC_MD_ICV_TEST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5668 | #define LTC_MD_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ICV_TEST_SHIFT)) & LTC_MD_ICV_TEST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5669 | #define LTC_MD_AS_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 5670 | #define LTC_MD_AS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5671 | #define LTC_MD_AS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AS_SHIFT)) & LTC_MD_AS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5672 | #define LTC_MD_AAI_MASK (0x1FF0U) |
AnnaBridge | 171:3a7713b1edbc | 5673 | #define LTC_MD_AAI_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5674 | #define LTC_MD_AAI(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_AAI_SHIFT)) & LTC_MD_AAI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5675 | #define LTC_MD_ALG_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5676 | #define LTC_MD_ALG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5677 | #define LTC_MD_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MD_ALG_SHIFT)) & LTC_MD_ALG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5678 | |
AnnaBridge | 171:3a7713b1edbc | 5679 | /*! @name MDPK - LTC Mode Register (PublicKey) */ |
AnnaBridge | 171:3a7713b1edbc | 5680 | #define LTC_MDPK_PKHA_MODE_LS_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5681 | #define LTC_MDPK_PKHA_MODE_LS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5682 | #define LTC_MDPK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_LS_SHIFT)) & LTC_MDPK_PKHA_MODE_LS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5683 | #define LTC_MDPK_PKHA_MODE_MS_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5684 | #define LTC_MDPK_PKHA_MODE_MS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5685 | #define LTC_MDPK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_PKHA_MODE_MS_SHIFT)) & LTC_MDPK_PKHA_MODE_MS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5686 | #define LTC_MDPK_ALG_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 5687 | #define LTC_MDPK_ALG_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5688 | #define LTC_MDPK_ALG(x) (((uint32_t)(((uint32_t)(x)) << LTC_MDPK_ALG_SHIFT)) & LTC_MDPK_ALG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5689 | |
AnnaBridge | 171:3a7713b1edbc | 5690 | /*! @name KS - LTC Key Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5691 | #define LTC_KS_KS_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 5692 | #define LTC_KS_KS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5693 | #define LTC_KS_KS(x) (((uint32_t)(((uint32_t)(x)) << LTC_KS_KS_SHIFT)) & LTC_KS_KS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5694 | |
AnnaBridge | 171:3a7713b1edbc | 5695 | /*! @name DS - LTC Data Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5696 | #define LTC_DS_DS_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5697 | #define LTC_DS_DS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5698 | #define LTC_DS_DS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DS_DS_SHIFT)) & LTC_DS_DS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5699 | |
AnnaBridge | 171:3a7713b1edbc | 5700 | /*! @name ICVS - LTC ICV Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5701 | #define LTC_ICVS_ICVS_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 5702 | #define LTC_ICVS_ICVS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5703 | #define LTC_ICVS_ICVS(x) (((uint32_t)(((uint32_t)(x)) << LTC_ICVS_ICVS_SHIFT)) & LTC_ICVS_ICVS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5704 | |
AnnaBridge | 171:3a7713b1edbc | 5705 | /*! @name COM - LTC Command Register */ |
AnnaBridge | 171:3a7713b1edbc | 5706 | #define LTC_COM_ALL_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5707 | #define LTC_COM_ALL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5708 | #define LTC_COM_ALL(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_ALL_SHIFT)) & LTC_COM_ALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5709 | #define LTC_COM_AES_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5710 | #define LTC_COM_AES_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5711 | #define LTC_COM_AES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_AES_SHIFT)) & LTC_COM_AES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5712 | #define LTC_COM_DES_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5713 | #define LTC_COM_DES_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5714 | #define LTC_COM_DES(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_DES_SHIFT)) & LTC_COM_DES_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5715 | #define LTC_COM_PK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5716 | #define LTC_COM_PK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5717 | #define LTC_COM_PK(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_PK_SHIFT)) & LTC_COM_PK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5718 | #define LTC_COM_MD_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5719 | #define LTC_COM_MD_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5720 | #define LTC_COM_MD(x) (((uint32_t)(((uint32_t)(x)) << LTC_COM_MD_SHIFT)) & LTC_COM_MD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5721 | |
AnnaBridge | 171:3a7713b1edbc | 5722 | /*! @name CTL - LTC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 5723 | #define LTC_CTL_IM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5724 | #define LTC_CTL_IM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5725 | #define LTC_CTL_IM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IM_SHIFT)) & LTC_CTL_IM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5726 | #define LTC_CTL_PDE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 5727 | #define LTC_CTL_PDE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5728 | #define LTC_CTL_PDE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_PDE_SHIFT)) & LTC_CTL_PDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5729 | #define LTC_CTL_IFE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 5730 | #define LTC_CTL_IFE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5731 | #define LTC_CTL_IFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFE_SHIFT)) & LTC_CTL_IFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5732 | #define LTC_CTL_IFR_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 5733 | #define LTC_CTL_IFR_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 5734 | #define LTC_CTL_IFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFR_SHIFT)) & LTC_CTL_IFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5735 | #define LTC_CTL_OFE_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 5736 | #define LTC_CTL_OFE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5737 | #define LTC_CTL_OFE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFE_SHIFT)) & LTC_CTL_OFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5738 | #define LTC_CTL_OFR_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 5739 | #define LTC_CTL_OFR_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 5740 | #define LTC_CTL_OFR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFR_SHIFT)) & LTC_CTL_OFR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5741 | #define LTC_CTL_IFS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5742 | #define LTC_CTL_IFS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5743 | #define LTC_CTL_IFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_IFS_SHIFT)) & LTC_CTL_IFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5744 | #define LTC_CTL_OFS_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 5745 | #define LTC_CTL_OFS_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 5746 | #define LTC_CTL_OFS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_OFS_SHIFT)) & LTC_CTL_OFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5747 | #define LTC_CTL_KIS_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 5748 | #define LTC_CTL_KIS_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5749 | #define LTC_CTL_KIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KIS_SHIFT)) & LTC_CTL_KIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5750 | #define LTC_CTL_KOS_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 5751 | #define LTC_CTL_KOS_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 5752 | #define LTC_CTL_KOS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KOS_SHIFT)) & LTC_CTL_KOS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5753 | #define LTC_CTL_CIS_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 5754 | #define LTC_CTL_CIS_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 5755 | #define LTC_CTL_CIS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_CIS_SHIFT)) & LTC_CTL_CIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5756 | #define LTC_CTL_COS_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 5757 | #define LTC_CTL_COS_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 5758 | #define LTC_CTL_COS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_COS_SHIFT)) & LTC_CTL_COS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5759 | #define LTC_CTL_KAL_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5760 | #define LTC_CTL_KAL_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5761 | #define LTC_CTL_KAL(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTL_KAL_SHIFT)) & LTC_CTL_KAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5762 | |
AnnaBridge | 171:3a7713b1edbc | 5763 | /*! @name CW - LTC Clear Written Register */ |
AnnaBridge | 171:3a7713b1edbc | 5764 | #define LTC_CW_CM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 5765 | #define LTC_CW_CM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5766 | #define LTC_CW_CM(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CM_SHIFT)) & LTC_CW_CM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5767 | #define LTC_CW_CDS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5768 | #define LTC_CW_CDS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5769 | #define LTC_CW_CDS(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CDS_SHIFT)) & LTC_CW_CDS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5770 | #define LTC_CW_CICV_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 5771 | #define LTC_CW_CICV_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 5772 | #define LTC_CW_CICV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CICV_SHIFT)) & LTC_CW_CICV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5773 | #define LTC_CW_CCR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 5774 | #define LTC_CW_CCR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 5775 | #define LTC_CW_CCR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CCR_SHIFT)) & LTC_CW_CCR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5776 | #define LTC_CW_CKR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5777 | #define LTC_CW_CKR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5778 | #define LTC_CW_CKR(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CKR_SHIFT)) & LTC_CW_CKR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5779 | #define LTC_CW_CPKA_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 5780 | #define LTC_CW_CPKA_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5781 | #define LTC_CW_CPKA(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKA_SHIFT)) & LTC_CW_CPKA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5782 | #define LTC_CW_CPKB_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 5783 | #define LTC_CW_CPKB_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 5784 | #define LTC_CW_CPKB(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKB_SHIFT)) & LTC_CW_CPKB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5785 | #define LTC_CW_CPKN_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 5786 | #define LTC_CW_CPKN_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 5787 | #define LTC_CW_CPKN(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKN_SHIFT)) & LTC_CW_CPKN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5788 | #define LTC_CW_CPKE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5789 | #define LTC_CW_CPKE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5790 | #define LTC_CW_CPKE(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CPKE_SHIFT)) & LTC_CW_CPKE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5791 | #define LTC_CW_COF_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 5792 | #define LTC_CW_COF_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 5793 | #define LTC_CW_COF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_COF_SHIFT)) & LTC_CW_COF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5794 | #define LTC_CW_CIF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5795 | #define LTC_CW_CIF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5796 | #define LTC_CW_CIF(x) (((uint32_t)(((uint32_t)(x)) << LTC_CW_CIF_SHIFT)) & LTC_CW_CIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5797 | |
AnnaBridge | 171:3a7713b1edbc | 5798 | /*! @name STA - LTC Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5799 | #define LTC_STA_AB_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 5800 | #define LTC_STA_AB_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 5801 | #define LTC_STA_AB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_AB_SHIFT)) & LTC_STA_AB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5802 | #define LTC_STA_DB_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 5803 | #define LTC_STA_DB_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 5804 | #define LTC_STA_DB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DB_SHIFT)) & LTC_STA_DB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5805 | #define LTC_STA_PB_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 5806 | #define LTC_STA_PB_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 5807 | #define LTC_STA_PB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PB_SHIFT)) & LTC_STA_PB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5808 | #define LTC_STA_MB_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 5809 | #define LTC_STA_MB_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 5810 | #define LTC_STA_MB(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_MB_SHIFT)) & LTC_STA_MB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5811 | #define LTC_STA_DI_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 5812 | #define LTC_STA_DI_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5813 | #define LTC_STA_DI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DI_SHIFT)) & LTC_STA_DI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5814 | #define LTC_STA_EI_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 5815 | #define LTC_STA_EI_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5816 | #define LTC_STA_EI(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_EI_SHIFT)) & LTC_STA_EI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5817 | #define LTC_STA_DPARRN_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 5818 | #define LTC_STA_DPARRN_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5819 | #define LTC_STA_DPARRN(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_DPARRN_SHIFT)) & LTC_STA_DPARRN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5820 | #define LTC_STA_PKP_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 5821 | #define LTC_STA_PKP_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 5822 | #define LTC_STA_PKP(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKP_SHIFT)) & LTC_STA_PKP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5823 | #define LTC_STA_PKO_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 5824 | #define LTC_STA_PKO_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 5825 | #define LTC_STA_PKO(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKO_SHIFT)) & LTC_STA_PKO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5826 | #define LTC_STA_PKZ_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 5827 | #define LTC_STA_PKZ_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 5828 | #define LTC_STA_PKZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_STA_PKZ_SHIFT)) & LTC_STA_PKZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5829 | |
AnnaBridge | 171:3a7713b1edbc | 5830 | /*! @name ESTA - LTC Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5831 | #define LTC_ESTA_ERRID1_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 5832 | #define LTC_ESTA_ERRID1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5833 | #define LTC_ESTA_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_ERRID1_SHIFT)) & LTC_ESTA_ERRID1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5834 | #define LTC_ESTA_CL1_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 5835 | #define LTC_ESTA_CL1_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5836 | #define LTC_ESTA_CL1(x) (((uint32_t)(((uint32_t)(x)) << LTC_ESTA_CL1_SHIFT)) & LTC_ESTA_CL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5837 | |
AnnaBridge | 171:3a7713b1edbc | 5838 | /*! @name AADSZ - LTC AAD Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5839 | #define LTC_AADSZ_AADSZ_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 5840 | #define LTC_AADSZ_AADSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5841 | #define LTC_AADSZ_AADSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AADSZ_SHIFT)) & LTC_AADSZ_AADSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5842 | #define LTC_AADSZ_AL_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5843 | #define LTC_AADSZ_AL_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5844 | #define LTC_AADSZ_AL(x) (((uint32_t)(((uint32_t)(x)) << LTC_AADSZ_AL_SHIFT)) & LTC_AADSZ_AL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5845 | |
AnnaBridge | 171:3a7713b1edbc | 5846 | /*! @name IVSZ - LTC IV Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5847 | #define LTC_IVSZ_IVSZ_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 5848 | #define LTC_IVSZ_IVSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5849 | #define LTC_IVSZ_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IVSZ_SHIFT)) & LTC_IVSZ_IVSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5850 | #define LTC_IVSZ_IL_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5851 | #define LTC_IVSZ_IL_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5852 | #define LTC_IVSZ_IL(x) (((uint32_t)(((uint32_t)(x)) << LTC_IVSZ_IL_SHIFT)) & LTC_IVSZ_IL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5853 | |
AnnaBridge | 171:3a7713b1edbc | 5854 | /*! @name DPAMS - LTC DPA Mask Seed Register */ |
AnnaBridge | 171:3a7713b1edbc | 5855 | #define LTC_DPAMS_DPAMS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5856 | #define LTC_DPAMS_DPAMS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5857 | #define LTC_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << LTC_DPAMS_DPAMS_SHIFT)) & LTC_DPAMS_DPAMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5858 | |
AnnaBridge | 171:3a7713b1edbc | 5859 | /*! @name PKASZ - LTC PKHA A Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5860 | #define LTC_PKASZ_PKASZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 5861 | #define LTC_PKASZ_PKASZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5862 | #define LTC_PKASZ_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKASZ_PKASZ_SHIFT)) & LTC_PKASZ_PKASZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5863 | |
AnnaBridge | 171:3a7713b1edbc | 5864 | /*! @name PKBSZ - LTC PKHA B Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5865 | #define LTC_PKBSZ_PKBSZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 5866 | #define LTC_PKBSZ_PKBSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5867 | #define LTC_PKBSZ_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKBSZ_PKBSZ_SHIFT)) & LTC_PKBSZ_PKBSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5868 | |
AnnaBridge | 171:3a7713b1edbc | 5869 | /*! @name PKNSZ - LTC PKHA N Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5870 | #define LTC_PKNSZ_PKNSZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 5871 | #define LTC_PKNSZ_PKNSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5872 | #define LTC_PKNSZ_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKNSZ_PKNSZ_SHIFT)) & LTC_PKNSZ_PKNSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5873 | |
AnnaBridge | 171:3a7713b1edbc | 5874 | /*! @name PKESZ - LTC PKHA E Size Register */ |
AnnaBridge | 171:3a7713b1edbc | 5875 | #define LTC_PKESZ_PKESZ_MASK (0x1FFU) |
AnnaBridge | 171:3a7713b1edbc | 5876 | #define LTC_PKESZ_PKESZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5877 | #define LTC_PKESZ_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKESZ_PKESZ_SHIFT)) & LTC_PKESZ_PKESZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5878 | |
AnnaBridge | 171:3a7713b1edbc | 5879 | /*! @name CTX - LTC Context Register */ |
AnnaBridge | 171:3a7713b1edbc | 5880 | #define LTC_CTX_CTX_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5881 | #define LTC_CTX_CTX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5882 | #define LTC_CTX_CTX(x) (((uint32_t)(((uint32_t)(x)) << LTC_CTX_CTX_SHIFT)) & LTC_CTX_CTX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5883 | |
AnnaBridge | 171:3a7713b1edbc | 5884 | /* The count of LTC_CTX */ |
AnnaBridge | 171:3a7713b1edbc | 5885 | #define LTC_CTX_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5886 | |
AnnaBridge | 171:3a7713b1edbc | 5887 | /*! @name KEY - LTC Key Registers */ |
AnnaBridge | 171:3a7713b1edbc | 5888 | #define LTC_KEY_KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5889 | #define LTC_KEY_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5890 | #define LTC_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << LTC_KEY_KEY_SHIFT)) & LTC_KEY_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5891 | |
AnnaBridge | 171:3a7713b1edbc | 5892 | /* The count of LTC_KEY */ |
AnnaBridge | 171:3a7713b1edbc | 5893 | #define LTC_KEY_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5894 | |
AnnaBridge | 171:3a7713b1edbc | 5895 | /*! @name VID1 - LTC Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 5896 | #define LTC_VID1_MIN_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5897 | #define LTC_VID1_MIN_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5898 | #define LTC_VID1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MIN_REV_SHIFT)) & LTC_VID1_MIN_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5899 | #define LTC_VID1_MAJ_REV_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 5900 | #define LTC_VID1_MAJ_REV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5901 | #define LTC_VID1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_MAJ_REV_SHIFT)) & LTC_VID1_MAJ_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5902 | #define LTC_VID1_IP_ID_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5903 | #define LTC_VID1_IP_ID_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5904 | #define LTC_VID1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID1_IP_ID_SHIFT)) & LTC_VID1_IP_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5905 | |
AnnaBridge | 171:3a7713b1edbc | 5906 | /*! @name VID2 - LTC Version ID 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 5907 | #define LTC_VID2_ECO_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 5908 | #define LTC_VID2_ECO_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5909 | #define LTC_VID2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ECO_REV_SHIFT)) & LTC_VID2_ECO_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5910 | #define LTC_VID2_ARCH_ERA_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 5911 | #define LTC_VID2_ARCH_ERA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5912 | #define LTC_VID2_ARCH_ERA(x) (((uint32_t)(((uint32_t)(x)) << LTC_VID2_ARCH_ERA_SHIFT)) & LTC_VID2_ARCH_ERA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5913 | |
AnnaBridge | 171:3a7713b1edbc | 5914 | /*! @name CHAVID - LTC CHA Version ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 5915 | #define LTC_CHAVID_AESREV_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 5916 | #define LTC_CHAVID_AESREV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5917 | #define LTC_CHAVID_AESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESREV_SHIFT)) & LTC_CHAVID_AESREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5918 | #define LTC_CHAVID_AESVID_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 5919 | #define LTC_CHAVID_AESVID_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 5920 | #define LTC_CHAVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_AESVID_SHIFT)) & LTC_CHAVID_AESVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5921 | #define LTC_CHAVID_DESREV_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 5922 | #define LTC_CHAVID_DESREV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 5923 | #define LTC_CHAVID_DESREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESREV_SHIFT)) & LTC_CHAVID_DESREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5924 | #define LTC_CHAVID_DESVID_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 5925 | #define LTC_CHAVID_DESVID_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 5926 | #define LTC_CHAVID_DESVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_DESVID_SHIFT)) & LTC_CHAVID_DESVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5927 | #define LTC_CHAVID_PKHAREV_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 5928 | #define LTC_CHAVID_PKHAREV_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5929 | #define LTC_CHAVID_PKHAREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAREV_SHIFT)) & LTC_CHAVID_PKHAREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5930 | #define LTC_CHAVID_PKHAVID_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 5931 | #define LTC_CHAVID_PKHAVID_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 5932 | #define LTC_CHAVID_PKHAVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_PKHAVID_SHIFT)) & LTC_CHAVID_PKHAVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5933 | #define LTC_CHAVID_MDHAREV_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 5934 | #define LTC_CHAVID_MDHAREV_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 5935 | #define LTC_CHAVID_MDHAREV(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_MDHAREV_SHIFT)) & LTC_CHAVID_MDHAREV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5936 | #define LTC_CHAVID_MDHAVID_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 5937 | #define LTC_CHAVID_MDHAVID_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 5938 | #define LTC_CHAVID_MDHAVID(x) (((uint32_t)(((uint32_t)(x)) << LTC_CHAVID_MDHAVID_SHIFT)) & LTC_CHAVID_MDHAVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5939 | |
AnnaBridge | 171:3a7713b1edbc | 5940 | /*! @name FIFOSTA - LTC FIFO Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 5941 | #define LTC_FIFOSTA_IFL_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 5942 | #define LTC_FIFOSTA_IFL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5943 | #define LTC_FIFOSTA_IFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFL_SHIFT)) & LTC_FIFOSTA_IFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5944 | #define LTC_FIFOSTA_IFF_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 5945 | #define LTC_FIFOSTA_IFF_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 5946 | #define LTC_FIFOSTA_IFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_IFF_SHIFT)) & LTC_FIFOSTA_IFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5947 | #define LTC_FIFOSTA_OFL_MASK (0x7F0000U) |
AnnaBridge | 171:3a7713b1edbc | 5948 | #define LTC_FIFOSTA_OFL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5949 | #define LTC_FIFOSTA_OFL(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFL_SHIFT)) & LTC_FIFOSTA_OFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5950 | #define LTC_FIFOSTA_OFF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 5951 | #define LTC_FIFOSTA_OFF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 5952 | #define LTC_FIFOSTA_OFF(x) (((uint32_t)(((uint32_t)(x)) << LTC_FIFOSTA_OFF_SHIFT)) & LTC_FIFOSTA_OFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5953 | |
AnnaBridge | 171:3a7713b1edbc | 5954 | /*! @name IFIFO - LTC Input Data FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 5955 | #define LTC_IFIFO_IFIFO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5956 | #define LTC_IFIFO_IFIFO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5957 | #define LTC_IFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_IFIFO_IFIFO_SHIFT)) & LTC_IFIFO_IFIFO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5958 | |
AnnaBridge | 171:3a7713b1edbc | 5959 | /*! @name OFIFO - LTC Output Data FIFO */ |
AnnaBridge | 171:3a7713b1edbc | 5960 | #define LTC_OFIFO_OFIFO_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5961 | #define LTC_OFIFO_OFIFO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5962 | #define LTC_OFIFO_OFIFO(x) (((uint32_t)(((uint32_t)(x)) << LTC_OFIFO_OFIFO_SHIFT)) & LTC_OFIFO_OFIFO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5963 | |
AnnaBridge | 171:3a7713b1edbc | 5964 | /* The count of LTC_PKA */ |
AnnaBridge | 171:3a7713b1edbc | 5965 | #define LTC_PKA_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 5966 | |
AnnaBridge | 171:3a7713b1edbc | 5967 | /*! @name PKA0 - LTC PKHA A0 0 Register..LTC PKHA A0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 5968 | #define LTC_PKA0_PKHA_A0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5969 | #define LTC_PKA0_PKHA_A0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5970 | #define LTC_PKA0_PKHA_A0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA0_PKHA_A0_SHIFT)) & LTC_PKA0_PKHA_A0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5971 | |
AnnaBridge | 171:3a7713b1edbc | 5972 | /* The count of LTC_PKA0 */ |
AnnaBridge | 171:3a7713b1edbc | 5973 | #define LTC_PKA0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5974 | |
AnnaBridge | 171:3a7713b1edbc | 5975 | /*! @name PKA1 - LTC PKHA A1 0 Register..LTC PKHA A1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 5976 | #define LTC_PKA1_PKHA_A1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5977 | #define LTC_PKA1_PKHA_A1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5978 | #define LTC_PKA1_PKHA_A1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA1_PKHA_A1_SHIFT)) & LTC_PKA1_PKHA_A1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5979 | |
AnnaBridge | 171:3a7713b1edbc | 5980 | /* The count of LTC_PKA1 */ |
AnnaBridge | 171:3a7713b1edbc | 5981 | #define LTC_PKA1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5982 | |
AnnaBridge | 171:3a7713b1edbc | 5983 | /*! @name PKA2 - LTC PKHA A2 0 Register..LTC PKHA A2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 5984 | #define LTC_PKA2_PKHA_A2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5985 | #define LTC_PKA2_PKHA_A2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5986 | #define LTC_PKA2_PKHA_A2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA2_PKHA_A2_SHIFT)) & LTC_PKA2_PKHA_A2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5987 | |
AnnaBridge | 171:3a7713b1edbc | 5988 | /* The count of LTC_PKA2 */ |
AnnaBridge | 171:3a7713b1edbc | 5989 | #define LTC_PKA2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5990 | |
AnnaBridge | 171:3a7713b1edbc | 5991 | /*! @name PKA3 - LTC PKHA A3 0 Register..LTC PKHA A3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 5992 | #define LTC_PKA3_PKHA_A3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 5993 | #define LTC_PKA3_PKHA_A3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 5994 | #define LTC_PKA3_PKHA_A3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKA3_PKHA_A3_SHIFT)) & LTC_PKA3_PKHA_A3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 5995 | |
AnnaBridge | 171:3a7713b1edbc | 5996 | /* The count of LTC_PKA3 */ |
AnnaBridge | 171:3a7713b1edbc | 5997 | #define LTC_PKA3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 5998 | |
AnnaBridge | 171:3a7713b1edbc | 5999 | /* The count of LTC_PKB */ |
AnnaBridge | 171:3a7713b1edbc | 6000 | #define LTC_PKB_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 6001 | |
AnnaBridge | 171:3a7713b1edbc | 6002 | /*! @name PKB0 - LTC PKHA B0 0 Register..LTC PKHA B0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6003 | #define LTC_PKB0_PKHA_B0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6004 | #define LTC_PKB0_PKHA_B0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6005 | #define LTC_PKB0_PKHA_B0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB0_PKHA_B0_SHIFT)) & LTC_PKB0_PKHA_B0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6006 | |
AnnaBridge | 171:3a7713b1edbc | 6007 | /* The count of LTC_PKB0 */ |
AnnaBridge | 171:3a7713b1edbc | 6008 | #define LTC_PKB0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6009 | |
AnnaBridge | 171:3a7713b1edbc | 6010 | /*! @name PKB1 - LTC PKHA B1 0 Register..LTC PKHA B1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6011 | #define LTC_PKB1_PKHA_B1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6012 | #define LTC_PKB1_PKHA_B1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6013 | #define LTC_PKB1_PKHA_B1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB1_PKHA_B1_SHIFT)) & LTC_PKB1_PKHA_B1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6014 | |
AnnaBridge | 171:3a7713b1edbc | 6015 | /* The count of LTC_PKB1 */ |
AnnaBridge | 171:3a7713b1edbc | 6016 | #define LTC_PKB1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6017 | |
AnnaBridge | 171:3a7713b1edbc | 6018 | /*! @name PKB2 - LTC PKHA B2 0 Register..LTC PKHA B2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6019 | #define LTC_PKB2_PKHA_B2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6020 | #define LTC_PKB2_PKHA_B2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6021 | #define LTC_PKB2_PKHA_B2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB2_PKHA_B2_SHIFT)) & LTC_PKB2_PKHA_B2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6022 | |
AnnaBridge | 171:3a7713b1edbc | 6023 | /* The count of LTC_PKB2 */ |
AnnaBridge | 171:3a7713b1edbc | 6024 | #define LTC_PKB2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6025 | |
AnnaBridge | 171:3a7713b1edbc | 6026 | /*! @name PKB3 - LTC PKHA B3 0 Register..LTC PKHA B3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6027 | #define LTC_PKB3_PKHA_B3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6028 | #define LTC_PKB3_PKHA_B3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6029 | #define LTC_PKB3_PKHA_B3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKB3_PKHA_B3_SHIFT)) & LTC_PKB3_PKHA_B3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6030 | |
AnnaBridge | 171:3a7713b1edbc | 6031 | /* The count of LTC_PKB3 */ |
AnnaBridge | 171:3a7713b1edbc | 6032 | #define LTC_PKB3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6033 | |
AnnaBridge | 171:3a7713b1edbc | 6034 | /* The count of LTC_PKN */ |
AnnaBridge | 171:3a7713b1edbc | 6035 | #define LTC_PKN_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 6036 | |
AnnaBridge | 171:3a7713b1edbc | 6037 | /*! @name PKN0 - LTC PKHA N0 0 Register..LTC PKHA N0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6038 | #define LTC_PKN0_PKHA_N0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6039 | #define LTC_PKN0_PKHA_N0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6040 | #define LTC_PKN0_PKHA_N0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN0_PKHA_N0_SHIFT)) & LTC_PKN0_PKHA_N0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6041 | |
AnnaBridge | 171:3a7713b1edbc | 6042 | /* The count of LTC_PKN0 */ |
AnnaBridge | 171:3a7713b1edbc | 6043 | #define LTC_PKN0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6044 | |
AnnaBridge | 171:3a7713b1edbc | 6045 | /*! @name PKN1 - LTC PKHA N1 0 Register..LTC PKHA N1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6046 | #define LTC_PKN1_PKHA_N1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6047 | #define LTC_PKN1_PKHA_N1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6048 | #define LTC_PKN1_PKHA_N1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN1_PKHA_N1_SHIFT)) & LTC_PKN1_PKHA_N1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6049 | |
AnnaBridge | 171:3a7713b1edbc | 6050 | /* The count of LTC_PKN1 */ |
AnnaBridge | 171:3a7713b1edbc | 6051 | #define LTC_PKN1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6052 | |
AnnaBridge | 171:3a7713b1edbc | 6053 | /*! @name PKN2 - LTC PKHA N2 0 Register..LTC PKHA N2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6054 | #define LTC_PKN2_PKHA_N2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6055 | #define LTC_PKN2_PKHA_N2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6056 | #define LTC_PKN2_PKHA_N2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN2_PKHA_N2_SHIFT)) & LTC_PKN2_PKHA_N2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6057 | |
AnnaBridge | 171:3a7713b1edbc | 6058 | /* The count of LTC_PKN2 */ |
AnnaBridge | 171:3a7713b1edbc | 6059 | #define LTC_PKN2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6060 | |
AnnaBridge | 171:3a7713b1edbc | 6061 | /*! @name PKN3 - LTC PKHA N3 0 Register..LTC PKHA N3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6062 | #define LTC_PKN3_PKHA_N3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6063 | #define LTC_PKN3_PKHA_N3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6064 | #define LTC_PKN3_PKHA_N3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKN3_PKHA_N3_SHIFT)) & LTC_PKN3_PKHA_N3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6065 | |
AnnaBridge | 171:3a7713b1edbc | 6066 | /* The count of LTC_PKN3 */ |
AnnaBridge | 171:3a7713b1edbc | 6067 | #define LTC_PKN3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6068 | |
AnnaBridge | 171:3a7713b1edbc | 6069 | /* The count of LTC_PKE */ |
AnnaBridge | 171:3a7713b1edbc | 6070 | #define LTC_PKE_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 6071 | |
AnnaBridge | 171:3a7713b1edbc | 6072 | /*! @name PKE0 - LTC PKHA E0 0 Register..LTC PKHA E0 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6073 | #define LTC_PKE0_PKHA_E0_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6074 | #define LTC_PKE0_PKHA_E0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6075 | #define LTC_PKE0_PKHA_E0(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE0_PKHA_E0_SHIFT)) & LTC_PKE0_PKHA_E0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6076 | |
AnnaBridge | 171:3a7713b1edbc | 6077 | /* The count of LTC_PKE0 */ |
AnnaBridge | 171:3a7713b1edbc | 6078 | #define LTC_PKE0_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6079 | |
AnnaBridge | 171:3a7713b1edbc | 6080 | /*! @name PKE1 - LTC PKHA E1 0 Register..LTC PKHA E1 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6081 | #define LTC_PKE1_PKHA_E1_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6082 | #define LTC_PKE1_PKHA_E1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6083 | #define LTC_PKE1_PKHA_E1(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE1_PKHA_E1_SHIFT)) & LTC_PKE1_PKHA_E1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6084 | |
AnnaBridge | 171:3a7713b1edbc | 6085 | /* The count of LTC_PKE1 */ |
AnnaBridge | 171:3a7713b1edbc | 6086 | #define LTC_PKE1_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6087 | |
AnnaBridge | 171:3a7713b1edbc | 6088 | /*! @name PKE2 - LTC PKHA E2 0 Register..LTC PKHA E2 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6089 | #define LTC_PKE2_PKHA_E2_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6090 | #define LTC_PKE2_PKHA_E2_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6091 | #define LTC_PKE2_PKHA_E2(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE2_PKHA_E2_SHIFT)) & LTC_PKE2_PKHA_E2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6092 | |
AnnaBridge | 171:3a7713b1edbc | 6093 | /* The count of LTC_PKE2 */ |
AnnaBridge | 171:3a7713b1edbc | 6094 | #define LTC_PKE2_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6095 | |
AnnaBridge | 171:3a7713b1edbc | 6096 | /*! @name PKE3 - LTC PKHA E3 0 Register..LTC PKHA E3 15 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6097 | #define LTC_PKE3_PKHA_E3_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6098 | #define LTC_PKE3_PKHA_E3_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6099 | #define LTC_PKE3_PKHA_E3(x) (((uint32_t)(((uint32_t)(x)) << LTC_PKE3_PKHA_E3_SHIFT)) & LTC_PKE3_PKHA_E3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6100 | |
AnnaBridge | 171:3a7713b1edbc | 6101 | /* The count of LTC_PKE3 */ |
AnnaBridge | 171:3a7713b1edbc | 6102 | #define LTC_PKE3_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6103 | |
AnnaBridge | 171:3a7713b1edbc | 6104 | |
AnnaBridge | 171:3a7713b1edbc | 6105 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6106 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6107 | */ /* end of group LTC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6108 | |
AnnaBridge | 171:3a7713b1edbc | 6109 | |
AnnaBridge | 171:3a7713b1edbc | 6110 | /* LTC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6111 | /** Peripheral LTC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 6112 | #define LTC0_BASE (0x40051000u) |
AnnaBridge | 171:3a7713b1edbc | 6113 | /** Peripheral LTC0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6114 | #define LTC0 ((LTC_Type *)LTC0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6115 | /** Array initializer of LTC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6116 | #define LTC_BASE_ADDRS { LTC0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6117 | /** Array initializer of LTC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6118 | #define LTC_BASE_PTRS { LTC0 } |
AnnaBridge | 171:3a7713b1edbc | 6119 | /** Interrupt vectors for the LTC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 6120 | #define LTC_IRQS { LTC0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 6121 | |
AnnaBridge | 171:3a7713b1edbc | 6122 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6123 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6124 | */ /* end of group LTC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6125 | |
AnnaBridge | 171:3a7713b1edbc | 6126 | |
AnnaBridge | 171:3a7713b1edbc | 6127 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6128 | -- MCG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6129 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6130 | |
AnnaBridge | 171:3a7713b1edbc | 6131 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6132 | * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6133 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6134 | */ |
AnnaBridge | 171:3a7713b1edbc | 6135 | |
AnnaBridge | 171:3a7713b1edbc | 6136 | /** MCG - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6137 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6138 | __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 6139 | __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 6140 | __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 6141 | __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 6142 | __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6143 | __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 6144 | __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 6145 | uint8_t RESERVED_0[1]; |
AnnaBridge | 171:3a7713b1edbc | 6146 | __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6147 | uint8_t RESERVED_1[1]; |
AnnaBridge | 171:3a7713b1edbc | 6148 | __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 6149 | __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 6150 | __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 6151 | __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 6152 | } MCG_Type; |
AnnaBridge | 171:3a7713b1edbc | 6153 | |
AnnaBridge | 171:3a7713b1edbc | 6154 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6155 | -- MCG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6156 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6157 | |
AnnaBridge | 171:3a7713b1edbc | 6158 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6159 | * @addtogroup MCG_Register_Masks MCG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6160 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6161 | */ |
AnnaBridge | 171:3a7713b1edbc | 6162 | |
AnnaBridge | 171:3a7713b1edbc | 6163 | /*! @name C1 - MCG Control 1 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6164 | #define MCG_C1_IREFSTEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6165 | #define MCG_C1_IREFSTEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6166 | #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6167 | #define MCG_C1_IRCLKEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6168 | #define MCG_C1_IRCLKEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6169 | #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6170 | #define MCG_C1_IREFS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6171 | #define MCG_C1_IREFS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6172 | #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6173 | #define MCG_C1_FRDIV_MASK (0x38U) |
AnnaBridge | 171:3a7713b1edbc | 6174 | #define MCG_C1_FRDIV_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6175 | #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6176 | #define MCG_C1_CLKS_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 6177 | #define MCG_C1_CLKS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6178 | #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6179 | |
AnnaBridge | 171:3a7713b1edbc | 6180 | /*! @name C2 - MCG Control 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6181 | #define MCG_C2_IRCS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6182 | #define MCG_C2_IRCS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6183 | #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6184 | #define MCG_C2_LP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6185 | #define MCG_C2_LP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6186 | #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6187 | #define MCG_C2_EREFS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6188 | #define MCG_C2_EREFS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6189 | #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6190 | #define MCG_C2_HGO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 6191 | #define MCG_C2_HGO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6192 | #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6193 | #define MCG_C2_RANGE_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 6194 | #define MCG_C2_RANGE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6195 | #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6196 | #define MCG_C2_FCFTRIM_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6197 | #define MCG_C2_FCFTRIM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6198 | #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6199 | #define MCG_C2_LOCRE0_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6200 | #define MCG_C2_LOCRE0_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6201 | #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6202 | |
AnnaBridge | 171:3a7713b1edbc | 6203 | /*! @name C3 - MCG Control 3 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6204 | #define MCG_C3_SCTRIM_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6205 | #define MCG_C3_SCTRIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6206 | #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6207 | |
AnnaBridge | 171:3a7713b1edbc | 6208 | /*! @name C4 - MCG Control 4 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6209 | #define MCG_C4_SCFTRIM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6210 | #define MCG_C4_SCFTRIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6211 | #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6212 | #define MCG_C4_FCTRIM_MASK (0x1EU) |
AnnaBridge | 171:3a7713b1edbc | 6213 | #define MCG_C4_FCTRIM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6214 | #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6215 | #define MCG_C4_DRST_DRS_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 6216 | #define MCG_C4_DRST_DRS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6217 | #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6218 | #define MCG_C4_DMX32_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6219 | #define MCG_C4_DMX32_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6220 | #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6221 | |
AnnaBridge | 171:3a7713b1edbc | 6222 | /*! @name C5 - MCG Control 5 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6223 | #define MCG_C5_PRDIV_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 6224 | #define MCG_C5_PRDIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6225 | #define MCG_C5_PRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6226 | #define MCG_C5_PLLSTEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6227 | #define MCG_C5_PLLSTEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6228 | #define MCG_C5_PLLSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6229 | #define MCG_C5_PLLCLKEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6230 | #define MCG_C5_PLLCLKEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6231 | #define MCG_C5_PLLCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6232 | |
AnnaBridge | 171:3a7713b1edbc | 6233 | /*! @name C6 - MCG Control 6 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6234 | #define MCG_C6_VDIV_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 6235 | #define MCG_C6_VDIV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6236 | #define MCG_C6_VDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6237 | #define MCG_C6_CME0_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6238 | #define MCG_C6_CME0_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6239 | #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6240 | #define MCG_C6_PLLS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6241 | #define MCG_C6_PLLS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6242 | #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6243 | #define MCG_C6_LOLIE0_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6244 | #define MCG_C6_LOLIE0_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6245 | #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6246 | |
AnnaBridge | 171:3a7713b1edbc | 6247 | /*! @name S - MCG Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 6248 | #define MCG_S_IRCST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6249 | #define MCG_S_IRCST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6250 | #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6251 | #define MCG_S_OSCINIT0_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6252 | #define MCG_S_OSCINIT0_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6253 | #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6254 | #define MCG_S_CLKST_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 6255 | #define MCG_S_CLKST_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6256 | #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6257 | #define MCG_S_IREFST_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6258 | #define MCG_S_IREFST_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6259 | #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6260 | #define MCG_S_PLLST_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6261 | #define MCG_S_PLLST_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6262 | #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6263 | #define MCG_S_LOCK0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6264 | #define MCG_S_LOCK0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6265 | #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6266 | #define MCG_S_LOLS0_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6267 | #define MCG_S_LOLS0_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6268 | #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6269 | |
AnnaBridge | 171:3a7713b1edbc | 6270 | /*! @name SC - MCG Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 6271 | #define MCG_SC_LOCS0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6272 | #define MCG_SC_LOCS0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6273 | #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6274 | #define MCG_SC_FCRDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 6275 | #define MCG_SC_FCRDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6276 | #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6277 | #define MCG_SC_FLTPRSRV_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 6278 | #define MCG_SC_FLTPRSRV_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6279 | #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6280 | #define MCG_SC_ATMF_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6281 | #define MCG_SC_ATMF_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6282 | #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6283 | #define MCG_SC_ATMS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6284 | #define MCG_SC_ATMS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6285 | #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6286 | #define MCG_SC_ATME_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6287 | #define MCG_SC_ATME_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6288 | #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6289 | |
AnnaBridge | 171:3a7713b1edbc | 6290 | /*! @name ATCVH - MCG Auto Trim Compare Value High Register */ |
AnnaBridge | 171:3a7713b1edbc | 6291 | #define MCG_ATCVH_ATCVH_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6292 | #define MCG_ATCVH_ATCVH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6293 | #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6294 | |
AnnaBridge | 171:3a7713b1edbc | 6295 | /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 6296 | #define MCG_ATCVL_ATCVL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6297 | #define MCG_ATCVL_ATCVL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6298 | #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6299 | |
AnnaBridge | 171:3a7713b1edbc | 6300 | /*! @name C7 - MCG Control 7 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6301 | #define MCG_C7_OSCSEL_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 6302 | #define MCG_C7_OSCSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6303 | #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6304 | |
AnnaBridge | 171:3a7713b1edbc | 6305 | /*! @name C8 - MCG Control 8 Register */ |
AnnaBridge | 171:3a7713b1edbc | 6306 | #define MCG_C8_LOCS1_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6307 | #define MCG_C8_LOCS1_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6308 | #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6309 | #define MCG_C8_CME1_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6310 | #define MCG_C8_CME1_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6311 | #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6312 | #define MCG_C8_LOLRE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6313 | #define MCG_C8_LOLRE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6314 | #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6315 | #define MCG_C8_LOCRE1_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6316 | #define MCG_C8_LOCRE1_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6317 | #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6318 | |
AnnaBridge | 171:3a7713b1edbc | 6319 | |
AnnaBridge | 171:3a7713b1edbc | 6320 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6321 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6322 | */ /* end of group MCG_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6323 | |
AnnaBridge | 171:3a7713b1edbc | 6324 | |
AnnaBridge | 171:3a7713b1edbc | 6325 | /* MCG - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6326 | /** Peripheral MCG base address */ |
AnnaBridge | 171:3a7713b1edbc | 6327 | #define MCG_BASE (0x40064000u) |
AnnaBridge | 171:3a7713b1edbc | 6328 | /** Peripheral MCG base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6329 | #define MCG ((MCG_Type *)MCG_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6330 | /** Array initializer of MCG peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6331 | #define MCG_BASE_ADDRS { MCG_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6332 | /** Array initializer of MCG peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6333 | #define MCG_BASE_PTRS { MCG } |
AnnaBridge | 171:3a7713b1edbc | 6334 | /** Interrupt vectors for the MCG peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 6335 | #define MCG_IRQS { MCG_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 6336 | /* MCG C5[PLLCLKEN0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 6337 | #define MCG_C5_PLLCLKEN0_MASK (MCG_C5_PLLCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6338 | #define MCG_C5_PLLCLKEN0_SHIFT (MCG_C5_PLLCLKEN_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 6339 | #define MCG_C5_PLLCLKEN0_WIDTH (MCG_C5_PLLCLKEN_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 6340 | #define MCG_C5_PLLCLKEN0(x) (MCG_C5_PLLCLKEN(x)) |
AnnaBridge | 171:3a7713b1edbc | 6341 | |
AnnaBridge | 171:3a7713b1edbc | 6342 | /* MCG C5[PLLSTEN0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 6343 | #define MCG_C5_PLLSTEN0_MASK (MCG_C5_PLLSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6344 | #define MCG_C5_PLLSTEN0_SHIFT (MCG_C5_PLLSTEN_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 6345 | #define MCG_C5_PLLSTEN0_WIDTH (MCG_C5_PLLSTEN_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 6346 | #define MCG_C5_PLLSTEN0(x) (MCG_C5_PLLSTEN(x)) |
AnnaBridge | 171:3a7713b1edbc | 6347 | |
AnnaBridge | 171:3a7713b1edbc | 6348 | /* MCG C5[PRDIV0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 6349 | #define MCG_C5_PRDIV0_MASK (MCG_C5_PRDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6350 | #define MCG_C5_PRDIV0_SHIFT (MCG_C5_PRDIV_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 6351 | #define MCG_C5_PRDIV0_WIDTH (MCG_C5_PRDIV_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 6352 | #define MCG_C5_PRDIV0(x) (MCG_C5_PRDIV(x)) |
AnnaBridge | 171:3a7713b1edbc | 6353 | |
AnnaBridge | 171:3a7713b1edbc | 6354 | /* MCG C6[VDIV0] backward compatibility */ |
AnnaBridge | 171:3a7713b1edbc | 6355 | #define MCG_C6_VDIV0_MASK (MCG_C6_VDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6356 | #define MCG_C6_VDIV0_SHIFT (MCG_C6_VDIV_SHIFT) |
AnnaBridge | 171:3a7713b1edbc | 6357 | #define MCG_C6_VDIV0_WIDTH (MCG_C6_VDIV_WIDTH) |
AnnaBridge | 171:3a7713b1edbc | 6358 | #define MCG_C6_VDIV0(x) (MCG_C6_VDIV(x)) |
AnnaBridge | 171:3a7713b1edbc | 6359 | |
AnnaBridge | 171:3a7713b1edbc | 6360 | |
AnnaBridge | 171:3a7713b1edbc | 6361 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6362 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6363 | */ /* end of group MCG_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6364 | |
AnnaBridge | 171:3a7713b1edbc | 6365 | |
AnnaBridge | 171:3a7713b1edbc | 6366 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6367 | -- MCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6368 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6369 | |
AnnaBridge | 171:3a7713b1edbc | 6370 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6371 | * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6372 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6373 | */ |
AnnaBridge | 171:3a7713b1edbc | 6374 | |
AnnaBridge | 171:3a7713b1edbc | 6375 | /** MCM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6376 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6377 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 6378 | __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6379 | __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 6380 | __IO uint32_t PLACR; /**< Platform Control Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 6381 | uint8_t RESERVED_1[48]; |
AnnaBridge | 171:3a7713b1edbc | 6382 | __IO uint32_t CPO; /**< Compute Operation Control Register, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 6383 | } MCM_Type; |
AnnaBridge | 171:3a7713b1edbc | 6384 | |
AnnaBridge | 171:3a7713b1edbc | 6385 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6386 | -- MCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6387 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6388 | |
AnnaBridge | 171:3a7713b1edbc | 6389 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6390 | * @addtogroup MCM_Register_Masks MCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6391 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6392 | */ |
AnnaBridge | 171:3a7713b1edbc | 6393 | |
AnnaBridge | 171:3a7713b1edbc | 6394 | /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 6395 | #define MCM_PLASC_ASC_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6396 | #define MCM_PLASC_ASC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6397 | #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6398 | |
AnnaBridge | 171:3a7713b1edbc | 6399 | /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 6400 | #define MCM_PLAMC_AMC_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 6401 | #define MCM_PLAMC_AMC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6402 | #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6403 | |
AnnaBridge | 171:3a7713b1edbc | 6404 | /*! @name PLACR - Platform Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 6405 | #define MCM_PLACR_ARB_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6406 | #define MCM_PLACR_ARB_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6407 | #define MCM_PLACR_ARB(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ARB_SHIFT)) & MCM_PLACR_ARB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6408 | #define MCM_PLACR_CFCC_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 6409 | #define MCM_PLACR_CFCC_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 6410 | #define MCM_PLACR_CFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_CFCC_SHIFT)) & MCM_PLACR_CFCC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6411 | #define MCM_PLACR_DFCDA_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 6412 | #define MCM_PLACR_DFCDA_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 6413 | #define MCM_PLACR_DFCDA(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCDA_SHIFT)) & MCM_PLACR_DFCDA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6414 | #define MCM_PLACR_DFCIC_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 6415 | #define MCM_PLACR_DFCIC_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6416 | #define MCM_PLACR_DFCIC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCIC_SHIFT)) & MCM_PLACR_DFCIC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6417 | #define MCM_PLACR_DFCC_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 6418 | #define MCM_PLACR_DFCC_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 6419 | #define MCM_PLACR_DFCC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCC_SHIFT)) & MCM_PLACR_DFCC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6420 | #define MCM_PLACR_EFDS_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 6421 | #define MCM_PLACR_EFDS_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 6422 | #define MCM_PLACR_EFDS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_EFDS_SHIFT)) & MCM_PLACR_EFDS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6423 | #define MCM_PLACR_DFCS_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 6424 | #define MCM_PLACR_DFCS_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 6425 | #define MCM_PLACR_DFCS(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_DFCS_SHIFT)) & MCM_PLACR_DFCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6426 | #define MCM_PLACR_ESFC_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 6427 | #define MCM_PLACR_ESFC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6428 | #define MCM_PLACR_ESFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_PLACR_ESFC_SHIFT)) & MCM_PLACR_ESFC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6429 | |
AnnaBridge | 171:3a7713b1edbc | 6430 | /*! @name CPO - Compute Operation Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 6431 | #define MCM_CPO_CPOREQ_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6432 | #define MCM_CPO_CPOREQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6433 | #define MCM_CPO_CPOREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6434 | #define MCM_CPO_CPOACK_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6435 | #define MCM_CPO_CPOACK_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6436 | #define MCM_CPO_CPOACK(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6437 | #define MCM_CPO_CPOWOI_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6438 | #define MCM_CPO_CPOWOI_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6439 | #define MCM_CPO_CPOWOI(x) (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6440 | |
AnnaBridge | 171:3a7713b1edbc | 6441 | |
AnnaBridge | 171:3a7713b1edbc | 6442 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6443 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6444 | */ /* end of group MCM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6445 | |
AnnaBridge | 171:3a7713b1edbc | 6446 | |
AnnaBridge | 171:3a7713b1edbc | 6447 | /* MCM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6448 | /** Peripheral MCM base address */ |
AnnaBridge | 171:3a7713b1edbc | 6449 | #define MCM_BASE (0xF0003000u) |
AnnaBridge | 171:3a7713b1edbc | 6450 | /** Peripheral MCM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6451 | #define MCM ((MCM_Type *)MCM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6452 | /** Array initializer of MCM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6453 | #define MCM_BASE_ADDRS { MCM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6454 | /** Array initializer of MCM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6455 | #define MCM_BASE_PTRS { MCM } |
AnnaBridge | 171:3a7713b1edbc | 6456 | |
AnnaBridge | 171:3a7713b1edbc | 6457 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6458 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6459 | */ /* end of group MCM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6460 | |
AnnaBridge | 171:3a7713b1edbc | 6461 | |
AnnaBridge | 171:3a7713b1edbc | 6462 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6463 | -- MPU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6464 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6465 | |
AnnaBridge | 171:3a7713b1edbc | 6466 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6467 | * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6468 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6469 | */ |
AnnaBridge | 171:3a7713b1edbc | 6470 | |
AnnaBridge | 171:3a7713b1edbc | 6471 | /** MPU - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6472 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6473 | __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 6474 | uint8_t RESERVED_0[12]; |
AnnaBridge | 171:3a7713b1edbc | 6475 | struct { /* offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6476 | __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6477 | __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6478 | } SP[5]; |
AnnaBridge | 171:3a7713b1edbc | 6479 | uint8_t RESERVED_1[968]; |
AnnaBridge | 171:3a7713b1edbc | 6480 | __IO uint32_t WORD[8][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6481 | uint8_t RESERVED_2[896]; |
AnnaBridge | 171:3a7713b1edbc | 6482 | __IO uint32_t RGDAAC[8]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6483 | } MPU_Type; |
AnnaBridge | 171:3a7713b1edbc | 6484 | |
AnnaBridge | 171:3a7713b1edbc | 6485 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6486 | -- MPU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6487 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6488 | |
AnnaBridge | 171:3a7713b1edbc | 6489 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6490 | * @addtogroup MPU_Register_Masks MPU Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6491 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6492 | */ |
AnnaBridge | 171:3a7713b1edbc | 6493 | |
AnnaBridge | 171:3a7713b1edbc | 6494 | /*! @name CESR - Control/Error Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 6495 | #define MPU_CESR_VLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6496 | #define MPU_CESR_VLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6497 | #define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6498 | #define MPU_CESR_NRGD_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 6499 | #define MPU_CESR_NRGD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6500 | #define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6501 | #define MPU_CESR_NSP_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 6502 | #define MPU_CESR_NSP_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6503 | #define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6504 | #define MPU_CESR_HRL_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 6505 | #define MPU_CESR_HRL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6506 | #define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6507 | #define MPU_CESR_SPERR_MASK (0xF8000000U) |
AnnaBridge | 171:3a7713b1edbc | 6508 | #define MPU_CESR_SPERR_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 6509 | #define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6510 | |
AnnaBridge | 171:3a7713b1edbc | 6511 | /*! @name EAR - Error Address Register, slave port n */ |
AnnaBridge | 171:3a7713b1edbc | 6512 | #define MPU_EAR_EADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6513 | #define MPU_EAR_EADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6514 | #define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6515 | |
AnnaBridge | 171:3a7713b1edbc | 6516 | /* The count of MPU_EAR */ |
AnnaBridge | 171:3a7713b1edbc | 6517 | #define MPU_EAR_COUNT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6518 | |
AnnaBridge | 171:3a7713b1edbc | 6519 | /*! @name EDR - Error Detail Register, slave port n */ |
AnnaBridge | 171:3a7713b1edbc | 6520 | #define MPU_EDR_ERW_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6521 | #define MPU_EDR_ERW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6522 | #define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6523 | #define MPU_EDR_EATTR_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 6524 | #define MPU_EDR_EATTR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6525 | #define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6526 | #define MPU_EDR_EMN_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 6527 | #define MPU_EDR_EMN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6528 | #define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6529 | #define MPU_EDR_EPID_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 6530 | #define MPU_EDR_EPID_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6531 | #define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6532 | #define MPU_EDR_EACD_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 6533 | #define MPU_EDR_EACD_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6534 | #define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6535 | |
AnnaBridge | 171:3a7713b1edbc | 6536 | /* The count of MPU_EDR */ |
AnnaBridge | 171:3a7713b1edbc | 6537 | #define MPU_EDR_COUNT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6538 | |
AnnaBridge | 171:3a7713b1edbc | 6539 | /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */ |
AnnaBridge | 171:3a7713b1edbc | 6540 | #define MPU_WORD_VLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6541 | #define MPU_WORD_VLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6542 | #define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6543 | #define MPU_WORD_M0UM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 6544 | #define MPU_WORD_M0UM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6545 | #define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6546 | #define MPU_WORD_M0SM_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 6547 | #define MPU_WORD_M0SM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6548 | #define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6549 | #define MPU_WORD_M0PE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6550 | #define MPU_WORD_M0PE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6551 | #define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6552 | #define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U) |
AnnaBridge | 171:3a7713b1edbc | 6553 | #define MPU_WORD_ENDADDR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6554 | #define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6555 | #define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U) |
AnnaBridge | 171:3a7713b1edbc | 6556 | #define MPU_WORD_SRTADDR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6557 | #define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6558 | #define MPU_WORD_M1UM_MASK (0x1C0U) |
AnnaBridge | 171:3a7713b1edbc | 6559 | #define MPU_WORD_M1UM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6560 | #define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6561 | #define MPU_WORD_M1SM_MASK (0x600U) |
AnnaBridge | 171:3a7713b1edbc | 6562 | #define MPU_WORD_M1SM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6563 | #define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6564 | #define MPU_WORD_M1PE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 6565 | #define MPU_WORD_M1PE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 6566 | #define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6567 | #define MPU_WORD_M2UM_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 6568 | #define MPU_WORD_M2UM_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6569 | #define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6570 | #define MPU_WORD_M2SM_MASK (0x18000U) |
AnnaBridge | 171:3a7713b1edbc | 6571 | #define MPU_WORD_M2SM_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 6572 | #define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6573 | #define MPU_WORD_PIDMASK_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 6574 | #define MPU_WORD_PIDMASK_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 6575 | #define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6576 | #define MPU_WORD_M2PE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 6577 | #define MPU_WORD_M2PE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 6578 | #define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6579 | #define MPU_WORD_M3UM_MASK (0x1C0000U) |
AnnaBridge | 171:3a7713b1edbc | 6580 | #define MPU_WORD_M3UM_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 6581 | #define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6582 | #define MPU_WORD_M3SM_MASK (0x600000U) |
AnnaBridge | 171:3a7713b1edbc | 6583 | #define MPU_WORD_M3SM_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 6584 | #define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6585 | #define MPU_WORD_M3PE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 6586 | #define MPU_WORD_M3PE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 6587 | #define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6588 | #define MPU_WORD_PID_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 6589 | #define MPU_WORD_PID_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 6590 | #define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6591 | #define MPU_WORD_M4WE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 6592 | #define MPU_WORD_M4WE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 6593 | #define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6594 | #define MPU_WORD_M4RE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 6595 | #define MPU_WORD_M4RE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 6596 | #define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6597 | #define MPU_WORD_M5WE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 6598 | #define MPU_WORD_M5WE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 6599 | #define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6600 | #define MPU_WORD_M5RE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 6601 | #define MPU_WORD_M5RE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 6602 | #define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6603 | #define MPU_WORD_M6WE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 6604 | #define MPU_WORD_M6WE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 6605 | #define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6606 | #define MPU_WORD_M6RE_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 6607 | #define MPU_WORD_M6RE_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 6608 | #define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6609 | #define MPU_WORD_M7WE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 6610 | #define MPU_WORD_M7WE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 6611 | #define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6612 | #define MPU_WORD_M7RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 6613 | #define MPU_WORD_M7RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 6614 | #define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6615 | |
AnnaBridge | 171:3a7713b1edbc | 6616 | /* The count of MPU_WORD */ |
AnnaBridge | 171:3a7713b1edbc | 6617 | #define MPU_WORD_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6618 | |
AnnaBridge | 171:3a7713b1edbc | 6619 | /* The count of MPU_WORD */ |
AnnaBridge | 171:3a7713b1edbc | 6620 | #define MPU_WORD_COUNT2 (4U) |
AnnaBridge | 171:3a7713b1edbc | 6621 | |
AnnaBridge | 171:3a7713b1edbc | 6622 | /*! @name RGDAAC - Region Descriptor Alternate Access Control n */ |
AnnaBridge | 171:3a7713b1edbc | 6623 | #define MPU_RGDAAC_M0UM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 6624 | #define MPU_RGDAAC_M0UM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6625 | #define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6626 | #define MPU_RGDAAC_M0SM_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 6627 | #define MPU_RGDAAC_M0SM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6628 | #define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6629 | #define MPU_RGDAAC_M0PE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6630 | #define MPU_RGDAAC_M0PE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6631 | #define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6632 | #define MPU_RGDAAC_M1UM_MASK (0x1C0U) |
AnnaBridge | 171:3a7713b1edbc | 6633 | #define MPU_RGDAAC_M1UM_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6634 | #define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6635 | #define MPU_RGDAAC_M1SM_MASK (0x600U) |
AnnaBridge | 171:3a7713b1edbc | 6636 | #define MPU_RGDAAC_M1SM_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6637 | #define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6638 | #define MPU_RGDAAC_M1PE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 6639 | #define MPU_RGDAAC_M1PE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 6640 | #define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6641 | #define MPU_RGDAAC_M2UM_MASK (0x7000U) |
AnnaBridge | 171:3a7713b1edbc | 6642 | #define MPU_RGDAAC_M2UM_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 6643 | #define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6644 | #define MPU_RGDAAC_M2SM_MASK (0x18000U) |
AnnaBridge | 171:3a7713b1edbc | 6645 | #define MPU_RGDAAC_M2SM_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 6646 | #define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6647 | #define MPU_RGDAAC_M2PE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 6648 | #define MPU_RGDAAC_M2PE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 6649 | #define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6650 | #define MPU_RGDAAC_M3UM_MASK (0x1C0000U) |
AnnaBridge | 171:3a7713b1edbc | 6651 | #define MPU_RGDAAC_M3UM_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 6652 | #define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6653 | #define MPU_RGDAAC_M3SM_MASK (0x600000U) |
AnnaBridge | 171:3a7713b1edbc | 6654 | #define MPU_RGDAAC_M3SM_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 6655 | #define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6656 | #define MPU_RGDAAC_M3PE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 6657 | #define MPU_RGDAAC_M3PE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 6658 | #define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6659 | #define MPU_RGDAAC_M4WE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 6660 | #define MPU_RGDAAC_M4WE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 6661 | #define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6662 | #define MPU_RGDAAC_M4RE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 6663 | #define MPU_RGDAAC_M4RE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 6664 | #define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6665 | #define MPU_RGDAAC_M5WE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 6666 | #define MPU_RGDAAC_M5WE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 6667 | #define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6668 | #define MPU_RGDAAC_M5RE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 6669 | #define MPU_RGDAAC_M5RE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 6670 | #define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6671 | #define MPU_RGDAAC_M6WE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 6672 | #define MPU_RGDAAC_M6WE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 6673 | #define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6674 | #define MPU_RGDAAC_M6RE_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 6675 | #define MPU_RGDAAC_M6RE_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 6676 | #define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6677 | #define MPU_RGDAAC_M7WE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 6678 | #define MPU_RGDAAC_M7WE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 6679 | #define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6680 | #define MPU_RGDAAC_M7RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 6681 | #define MPU_RGDAAC_M7RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 6682 | #define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6683 | |
AnnaBridge | 171:3a7713b1edbc | 6684 | /* The count of MPU_RGDAAC */ |
AnnaBridge | 171:3a7713b1edbc | 6685 | #define MPU_RGDAAC_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6686 | |
AnnaBridge | 171:3a7713b1edbc | 6687 | |
AnnaBridge | 171:3a7713b1edbc | 6688 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6689 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6690 | */ /* end of group MPU_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6691 | |
AnnaBridge | 171:3a7713b1edbc | 6692 | |
AnnaBridge | 171:3a7713b1edbc | 6693 | /* MPU - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6694 | /** Peripheral MPU base address */ |
AnnaBridge | 171:3a7713b1edbc | 6695 | #define MPU_BASE (0x4000D000u) |
AnnaBridge | 171:3a7713b1edbc | 6696 | /** Peripheral MPU base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6697 | #define MPU ((MPU_Type *)MPU_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6698 | /** Array initializer of MPU peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6699 | #define MPU_BASE_ADDRS { MPU_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6700 | /** Array initializer of MPU peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6701 | #define MPU_BASE_PTRS { MPU } |
AnnaBridge | 171:3a7713b1edbc | 6702 | |
AnnaBridge | 171:3a7713b1edbc | 6703 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6704 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6705 | */ /* end of group MPU_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6706 | |
AnnaBridge | 171:3a7713b1edbc | 6707 | |
AnnaBridge | 171:3a7713b1edbc | 6708 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6709 | -- MTB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6710 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6711 | |
AnnaBridge | 171:3a7713b1edbc | 6712 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6713 | * @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6714 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6715 | */ |
AnnaBridge | 171:3a7713b1edbc | 6716 | |
AnnaBridge | 171:3a7713b1edbc | 6717 | /** MTB - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6718 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6719 | __IO uint32_t POSITION; /**< MTB Position Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 6720 | __IO uint32_t MASTER; /**< MTB Master Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6721 | __IO uint32_t FLOW; /**< MTB Flow Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 6722 | __I uint32_t BASE; /**< MTB Base Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 6723 | uint8_t RESERVED_0[3824]; |
AnnaBridge | 171:3a7713b1edbc | 6724 | __I uint32_t MODECTRL; /**< Integration Mode Control Register, offset: 0xF00 */ |
AnnaBridge | 171:3a7713b1edbc | 6725 | uint8_t RESERVED_1[156]; |
AnnaBridge | 171:3a7713b1edbc | 6726 | __I uint32_t TAGSET; /**< Claim TAG Set Register, offset: 0xFA0 */ |
AnnaBridge | 171:3a7713b1edbc | 6727 | __I uint32_t TAGCLEAR; /**< Claim TAG Clear Register, offset: 0xFA4 */ |
AnnaBridge | 171:3a7713b1edbc | 6728 | uint8_t RESERVED_2[8]; |
AnnaBridge | 171:3a7713b1edbc | 6729 | __I uint32_t LOCKACCESS; /**< Lock Access Register, offset: 0xFB0 */ |
AnnaBridge | 171:3a7713b1edbc | 6730 | __I uint32_t LOCKSTAT; /**< Lock Status Register, offset: 0xFB4 */ |
AnnaBridge | 171:3a7713b1edbc | 6731 | __I uint32_t AUTHSTAT; /**< Authentication Status Register, offset: 0xFB8 */ |
AnnaBridge | 171:3a7713b1edbc | 6732 | __I uint32_t DEVICEARCH; /**< Device Architecture Register, offset: 0xFBC */ |
AnnaBridge | 171:3a7713b1edbc | 6733 | uint8_t RESERVED_3[8]; |
AnnaBridge | 171:3a7713b1edbc | 6734 | __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ |
AnnaBridge | 171:3a7713b1edbc | 6735 | __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ |
AnnaBridge | 171:3a7713b1edbc | 6736 | __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ |
AnnaBridge | 171:3a7713b1edbc | 6737 | __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ |
AnnaBridge | 171:3a7713b1edbc | 6738 | __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ |
AnnaBridge | 171:3a7713b1edbc | 6739 | __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ |
AnnaBridge | 171:3a7713b1edbc | 6740 | __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ |
AnnaBridge | 171:3a7713b1edbc | 6741 | __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ |
AnnaBridge | 171:3a7713b1edbc | 6742 | __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ |
AnnaBridge | 171:3a7713b1edbc | 6743 | __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ |
AnnaBridge | 171:3a7713b1edbc | 6744 | __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6745 | } MTB_Type; |
AnnaBridge | 171:3a7713b1edbc | 6746 | |
AnnaBridge | 171:3a7713b1edbc | 6747 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6748 | -- MTB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6749 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6750 | |
AnnaBridge | 171:3a7713b1edbc | 6751 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6752 | * @addtogroup MTB_Register_Masks MTB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6753 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6754 | */ |
AnnaBridge | 171:3a7713b1edbc | 6755 | |
AnnaBridge | 171:3a7713b1edbc | 6756 | /*! @name POSITION - MTB Position Register */ |
AnnaBridge | 171:3a7713b1edbc | 6757 | #define MTB_POSITION_WRAP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6758 | #define MTB_POSITION_WRAP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6759 | #define MTB_POSITION_WRAP(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_WRAP_SHIFT)) & MTB_POSITION_WRAP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6760 | #define MTB_POSITION_POINTER_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 6761 | #define MTB_POSITION_POINTER_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6762 | #define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x)) << MTB_POSITION_POINTER_SHIFT)) & MTB_POSITION_POINTER_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6763 | |
AnnaBridge | 171:3a7713b1edbc | 6764 | /*! @name MASTER - MTB Master Register */ |
AnnaBridge | 171:3a7713b1edbc | 6765 | #define MTB_MASTER_MASK_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 6766 | #define MTB_MASTER_MASK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6767 | #define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_MASK_SHIFT)) & MTB_MASTER_MASK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6768 | #define MTB_MASTER_TSTARTEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 6769 | #define MTB_MASTER_TSTARTEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 6770 | #define MTB_MASTER_TSTARTEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTARTEN_SHIFT)) & MTB_MASTER_TSTARTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6771 | #define MTB_MASTER_TSTOPEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 6772 | #define MTB_MASTER_TSTOPEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 6773 | #define MTB_MASTER_TSTOPEN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_TSTOPEN_SHIFT)) & MTB_MASTER_TSTOPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6774 | #define MTB_MASTER_SFRWPRIV_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 6775 | #define MTB_MASTER_SFRWPRIV_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 6776 | #define MTB_MASTER_SFRWPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_SFRWPRIV_SHIFT)) & MTB_MASTER_SFRWPRIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6777 | #define MTB_MASTER_RAMPRIV_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 6778 | #define MTB_MASTER_RAMPRIV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6779 | #define MTB_MASTER_RAMPRIV(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_RAMPRIV_SHIFT)) & MTB_MASTER_RAMPRIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6780 | #define MTB_MASTER_HALTREQ_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 6781 | #define MTB_MASTER_HALTREQ_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 6782 | #define MTB_MASTER_HALTREQ(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_HALTREQ_SHIFT)) & MTB_MASTER_HALTREQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6783 | #define MTB_MASTER_EN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 6784 | #define MTB_MASTER_EN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 6785 | #define MTB_MASTER_EN(x) (((uint32_t)(((uint32_t)(x)) << MTB_MASTER_EN_SHIFT)) & MTB_MASTER_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6786 | |
AnnaBridge | 171:3a7713b1edbc | 6787 | /*! @name FLOW - MTB Flow Register */ |
AnnaBridge | 171:3a7713b1edbc | 6788 | #define MTB_FLOW_AUTOSTOP_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6789 | #define MTB_FLOW_AUTOSTOP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6790 | #define MTB_FLOW_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOSTOP_SHIFT)) & MTB_FLOW_AUTOSTOP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6791 | #define MTB_FLOW_AUTOHALT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 6792 | #define MTB_FLOW_AUTOHALT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 6793 | #define MTB_FLOW_AUTOHALT(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_AUTOHALT_SHIFT)) & MTB_FLOW_AUTOHALT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6794 | #define MTB_FLOW_WATERMARK_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 6795 | #define MTB_FLOW_WATERMARK_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 6796 | #define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << MTB_FLOW_WATERMARK_SHIFT)) & MTB_FLOW_WATERMARK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6797 | |
AnnaBridge | 171:3a7713b1edbc | 6798 | /*! @name BASE - MTB Base Register */ |
AnnaBridge | 171:3a7713b1edbc | 6799 | #define MTB_BASE_BASEADDR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6800 | #define MTB_BASE_BASEADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6801 | #define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << MTB_BASE_BASEADDR_SHIFT)) & MTB_BASE_BASEADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6802 | |
AnnaBridge | 171:3a7713b1edbc | 6803 | /*! @name MODECTRL - Integration Mode Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 6804 | #define MTB_MODECTRL_MODECTRL_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6805 | #define MTB_MODECTRL_MODECTRL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6806 | #define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x)) << MTB_MODECTRL_MODECTRL_SHIFT)) & MTB_MODECTRL_MODECTRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6807 | |
AnnaBridge | 171:3a7713b1edbc | 6808 | /*! @name TAGSET - Claim TAG Set Register */ |
AnnaBridge | 171:3a7713b1edbc | 6809 | #define MTB_TAGSET_TAGSET_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6810 | #define MTB_TAGSET_TAGSET_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6811 | #define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGSET_TAGSET_SHIFT)) & MTB_TAGSET_TAGSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6812 | |
AnnaBridge | 171:3a7713b1edbc | 6813 | /*! @name TAGCLEAR - Claim TAG Clear Register */ |
AnnaBridge | 171:3a7713b1edbc | 6814 | #define MTB_TAGCLEAR_TAGCLEAR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6815 | #define MTB_TAGCLEAR_TAGCLEAR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6816 | #define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x)) << MTB_TAGCLEAR_TAGCLEAR_SHIFT)) & MTB_TAGCLEAR_TAGCLEAR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6817 | |
AnnaBridge | 171:3a7713b1edbc | 6818 | /*! @name LOCKACCESS - Lock Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 6819 | #define MTB_LOCKACCESS_LOCKACCESS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6820 | #define MTB_LOCKACCESS_LOCKACCESS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6821 | #define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKACCESS_LOCKACCESS_SHIFT)) & MTB_LOCKACCESS_LOCKACCESS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6822 | |
AnnaBridge | 171:3a7713b1edbc | 6823 | /*! @name LOCKSTAT - Lock Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 6824 | #define MTB_LOCKSTAT_LOCKSTAT_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6825 | #define MTB_LOCKSTAT_LOCKSTAT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6826 | #define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x)) << MTB_LOCKSTAT_LOCKSTAT_SHIFT)) & MTB_LOCKSTAT_LOCKSTAT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6827 | |
AnnaBridge | 171:3a7713b1edbc | 6828 | /*! @name AUTHSTAT - Authentication Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 6829 | #define MTB_AUTHSTAT_BIT0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 6830 | #define MTB_AUTHSTAT_BIT0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6831 | #define MTB_AUTHSTAT_BIT0(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT0_SHIFT)) & MTB_AUTHSTAT_BIT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6832 | #define MTB_AUTHSTAT_BIT2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 6833 | #define MTB_AUTHSTAT_BIT2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6834 | #define MTB_AUTHSTAT_BIT2(x) (((uint32_t)(((uint32_t)(x)) << MTB_AUTHSTAT_BIT2_SHIFT)) & MTB_AUTHSTAT_BIT2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6835 | |
AnnaBridge | 171:3a7713b1edbc | 6836 | /*! @name DEVICEARCH - Device Architecture Register */ |
AnnaBridge | 171:3a7713b1edbc | 6837 | #define MTB_DEVICEARCH_DEVICEARCH_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6838 | #define MTB_DEVICEARCH_DEVICEARCH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6839 | #define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICEARCH_DEVICEARCH_SHIFT)) & MTB_DEVICEARCH_DEVICEARCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6840 | |
AnnaBridge | 171:3a7713b1edbc | 6841 | /*! @name DEVICECFG - Device Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 6842 | #define MTB_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6843 | #define MTB_DEVICECFG_DEVICECFG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6844 | #define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICECFG_DEVICECFG_SHIFT)) & MTB_DEVICECFG_DEVICECFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6845 | |
AnnaBridge | 171:3a7713b1edbc | 6846 | /*! @name DEVICETYPID - Device Type Identifier Register */ |
AnnaBridge | 171:3a7713b1edbc | 6847 | #define MTB_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6848 | #define MTB_DEVICETYPID_DEVICETYPID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6849 | #define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_DEVICETYPID_DEVICETYPID_SHIFT)) & MTB_DEVICETYPID_DEVICETYPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6850 | |
AnnaBridge | 171:3a7713b1edbc | 6851 | /*! @name PERIPHID4 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6852 | #define MTB_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6853 | #define MTB_PERIPHID4_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6854 | #define MTB_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID4_PERIPHID_SHIFT)) & MTB_PERIPHID4_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6855 | |
AnnaBridge | 171:3a7713b1edbc | 6856 | /*! @name PERIPHID5 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6857 | #define MTB_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6858 | #define MTB_PERIPHID5_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6859 | #define MTB_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID5_PERIPHID_SHIFT)) & MTB_PERIPHID5_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6860 | |
AnnaBridge | 171:3a7713b1edbc | 6861 | /*! @name PERIPHID6 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6862 | #define MTB_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6863 | #define MTB_PERIPHID6_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6864 | #define MTB_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID6_PERIPHID_SHIFT)) & MTB_PERIPHID6_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6865 | |
AnnaBridge | 171:3a7713b1edbc | 6866 | /*! @name PERIPHID7 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6867 | #define MTB_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6868 | #define MTB_PERIPHID7_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6869 | #define MTB_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID7_PERIPHID_SHIFT)) & MTB_PERIPHID7_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6870 | |
AnnaBridge | 171:3a7713b1edbc | 6871 | /*! @name PERIPHID0 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6872 | #define MTB_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6873 | #define MTB_PERIPHID0_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6874 | #define MTB_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID0_PERIPHID_SHIFT)) & MTB_PERIPHID0_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6875 | |
AnnaBridge | 171:3a7713b1edbc | 6876 | /*! @name PERIPHID1 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6877 | #define MTB_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6878 | #define MTB_PERIPHID1_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6879 | #define MTB_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID1_PERIPHID_SHIFT)) & MTB_PERIPHID1_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6880 | |
AnnaBridge | 171:3a7713b1edbc | 6881 | /*! @name PERIPHID2 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6882 | #define MTB_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6883 | #define MTB_PERIPHID2_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6884 | #define MTB_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID2_PERIPHID_SHIFT)) & MTB_PERIPHID2_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6885 | |
AnnaBridge | 171:3a7713b1edbc | 6886 | /*! @name PERIPHID3 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6887 | #define MTB_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6888 | #define MTB_PERIPHID3_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6889 | #define MTB_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTB_PERIPHID3_PERIPHID_SHIFT)) & MTB_PERIPHID3_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6890 | |
AnnaBridge | 171:3a7713b1edbc | 6891 | /*! @name COMPID - Component ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 6892 | #define MTB_COMPID_COMPID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6893 | #define MTB_COMPID_COMPID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6894 | #define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTB_COMPID_COMPID_SHIFT)) & MTB_COMPID_COMPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6895 | |
AnnaBridge | 171:3a7713b1edbc | 6896 | /* The count of MTB_COMPID */ |
AnnaBridge | 171:3a7713b1edbc | 6897 | #define MTB_COMPID_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 6898 | |
AnnaBridge | 171:3a7713b1edbc | 6899 | |
AnnaBridge | 171:3a7713b1edbc | 6900 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6901 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6902 | */ /* end of group MTB_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 6903 | |
AnnaBridge | 171:3a7713b1edbc | 6904 | |
AnnaBridge | 171:3a7713b1edbc | 6905 | /* MTB - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6906 | /** Peripheral MTB base address */ |
AnnaBridge | 171:3a7713b1edbc | 6907 | #define MTB_BASE (0xF0000000u) |
AnnaBridge | 171:3a7713b1edbc | 6908 | /** Peripheral MTB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 6909 | #define MTB ((MTB_Type *)MTB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 6910 | /** Array initializer of MTB peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 6911 | #define MTB_BASE_ADDRS { MTB_BASE } |
AnnaBridge | 171:3a7713b1edbc | 6912 | /** Array initializer of MTB peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 6913 | #define MTB_BASE_PTRS { MTB } |
AnnaBridge | 171:3a7713b1edbc | 6914 | |
AnnaBridge | 171:3a7713b1edbc | 6915 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6916 | * @} |
AnnaBridge | 171:3a7713b1edbc | 6917 | */ /* end of group MTB_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 6918 | |
AnnaBridge | 171:3a7713b1edbc | 6919 | |
AnnaBridge | 171:3a7713b1edbc | 6920 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6921 | -- MTBDWT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6922 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6923 | |
AnnaBridge | 171:3a7713b1edbc | 6924 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6925 | * @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 6926 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6927 | */ |
AnnaBridge | 171:3a7713b1edbc | 6928 | |
AnnaBridge | 171:3a7713b1edbc | 6929 | /** MTBDWT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 6930 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 6931 | __I uint32_t CTRL; /**< MTB DWT Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 6932 | uint8_t RESERVED_0[28]; |
AnnaBridge | 171:3a7713b1edbc | 6933 | struct { /* offset: 0x20, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 6934 | __IO uint32_t COMP; /**< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 6935 | __IO uint32_t MASK; /**< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 6936 | __IO uint32_t FCT; /**< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 6937 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 6938 | } COMPARATOR[2]; |
AnnaBridge | 171:3a7713b1edbc | 6939 | uint8_t RESERVED_1[448]; |
AnnaBridge | 171:3a7713b1edbc | 6940 | __IO uint32_t TBCTRL; /**< MTB_DWT Trace Buffer Control Register, offset: 0x200 */ |
AnnaBridge | 171:3a7713b1edbc | 6941 | uint8_t RESERVED_2[3524]; |
AnnaBridge | 171:3a7713b1edbc | 6942 | __I uint32_t DEVICECFG; /**< Device Configuration Register, offset: 0xFC8 */ |
AnnaBridge | 171:3a7713b1edbc | 6943 | __I uint32_t DEVICETYPID; /**< Device Type Identifier Register, offset: 0xFCC */ |
AnnaBridge | 171:3a7713b1edbc | 6944 | __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ |
AnnaBridge | 171:3a7713b1edbc | 6945 | __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ |
AnnaBridge | 171:3a7713b1edbc | 6946 | __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ |
AnnaBridge | 171:3a7713b1edbc | 6947 | __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ |
AnnaBridge | 171:3a7713b1edbc | 6948 | __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ |
AnnaBridge | 171:3a7713b1edbc | 6949 | __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ |
AnnaBridge | 171:3a7713b1edbc | 6950 | __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ |
AnnaBridge | 171:3a7713b1edbc | 6951 | __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ |
AnnaBridge | 171:3a7713b1edbc | 6952 | __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 6953 | } MTBDWT_Type; |
AnnaBridge | 171:3a7713b1edbc | 6954 | |
AnnaBridge | 171:3a7713b1edbc | 6955 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 6956 | -- MTBDWT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6957 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 6958 | |
AnnaBridge | 171:3a7713b1edbc | 6959 | /*! |
AnnaBridge | 171:3a7713b1edbc | 6960 | * @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 6961 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 6962 | */ |
AnnaBridge | 171:3a7713b1edbc | 6963 | |
AnnaBridge | 171:3a7713b1edbc | 6964 | /*! @name CTRL - MTB DWT Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 6965 | #define MTBDWT_CTRL_DWTCFGCTRL_MASK (0xFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6966 | #define MTBDWT_CTRL_DWTCFGCTRL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6967 | #define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_DWTCFGCTRL_SHIFT)) & MTBDWT_CTRL_DWTCFGCTRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6968 | #define MTBDWT_CTRL_NUMCMP_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 6969 | #define MTBDWT_CTRL_NUMCMP_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 6970 | #define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_CTRL_NUMCMP_SHIFT)) & MTBDWT_CTRL_NUMCMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6971 | |
AnnaBridge | 171:3a7713b1edbc | 6972 | /*! @name COMP - MTB_DWT Comparator Register */ |
AnnaBridge | 171:3a7713b1edbc | 6973 | #define MTBDWT_COMP_COMP_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 6974 | #define MTBDWT_COMP_COMP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6975 | #define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMP_COMP_SHIFT)) & MTBDWT_COMP_COMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6976 | |
AnnaBridge | 171:3a7713b1edbc | 6977 | /* The count of MTBDWT_COMP */ |
AnnaBridge | 171:3a7713b1edbc | 6978 | #define MTBDWT_COMP_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6979 | |
AnnaBridge | 171:3a7713b1edbc | 6980 | /*! @name MASK - MTB_DWT Comparator Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 6981 | #define MTBDWT_MASK_MASK_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 6982 | #define MTBDWT_MASK_MASK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6983 | #define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_MASK_MASK_SHIFT)) & MTBDWT_MASK_MASK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6984 | |
AnnaBridge | 171:3a7713b1edbc | 6985 | /* The count of MTBDWT_MASK */ |
AnnaBridge | 171:3a7713b1edbc | 6986 | #define MTBDWT_MASK_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 6987 | |
AnnaBridge | 171:3a7713b1edbc | 6988 | /*! @name FCT - MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 6989 | #define MTBDWT_FCT_FUNCTION_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 6990 | #define MTBDWT_FCT_FUNCTION_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 6991 | #define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_FUNCTION_SHIFT)) & MTBDWT_FCT_FUNCTION_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6992 | #define MTBDWT_FCT_DATAVMATCH_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 6993 | #define MTBDWT_FCT_DATAVMATCH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 6994 | #define MTBDWT_FCT_DATAVMATCH(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVMATCH_SHIFT)) & MTBDWT_FCT_DATAVMATCH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6995 | #define MTBDWT_FCT_DATAVSIZE_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 6996 | #define MTBDWT_FCT_DATAVSIZE_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 6997 | #define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVSIZE_SHIFT)) & MTBDWT_FCT_DATAVSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 6998 | #define MTBDWT_FCT_DATAVADDR0_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 6999 | #define MTBDWT_FCT_DATAVADDR0_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7000 | #define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_DATAVADDR0_SHIFT)) & MTBDWT_FCT_DATAVADDR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7001 | #define MTBDWT_FCT_MATCHED_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 7002 | #define MTBDWT_FCT_MATCHED_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7003 | #define MTBDWT_FCT_MATCHED(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_FCT_MATCHED_SHIFT)) & MTBDWT_FCT_MATCHED_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7004 | |
AnnaBridge | 171:3a7713b1edbc | 7005 | /* The count of MTBDWT_FCT */ |
AnnaBridge | 171:3a7713b1edbc | 7006 | #define MTBDWT_FCT_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7007 | |
AnnaBridge | 171:3a7713b1edbc | 7008 | /*! @name TBCTRL - MTB_DWT Trace Buffer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7009 | #define MTBDWT_TBCTRL_ACOMP0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7010 | #define MTBDWT_TBCTRL_ACOMP0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7011 | #define MTBDWT_TBCTRL_ACOMP0(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP0_SHIFT)) & MTBDWT_TBCTRL_ACOMP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7012 | #define MTBDWT_TBCTRL_ACOMP1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7013 | #define MTBDWT_TBCTRL_ACOMP1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7014 | #define MTBDWT_TBCTRL_ACOMP1(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_ACOMP1_SHIFT)) & MTBDWT_TBCTRL_ACOMP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7015 | #define MTBDWT_TBCTRL_NUMCOMP_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 7016 | #define MTBDWT_TBCTRL_NUMCOMP_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 7017 | #define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_TBCTRL_NUMCOMP_SHIFT)) & MTBDWT_TBCTRL_NUMCOMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7018 | |
AnnaBridge | 171:3a7713b1edbc | 7019 | /*! @name DEVICECFG - Device Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7020 | #define MTBDWT_DEVICECFG_DEVICECFG_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7021 | #define MTBDWT_DEVICECFG_DEVICECFG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7022 | #define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICECFG_DEVICECFG_SHIFT)) & MTBDWT_DEVICECFG_DEVICECFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7023 | |
AnnaBridge | 171:3a7713b1edbc | 7024 | /*! @name DEVICETYPID - Device Type Identifier Register */ |
AnnaBridge | 171:3a7713b1edbc | 7025 | #define MTBDWT_DEVICETYPID_DEVICETYPID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7026 | #define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7027 | #define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT)) & MTBDWT_DEVICETYPID_DEVICETYPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7028 | |
AnnaBridge | 171:3a7713b1edbc | 7029 | /*! @name PERIPHID4 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7030 | #define MTBDWT_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7031 | #define MTBDWT_PERIPHID4_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7032 | #define MTBDWT_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID4_PERIPHID_SHIFT)) & MTBDWT_PERIPHID4_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7033 | |
AnnaBridge | 171:3a7713b1edbc | 7034 | /*! @name PERIPHID5 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7035 | #define MTBDWT_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7036 | #define MTBDWT_PERIPHID5_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7037 | #define MTBDWT_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID5_PERIPHID_SHIFT)) & MTBDWT_PERIPHID5_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7038 | |
AnnaBridge | 171:3a7713b1edbc | 7039 | /*! @name PERIPHID6 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7040 | #define MTBDWT_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7041 | #define MTBDWT_PERIPHID6_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7042 | #define MTBDWT_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID6_PERIPHID_SHIFT)) & MTBDWT_PERIPHID6_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7043 | |
AnnaBridge | 171:3a7713b1edbc | 7044 | /*! @name PERIPHID7 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7045 | #define MTBDWT_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7046 | #define MTBDWT_PERIPHID7_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7047 | #define MTBDWT_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID7_PERIPHID_SHIFT)) & MTBDWT_PERIPHID7_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7048 | |
AnnaBridge | 171:3a7713b1edbc | 7049 | /*! @name PERIPHID0 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7050 | #define MTBDWT_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7051 | #define MTBDWT_PERIPHID0_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7052 | #define MTBDWT_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID0_PERIPHID_SHIFT)) & MTBDWT_PERIPHID0_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7053 | |
AnnaBridge | 171:3a7713b1edbc | 7054 | /*! @name PERIPHID1 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7055 | #define MTBDWT_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7056 | #define MTBDWT_PERIPHID1_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7057 | #define MTBDWT_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID1_PERIPHID_SHIFT)) & MTBDWT_PERIPHID1_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7058 | |
AnnaBridge | 171:3a7713b1edbc | 7059 | /*! @name PERIPHID2 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7060 | #define MTBDWT_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7061 | #define MTBDWT_PERIPHID2_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7062 | #define MTBDWT_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID2_PERIPHID_SHIFT)) & MTBDWT_PERIPHID2_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7063 | |
AnnaBridge | 171:3a7713b1edbc | 7064 | /*! @name PERIPHID3 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7065 | #define MTBDWT_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7066 | #define MTBDWT_PERIPHID3_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7067 | #define MTBDWT_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_PERIPHID3_PERIPHID_SHIFT)) & MTBDWT_PERIPHID3_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7068 | |
AnnaBridge | 171:3a7713b1edbc | 7069 | /*! @name COMPID - Component ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 7070 | #define MTBDWT_COMPID_COMPID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7071 | #define MTBDWT_COMPID_COMPID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7072 | #define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << MTBDWT_COMPID_COMPID_SHIFT)) & MTBDWT_COMPID_COMPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7073 | |
AnnaBridge | 171:3a7713b1edbc | 7074 | /* The count of MTBDWT_COMPID */ |
AnnaBridge | 171:3a7713b1edbc | 7075 | #define MTBDWT_COMPID_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7076 | |
AnnaBridge | 171:3a7713b1edbc | 7077 | |
AnnaBridge | 171:3a7713b1edbc | 7078 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7079 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7080 | */ /* end of group MTBDWT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7081 | |
AnnaBridge | 171:3a7713b1edbc | 7082 | |
AnnaBridge | 171:3a7713b1edbc | 7083 | /* MTBDWT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7084 | /** Peripheral MTBDWT base address */ |
AnnaBridge | 171:3a7713b1edbc | 7085 | #define MTBDWT_BASE (0xF0001000u) |
AnnaBridge | 171:3a7713b1edbc | 7086 | /** Peripheral MTBDWT base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7087 | #define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7088 | /** Array initializer of MTBDWT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7089 | #define MTBDWT_BASE_ADDRS { MTBDWT_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7090 | /** Array initializer of MTBDWT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7091 | #define MTBDWT_BASE_PTRS { MTBDWT } |
AnnaBridge | 171:3a7713b1edbc | 7092 | |
AnnaBridge | 171:3a7713b1edbc | 7093 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7094 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7095 | */ /* end of group MTBDWT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7096 | |
AnnaBridge | 171:3a7713b1edbc | 7097 | |
AnnaBridge | 171:3a7713b1edbc | 7098 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7099 | -- NV Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7100 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7101 | |
AnnaBridge | 171:3a7713b1edbc | 7102 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7103 | * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7104 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7105 | */ |
AnnaBridge | 171:3a7713b1edbc | 7106 | |
AnnaBridge | 171:3a7713b1edbc | 7107 | /** NV - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7108 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7109 | __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7110 | __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 7111 | __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 7112 | __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 7113 | __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7114 | __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 7115 | __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 7116 | __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 7117 | __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7118 | __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 7119 | __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 7120 | __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 7121 | __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 7122 | __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */ |
AnnaBridge | 171:3a7713b1edbc | 7123 | } NV_Type; |
AnnaBridge | 171:3a7713b1edbc | 7124 | |
AnnaBridge | 171:3a7713b1edbc | 7125 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7126 | -- NV Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7127 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7128 | |
AnnaBridge | 171:3a7713b1edbc | 7129 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7130 | * @addtogroup NV_Register_Masks NV Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7131 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7132 | */ |
AnnaBridge | 171:3a7713b1edbc | 7133 | |
AnnaBridge | 171:3a7713b1edbc | 7134 | /*! @name BACKKEY3 - Backdoor Comparison Key 3. */ |
AnnaBridge | 171:3a7713b1edbc | 7135 | #define NV_BACKKEY3_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7136 | #define NV_BACKKEY3_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7137 | #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7138 | |
AnnaBridge | 171:3a7713b1edbc | 7139 | /*! @name BACKKEY2 - Backdoor Comparison Key 2. */ |
AnnaBridge | 171:3a7713b1edbc | 7140 | #define NV_BACKKEY2_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7141 | #define NV_BACKKEY2_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7142 | #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7143 | |
AnnaBridge | 171:3a7713b1edbc | 7144 | /*! @name BACKKEY1 - Backdoor Comparison Key 1. */ |
AnnaBridge | 171:3a7713b1edbc | 7145 | #define NV_BACKKEY1_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7146 | #define NV_BACKKEY1_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7147 | #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7148 | |
AnnaBridge | 171:3a7713b1edbc | 7149 | /*! @name BACKKEY0 - Backdoor Comparison Key 0. */ |
AnnaBridge | 171:3a7713b1edbc | 7150 | #define NV_BACKKEY0_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7151 | #define NV_BACKKEY0_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7152 | #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7153 | |
AnnaBridge | 171:3a7713b1edbc | 7154 | /*! @name BACKKEY7 - Backdoor Comparison Key 7. */ |
AnnaBridge | 171:3a7713b1edbc | 7155 | #define NV_BACKKEY7_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7156 | #define NV_BACKKEY7_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7157 | #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7158 | |
AnnaBridge | 171:3a7713b1edbc | 7159 | /*! @name BACKKEY6 - Backdoor Comparison Key 6. */ |
AnnaBridge | 171:3a7713b1edbc | 7160 | #define NV_BACKKEY6_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7161 | #define NV_BACKKEY6_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7162 | #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7163 | |
AnnaBridge | 171:3a7713b1edbc | 7164 | /*! @name BACKKEY5 - Backdoor Comparison Key 5. */ |
AnnaBridge | 171:3a7713b1edbc | 7165 | #define NV_BACKKEY5_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7166 | #define NV_BACKKEY5_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7167 | #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7168 | |
AnnaBridge | 171:3a7713b1edbc | 7169 | /*! @name BACKKEY4 - Backdoor Comparison Key 4. */ |
AnnaBridge | 171:3a7713b1edbc | 7170 | #define NV_BACKKEY4_KEY_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7171 | #define NV_BACKKEY4_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7172 | #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7173 | |
AnnaBridge | 171:3a7713b1edbc | 7174 | /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 7175 | #define NV_FPROT3_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7176 | #define NV_FPROT3_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7177 | #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7178 | |
AnnaBridge | 171:3a7713b1edbc | 7179 | /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */ |
AnnaBridge | 171:3a7713b1edbc | 7180 | #define NV_FPROT2_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7181 | #define NV_FPROT2_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7182 | #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7183 | |
AnnaBridge | 171:3a7713b1edbc | 7184 | /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 7185 | #define NV_FPROT1_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7186 | #define NV_FPROT1_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7187 | #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7188 | |
AnnaBridge | 171:3a7713b1edbc | 7189 | /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */ |
AnnaBridge | 171:3a7713b1edbc | 7190 | #define NV_FPROT0_PROT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 7191 | #define NV_FPROT0_PROT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7192 | #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7193 | |
AnnaBridge | 171:3a7713b1edbc | 7194 | /*! @name FSEC - Non-volatile Flash Security Register */ |
AnnaBridge | 171:3a7713b1edbc | 7195 | #define NV_FSEC_SEC_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7196 | #define NV_FSEC_SEC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7197 | #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7198 | #define NV_FSEC_FSLACC_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7199 | #define NV_FSEC_FSLACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7200 | #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7201 | #define NV_FSEC_MEEN_MASK (0x30U) |
AnnaBridge | 171:3a7713b1edbc | 7202 | #define NV_FSEC_MEEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7203 | #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7204 | #define NV_FSEC_KEYEN_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7205 | #define NV_FSEC_KEYEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7206 | #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7207 | |
AnnaBridge | 171:3a7713b1edbc | 7208 | /*! @name FOPT - Non-volatile Flash Option Register */ |
AnnaBridge | 171:3a7713b1edbc | 7209 | #define NV_FOPT_LPBOOT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7210 | #define NV_FOPT_LPBOOT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7211 | #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7212 | #define NV_FOPT_BOOTPIN_OPT_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7213 | #define NV_FOPT_BOOTPIN_OPT_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7214 | #define NV_FOPT_BOOTPIN_OPT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTPIN_OPT_SHIFT)) & NV_FOPT_BOOTPIN_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7215 | #define NV_FOPT_NMI_DIS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7216 | #define NV_FOPT_NMI_DIS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7217 | #define NV_FOPT_NMI_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7218 | #define NV_FOPT_FAST_INIT_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7219 | #define NV_FOPT_FAST_INIT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7220 | #define NV_FOPT_FAST_INIT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_FAST_INIT_SHIFT)) & NV_FOPT_FAST_INIT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7221 | #define NV_FOPT_BOOTSRC_SEL_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7222 | #define NV_FOPT_BOOTSRC_SEL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7223 | #define NV_FOPT_BOOTSRC_SEL(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_BOOTSRC_SEL_SHIFT)) & NV_FOPT_BOOTSRC_SEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7224 | |
AnnaBridge | 171:3a7713b1edbc | 7225 | |
AnnaBridge | 171:3a7713b1edbc | 7226 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7227 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7228 | */ /* end of group NV_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7229 | |
AnnaBridge | 171:3a7713b1edbc | 7230 | |
AnnaBridge | 171:3a7713b1edbc | 7231 | /* NV - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7232 | /** Peripheral FTFA_FlashConfig base address */ |
AnnaBridge | 171:3a7713b1edbc | 7233 | #define FTFA_FlashConfig_BASE (0x400u) |
AnnaBridge | 171:3a7713b1edbc | 7234 | /** Peripheral FTFA_FlashConfig base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7235 | #define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7236 | /** Array initializer of NV peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7237 | #define NV_BASE_ADDRS { FTFA_FlashConfig_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7238 | /** Array initializer of NV peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7239 | #define NV_BASE_PTRS { FTFA_FlashConfig } |
AnnaBridge | 171:3a7713b1edbc | 7240 | |
AnnaBridge | 171:3a7713b1edbc | 7241 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7242 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7243 | */ /* end of group NV_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7244 | |
AnnaBridge | 171:3a7713b1edbc | 7245 | |
AnnaBridge | 171:3a7713b1edbc | 7246 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7247 | -- OSC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7248 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7249 | |
AnnaBridge | 171:3a7713b1edbc | 7250 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7251 | * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7252 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7253 | */ |
AnnaBridge | 171:3a7713b1edbc | 7254 | |
AnnaBridge | 171:3a7713b1edbc | 7255 | /** OSC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7256 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7257 | __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7258 | uint8_t RESERVED_0[1]; |
AnnaBridge | 171:3a7713b1edbc | 7259 | __IO uint8_t DIV; /**< OSC_DIV, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 7260 | } OSC_Type; |
AnnaBridge | 171:3a7713b1edbc | 7261 | |
AnnaBridge | 171:3a7713b1edbc | 7262 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7263 | -- OSC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7264 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7265 | |
AnnaBridge | 171:3a7713b1edbc | 7266 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7267 | * @addtogroup OSC_Register_Masks OSC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7268 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7269 | */ |
AnnaBridge | 171:3a7713b1edbc | 7270 | |
AnnaBridge | 171:3a7713b1edbc | 7271 | /*! @name CR - OSC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7272 | #define OSC_CR_SC16P_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7273 | #define OSC_CR_SC16P_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7274 | #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7275 | #define OSC_CR_SC8P_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7276 | #define OSC_CR_SC8P_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7277 | #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7278 | #define OSC_CR_SC4P_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7279 | #define OSC_CR_SC4P_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7280 | #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7281 | #define OSC_CR_SC2P_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7282 | #define OSC_CR_SC2P_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7283 | #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7284 | #define OSC_CR_EREFSTEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7285 | #define OSC_CR_EREFSTEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7286 | #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7287 | #define OSC_CR_ERCLKEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7288 | #define OSC_CR_ERCLKEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7289 | #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7290 | |
AnnaBridge | 171:3a7713b1edbc | 7291 | /*! @name DIV - OSC_DIV */ |
AnnaBridge | 171:3a7713b1edbc | 7292 | #define OSC_DIV_ERPS_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 7293 | #define OSC_DIV_ERPS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7294 | #define OSC_DIV_ERPS(x) (((uint8_t)(((uint8_t)(x)) << OSC_DIV_ERPS_SHIFT)) & OSC_DIV_ERPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7295 | |
AnnaBridge | 171:3a7713b1edbc | 7296 | |
AnnaBridge | 171:3a7713b1edbc | 7297 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7298 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7299 | */ /* end of group OSC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7300 | |
AnnaBridge | 171:3a7713b1edbc | 7301 | |
AnnaBridge | 171:3a7713b1edbc | 7302 | /* OSC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7303 | /** Peripheral OSC base address */ |
AnnaBridge | 171:3a7713b1edbc | 7304 | #define OSC_BASE (0x40065000u) |
AnnaBridge | 171:3a7713b1edbc | 7305 | /** Peripheral OSC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7306 | #define OSC ((OSC_Type *)OSC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7307 | /** Array initializer of OSC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7308 | #define OSC_BASE_ADDRS { OSC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7309 | /** Array initializer of OSC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7310 | #define OSC_BASE_PTRS { OSC } |
AnnaBridge | 171:3a7713b1edbc | 7311 | |
AnnaBridge | 171:3a7713b1edbc | 7312 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7313 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7314 | */ /* end of group OSC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7315 | |
AnnaBridge | 171:3a7713b1edbc | 7316 | |
AnnaBridge | 171:3a7713b1edbc | 7317 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7318 | -- PIT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7319 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7320 | |
AnnaBridge | 171:3a7713b1edbc | 7321 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7322 | * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7323 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7324 | */ |
AnnaBridge | 171:3a7713b1edbc | 7325 | |
AnnaBridge | 171:3a7713b1edbc | 7326 | /** PIT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7327 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7328 | __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7329 | uint8_t RESERVED_0[220]; |
AnnaBridge | 171:3a7713b1edbc | 7330 | __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ |
AnnaBridge | 171:3a7713b1edbc | 7331 | __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ |
AnnaBridge | 171:3a7713b1edbc | 7332 | uint8_t RESERVED_1[24]; |
AnnaBridge | 171:3a7713b1edbc | 7333 | struct { /* offset: 0x100, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7334 | __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7335 | __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7336 | __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7337 | __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7338 | } CHANNEL[4]; |
AnnaBridge | 171:3a7713b1edbc | 7339 | } PIT_Type; |
AnnaBridge | 171:3a7713b1edbc | 7340 | |
AnnaBridge | 171:3a7713b1edbc | 7341 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7342 | -- PIT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7343 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7344 | |
AnnaBridge | 171:3a7713b1edbc | 7345 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7346 | * @addtogroup PIT_Register_Masks PIT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7347 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7348 | */ |
AnnaBridge | 171:3a7713b1edbc | 7349 | |
AnnaBridge | 171:3a7713b1edbc | 7350 | /*! @name MCR - PIT Module Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7351 | #define PIT_MCR_FRZ_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7352 | #define PIT_MCR_FRZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7353 | #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7354 | #define PIT_MCR_MDIS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7355 | #define PIT_MCR_MDIS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7356 | #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7357 | |
AnnaBridge | 171:3a7713b1edbc | 7358 | /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ |
AnnaBridge | 171:3a7713b1edbc | 7359 | #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7360 | #define PIT_LTMR64H_LTH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7361 | #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7362 | |
AnnaBridge | 171:3a7713b1edbc | 7363 | /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ |
AnnaBridge | 171:3a7713b1edbc | 7364 | #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7365 | #define PIT_LTMR64L_LTL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7366 | #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7367 | |
AnnaBridge | 171:3a7713b1edbc | 7368 | /*! @name LDVAL - Timer Load Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 7369 | #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7370 | #define PIT_LDVAL_TSV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7371 | #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7372 | |
AnnaBridge | 171:3a7713b1edbc | 7373 | /* The count of PIT_LDVAL */ |
AnnaBridge | 171:3a7713b1edbc | 7374 | #define PIT_LDVAL_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7375 | |
AnnaBridge | 171:3a7713b1edbc | 7376 | /*! @name CVAL - Current Timer Value Register */ |
AnnaBridge | 171:3a7713b1edbc | 7377 | #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7378 | #define PIT_CVAL_TVL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7379 | #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7380 | |
AnnaBridge | 171:3a7713b1edbc | 7381 | /* The count of PIT_CVAL */ |
AnnaBridge | 171:3a7713b1edbc | 7382 | #define PIT_CVAL_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7383 | |
AnnaBridge | 171:3a7713b1edbc | 7384 | /*! @name TCTRL - Timer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7385 | #define PIT_TCTRL_TEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7386 | #define PIT_TCTRL_TEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7387 | #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7388 | #define PIT_TCTRL_TIE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7389 | #define PIT_TCTRL_TIE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7390 | #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7391 | #define PIT_TCTRL_CHN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7392 | #define PIT_TCTRL_CHN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7393 | #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7394 | |
AnnaBridge | 171:3a7713b1edbc | 7395 | /* The count of PIT_TCTRL */ |
AnnaBridge | 171:3a7713b1edbc | 7396 | #define PIT_TCTRL_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7397 | |
AnnaBridge | 171:3a7713b1edbc | 7398 | /*! @name TFLG - Timer Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 7399 | #define PIT_TFLG_TIF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7400 | #define PIT_TFLG_TIF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7401 | #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7402 | |
AnnaBridge | 171:3a7713b1edbc | 7403 | /* The count of PIT_TFLG */ |
AnnaBridge | 171:3a7713b1edbc | 7404 | #define PIT_TFLG_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7405 | |
AnnaBridge | 171:3a7713b1edbc | 7406 | |
AnnaBridge | 171:3a7713b1edbc | 7407 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7408 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7409 | */ /* end of group PIT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7410 | |
AnnaBridge | 171:3a7713b1edbc | 7411 | |
AnnaBridge | 171:3a7713b1edbc | 7412 | /* PIT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7413 | /** Peripheral PIT0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 7414 | #define PIT0_BASE (0x40037000u) |
AnnaBridge | 171:3a7713b1edbc | 7415 | /** Peripheral PIT0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7416 | #define PIT0 ((PIT_Type *)PIT0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7417 | /** Array initializer of PIT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7418 | #define PIT_BASE_ADDRS { PIT0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7419 | /** Array initializer of PIT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7420 | #define PIT_BASE_PTRS { PIT0 } |
AnnaBridge | 171:3a7713b1edbc | 7421 | /** Interrupt vectors for the PIT peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 7422 | #define PIT_IRQS { PIT0_IRQn, PIT0_IRQn, PIT0_IRQn, PIT0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 7423 | |
AnnaBridge | 171:3a7713b1edbc | 7424 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7425 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7426 | */ /* end of group PIT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7427 | |
AnnaBridge | 171:3a7713b1edbc | 7428 | |
AnnaBridge | 171:3a7713b1edbc | 7429 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7430 | -- PMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7431 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7432 | |
AnnaBridge | 171:3a7713b1edbc | 7433 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7434 | * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7435 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7436 | */ |
AnnaBridge | 171:3a7713b1edbc | 7437 | |
AnnaBridge | 171:3a7713b1edbc | 7438 | /** PMC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7439 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7440 | __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7441 | __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 7442 | __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 7443 | uint8_t RESERVED_0[8]; |
AnnaBridge | 171:3a7713b1edbc | 7444 | __IO uint8_t HVDSC1; /**< High Voltage Detect Status And Control 1 register, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 7445 | } PMC_Type; |
AnnaBridge | 171:3a7713b1edbc | 7446 | |
AnnaBridge | 171:3a7713b1edbc | 7447 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7448 | -- PMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7449 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7450 | |
AnnaBridge | 171:3a7713b1edbc | 7451 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7452 | * @addtogroup PMC_Register_Masks PMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7453 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7454 | */ |
AnnaBridge | 171:3a7713b1edbc | 7455 | |
AnnaBridge | 171:3a7713b1edbc | 7456 | /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 7457 | #define PMC_LVDSC1_LVDV_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7458 | #define PMC_LVDSC1_LVDV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7459 | #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7460 | #define PMC_LVDSC1_LVDRE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7461 | #define PMC_LVDSC1_LVDRE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7462 | #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7463 | #define PMC_LVDSC1_LVDIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7464 | #define PMC_LVDSC1_LVDIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7465 | #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7466 | #define PMC_LVDSC1_LVDACK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7467 | #define PMC_LVDSC1_LVDACK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7468 | #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7469 | #define PMC_LVDSC1_LVDF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7470 | #define PMC_LVDSC1_LVDF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7471 | #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7472 | |
AnnaBridge | 171:3a7713b1edbc | 7473 | /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */ |
AnnaBridge | 171:3a7713b1edbc | 7474 | #define PMC_LVDSC2_LVWV_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 7475 | #define PMC_LVDSC2_LVWV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7476 | #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7477 | #define PMC_LVDSC2_LVWIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7478 | #define PMC_LVDSC2_LVWIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7479 | #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7480 | #define PMC_LVDSC2_LVWACK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7481 | #define PMC_LVDSC2_LVWACK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7482 | #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7483 | #define PMC_LVDSC2_LVWF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7484 | #define PMC_LVDSC2_LVWF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7485 | #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7486 | |
AnnaBridge | 171:3a7713b1edbc | 7487 | /*! @name REGSC - Regulator Status And Control register */ |
AnnaBridge | 171:3a7713b1edbc | 7488 | #define PMC_REGSC_BGBE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7489 | #define PMC_REGSC_BGBE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7490 | #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7491 | #define PMC_REGSC_REGONS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7492 | #define PMC_REGSC_REGONS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7493 | #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7494 | #define PMC_REGSC_ACKISO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 7495 | #define PMC_REGSC_ACKISO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7496 | #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7497 | #define PMC_REGSC_BGEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7498 | #define PMC_REGSC_BGEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7499 | #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7500 | #define PMC_REGSC_VLPO_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7501 | #define PMC_REGSC_VLPO_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7502 | #define PMC_REGSC_VLPO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_VLPO_SHIFT)) & PMC_REGSC_VLPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7503 | |
AnnaBridge | 171:3a7713b1edbc | 7504 | /*! @name HVDSC1 - High Voltage Detect Status And Control 1 register */ |
AnnaBridge | 171:3a7713b1edbc | 7505 | #define PMC_HVDSC1_HVDV_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7506 | #define PMC_HVDSC1_HVDV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7507 | #define PMC_HVDSC1_HVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDV_SHIFT)) & PMC_HVDSC1_HVDV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7508 | #define PMC_HVDSC1_HVDRE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7509 | #define PMC_HVDSC1_HVDRE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7510 | #define PMC_HVDSC1_HVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDRE_SHIFT)) & PMC_HVDSC1_HVDRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7511 | #define PMC_HVDSC1_HVDIE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7512 | #define PMC_HVDSC1_HVDIE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7513 | #define PMC_HVDSC1_HVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDIE_SHIFT)) & PMC_HVDSC1_HVDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7514 | #define PMC_HVDSC1_HVDACK_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7515 | #define PMC_HVDSC1_HVDACK_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7516 | #define PMC_HVDSC1_HVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDACK_SHIFT)) & PMC_HVDSC1_HVDACK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7517 | #define PMC_HVDSC1_HVDF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7518 | #define PMC_HVDSC1_HVDF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7519 | #define PMC_HVDSC1_HVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_HVDSC1_HVDF_SHIFT)) & PMC_HVDSC1_HVDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7520 | |
AnnaBridge | 171:3a7713b1edbc | 7521 | |
AnnaBridge | 171:3a7713b1edbc | 7522 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7523 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7524 | */ /* end of group PMC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7525 | |
AnnaBridge | 171:3a7713b1edbc | 7526 | |
AnnaBridge | 171:3a7713b1edbc | 7527 | /* PMC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7528 | /** Peripheral PMC base address */ |
AnnaBridge | 171:3a7713b1edbc | 7529 | #define PMC_BASE (0x4007D000u) |
AnnaBridge | 171:3a7713b1edbc | 7530 | /** Peripheral PMC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7531 | #define PMC ((PMC_Type *)PMC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7532 | /** Array initializer of PMC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7533 | #define PMC_BASE_ADDRS { PMC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7534 | /** Array initializer of PMC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7535 | #define PMC_BASE_PTRS { PMC } |
AnnaBridge | 171:3a7713b1edbc | 7536 | /** Interrupt vectors for the PMC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 7537 | #define PMC_IRQS { PMC_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 7538 | |
AnnaBridge | 171:3a7713b1edbc | 7539 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7540 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7541 | */ /* end of group PMC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7542 | |
AnnaBridge | 171:3a7713b1edbc | 7543 | |
AnnaBridge | 171:3a7713b1edbc | 7544 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7545 | -- PORT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7546 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7547 | |
AnnaBridge | 171:3a7713b1edbc | 7548 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7549 | * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7550 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7551 | */ |
AnnaBridge | 171:3a7713b1edbc | 7552 | |
AnnaBridge | 171:3a7713b1edbc | 7553 | /** PORT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7554 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7555 | __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7556 | __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 7557 | __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 7558 | __O uint32_t GICLR; /**< Global Interrupt Control Low Register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 7559 | __O uint32_t GICHR; /**< Global Interrupt Control High Register, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 7560 | uint8_t RESERVED_0[16]; |
AnnaBridge | 171:3a7713b1edbc | 7561 | __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */ |
AnnaBridge | 171:3a7713b1edbc | 7562 | } PORT_Type; |
AnnaBridge | 171:3a7713b1edbc | 7563 | |
AnnaBridge | 171:3a7713b1edbc | 7564 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7565 | -- PORT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7566 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7567 | |
AnnaBridge | 171:3a7713b1edbc | 7568 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7569 | * @addtogroup PORT_Register_Masks PORT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7570 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7571 | */ |
AnnaBridge | 171:3a7713b1edbc | 7572 | |
AnnaBridge | 171:3a7713b1edbc | 7573 | /*! @name PCR - Pin Control Register n */ |
AnnaBridge | 171:3a7713b1edbc | 7574 | #define PORT_PCR_PS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7575 | #define PORT_PCR_PS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7576 | #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7577 | #define PORT_PCR_PE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7578 | #define PORT_PCR_PE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7579 | #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7580 | #define PORT_PCR_SRE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7581 | #define PORT_PCR_SRE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7582 | #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7583 | #define PORT_PCR_PFE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 7584 | #define PORT_PCR_PFE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 7585 | #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7586 | #define PORT_PCR_ODE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7587 | #define PORT_PCR_ODE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7588 | #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7589 | #define PORT_PCR_MUX_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 7590 | #define PORT_PCR_MUX_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7591 | #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7592 | #define PORT_PCR_LK_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 7593 | #define PORT_PCR_LK_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 7594 | #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7595 | #define PORT_PCR_IRQC_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7596 | #define PORT_PCR_IRQC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7597 | #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7598 | #define PORT_PCR_ISF_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 7599 | #define PORT_PCR_ISF_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7600 | #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7601 | |
AnnaBridge | 171:3a7713b1edbc | 7602 | /* The count of PORT_PCR */ |
AnnaBridge | 171:3a7713b1edbc | 7603 | #define PORT_PCR_COUNT (32U) |
AnnaBridge | 171:3a7713b1edbc | 7604 | |
AnnaBridge | 171:3a7713b1edbc | 7605 | /*! @name GPCLR - Global Pin Control Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 7606 | #define PORT_GPCLR_GPWD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7607 | #define PORT_GPCLR_GPWD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7608 | #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7609 | #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7610 | #define PORT_GPCLR_GPWE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7611 | #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7612 | |
AnnaBridge | 171:3a7713b1edbc | 7613 | /*! @name GPCHR - Global Pin Control High Register */ |
AnnaBridge | 171:3a7713b1edbc | 7614 | #define PORT_GPCHR_GPWD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7615 | #define PORT_GPCHR_GPWD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7616 | #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7617 | #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7618 | #define PORT_GPCHR_GPWE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7619 | #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7620 | |
AnnaBridge | 171:3a7713b1edbc | 7621 | /*! @name GICLR - Global Interrupt Control Low Register */ |
AnnaBridge | 171:3a7713b1edbc | 7622 | #define PORT_GICLR_GIWE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7623 | #define PORT_GICLR_GIWE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7624 | #define PORT_GICLR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWE_SHIFT)) & PORT_GICLR_GIWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7625 | #define PORT_GICLR_GIWD_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7626 | #define PORT_GICLR_GIWD_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7627 | #define PORT_GICLR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICLR_GIWD_SHIFT)) & PORT_GICLR_GIWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7628 | |
AnnaBridge | 171:3a7713b1edbc | 7629 | /*! @name GICHR - Global Interrupt Control High Register */ |
AnnaBridge | 171:3a7713b1edbc | 7630 | #define PORT_GICHR_GIWE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7631 | #define PORT_GICHR_GIWE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7632 | #define PORT_GICHR_GIWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWE_SHIFT)) & PORT_GICHR_GIWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7633 | #define PORT_GICHR_GIWD_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7634 | #define PORT_GICHR_GIWD_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7635 | #define PORT_GICHR_GIWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GICHR_GIWD_SHIFT)) & PORT_GICHR_GIWD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7636 | |
AnnaBridge | 171:3a7713b1edbc | 7637 | /*! @name ISFR - Interrupt Status Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 7638 | #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7639 | #define PORT_ISFR_ISF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7640 | #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7641 | |
AnnaBridge | 171:3a7713b1edbc | 7642 | |
AnnaBridge | 171:3a7713b1edbc | 7643 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7644 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7645 | */ /* end of group PORT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 7646 | |
AnnaBridge | 171:3a7713b1edbc | 7647 | |
AnnaBridge | 171:3a7713b1edbc | 7648 | /* PORT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7649 | /** Peripheral PORTA base address */ |
AnnaBridge | 171:3a7713b1edbc | 7650 | #define PORTA_BASE (0x40049000u) |
AnnaBridge | 171:3a7713b1edbc | 7651 | /** Peripheral PORTA base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7652 | #define PORTA ((PORT_Type *)PORTA_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7653 | /** Peripheral PORTB base address */ |
AnnaBridge | 171:3a7713b1edbc | 7654 | #define PORTB_BASE (0x4004A000u) |
AnnaBridge | 171:3a7713b1edbc | 7655 | /** Peripheral PORTB base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7656 | #define PORTB ((PORT_Type *)PORTB_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7657 | /** Peripheral PORTC base address */ |
AnnaBridge | 171:3a7713b1edbc | 7658 | #define PORTC_BASE (0x4004B000u) |
AnnaBridge | 171:3a7713b1edbc | 7659 | /** Peripheral PORTC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7660 | #define PORTC ((PORT_Type *)PORTC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7661 | /** Peripheral PORTD base address */ |
AnnaBridge | 171:3a7713b1edbc | 7662 | #define PORTD_BASE (0x4004C000u) |
AnnaBridge | 171:3a7713b1edbc | 7663 | /** Peripheral PORTD base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7664 | #define PORTD ((PORT_Type *)PORTD_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7665 | /** Peripheral PORTE base address */ |
AnnaBridge | 171:3a7713b1edbc | 7666 | #define PORTE_BASE (0x4004D000u) |
AnnaBridge | 171:3a7713b1edbc | 7667 | /** Peripheral PORTE base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 7668 | #define PORTE ((PORT_Type *)PORTE_BASE) |
AnnaBridge | 171:3a7713b1edbc | 7669 | /** Array initializer of PORT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 7670 | #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE } |
AnnaBridge | 171:3a7713b1edbc | 7671 | /** Array initializer of PORT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 7672 | #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE } |
AnnaBridge | 171:3a7713b1edbc | 7673 | /** Interrupt vectors for the PORT peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 7674 | #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 7675 | |
AnnaBridge | 171:3a7713b1edbc | 7676 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7677 | * @} |
AnnaBridge | 171:3a7713b1edbc | 7678 | */ /* end of group PORT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 7679 | |
AnnaBridge | 171:3a7713b1edbc | 7680 | |
AnnaBridge | 171:3a7713b1edbc | 7681 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7682 | -- QuadSPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7683 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7684 | |
AnnaBridge | 171:3a7713b1edbc | 7685 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7686 | * @addtogroup QuadSPI_Peripheral_Access_Layer QuadSPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 7687 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7688 | */ |
AnnaBridge | 171:3a7713b1edbc | 7689 | |
AnnaBridge | 171:3a7713b1edbc | 7690 | /** QuadSPI - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 7691 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 7692 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 7693 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 7694 | union { /* offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7695 | __IO uint32_t IPCR; /**< IP Configuration Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7696 | struct { |
AnnaBridge | 171:3a7713b1edbc | 7697 | __IO uint16_t IDATZ; /**< IP data transfer size, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 7698 | __IO uint8_t PAR_EN; /**< IP data transfer size, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 7699 | __IO uint8_t SEQID; /**< IP data transfer size, offset: 0xB */ |
AnnaBridge | 171:3a7713b1edbc | 7700 | } IPCR_ACCESSBIT; |
AnnaBridge | 171:3a7713b1edbc | 7701 | }; |
AnnaBridge | 171:3a7713b1edbc | 7702 | __IO uint32_t FLSHCR; /**< Flash Configuration Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 7703 | __IO uint32_t BUF0CR; /**< Buffer0 Configuration Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 7704 | __IO uint32_t BUF1CR; /**< Buffer1 Configuration Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 7705 | __IO uint32_t BUF2CR; /**< Buffer2 Configuration Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 7706 | __IO uint32_t BUF3CR; /**< Buffer3 Configuration Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 7707 | __IO uint32_t BFGENCR; /**< Buffer Generic Configuration Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 7708 | __IO uint32_t SOCCR; /**< SOC Configuration Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 7709 | uint8_t RESERVED_1[8]; |
AnnaBridge | 171:3a7713b1edbc | 7710 | __IO uint32_t BUF0IND; /**< Buffer0 Top Index Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 7711 | __IO uint32_t BUF1IND; /**< Buffer1 Top Index Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 7712 | __IO uint32_t BUF2IND; /**< Buffer2 Top Index Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 7713 | uint8_t RESERVED_2[196]; |
AnnaBridge | 171:3a7713b1edbc | 7714 | __IO uint32_t SFAR; /**< Serial Flash Address Register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 7715 | __IO uint32_t SFACR; /**< Serial Flash Address Configuration Register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 7716 | __IO uint32_t SMPR; /**< Sampling Register, offset: 0x108 */ |
AnnaBridge | 171:3a7713b1edbc | 7717 | __I uint32_t RBSR; /**< RX Buffer Status Register, offset: 0x10C */ |
AnnaBridge | 171:3a7713b1edbc | 7718 | __IO uint32_t RBCT; /**< RX Buffer Control Register, offset: 0x110 */ |
AnnaBridge | 171:3a7713b1edbc | 7719 | uint8_t RESERVED_3[60]; |
AnnaBridge | 171:3a7713b1edbc | 7720 | __I uint32_t TBSR; /**< TX Buffer Status Register, offset: 0x150 */ |
AnnaBridge | 171:3a7713b1edbc | 7721 | __IO uint32_t TBDR; /**< TX Buffer Data Register, offset: 0x154 */ |
AnnaBridge | 171:3a7713b1edbc | 7722 | __IO uint32_t TBCT; /**< Tx Buffer Control Register, offset: 0x158 */ |
AnnaBridge | 171:3a7713b1edbc | 7723 | __I uint32_t SR; /**< Status Register, offset: 0x15C */ |
AnnaBridge | 171:3a7713b1edbc | 7724 | __IO uint32_t FR; /**< Flag Register, offset: 0x160 */ |
AnnaBridge | 171:3a7713b1edbc | 7725 | __IO uint32_t RSER; /**< Interrupt and DMA Request Select and Enable Register, offset: 0x164 */ |
AnnaBridge | 171:3a7713b1edbc | 7726 | __I uint32_t SPNDST; /**< Sequence Suspend Status Register, offset: 0x168 */ |
AnnaBridge | 171:3a7713b1edbc | 7727 | __IO uint32_t SPTRCLR; /**< Sequence Pointer Clear Register, offset: 0x16C */ |
AnnaBridge | 171:3a7713b1edbc | 7728 | uint8_t RESERVED_4[16]; |
AnnaBridge | 171:3a7713b1edbc | 7729 | __IO uint32_t SFA1AD; /**< Serial Flash A1 Top Address, offset: 0x180 */ |
AnnaBridge | 171:3a7713b1edbc | 7730 | __IO uint32_t SFA2AD; /**< Serial Flash A2 Top Address, offset: 0x184 */ |
AnnaBridge | 171:3a7713b1edbc | 7731 | __IO uint32_t SFB1AD; /**< Serial Flash B1Top Address, offset: 0x188 */ |
AnnaBridge | 171:3a7713b1edbc | 7732 | __IO uint32_t SFB2AD; /**< Serial Flash B2Top Address, offset: 0x18C */ |
AnnaBridge | 171:3a7713b1edbc | 7733 | __IO uint32_t DLPR; /**< Data Learn Pattern Register, offset: 0x190 */ |
AnnaBridge | 171:3a7713b1edbc | 7734 | uint8_t RESERVED_5[108]; |
AnnaBridge | 171:3a7713b1edbc | 7735 | __I uint32_t RBDR[16]; /**< RX Buffer Data Register, array offset: 0x200, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7736 | uint8_t RESERVED_6[192]; |
AnnaBridge | 171:3a7713b1edbc | 7737 | __IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x300 */ |
AnnaBridge | 171:3a7713b1edbc | 7738 | __IO uint32_t LCKCR; /**< LUT Lock Configuration Register, offset: 0x304 */ |
AnnaBridge | 171:3a7713b1edbc | 7739 | uint8_t RESERVED_7[8]; |
AnnaBridge | 171:3a7713b1edbc | 7740 | __IO uint32_t LUT[64]; /**< Look-up Table register, array offset: 0x310, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 7741 | } QuadSPI_Type; |
AnnaBridge | 171:3a7713b1edbc | 7742 | |
AnnaBridge | 171:3a7713b1edbc | 7743 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 7744 | -- QuadSPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7745 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 7746 | |
AnnaBridge | 171:3a7713b1edbc | 7747 | /*! |
AnnaBridge | 171:3a7713b1edbc | 7748 | * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 7749 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 7750 | */ |
AnnaBridge | 171:3a7713b1edbc | 7751 | |
AnnaBridge | 171:3a7713b1edbc | 7752 | /*! @name MCR - Module Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7753 | #define QuadSPI_MCR_SWRSTSD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7754 | #define QuadSPI_MCR_SWRSTSD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7755 | #define QuadSPI_MCR_SWRSTSD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTSD_SHIFT)) & QuadSPI_MCR_SWRSTSD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7756 | #define QuadSPI_MCR_SWRSTHD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7757 | #define QuadSPI_MCR_SWRSTHD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7758 | #define QuadSPI_MCR_SWRSTHD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SWRSTHD_SHIFT)) & QuadSPI_MCR_SWRSTHD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7759 | #define QuadSPI_MCR_END_CFG_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 7760 | #define QuadSPI_MCR_END_CFG_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7761 | #define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_END_CFG_SHIFT)) & QuadSPI_MCR_END_CFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7762 | #define QuadSPI_MCR_DQS_LAT_EN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7763 | #define QuadSPI_MCR_DQS_LAT_EN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7764 | #define QuadSPI_MCR_DQS_LAT_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_LAT_EN_SHIFT)) & QuadSPI_MCR_DQS_LAT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7765 | #define QuadSPI_MCR_DQS_EN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7766 | #define QuadSPI_MCR_DQS_EN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7767 | #define QuadSPI_MCR_DQS_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DQS_EN_SHIFT)) & QuadSPI_MCR_DQS_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7768 | #define QuadSPI_MCR_DDR_EN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7769 | #define QuadSPI_MCR_DDR_EN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7770 | #define QuadSPI_MCR_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_DDR_EN_SHIFT)) & QuadSPI_MCR_DDR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7771 | #define QuadSPI_MCR_CLR_RXF_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 7772 | #define QuadSPI_MCR_CLR_RXF_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 7773 | #define QuadSPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_RXF_SHIFT)) & QuadSPI_MCR_CLR_RXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7774 | #define QuadSPI_MCR_CLR_TXF_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 7775 | #define QuadSPI_MCR_CLR_TXF_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 7776 | #define QuadSPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_CLR_TXF_SHIFT)) & QuadSPI_MCR_CLR_TXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7777 | #define QuadSPI_MCR_MDIS_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 7778 | #define QuadSPI_MCR_MDIS_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 7779 | #define QuadSPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_MDIS_SHIFT)) & QuadSPI_MCR_MDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7780 | #define QuadSPI_MCR_SCLKCFG_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 7781 | #define QuadSPI_MCR_SCLKCFG_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7782 | #define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_MCR_SCLKCFG_SHIFT)) & QuadSPI_MCR_SCLKCFG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7783 | |
AnnaBridge | 171:3a7713b1edbc | 7784 | /*! @name IPCR - IP Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7785 | #define QuadSPI_IPCR_IDATSZ_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7786 | #define QuadSPI_IPCR_IDATSZ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7787 | #define QuadSPI_IPCR_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_IDATSZ_SHIFT)) & QuadSPI_IPCR_IDATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7788 | #define QuadSPI_IPCR_PAR_EN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 7789 | #define QuadSPI_IPCR_PAR_EN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7790 | #define QuadSPI_IPCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_PAR_EN_SHIFT)) & QuadSPI_IPCR_PAR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7791 | #define QuadSPI_IPCR_SEQID_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 7792 | #define QuadSPI_IPCR_SEQID_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7793 | #define QuadSPI_IPCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_IPCR_SEQID_SHIFT)) & QuadSPI_IPCR_SEQID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7794 | |
AnnaBridge | 171:3a7713b1edbc | 7795 | /*! @name FLSHCR - Flash Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7796 | #define QuadSPI_FLSHCR_TCSS_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7797 | #define QuadSPI_FLSHCR_TCSS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7798 | #define QuadSPI_FLSHCR_TCSS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSS_SHIFT)) & QuadSPI_FLSHCR_TCSS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7799 | #define QuadSPI_FLSHCR_TCSH_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 7800 | #define QuadSPI_FLSHCR_TCSH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7801 | #define QuadSPI_FLSHCR_TCSH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TCSH_SHIFT)) & QuadSPI_FLSHCR_TCSH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7802 | #define QuadSPI_FLSHCR_TDH_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 7803 | #define QuadSPI_FLSHCR_TDH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7804 | #define QuadSPI_FLSHCR_TDH(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FLSHCR_TDH_SHIFT)) & QuadSPI_FLSHCR_TDH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7805 | |
AnnaBridge | 171:3a7713b1edbc | 7806 | /*! @name BUF0CR - Buffer0 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7807 | #define QuadSPI_BUF0CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7808 | #define QuadSPI_BUF0CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7809 | #define QuadSPI_BUF0CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_MSTRID_SHIFT)) & QuadSPI_BUF0CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7810 | #define QuadSPI_BUF0CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 7811 | #define QuadSPI_BUF0CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7812 | #define QuadSPI_BUF0CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_ADATSZ_SHIFT)) & QuadSPI_BUF0CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7813 | #define QuadSPI_BUF0CR_HP_EN_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 7814 | #define QuadSPI_BUF0CR_HP_EN_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 7815 | #define QuadSPI_BUF0CR_HP_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0CR_HP_EN_SHIFT)) & QuadSPI_BUF0CR_HP_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7816 | |
AnnaBridge | 171:3a7713b1edbc | 7817 | /*! @name BUF1CR - Buffer1 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7818 | #define QuadSPI_BUF1CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7819 | #define QuadSPI_BUF1CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7820 | #define QuadSPI_BUF1CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_MSTRID_SHIFT)) & QuadSPI_BUF1CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7821 | #define QuadSPI_BUF1CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 7822 | #define QuadSPI_BUF1CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7823 | #define QuadSPI_BUF1CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1CR_ADATSZ_SHIFT)) & QuadSPI_BUF1CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7824 | |
AnnaBridge | 171:3a7713b1edbc | 7825 | /*! @name BUF2CR - Buffer2 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7826 | #define QuadSPI_BUF2CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7827 | #define QuadSPI_BUF2CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7828 | #define QuadSPI_BUF2CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_MSTRID_SHIFT)) & QuadSPI_BUF2CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7829 | #define QuadSPI_BUF2CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 7830 | #define QuadSPI_BUF2CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7831 | #define QuadSPI_BUF2CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2CR_ADATSZ_SHIFT)) & QuadSPI_BUF2CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7832 | |
AnnaBridge | 171:3a7713b1edbc | 7833 | /*! @name BUF3CR - Buffer3 Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7834 | #define QuadSPI_BUF3CR_MSTRID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7835 | #define QuadSPI_BUF3CR_MSTRID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7836 | #define QuadSPI_BUF3CR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_MSTRID_SHIFT)) & QuadSPI_BUF3CR_MSTRID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7837 | #define QuadSPI_BUF3CR_ADATSZ_MASK (0x7F00U) |
AnnaBridge | 171:3a7713b1edbc | 7838 | #define QuadSPI_BUF3CR_ADATSZ_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7839 | #define QuadSPI_BUF3CR_ADATSZ(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ADATSZ_SHIFT)) & QuadSPI_BUF3CR_ADATSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7840 | #define QuadSPI_BUF3CR_ALLMST_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 7841 | #define QuadSPI_BUF3CR_ALLMST_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 7842 | #define QuadSPI_BUF3CR_ALLMST(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF3CR_ALLMST_SHIFT)) & QuadSPI_BUF3CR_ALLMST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7843 | |
AnnaBridge | 171:3a7713b1edbc | 7844 | /*! @name BFGENCR - Buffer Generic Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7845 | #define QuadSPI_BFGENCR_SEQID_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 7846 | #define QuadSPI_BFGENCR_SEQID_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7847 | #define QuadSPI_BFGENCR_SEQID(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_SEQID_SHIFT)) & QuadSPI_BFGENCR_SEQID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7848 | #define QuadSPI_BFGENCR_PAR_EN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 7849 | #define QuadSPI_BFGENCR_PAR_EN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7850 | #define QuadSPI_BFGENCR_PAR_EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BFGENCR_PAR_EN_SHIFT)) & QuadSPI_BFGENCR_PAR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7851 | |
AnnaBridge | 171:3a7713b1edbc | 7852 | /*! @name SOCCR - SOC Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7853 | #define QuadSPI_SOCCR_QSPISRC_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 7854 | #define QuadSPI_SOCCR_QSPISRC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7855 | #define QuadSPI_SOCCR_QSPISRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_QSPISRC_SHIFT)) & QuadSPI_SOCCR_QSPISRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7856 | #define QuadSPI_SOCCR_DQSLPEN_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 7857 | #define QuadSPI_SOCCR_DQSLPEN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7858 | #define QuadSPI_SOCCR_DQSLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSLPEN_SHIFT)) & QuadSPI_SOCCR_DQSLPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7859 | #define QuadSPI_SOCCR_DQSPADLPEN_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 7860 | #define QuadSPI_SOCCR_DQSPADLPEN_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 7861 | #define QuadSPI_SOCCR_DQSPADLPEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPADLPEN_SHIFT)) & QuadSPI_SOCCR_DQSPADLPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7862 | #define QuadSPI_SOCCR_DQSPHASEL_MASK (0xC00U) |
AnnaBridge | 171:3a7713b1edbc | 7863 | #define QuadSPI_SOCCR_DQSPHASEL_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 7864 | #define QuadSPI_SOCCR_DQSPHASEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSPHASEL_SHIFT)) & QuadSPI_SOCCR_DQSPHASEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7865 | #define QuadSPI_SOCCR_DQSINVSEL_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 7866 | #define QuadSPI_SOCCR_DQSINVSEL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7867 | #define QuadSPI_SOCCR_DQSINVSEL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DQSINVSEL_SHIFT)) & QuadSPI_SOCCR_DQSINVSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7868 | #define QuadSPI_SOCCR_CK2EN_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 7869 | #define QuadSPI_SOCCR_CK2EN_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 7870 | #define QuadSPI_SOCCR_CK2EN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_CK2EN_SHIFT)) & QuadSPI_SOCCR_CK2EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7871 | #define QuadSPI_SOCCR_DIFFCKEN_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 7872 | #define QuadSPI_SOCCR_DIFFCKEN_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 7873 | #define QuadSPI_SOCCR_DIFFCKEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DIFFCKEN_SHIFT)) & QuadSPI_SOCCR_DIFFCKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7874 | #define QuadSPI_SOCCR_OCTEN_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 7875 | #define QuadSPI_SOCCR_OCTEN_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 7876 | #define QuadSPI_SOCCR_OCTEN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_OCTEN_SHIFT)) & QuadSPI_SOCCR_OCTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7877 | #define QuadSPI_SOCCR_DLYTAPSELA_MASK (0x3F0000U) |
AnnaBridge | 171:3a7713b1edbc | 7878 | #define QuadSPI_SOCCR_DLYTAPSELA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7879 | #define QuadSPI_SOCCR_DLYTAPSELA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELA_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7880 | #define QuadSPI_SOCCR_DLYTAPSELB_MASK (0x3F000000U) |
AnnaBridge | 171:3a7713b1edbc | 7881 | #define QuadSPI_SOCCR_DLYTAPSELB_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 7882 | #define QuadSPI_SOCCR_DLYTAPSELB(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SOCCR_DLYTAPSELB_SHIFT)) & QuadSPI_SOCCR_DLYTAPSELB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7883 | |
AnnaBridge | 171:3a7713b1edbc | 7884 | /*! @name BUF0IND - Buffer0 Top Index Register */ |
AnnaBridge | 171:3a7713b1edbc | 7885 | #define QuadSPI_BUF0IND_TPINDX0_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 7886 | #define QuadSPI_BUF0IND_TPINDX0_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7887 | #define QuadSPI_BUF0IND_TPINDX0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF0IND_TPINDX0_SHIFT)) & QuadSPI_BUF0IND_TPINDX0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7888 | |
AnnaBridge | 171:3a7713b1edbc | 7889 | /*! @name BUF1IND - Buffer1 Top Index Register */ |
AnnaBridge | 171:3a7713b1edbc | 7890 | #define QuadSPI_BUF1IND_TPINDX1_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 7891 | #define QuadSPI_BUF1IND_TPINDX1_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7892 | #define QuadSPI_BUF1IND_TPINDX1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF1IND_TPINDX1_SHIFT)) & QuadSPI_BUF1IND_TPINDX1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7893 | |
AnnaBridge | 171:3a7713b1edbc | 7894 | /*! @name BUF2IND - Buffer2 Top Index Register */ |
AnnaBridge | 171:3a7713b1edbc | 7895 | #define QuadSPI_BUF2IND_TPINDX2_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 7896 | #define QuadSPI_BUF2IND_TPINDX2_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 7897 | #define QuadSPI_BUF2IND_TPINDX2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_BUF2IND_TPINDX2_SHIFT)) & QuadSPI_BUF2IND_TPINDX2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7898 | |
AnnaBridge | 171:3a7713b1edbc | 7899 | /*! @name SFAR - Serial Flash Address Register */ |
AnnaBridge | 171:3a7713b1edbc | 7900 | #define QuadSPI_SFAR_SFADR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7901 | #define QuadSPI_SFAR_SFADR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7902 | #define QuadSPI_SFAR_SFADR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFAR_SFADR_SHIFT)) & QuadSPI_SFAR_SFADR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7903 | |
AnnaBridge | 171:3a7713b1edbc | 7904 | /*! @name SFACR - Serial Flash Address Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 7905 | #define QuadSPI_SFACR_CAS_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7906 | #define QuadSPI_SFACR_CAS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7907 | #define QuadSPI_SFACR_CAS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_CAS_SHIFT)) & QuadSPI_SFACR_CAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7908 | #define QuadSPI_SFACR_WA_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 7909 | #define QuadSPI_SFACR_WA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7910 | #define QuadSPI_SFACR_WA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFACR_WA_SHIFT)) & QuadSPI_SFACR_WA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7911 | |
AnnaBridge | 171:3a7713b1edbc | 7912 | /*! @name SMPR - Sampling Register */ |
AnnaBridge | 171:3a7713b1edbc | 7913 | #define QuadSPI_SMPR_HSENA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7914 | #define QuadSPI_SMPR_HSENA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7915 | #define QuadSPI_SMPR_HSENA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSENA_SHIFT)) & QuadSPI_SMPR_HSENA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7916 | #define QuadSPI_SMPR_HSPHS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7917 | #define QuadSPI_SMPR_HSPHS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7918 | #define QuadSPI_SMPR_HSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSPHS_SHIFT)) & QuadSPI_SMPR_HSPHS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7919 | #define QuadSPI_SMPR_HSDLY_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7920 | #define QuadSPI_SMPR_HSDLY_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7921 | #define QuadSPI_SMPR_HSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_HSDLY_SHIFT)) & QuadSPI_SMPR_HSDLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7922 | #define QuadSPI_SMPR_FSPHS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7923 | #define QuadSPI_SMPR_FSPHS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7924 | #define QuadSPI_SMPR_FSPHS(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSPHS_SHIFT)) & QuadSPI_SMPR_FSPHS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7925 | #define QuadSPI_SMPR_FSDLY_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7926 | #define QuadSPI_SMPR_FSDLY_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7927 | #define QuadSPI_SMPR_FSDLY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_FSDLY_SHIFT)) & QuadSPI_SMPR_FSDLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7928 | #define QuadSPI_SMPR_DDRSMP_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 7929 | #define QuadSPI_SMPR_DDRSMP_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7930 | #define QuadSPI_SMPR_DDRSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SMPR_DDRSMP_SHIFT)) & QuadSPI_SMPR_DDRSMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7931 | |
AnnaBridge | 171:3a7713b1edbc | 7932 | /*! @name RBSR - RX Buffer Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 7933 | #define QuadSPI_RBSR_RDBFL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 7934 | #define QuadSPI_RBSR_RDBFL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7935 | #define QuadSPI_RBSR_RDBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDBFL_SHIFT)) & QuadSPI_RBSR_RDBFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7936 | #define QuadSPI_RBSR_RDCTR_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7937 | #define QuadSPI_RBSR_RDCTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7938 | #define QuadSPI_RBSR_RDCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBSR_RDCTR_SHIFT)) & QuadSPI_RBSR_RDCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7939 | |
AnnaBridge | 171:3a7713b1edbc | 7940 | /*! @name RBCT - RX Buffer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7941 | #define QuadSPI_RBCT_WMRK_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7942 | #define QuadSPI_RBCT_WMRK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7943 | #define QuadSPI_RBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_WMRK_SHIFT)) & QuadSPI_RBCT_WMRK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7944 | #define QuadSPI_RBCT_RXBRD_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 7945 | #define QuadSPI_RBCT_RXBRD_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7946 | #define QuadSPI_RBCT_RXBRD(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBCT_RXBRD_SHIFT)) & QuadSPI_RBCT_RXBRD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7947 | |
AnnaBridge | 171:3a7713b1edbc | 7948 | /*! @name TBSR - TX Buffer Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 7949 | #define QuadSPI_TBSR_TRBFL_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 7950 | #define QuadSPI_TBSR_TRBFL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7951 | #define QuadSPI_TBSR_TRBFL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRBFL_SHIFT)) & QuadSPI_TBSR_TRBFL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7952 | #define QuadSPI_TBSR_TRCTR_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 7953 | #define QuadSPI_TBSR_TRCTR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 7954 | #define QuadSPI_TBSR_TRCTR(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBSR_TRCTR_SHIFT)) & QuadSPI_TBSR_TRCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7955 | |
AnnaBridge | 171:3a7713b1edbc | 7956 | /*! @name TBDR - TX Buffer Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 7957 | #define QuadSPI_TBDR_TXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 7958 | #define QuadSPI_TBDR_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7959 | #define QuadSPI_TBDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBDR_TXDATA_SHIFT)) & QuadSPI_TBDR_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7960 | |
AnnaBridge | 171:3a7713b1edbc | 7961 | /*! @name TBCT - Tx Buffer Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 7962 | #define QuadSPI_TBCT_WMRK_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 7963 | #define QuadSPI_TBCT_WMRK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7964 | #define QuadSPI_TBCT_WMRK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_TBCT_WMRK_SHIFT)) & QuadSPI_TBCT_WMRK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7965 | |
AnnaBridge | 171:3a7713b1edbc | 7966 | /*! @name SR - Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 7967 | #define QuadSPI_SR_BUSY_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 7968 | #define QuadSPI_SR_BUSY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 7969 | #define QuadSPI_SR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_BUSY_SHIFT)) & QuadSPI_SR_BUSY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7970 | #define QuadSPI_SR_IP_ACC_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 7971 | #define QuadSPI_SR_IP_ACC_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 7972 | #define QuadSPI_SR_IP_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_IP_ACC_SHIFT)) & QuadSPI_SR_IP_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7973 | #define QuadSPI_SR_AHB_ACC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 7974 | #define QuadSPI_SR_AHB_ACC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 7975 | #define QuadSPI_SR_AHB_ACC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB_ACC_SHIFT)) & QuadSPI_SR_AHB_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7976 | #define QuadSPI_SR_AHBGNT_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 7977 | #define QuadSPI_SR_AHBGNT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 7978 | #define QuadSPI_SR_AHBGNT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBGNT_SHIFT)) & QuadSPI_SR_AHBGNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7979 | #define QuadSPI_SR_AHBTRN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 7980 | #define QuadSPI_SR_AHBTRN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 7981 | #define QuadSPI_SR_AHBTRN(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHBTRN_SHIFT)) & QuadSPI_SR_AHBTRN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7982 | #define QuadSPI_SR_AHB0NE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 7983 | #define QuadSPI_SR_AHB0NE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 7984 | #define QuadSPI_SR_AHB0NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0NE_SHIFT)) & QuadSPI_SR_AHB0NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7985 | #define QuadSPI_SR_AHB1NE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 7986 | #define QuadSPI_SR_AHB1NE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 7987 | #define QuadSPI_SR_AHB1NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1NE_SHIFT)) & QuadSPI_SR_AHB1NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7988 | #define QuadSPI_SR_AHB2NE_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 7989 | #define QuadSPI_SR_AHB2NE_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 7990 | #define QuadSPI_SR_AHB2NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2NE_SHIFT)) & QuadSPI_SR_AHB2NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7991 | #define QuadSPI_SR_AHB3NE_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 7992 | #define QuadSPI_SR_AHB3NE_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 7993 | #define QuadSPI_SR_AHB3NE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3NE_SHIFT)) & QuadSPI_SR_AHB3NE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7994 | #define QuadSPI_SR_AHB0FUL_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 7995 | #define QuadSPI_SR_AHB0FUL_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 7996 | #define QuadSPI_SR_AHB0FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB0FUL_SHIFT)) & QuadSPI_SR_AHB0FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 7997 | #define QuadSPI_SR_AHB1FUL_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 7998 | #define QuadSPI_SR_AHB1FUL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 7999 | #define QuadSPI_SR_AHB1FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB1FUL_SHIFT)) & QuadSPI_SR_AHB1FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8000 | #define QuadSPI_SR_AHB2FUL_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 8001 | #define QuadSPI_SR_AHB2FUL_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 8002 | #define QuadSPI_SR_AHB2FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB2FUL_SHIFT)) & QuadSPI_SR_AHB2FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8003 | #define QuadSPI_SR_AHB3FUL_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8004 | #define QuadSPI_SR_AHB3FUL_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8005 | #define QuadSPI_SR_AHB3FUL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_AHB3FUL_SHIFT)) & QuadSPI_SR_AHB3FUL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8006 | #define QuadSPI_SR_RXWE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8007 | #define QuadSPI_SR_RXWE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8008 | #define QuadSPI_SR_RXWE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXWE_SHIFT)) & QuadSPI_SR_RXWE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8009 | #define QuadSPI_SR_RXFULL_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 8010 | #define QuadSPI_SR_RXFULL_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 8011 | #define QuadSPI_SR_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXFULL_SHIFT)) & QuadSPI_SR_RXFULL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8012 | #define QuadSPI_SR_RXDMA_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8013 | #define QuadSPI_SR_RXDMA_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8014 | #define QuadSPI_SR_RXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_RXDMA_SHIFT)) & QuadSPI_SR_RXDMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8015 | #define QuadSPI_SR_TXEDA_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 8016 | #define QuadSPI_SR_TXEDA_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8017 | #define QuadSPI_SR_TXEDA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXEDA_SHIFT)) & QuadSPI_SR_TXEDA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8018 | #define QuadSPI_SR_TXWA_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8019 | #define QuadSPI_SR_TXWA_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8020 | #define QuadSPI_SR_TXWA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXWA_SHIFT)) & QuadSPI_SR_TXWA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8021 | #define QuadSPI_SR_TXDMA_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8022 | #define QuadSPI_SR_TXDMA_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8023 | #define QuadSPI_SR_TXDMA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXDMA_SHIFT)) & QuadSPI_SR_TXDMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8024 | #define QuadSPI_SR_TXFULL_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8025 | #define QuadSPI_SR_TXFULL_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8026 | #define QuadSPI_SR_TXFULL(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_TXFULL_SHIFT)) & QuadSPI_SR_TXFULL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8027 | #define QuadSPI_SR_DLPSMP_MASK (0xE0000000U) |
AnnaBridge | 171:3a7713b1edbc | 8028 | #define QuadSPI_SR_DLPSMP_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 8029 | #define QuadSPI_SR_DLPSMP(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SR_DLPSMP_SHIFT)) & QuadSPI_SR_DLPSMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8030 | |
AnnaBridge | 171:3a7713b1edbc | 8031 | /*! @name FR - Flag Register */ |
AnnaBridge | 171:3a7713b1edbc | 8032 | #define QuadSPI_FR_TFF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8033 | #define QuadSPI_FR_TFF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8034 | #define QuadSPI_FR_TFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TFF_SHIFT)) & QuadSPI_FR_TFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8035 | #define QuadSPI_FR_IPGEF_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8036 | #define QuadSPI_FR_IPGEF_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8037 | #define QuadSPI_FR_IPGEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPGEF_SHIFT)) & QuadSPI_FR_IPGEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8038 | #define QuadSPI_FR_IPIEF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8039 | #define QuadSPI_FR_IPIEF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8040 | #define QuadSPI_FR_IPIEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPIEF_SHIFT)) & QuadSPI_FR_IPIEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8041 | #define QuadSPI_FR_IPAEF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8042 | #define QuadSPI_FR_IPAEF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8043 | #define QuadSPI_FR_IPAEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IPAEF_SHIFT)) & QuadSPI_FR_IPAEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8044 | #define QuadSPI_FR_IUEF_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 8045 | #define QuadSPI_FR_IUEF_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 8046 | #define QuadSPI_FR_IUEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_IUEF_SHIFT)) & QuadSPI_FR_IUEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8047 | #define QuadSPI_FR_ABOF_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 8048 | #define QuadSPI_FR_ABOF_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8049 | #define QuadSPI_FR_ABOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABOF_SHIFT)) & QuadSPI_FR_ABOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8050 | #define QuadSPI_FR_AIBSEF_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 8051 | #define QuadSPI_FR_AIBSEF_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 8052 | #define QuadSPI_FR_AIBSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AIBSEF_SHIFT)) & QuadSPI_FR_AIBSEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8053 | #define QuadSPI_FR_AITEF_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8054 | #define QuadSPI_FR_AITEF_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8055 | #define QuadSPI_FR_AITEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_AITEF_SHIFT)) & QuadSPI_FR_AITEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8056 | #define QuadSPI_FR_ABSEF_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8057 | #define QuadSPI_FR_ABSEF_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8058 | #define QuadSPI_FR_ABSEF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ABSEF_SHIFT)) & QuadSPI_FR_ABSEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8059 | #define QuadSPI_FR_RBDF_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8060 | #define QuadSPI_FR_RBDF_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8061 | #define QuadSPI_FR_RBDF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBDF_SHIFT)) & QuadSPI_FR_RBDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8062 | #define QuadSPI_FR_RBOF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 8063 | #define QuadSPI_FR_RBOF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 8064 | #define QuadSPI_FR_RBOF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_RBOF_SHIFT)) & QuadSPI_FR_RBOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8065 | #define QuadSPI_FR_ILLINE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8066 | #define QuadSPI_FR_ILLINE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8067 | #define QuadSPI_FR_ILLINE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_ILLINE_SHIFT)) & QuadSPI_FR_ILLINE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8068 | #define QuadSPI_FR_TBUF_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8069 | #define QuadSPI_FR_TBUF_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8070 | #define QuadSPI_FR_TBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBUF_SHIFT)) & QuadSPI_FR_TBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8071 | #define QuadSPI_FR_TBFF_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8072 | #define QuadSPI_FR_TBFF_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8073 | #define QuadSPI_FR_TBFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_TBFF_SHIFT)) & QuadSPI_FR_TBFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8074 | #define QuadSPI_FR_DLPFF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8075 | #define QuadSPI_FR_DLPFF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8076 | #define QuadSPI_FR_DLPFF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_FR_DLPFF_SHIFT)) & QuadSPI_FR_DLPFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8077 | |
AnnaBridge | 171:3a7713b1edbc | 8078 | /*! @name RSER - Interrupt and DMA Request Select and Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 8079 | #define QuadSPI_RSER_TFIE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8080 | #define QuadSPI_RSER_TFIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8081 | #define QuadSPI_RSER_TFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TFIE_SHIFT)) & QuadSPI_RSER_TFIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8082 | #define QuadSPI_RSER_IPGEIE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8083 | #define QuadSPI_RSER_IPGEIE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8084 | #define QuadSPI_RSER_IPGEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPGEIE_SHIFT)) & QuadSPI_RSER_IPGEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8085 | #define QuadSPI_RSER_IPIEIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8086 | #define QuadSPI_RSER_IPIEIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8087 | #define QuadSPI_RSER_IPIEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPIEIE_SHIFT)) & QuadSPI_RSER_IPIEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8088 | #define QuadSPI_RSER_IPAEIE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8089 | #define QuadSPI_RSER_IPAEIE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8090 | #define QuadSPI_RSER_IPAEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IPAEIE_SHIFT)) & QuadSPI_RSER_IPAEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8091 | #define QuadSPI_RSER_IUEIE_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 8092 | #define QuadSPI_RSER_IUEIE_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 8093 | #define QuadSPI_RSER_IUEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_IUEIE_SHIFT)) & QuadSPI_RSER_IUEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8094 | #define QuadSPI_RSER_ABOIE_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 8095 | #define QuadSPI_RSER_ABOIE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8096 | #define QuadSPI_RSER_ABOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABOIE_SHIFT)) & QuadSPI_RSER_ABOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8097 | #define QuadSPI_RSER_AIBSIE_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 8098 | #define QuadSPI_RSER_AIBSIE_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 8099 | #define QuadSPI_RSER_AIBSIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AIBSIE_SHIFT)) & QuadSPI_RSER_AIBSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8100 | #define QuadSPI_RSER_AITIE_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 8101 | #define QuadSPI_RSER_AITIE_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 8102 | #define QuadSPI_RSER_AITIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_AITIE_SHIFT)) & QuadSPI_RSER_AITIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8103 | #define QuadSPI_RSER_ABSEIE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 8104 | #define QuadSPI_RSER_ABSEIE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 8105 | #define QuadSPI_RSER_ABSEIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ABSEIE_SHIFT)) & QuadSPI_RSER_ABSEIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8106 | #define QuadSPI_RSER_RBDIE_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 8107 | #define QuadSPI_RSER_RBDIE_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8108 | #define QuadSPI_RSER_RBDIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDIE_SHIFT)) & QuadSPI_RSER_RBDIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8109 | #define QuadSPI_RSER_RBOIE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 8110 | #define QuadSPI_RSER_RBOIE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 8111 | #define QuadSPI_RSER_RBOIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBOIE_SHIFT)) & QuadSPI_RSER_RBOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8112 | #define QuadSPI_RSER_RBDDE_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 8113 | #define QuadSPI_RSER_RBDDE_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 8114 | #define QuadSPI_RSER_RBDDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_RBDDE_SHIFT)) & QuadSPI_RSER_RBDDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8115 | #define QuadSPI_RSER_ILLINIE_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 8116 | #define QuadSPI_RSER_ILLINIE_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 8117 | #define QuadSPI_RSER_ILLINIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_ILLINIE_SHIFT)) & QuadSPI_RSER_ILLINIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8118 | #define QuadSPI_RSER_TBFDE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8119 | #define QuadSPI_RSER_TBFDE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8120 | #define QuadSPI_RSER_TBFDE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFDE_SHIFT)) & QuadSPI_RSER_TBFDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8121 | #define QuadSPI_RSER_TBUIE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8122 | #define QuadSPI_RSER_TBUIE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8123 | #define QuadSPI_RSER_TBUIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBUIE_SHIFT)) & QuadSPI_RSER_TBUIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8124 | #define QuadSPI_RSER_TBFIE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 8125 | #define QuadSPI_RSER_TBFIE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 8126 | #define QuadSPI_RSER_TBFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_TBFIE_SHIFT)) & QuadSPI_RSER_TBFIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8127 | #define QuadSPI_RSER_DLPFIE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 8128 | #define QuadSPI_RSER_DLPFIE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 8129 | #define QuadSPI_RSER_DLPFIE(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RSER_DLPFIE_SHIFT)) & QuadSPI_RSER_DLPFIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8130 | |
AnnaBridge | 171:3a7713b1edbc | 8131 | /*! @name SPNDST - Sequence Suspend Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 8132 | #define QuadSPI_SPNDST_SUSPND_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8133 | #define QuadSPI_SPNDST_SUSPND_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8134 | #define QuadSPI_SPNDST_SUSPND(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SUSPND_SHIFT)) & QuadSPI_SPNDST_SUSPND_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8135 | #define QuadSPI_SPNDST_SPDBUF_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 8136 | #define QuadSPI_SPNDST_SPDBUF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8137 | #define QuadSPI_SPNDST_SPDBUF(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_SPDBUF_SHIFT)) & QuadSPI_SPNDST_SPDBUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8138 | #define QuadSPI_SPNDST_DATLFT_MASK (0x7E00U) |
AnnaBridge | 171:3a7713b1edbc | 8139 | #define QuadSPI_SPNDST_DATLFT_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 8140 | #define QuadSPI_SPNDST_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPNDST_DATLFT_SHIFT)) & QuadSPI_SPNDST_DATLFT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8141 | |
AnnaBridge | 171:3a7713b1edbc | 8142 | /*! @name SPTRCLR - Sequence Pointer Clear Register */ |
AnnaBridge | 171:3a7713b1edbc | 8143 | #define QuadSPI_SPTRCLR_BFPTRC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8144 | #define QuadSPI_SPTRCLR_BFPTRC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8145 | #define QuadSPI_SPTRCLR_BFPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_BFPTRC_SHIFT)) & QuadSPI_SPTRCLR_BFPTRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8146 | #define QuadSPI_SPTRCLR_IPPTRC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 8147 | #define QuadSPI_SPTRCLR_IPPTRC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8148 | #define QuadSPI_SPTRCLR_IPPTRC(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SPTRCLR_IPPTRC_SHIFT)) & QuadSPI_SPTRCLR_IPPTRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8149 | |
AnnaBridge | 171:3a7713b1edbc | 8150 | /*! @name SFA1AD - Serial Flash A1 Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 8151 | #define QuadSPI_SFA1AD_TPADA1_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 8152 | #define QuadSPI_SFA1AD_TPADA1_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8153 | #define QuadSPI_SFA1AD_TPADA1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA1AD_TPADA1_SHIFT)) & QuadSPI_SFA1AD_TPADA1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8154 | |
AnnaBridge | 171:3a7713b1edbc | 8155 | /*! @name SFA2AD - Serial Flash A2 Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 8156 | #define QuadSPI_SFA2AD_TPADA2_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 8157 | #define QuadSPI_SFA2AD_TPADA2_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8158 | #define QuadSPI_SFA2AD_TPADA2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFA2AD_TPADA2_SHIFT)) & QuadSPI_SFA2AD_TPADA2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8159 | |
AnnaBridge | 171:3a7713b1edbc | 8160 | /*! @name SFB1AD - Serial Flash B1Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 8161 | #define QuadSPI_SFB1AD_TPADB1_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 8162 | #define QuadSPI_SFB1AD_TPADB1_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8163 | #define QuadSPI_SFB1AD_TPADB1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB1AD_TPADB1_SHIFT)) & QuadSPI_SFB1AD_TPADB1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8164 | |
AnnaBridge | 171:3a7713b1edbc | 8165 | /*! @name SFB2AD - Serial Flash B2Top Address */ |
AnnaBridge | 171:3a7713b1edbc | 8166 | #define QuadSPI_SFB2AD_TPADB2_MASK (0xFFFFFC00U) |
AnnaBridge | 171:3a7713b1edbc | 8167 | #define QuadSPI_SFB2AD_TPADB2_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8168 | #define QuadSPI_SFB2AD_TPADB2(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_SFB2AD_TPADB2_SHIFT)) & QuadSPI_SFB2AD_TPADB2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8169 | |
AnnaBridge | 171:3a7713b1edbc | 8170 | /*! @name DLPR - Data Learn Pattern Register */ |
AnnaBridge | 171:3a7713b1edbc | 8171 | #define QuadSPI_DLPR_DLPV_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8172 | #define QuadSPI_DLPR_DLPV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8173 | #define QuadSPI_DLPR_DLPV(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_DLPR_DLPV_SHIFT)) & QuadSPI_DLPR_DLPV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8174 | |
AnnaBridge | 171:3a7713b1edbc | 8175 | /*! @name RBDR - RX Buffer Data Register */ |
AnnaBridge | 171:3a7713b1edbc | 8176 | #define QuadSPI_RBDR_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8177 | #define QuadSPI_RBDR_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8178 | #define QuadSPI_RBDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_RBDR_RXDATA_SHIFT)) & QuadSPI_RBDR_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8179 | |
AnnaBridge | 171:3a7713b1edbc | 8180 | /* The count of QuadSPI_RBDR */ |
AnnaBridge | 171:3a7713b1edbc | 8181 | #define QuadSPI_RBDR_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8182 | |
AnnaBridge | 171:3a7713b1edbc | 8183 | /*! @name LUTKEY - LUT Key Register */ |
AnnaBridge | 171:3a7713b1edbc | 8184 | #define QuadSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8185 | #define QuadSPI_LUTKEY_KEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8186 | #define QuadSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUTKEY_KEY_SHIFT)) & QuadSPI_LUTKEY_KEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8187 | |
AnnaBridge | 171:3a7713b1edbc | 8188 | /*! @name LCKCR - LUT Lock Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 8189 | #define QuadSPI_LCKCR_LOCK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8190 | #define QuadSPI_LCKCR_LOCK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8191 | #define QuadSPI_LCKCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_LOCK_SHIFT)) & QuadSPI_LCKCR_LOCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8192 | #define QuadSPI_LCKCR_UNLOCK_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8193 | #define QuadSPI_LCKCR_UNLOCK_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8194 | #define QuadSPI_LCKCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LCKCR_UNLOCK_SHIFT)) & QuadSPI_LCKCR_UNLOCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8195 | |
AnnaBridge | 171:3a7713b1edbc | 8196 | /*! @name LUT - Look-up Table register */ |
AnnaBridge | 171:3a7713b1edbc | 8197 | #define QuadSPI_LUT_OPRND0_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 8198 | #define QuadSPI_LUT_OPRND0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8199 | #define QuadSPI_LUT_OPRND0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND0_SHIFT)) & QuadSPI_LUT_OPRND0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8200 | #define QuadSPI_LUT_PAD0_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 8201 | #define QuadSPI_LUT_PAD0_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8202 | #define QuadSPI_LUT_PAD0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD0_SHIFT)) & QuadSPI_LUT_PAD0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8203 | #define QuadSPI_LUT_INSTR0_MASK (0xFC00U) |
AnnaBridge | 171:3a7713b1edbc | 8204 | #define QuadSPI_LUT_INSTR0_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8205 | #define QuadSPI_LUT_INSTR0(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR0_SHIFT)) & QuadSPI_LUT_INSTR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8206 | #define QuadSPI_LUT_OPRND1_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 8207 | #define QuadSPI_LUT_OPRND1_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8208 | #define QuadSPI_LUT_OPRND1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_OPRND1_SHIFT)) & QuadSPI_LUT_OPRND1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8209 | #define QuadSPI_LUT_PAD1_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 8210 | #define QuadSPI_LUT_PAD1_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8211 | #define QuadSPI_LUT_PAD1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_PAD1_SHIFT)) & QuadSPI_LUT_PAD1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8212 | #define QuadSPI_LUT_INSTR1_MASK (0xFC000000U) |
AnnaBridge | 171:3a7713b1edbc | 8213 | #define QuadSPI_LUT_INSTR1_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8214 | #define QuadSPI_LUT_INSTR1(x) (((uint32_t)(((uint32_t)(x)) << QuadSPI_LUT_INSTR1_SHIFT)) & QuadSPI_LUT_INSTR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8215 | |
AnnaBridge | 171:3a7713b1edbc | 8216 | /* The count of QuadSPI_LUT */ |
AnnaBridge | 171:3a7713b1edbc | 8217 | #define QuadSPI_LUT_COUNT (64U) |
AnnaBridge | 171:3a7713b1edbc | 8218 | |
AnnaBridge | 171:3a7713b1edbc | 8219 | |
AnnaBridge | 171:3a7713b1edbc | 8220 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8221 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8222 | */ /* end of group QuadSPI_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8223 | |
AnnaBridge | 171:3a7713b1edbc | 8224 | |
AnnaBridge | 171:3a7713b1edbc | 8225 | /* QuadSPI - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8226 | /** Peripheral QuadSPI0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 8227 | #define QuadSPI0_BASE (0x4005A000u) |
AnnaBridge | 171:3a7713b1edbc | 8228 | /** Peripheral QuadSPI0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8229 | #define QuadSPI0 ((QuadSPI_Type *)QuadSPI0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8230 | /** Array initializer of QuadSPI peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8231 | #define QuadSPI_BASE_ADDRS { QuadSPI0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8232 | /** Array initializer of QuadSPI peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8233 | #define QuadSPI_BASE_PTRS { QuadSPI0 } |
AnnaBridge | 171:3a7713b1edbc | 8234 | /** Interrupt vectors for the QuadSPI peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 8235 | #define QuadSPI_IRQS { QSPI0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8236 | |
AnnaBridge | 171:3a7713b1edbc | 8237 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8238 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8239 | */ /* end of group QuadSPI_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8240 | |
AnnaBridge | 171:3a7713b1edbc | 8241 | |
AnnaBridge | 171:3a7713b1edbc | 8242 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8243 | -- RCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8244 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8245 | |
AnnaBridge | 171:3a7713b1edbc | 8246 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8247 | * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8248 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8249 | */ |
AnnaBridge | 171:3a7713b1edbc | 8250 | |
AnnaBridge | 171:3a7713b1edbc | 8251 | /** RCM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8252 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8253 | __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8254 | __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 8255 | uint8_t RESERVED_0[2]; |
AnnaBridge | 171:3a7713b1edbc | 8256 | __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8257 | __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */ |
AnnaBridge | 171:3a7713b1edbc | 8258 | __IO uint8_t FM; /**< Force Mode Register, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 8259 | __IO uint8_t MR; /**< Mode Register, offset: 0x7 */ |
AnnaBridge | 171:3a7713b1edbc | 8260 | __IO uint8_t SSRS0; /**< Sticky System Reset Status Register 0, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 8261 | __IO uint8_t SSRS1; /**< Sticky System Reset Status Register 1, offset: 0x9 */ |
AnnaBridge | 171:3a7713b1edbc | 8262 | } RCM_Type; |
AnnaBridge | 171:3a7713b1edbc | 8263 | |
AnnaBridge | 171:3a7713b1edbc | 8264 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8265 | -- RCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8266 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8267 | |
AnnaBridge | 171:3a7713b1edbc | 8268 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8269 | * @addtogroup RCM_Register_Masks RCM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8270 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8271 | */ |
AnnaBridge | 171:3a7713b1edbc | 8272 | |
AnnaBridge | 171:3a7713b1edbc | 8273 | /*! @name SRS0 - System Reset Status Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 8274 | #define RCM_SRS0_WAKEUP_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8275 | #define RCM_SRS0_WAKEUP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8276 | #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8277 | #define RCM_SRS0_LVD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8278 | #define RCM_SRS0_LVD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8279 | #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8280 | #define RCM_SRS0_LOC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8281 | #define RCM_SRS0_LOC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8282 | #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8283 | #define RCM_SRS0_LOL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8284 | #define RCM_SRS0_LOL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8285 | #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8286 | #define RCM_SRS0_WDOG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8287 | #define RCM_SRS0_WDOG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8288 | #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8289 | #define RCM_SRS0_PIN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8290 | #define RCM_SRS0_PIN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8291 | #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8292 | #define RCM_SRS0_POR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8293 | #define RCM_SRS0_POR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8294 | #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8295 | |
AnnaBridge | 171:3a7713b1edbc | 8296 | /*! @name SRS1 - System Reset Status Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 8297 | #define RCM_SRS1_LOCKUP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8298 | #define RCM_SRS1_LOCKUP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8299 | #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8300 | #define RCM_SRS1_SW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8301 | #define RCM_SRS1_SW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8302 | #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8303 | #define RCM_SRS1_MDM_AP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8304 | #define RCM_SRS1_MDM_AP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8305 | #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8306 | #define RCM_SRS1_SACKERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8307 | #define RCM_SRS1_SACKERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8308 | #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8309 | |
AnnaBridge | 171:3a7713b1edbc | 8310 | /*! @name RPFC - Reset Pin Filter Control register */ |
AnnaBridge | 171:3a7713b1edbc | 8311 | #define RCM_RPFC_RSTFLTSRW_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 8312 | #define RCM_RPFC_RSTFLTSRW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8313 | #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8314 | #define RCM_RPFC_RSTFLTSS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8315 | #define RCM_RPFC_RSTFLTSS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8316 | #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8317 | |
AnnaBridge | 171:3a7713b1edbc | 8318 | /*! @name RPFW - Reset Pin Filter Width register */ |
AnnaBridge | 171:3a7713b1edbc | 8319 | #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU) |
AnnaBridge | 171:3a7713b1edbc | 8320 | #define RCM_RPFW_RSTFLTSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8321 | #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8322 | |
AnnaBridge | 171:3a7713b1edbc | 8323 | /*! @name FM - Force Mode Register */ |
AnnaBridge | 171:3a7713b1edbc | 8324 | #define RCM_FM_FORCEROM_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 8325 | #define RCM_FM_FORCEROM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8326 | #define RCM_FM_FORCEROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_FM_FORCEROM_SHIFT)) & RCM_FM_FORCEROM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8327 | |
AnnaBridge | 171:3a7713b1edbc | 8328 | /*! @name MR - Mode Register */ |
AnnaBridge | 171:3a7713b1edbc | 8329 | #define RCM_MR_BOOTROM_MASK (0x6U) |
AnnaBridge | 171:3a7713b1edbc | 8330 | #define RCM_MR_BOOTROM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8331 | #define RCM_MR_BOOTROM(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_BOOTROM_SHIFT)) & RCM_MR_BOOTROM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8332 | |
AnnaBridge | 171:3a7713b1edbc | 8333 | /*! @name SSRS0 - Sticky System Reset Status Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 8334 | #define RCM_SSRS0_SWAKEUP_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8335 | #define RCM_SSRS0_SWAKEUP_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8336 | #define RCM_SSRS0_SWAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8337 | #define RCM_SSRS0_SLVD_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8338 | #define RCM_SSRS0_SLVD_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8339 | #define RCM_SSRS0_SLVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8340 | #define RCM_SSRS0_SLOC_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8341 | #define RCM_SSRS0_SLOC_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8342 | #define RCM_SSRS0_SLOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8343 | #define RCM_SSRS0_SLOL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8344 | #define RCM_SSRS0_SLOL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8345 | #define RCM_SSRS0_SLOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8346 | #define RCM_SSRS0_SWDOG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8347 | #define RCM_SSRS0_SWDOG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8348 | #define RCM_SSRS0_SWDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8349 | #define RCM_SSRS0_SPIN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8350 | #define RCM_SSRS0_SPIN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8351 | #define RCM_SSRS0_SPIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8352 | #define RCM_SSRS0_SPOR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8353 | #define RCM_SSRS0_SPOR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8354 | #define RCM_SSRS0_SPOR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8355 | |
AnnaBridge | 171:3a7713b1edbc | 8356 | /*! @name SSRS1 - Sticky System Reset Status Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 8357 | #define RCM_SSRS1_SLOCKUP_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8358 | #define RCM_SSRS1_SLOCKUP_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8359 | #define RCM_SSRS1_SLOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8360 | #define RCM_SSRS1_SSW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8361 | #define RCM_SSRS1_SSW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8362 | #define RCM_SSRS1_SSW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8363 | #define RCM_SSRS1_SMDM_AP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8364 | #define RCM_SSRS1_SMDM_AP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8365 | #define RCM_SSRS1_SMDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8366 | #define RCM_SSRS1_SSACKERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8367 | #define RCM_SSRS1_SSACKERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8368 | #define RCM_SSRS1_SSACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8369 | |
AnnaBridge | 171:3a7713b1edbc | 8370 | |
AnnaBridge | 171:3a7713b1edbc | 8371 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8372 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8373 | */ /* end of group RCM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8374 | |
AnnaBridge | 171:3a7713b1edbc | 8375 | |
AnnaBridge | 171:3a7713b1edbc | 8376 | /* RCM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8377 | /** Peripheral RCM base address */ |
AnnaBridge | 171:3a7713b1edbc | 8378 | #define RCM_BASE (0x4007F000u) |
AnnaBridge | 171:3a7713b1edbc | 8379 | /** Peripheral RCM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8380 | #define RCM ((RCM_Type *)RCM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8381 | /** Array initializer of RCM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8382 | #define RCM_BASE_ADDRS { RCM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8383 | /** Array initializer of RCM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8384 | #define RCM_BASE_PTRS { RCM } |
AnnaBridge | 171:3a7713b1edbc | 8385 | |
AnnaBridge | 171:3a7713b1edbc | 8386 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8387 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8388 | */ /* end of group RCM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8389 | |
AnnaBridge | 171:3a7713b1edbc | 8390 | |
AnnaBridge | 171:3a7713b1edbc | 8391 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8392 | -- RFSYS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8393 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8394 | |
AnnaBridge | 171:3a7713b1edbc | 8395 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8396 | * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8397 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8398 | */ |
AnnaBridge | 171:3a7713b1edbc | 8399 | |
AnnaBridge | 171:3a7713b1edbc | 8400 | /** RFSYS - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8401 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8402 | __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8403 | } RFSYS_Type; |
AnnaBridge | 171:3a7713b1edbc | 8404 | |
AnnaBridge | 171:3a7713b1edbc | 8405 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8406 | -- RFSYS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8407 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8408 | |
AnnaBridge | 171:3a7713b1edbc | 8409 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8410 | * @addtogroup RFSYS_Register_Masks RFSYS Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8411 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8412 | */ |
AnnaBridge | 171:3a7713b1edbc | 8413 | |
AnnaBridge | 171:3a7713b1edbc | 8414 | /*! @name REG - Register file register */ |
AnnaBridge | 171:3a7713b1edbc | 8415 | #define RFSYS_REG_LL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 8416 | #define RFSYS_REG_LL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8417 | #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8418 | #define RFSYS_REG_LH_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 8419 | #define RFSYS_REG_LH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8420 | #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8421 | #define RFSYS_REG_HL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 8422 | #define RFSYS_REG_HL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8423 | #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8424 | #define RFSYS_REG_HH_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 8425 | #define RFSYS_REG_HH_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8426 | #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8427 | |
AnnaBridge | 171:3a7713b1edbc | 8428 | /* The count of RFSYS_REG */ |
AnnaBridge | 171:3a7713b1edbc | 8429 | #define RFSYS_REG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8430 | |
AnnaBridge | 171:3a7713b1edbc | 8431 | |
AnnaBridge | 171:3a7713b1edbc | 8432 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8433 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8434 | */ /* end of group RFSYS_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8435 | |
AnnaBridge | 171:3a7713b1edbc | 8436 | |
AnnaBridge | 171:3a7713b1edbc | 8437 | /* RFSYS - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8438 | /** Peripheral RFSYS base address */ |
AnnaBridge | 171:3a7713b1edbc | 8439 | #define RFSYS_BASE (0x40041000u) |
AnnaBridge | 171:3a7713b1edbc | 8440 | /** Peripheral RFSYS base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8441 | #define RFSYS ((RFSYS_Type *)RFSYS_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8442 | /** Array initializer of RFSYS peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8443 | #define RFSYS_BASE_ADDRS { RFSYS_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8444 | /** Array initializer of RFSYS peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8445 | #define RFSYS_BASE_PTRS { RFSYS } |
AnnaBridge | 171:3a7713b1edbc | 8446 | |
AnnaBridge | 171:3a7713b1edbc | 8447 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8448 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8449 | */ /* end of group RFSYS_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8450 | |
AnnaBridge | 171:3a7713b1edbc | 8451 | |
AnnaBridge | 171:3a7713b1edbc | 8452 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8453 | -- RFVBAT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8454 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8455 | |
AnnaBridge | 171:3a7713b1edbc | 8456 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8457 | * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8458 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8459 | */ |
AnnaBridge | 171:3a7713b1edbc | 8460 | |
AnnaBridge | 171:3a7713b1edbc | 8461 | /** RFVBAT - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8462 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8463 | __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8464 | } RFVBAT_Type; |
AnnaBridge | 171:3a7713b1edbc | 8465 | |
AnnaBridge | 171:3a7713b1edbc | 8466 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8467 | -- RFVBAT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8468 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8469 | |
AnnaBridge | 171:3a7713b1edbc | 8470 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8471 | * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8472 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8473 | */ |
AnnaBridge | 171:3a7713b1edbc | 8474 | |
AnnaBridge | 171:3a7713b1edbc | 8475 | /*! @name REG - VBAT register file register */ |
AnnaBridge | 171:3a7713b1edbc | 8476 | #define RFVBAT_REG_LL_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 8477 | #define RFVBAT_REG_LL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8478 | #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8479 | #define RFVBAT_REG_LH_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 8480 | #define RFVBAT_REG_LH_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8481 | #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8482 | #define RFVBAT_REG_HL_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 8483 | #define RFVBAT_REG_HL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8484 | #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8485 | #define RFVBAT_REG_HH_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 8486 | #define RFVBAT_REG_HH_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8487 | #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8488 | |
AnnaBridge | 171:3a7713b1edbc | 8489 | /* The count of RFVBAT_REG */ |
AnnaBridge | 171:3a7713b1edbc | 8490 | #define RFVBAT_REG_COUNT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8491 | |
AnnaBridge | 171:3a7713b1edbc | 8492 | |
AnnaBridge | 171:3a7713b1edbc | 8493 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8494 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8495 | */ /* end of group RFVBAT_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8496 | |
AnnaBridge | 171:3a7713b1edbc | 8497 | |
AnnaBridge | 171:3a7713b1edbc | 8498 | /* RFVBAT - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8499 | /** Peripheral RFVBAT base address */ |
AnnaBridge | 171:3a7713b1edbc | 8500 | #define RFVBAT_BASE (0x4003E000u) |
AnnaBridge | 171:3a7713b1edbc | 8501 | /** Peripheral RFVBAT base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8502 | #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8503 | /** Array initializer of RFVBAT peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8504 | #define RFVBAT_BASE_ADDRS { RFVBAT_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8505 | /** Array initializer of RFVBAT peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8506 | #define RFVBAT_BASE_PTRS { RFVBAT } |
AnnaBridge | 171:3a7713b1edbc | 8507 | |
AnnaBridge | 171:3a7713b1edbc | 8508 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8509 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8510 | */ /* end of group RFVBAT_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8511 | |
AnnaBridge | 171:3a7713b1edbc | 8512 | |
AnnaBridge | 171:3a7713b1edbc | 8513 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8514 | -- ROM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8515 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8516 | |
AnnaBridge | 171:3a7713b1edbc | 8517 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8518 | * @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8519 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8520 | */ |
AnnaBridge | 171:3a7713b1edbc | 8521 | |
AnnaBridge | 171:3a7713b1edbc | 8522 | /** ROM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8523 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8524 | __I uint32_t ENTRY[3]; /**< Entry, array offset: 0x0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8525 | __I uint32_t TABLEMARK; /**< End of Table Marker Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 8526 | uint8_t RESERVED_0[4028]; |
AnnaBridge | 171:3a7713b1edbc | 8527 | __I uint32_t SYSACCESS; /**< System Access Register, offset: 0xFCC */ |
AnnaBridge | 171:3a7713b1edbc | 8528 | __I uint32_t PERIPHID4; /**< Peripheral ID Register, offset: 0xFD0 */ |
AnnaBridge | 171:3a7713b1edbc | 8529 | __I uint32_t PERIPHID5; /**< Peripheral ID Register, offset: 0xFD4 */ |
AnnaBridge | 171:3a7713b1edbc | 8530 | __I uint32_t PERIPHID6; /**< Peripheral ID Register, offset: 0xFD8 */ |
AnnaBridge | 171:3a7713b1edbc | 8531 | __I uint32_t PERIPHID7; /**< Peripheral ID Register, offset: 0xFDC */ |
AnnaBridge | 171:3a7713b1edbc | 8532 | __I uint32_t PERIPHID0; /**< Peripheral ID Register, offset: 0xFE0 */ |
AnnaBridge | 171:3a7713b1edbc | 8533 | __I uint32_t PERIPHID1; /**< Peripheral ID Register, offset: 0xFE4 */ |
AnnaBridge | 171:3a7713b1edbc | 8534 | __I uint32_t PERIPHID2; /**< Peripheral ID Register, offset: 0xFE8 */ |
AnnaBridge | 171:3a7713b1edbc | 8535 | __I uint32_t PERIPHID3; /**< Peripheral ID Register, offset: 0xFEC */ |
AnnaBridge | 171:3a7713b1edbc | 8536 | __I uint32_t COMPID[4]; /**< Component ID Register, array offset: 0xFF0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8537 | } ROM_Type; |
AnnaBridge | 171:3a7713b1edbc | 8538 | |
AnnaBridge | 171:3a7713b1edbc | 8539 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8540 | -- ROM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8541 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8542 | |
AnnaBridge | 171:3a7713b1edbc | 8543 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8544 | * @addtogroup ROM_Register_Masks ROM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8545 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8546 | */ |
AnnaBridge | 171:3a7713b1edbc | 8547 | |
AnnaBridge | 171:3a7713b1edbc | 8548 | /*! @name ENTRY - Entry */ |
AnnaBridge | 171:3a7713b1edbc | 8549 | #define ROM_ENTRY_ENTRY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8550 | #define ROM_ENTRY_ENTRY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8551 | #define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << ROM_ENTRY_ENTRY_SHIFT)) & ROM_ENTRY_ENTRY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8552 | |
AnnaBridge | 171:3a7713b1edbc | 8553 | /* The count of ROM_ENTRY */ |
AnnaBridge | 171:3a7713b1edbc | 8554 | #define ROM_ENTRY_COUNT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8555 | |
AnnaBridge | 171:3a7713b1edbc | 8556 | /*! @name TABLEMARK - End of Table Marker Register */ |
AnnaBridge | 171:3a7713b1edbc | 8557 | #define ROM_TABLEMARK_MARK_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8558 | #define ROM_TABLEMARK_MARK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8559 | #define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x)) << ROM_TABLEMARK_MARK_SHIFT)) & ROM_TABLEMARK_MARK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8560 | |
AnnaBridge | 171:3a7713b1edbc | 8561 | /*! @name SYSACCESS - System Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 8562 | #define ROM_SYSACCESS_SYSACCESS_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8563 | #define ROM_SYSACCESS_SYSACCESS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8564 | #define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x)) << ROM_SYSACCESS_SYSACCESS_SHIFT)) & ROM_SYSACCESS_SYSACCESS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8565 | |
AnnaBridge | 171:3a7713b1edbc | 8566 | /*! @name PERIPHID4 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8567 | #define ROM_PERIPHID4_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8568 | #define ROM_PERIPHID4_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8569 | #define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID4_PERIPHID_SHIFT)) & ROM_PERIPHID4_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8570 | |
AnnaBridge | 171:3a7713b1edbc | 8571 | /*! @name PERIPHID5 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8572 | #define ROM_PERIPHID5_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8573 | #define ROM_PERIPHID5_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8574 | #define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID5_PERIPHID_SHIFT)) & ROM_PERIPHID5_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8575 | |
AnnaBridge | 171:3a7713b1edbc | 8576 | /*! @name PERIPHID6 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8577 | #define ROM_PERIPHID6_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8578 | #define ROM_PERIPHID6_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8579 | #define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID6_PERIPHID_SHIFT)) & ROM_PERIPHID6_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8580 | |
AnnaBridge | 171:3a7713b1edbc | 8581 | /*! @name PERIPHID7 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8582 | #define ROM_PERIPHID7_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8583 | #define ROM_PERIPHID7_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8584 | #define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID7_PERIPHID_SHIFT)) & ROM_PERIPHID7_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8585 | |
AnnaBridge | 171:3a7713b1edbc | 8586 | /*! @name PERIPHID0 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8587 | #define ROM_PERIPHID0_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8588 | #define ROM_PERIPHID0_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8589 | #define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID0_PERIPHID_SHIFT)) & ROM_PERIPHID0_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8590 | |
AnnaBridge | 171:3a7713b1edbc | 8591 | /*! @name PERIPHID1 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8592 | #define ROM_PERIPHID1_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8593 | #define ROM_PERIPHID1_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8594 | #define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID1_PERIPHID_SHIFT)) & ROM_PERIPHID1_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8595 | |
AnnaBridge | 171:3a7713b1edbc | 8596 | /*! @name PERIPHID2 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8597 | #define ROM_PERIPHID2_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8598 | #define ROM_PERIPHID2_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8599 | #define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID2_PERIPHID_SHIFT)) & ROM_PERIPHID2_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8600 | |
AnnaBridge | 171:3a7713b1edbc | 8601 | /*! @name PERIPHID3 - Peripheral ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8602 | #define ROM_PERIPHID3_PERIPHID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8603 | #define ROM_PERIPHID3_PERIPHID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8604 | #define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x)) << ROM_PERIPHID3_PERIPHID_SHIFT)) & ROM_PERIPHID3_PERIPHID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8605 | |
AnnaBridge | 171:3a7713b1edbc | 8606 | /*! @name COMPID - Component ID Register */ |
AnnaBridge | 171:3a7713b1edbc | 8607 | #define ROM_COMPID_COMPID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8608 | #define ROM_COMPID_COMPID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8609 | #define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x)) << ROM_COMPID_COMPID_SHIFT)) & ROM_COMPID_COMPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8610 | |
AnnaBridge | 171:3a7713b1edbc | 8611 | /* The count of ROM_COMPID */ |
AnnaBridge | 171:3a7713b1edbc | 8612 | #define ROM_COMPID_COUNT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8613 | |
AnnaBridge | 171:3a7713b1edbc | 8614 | |
AnnaBridge | 171:3a7713b1edbc | 8615 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8616 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8617 | */ /* end of group ROM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8618 | |
AnnaBridge | 171:3a7713b1edbc | 8619 | |
AnnaBridge | 171:3a7713b1edbc | 8620 | /* ROM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8621 | /** Peripheral ROM base address */ |
AnnaBridge | 171:3a7713b1edbc | 8622 | #define ROM_BASE (0xF0002000u) |
AnnaBridge | 171:3a7713b1edbc | 8623 | /** Peripheral ROM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8624 | #define ROM ((ROM_Type *)ROM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8625 | /** Array initializer of ROM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8626 | #define ROM_BASE_ADDRS { ROM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8627 | /** Array initializer of ROM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8628 | #define ROM_BASE_PTRS { ROM } |
AnnaBridge | 171:3a7713b1edbc | 8629 | |
AnnaBridge | 171:3a7713b1edbc | 8630 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8631 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8632 | */ /* end of group ROM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8633 | |
AnnaBridge | 171:3a7713b1edbc | 8634 | |
AnnaBridge | 171:3a7713b1edbc | 8635 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8636 | -- RTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8637 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8638 | |
AnnaBridge | 171:3a7713b1edbc | 8639 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8640 | * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8641 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8642 | */ |
AnnaBridge | 171:3a7713b1edbc | 8643 | |
AnnaBridge | 171:3a7713b1edbc | 8644 | /** RTC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8645 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8646 | __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8647 | __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 8648 | __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 8649 | __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 8650 | __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 8651 | __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 8652 | __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 8653 | __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 8654 | uint8_t RESERVED_0[2016]; |
AnnaBridge | 171:3a7713b1edbc | 8655 | __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */ |
AnnaBridge | 171:3a7713b1edbc | 8656 | __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */ |
AnnaBridge | 171:3a7713b1edbc | 8657 | } RTC_Type; |
AnnaBridge | 171:3a7713b1edbc | 8658 | |
AnnaBridge | 171:3a7713b1edbc | 8659 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8660 | -- RTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8661 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8662 | |
AnnaBridge | 171:3a7713b1edbc | 8663 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8664 | * @addtogroup RTC_Register_Masks RTC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8665 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8666 | */ |
AnnaBridge | 171:3a7713b1edbc | 8667 | |
AnnaBridge | 171:3a7713b1edbc | 8668 | /*! @name TSR - RTC Time Seconds Register */ |
AnnaBridge | 171:3a7713b1edbc | 8669 | #define RTC_TSR_TSR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8670 | #define RTC_TSR_TSR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8671 | #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8672 | |
AnnaBridge | 171:3a7713b1edbc | 8673 | /*! @name TPR - RTC Time Prescaler Register */ |
AnnaBridge | 171:3a7713b1edbc | 8674 | #define RTC_TPR_TPR_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8675 | #define RTC_TPR_TPR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8676 | #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8677 | |
AnnaBridge | 171:3a7713b1edbc | 8678 | /*! @name TAR - RTC Time Alarm Register */ |
AnnaBridge | 171:3a7713b1edbc | 8679 | #define RTC_TAR_TAR_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 8680 | #define RTC_TAR_TAR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8681 | #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8682 | |
AnnaBridge | 171:3a7713b1edbc | 8683 | /*! @name TCR - RTC Time Compensation Register */ |
AnnaBridge | 171:3a7713b1edbc | 8684 | #define RTC_TCR_TCR_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 8685 | #define RTC_TCR_TCR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8686 | #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8687 | #define RTC_TCR_CIR_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 8688 | #define RTC_TCR_CIR_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8689 | #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8690 | #define RTC_TCR_TCV_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 8691 | #define RTC_TCR_TCV_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8692 | #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8693 | #define RTC_TCR_CIC_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 8694 | #define RTC_TCR_CIC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8695 | #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8696 | |
AnnaBridge | 171:3a7713b1edbc | 8697 | /*! @name CR - RTC Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 8698 | #define RTC_CR_SWR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8699 | #define RTC_CR_SWR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8700 | #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8701 | #define RTC_CR_WPE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8702 | #define RTC_CR_WPE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8703 | #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8704 | #define RTC_CR_SUP_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8705 | #define RTC_CR_SUP_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8706 | #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8707 | #define RTC_CR_UM_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8708 | #define RTC_CR_UM_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8709 | #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8710 | #define RTC_CR_WPS_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8711 | #define RTC_CR_WPS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8712 | #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8713 | #define RTC_CR_OSCE_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 8714 | #define RTC_CR_OSCE_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 8715 | #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8716 | #define RTC_CR_CLKO_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 8717 | #define RTC_CR_CLKO_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 8718 | #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8719 | #define RTC_CR_SC16P_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 8720 | #define RTC_CR_SC16P_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 8721 | #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8722 | #define RTC_CR_SC8P_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 8723 | #define RTC_CR_SC8P_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 8724 | #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8725 | #define RTC_CR_SC4P_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 8726 | #define RTC_CR_SC4P_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8727 | #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8728 | #define RTC_CR_SC2P_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 8729 | #define RTC_CR_SC2P_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 8730 | #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8731 | |
AnnaBridge | 171:3a7713b1edbc | 8732 | /*! @name SR - RTC Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 8733 | #define RTC_SR_TIF_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8734 | #define RTC_SR_TIF_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8735 | #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8736 | #define RTC_SR_TOF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8737 | #define RTC_SR_TOF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8738 | #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8739 | #define RTC_SR_TAF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8740 | #define RTC_SR_TAF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8741 | #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8742 | #define RTC_SR_TCE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8743 | #define RTC_SR_TCE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8744 | #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8745 | |
AnnaBridge | 171:3a7713b1edbc | 8746 | /*! @name LR - RTC Lock Register */ |
AnnaBridge | 171:3a7713b1edbc | 8747 | #define RTC_LR_TCL_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8748 | #define RTC_LR_TCL_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8749 | #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8750 | #define RTC_LR_CRL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8751 | #define RTC_LR_CRL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8752 | #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8753 | #define RTC_LR_SRL_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8754 | #define RTC_LR_SRL_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8755 | #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8756 | #define RTC_LR_LRL_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8757 | #define RTC_LR_LRL_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8758 | #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8759 | |
AnnaBridge | 171:3a7713b1edbc | 8760 | /*! @name IER - RTC Interrupt Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 8761 | #define RTC_IER_TIIE_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8762 | #define RTC_IER_TIIE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8763 | #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8764 | #define RTC_IER_TOIE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8765 | #define RTC_IER_TOIE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8766 | #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8767 | #define RTC_IER_TAIE_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8768 | #define RTC_IER_TAIE_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8769 | #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8770 | #define RTC_IER_TSIE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8771 | #define RTC_IER_TSIE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8772 | #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8773 | #define RTC_IER_WPON_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8774 | #define RTC_IER_WPON_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8775 | #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8776 | |
AnnaBridge | 171:3a7713b1edbc | 8777 | /*! @name WAR - RTC Write Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 8778 | #define RTC_WAR_TSRW_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8779 | #define RTC_WAR_TSRW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8780 | #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8781 | #define RTC_WAR_TPRW_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8782 | #define RTC_WAR_TPRW_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8783 | #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8784 | #define RTC_WAR_TARW_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8785 | #define RTC_WAR_TARW_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8786 | #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8787 | #define RTC_WAR_TCRW_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8788 | #define RTC_WAR_TCRW_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8789 | #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8790 | #define RTC_WAR_CRW_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8791 | #define RTC_WAR_CRW_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8792 | #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8793 | #define RTC_WAR_SRW_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8794 | #define RTC_WAR_SRW_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8795 | #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8796 | #define RTC_WAR_LRW_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8797 | #define RTC_WAR_LRW_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8798 | #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8799 | #define RTC_WAR_IERW_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8800 | #define RTC_WAR_IERW_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8801 | #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8802 | |
AnnaBridge | 171:3a7713b1edbc | 8803 | /*! @name RAR - RTC Read Access Register */ |
AnnaBridge | 171:3a7713b1edbc | 8804 | #define RTC_RAR_TSRR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 8805 | #define RTC_RAR_TSRR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8806 | #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8807 | #define RTC_RAR_TPRR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 8808 | #define RTC_RAR_TPRR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 8809 | #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8810 | #define RTC_RAR_TARR_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 8811 | #define RTC_RAR_TARR_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 8812 | #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8813 | #define RTC_RAR_TCRR_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 8814 | #define RTC_RAR_TCRR_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 8815 | #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8816 | #define RTC_RAR_CRR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8817 | #define RTC_RAR_CRR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8818 | #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8819 | #define RTC_RAR_SRR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 8820 | #define RTC_RAR_SRR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8821 | #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8822 | #define RTC_RAR_LRR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 8823 | #define RTC_RAR_LRR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 8824 | #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8825 | #define RTC_RAR_IERR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 8826 | #define RTC_RAR_IERR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8827 | #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8828 | |
AnnaBridge | 171:3a7713b1edbc | 8829 | |
AnnaBridge | 171:3a7713b1edbc | 8830 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8831 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8832 | */ /* end of group RTC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 8833 | |
AnnaBridge | 171:3a7713b1edbc | 8834 | |
AnnaBridge | 171:3a7713b1edbc | 8835 | /* RTC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8836 | /** Peripheral RTC base address */ |
AnnaBridge | 171:3a7713b1edbc | 8837 | #define RTC_BASE (0x4003D000u) |
AnnaBridge | 171:3a7713b1edbc | 8838 | /** Peripheral RTC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 8839 | #define RTC ((RTC_Type *)RTC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 8840 | /** Array initializer of RTC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 8841 | #define RTC_BASE_ADDRS { RTC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 8842 | /** Array initializer of RTC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 8843 | #define RTC_BASE_PTRS { RTC } |
AnnaBridge | 171:3a7713b1edbc | 8844 | /** Interrupt vectors for the RTC peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 8845 | #define RTC_IRQS { RTC_Alarm_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8846 | #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 8847 | |
AnnaBridge | 171:3a7713b1edbc | 8848 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8849 | * @} |
AnnaBridge | 171:3a7713b1edbc | 8850 | */ /* end of group RTC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 8851 | |
AnnaBridge | 171:3a7713b1edbc | 8852 | |
AnnaBridge | 171:3a7713b1edbc | 8853 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8854 | -- SIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8855 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8856 | |
AnnaBridge | 171:3a7713b1edbc | 8857 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8858 | * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 8859 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8860 | */ |
AnnaBridge | 171:3a7713b1edbc | 8861 | |
AnnaBridge | 171:3a7713b1edbc | 8862 | /** SIM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 8863 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 8864 | __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 8865 | uint8_t RESERVED_0[4096]; |
AnnaBridge | 171:3a7713b1edbc | 8866 | __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */ |
AnnaBridge | 171:3a7713b1edbc | 8867 | uint8_t RESERVED_1[8]; |
AnnaBridge | 171:3a7713b1edbc | 8868 | __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */ |
AnnaBridge | 171:3a7713b1edbc | 8869 | uint8_t RESERVED_2[4]; |
AnnaBridge | 171:3a7713b1edbc | 8870 | __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */ |
AnnaBridge | 171:3a7713b1edbc | 8871 | uint8_t RESERVED_3[4]; |
AnnaBridge | 171:3a7713b1edbc | 8872 | __IO uint32_t SOPT9; /**< System Options Register 9, offset: 0x1020 */ |
AnnaBridge | 171:3a7713b1edbc | 8873 | __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */ |
AnnaBridge | 171:3a7713b1edbc | 8874 | uint8_t RESERVED_4[12]; |
AnnaBridge | 171:3a7713b1edbc | 8875 | __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */ |
AnnaBridge | 171:3a7713b1edbc | 8876 | __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */ |
AnnaBridge | 171:3a7713b1edbc | 8877 | __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */ |
AnnaBridge | 171:3a7713b1edbc | 8878 | __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */ |
AnnaBridge | 171:3a7713b1edbc | 8879 | __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */ |
AnnaBridge | 171:3a7713b1edbc | 8880 | __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */ |
AnnaBridge | 171:3a7713b1edbc | 8881 | __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */ |
AnnaBridge | 171:3a7713b1edbc | 8882 | __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */ |
AnnaBridge | 171:3a7713b1edbc | 8883 | __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */ |
AnnaBridge | 171:3a7713b1edbc | 8884 | __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */ |
AnnaBridge | 171:3a7713b1edbc | 8885 | __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */ |
AnnaBridge | 171:3a7713b1edbc | 8886 | __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */ |
AnnaBridge | 171:3a7713b1edbc | 8887 | __IO uint32_t CLKDIV3; /**< System Clock Divider Register 3, offset: 0x1064 */ |
AnnaBridge | 171:3a7713b1edbc | 8888 | uint8_t RESERVED_5[4]; |
AnnaBridge | 171:3a7713b1edbc | 8889 | __IO uint32_t MISCCTRL; /**< Misc Control Register, offset: 0x106C */ |
AnnaBridge | 171:3a7713b1edbc | 8890 | uint8_t RESERVED_6[32]; |
AnnaBridge | 171:3a7713b1edbc | 8891 | __I uint32_t SECKEY0; /**< Secure Key Register 0, offset: 0x1090 */ |
AnnaBridge | 171:3a7713b1edbc | 8892 | __I uint32_t SECKEY1; /**< Secure Key Register 1, offset: 0x1094 */ |
AnnaBridge | 171:3a7713b1edbc | 8893 | __I uint32_t SECKEY2; /**< Secure Key Register 2, offset: 0x1098 */ |
AnnaBridge | 171:3a7713b1edbc | 8894 | __I uint32_t SECKEY3; /**< Secure Key Register 3, offset: 0x109C */ |
AnnaBridge | 171:3a7713b1edbc | 8895 | } SIM_Type; |
AnnaBridge | 171:3a7713b1edbc | 8896 | |
AnnaBridge | 171:3a7713b1edbc | 8897 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 8898 | -- SIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8899 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 8900 | |
AnnaBridge | 171:3a7713b1edbc | 8901 | /*! |
AnnaBridge | 171:3a7713b1edbc | 8902 | * @addtogroup SIM_Register_Masks SIM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 8903 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 8904 | */ |
AnnaBridge | 171:3a7713b1edbc | 8905 | |
AnnaBridge | 171:3a7713b1edbc | 8906 | /*! @name SOPT1 - System Options Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 8907 | #define SIM_SOPT1_RAMSIZE_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 8908 | #define SIM_SOPT1_RAMSIZE_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8909 | #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8910 | #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 8911 | #define SIM_SOPT1_OSC32KSEL_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8912 | #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8913 | |
AnnaBridge | 171:3a7713b1edbc | 8914 | /*! @name SOPT2 - System Options Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 8915 | #define SIM_SOPT2_RTCCLKOUTS_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8916 | #define SIM_SOPT2_RTCCLKOUTS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8917 | #define SIM_SOPT2_RTCCLKOUTS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTS_SHIFT)) & SIM_SOPT2_RTCCLKOUTS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8918 | #define SIM_SOPT2_CLKOUT_MASK (0xE0U) |
AnnaBridge | 171:3a7713b1edbc | 8919 | #define SIM_SOPT2_CLKOUT_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 8920 | #define SIM_SOPT2_CLKOUT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUT_SHIFT)) & SIM_SOPT2_CLKOUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8921 | #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 8922 | #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8923 | #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8924 | #define SIM_SOPT2_USBSRC_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 8925 | #define SIM_SOPT2_USBSRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8926 | #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8927 | #define SIM_SOPT2_FLEXIOSRC_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 8928 | #define SIM_SOPT2_FLEXIOSRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8929 | #define SIM_SOPT2_FLEXIOSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FLEXIOSRC_SHIFT)) & SIM_SOPT2_FLEXIOSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8930 | #define SIM_SOPT2_TPMSRC_MASK (0x3000000U) |
AnnaBridge | 171:3a7713b1edbc | 8931 | #define SIM_SOPT2_TPMSRC_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8932 | #define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8933 | #define SIM_SOPT2_LPUARTSRC_MASK (0xC000000U) |
AnnaBridge | 171:3a7713b1edbc | 8934 | #define SIM_SOPT2_LPUARTSRC_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8935 | #define SIM_SOPT2_LPUARTSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8936 | #define SIM_SOPT2_EMVSIMSRC_MASK (0xC0000000U) |
AnnaBridge | 171:3a7713b1edbc | 8937 | #define SIM_SOPT2_EMVSIMSRC_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 8938 | #define SIM_SOPT2_EMVSIMSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_EMVSIMSRC_SHIFT)) & SIM_SOPT2_EMVSIMSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8939 | |
AnnaBridge | 171:3a7713b1edbc | 8940 | /*! @name SOPT5 - System Options Register 5 */ |
AnnaBridge | 171:3a7713b1edbc | 8941 | #define SIM_SOPT5_LPUART0TXSRC_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 8942 | #define SIM_SOPT5_LPUART0TXSRC_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 8943 | #define SIM_SOPT5_LPUART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8944 | #define SIM_SOPT5_LPUART0RXSRC_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 8945 | #define SIM_SOPT5_LPUART0RXSRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8946 | #define SIM_SOPT5_LPUART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8947 | #define SIM_SOPT5_LPUART1TXSRC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 8948 | #define SIM_SOPT5_LPUART1TXSRC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8949 | #define SIM_SOPT5_LPUART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1TXSRC_SHIFT)) & SIM_SOPT5_LPUART1TXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8950 | #define SIM_SOPT5_LPUART1RXSRC_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 8951 | #define SIM_SOPT5_LPUART1RXSRC_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 8952 | #define SIM_SOPT5_LPUART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART1RXSRC_SHIFT)) & SIM_SOPT5_LPUART1RXSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8953 | |
AnnaBridge | 171:3a7713b1edbc | 8954 | /*! @name SOPT7 - System Options Register 7 */ |
AnnaBridge | 171:3a7713b1edbc | 8955 | #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 8956 | #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8957 | #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8958 | #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 8959 | #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8960 | #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8961 | |
AnnaBridge | 171:3a7713b1edbc | 8962 | /*! @name SOPT9 - System Options Register 9 */ |
AnnaBridge | 171:3a7713b1edbc | 8963 | #define SIM_SOPT9_TPM1CH0SRC_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 8964 | #define SIM_SOPT9_TPM1CH0SRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 8965 | #define SIM_SOPT9_TPM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8966 | #define SIM_SOPT9_TPM2CH0SRC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 8967 | #define SIM_SOPT9_TPM2CH0SRC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 8968 | #define SIM_SOPT9_TPM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8969 | #define SIM_SOPT9_TPM0CLKSEL_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 8970 | #define SIM_SOPT9_TPM0CLKSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8971 | #define SIM_SOPT9_TPM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM0CLKSEL_SHIFT)) & SIM_SOPT9_TPM0CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8972 | #define SIM_SOPT9_TPM1CLKSEL_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 8973 | #define SIM_SOPT9_TPM1CLKSEL_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 8974 | #define SIM_SOPT9_TPM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8975 | #define SIM_SOPT9_TPM2CLKSEL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 8976 | #define SIM_SOPT9_TPM2CLKSEL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 8977 | #define SIM_SOPT9_TPM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8978 | |
AnnaBridge | 171:3a7713b1edbc | 8979 | /*! @name SDID - System Device Identification Register */ |
AnnaBridge | 171:3a7713b1edbc | 8980 | #define SIM_SDID_PINID_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 8981 | #define SIM_SDID_PINID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 8982 | #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8983 | #define SIM_SDID_FAMID_MASK (0x70U) |
AnnaBridge | 171:3a7713b1edbc | 8984 | #define SIM_SDID_FAMID_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 8985 | #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8986 | #define SIM_SDID_DIEID_MASK (0xF80U) |
AnnaBridge | 171:3a7713b1edbc | 8987 | #define SIM_SDID_DIEID_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 8988 | #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8989 | #define SIM_SDID_REVID_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 8990 | #define SIM_SDID_REVID_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 8991 | #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8992 | #define SIM_SDID_SUBFAMID_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 8993 | #define SIM_SDID_SUBFAMID_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 8994 | #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8995 | #define SIM_SDID_FAMILYID_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 8996 | #define SIM_SDID_FAMILYID_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 8997 | #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 8998 | |
AnnaBridge | 171:3a7713b1edbc | 8999 | /*! @name SCGC4 - System Clock Gating Control Register 4 */ |
AnnaBridge | 171:3a7713b1edbc | 9000 | #define SIM_SCGC4_EWM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9001 | #define SIM_SCGC4_EWM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9002 | #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9003 | #define SIM_SCGC4_I2C0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9004 | #define SIM_SCGC4_I2C0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9005 | #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9006 | #define SIM_SCGC4_I2C1_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9007 | #define SIM_SCGC4_I2C1_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9008 | #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9009 | #define SIM_SCGC4_USBOTG_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 9010 | #define SIM_SCGC4_USBOTG_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 9011 | #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9012 | #define SIM_SCGC4_CMP_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 9013 | #define SIM_SCGC4_CMP_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 9014 | #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9015 | #define SIM_SCGC4_VREF_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 9016 | #define SIM_SCGC4_VREF_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9017 | #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9018 | |
AnnaBridge | 171:3a7713b1edbc | 9019 | /*! @name SCGC5 - System Clock Gating Control Register 5 */ |
AnnaBridge | 171:3a7713b1edbc | 9020 | #define SIM_SCGC5_LPTMR0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9021 | #define SIM_SCGC5_LPTMR0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9022 | #define SIM_SCGC5_LPTMR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR0_SHIFT)) & SIM_SCGC5_LPTMR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9023 | #define SIM_SCGC5_SECREG_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9024 | #define SIM_SCGC5_SECREG_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9025 | #define SIM_SCGC5_SECREG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_SECREG_SHIFT)) & SIM_SCGC5_SECREG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9026 | #define SIM_SCGC5_LPTMR1_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9027 | #define SIM_SCGC5_LPTMR1_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9028 | #define SIM_SCGC5_LPTMR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR1_SHIFT)) & SIM_SCGC5_LPTMR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9029 | #define SIM_SCGC5_TSI_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9030 | #define SIM_SCGC5_TSI_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9031 | #define SIM_SCGC5_TSI(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9032 | #define SIM_SCGC5_PTA_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 9033 | #define SIM_SCGC5_PTA_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 9034 | #define SIM_SCGC5_PTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTA_SHIFT)) & SIM_SCGC5_PTA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9035 | #define SIM_SCGC5_PTB_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 9036 | #define SIM_SCGC5_PTB_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 9037 | #define SIM_SCGC5_PTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTB_SHIFT)) & SIM_SCGC5_PTB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9038 | #define SIM_SCGC5_PTC_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 9039 | #define SIM_SCGC5_PTC_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 9040 | #define SIM_SCGC5_PTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTC_SHIFT)) & SIM_SCGC5_PTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9041 | #define SIM_SCGC5_PTD_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 9042 | #define SIM_SCGC5_PTD_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9043 | #define SIM_SCGC5_PTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTD_SHIFT)) & SIM_SCGC5_PTD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9044 | #define SIM_SCGC5_PTE_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 9045 | #define SIM_SCGC5_PTE_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 9046 | #define SIM_SCGC5_PTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PTE_SHIFT)) & SIM_SCGC5_PTE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9047 | #define SIM_SCGC5_EMVSIM0_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 9048 | #define SIM_SCGC5_EMVSIM0_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 9049 | #define SIM_SCGC5_EMVSIM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_EMVSIM0_SHIFT)) & SIM_SCGC5_EMVSIM0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9050 | #define SIM_SCGC5_EMVSIM1_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 9051 | #define SIM_SCGC5_EMVSIM1_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 9052 | #define SIM_SCGC5_EMVSIM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_EMVSIM1_SHIFT)) & SIM_SCGC5_EMVSIM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9053 | #define SIM_SCGC5_LTC_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9054 | #define SIM_SCGC5_LTC_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9055 | #define SIM_SCGC5_LTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LTC_SHIFT)) & SIM_SCGC5_LTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9056 | #define SIM_SCGC5_LPUART0_MASK (0x100000U) |
AnnaBridge | 171:3a7713b1edbc | 9057 | #define SIM_SCGC5_LPUART0_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9058 | #define SIM_SCGC5_LPUART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART0_SHIFT)) & SIM_SCGC5_LPUART0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9059 | #define SIM_SCGC5_LPUART1_MASK (0x200000U) |
AnnaBridge | 171:3a7713b1edbc | 9060 | #define SIM_SCGC5_LPUART1_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 9061 | #define SIM_SCGC5_LPUART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART1_SHIFT)) & SIM_SCGC5_LPUART1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9062 | #define SIM_SCGC5_LPUART2_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 9063 | #define SIM_SCGC5_LPUART2_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 9064 | #define SIM_SCGC5_LPUART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPUART2_SHIFT)) & SIM_SCGC5_LPUART2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9065 | #define SIM_SCGC5_QSPI0_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9066 | #define SIM_SCGC5_QSPI0_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9067 | #define SIM_SCGC5_QSPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_QSPI0_SHIFT)) & SIM_SCGC5_QSPI0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9068 | #define SIM_SCGC5_FLEXIO0_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9069 | #define SIM_SCGC5_FLEXIO0_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9070 | #define SIM_SCGC5_FLEXIO0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_FLEXIO0_SHIFT)) & SIM_SCGC5_FLEXIO0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9071 | |
AnnaBridge | 171:3a7713b1edbc | 9072 | /*! @name SCGC6 - System Clock Gating Control Register 6 */ |
AnnaBridge | 171:3a7713b1edbc | 9073 | #define SIM_SCGC6_NVM_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9074 | #define SIM_SCGC6_NVM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9075 | #define SIM_SCGC6_NVM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_NVM_SHIFT)) & SIM_SCGC6_NVM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9076 | #define SIM_SCGC6_DMACHMUX_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9077 | #define SIM_SCGC6_DMACHMUX_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9078 | #define SIM_SCGC6_DMACHMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMACHMUX_SHIFT)) & SIM_SCGC6_DMACHMUX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9079 | #define SIM_SCGC6_INTMUX0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9080 | #define SIM_SCGC6_INTMUX0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9081 | #define SIM_SCGC6_INTMUX0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_INTMUX0_SHIFT)) & SIM_SCGC6_INTMUX0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9082 | #define SIM_SCGC6_TRNG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9083 | #define SIM_SCGC6_TRNG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9084 | #define SIM_SCGC6_TRNG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TRNG_SHIFT)) & SIM_SCGC6_TRNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9085 | #define SIM_SCGC6_SPI0_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 9086 | #define SIM_SCGC6_SPI0_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9087 | #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9088 | #define SIM_SCGC6_SPI1_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 9089 | #define SIM_SCGC6_SPI1_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 9090 | #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9091 | #define SIM_SCGC6_CRC_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 9092 | #define SIM_SCGC6_CRC_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 9093 | #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9094 | #define SIM_SCGC6_PIT0_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 9095 | #define SIM_SCGC6_PIT0_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 9096 | #define SIM_SCGC6_PIT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT0_SHIFT)) & SIM_SCGC6_PIT0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9097 | #define SIM_SCGC6_TPM0_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 9098 | #define SIM_SCGC6_TPM0_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9099 | #define SIM_SCGC6_TPM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM0_SHIFT)) & SIM_SCGC6_TPM0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9100 | #define SIM_SCGC6_TPM1_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9101 | #define SIM_SCGC6_TPM1_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9102 | #define SIM_SCGC6_TPM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM1_SHIFT)) & SIM_SCGC6_TPM1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9103 | #define SIM_SCGC6_TPM2_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9104 | #define SIM_SCGC6_TPM2_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9105 | #define SIM_SCGC6_TPM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_TPM2_SHIFT)) & SIM_SCGC6_TPM2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9106 | #define SIM_SCGC6_ADC0_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9107 | #define SIM_SCGC6_ADC0_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9108 | #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9109 | #define SIM_SCGC6_RTC_MASK (0x20000000U) |
AnnaBridge | 171:3a7713b1edbc | 9110 | #define SIM_SCGC6_RTC_SHIFT (29U) |
AnnaBridge | 171:3a7713b1edbc | 9111 | #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9112 | #define SIM_SCGC6_RTC_RF_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9113 | #define SIM_SCGC6_RTC_RF_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9114 | #define SIM_SCGC6_RTC_RF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_RF_SHIFT)) & SIM_SCGC6_RTC_RF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9115 | #define SIM_SCGC6_DAC0_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9116 | #define SIM_SCGC6_DAC0_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9117 | #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9118 | |
AnnaBridge | 171:3a7713b1edbc | 9119 | /*! @name SCGC7 - System Clock Gating Control Register 7 */ |
AnnaBridge | 171:3a7713b1edbc | 9120 | #define SIM_SCGC7_DMA_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9121 | #define SIM_SCGC7_DMA_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9122 | #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9123 | #define SIM_SCGC7_MPU_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9124 | #define SIM_SCGC7_MPU_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9125 | #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9126 | |
AnnaBridge | 171:3a7713b1edbc | 9127 | /*! @name CLKDIV1 - System Clock Divider Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 9128 | #define SIM_CLKDIV1_OUTDIV5_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 9129 | #define SIM_CLKDIV1_OUTDIV5_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9130 | #define SIM_CLKDIV1_OUTDIV5(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV5_SHIFT)) & SIM_CLKDIV1_OUTDIV5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9131 | #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9132 | #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9133 | #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9134 | #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 9135 | #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9136 | #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9137 | #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 9138 | #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9139 | #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9140 | |
AnnaBridge | 171:3a7713b1edbc | 9141 | /*! @name CLKDIV2 - System Clock Divider Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 9142 | #define SIM_CLKDIV2_USBFRAC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9143 | #define SIM_CLKDIV2_USBFRAC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9144 | #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9145 | #define SIM_CLKDIV2_USBDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 9146 | #define SIM_CLKDIV2_USBDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9147 | #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9148 | |
AnnaBridge | 171:3a7713b1edbc | 9149 | /*! @name FCFG1 - Flash Configuration Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 9150 | #define SIM_FCFG1_FLASHDIS_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9151 | #define SIM_FCFG1_FLASHDIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9152 | #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9153 | #define SIM_FCFG1_FLASHDOZE_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9154 | #define SIM_FCFG1_FLASHDOZE_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9155 | #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9156 | #define SIM_FCFG1_PFSIZE_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 9157 | #define SIM_FCFG1_PFSIZE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9158 | #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9159 | |
AnnaBridge | 171:3a7713b1edbc | 9160 | /*! @name FCFG2 - Flash Configuration Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 9161 | #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U) |
AnnaBridge | 171:3a7713b1edbc | 9162 | #define SIM_FCFG2_MAXADDR0_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9163 | #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9164 | |
AnnaBridge | 171:3a7713b1edbc | 9165 | /*! @name UIDH - Unique Identification Register High */ |
AnnaBridge | 171:3a7713b1edbc | 9166 | #define SIM_UIDH_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9167 | #define SIM_UIDH_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9168 | #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9169 | |
AnnaBridge | 171:3a7713b1edbc | 9170 | /*! @name UIDMH - Unique Identification Register Mid-High */ |
AnnaBridge | 171:3a7713b1edbc | 9171 | #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9172 | #define SIM_UIDMH_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9173 | #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9174 | |
AnnaBridge | 171:3a7713b1edbc | 9175 | /*! @name UIDML - Unique Identification Register Mid Low */ |
AnnaBridge | 171:3a7713b1edbc | 9176 | #define SIM_UIDML_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9177 | #define SIM_UIDML_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9178 | #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9179 | |
AnnaBridge | 171:3a7713b1edbc | 9180 | /*! @name UIDL - Unique Identification Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 9181 | #define SIM_UIDL_UID_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9182 | #define SIM_UIDL_UID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9183 | #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9184 | |
AnnaBridge | 171:3a7713b1edbc | 9185 | /*! @name CLKDIV3 - System Clock Divider Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 9186 | #define SIM_CLKDIV3_PLLFLLFRAC_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9187 | #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9188 | #define SIM_CLKDIV3_PLLFLLFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9189 | #define SIM_CLKDIV3_PLLFLLDIV_MASK (0xEU) |
AnnaBridge | 171:3a7713b1edbc | 9190 | #define SIM_CLKDIV3_PLLFLLDIV_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9191 | #define SIM_CLKDIV3_PLLFLLDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9192 | |
AnnaBridge | 171:3a7713b1edbc | 9193 | /*! @name MISCCTRL - Misc Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 9194 | #define SIM_MISCCTRL_DMAINTSEL0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9195 | #define SIM_MISCCTRL_DMAINTSEL0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9196 | #define SIM_MISCCTRL_DMAINTSEL0(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL0_SHIFT)) & SIM_MISCCTRL_DMAINTSEL0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9197 | #define SIM_MISCCTRL_DMAINTSEL1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9198 | #define SIM_MISCCTRL_DMAINTSEL1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9199 | #define SIM_MISCCTRL_DMAINTSEL1(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL1_SHIFT)) & SIM_MISCCTRL_DMAINTSEL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9200 | #define SIM_MISCCTRL_DMAINTSEL2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9201 | #define SIM_MISCCTRL_DMAINTSEL2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9202 | #define SIM_MISCCTRL_DMAINTSEL2(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL2_SHIFT)) & SIM_MISCCTRL_DMAINTSEL2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9203 | #define SIM_MISCCTRL_DMAINTSEL3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9204 | #define SIM_MISCCTRL_DMAINTSEL3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9205 | #define SIM_MISCCTRL_DMAINTSEL3(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_DMAINTSEL3_SHIFT)) & SIM_MISCCTRL_DMAINTSEL3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9206 | #define SIM_MISCCTRL_LTCEN_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 9207 | #define SIM_MISCCTRL_LTCEN_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9208 | #define SIM_MISCCTRL_LTCEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_MISCCTRL_LTCEN_SHIFT)) & SIM_MISCCTRL_LTCEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9209 | |
AnnaBridge | 171:3a7713b1edbc | 9210 | /*! @name SECKEY0 - Secure Key Register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 9211 | #define SIM_SECKEY0_SECKEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9212 | #define SIM_SECKEY0_SECKEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9213 | #define SIM_SECKEY0_SECKEY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY0_SECKEY_SHIFT)) & SIM_SECKEY0_SECKEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9214 | |
AnnaBridge | 171:3a7713b1edbc | 9215 | /*! @name SECKEY1 - Secure Key Register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 9216 | #define SIM_SECKEY1_SECKEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9217 | #define SIM_SECKEY1_SECKEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9218 | #define SIM_SECKEY1_SECKEY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY1_SECKEY_SHIFT)) & SIM_SECKEY1_SECKEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9219 | |
AnnaBridge | 171:3a7713b1edbc | 9220 | /*! @name SECKEY2 - Secure Key Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 9221 | #define SIM_SECKEY2_SECKEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9222 | #define SIM_SECKEY2_SECKEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9223 | #define SIM_SECKEY2_SECKEY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY2_SECKEY_SHIFT)) & SIM_SECKEY2_SECKEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9224 | |
AnnaBridge | 171:3a7713b1edbc | 9225 | /*! @name SECKEY3 - Secure Key Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 9226 | #define SIM_SECKEY3_SECKEY_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9227 | #define SIM_SECKEY3_SECKEY_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9228 | #define SIM_SECKEY3_SECKEY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SECKEY3_SECKEY_SHIFT)) & SIM_SECKEY3_SECKEY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9229 | |
AnnaBridge | 171:3a7713b1edbc | 9230 | |
AnnaBridge | 171:3a7713b1edbc | 9231 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9232 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9233 | */ /* end of group SIM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9234 | |
AnnaBridge | 171:3a7713b1edbc | 9235 | |
AnnaBridge | 171:3a7713b1edbc | 9236 | /* SIM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9237 | /** Peripheral SIM base address */ |
AnnaBridge | 171:3a7713b1edbc | 9238 | #define SIM_BASE (0x40047000u) |
AnnaBridge | 171:3a7713b1edbc | 9239 | /** Peripheral SIM base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9240 | #define SIM ((SIM_Type *)SIM_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9241 | /** Array initializer of SIM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9242 | #define SIM_BASE_ADDRS { SIM_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9243 | /** Array initializer of SIM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9244 | #define SIM_BASE_PTRS { SIM } |
AnnaBridge | 171:3a7713b1edbc | 9245 | |
AnnaBridge | 171:3a7713b1edbc | 9246 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9247 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9248 | */ /* end of group SIM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9249 | |
AnnaBridge | 171:3a7713b1edbc | 9250 | |
AnnaBridge | 171:3a7713b1edbc | 9251 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9252 | -- SMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9253 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9254 | |
AnnaBridge | 171:3a7713b1edbc | 9255 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9256 | * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9257 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9258 | */ |
AnnaBridge | 171:3a7713b1edbc | 9259 | |
AnnaBridge | 171:3a7713b1edbc | 9260 | /** SMC - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9261 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9262 | __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 9263 | __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 9264 | __IO uint8_t STOPCTRL; /**< Stop Control Register, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 9265 | __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */ |
AnnaBridge | 171:3a7713b1edbc | 9266 | } SMC_Type; |
AnnaBridge | 171:3a7713b1edbc | 9267 | |
AnnaBridge | 171:3a7713b1edbc | 9268 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9269 | -- SMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9270 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9271 | |
AnnaBridge | 171:3a7713b1edbc | 9272 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9273 | * @addtogroup SMC_Register_Masks SMC Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9274 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9275 | */ |
AnnaBridge | 171:3a7713b1edbc | 9276 | |
AnnaBridge | 171:3a7713b1edbc | 9277 | /*! @name PMPROT - Power Mode Protection register */ |
AnnaBridge | 171:3a7713b1edbc | 9278 | #define SMC_PMPROT_AVLLS_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9279 | #define SMC_PMPROT_AVLLS_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9280 | #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9281 | #define SMC_PMPROT_ALLS_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9282 | #define SMC_PMPROT_ALLS_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9283 | #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9284 | #define SMC_PMPROT_AVLP_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9285 | #define SMC_PMPROT_AVLP_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9286 | #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9287 | #define SMC_PMPROT_AHSRUN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9288 | #define SMC_PMPROT_AHSRUN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9289 | #define SMC_PMPROT_AHSRUN(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9290 | |
AnnaBridge | 171:3a7713b1edbc | 9291 | /*! @name PMCTRL - Power Mode Control register */ |
AnnaBridge | 171:3a7713b1edbc | 9292 | #define SMC_PMCTRL_STOPM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 9293 | #define SMC_PMCTRL_STOPM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9294 | #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9295 | #define SMC_PMCTRL_STOPA_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9296 | #define SMC_PMCTRL_STOPA_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9297 | #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9298 | #define SMC_PMCTRL_RUNM_MASK (0x60U) |
AnnaBridge | 171:3a7713b1edbc | 9299 | #define SMC_PMCTRL_RUNM_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9300 | #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9301 | |
AnnaBridge | 171:3a7713b1edbc | 9302 | /*! @name STOPCTRL - Stop Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 9303 | #define SMC_STOPCTRL_LLSM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 9304 | #define SMC_STOPCTRL_LLSM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9305 | #define SMC_STOPCTRL_LLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9306 | #define SMC_STOPCTRL_LPOPO_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9307 | #define SMC_STOPCTRL_LPOPO_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9308 | #define SMC_STOPCTRL_LPOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LPOPO_SHIFT)) & SMC_STOPCTRL_LPOPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9309 | #define SMC_STOPCTRL_PORPO_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9310 | #define SMC_STOPCTRL_PORPO_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9311 | #define SMC_STOPCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9312 | #define SMC_STOPCTRL_PSTOPO_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 9313 | #define SMC_STOPCTRL_PSTOPO_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9314 | #define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9315 | |
AnnaBridge | 171:3a7713b1edbc | 9316 | /*! @name PMSTAT - Power Mode Status register */ |
AnnaBridge | 171:3a7713b1edbc | 9317 | #define SMC_PMSTAT_PMSTAT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 9318 | #define SMC_PMSTAT_PMSTAT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9319 | #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9320 | |
AnnaBridge | 171:3a7713b1edbc | 9321 | |
AnnaBridge | 171:3a7713b1edbc | 9322 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9323 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9324 | */ /* end of group SMC_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9325 | |
AnnaBridge | 171:3a7713b1edbc | 9326 | |
AnnaBridge | 171:3a7713b1edbc | 9327 | /* SMC - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9328 | /** Peripheral SMC base address */ |
AnnaBridge | 171:3a7713b1edbc | 9329 | #define SMC_BASE (0x4007E000u) |
AnnaBridge | 171:3a7713b1edbc | 9330 | /** Peripheral SMC base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9331 | #define SMC ((SMC_Type *)SMC_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9332 | /** Array initializer of SMC peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9333 | #define SMC_BASE_ADDRS { SMC_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9334 | /** Array initializer of SMC peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9335 | #define SMC_BASE_PTRS { SMC } |
AnnaBridge | 171:3a7713b1edbc | 9336 | |
AnnaBridge | 171:3a7713b1edbc | 9337 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9338 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9339 | */ /* end of group SMC_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9340 | |
AnnaBridge | 171:3a7713b1edbc | 9341 | |
AnnaBridge | 171:3a7713b1edbc | 9342 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9343 | -- SPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9344 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9345 | |
AnnaBridge | 171:3a7713b1edbc | 9346 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9347 | * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9348 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9349 | */ |
AnnaBridge | 171:3a7713b1edbc | 9350 | |
AnnaBridge | 171:3a7713b1edbc | 9351 | /** SPI - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9352 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9353 | __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 9354 | uint8_t RESERVED_0[4]; |
AnnaBridge | 171:3a7713b1edbc | 9355 | __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9356 | union { /* offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 9357 | __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9358 | __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9359 | }; |
AnnaBridge | 171:3a7713b1edbc | 9360 | uint8_t RESERVED_1[24]; |
AnnaBridge | 171:3a7713b1edbc | 9361 | __IO uint32_t SR; /**< Status Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 9362 | __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 9363 | union { /* offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 9364 | __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 9365 | __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 9366 | }; |
AnnaBridge | 171:3a7713b1edbc | 9367 | __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 9368 | __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 9369 | __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */ |
AnnaBridge | 171:3a7713b1edbc | 9370 | __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */ |
AnnaBridge | 171:3a7713b1edbc | 9371 | __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */ |
AnnaBridge | 171:3a7713b1edbc | 9372 | uint8_t RESERVED_2[48]; |
AnnaBridge | 171:3a7713b1edbc | 9373 | __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */ |
AnnaBridge | 171:3a7713b1edbc | 9374 | __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 9375 | __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 9376 | __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 9377 | } SPI_Type; |
AnnaBridge | 171:3a7713b1edbc | 9378 | |
AnnaBridge | 171:3a7713b1edbc | 9379 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9380 | -- SPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9381 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9382 | |
AnnaBridge | 171:3a7713b1edbc | 9383 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9384 | * @addtogroup SPI_Register_Masks SPI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9385 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9386 | */ |
AnnaBridge | 171:3a7713b1edbc | 9387 | |
AnnaBridge | 171:3a7713b1edbc | 9388 | /*! @name MCR - Module Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 9389 | #define SPI_MCR_HALT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9390 | #define SPI_MCR_HALT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9391 | #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9392 | #define SPI_MCR_SMPL_PT_MASK (0x300U) |
AnnaBridge | 171:3a7713b1edbc | 9393 | #define SPI_MCR_SMPL_PT_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9394 | #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9395 | #define SPI_MCR_CLR_RXF_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 9396 | #define SPI_MCR_CLR_RXF_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 9397 | #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9398 | #define SPI_MCR_CLR_TXF_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 9399 | #define SPI_MCR_CLR_TXF_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 9400 | #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9401 | #define SPI_MCR_DIS_RXF_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 9402 | #define SPI_MCR_DIS_RXF_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9403 | #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9404 | #define SPI_MCR_DIS_TXF_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 9405 | #define SPI_MCR_DIS_TXF_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 9406 | #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9407 | #define SPI_MCR_MDIS_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 9408 | #define SPI_MCR_MDIS_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 9409 | #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9410 | #define SPI_MCR_DOZE_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 9411 | #define SPI_MCR_DOZE_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 9412 | #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9413 | #define SPI_MCR_PCSIS_MASK (0x3F0000U) |
AnnaBridge | 171:3a7713b1edbc | 9414 | #define SPI_MCR_PCSIS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9415 | #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9416 | #define SPI_MCR_ROOE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 9417 | #define SPI_MCR_ROOE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9418 | #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9419 | #define SPI_MCR_PCSSE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9420 | #define SPI_MCR_PCSSE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9421 | #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9422 | #define SPI_MCR_MTFE_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9423 | #define SPI_MCR_MTFE_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9424 | #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9425 | #define SPI_MCR_FRZ_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9426 | #define SPI_MCR_FRZ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9427 | #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9428 | #define SPI_MCR_DCONF_MASK (0x30000000U) |
AnnaBridge | 171:3a7713b1edbc | 9429 | #define SPI_MCR_DCONF_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9430 | #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9431 | #define SPI_MCR_CONT_SCKE_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9432 | #define SPI_MCR_CONT_SCKE_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9433 | #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9434 | #define SPI_MCR_MSTR_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9435 | #define SPI_MCR_MSTR_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9436 | #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9437 | |
AnnaBridge | 171:3a7713b1edbc | 9438 | /*! @name TCR - Transfer Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 9439 | #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9440 | #define SPI_TCR_SPI_TCNT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9441 | #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9442 | |
AnnaBridge | 171:3a7713b1edbc | 9443 | /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */ |
AnnaBridge | 171:3a7713b1edbc | 9444 | #define SPI_CTAR_BR_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9445 | #define SPI_CTAR_BR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9446 | #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9447 | #define SPI_CTAR_DT_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 9448 | #define SPI_CTAR_DT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9449 | #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9450 | #define SPI_CTAR_ASC_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9451 | #define SPI_CTAR_ASC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9452 | #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9453 | #define SPI_CTAR_CSSCK_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 9454 | #define SPI_CTAR_CSSCK_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9455 | #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9456 | #define SPI_CTAR_PBR_MASK (0x30000U) |
AnnaBridge | 171:3a7713b1edbc | 9457 | #define SPI_CTAR_PBR_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9458 | #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9459 | #define SPI_CTAR_PDT_MASK (0xC0000U) |
AnnaBridge | 171:3a7713b1edbc | 9460 | #define SPI_CTAR_PDT_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 9461 | #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9462 | #define SPI_CTAR_PASC_MASK (0x300000U) |
AnnaBridge | 171:3a7713b1edbc | 9463 | #define SPI_CTAR_PASC_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9464 | #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9465 | #define SPI_CTAR_PCSSCK_MASK (0xC00000U) |
AnnaBridge | 171:3a7713b1edbc | 9466 | #define SPI_CTAR_PCSSCK_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 9467 | #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9468 | #define SPI_CTAR_LSBFE_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 9469 | #define SPI_CTAR_LSBFE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9470 | #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9471 | #define SPI_CTAR_CPHA_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9472 | #define SPI_CTAR_CPHA_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9473 | #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9474 | #define SPI_CTAR_CPOL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9475 | #define SPI_CTAR_CPOL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9476 | #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9477 | #define SPI_CTAR_FMSZ_MASK (0x78000000U) |
AnnaBridge | 171:3a7713b1edbc | 9478 | #define SPI_CTAR_FMSZ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9479 | #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9480 | #define SPI_CTAR_DBR_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9481 | #define SPI_CTAR_DBR_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9482 | #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9483 | |
AnnaBridge | 171:3a7713b1edbc | 9484 | /* The count of SPI_CTAR */ |
AnnaBridge | 171:3a7713b1edbc | 9485 | #define SPI_CTAR_COUNT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9486 | |
AnnaBridge | 171:3a7713b1edbc | 9487 | /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */ |
AnnaBridge | 171:3a7713b1edbc | 9488 | #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9489 | #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9490 | #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9491 | #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9492 | #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9493 | #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9494 | #define SPI_CTAR_SLAVE_FMSZ_MASK (0x78000000U) |
AnnaBridge | 171:3a7713b1edbc | 9495 | #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9496 | #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9497 | |
AnnaBridge | 171:3a7713b1edbc | 9498 | /* The count of SPI_CTAR_SLAVE */ |
AnnaBridge | 171:3a7713b1edbc | 9499 | #define SPI_CTAR_SLAVE_COUNT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9500 | |
AnnaBridge | 171:3a7713b1edbc | 9501 | /*! @name SR - Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 9502 | #define SPI_SR_POPNXTPTR_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9503 | #define SPI_SR_POPNXTPTR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9504 | #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9505 | #define SPI_SR_RXCTR_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 9506 | #define SPI_SR_RXCTR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9507 | #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9508 | #define SPI_SR_TXNXTPTR_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9509 | #define SPI_SR_TXNXTPTR_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9510 | #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9511 | #define SPI_SR_TXCTR_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 9512 | #define SPI_SR_TXCTR_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9513 | #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9514 | #define SPI_SR_RFDF_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9515 | #define SPI_SR_RFDF_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9516 | #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9517 | #define SPI_SR_RFOF_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 9518 | #define SPI_SR_RFOF_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 9519 | #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9520 | #define SPI_SR_TFFF_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9521 | #define SPI_SR_TFFF_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9522 | #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9523 | #define SPI_SR_TFUF_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9524 | #define SPI_SR_TFUF_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9525 | #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9526 | #define SPI_SR_EOQF_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 9527 | #define SPI_SR_EOQF_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9528 | #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9529 | #define SPI_SR_TXRXS_MASK (0x40000000U) |
AnnaBridge | 171:3a7713b1edbc | 9530 | #define SPI_SR_TXRXS_SHIFT (30U) |
AnnaBridge | 171:3a7713b1edbc | 9531 | #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9532 | #define SPI_SR_TCF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9533 | #define SPI_SR_TCF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9534 | #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9535 | |
AnnaBridge | 171:3a7713b1edbc | 9536 | /*! @name RSER - DMA/Interrupt Request Select and Enable Register */ |
AnnaBridge | 171:3a7713b1edbc | 9537 | #define SPI_RSER_RFDF_DIRS_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 9538 | #define SPI_RSER_RFDF_DIRS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9539 | #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9540 | #define SPI_RSER_RFDF_RE_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9541 | #define SPI_RSER_RFDF_RE_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9542 | #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9543 | #define SPI_RSER_RFOF_RE_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 9544 | #define SPI_RSER_RFOF_RE_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 9545 | #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9546 | #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U) |
AnnaBridge | 171:3a7713b1edbc | 9547 | #define SPI_RSER_TFFF_DIRS_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9548 | #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9549 | #define SPI_RSER_TFFF_RE_MASK (0x2000000U) |
AnnaBridge | 171:3a7713b1edbc | 9550 | #define SPI_RSER_TFFF_RE_SHIFT (25U) |
AnnaBridge | 171:3a7713b1edbc | 9551 | #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9552 | #define SPI_RSER_TFUF_RE_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9553 | #define SPI_RSER_TFUF_RE_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9554 | #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9555 | #define SPI_RSER_EOQF_RE_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 9556 | #define SPI_RSER_EOQF_RE_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9557 | #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9558 | #define SPI_RSER_TCF_RE_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9559 | #define SPI_RSER_TCF_RE_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9560 | #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9561 | |
AnnaBridge | 171:3a7713b1edbc | 9562 | /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */ |
AnnaBridge | 171:3a7713b1edbc | 9563 | #define SPI_PUSHR_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9564 | #define SPI_PUSHR_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9565 | #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9566 | #define SPI_PUSHR_PCS_MASK (0x3F0000U) |
AnnaBridge | 171:3a7713b1edbc | 9567 | #define SPI_PUSHR_PCS_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9568 | #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9569 | #define SPI_PUSHR_CTCNT_MASK (0x4000000U) |
AnnaBridge | 171:3a7713b1edbc | 9570 | #define SPI_PUSHR_CTCNT_SHIFT (26U) |
AnnaBridge | 171:3a7713b1edbc | 9571 | #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9572 | #define SPI_PUSHR_EOQ_MASK (0x8000000U) |
AnnaBridge | 171:3a7713b1edbc | 9573 | #define SPI_PUSHR_EOQ_SHIFT (27U) |
AnnaBridge | 171:3a7713b1edbc | 9574 | #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9575 | #define SPI_PUSHR_CTAS_MASK (0x70000000U) |
AnnaBridge | 171:3a7713b1edbc | 9576 | #define SPI_PUSHR_CTAS_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 9577 | #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9578 | #define SPI_PUSHR_CONT_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 9579 | #define SPI_PUSHR_CONT_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 9580 | #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9581 | |
AnnaBridge | 171:3a7713b1edbc | 9582 | /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */ |
AnnaBridge | 171:3a7713b1edbc | 9583 | #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9584 | #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9585 | #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9586 | |
AnnaBridge | 171:3a7713b1edbc | 9587 | /*! @name POPR - POP RX FIFO Register */ |
AnnaBridge | 171:3a7713b1edbc | 9588 | #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9589 | #define SPI_POPR_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9590 | #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9591 | |
AnnaBridge | 171:3a7713b1edbc | 9592 | /*! @name TXFR0 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9593 | #define SPI_TXFR0_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9594 | #define SPI_TXFR0_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9595 | #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9596 | #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9597 | #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9598 | #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9599 | |
AnnaBridge | 171:3a7713b1edbc | 9600 | /*! @name TXFR1 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9601 | #define SPI_TXFR1_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9602 | #define SPI_TXFR1_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9603 | #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9604 | #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9605 | #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9606 | #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9607 | |
AnnaBridge | 171:3a7713b1edbc | 9608 | /*! @name TXFR2 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9609 | #define SPI_TXFR2_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9610 | #define SPI_TXFR2_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9611 | #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9612 | #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9613 | #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9614 | #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9615 | |
AnnaBridge | 171:3a7713b1edbc | 9616 | /*! @name TXFR3 - Transmit FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9617 | #define SPI_TXFR3_TXDATA_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9618 | #define SPI_TXFR3_TXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9619 | #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9620 | #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9621 | #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9622 | #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9623 | |
AnnaBridge | 171:3a7713b1edbc | 9624 | /*! @name RXFR0 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9625 | #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9626 | #define SPI_RXFR0_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9627 | #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9628 | |
AnnaBridge | 171:3a7713b1edbc | 9629 | /*! @name RXFR1 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9630 | #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9631 | #define SPI_RXFR1_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9632 | #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9633 | |
AnnaBridge | 171:3a7713b1edbc | 9634 | /*! @name RXFR2 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9635 | #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9636 | #define SPI_RXFR2_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9637 | #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9638 | |
AnnaBridge | 171:3a7713b1edbc | 9639 | /*! @name RXFR3 - Receive FIFO Registers */ |
AnnaBridge | 171:3a7713b1edbc | 9640 | #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9641 | #define SPI_RXFR3_RXDATA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9642 | #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9643 | |
AnnaBridge | 171:3a7713b1edbc | 9644 | |
AnnaBridge | 171:3a7713b1edbc | 9645 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9646 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9647 | */ /* end of group SPI_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9648 | |
AnnaBridge | 171:3a7713b1edbc | 9649 | |
AnnaBridge | 171:3a7713b1edbc | 9650 | /* SPI - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9651 | /** Peripheral SPI0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 9652 | #define SPI0_BASE (0x4002C000u) |
AnnaBridge | 171:3a7713b1edbc | 9653 | /** Peripheral SPI0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9654 | #define SPI0 ((SPI_Type *)SPI0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9655 | /** Peripheral SPI1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 9656 | #define SPI1_BASE (0x4002D000u) |
AnnaBridge | 171:3a7713b1edbc | 9657 | /** Peripheral SPI1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9658 | #define SPI1 ((SPI_Type *)SPI1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9659 | /** Array initializer of SPI peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9660 | #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9661 | /** Array initializer of SPI peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9662 | #define SPI_BASE_PTRS { SPI0, SPI1 } |
AnnaBridge | 171:3a7713b1edbc | 9663 | /** Interrupt vectors for the SPI peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 9664 | #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 9665 | |
AnnaBridge | 171:3a7713b1edbc | 9666 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9667 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9668 | */ /* end of group SPI_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9669 | |
AnnaBridge | 171:3a7713b1edbc | 9670 | |
AnnaBridge | 171:3a7713b1edbc | 9671 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9672 | -- TPM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9673 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9674 | |
AnnaBridge | 171:3a7713b1edbc | 9675 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9676 | * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9677 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9678 | */ |
AnnaBridge | 171:3a7713b1edbc | 9679 | |
AnnaBridge | 171:3a7713b1edbc | 9680 | /** TPM - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9681 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9682 | __IO uint32_t SC; /**< Status and Control, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 9683 | __IO uint32_t CNT; /**< Counter, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9684 | __IO uint32_t MOD; /**< Modulo, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9685 | struct { /* offset: 0xC, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9686 | __IO uint32_t CnSC; /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9687 | __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9688 | } CONTROLS[6]; |
AnnaBridge | 171:3a7713b1edbc | 9689 | uint8_t RESERVED_0[20]; |
AnnaBridge | 171:3a7713b1edbc | 9690 | __IO uint32_t STATUS; /**< Capture and Compare Status, offset: 0x50 */ |
AnnaBridge | 171:3a7713b1edbc | 9691 | uint8_t RESERVED_1[16]; |
AnnaBridge | 171:3a7713b1edbc | 9692 | __IO uint32_t COMBINE; /**< Combine Channel Register, offset: 0x64 */ |
AnnaBridge | 171:3a7713b1edbc | 9693 | uint8_t RESERVED_2[8]; |
AnnaBridge | 171:3a7713b1edbc | 9694 | __IO uint32_t POL; /**< Channel Polarity, offset: 0x70 */ |
AnnaBridge | 171:3a7713b1edbc | 9695 | uint8_t RESERVED_3[4]; |
AnnaBridge | 171:3a7713b1edbc | 9696 | __IO uint32_t FILTER; /**< Filter Control, offset: 0x78 */ |
AnnaBridge | 171:3a7713b1edbc | 9697 | uint8_t RESERVED_4[8]; |
AnnaBridge | 171:3a7713b1edbc | 9698 | __IO uint32_t CONF; /**< Configuration, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 9699 | } TPM_Type; |
AnnaBridge | 171:3a7713b1edbc | 9700 | |
AnnaBridge | 171:3a7713b1edbc | 9701 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9702 | -- TPM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9703 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9704 | |
AnnaBridge | 171:3a7713b1edbc | 9705 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9706 | * @addtogroup TPM_Register_Masks TPM Register Masks |
AnnaBridge | 171:3a7713b1edbc | 9707 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9708 | */ |
AnnaBridge | 171:3a7713b1edbc | 9709 | |
AnnaBridge | 171:3a7713b1edbc | 9710 | /*! @name SC - Status and Control */ |
AnnaBridge | 171:3a7713b1edbc | 9711 | #define TPM_SC_PS_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 9712 | #define TPM_SC_PS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9713 | #define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9714 | #define TPM_SC_CMOD_MASK (0x18U) |
AnnaBridge | 171:3a7713b1edbc | 9715 | #define TPM_SC_CMOD_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9716 | #define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9717 | #define TPM_SC_CPWMS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9718 | #define TPM_SC_CPWMS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9719 | #define TPM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9720 | #define TPM_SC_TOIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9721 | #define TPM_SC_TOIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9722 | #define TPM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9723 | #define TPM_SC_TOF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9724 | #define TPM_SC_TOF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9725 | #define TPM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9726 | #define TPM_SC_DMA_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 9727 | #define TPM_SC_DMA_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9728 | #define TPM_SC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9729 | |
AnnaBridge | 171:3a7713b1edbc | 9730 | /*! @name CNT - Counter */ |
AnnaBridge | 171:3a7713b1edbc | 9731 | #define TPM_CNT_COUNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9732 | #define TPM_CNT_COUNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9733 | #define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9734 | |
AnnaBridge | 171:3a7713b1edbc | 9735 | /*! @name MOD - Modulo */ |
AnnaBridge | 171:3a7713b1edbc | 9736 | #define TPM_MOD_MOD_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9737 | #define TPM_MOD_MOD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9738 | #define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9739 | |
AnnaBridge | 171:3a7713b1edbc | 9740 | /*! @name CnSC - Channel (n) Status and Control */ |
AnnaBridge | 171:3a7713b1edbc | 9741 | #define TPM_CnSC_DMA_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9742 | #define TPM_CnSC_DMA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9743 | #define TPM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9744 | #define TPM_CnSC_ELSA_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9745 | #define TPM_CnSC_ELSA_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9746 | #define TPM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9747 | #define TPM_CnSC_ELSB_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9748 | #define TPM_CnSC_ELSB_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9749 | #define TPM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9750 | #define TPM_CnSC_MSA_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9751 | #define TPM_CnSC_MSA_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9752 | #define TPM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9753 | #define TPM_CnSC_MSB_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9754 | #define TPM_CnSC_MSB_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9755 | #define TPM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9756 | #define TPM_CnSC_CHIE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 9757 | #define TPM_CnSC_CHIE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9758 | #define TPM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9759 | #define TPM_CnSC_CHF_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 9760 | #define TPM_CnSC_CHF_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 9761 | #define TPM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9762 | |
AnnaBridge | 171:3a7713b1edbc | 9763 | /* The count of TPM_CnSC */ |
AnnaBridge | 171:3a7713b1edbc | 9764 | #define TPM_CnSC_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9765 | |
AnnaBridge | 171:3a7713b1edbc | 9766 | /*! @name CnV - Channel (n) Value */ |
AnnaBridge | 171:3a7713b1edbc | 9767 | #define TPM_CnV_VAL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 9768 | #define TPM_CnV_VAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9769 | #define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9770 | |
AnnaBridge | 171:3a7713b1edbc | 9771 | /* The count of TPM_CnV */ |
AnnaBridge | 171:3a7713b1edbc | 9772 | #define TPM_CnV_COUNT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9773 | |
AnnaBridge | 171:3a7713b1edbc | 9774 | /*! @name STATUS - Capture and Compare Status */ |
AnnaBridge | 171:3a7713b1edbc | 9775 | #define TPM_STATUS_CH0F_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9776 | #define TPM_STATUS_CH0F_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9777 | #define TPM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9778 | #define TPM_STATUS_CH1F_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9779 | #define TPM_STATUS_CH1F_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9780 | #define TPM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9781 | #define TPM_STATUS_CH2F_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9782 | #define TPM_STATUS_CH2F_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9783 | #define TPM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH2F_SHIFT)) & TPM_STATUS_CH2F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9784 | #define TPM_STATUS_CH3F_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9785 | #define TPM_STATUS_CH3F_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9786 | #define TPM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH3F_SHIFT)) & TPM_STATUS_CH3F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9787 | #define TPM_STATUS_CH4F_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9788 | #define TPM_STATUS_CH4F_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9789 | #define TPM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH4F_SHIFT)) & TPM_STATUS_CH4F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9790 | #define TPM_STATUS_CH5F_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9791 | #define TPM_STATUS_CH5F_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9792 | #define TPM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH5F_SHIFT)) & TPM_STATUS_CH5F_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9793 | #define TPM_STATUS_TOF_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 9794 | #define TPM_STATUS_TOF_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9795 | #define TPM_STATUS_TOF(x) (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9796 | |
AnnaBridge | 171:3a7713b1edbc | 9797 | /*! @name COMBINE - Combine Channel Register */ |
AnnaBridge | 171:3a7713b1edbc | 9798 | #define TPM_COMBINE_COMBINE0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9799 | #define TPM_COMBINE_COMBINE0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9800 | #define TPM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9801 | #define TPM_COMBINE_COMSWAP0_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9802 | #define TPM_COMBINE_COMSWAP0_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9803 | #define TPM_COMBINE_COMSWAP0(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9804 | #define TPM_COMBINE_COMBINE1_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 9805 | #define TPM_COMBINE_COMBINE1_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9806 | #define TPM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE1_SHIFT)) & TPM_COMBINE_COMBINE1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9807 | #define TPM_COMBINE_COMSWAP1_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 9808 | #define TPM_COMBINE_COMSWAP1_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 9809 | #define TPM_COMBINE_COMSWAP1(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP1_SHIFT)) & TPM_COMBINE_COMSWAP1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9810 | #define TPM_COMBINE_COMBINE2_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 9811 | #define TPM_COMBINE_COMBINE2_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9812 | #define TPM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE2_SHIFT)) & TPM_COMBINE_COMBINE2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9813 | #define TPM_COMBINE_COMSWAP2_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9814 | #define TPM_COMBINE_COMSWAP2_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9815 | #define TPM_COMBINE_COMSWAP2(x) (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP2_SHIFT)) & TPM_COMBINE_COMSWAP2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9816 | |
AnnaBridge | 171:3a7713b1edbc | 9817 | /*! @name POL - Channel Polarity */ |
AnnaBridge | 171:3a7713b1edbc | 9818 | #define TPM_POL_POL0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 9819 | #define TPM_POL_POL0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9820 | #define TPM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9821 | #define TPM_POL_POL1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 9822 | #define TPM_POL_POL1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 9823 | #define TPM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9824 | #define TPM_POL_POL2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 9825 | #define TPM_POL_POL2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 9826 | #define TPM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL2_SHIFT)) & TPM_POL_POL2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9827 | #define TPM_POL_POL3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 9828 | #define TPM_POL_POL3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 9829 | #define TPM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL3_SHIFT)) & TPM_POL_POL3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9830 | #define TPM_POL_POL4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 9831 | #define TPM_POL_POL4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9832 | #define TPM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL4_SHIFT)) & TPM_POL_POL4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9833 | #define TPM_POL_POL5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9834 | #define TPM_POL_POL5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9835 | #define TPM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL5_SHIFT)) & TPM_POL_POL5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9836 | |
AnnaBridge | 171:3a7713b1edbc | 9837 | /*! @name FILTER - Filter Control */ |
AnnaBridge | 171:3a7713b1edbc | 9838 | #define TPM_FILTER_CH0FVAL_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 9839 | #define TPM_FILTER_CH0FVAL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 9840 | #define TPM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9841 | #define TPM_FILTER_CH1FVAL_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 9842 | #define TPM_FILTER_CH1FVAL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 9843 | #define TPM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9844 | #define TPM_FILTER_CH2FVAL_MASK (0xF00U) |
AnnaBridge | 171:3a7713b1edbc | 9845 | #define TPM_FILTER_CH2FVAL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9846 | #define TPM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH2FVAL_SHIFT)) & TPM_FILTER_CH2FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9847 | #define TPM_FILTER_CH3FVAL_MASK (0xF000U) |
AnnaBridge | 171:3a7713b1edbc | 9848 | #define TPM_FILTER_CH3FVAL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 9849 | #define TPM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH3FVAL_SHIFT)) & TPM_FILTER_CH3FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9850 | #define TPM_FILTER_CH4FVAL_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 9851 | #define TPM_FILTER_CH4FVAL_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9852 | #define TPM_FILTER_CH4FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH4FVAL_SHIFT)) & TPM_FILTER_CH4FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9853 | #define TPM_FILTER_CH5FVAL_MASK (0xF00000U) |
AnnaBridge | 171:3a7713b1edbc | 9854 | #define TPM_FILTER_CH5FVAL_SHIFT (20U) |
AnnaBridge | 171:3a7713b1edbc | 9855 | #define TPM_FILTER_CH5FVAL(x) (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH5FVAL_SHIFT)) & TPM_FILTER_CH5FVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9856 | |
AnnaBridge | 171:3a7713b1edbc | 9857 | /*! @name CONF - Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 9858 | #define TPM_CONF_DOZEEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 9859 | #define TPM_CONF_DOZEEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 9860 | #define TPM_CONF_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9861 | #define TPM_CONF_DBGMODE_MASK (0xC0U) |
AnnaBridge | 171:3a7713b1edbc | 9862 | #define TPM_CONF_DBGMODE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 9863 | #define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9864 | #define TPM_CONF_GTBSYNC_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 9865 | #define TPM_CONF_GTBSYNC_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 9866 | #define TPM_CONF_GTBSYNC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9867 | #define TPM_CONF_GTBEEN_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 9868 | #define TPM_CONF_GTBEEN_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 9869 | #define TPM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9870 | #define TPM_CONF_CSOT_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 9871 | #define TPM_CONF_CSOT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 9872 | #define TPM_CONF_CSOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9873 | #define TPM_CONF_CSOO_MASK (0x20000U) |
AnnaBridge | 171:3a7713b1edbc | 9874 | #define TPM_CONF_CSOO_SHIFT (17U) |
AnnaBridge | 171:3a7713b1edbc | 9875 | #define TPM_CONF_CSOO(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9876 | #define TPM_CONF_CROT_MASK (0x40000U) |
AnnaBridge | 171:3a7713b1edbc | 9877 | #define TPM_CONF_CROT_SHIFT (18U) |
AnnaBridge | 171:3a7713b1edbc | 9878 | #define TPM_CONF_CROT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9879 | #define TPM_CONF_CPOT_MASK (0x80000U) |
AnnaBridge | 171:3a7713b1edbc | 9880 | #define TPM_CONF_CPOT_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 9881 | #define TPM_CONF_CPOT(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9882 | #define TPM_CONF_TRGPOL_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 9883 | #define TPM_CONF_TRGPOL_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 9884 | #define TPM_CONF_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9885 | #define TPM_CONF_TRGSRC_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 9886 | #define TPM_CONF_TRGSRC_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 9887 | #define TPM_CONF_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9888 | #define TPM_CONF_TRGSEL_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 9889 | #define TPM_CONF_TRGSEL_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 9890 | #define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 9891 | |
AnnaBridge | 171:3a7713b1edbc | 9892 | |
AnnaBridge | 171:3a7713b1edbc | 9893 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9894 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9895 | */ /* end of group TPM_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 9896 | |
AnnaBridge | 171:3a7713b1edbc | 9897 | |
AnnaBridge | 171:3a7713b1edbc | 9898 | /* TPM - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9899 | /** Peripheral TPM0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 9900 | #define TPM0_BASE (0x40038000u) |
AnnaBridge | 171:3a7713b1edbc | 9901 | /** Peripheral TPM0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9902 | #define TPM0 ((TPM_Type *)TPM0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9903 | /** Peripheral TPM1 base address */ |
AnnaBridge | 171:3a7713b1edbc | 9904 | #define TPM1_BASE (0x40039000u) |
AnnaBridge | 171:3a7713b1edbc | 9905 | /** Peripheral TPM1 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9906 | #define TPM1 ((TPM_Type *)TPM1_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9907 | /** Peripheral TPM2 base address */ |
AnnaBridge | 171:3a7713b1edbc | 9908 | #define TPM2_BASE (0x4003A000u) |
AnnaBridge | 171:3a7713b1edbc | 9909 | /** Peripheral TPM2 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 9910 | #define TPM2 ((TPM_Type *)TPM2_BASE) |
AnnaBridge | 171:3a7713b1edbc | 9911 | /** Array initializer of TPM peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 9912 | #define TPM_BASE_ADDRS { TPM0_BASE, TPM1_BASE, TPM2_BASE } |
AnnaBridge | 171:3a7713b1edbc | 9913 | /** Array initializer of TPM peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 9914 | #define TPM_BASE_PTRS { TPM0, TPM1, TPM2 } |
AnnaBridge | 171:3a7713b1edbc | 9915 | /** Interrupt vectors for the TPM peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 9916 | #define TPM_IRQS { TPM0_IRQn, TPM1_IRQn, TPM2_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 9917 | |
AnnaBridge | 171:3a7713b1edbc | 9918 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9919 | * @} |
AnnaBridge | 171:3a7713b1edbc | 9920 | */ /* end of group TPM_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 9921 | |
AnnaBridge | 171:3a7713b1edbc | 9922 | |
AnnaBridge | 171:3a7713b1edbc | 9923 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9924 | -- TRNG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9925 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 9926 | |
AnnaBridge | 171:3a7713b1edbc | 9927 | /*! |
AnnaBridge | 171:3a7713b1edbc | 9928 | * @addtogroup TRNG_Peripheral_Access_Layer TRNG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 9929 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 9930 | */ |
AnnaBridge | 171:3a7713b1edbc | 9931 | |
AnnaBridge | 171:3a7713b1edbc | 9932 | /** TRNG - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 9933 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 9934 | __IO uint32_t MCTL; /**< TRNG0 Miscellaneous Control Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 9935 | __IO uint32_t SCMISC; /**< TRNG0 Statistical Check Miscellaneous Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9936 | __IO uint32_t PKRRNG; /**< TRNG0 Poker Range Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 9937 | union { /* offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 9938 | __IO uint32_t PKRMAX; /**< TRNG0 Poker Maximum Limit Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 9939 | __I uint32_t PKRSQ; /**< TRNG0 Poker Square Calculation Result Register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 9940 | }; |
AnnaBridge | 171:3a7713b1edbc | 9941 | __IO uint32_t SDCTL; /**< TRNG0 Seed Control Register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 9942 | union { /* offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 9943 | __IO uint32_t SBLIM; /**< TRNG0 Sparse Bit Limit Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 9944 | __I uint32_t TOTSAM; /**< TRNG0 Total Samples Register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 9945 | }; |
AnnaBridge | 171:3a7713b1edbc | 9946 | __IO uint32_t FRQMIN; /**< TRNG0 Frequency Count Minimum Limit Register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 9947 | union { /* offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 9948 | __I uint32_t FRQCNT; /**< TRNG0 Frequency Count Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 9949 | __IO uint32_t FRQMAX; /**< TRNG0 Frequency Count Maximum Limit Register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 9950 | }; |
AnnaBridge | 171:3a7713b1edbc | 9951 | union { /* offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 9952 | __I uint32_t SCMC; /**< TRNG0 Statistical Check Monobit Count Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 9953 | __IO uint32_t SCML; /**< TRNG0 Statistical Check Monobit Limit Register, offset: 0x20 */ |
AnnaBridge | 171:3a7713b1edbc | 9954 | }; |
AnnaBridge | 171:3a7713b1edbc | 9955 | union { /* offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 9956 | __I uint32_t SCR1C; /**< TRNG0 Statistical Check Run Length 1 Count Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 9957 | __IO uint32_t SCR1L; /**< TRNG0 Statistical Check Run Length 1 Limit Register, offset: 0x24 */ |
AnnaBridge | 171:3a7713b1edbc | 9958 | }; |
AnnaBridge | 171:3a7713b1edbc | 9959 | union { /* offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 9960 | __I uint32_t SCR2C; /**< TRNG0 Statistical Check Run Length 2 Count Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 9961 | __IO uint32_t SCR2L; /**< TRNG0 Statistical Check Run Length 2 Limit Register, offset: 0x28 */ |
AnnaBridge | 171:3a7713b1edbc | 9962 | }; |
AnnaBridge | 171:3a7713b1edbc | 9963 | union { /* offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 9964 | __I uint32_t SCR3C; /**< TRNG0 Statistical Check Run Length 3 Count Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 9965 | __IO uint32_t SCR3L; /**< TRNG0 Statistical Check Run Length 3 Limit Register, offset: 0x2C */ |
AnnaBridge | 171:3a7713b1edbc | 9966 | }; |
AnnaBridge | 171:3a7713b1edbc | 9967 | union { /* offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 9968 | __I uint32_t SCR4C; /**< TRNG0 Statistical Check Run Length 4 Count Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 9969 | __IO uint32_t SCR4L; /**< TRNG0 Statistical Check Run Length 4 Limit Register, offset: 0x30 */ |
AnnaBridge | 171:3a7713b1edbc | 9970 | }; |
AnnaBridge | 171:3a7713b1edbc | 9971 | union { /* offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 9972 | __I uint32_t SCR5C; /**< TRNG0 Statistical Check Run Length 5 Count Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 9973 | __IO uint32_t SCR5L; /**< TRNG0 Statistical Check Run Length 5 Limit Register, offset: 0x34 */ |
AnnaBridge | 171:3a7713b1edbc | 9974 | }; |
AnnaBridge | 171:3a7713b1edbc | 9975 | union { /* offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 9976 | __I uint32_t SCR6PC; /**< TRNG0 Statistical Check Run Length 6+ Count Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 9977 | __IO uint32_t SCR6PL; /**< TRNG0 Statistical Check Run Length 6+ Limit Register, offset: 0x38 */ |
AnnaBridge | 171:3a7713b1edbc | 9978 | }; |
AnnaBridge | 171:3a7713b1edbc | 9979 | __I uint32_t STATUS; /**< TRNG0 Status Register, offset: 0x3C */ |
AnnaBridge | 171:3a7713b1edbc | 9980 | __I uint32_t ENT[16]; /**< RNG TRNG Entropy Read Register, array offset: 0x40, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 9981 | __I uint32_t PKRCNT10; /**< TRNG0 Statistical Check Poker Count 1 and 0 Register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 9982 | __I uint32_t PKRCNT32; /**< TRNG0 Statistical Check Poker Count 3 and 2 Register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 9983 | __I uint32_t PKRCNT54; /**< TRNG0 Statistical Check Poker Count 5 and 4 Register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 9984 | __I uint32_t PKRCNT76; /**< TRNG0 Statistical Check Poker Count 7 and 6 Register, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 9985 | __I uint32_t PKRCNT98; /**< TRNG0 Statistical Check Poker Count 9 and 8 Register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 9986 | __I uint32_t PKRCNTBA; /**< TRNG0 Statistical Check Poker Count B and A Register, offset: 0x94 */ |
AnnaBridge | 171:3a7713b1edbc | 9987 | __I uint32_t PKRCNTDC; /**< TRNG0 Statistical Check Poker Count D and C Register, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 9988 | __I uint32_t PKRCNTFE; /**< TRNG0 Statistical Check Poker Count F and E Register, offset: 0x9C */ |
AnnaBridge | 171:3a7713b1edbc | 9989 | __IO uint32_t SEC_CFG; /**< TRNG0 Security Configuration Register, offset: 0xA0 */ |
AnnaBridge | 171:3a7713b1edbc | 9990 | __IO uint32_t INT_CTRL; /**< TRNG0 Interrupt Control Register, offset: 0xA4 */ |
AnnaBridge | 171:3a7713b1edbc | 9991 | __IO uint32_t INT_MASK; /**< TRNG0 Mask Register, offset: 0xA8 */ |
AnnaBridge | 171:3a7713b1edbc | 9992 | __IO uint32_t INT_STATUS; /**< TRNG0 Interrupt Status Register, offset: 0xAC */ |
AnnaBridge | 171:3a7713b1edbc | 9993 | uint8_t RESERVED_0[64]; |
AnnaBridge | 171:3a7713b1edbc | 9994 | __I uint32_t VID1; /**< TRNG0 Version ID Register (MS), offset: 0xF0 */ |
AnnaBridge | 171:3a7713b1edbc | 9995 | __I uint32_t VID2; /**< TRNG0 Version ID Register (LS), offset: 0xF4 */ |
AnnaBridge | 171:3a7713b1edbc | 9996 | } TRNG_Type; |
AnnaBridge | 171:3a7713b1edbc | 9997 | |
AnnaBridge | 171:3a7713b1edbc | 9998 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 9999 | -- TRNG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10000 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10001 | |
AnnaBridge | 171:3a7713b1edbc | 10002 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10003 | * @addtogroup TRNG_Register_Masks TRNG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10004 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10005 | */ |
AnnaBridge | 171:3a7713b1edbc | 10006 | |
AnnaBridge | 171:3a7713b1edbc | 10007 | /*! @name MCTL - TRNG0 Miscellaneous Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10008 | #define TRNG_MCTL_SAMP_MODE_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 10009 | #define TRNG_MCTL_SAMP_MODE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10010 | #define TRNG_MCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_SAMP_MODE_SHIFT)) & TRNG_MCTL_SAMP_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10011 | #define TRNG_MCTL_OSC_DIV_MASK (0xCU) |
AnnaBridge | 171:3a7713b1edbc | 10012 | #define TRNG_MCTL_OSC_DIV_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10013 | #define TRNG_MCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_OSC_DIV_SHIFT)) & TRNG_MCTL_OSC_DIV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10014 | #define TRNG_MCTL_UNUSED_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10015 | #define TRNG_MCTL_UNUSED_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10016 | #define TRNG_MCTL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_UNUSED_SHIFT)) & TRNG_MCTL_UNUSED_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10017 | #define TRNG_MCTL_TRNG_ACC_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10018 | #define TRNG_MCTL_TRNG_ACC_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10019 | #define TRNG_MCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TRNG_ACC_SHIFT)) & TRNG_MCTL_TRNG_ACC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10020 | #define TRNG_MCTL_RST_DEF_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10021 | #define TRNG_MCTL_RST_DEF_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10022 | #define TRNG_MCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_RST_DEF_SHIFT)) & TRNG_MCTL_RST_DEF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10023 | #define TRNG_MCTL_FOR_SCLK_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10024 | #define TRNG_MCTL_FOR_SCLK_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10025 | #define TRNG_MCTL_FOR_SCLK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FOR_SCLK_SHIFT)) & TRNG_MCTL_FOR_SCLK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10026 | #define TRNG_MCTL_FCT_FAIL_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 10027 | #define TRNG_MCTL_FCT_FAIL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10028 | #define TRNG_MCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_FAIL_SHIFT)) & TRNG_MCTL_FCT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10029 | #define TRNG_MCTL_FCT_VAL_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 10030 | #define TRNG_MCTL_FCT_VAL_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 10031 | #define TRNG_MCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_FCT_VAL_SHIFT)) & TRNG_MCTL_FCT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10032 | #define TRNG_MCTL_ENT_VAL_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 10033 | #define TRNG_MCTL_ENT_VAL_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 10034 | #define TRNG_MCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ENT_VAL_SHIFT)) & TRNG_MCTL_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10035 | #define TRNG_MCTL_TST_OUT_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 10036 | #define TRNG_MCTL_TST_OUT_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 10037 | #define TRNG_MCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TST_OUT_SHIFT)) & TRNG_MCTL_TST_OUT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10038 | #define TRNG_MCTL_ERR_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 10039 | #define TRNG_MCTL_ERR_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 10040 | #define TRNG_MCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_ERR_SHIFT)) & TRNG_MCTL_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10041 | #define TRNG_MCTL_TSTOP_OK_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 10042 | #define TRNG_MCTL_TSTOP_OK_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 10043 | #define TRNG_MCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_TSTOP_OK_SHIFT)) & TRNG_MCTL_TSTOP_OK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10044 | #define TRNG_MCTL_PRGM_MASK (0x10000U) |
AnnaBridge | 171:3a7713b1edbc | 10045 | #define TRNG_MCTL_PRGM_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10046 | #define TRNG_MCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_MCTL_PRGM_SHIFT)) & TRNG_MCTL_PRGM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10047 | |
AnnaBridge | 171:3a7713b1edbc | 10048 | /*! @name SCMISC - TRNG0 Statistical Check Miscellaneous Register */ |
AnnaBridge | 171:3a7713b1edbc | 10049 | #define TRNG_SCMISC_LRUN_MAX_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10050 | #define TRNG_SCMISC_LRUN_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10051 | #define TRNG_SCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_LRUN_MAX_SHIFT)) & TRNG_SCMISC_LRUN_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10052 | #define TRNG_SCMISC_RTY_CT_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10053 | #define TRNG_SCMISC_RTY_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10054 | #define TRNG_SCMISC_RTY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMISC_RTY_CT_SHIFT)) & TRNG_SCMISC_RTY_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10055 | |
AnnaBridge | 171:3a7713b1edbc | 10056 | /*! @name PKRRNG - TRNG0 Poker Range Register */ |
AnnaBridge | 171:3a7713b1edbc | 10057 | #define TRNG_PKRRNG_PKR_RNG_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10058 | #define TRNG_PKRRNG_PKR_RNG_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10059 | #define TRNG_PKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRRNG_PKR_RNG_SHIFT)) & TRNG_PKRRNG_PKR_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10060 | |
AnnaBridge | 171:3a7713b1edbc | 10061 | /*! @name PKRMAX - TRNG0 Poker Maximum Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10062 | #define TRNG_PKRMAX_PKR_MAX_MASK (0xFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10063 | #define TRNG_PKRMAX_PKR_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10064 | #define TRNG_PKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRMAX_PKR_MAX_SHIFT)) & TRNG_PKRMAX_PKR_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10065 | |
AnnaBridge | 171:3a7713b1edbc | 10066 | /*! @name PKRSQ - TRNG0 Poker Square Calculation Result Register */ |
AnnaBridge | 171:3a7713b1edbc | 10067 | #define TRNG_PKRSQ_PKR_SQ_MASK (0xFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10068 | #define TRNG_PKRSQ_PKR_SQ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10069 | #define TRNG_PKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRSQ_PKR_SQ_SHIFT)) & TRNG_PKRSQ_PKR_SQ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10070 | |
AnnaBridge | 171:3a7713b1edbc | 10071 | /*! @name SDCTL - TRNG0 Seed Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10072 | #define TRNG_SDCTL_SAMP_SIZE_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10073 | #define TRNG_SDCTL_SAMP_SIZE_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10074 | #define TRNG_SDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_SAMP_SIZE_SHIFT)) & TRNG_SDCTL_SAMP_SIZE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10075 | #define TRNG_SDCTL_ENT_DLY_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10076 | #define TRNG_SDCTL_ENT_DLY_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10077 | #define TRNG_SDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SDCTL_ENT_DLY_SHIFT)) & TRNG_SDCTL_ENT_DLY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10078 | |
AnnaBridge | 171:3a7713b1edbc | 10079 | /*! @name SBLIM - TRNG0 Sparse Bit Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10080 | #define TRNG_SBLIM_SB_LIM_MASK (0x3FFU) |
AnnaBridge | 171:3a7713b1edbc | 10081 | #define TRNG_SBLIM_SB_LIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10082 | #define TRNG_SBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SBLIM_SB_LIM_SHIFT)) & TRNG_SBLIM_SB_LIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10083 | |
AnnaBridge | 171:3a7713b1edbc | 10084 | /*! @name TOTSAM - TRNG0 Total Samples Register */ |
AnnaBridge | 171:3a7713b1edbc | 10085 | #define TRNG_TOTSAM_TOT_SAM_MASK (0xFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10086 | #define TRNG_TOTSAM_TOT_SAM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10087 | #define TRNG_TOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_TOTSAM_TOT_SAM_SHIFT)) & TRNG_TOTSAM_TOT_SAM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10088 | |
AnnaBridge | 171:3a7713b1edbc | 10089 | /*! @name FRQMIN - TRNG0 Frequency Count Minimum Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10090 | #define TRNG_FRQMIN_FRQ_MIN_MASK (0x3FFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10091 | #define TRNG_FRQMIN_FRQ_MIN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10092 | #define TRNG_FRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMIN_FRQ_MIN_SHIFT)) & TRNG_FRQMIN_FRQ_MIN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10093 | |
AnnaBridge | 171:3a7713b1edbc | 10094 | /*! @name FRQCNT - TRNG0 Frequency Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10095 | #define TRNG_FRQCNT_FRQ_CT_MASK (0x3FFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10096 | #define TRNG_FRQCNT_FRQ_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10097 | #define TRNG_FRQCNT_FRQ_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQCNT_FRQ_CT_SHIFT)) & TRNG_FRQCNT_FRQ_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10098 | |
AnnaBridge | 171:3a7713b1edbc | 10099 | /*! @name FRQMAX - TRNG0 Frequency Count Maximum Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10100 | #define TRNG_FRQMAX_FRQ_MAX_MASK (0x3FFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10101 | #define TRNG_FRQMAX_FRQ_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10102 | #define TRNG_FRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_FRQMAX_FRQ_MAX_SHIFT)) & TRNG_FRQMAX_FRQ_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10103 | |
AnnaBridge | 171:3a7713b1edbc | 10104 | /*! @name SCMC - TRNG0 Statistical Check Monobit Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10105 | #define TRNG_SCMC_MONO_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10106 | #define TRNG_SCMC_MONO_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10107 | #define TRNG_SCMC_MONO_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCMC_MONO_CT_SHIFT)) & TRNG_SCMC_MONO_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10108 | |
AnnaBridge | 171:3a7713b1edbc | 10109 | /*! @name SCML - TRNG0 Statistical Check Monobit Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10110 | #define TRNG_SCML_MONO_MAX_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10111 | #define TRNG_SCML_MONO_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10112 | #define TRNG_SCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_MAX_SHIFT)) & TRNG_SCML_MONO_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10113 | #define TRNG_SCML_MONO_RNG_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10114 | #define TRNG_SCML_MONO_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10115 | #define TRNG_SCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCML_MONO_RNG_SHIFT)) & TRNG_SCML_MONO_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10116 | |
AnnaBridge | 171:3a7713b1edbc | 10117 | /*! @name SCR1C - TRNG0 Statistical Check Run Length 1 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10118 | #define TRNG_SCR1C_R1_0_CT_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 10119 | #define TRNG_SCR1C_R1_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10120 | #define TRNG_SCR1C_R1_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_0_CT_SHIFT)) & TRNG_SCR1C_R1_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10121 | #define TRNG_SCR1C_R1_1_CT_MASK (0x7FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10122 | #define TRNG_SCR1C_R1_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10123 | #define TRNG_SCR1C_R1_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1C_R1_1_CT_SHIFT)) & TRNG_SCR1C_R1_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10124 | |
AnnaBridge | 171:3a7713b1edbc | 10125 | /*! @name SCR1L - TRNG0 Statistical Check Run Length 1 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10126 | #define TRNG_SCR1L_RUN1_MAX_MASK (0x7FFFU) |
AnnaBridge | 171:3a7713b1edbc | 10127 | #define TRNG_SCR1L_RUN1_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10128 | #define TRNG_SCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_MAX_SHIFT)) & TRNG_SCR1L_RUN1_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10129 | #define TRNG_SCR1L_RUN1_RNG_MASK (0x7FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10130 | #define TRNG_SCR1L_RUN1_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10131 | #define TRNG_SCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR1L_RUN1_RNG_SHIFT)) & TRNG_SCR1L_RUN1_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10132 | |
AnnaBridge | 171:3a7713b1edbc | 10133 | /*! @name SCR2C - TRNG0 Statistical Check Run Length 2 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10134 | #define TRNG_SCR2C_R2_0_CT_MASK (0x3FFFU) |
AnnaBridge | 171:3a7713b1edbc | 10135 | #define TRNG_SCR2C_R2_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10136 | #define TRNG_SCR2C_R2_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_0_CT_SHIFT)) & TRNG_SCR2C_R2_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10137 | #define TRNG_SCR2C_R2_1_CT_MASK (0x3FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10138 | #define TRNG_SCR2C_R2_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10139 | #define TRNG_SCR2C_R2_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2C_R2_1_CT_SHIFT)) & TRNG_SCR2C_R2_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10140 | |
AnnaBridge | 171:3a7713b1edbc | 10141 | /*! @name SCR2L - TRNG0 Statistical Check Run Length 2 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10142 | #define TRNG_SCR2L_RUN2_MAX_MASK (0x3FFFU) |
AnnaBridge | 171:3a7713b1edbc | 10143 | #define TRNG_SCR2L_RUN2_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10144 | #define TRNG_SCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_MAX_SHIFT)) & TRNG_SCR2L_RUN2_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10145 | #define TRNG_SCR2L_RUN2_RNG_MASK (0x3FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10146 | #define TRNG_SCR2L_RUN2_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10147 | #define TRNG_SCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR2L_RUN2_RNG_SHIFT)) & TRNG_SCR2L_RUN2_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10148 | |
AnnaBridge | 171:3a7713b1edbc | 10149 | /*! @name SCR3C - TRNG0 Statistical Check Run Length 3 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10150 | #define TRNG_SCR3C_R3_0_CT_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 10151 | #define TRNG_SCR3C_R3_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10152 | #define TRNG_SCR3C_R3_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_0_CT_SHIFT)) & TRNG_SCR3C_R3_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10153 | #define TRNG_SCR3C_R3_1_CT_MASK (0x1FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10154 | #define TRNG_SCR3C_R3_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10155 | #define TRNG_SCR3C_R3_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3C_R3_1_CT_SHIFT)) & TRNG_SCR3C_R3_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10156 | |
AnnaBridge | 171:3a7713b1edbc | 10157 | /*! @name SCR3L - TRNG0 Statistical Check Run Length 3 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10158 | #define TRNG_SCR3L_RUN3_MAX_MASK (0x1FFFU) |
AnnaBridge | 171:3a7713b1edbc | 10159 | #define TRNG_SCR3L_RUN3_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10160 | #define TRNG_SCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_MAX_SHIFT)) & TRNG_SCR3L_RUN3_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10161 | #define TRNG_SCR3L_RUN3_RNG_MASK (0x1FFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10162 | #define TRNG_SCR3L_RUN3_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10163 | #define TRNG_SCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR3L_RUN3_RNG_SHIFT)) & TRNG_SCR3L_RUN3_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10164 | |
AnnaBridge | 171:3a7713b1edbc | 10165 | /*! @name SCR4C - TRNG0 Statistical Check Run Length 4 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10166 | #define TRNG_SCR4C_R4_0_CT_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10167 | #define TRNG_SCR4C_R4_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10168 | #define TRNG_SCR4C_R4_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_0_CT_SHIFT)) & TRNG_SCR4C_R4_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10169 | #define TRNG_SCR4C_R4_1_CT_MASK (0xFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10170 | #define TRNG_SCR4C_R4_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10171 | #define TRNG_SCR4C_R4_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4C_R4_1_CT_SHIFT)) & TRNG_SCR4C_R4_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10172 | |
AnnaBridge | 171:3a7713b1edbc | 10173 | /*! @name SCR4L - TRNG0 Statistical Check Run Length 4 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10174 | #define TRNG_SCR4L_RUN4_MAX_MASK (0xFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10175 | #define TRNG_SCR4L_RUN4_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10176 | #define TRNG_SCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_MAX_SHIFT)) & TRNG_SCR4L_RUN4_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10177 | #define TRNG_SCR4L_RUN4_RNG_MASK (0xFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10178 | #define TRNG_SCR4L_RUN4_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10179 | #define TRNG_SCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR4L_RUN4_RNG_SHIFT)) & TRNG_SCR4L_RUN4_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10180 | |
AnnaBridge | 171:3a7713b1edbc | 10181 | /*! @name SCR5C - TRNG0 Statistical Check Run Length 5 Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10182 | #define TRNG_SCR5C_R5_0_CT_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 10183 | #define TRNG_SCR5C_R5_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10184 | #define TRNG_SCR5C_R5_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_0_CT_SHIFT)) & TRNG_SCR5C_R5_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10185 | #define TRNG_SCR5C_R5_1_CT_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10186 | #define TRNG_SCR5C_R5_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10187 | #define TRNG_SCR5C_R5_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5C_R5_1_CT_SHIFT)) & TRNG_SCR5C_R5_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10188 | |
AnnaBridge | 171:3a7713b1edbc | 10189 | /*! @name SCR5L - TRNG0 Statistical Check Run Length 5 Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10190 | #define TRNG_SCR5L_RUN5_MAX_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 10191 | #define TRNG_SCR5L_RUN5_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10192 | #define TRNG_SCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_MAX_SHIFT)) & TRNG_SCR5L_RUN5_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10193 | #define TRNG_SCR5L_RUN5_RNG_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10194 | #define TRNG_SCR5L_RUN5_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10195 | #define TRNG_SCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR5L_RUN5_RNG_SHIFT)) & TRNG_SCR5L_RUN5_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10196 | |
AnnaBridge | 171:3a7713b1edbc | 10197 | /*! @name SCR6PC - TRNG0 Statistical Check Run Length 6+ Count Register */ |
AnnaBridge | 171:3a7713b1edbc | 10198 | #define TRNG_SCR6PC_R6P_0_CT_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 10199 | #define TRNG_SCR6PC_R6P_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10200 | #define TRNG_SCR6PC_R6P_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_0_CT_SHIFT)) & TRNG_SCR6PC_R6P_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10201 | #define TRNG_SCR6PC_R6P_1_CT_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10202 | #define TRNG_SCR6PC_R6P_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10203 | #define TRNG_SCR6PC_R6P_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PC_R6P_1_CT_SHIFT)) & TRNG_SCR6PC_R6P_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10204 | |
AnnaBridge | 171:3a7713b1edbc | 10205 | /*! @name SCR6PL - TRNG0 Statistical Check Run Length 6+ Limit Register */ |
AnnaBridge | 171:3a7713b1edbc | 10206 | #define TRNG_SCR6PL_RUN6P_MAX_MASK (0x7FFU) |
AnnaBridge | 171:3a7713b1edbc | 10207 | #define TRNG_SCR6PL_RUN6P_MAX_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10208 | #define TRNG_SCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_MAX_SHIFT)) & TRNG_SCR6PL_RUN6P_MAX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10209 | #define TRNG_SCR6PL_RUN6P_RNG_MASK (0x7FF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10210 | #define TRNG_SCR6PL_RUN6P_RNG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10211 | #define TRNG_SCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SCR6PL_RUN6P_RNG_SHIFT)) & TRNG_SCR6PL_RUN6P_RNG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10212 | |
AnnaBridge | 171:3a7713b1edbc | 10213 | /*! @name STATUS - TRNG0 Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 10214 | #define TRNG_STATUS_TF1BR0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10215 | #define TRNG_STATUS_TF1BR0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10216 | #define TRNG_STATUS_TF1BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR0_SHIFT)) & TRNG_STATUS_TF1BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10217 | #define TRNG_STATUS_TF1BR1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10218 | #define TRNG_STATUS_TF1BR1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10219 | #define TRNG_STATUS_TF1BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF1BR1_SHIFT)) & TRNG_STATUS_TF1BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10220 | #define TRNG_STATUS_TF2BR0_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10221 | #define TRNG_STATUS_TF2BR0_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10222 | #define TRNG_STATUS_TF2BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR0_SHIFT)) & TRNG_STATUS_TF2BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10223 | #define TRNG_STATUS_TF2BR1_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10224 | #define TRNG_STATUS_TF2BR1_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10225 | #define TRNG_STATUS_TF2BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF2BR1_SHIFT)) & TRNG_STATUS_TF2BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10226 | #define TRNG_STATUS_TF3BR0_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10227 | #define TRNG_STATUS_TF3BR0_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10228 | #define TRNG_STATUS_TF3BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR0_SHIFT)) & TRNG_STATUS_TF3BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10229 | #define TRNG_STATUS_TF3BR1_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10230 | #define TRNG_STATUS_TF3BR1_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10231 | #define TRNG_STATUS_TF3BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF3BR1_SHIFT)) & TRNG_STATUS_TF3BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10232 | #define TRNG_STATUS_TF4BR0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10233 | #define TRNG_STATUS_TF4BR0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10234 | #define TRNG_STATUS_TF4BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR0_SHIFT)) & TRNG_STATUS_TF4BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10235 | #define TRNG_STATUS_TF4BR1_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10236 | #define TRNG_STATUS_TF4BR1_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10237 | #define TRNG_STATUS_TF4BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF4BR1_SHIFT)) & TRNG_STATUS_TF4BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10238 | #define TRNG_STATUS_TF5BR0_MASK (0x100U) |
AnnaBridge | 171:3a7713b1edbc | 10239 | #define TRNG_STATUS_TF5BR0_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10240 | #define TRNG_STATUS_TF5BR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR0_SHIFT)) & TRNG_STATUS_TF5BR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10241 | #define TRNG_STATUS_TF5BR1_MASK (0x200U) |
AnnaBridge | 171:3a7713b1edbc | 10242 | #define TRNG_STATUS_TF5BR1_SHIFT (9U) |
AnnaBridge | 171:3a7713b1edbc | 10243 | #define TRNG_STATUS_TF5BR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF5BR1_SHIFT)) & TRNG_STATUS_TF5BR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10244 | #define TRNG_STATUS_TF6PBR0_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 10245 | #define TRNG_STATUS_TF6PBR0_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 10246 | #define TRNG_STATUS_TF6PBR0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR0_SHIFT)) & TRNG_STATUS_TF6PBR0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10247 | #define TRNG_STATUS_TF6PBR1_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 10248 | #define TRNG_STATUS_TF6PBR1_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 10249 | #define TRNG_STATUS_TF6PBR1(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TF6PBR1_SHIFT)) & TRNG_STATUS_TF6PBR1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10250 | #define TRNG_STATUS_TFSB_MASK (0x1000U) |
AnnaBridge | 171:3a7713b1edbc | 10251 | #define TRNG_STATUS_TFSB_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 10252 | #define TRNG_STATUS_TFSB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFSB_SHIFT)) & TRNG_STATUS_TFSB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10253 | #define TRNG_STATUS_TFLR_MASK (0x2000U) |
AnnaBridge | 171:3a7713b1edbc | 10254 | #define TRNG_STATUS_TFLR_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 10255 | #define TRNG_STATUS_TFLR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFLR_SHIFT)) & TRNG_STATUS_TFLR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10256 | #define TRNG_STATUS_TFP_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 10257 | #define TRNG_STATUS_TFP_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 10258 | #define TRNG_STATUS_TFP(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFP_SHIFT)) & TRNG_STATUS_TFP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10259 | #define TRNG_STATUS_TFMB_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 10260 | #define TRNG_STATUS_TFMB_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 10261 | #define TRNG_STATUS_TFMB(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_TFMB_SHIFT)) & TRNG_STATUS_TFMB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10262 | #define TRNG_STATUS_RETRY_CT_MASK (0xF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10263 | #define TRNG_STATUS_RETRY_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10264 | #define TRNG_STATUS_RETRY_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_STATUS_RETRY_CT_SHIFT)) & TRNG_STATUS_RETRY_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10265 | |
AnnaBridge | 171:3a7713b1edbc | 10266 | /*! @name ENT - RNG TRNG Entropy Read Register */ |
AnnaBridge | 171:3a7713b1edbc | 10267 | #define TRNG_ENT_ENT_MASK (0xFFFFFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10268 | #define TRNG_ENT_ENT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10269 | #define TRNG_ENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_ENT_ENT_SHIFT)) & TRNG_ENT_ENT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10270 | |
AnnaBridge | 171:3a7713b1edbc | 10271 | /* The count of TRNG_ENT */ |
AnnaBridge | 171:3a7713b1edbc | 10272 | #define TRNG_ENT_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10273 | |
AnnaBridge | 171:3a7713b1edbc | 10274 | /*! @name PKRCNT10 - TRNG0 Statistical Check Poker Count 1 and 0 Register */ |
AnnaBridge | 171:3a7713b1edbc | 10275 | #define TRNG_PKRCNT10_PKR_0_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10276 | #define TRNG_PKRCNT10_PKR_0_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10277 | #define TRNG_PKRCNT10_PKR_0_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_0_CT_SHIFT)) & TRNG_PKRCNT10_PKR_0_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10278 | #define TRNG_PKRCNT10_PKR_1_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10279 | #define TRNG_PKRCNT10_PKR_1_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10280 | #define TRNG_PKRCNT10_PKR_1_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT10_PKR_1_CT_SHIFT)) & TRNG_PKRCNT10_PKR_1_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10281 | |
AnnaBridge | 171:3a7713b1edbc | 10282 | /*! @name PKRCNT32 - TRNG0 Statistical Check Poker Count 3 and 2 Register */ |
AnnaBridge | 171:3a7713b1edbc | 10283 | #define TRNG_PKRCNT32_PKR_2_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10284 | #define TRNG_PKRCNT32_PKR_2_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10285 | #define TRNG_PKRCNT32_PKR_2_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_2_CT_SHIFT)) & TRNG_PKRCNT32_PKR_2_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10286 | #define TRNG_PKRCNT32_PKR_3_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10287 | #define TRNG_PKRCNT32_PKR_3_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10288 | #define TRNG_PKRCNT32_PKR_3_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT32_PKR_3_CT_SHIFT)) & TRNG_PKRCNT32_PKR_3_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10289 | |
AnnaBridge | 171:3a7713b1edbc | 10290 | /*! @name PKRCNT54 - TRNG0 Statistical Check Poker Count 5 and 4 Register */ |
AnnaBridge | 171:3a7713b1edbc | 10291 | #define TRNG_PKRCNT54_PKR_4_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10292 | #define TRNG_PKRCNT54_PKR_4_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10293 | #define TRNG_PKRCNT54_PKR_4_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_4_CT_SHIFT)) & TRNG_PKRCNT54_PKR_4_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10294 | #define TRNG_PKRCNT54_PKR_5_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10295 | #define TRNG_PKRCNT54_PKR_5_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10296 | #define TRNG_PKRCNT54_PKR_5_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT54_PKR_5_CT_SHIFT)) & TRNG_PKRCNT54_PKR_5_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10297 | |
AnnaBridge | 171:3a7713b1edbc | 10298 | /*! @name PKRCNT76 - TRNG0 Statistical Check Poker Count 7 and 6 Register */ |
AnnaBridge | 171:3a7713b1edbc | 10299 | #define TRNG_PKRCNT76_PKR_6_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10300 | #define TRNG_PKRCNT76_PKR_6_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10301 | #define TRNG_PKRCNT76_PKR_6_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_6_CT_SHIFT)) & TRNG_PKRCNT76_PKR_6_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10302 | #define TRNG_PKRCNT76_PKR_7_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10303 | #define TRNG_PKRCNT76_PKR_7_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10304 | #define TRNG_PKRCNT76_PKR_7_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT76_PKR_7_CT_SHIFT)) & TRNG_PKRCNT76_PKR_7_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10305 | |
AnnaBridge | 171:3a7713b1edbc | 10306 | /*! @name PKRCNT98 - TRNG0 Statistical Check Poker Count 9 and 8 Register */ |
AnnaBridge | 171:3a7713b1edbc | 10307 | #define TRNG_PKRCNT98_PKR_8_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10308 | #define TRNG_PKRCNT98_PKR_8_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10309 | #define TRNG_PKRCNT98_PKR_8_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_8_CT_SHIFT)) & TRNG_PKRCNT98_PKR_8_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10310 | #define TRNG_PKRCNT98_PKR_9_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10311 | #define TRNG_PKRCNT98_PKR_9_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10312 | #define TRNG_PKRCNT98_PKR_9_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNT98_PKR_9_CT_SHIFT)) & TRNG_PKRCNT98_PKR_9_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10313 | |
AnnaBridge | 171:3a7713b1edbc | 10314 | /*! @name PKRCNTBA - TRNG0 Statistical Check Poker Count B and A Register */ |
AnnaBridge | 171:3a7713b1edbc | 10315 | #define TRNG_PKRCNTBA_PKR_A_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10316 | #define TRNG_PKRCNTBA_PKR_A_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10317 | #define TRNG_PKRCNTBA_PKR_A_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_A_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_A_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10318 | #define TRNG_PKRCNTBA_PKR_B_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10319 | #define TRNG_PKRCNTBA_PKR_B_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10320 | #define TRNG_PKRCNTBA_PKR_B_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTBA_PKR_B_CT_SHIFT)) & TRNG_PKRCNTBA_PKR_B_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10321 | |
AnnaBridge | 171:3a7713b1edbc | 10322 | /*! @name PKRCNTDC - TRNG0 Statistical Check Poker Count D and C Register */ |
AnnaBridge | 171:3a7713b1edbc | 10323 | #define TRNG_PKRCNTDC_PKR_C_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10324 | #define TRNG_PKRCNTDC_PKR_C_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10325 | #define TRNG_PKRCNTDC_PKR_C_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_C_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_C_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10326 | #define TRNG_PKRCNTDC_PKR_D_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10327 | #define TRNG_PKRCNTDC_PKR_D_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10328 | #define TRNG_PKRCNTDC_PKR_D_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTDC_PKR_D_CT_SHIFT)) & TRNG_PKRCNTDC_PKR_D_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10329 | |
AnnaBridge | 171:3a7713b1edbc | 10330 | /*! @name PKRCNTFE - TRNG0 Statistical Check Poker Count F and E Register */ |
AnnaBridge | 171:3a7713b1edbc | 10331 | #define TRNG_PKRCNTFE_PKR_E_CT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10332 | #define TRNG_PKRCNTFE_PKR_E_CT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10333 | #define TRNG_PKRCNTFE_PKR_E_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_E_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_E_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10334 | #define TRNG_PKRCNTFE_PKR_F_CT_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10335 | #define TRNG_PKRCNTFE_PKR_F_CT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10336 | #define TRNG_PKRCNTFE_PKR_F_CT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_PKRCNTFE_PKR_F_CT_SHIFT)) & TRNG_PKRCNTFE_PKR_F_CT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10337 | |
AnnaBridge | 171:3a7713b1edbc | 10338 | /*! @name SEC_CFG - TRNG0 Security Configuration Register */ |
AnnaBridge | 171:3a7713b1edbc | 10339 | #define TRNG_SEC_CFG_SH0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10340 | #define TRNG_SEC_CFG_SH0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10341 | #define TRNG_SEC_CFG_SH0(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SH0_SHIFT)) & TRNG_SEC_CFG_SH0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10342 | #define TRNG_SEC_CFG_NO_PRGM_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10343 | #define TRNG_SEC_CFG_NO_PRGM_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10344 | #define TRNG_SEC_CFG_NO_PRGM(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_NO_PRGM_SHIFT)) & TRNG_SEC_CFG_NO_PRGM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10345 | #define TRNG_SEC_CFG_SK_VAL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10346 | #define TRNG_SEC_CFG_SK_VAL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10347 | #define TRNG_SEC_CFG_SK_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_SEC_CFG_SK_VAL_SHIFT)) & TRNG_SEC_CFG_SK_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10348 | |
AnnaBridge | 171:3a7713b1edbc | 10349 | /*! @name INT_CTRL - TRNG0 Interrupt Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 10350 | #define TRNG_INT_CTRL_HW_ERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10351 | #define TRNG_INT_CTRL_HW_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10352 | #define TRNG_INT_CTRL_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_HW_ERR_SHIFT)) & TRNG_INT_CTRL_HW_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10353 | #define TRNG_INT_CTRL_ENT_VAL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10354 | #define TRNG_INT_CTRL_ENT_VAL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10355 | #define TRNG_INT_CTRL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_ENT_VAL_SHIFT)) & TRNG_INT_CTRL_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10356 | #define TRNG_INT_CTRL_FRQ_CT_FAIL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10357 | #define TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10358 | #define TRNG_INT_CTRL_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_CTRL_FRQ_CT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10359 | #define TRNG_INT_CTRL_UNUSED_MASK (0xFFFFFFF8U) |
AnnaBridge | 171:3a7713b1edbc | 10360 | #define TRNG_INT_CTRL_UNUSED_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10361 | #define TRNG_INT_CTRL_UNUSED(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_CTRL_UNUSED_SHIFT)) & TRNG_INT_CTRL_UNUSED_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10362 | |
AnnaBridge | 171:3a7713b1edbc | 10363 | /*! @name INT_MASK - TRNG0 Mask Register */ |
AnnaBridge | 171:3a7713b1edbc | 10364 | #define TRNG_INT_MASK_HW_ERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10365 | #define TRNG_INT_MASK_HW_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10366 | #define TRNG_INT_MASK_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_HW_ERR_SHIFT)) & TRNG_INT_MASK_HW_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10367 | #define TRNG_INT_MASK_ENT_VAL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10368 | #define TRNG_INT_MASK_ENT_VAL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10369 | #define TRNG_INT_MASK_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_ENT_VAL_SHIFT)) & TRNG_INT_MASK_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10370 | #define TRNG_INT_MASK_FRQ_CT_FAIL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10371 | #define TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10372 | #define TRNG_INT_MASK_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_MASK_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_MASK_FRQ_CT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10373 | |
AnnaBridge | 171:3a7713b1edbc | 10374 | /*! @name INT_STATUS - TRNG0 Interrupt Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 10375 | #define TRNG_INT_STATUS_HW_ERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10376 | #define TRNG_INT_STATUS_HW_ERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10377 | #define TRNG_INT_STATUS_HW_ERR(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_HW_ERR_SHIFT)) & TRNG_INT_STATUS_HW_ERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10378 | #define TRNG_INT_STATUS_ENT_VAL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10379 | #define TRNG_INT_STATUS_ENT_VAL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10380 | #define TRNG_INT_STATUS_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_ENT_VAL_SHIFT)) & TRNG_INT_STATUS_ENT_VAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10381 | #define TRNG_INT_STATUS_FRQ_CT_FAIL_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10382 | #define TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10383 | #define TRNG_INT_STATUS_FRQ_CT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << TRNG_INT_STATUS_FRQ_CT_FAIL_SHIFT)) & TRNG_INT_STATUS_FRQ_CT_FAIL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10384 | |
AnnaBridge | 171:3a7713b1edbc | 10385 | /*! @name VID1 - TRNG0 Version ID Register (MS) */ |
AnnaBridge | 171:3a7713b1edbc | 10386 | #define TRNG_VID1_TRNG0_MIN_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10387 | #define TRNG_VID1_TRNG0_MIN_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10388 | #define TRNG_VID1_TRNG0_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_TRNG0_MIN_REV_SHIFT)) & TRNG_VID1_TRNG0_MIN_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10389 | #define TRNG_VID1_TRNG0_MAJ_REV_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 10390 | #define TRNG_VID1_TRNG0_MAJ_REV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10391 | #define TRNG_VID1_TRNG0_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_TRNG0_MAJ_REV_SHIFT)) & TRNG_VID1_TRNG0_MAJ_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10392 | #define TRNG_VID1_TRNG0_IP_ID_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10393 | #define TRNG_VID1_TRNG0_IP_ID_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10394 | #define TRNG_VID1_TRNG0_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID1_TRNG0_IP_ID_SHIFT)) & TRNG_VID1_TRNG0_IP_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10395 | |
AnnaBridge | 171:3a7713b1edbc | 10396 | /*! @name VID2 - TRNG0 Version ID Register (LS) */ |
AnnaBridge | 171:3a7713b1edbc | 10397 | #define TRNG_VID2_TRNG0_CONFIG_OPT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10398 | #define TRNG_VID2_TRNG0_CONFIG_OPT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10399 | #define TRNG_VID2_TRNG0_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_CONFIG_OPT_SHIFT)) & TRNG_VID2_TRNG0_CONFIG_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10400 | #define TRNG_VID2_TRNG0_ECO_REV_MASK (0xFF00U) |
AnnaBridge | 171:3a7713b1edbc | 10401 | #define TRNG_VID2_TRNG0_ECO_REV_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10402 | #define TRNG_VID2_TRNG0_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_ECO_REV_SHIFT)) & TRNG_VID2_TRNG0_ECO_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10403 | #define TRNG_VID2_TRNG0_INTG_OPT_MASK (0xFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10404 | #define TRNG_VID2_TRNG0_INTG_OPT_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10405 | #define TRNG_VID2_TRNG0_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_INTG_OPT_SHIFT)) & TRNG_VID2_TRNG0_INTG_OPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10406 | #define TRNG_VID2_TRNG0_ERA_MASK (0xFF000000U) |
AnnaBridge | 171:3a7713b1edbc | 10407 | #define TRNG_VID2_TRNG0_ERA_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 10408 | #define TRNG_VID2_TRNG0_ERA(x) (((uint32_t)(((uint32_t)(x)) << TRNG_VID2_TRNG0_ERA_SHIFT)) & TRNG_VID2_TRNG0_ERA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10409 | |
AnnaBridge | 171:3a7713b1edbc | 10410 | |
AnnaBridge | 171:3a7713b1edbc | 10411 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10412 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10413 | */ /* end of group TRNG_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10414 | |
AnnaBridge | 171:3a7713b1edbc | 10415 | |
AnnaBridge | 171:3a7713b1edbc | 10416 | /* TRNG - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10417 | /** Peripheral TRNG0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 10418 | #define TRNG0_BASE (0x40025000u) |
AnnaBridge | 171:3a7713b1edbc | 10419 | /** Peripheral TRNG0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10420 | #define TRNG0 ((TRNG_Type *)TRNG0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10421 | /** Array initializer of TRNG peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10422 | #define TRNG_BASE_ADDRS { TRNG0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10423 | /** Array initializer of TRNG peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10424 | #define TRNG_BASE_PTRS { TRNG0 } |
AnnaBridge | 171:3a7713b1edbc | 10425 | /** Interrupt vectors for the TRNG peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 10426 | #define TRNG_IRQS { TRNG0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 10427 | |
AnnaBridge | 171:3a7713b1edbc | 10428 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10429 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10430 | */ /* end of group TRNG_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10431 | |
AnnaBridge | 171:3a7713b1edbc | 10432 | |
AnnaBridge | 171:3a7713b1edbc | 10433 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10434 | -- TSI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10435 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10436 | |
AnnaBridge | 171:3a7713b1edbc | 10437 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10438 | * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10439 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10440 | */ |
AnnaBridge | 171:3a7713b1edbc | 10441 | |
AnnaBridge | 171:3a7713b1edbc | 10442 | /** TSI - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10443 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10444 | __IO uint32_t GENCS; /**< TSI General Control and Status Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10445 | __IO uint32_t DATA; /**< TSI DATA Register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10446 | __IO uint32_t TSHD; /**< TSI Threshold Register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10447 | } TSI_Type; |
AnnaBridge | 171:3a7713b1edbc | 10448 | |
AnnaBridge | 171:3a7713b1edbc | 10449 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10450 | -- TSI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10451 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10452 | |
AnnaBridge | 171:3a7713b1edbc | 10453 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10454 | * @addtogroup TSI_Register_Masks TSI Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10455 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10456 | */ |
AnnaBridge | 171:3a7713b1edbc | 10457 | |
AnnaBridge | 171:3a7713b1edbc | 10458 | /*! @name GENCS - TSI General Control and Status Register */ |
AnnaBridge | 171:3a7713b1edbc | 10459 | #define TSI_GENCS_EOSDMEO_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10460 | #define TSI_GENCS_EOSDMEO_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10461 | #define TSI_GENCS_EOSDMEO(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10462 | #define TSI_GENCS_CURSW_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10463 | #define TSI_GENCS_CURSW_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10464 | #define TSI_GENCS_CURSW(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10465 | #define TSI_GENCS_EOSF_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10466 | #define TSI_GENCS_EOSF_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10467 | #define TSI_GENCS_EOSF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10468 | #define TSI_GENCS_SCNIP_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10469 | #define TSI_GENCS_SCNIP_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10470 | #define TSI_GENCS_SCNIP(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10471 | #define TSI_GENCS_STM_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10472 | #define TSI_GENCS_STM_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10473 | #define TSI_GENCS_STM(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10474 | #define TSI_GENCS_STPE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10475 | #define TSI_GENCS_STPE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10476 | #define TSI_GENCS_STPE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10477 | #define TSI_GENCS_TSIIEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10478 | #define TSI_GENCS_TSIIEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10479 | #define TSI_GENCS_TSIIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10480 | #define TSI_GENCS_TSIEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10481 | #define TSI_GENCS_TSIEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10482 | #define TSI_GENCS_TSIEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10483 | #define TSI_GENCS_NSCN_MASK (0x1F00U) |
AnnaBridge | 171:3a7713b1edbc | 10484 | #define TSI_GENCS_NSCN_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 10485 | #define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10486 | #define TSI_GENCS_PS_MASK (0xE000U) |
AnnaBridge | 171:3a7713b1edbc | 10487 | #define TSI_GENCS_PS_SHIFT (13U) |
AnnaBridge | 171:3a7713b1edbc | 10488 | #define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10489 | #define TSI_GENCS_EXTCHRG_MASK (0x70000U) |
AnnaBridge | 171:3a7713b1edbc | 10490 | #define TSI_GENCS_EXTCHRG_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10491 | #define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10492 | #define TSI_GENCS_DVOLT_MASK (0x180000U) |
AnnaBridge | 171:3a7713b1edbc | 10493 | #define TSI_GENCS_DVOLT_SHIFT (19U) |
AnnaBridge | 171:3a7713b1edbc | 10494 | #define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10495 | #define TSI_GENCS_REFCHRG_MASK (0xE00000U) |
AnnaBridge | 171:3a7713b1edbc | 10496 | #define TSI_GENCS_REFCHRG_SHIFT (21U) |
AnnaBridge | 171:3a7713b1edbc | 10497 | #define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10498 | #define TSI_GENCS_MODE_MASK (0xF000000U) |
AnnaBridge | 171:3a7713b1edbc | 10499 | #define TSI_GENCS_MODE_SHIFT (24U) |
AnnaBridge | 171:3a7713b1edbc | 10500 | #define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10501 | #define TSI_GENCS_ESOR_MASK (0x10000000U) |
AnnaBridge | 171:3a7713b1edbc | 10502 | #define TSI_GENCS_ESOR_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 10503 | #define TSI_GENCS_ESOR(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10504 | #define TSI_GENCS_OUTRGF_MASK (0x80000000U) |
AnnaBridge | 171:3a7713b1edbc | 10505 | #define TSI_GENCS_OUTRGF_SHIFT (31U) |
AnnaBridge | 171:3a7713b1edbc | 10506 | #define TSI_GENCS_OUTRGF(x) (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10507 | |
AnnaBridge | 171:3a7713b1edbc | 10508 | /*! @name DATA - TSI DATA Register */ |
AnnaBridge | 171:3a7713b1edbc | 10509 | #define TSI_DATA_TSICNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10510 | #define TSI_DATA_TSICNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10511 | #define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10512 | #define TSI_DATA_SWTS_MASK (0x400000U) |
AnnaBridge | 171:3a7713b1edbc | 10513 | #define TSI_DATA_SWTS_SHIFT (22U) |
AnnaBridge | 171:3a7713b1edbc | 10514 | #define TSI_DATA_SWTS(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10515 | #define TSI_DATA_DMAEN_MASK (0x800000U) |
AnnaBridge | 171:3a7713b1edbc | 10516 | #define TSI_DATA_DMAEN_SHIFT (23U) |
AnnaBridge | 171:3a7713b1edbc | 10517 | #define TSI_DATA_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10518 | #define TSI_DATA_TSICH_MASK (0xF0000000U) |
AnnaBridge | 171:3a7713b1edbc | 10519 | #define TSI_DATA_TSICH_SHIFT (28U) |
AnnaBridge | 171:3a7713b1edbc | 10520 | #define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10521 | |
AnnaBridge | 171:3a7713b1edbc | 10522 | /*! @name TSHD - TSI Threshold Register */ |
AnnaBridge | 171:3a7713b1edbc | 10523 | #define TSI_TSHD_THRESL_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 10524 | #define TSI_TSHD_THRESL_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10525 | #define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10526 | #define TSI_TSHD_THRESH_MASK (0xFFFF0000U) |
AnnaBridge | 171:3a7713b1edbc | 10527 | #define TSI_TSHD_THRESH_SHIFT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10528 | #define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10529 | |
AnnaBridge | 171:3a7713b1edbc | 10530 | |
AnnaBridge | 171:3a7713b1edbc | 10531 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10532 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10533 | */ /* end of group TSI_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 10534 | |
AnnaBridge | 171:3a7713b1edbc | 10535 | |
AnnaBridge | 171:3a7713b1edbc | 10536 | /* TSI - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10537 | /** Peripheral TSI0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 10538 | #define TSI0_BASE (0x40045000u) |
AnnaBridge | 171:3a7713b1edbc | 10539 | /** Peripheral TSI0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 10540 | #define TSI0 ((TSI_Type *)TSI0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 10541 | /** Array initializer of TSI peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 10542 | #define TSI_BASE_ADDRS { TSI0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 10543 | /** Array initializer of TSI peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 10544 | #define TSI_BASE_PTRS { TSI0 } |
AnnaBridge | 171:3a7713b1edbc | 10545 | /** Interrupt vectors for the TSI peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 10546 | #define TSI_IRQS { TSI0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 10547 | |
AnnaBridge | 171:3a7713b1edbc | 10548 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10549 | * @} |
AnnaBridge | 171:3a7713b1edbc | 10550 | */ /* end of group TSI_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 10551 | |
AnnaBridge | 171:3a7713b1edbc | 10552 | |
AnnaBridge | 171:3a7713b1edbc | 10553 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10554 | -- USB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10555 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10556 | |
AnnaBridge | 171:3a7713b1edbc | 10557 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10558 | * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 10559 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10560 | */ |
AnnaBridge | 171:3a7713b1edbc | 10561 | |
AnnaBridge | 171:3a7713b1edbc | 10562 | /** USB - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 10563 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 10564 | __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 10565 | uint8_t RESERVED_0[3]; |
AnnaBridge | 171:3a7713b1edbc | 10566 | __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10567 | uint8_t RESERVED_1[3]; |
AnnaBridge | 171:3a7713b1edbc | 10568 | __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 10569 | uint8_t RESERVED_2[3]; |
AnnaBridge | 171:3a7713b1edbc | 10570 | __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 10571 | uint8_t RESERVED_3[3]; |
AnnaBridge | 171:3a7713b1edbc | 10572 | __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 10573 | uint8_t RESERVED_4[3]; |
AnnaBridge | 171:3a7713b1edbc | 10574 | __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 10575 | uint8_t RESERVED_5[3]; |
AnnaBridge | 171:3a7713b1edbc | 10576 | __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */ |
AnnaBridge | 171:3a7713b1edbc | 10577 | uint8_t RESERVED_6[3]; |
AnnaBridge | 171:3a7713b1edbc | 10578 | __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */ |
AnnaBridge | 171:3a7713b1edbc | 10579 | uint8_t RESERVED_7[99]; |
AnnaBridge | 171:3a7713b1edbc | 10580 | __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */ |
AnnaBridge | 171:3a7713b1edbc | 10581 | uint8_t RESERVED_8[3]; |
AnnaBridge | 171:3a7713b1edbc | 10582 | __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */ |
AnnaBridge | 171:3a7713b1edbc | 10583 | uint8_t RESERVED_9[3]; |
AnnaBridge | 171:3a7713b1edbc | 10584 | __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */ |
AnnaBridge | 171:3a7713b1edbc | 10585 | uint8_t RESERVED_10[3]; |
AnnaBridge | 171:3a7713b1edbc | 10586 | __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */ |
AnnaBridge | 171:3a7713b1edbc | 10587 | uint8_t RESERVED_11[3]; |
AnnaBridge | 171:3a7713b1edbc | 10588 | __I uint8_t STAT; /**< Status register, offset: 0x90 */ |
AnnaBridge | 171:3a7713b1edbc | 10589 | uint8_t RESERVED_12[3]; |
AnnaBridge | 171:3a7713b1edbc | 10590 | __IO uint8_t CTL; /**< Control register, offset: 0x94 */ |
AnnaBridge | 171:3a7713b1edbc | 10591 | uint8_t RESERVED_13[3]; |
AnnaBridge | 171:3a7713b1edbc | 10592 | __IO uint8_t ADDR; /**< Address register, offset: 0x98 */ |
AnnaBridge | 171:3a7713b1edbc | 10593 | uint8_t RESERVED_14[3]; |
AnnaBridge | 171:3a7713b1edbc | 10594 | __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */ |
AnnaBridge | 171:3a7713b1edbc | 10595 | uint8_t RESERVED_15[3]; |
AnnaBridge | 171:3a7713b1edbc | 10596 | __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */ |
AnnaBridge | 171:3a7713b1edbc | 10597 | uint8_t RESERVED_16[3]; |
AnnaBridge | 171:3a7713b1edbc | 10598 | __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */ |
AnnaBridge | 171:3a7713b1edbc | 10599 | uint8_t RESERVED_17[3]; |
AnnaBridge | 171:3a7713b1edbc | 10600 | __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */ |
AnnaBridge | 171:3a7713b1edbc | 10601 | uint8_t RESERVED_18[3]; |
AnnaBridge | 171:3a7713b1edbc | 10602 | __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */ |
AnnaBridge | 171:3a7713b1edbc | 10603 | uint8_t RESERVED_19[3]; |
AnnaBridge | 171:3a7713b1edbc | 10604 | __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */ |
AnnaBridge | 171:3a7713b1edbc | 10605 | uint8_t RESERVED_20[3]; |
AnnaBridge | 171:3a7713b1edbc | 10606 | __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */ |
AnnaBridge | 171:3a7713b1edbc | 10607 | uint8_t RESERVED_21[11]; |
AnnaBridge | 171:3a7713b1edbc | 10608 | struct { /* offset: 0xC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10609 | __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 10610 | uint8_t RESERVED_0[3]; |
AnnaBridge | 171:3a7713b1edbc | 10611 | } ENDPOINT[16]; |
AnnaBridge | 171:3a7713b1edbc | 10612 | __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */ |
AnnaBridge | 171:3a7713b1edbc | 10613 | uint8_t RESERVED_22[3]; |
AnnaBridge | 171:3a7713b1edbc | 10614 | __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */ |
AnnaBridge | 171:3a7713b1edbc | 10615 | uint8_t RESERVED_23[3]; |
AnnaBridge | 171:3a7713b1edbc | 10616 | __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */ |
AnnaBridge | 171:3a7713b1edbc | 10617 | uint8_t RESERVED_24[3]; |
AnnaBridge | 171:3a7713b1edbc | 10618 | __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */ |
AnnaBridge | 171:3a7713b1edbc | 10619 | uint8_t RESERVED_25[7]; |
AnnaBridge | 171:3a7713b1edbc | 10620 | __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */ |
AnnaBridge | 171:3a7713b1edbc | 10621 | uint8_t RESERVED_26[15]; |
AnnaBridge | 171:3a7713b1edbc | 10622 | __IO uint8_t KEEP_ALIVE_CTRL; /**< Keep Alive mode control, offset: 0x124 */ |
AnnaBridge | 171:3a7713b1edbc | 10623 | uint8_t RESERVED_27[3]; |
AnnaBridge | 171:3a7713b1edbc | 10624 | __IO uint8_t KEEP_ALIVE_WKCTRL; /**< Keep Alive mode wakeup control, offset: 0x128 */ |
AnnaBridge | 171:3a7713b1edbc | 10625 | uint8_t RESERVED_28[3]; |
AnnaBridge | 171:3a7713b1edbc | 10626 | __IO uint8_t MISCCTRL; /**< Miscellaneous Control register, offset: 0x12C */ |
AnnaBridge | 171:3a7713b1edbc | 10627 | uint8_t RESERVED_29[3]; |
AnnaBridge | 171:3a7713b1edbc | 10628 | __IO uint8_t STALL_IL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in IN direction, offset: 0x130 */ |
AnnaBridge | 171:3a7713b1edbc | 10629 | uint8_t RESERVED_30[3]; |
AnnaBridge | 171:3a7713b1edbc | 10630 | __IO uint8_t STALL_IH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in IN direction, offset: 0x134 */ |
AnnaBridge | 171:3a7713b1edbc | 10631 | uint8_t RESERVED_31[3]; |
AnnaBridge | 171:3a7713b1edbc | 10632 | __IO uint8_t STALL_OL_DIS; /**< Peripheral mode stall disable for endpoints 7 to 0 in OUT direction, offset: 0x138 */ |
AnnaBridge | 171:3a7713b1edbc | 10633 | uint8_t RESERVED_32[3]; |
AnnaBridge | 171:3a7713b1edbc | 10634 | __IO uint8_t STALL_OH_DIS; /**< Peripheral mode stall disable for endpoints 15 to 8 in OUT direction, offset: 0x13C */ |
AnnaBridge | 171:3a7713b1edbc | 10635 | uint8_t RESERVED_33[3]; |
AnnaBridge | 171:3a7713b1edbc | 10636 | __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */ |
AnnaBridge | 171:3a7713b1edbc | 10637 | uint8_t RESERVED_34[3]; |
AnnaBridge | 171:3a7713b1edbc | 10638 | __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */ |
AnnaBridge | 171:3a7713b1edbc | 10639 | uint8_t RESERVED_35[15]; |
AnnaBridge | 171:3a7713b1edbc | 10640 | __IO uint8_t CLK_RECOVER_INT_EN; /**< Clock recovery combined interrupt enable, offset: 0x154 */ |
AnnaBridge | 171:3a7713b1edbc | 10641 | uint8_t RESERVED_36[7]; |
AnnaBridge | 171:3a7713b1edbc | 10642 | __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */ |
AnnaBridge | 171:3a7713b1edbc | 10643 | } USB_Type; |
AnnaBridge | 171:3a7713b1edbc | 10644 | |
AnnaBridge | 171:3a7713b1edbc | 10645 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 10646 | -- USB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10647 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 10648 | |
AnnaBridge | 171:3a7713b1edbc | 10649 | /*! |
AnnaBridge | 171:3a7713b1edbc | 10650 | * @addtogroup USB_Register_Masks USB Register Masks |
AnnaBridge | 171:3a7713b1edbc | 10651 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 10652 | */ |
AnnaBridge | 171:3a7713b1edbc | 10653 | |
AnnaBridge | 171:3a7713b1edbc | 10654 | /*! @name PERID - Peripheral ID register */ |
AnnaBridge | 171:3a7713b1edbc | 10655 | #define USB_PERID_ID_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 10656 | #define USB_PERID_ID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10657 | #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10658 | |
AnnaBridge | 171:3a7713b1edbc | 10659 | /*! @name IDCOMP - Peripheral ID Complement register */ |
AnnaBridge | 171:3a7713b1edbc | 10660 | #define USB_IDCOMP_NID_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 10661 | #define USB_IDCOMP_NID_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10662 | #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10663 | |
AnnaBridge | 171:3a7713b1edbc | 10664 | /*! @name REV - Peripheral Revision register */ |
AnnaBridge | 171:3a7713b1edbc | 10665 | #define USB_REV_REV_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10666 | #define USB_REV_REV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10667 | #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10668 | |
AnnaBridge | 171:3a7713b1edbc | 10669 | /*! @name ADDINFO - Peripheral Additional Info register */ |
AnnaBridge | 171:3a7713b1edbc | 10670 | #define USB_ADDINFO_IEHOST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10671 | #define USB_ADDINFO_IEHOST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10672 | #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10673 | |
AnnaBridge | 171:3a7713b1edbc | 10674 | /*! @name OTGISTAT - OTG Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 10675 | #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10676 | #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10677 | #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10678 | #define USB_OTGISTAT_ONEMSEC_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10679 | #define USB_OTGISTAT_ONEMSEC_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10680 | #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10681 | |
AnnaBridge | 171:3a7713b1edbc | 10682 | /*! @name OTGICR - OTG Interrupt Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10683 | #define USB_OTGICR_LINESTATEEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10684 | #define USB_OTGICR_LINESTATEEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10685 | #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10686 | #define USB_OTGICR_ONEMSECEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10687 | #define USB_OTGICR_ONEMSECEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10688 | #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10689 | |
AnnaBridge | 171:3a7713b1edbc | 10690 | /*! @name OTGSTAT - OTG Status register */ |
AnnaBridge | 171:3a7713b1edbc | 10691 | #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10692 | #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10693 | #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10694 | #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10695 | #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10696 | #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10697 | |
AnnaBridge | 171:3a7713b1edbc | 10698 | /*! @name OTGCTL - OTG Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10699 | #define USB_OTGCTL_OTGEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10700 | #define USB_OTGCTL_OTGEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10701 | #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10702 | #define USB_OTGCTL_DMLOW_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10703 | #define USB_OTGCTL_DMLOW_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10704 | #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10705 | #define USB_OTGCTL_DPLOW_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10706 | #define USB_OTGCTL_DPLOW_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10707 | #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10708 | #define USB_OTGCTL_DPHIGH_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10709 | #define USB_OTGCTL_DPHIGH_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10710 | #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10711 | |
AnnaBridge | 171:3a7713b1edbc | 10712 | /*! @name ISTAT - Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 10713 | #define USB_ISTAT_USBRST_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10714 | #define USB_ISTAT_USBRST_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10715 | #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10716 | #define USB_ISTAT_ERROR_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10717 | #define USB_ISTAT_ERROR_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10718 | #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10719 | #define USB_ISTAT_SOFTOK_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10720 | #define USB_ISTAT_SOFTOK_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10721 | #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10722 | #define USB_ISTAT_TOKDNE_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10723 | #define USB_ISTAT_TOKDNE_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10724 | #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10725 | #define USB_ISTAT_SLEEP_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10726 | #define USB_ISTAT_SLEEP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10727 | #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10728 | #define USB_ISTAT_RESUME_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10729 | #define USB_ISTAT_RESUME_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10730 | #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10731 | #define USB_ISTAT_ATTACH_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10732 | #define USB_ISTAT_ATTACH_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10733 | #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10734 | #define USB_ISTAT_STALL_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10735 | #define USB_ISTAT_STALL_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10736 | #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10737 | |
AnnaBridge | 171:3a7713b1edbc | 10738 | /*! @name INTEN - Interrupt Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 10739 | #define USB_INTEN_USBRSTEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10740 | #define USB_INTEN_USBRSTEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10741 | #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10742 | #define USB_INTEN_ERROREN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10743 | #define USB_INTEN_ERROREN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10744 | #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10745 | #define USB_INTEN_SOFTOKEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10746 | #define USB_INTEN_SOFTOKEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10747 | #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10748 | #define USB_INTEN_TOKDNEEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10749 | #define USB_INTEN_TOKDNEEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10750 | #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10751 | #define USB_INTEN_SLEEPEN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10752 | #define USB_INTEN_SLEEPEN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10753 | #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10754 | #define USB_INTEN_RESUMEEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10755 | #define USB_INTEN_RESUMEEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10756 | #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10757 | #define USB_INTEN_ATTACHEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10758 | #define USB_INTEN_ATTACHEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10759 | #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10760 | #define USB_INTEN_STALLEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10761 | #define USB_INTEN_STALLEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10762 | #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10763 | |
AnnaBridge | 171:3a7713b1edbc | 10764 | /*! @name ERRSTAT - Error Interrupt Status register */ |
AnnaBridge | 171:3a7713b1edbc | 10765 | #define USB_ERRSTAT_PIDERR_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10766 | #define USB_ERRSTAT_PIDERR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10767 | #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10768 | #define USB_ERRSTAT_CRC5EOF_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10769 | #define USB_ERRSTAT_CRC5EOF_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10770 | #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10771 | #define USB_ERRSTAT_CRC16_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10772 | #define USB_ERRSTAT_CRC16_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10773 | #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10774 | #define USB_ERRSTAT_DFN8_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10775 | #define USB_ERRSTAT_DFN8_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10776 | #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10777 | #define USB_ERRSTAT_BTOERR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10778 | #define USB_ERRSTAT_BTOERR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10779 | #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10780 | #define USB_ERRSTAT_DMAERR_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10781 | #define USB_ERRSTAT_DMAERR_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10782 | #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10783 | #define USB_ERRSTAT_OWNERR_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10784 | #define USB_ERRSTAT_OWNERR_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10785 | #define USB_ERRSTAT_OWNERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_OWNERR_SHIFT)) & USB_ERRSTAT_OWNERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10786 | #define USB_ERRSTAT_BTSERR_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10787 | #define USB_ERRSTAT_BTSERR_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10788 | #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10789 | |
AnnaBridge | 171:3a7713b1edbc | 10790 | /*! @name ERREN - Error Interrupt Enable register */ |
AnnaBridge | 171:3a7713b1edbc | 10791 | #define USB_ERREN_PIDERREN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10792 | #define USB_ERREN_PIDERREN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10793 | #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10794 | #define USB_ERREN_CRC5EOFEN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10795 | #define USB_ERREN_CRC5EOFEN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10796 | #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10797 | #define USB_ERREN_CRC16EN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10798 | #define USB_ERREN_CRC16EN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10799 | #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10800 | #define USB_ERREN_DFN8EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10801 | #define USB_ERREN_DFN8EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10802 | #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10803 | #define USB_ERREN_BTOERREN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10804 | #define USB_ERREN_BTOERREN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10805 | #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10806 | #define USB_ERREN_DMAERREN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10807 | #define USB_ERREN_DMAERREN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10808 | #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10809 | #define USB_ERREN_OWNERREN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10810 | #define USB_ERREN_OWNERREN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10811 | #define USB_ERREN_OWNERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_OWNERREN_SHIFT)) & USB_ERREN_OWNERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10812 | #define USB_ERREN_BTSERREN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10813 | #define USB_ERREN_BTSERREN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10814 | #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10815 | |
AnnaBridge | 171:3a7713b1edbc | 10816 | /*! @name STAT - Status register */ |
AnnaBridge | 171:3a7713b1edbc | 10817 | #define USB_STAT_ODD_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10818 | #define USB_STAT_ODD_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10819 | #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10820 | #define USB_STAT_TX_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10821 | #define USB_STAT_TX_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10822 | #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10823 | #define USB_STAT_ENDP_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 10824 | #define USB_STAT_ENDP_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10825 | #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10826 | |
AnnaBridge | 171:3a7713b1edbc | 10827 | /*! @name CTL - Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10828 | #define USB_CTL_USBENSOFEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10829 | #define USB_CTL_USBENSOFEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10830 | #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10831 | #define USB_CTL_ODDRST_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10832 | #define USB_CTL_ODDRST_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10833 | #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10834 | #define USB_CTL_RESUME_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10835 | #define USB_CTL_RESUME_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10836 | #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10837 | #define USB_CTL_HOSTMODEEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10838 | #define USB_CTL_HOSTMODEEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10839 | #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10840 | #define USB_CTL_RESET_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10841 | #define USB_CTL_RESET_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10842 | #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10843 | #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10844 | #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10845 | #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10846 | #define USB_CTL_SE0_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10847 | #define USB_CTL_SE0_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10848 | #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10849 | #define USB_CTL_JSTATE_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10850 | #define USB_CTL_JSTATE_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10851 | #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10852 | |
AnnaBridge | 171:3a7713b1edbc | 10853 | /*! @name ADDR - Address register */ |
AnnaBridge | 171:3a7713b1edbc | 10854 | #define USB_ADDR_ADDR_MASK (0x7FU) |
AnnaBridge | 171:3a7713b1edbc | 10855 | #define USB_ADDR_ADDR_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10856 | #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10857 | #define USB_ADDR_LSEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10858 | #define USB_ADDR_LSEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10859 | #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10860 | |
AnnaBridge | 171:3a7713b1edbc | 10861 | /*! @name BDTPAGE1 - BDT Page register 1 */ |
AnnaBridge | 171:3a7713b1edbc | 10862 | #define USB_BDTPAGE1_BDTBA_MASK (0xFEU) |
AnnaBridge | 171:3a7713b1edbc | 10863 | #define USB_BDTPAGE1_BDTBA_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10864 | #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10865 | |
AnnaBridge | 171:3a7713b1edbc | 10866 | /*! @name FRMNUML - Frame Number register Low */ |
AnnaBridge | 171:3a7713b1edbc | 10867 | #define USB_FRMNUML_FRM_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10868 | #define USB_FRMNUML_FRM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10869 | #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10870 | |
AnnaBridge | 171:3a7713b1edbc | 10871 | /*! @name FRMNUMH - Frame Number register High */ |
AnnaBridge | 171:3a7713b1edbc | 10872 | #define USB_FRMNUMH_FRM_MASK (0x7U) |
AnnaBridge | 171:3a7713b1edbc | 10873 | #define USB_FRMNUMH_FRM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10874 | #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10875 | |
AnnaBridge | 171:3a7713b1edbc | 10876 | /*! @name TOKEN - Token register */ |
AnnaBridge | 171:3a7713b1edbc | 10877 | #define USB_TOKEN_TOKENENDPT_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 10878 | #define USB_TOKEN_TOKENENDPT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10879 | #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10880 | #define USB_TOKEN_TOKENPID_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 10881 | #define USB_TOKEN_TOKENPID_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10882 | #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10883 | |
AnnaBridge | 171:3a7713b1edbc | 10884 | /*! @name SOFTHLD - SOF Threshold register */ |
AnnaBridge | 171:3a7713b1edbc | 10885 | #define USB_SOFTHLD_CNT_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10886 | #define USB_SOFTHLD_CNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10887 | #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10888 | |
AnnaBridge | 171:3a7713b1edbc | 10889 | /*! @name BDTPAGE2 - BDT Page Register 2 */ |
AnnaBridge | 171:3a7713b1edbc | 10890 | #define USB_BDTPAGE2_BDTBA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10891 | #define USB_BDTPAGE2_BDTBA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10892 | #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10893 | |
AnnaBridge | 171:3a7713b1edbc | 10894 | /*! @name BDTPAGE3 - BDT Page Register 3 */ |
AnnaBridge | 171:3a7713b1edbc | 10895 | #define USB_BDTPAGE3_BDTBA_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10896 | #define USB_BDTPAGE3_BDTBA_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10897 | #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10898 | |
AnnaBridge | 171:3a7713b1edbc | 10899 | /*! @name ENDPT - Endpoint Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10900 | #define USB_ENDPT_EPHSHK_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10901 | #define USB_ENDPT_EPHSHK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10902 | #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10903 | #define USB_ENDPT_EPSTALL_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10904 | #define USB_ENDPT_EPSTALL_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10905 | #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10906 | #define USB_ENDPT_EPTXEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10907 | #define USB_ENDPT_EPTXEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10908 | #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10909 | #define USB_ENDPT_EPRXEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10910 | #define USB_ENDPT_EPRXEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10911 | #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10912 | #define USB_ENDPT_EPCTLDIS_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10913 | #define USB_ENDPT_EPCTLDIS_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10914 | #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10915 | #define USB_ENDPT_RETRYDIS_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10916 | #define USB_ENDPT_RETRYDIS_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10917 | #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10918 | #define USB_ENDPT_HOSTWOHUB_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10919 | #define USB_ENDPT_HOSTWOHUB_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10920 | #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10921 | |
AnnaBridge | 171:3a7713b1edbc | 10922 | /* The count of USB_ENDPT */ |
AnnaBridge | 171:3a7713b1edbc | 10923 | #define USB_ENDPT_COUNT (16U) |
AnnaBridge | 171:3a7713b1edbc | 10924 | |
AnnaBridge | 171:3a7713b1edbc | 10925 | /*! @name USBCTRL - USB Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10926 | #define USB_USBCTRL_UARTSEL_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10927 | #define USB_USBCTRL_UARTSEL_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10928 | #define USB_USBCTRL_UARTSEL(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTSEL_SHIFT)) & USB_USBCTRL_UARTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10929 | #define USB_USBCTRL_UARTCHLS_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10930 | #define USB_USBCTRL_UARTCHLS_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10931 | #define USB_USBCTRL_UARTCHLS(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_UARTCHLS_SHIFT)) & USB_USBCTRL_UARTCHLS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10932 | #define USB_USBCTRL_PDE_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10933 | #define USB_USBCTRL_PDE_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10934 | #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10935 | #define USB_USBCTRL_SUSP_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10936 | #define USB_USBCTRL_SUSP_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10937 | #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10938 | |
AnnaBridge | 171:3a7713b1edbc | 10939 | /*! @name OBSERVE - USB OTG Observe register */ |
AnnaBridge | 171:3a7713b1edbc | 10940 | #define USB_OBSERVE_DMPD_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10941 | #define USB_OBSERVE_DMPD_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10942 | #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10943 | #define USB_OBSERVE_DPPD_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 10944 | #define USB_OBSERVE_DPPD_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 10945 | #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10946 | #define USB_OBSERVE_DPPU_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10947 | #define USB_OBSERVE_DPPU_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10948 | #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10949 | |
AnnaBridge | 171:3a7713b1edbc | 10950 | /*! @name CONTROL - USB OTG Control register */ |
AnnaBridge | 171:3a7713b1edbc | 10951 | #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10952 | #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10953 | #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10954 | |
AnnaBridge | 171:3a7713b1edbc | 10955 | /*! @name USBTRC0 - USB Transceiver Control register 0 */ |
AnnaBridge | 171:3a7713b1edbc | 10956 | #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10957 | #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10958 | #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10959 | #define USB_USBTRC0_SYNC_DET_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10960 | #define USB_USBTRC0_SYNC_DET_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10961 | #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10962 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 10963 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 10964 | #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10965 | #define USB_USBTRC0_VREDG_DET_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10966 | #define USB_USBTRC0_VREDG_DET_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10967 | #define USB_USBTRC0_VREDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VREDG_DET_SHIFT)) & USB_USBTRC0_VREDG_DET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10968 | #define USB_USBTRC0_VFEDG_DET_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10969 | #define USB_USBTRC0_VFEDG_DET_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10970 | #define USB_USBTRC0_VFEDG_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_VFEDG_DET_SHIFT)) & USB_USBTRC0_VFEDG_DET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10971 | #define USB_USBTRC0_USBRESMEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 10972 | #define USB_USBTRC0_USBRESMEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 10973 | #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10974 | #define USB_USBTRC0_USBRESET_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10975 | #define USB_USBTRC0_USBRESET_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10976 | #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10977 | |
AnnaBridge | 171:3a7713b1edbc | 10978 | /*! @name USBFRMADJUST - Frame Adjust Register */ |
AnnaBridge | 171:3a7713b1edbc | 10979 | #define USB_USBFRMADJUST_ADJ_MASK (0xFFU) |
AnnaBridge | 171:3a7713b1edbc | 10980 | #define USB_USBFRMADJUST_ADJ_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10981 | #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10982 | |
AnnaBridge | 171:3a7713b1edbc | 10983 | /*! @name KEEP_ALIVE_CTRL - Keep Alive mode control */ |
AnnaBridge | 171:3a7713b1edbc | 10984 | #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 10985 | #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 10986 | #define USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_KEEP_ALIVE_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10987 | #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 10988 | #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 10989 | #define USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_OWN_OVERRD_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10990 | #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 10991 | #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 10992 | #define USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_REQ_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10993 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 10994 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 10995 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10996 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 10997 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 10998 | #define USB_KEEP_ALIVE_CTRL_WAKE_INT_STS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_SHIFT)) & USB_KEEP_ALIVE_CTRL_WAKE_INT_STS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 10999 | |
AnnaBridge | 171:3a7713b1edbc | 11000 | /*! @name KEEP_ALIVE_WKCTRL - Keep Alive mode wakeup control */ |
AnnaBridge | 171:3a7713b1edbc | 11001 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK (0xFU) |
AnnaBridge | 171:3a7713b1edbc | 11002 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11003 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ON_THIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11004 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK (0xF0U) |
AnnaBridge | 171:3a7713b1edbc | 11005 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11006 | #define USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_SHIFT)) & USB_KEEP_ALIVE_WKCTRL_WAKE_ENDPT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11007 | |
AnnaBridge | 171:3a7713b1edbc | 11008 | /*! @name MISCCTRL - Miscellaneous Control register */ |
AnnaBridge | 171:3a7713b1edbc | 11009 | #define USB_MISCCTRL_SOFDYNTHLD_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11010 | #define USB_MISCCTRL_SOFDYNTHLD_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11011 | #define USB_MISCCTRL_SOFDYNTHLD(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFDYNTHLD_SHIFT)) & USB_MISCCTRL_SOFDYNTHLD_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11012 | #define USB_MISCCTRL_SOFBUSSET_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11013 | #define USB_MISCCTRL_SOFBUSSET_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11014 | #define USB_MISCCTRL_SOFBUSSET(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_SOFBUSSET_SHIFT)) & USB_MISCCTRL_SOFBUSSET_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11015 | #define USB_MISCCTRL_OWNERRISODIS_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11016 | #define USB_MISCCTRL_OWNERRISODIS_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11017 | #define USB_MISCCTRL_OWNERRISODIS(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_OWNERRISODIS_SHIFT)) & USB_MISCCTRL_OWNERRISODIS_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11018 | #define USB_MISCCTRL_VREDG_EN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11019 | #define USB_MISCCTRL_VREDG_EN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11020 | #define USB_MISCCTRL_VREDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VREDG_EN_SHIFT)) & USB_MISCCTRL_VREDG_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11021 | #define USB_MISCCTRL_VFEDG_EN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11022 | #define USB_MISCCTRL_VFEDG_EN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11023 | #define USB_MISCCTRL_VFEDG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_VFEDG_EN_SHIFT)) & USB_MISCCTRL_VFEDG_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11024 | #define USB_MISCCTRL_STL_ADJ_EN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11025 | #define USB_MISCCTRL_STL_ADJ_EN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11026 | #define USB_MISCCTRL_STL_ADJ_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_MISCCTRL_STL_ADJ_EN_SHIFT)) & USB_MISCCTRL_STL_ADJ_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11027 | |
AnnaBridge | 171:3a7713b1edbc | 11028 | /*! @name STALL_IL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in IN direction */ |
AnnaBridge | 171:3a7713b1edbc | 11029 | #define USB_STALL_IL_DIS_STALL_I_DIS0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11030 | #define USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11031 | #define USB_STALL_IL_DIS_STALL_I_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS0_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11032 | #define USB_STALL_IL_DIS_STALL_I_DIS1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11033 | #define USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11034 | #define USB_STALL_IL_DIS_STALL_I_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS1_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11035 | #define USB_STALL_IL_DIS_STALL_I_DIS2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11036 | #define USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11037 | #define USB_STALL_IL_DIS_STALL_I_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS2_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11038 | #define USB_STALL_IL_DIS_STALL_I_DIS3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11039 | #define USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11040 | #define USB_STALL_IL_DIS_STALL_I_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS3_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11041 | #define USB_STALL_IL_DIS_STALL_I_DIS4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11042 | #define USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11043 | #define USB_STALL_IL_DIS_STALL_I_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS4_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11044 | #define USB_STALL_IL_DIS_STALL_I_DIS5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11045 | #define USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11046 | #define USB_STALL_IL_DIS_STALL_I_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS5_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11047 | #define USB_STALL_IL_DIS_STALL_I_DIS6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11048 | #define USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11049 | #define USB_STALL_IL_DIS_STALL_I_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS6_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11050 | #define USB_STALL_IL_DIS_STALL_I_DIS7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11051 | #define USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11052 | #define USB_STALL_IL_DIS_STALL_I_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IL_DIS_STALL_I_DIS7_SHIFT)) & USB_STALL_IL_DIS_STALL_I_DIS7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11053 | |
AnnaBridge | 171:3a7713b1edbc | 11054 | /*! @name STALL_IH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in IN direction */ |
AnnaBridge | 171:3a7713b1edbc | 11055 | #define USB_STALL_IH_DIS_STALL_I_DIS8_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11056 | #define USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11057 | #define USB_STALL_IH_DIS_STALL_I_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS8_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11058 | #define USB_STALL_IH_DIS_STALL_I_DIS9_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11059 | #define USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11060 | #define USB_STALL_IH_DIS_STALL_I_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS9_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11061 | #define USB_STALL_IH_DIS_STALL_I_DIS10_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11062 | #define USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11063 | #define USB_STALL_IH_DIS_STALL_I_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS10_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11064 | #define USB_STALL_IH_DIS_STALL_I_DIS11_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11065 | #define USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11066 | #define USB_STALL_IH_DIS_STALL_I_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS11_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11067 | #define USB_STALL_IH_DIS_STALL_I_DIS12_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11068 | #define USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11069 | #define USB_STALL_IH_DIS_STALL_I_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS12_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11070 | #define USB_STALL_IH_DIS_STALL_I_DIS13_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11071 | #define USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11072 | #define USB_STALL_IH_DIS_STALL_I_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS13_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11073 | #define USB_STALL_IH_DIS_STALL_I_DIS14_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11074 | #define USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11075 | #define USB_STALL_IH_DIS_STALL_I_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS14_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11076 | #define USB_STALL_IH_DIS_STALL_I_DIS15_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11077 | #define USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11078 | #define USB_STALL_IH_DIS_STALL_I_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_IH_DIS_STALL_I_DIS15_SHIFT)) & USB_STALL_IH_DIS_STALL_I_DIS15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11079 | |
AnnaBridge | 171:3a7713b1edbc | 11080 | /*! @name STALL_OL_DIS - Peripheral mode stall disable for endpoints 7 to 0 in OUT direction */ |
AnnaBridge | 171:3a7713b1edbc | 11081 | #define USB_STALL_OL_DIS_STALL_O_DIS0_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11082 | #define USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11083 | #define USB_STALL_OL_DIS_STALL_O_DIS0(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS0_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS0_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11084 | #define USB_STALL_OL_DIS_STALL_O_DIS1_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11085 | #define USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11086 | #define USB_STALL_OL_DIS_STALL_O_DIS1(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS1_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS1_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11087 | #define USB_STALL_OL_DIS_STALL_O_DIS2_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11088 | #define USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11089 | #define USB_STALL_OL_DIS_STALL_O_DIS2(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS2_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS2_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11090 | #define USB_STALL_OL_DIS_STALL_O_DIS3_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11091 | #define USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11092 | #define USB_STALL_OL_DIS_STALL_O_DIS3(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS3_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS3_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11093 | #define USB_STALL_OL_DIS_STALL_O_DIS4_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11094 | #define USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11095 | #define USB_STALL_OL_DIS_STALL_O_DIS4(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS4_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS4_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11096 | #define USB_STALL_OL_DIS_STALL_O_DIS5_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11097 | #define USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11098 | #define USB_STALL_OL_DIS_STALL_O_DIS5(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS5_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS5_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11099 | #define USB_STALL_OL_DIS_STALL_O_DIS6_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11100 | #define USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11101 | #define USB_STALL_OL_DIS_STALL_O_DIS6(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS6_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS6_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11102 | #define USB_STALL_OL_DIS_STALL_O_DIS7_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11103 | #define USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11104 | #define USB_STALL_OL_DIS_STALL_O_DIS7(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OL_DIS_STALL_O_DIS7_SHIFT)) & USB_STALL_OL_DIS_STALL_O_DIS7_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11105 | |
AnnaBridge | 171:3a7713b1edbc | 11106 | /*! @name STALL_OH_DIS - Peripheral mode stall disable for endpoints 15 to 8 in OUT direction */ |
AnnaBridge | 171:3a7713b1edbc | 11107 | #define USB_STALL_OH_DIS_STALL_O_DIS8_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11108 | #define USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11109 | #define USB_STALL_OH_DIS_STALL_O_DIS8(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS8_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS8_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11110 | #define USB_STALL_OH_DIS_STALL_O_DIS9_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11111 | #define USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11112 | #define USB_STALL_OH_DIS_STALL_O_DIS9(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS9_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS9_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11113 | #define USB_STALL_OH_DIS_STALL_O_DIS10_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11114 | #define USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11115 | #define USB_STALL_OH_DIS_STALL_O_DIS10(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS10_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS10_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11116 | #define USB_STALL_OH_DIS_STALL_O_DIS11_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11117 | #define USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11118 | #define USB_STALL_OH_DIS_STALL_O_DIS11(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS11_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS11_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11119 | #define USB_STALL_OH_DIS_STALL_O_DIS12_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11120 | #define USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11121 | #define USB_STALL_OH_DIS_STALL_O_DIS12(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS12_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS12_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11122 | #define USB_STALL_OH_DIS_STALL_O_DIS13_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11123 | #define USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11124 | #define USB_STALL_OH_DIS_STALL_O_DIS13(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS13_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS13_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11125 | #define USB_STALL_OH_DIS_STALL_O_DIS14_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11126 | #define USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11127 | #define USB_STALL_OH_DIS_STALL_O_DIS14(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS14_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS14_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11128 | #define USB_STALL_OH_DIS_STALL_O_DIS15_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11129 | #define USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11130 | #define USB_STALL_OH_DIS_STALL_O_DIS15(x) (((uint8_t)(((uint8_t)(x)) << USB_STALL_OH_DIS_STALL_O_DIS15_SHIFT)) & USB_STALL_OH_DIS_STALL_O_DIS15_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11131 | |
AnnaBridge | 171:3a7713b1edbc | 11132 | /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */ |
AnnaBridge | 171:3a7713b1edbc | 11133 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11134 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11135 | #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11136 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11137 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11138 | #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11139 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11140 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11141 | #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11142 | |
AnnaBridge | 171:3a7713b1edbc | 11143 | /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */ |
AnnaBridge | 171:3a7713b1edbc | 11144 | #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11145 | #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11146 | #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11147 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11148 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11149 | #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11150 | |
AnnaBridge | 171:3a7713b1edbc | 11151 | /*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 11152 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11153 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11154 | #define USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USB_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11155 | |
AnnaBridge | 171:3a7713b1edbc | 11156 | /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */ |
AnnaBridge | 171:3a7713b1edbc | 11157 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11158 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11159 | #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11160 | |
AnnaBridge | 171:3a7713b1edbc | 11161 | |
AnnaBridge | 171:3a7713b1edbc | 11162 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11163 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11164 | */ /* end of group USB_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11165 | |
AnnaBridge | 171:3a7713b1edbc | 11166 | |
AnnaBridge | 171:3a7713b1edbc | 11167 | /* USB - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11168 | /** Peripheral USB0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 11169 | #define USB0_BASE (0x40072000u) |
AnnaBridge | 171:3a7713b1edbc | 11170 | /** Peripheral USB0 base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11171 | #define USB0 ((USB_Type *)USB0_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11172 | /** Array initializer of USB peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11173 | #define USB_BASE_ADDRS { USB0_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11174 | /** Array initializer of USB peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11175 | #define USB_BASE_PTRS { USB0 } |
AnnaBridge | 171:3a7713b1edbc | 11176 | /** Interrupt vectors for the USB peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 11177 | #define USB_IRQS { USB0_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 11178 | |
AnnaBridge | 171:3a7713b1edbc | 11179 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11180 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11181 | */ /* end of group USB_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11182 | |
AnnaBridge | 171:3a7713b1edbc | 11183 | |
AnnaBridge | 171:3a7713b1edbc | 11184 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11185 | -- VREF Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11186 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11187 | |
AnnaBridge | 171:3a7713b1edbc | 11188 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11189 | * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11190 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11191 | */ |
AnnaBridge | 171:3a7713b1edbc | 11192 | |
AnnaBridge | 171:3a7713b1edbc | 11193 | /** VREF - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11194 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11195 | __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 11196 | __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */ |
AnnaBridge | 171:3a7713b1edbc | 11197 | } VREF_Type; |
AnnaBridge | 171:3a7713b1edbc | 11198 | |
AnnaBridge | 171:3a7713b1edbc | 11199 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11200 | -- VREF Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11201 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11202 | |
AnnaBridge | 171:3a7713b1edbc | 11203 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11204 | * @addtogroup VREF_Register_Masks VREF Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11205 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11206 | */ |
AnnaBridge | 171:3a7713b1edbc | 11207 | |
AnnaBridge | 171:3a7713b1edbc | 11208 | /*! @name TRM - VREF Trim Register */ |
AnnaBridge | 171:3a7713b1edbc | 11209 | #define VREF_TRM_TRIM_MASK (0x3FU) |
AnnaBridge | 171:3a7713b1edbc | 11210 | #define VREF_TRM_TRIM_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11211 | #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11212 | #define VREF_TRM_CHOPEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11213 | #define VREF_TRM_CHOPEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11214 | #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11215 | |
AnnaBridge | 171:3a7713b1edbc | 11216 | /*! @name SC - VREF Status and Control Register */ |
AnnaBridge | 171:3a7713b1edbc | 11217 | #define VREF_SC_MODE_LV_MASK (0x3U) |
AnnaBridge | 171:3a7713b1edbc | 11218 | #define VREF_SC_MODE_LV_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11219 | #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11220 | #define VREF_SC_VREFST_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11221 | #define VREF_SC_VREFST_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11222 | #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11223 | #define VREF_SC_ICOMPEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11224 | #define VREF_SC_ICOMPEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11225 | #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11226 | #define VREF_SC_REGEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11227 | #define VREF_SC_REGEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11228 | #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11229 | #define VREF_SC_VREFEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11230 | #define VREF_SC_VREFEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11231 | #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11232 | |
AnnaBridge | 171:3a7713b1edbc | 11233 | |
AnnaBridge | 171:3a7713b1edbc | 11234 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11235 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11236 | */ /* end of group VREF_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11237 | |
AnnaBridge | 171:3a7713b1edbc | 11238 | |
AnnaBridge | 171:3a7713b1edbc | 11239 | /* VREF - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11240 | /** Peripheral VREF base address */ |
AnnaBridge | 171:3a7713b1edbc | 11241 | #define VREF_BASE (0x40074000u) |
AnnaBridge | 171:3a7713b1edbc | 11242 | /** Peripheral VREF base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11243 | #define VREF ((VREF_Type *)VREF_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11244 | /** Array initializer of VREF peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11245 | #define VREF_BASE_ADDRS { VREF_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11246 | /** Array initializer of VREF peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11247 | #define VREF_BASE_PTRS { VREF } |
AnnaBridge | 171:3a7713b1edbc | 11248 | |
AnnaBridge | 171:3a7713b1edbc | 11249 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11250 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11251 | */ /* end of group VREF_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11252 | |
AnnaBridge | 171:3a7713b1edbc | 11253 | |
AnnaBridge | 171:3a7713b1edbc | 11254 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11255 | -- WDOG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11256 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11257 | |
AnnaBridge | 171:3a7713b1edbc | 11258 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11259 | * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer |
AnnaBridge | 171:3a7713b1edbc | 11260 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11261 | */ |
AnnaBridge | 171:3a7713b1edbc | 11262 | |
AnnaBridge | 171:3a7713b1edbc | 11263 | /** WDOG - Register Layout Typedef */ |
AnnaBridge | 171:3a7713b1edbc | 11264 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 11265 | __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */ |
AnnaBridge | 171:3a7713b1edbc | 11266 | __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */ |
AnnaBridge | 171:3a7713b1edbc | 11267 | __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */ |
AnnaBridge | 171:3a7713b1edbc | 11268 | __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */ |
AnnaBridge | 171:3a7713b1edbc | 11269 | __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */ |
AnnaBridge | 171:3a7713b1edbc | 11270 | __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */ |
AnnaBridge | 171:3a7713b1edbc | 11271 | __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */ |
AnnaBridge | 171:3a7713b1edbc | 11272 | __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */ |
AnnaBridge | 171:3a7713b1edbc | 11273 | __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */ |
AnnaBridge | 171:3a7713b1edbc | 11274 | __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */ |
AnnaBridge | 171:3a7713b1edbc | 11275 | __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */ |
AnnaBridge | 171:3a7713b1edbc | 11276 | __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */ |
AnnaBridge | 171:3a7713b1edbc | 11277 | } WDOG_Type; |
AnnaBridge | 171:3a7713b1edbc | 11278 | |
AnnaBridge | 171:3a7713b1edbc | 11279 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11280 | -- WDOG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11281 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11282 | |
AnnaBridge | 171:3a7713b1edbc | 11283 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11284 | * @addtogroup WDOG_Register_Masks WDOG Register Masks |
AnnaBridge | 171:3a7713b1edbc | 11285 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11286 | */ |
AnnaBridge | 171:3a7713b1edbc | 11287 | |
AnnaBridge | 171:3a7713b1edbc | 11288 | /*! @name STCTRLH - Watchdog Status and Control Register High */ |
AnnaBridge | 171:3a7713b1edbc | 11289 | #define WDOG_STCTRLH_WDOGEN_MASK (0x1U) |
AnnaBridge | 171:3a7713b1edbc | 11290 | #define WDOG_STCTRLH_WDOGEN_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11291 | #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11292 | #define WDOG_STCTRLH_CLKSRC_MASK (0x2U) |
AnnaBridge | 171:3a7713b1edbc | 11293 | #define WDOG_STCTRLH_CLKSRC_SHIFT (1U) |
AnnaBridge | 171:3a7713b1edbc | 11294 | #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11295 | #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U) |
AnnaBridge | 171:3a7713b1edbc | 11296 | #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U) |
AnnaBridge | 171:3a7713b1edbc | 11297 | #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11298 | #define WDOG_STCTRLH_WINEN_MASK (0x8U) |
AnnaBridge | 171:3a7713b1edbc | 11299 | #define WDOG_STCTRLH_WINEN_SHIFT (3U) |
AnnaBridge | 171:3a7713b1edbc | 11300 | #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11301 | #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U) |
AnnaBridge | 171:3a7713b1edbc | 11302 | #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U) |
AnnaBridge | 171:3a7713b1edbc | 11303 | #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11304 | #define WDOG_STCTRLH_DBGEN_MASK (0x20U) |
AnnaBridge | 171:3a7713b1edbc | 11305 | #define WDOG_STCTRLH_DBGEN_SHIFT (5U) |
AnnaBridge | 171:3a7713b1edbc | 11306 | #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11307 | #define WDOG_STCTRLH_STOPEN_MASK (0x40U) |
AnnaBridge | 171:3a7713b1edbc | 11308 | #define WDOG_STCTRLH_STOPEN_SHIFT (6U) |
AnnaBridge | 171:3a7713b1edbc | 11309 | #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11310 | #define WDOG_STCTRLH_WAITEN_MASK (0x80U) |
AnnaBridge | 171:3a7713b1edbc | 11311 | #define WDOG_STCTRLH_WAITEN_SHIFT (7U) |
AnnaBridge | 171:3a7713b1edbc | 11312 | #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11313 | #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U) |
AnnaBridge | 171:3a7713b1edbc | 11314 | #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U) |
AnnaBridge | 171:3a7713b1edbc | 11315 | #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11316 | #define WDOG_STCTRLH_TESTSEL_MASK (0x800U) |
AnnaBridge | 171:3a7713b1edbc | 11317 | #define WDOG_STCTRLH_TESTSEL_SHIFT (11U) |
AnnaBridge | 171:3a7713b1edbc | 11318 | #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11319 | #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U) |
AnnaBridge | 171:3a7713b1edbc | 11320 | #define WDOG_STCTRLH_BYTESEL_SHIFT (12U) |
AnnaBridge | 171:3a7713b1edbc | 11321 | #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11322 | #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U) |
AnnaBridge | 171:3a7713b1edbc | 11323 | #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U) |
AnnaBridge | 171:3a7713b1edbc | 11324 | #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11325 | |
AnnaBridge | 171:3a7713b1edbc | 11326 | /*! @name STCTRLL - Watchdog Status and Control Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 11327 | #define WDOG_STCTRLL_INTFLG_MASK (0x8000U) |
AnnaBridge | 171:3a7713b1edbc | 11328 | #define WDOG_STCTRLL_INTFLG_SHIFT (15U) |
AnnaBridge | 171:3a7713b1edbc | 11329 | #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11330 | |
AnnaBridge | 171:3a7713b1edbc | 11331 | /*! @name TOVALH - Watchdog Time-out Value Register High */ |
AnnaBridge | 171:3a7713b1edbc | 11332 | #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11333 | #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11334 | #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11335 | |
AnnaBridge | 171:3a7713b1edbc | 11336 | /*! @name TOVALL - Watchdog Time-out Value Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 11337 | #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11338 | #define WDOG_TOVALL_TOVALLOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11339 | #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11340 | |
AnnaBridge | 171:3a7713b1edbc | 11341 | /*! @name WINH - Watchdog Window Register High */ |
AnnaBridge | 171:3a7713b1edbc | 11342 | #define WDOG_WINH_WINHIGH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11343 | #define WDOG_WINH_WINHIGH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11344 | #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11345 | |
AnnaBridge | 171:3a7713b1edbc | 11346 | /*! @name WINL - Watchdog Window Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 11347 | #define WDOG_WINL_WINLOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11348 | #define WDOG_WINL_WINLOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11349 | #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11350 | |
AnnaBridge | 171:3a7713b1edbc | 11351 | /*! @name REFRESH - Watchdog Refresh register */ |
AnnaBridge | 171:3a7713b1edbc | 11352 | #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11353 | #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11354 | #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11355 | |
AnnaBridge | 171:3a7713b1edbc | 11356 | /*! @name UNLOCK - Watchdog Unlock register */ |
AnnaBridge | 171:3a7713b1edbc | 11357 | #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11358 | #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11359 | #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11360 | |
AnnaBridge | 171:3a7713b1edbc | 11361 | /*! @name TMROUTH - Watchdog Timer Output Register High */ |
AnnaBridge | 171:3a7713b1edbc | 11362 | #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11363 | #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11364 | #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11365 | |
AnnaBridge | 171:3a7713b1edbc | 11366 | /*! @name TMROUTL - Watchdog Timer Output Register Low */ |
AnnaBridge | 171:3a7713b1edbc | 11367 | #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11368 | #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11369 | #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11370 | |
AnnaBridge | 171:3a7713b1edbc | 11371 | /*! @name RSTCNT - Watchdog Reset Count register */ |
AnnaBridge | 171:3a7713b1edbc | 11372 | #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU) |
AnnaBridge | 171:3a7713b1edbc | 11373 | #define WDOG_RSTCNT_RSTCNT_SHIFT (0U) |
AnnaBridge | 171:3a7713b1edbc | 11374 | #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11375 | |
AnnaBridge | 171:3a7713b1edbc | 11376 | /*! @name PRESC - Watchdog Prescaler register */ |
AnnaBridge | 171:3a7713b1edbc | 11377 | #define WDOG_PRESC_PRESCVAL_MASK (0x700U) |
AnnaBridge | 171:3a7713b1edbc | 11378 | #define WDOG_PRESC_PRESCVAL_SHIFT (8U) |
AnnaBridge | 171:3a7713b1edbc | 11379 | #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK) |
AnnaBridge | 171:3a7713b1edbc | 11380 | |
AnnaBridge | 171:3a7713b1edbc | 11381 | |
AnnaBridge | 171:3a7713b1edbc | 11382 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11383 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11384 | */ /* end of group WDOG_Register_Masks */ |
AnnaBridge | 171:3a7713b1edbc | 11385 | |
AnnaBridge | 171:3a7713b1edbc | 11386 | |
AnnaBridge | 171:3a7713b1edbc | 11387 | /* WDOG - Peripheral instance base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11388 | /** Peripheral WDOG base address */ |
AnnaBridge | 171:3a7713b1edbc | 11389 | #define WDOG_BASE (0x40052000u) |
AnnaBridge | 171:3a7713b1edbc | 11390 | /** Peripheral WDOG base pointer */ |
AnnaBridge | 171:3a7713b1edbc | 11391 | #define WDOG ((WDOG_Type *)WDOG_BASE) |
AnnaBridge | 171:3a7713b1edbc | 11392 | /** Array initializer of WDOG peripheral base addresses */ |
AnnaBridge | 171:3a7713b1edbc | 11393 | #define WDOG_BASE_ADDRS { WDOG_BASE } |
AnnaBridge | 171:3a7713b1edbc | 11394 | /** Array initializer of WDOG peripheral base pointers */ |
AnnaBridge | 171:3a7713b1edbc | 11395 | #define WDOG_BASE_PTRS { WDOG } |
AnnaBridge | 171:3a7713b1edbc | 11396 | /** Interrupt vectors for the WDOG peripheral type */ |
AnnaBridge | 171:3a7713b1edbc | 11397 | #define WDOG_IRQS { WDOG_EWM_IRQn } |
AnnaBridge | 171:3a7713b1edbc | 11398 | |
AnnaBridge | 171:3a7713b1edbc | 11399 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11400 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11401 | */ /* end of group WDOG_Peripheral_Access_Layer */ |
AnnaBridge | 171:3a7713b1edbc | 11402 | |
AnnaBridge | 171:3a7713b1edbc | 11403 | |
AnnaBridge | 171:3a7713b1edbc | 11404 | /* |
AnnaBridge | 171:3a7713b1edbc | 11405 | ** End of section using anonymous unions |
AnnaBridge | 171:3a7713b1edbc | 11406 | */ |
AnnaBridge | 171:3a7713b1edbc | 11407 | |
AnnaBridge | 171:3a7713b1edbc | 11408 | #if defined(__ARMCC_VERSION) |
AnnaBridge | 171:3a7713b1edbc | 11409 | #pragma pop |
AnnaBridge | 171:3a7713b1edbc | 11410 | #elif defined(__CWCC__) |
AnnaBridge | 171:3a7713b1edbc | 11411 | #pragma pop |
AnnaBridge | 171:3a7713b1edbc | 11412 | #elif defined(__GNUC__) |
AnnaBridge | 171:3a7713b1edbc | 11413 | /* leave anonymous unions enabled */ |
AnnaBridge | 171:3a7713b1edbc | 11414 | #elif defined(__IAR_SYSTEMS_ICC__) |
AnnaBridge | 171:3a7713b1edbc | 11415 | #pragma language=default |
AnnaBridge | 171:3a7713b1edbc | 11416 | #else |
AnnaBridge | 171:3a7713b1edbc | 11417 | #error Not supported compiler type |
AnnaBridge | 171:3a7713b1edbc | 11418 | #endif |
AnnaBridge | 171:3a7713b1edbc | 11419 | |
AnnaBridge | 171:3a7713b1edbc | 11420 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11421 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11422 | */ /* end of group Peripheral_access_layer */ |
AnnaBridge | 171:3a7713b1edbc | 11423 | |
AnnaBridge | 171:3a7713b1edbc | 11424 | |
AnnaBridge | 171:3a7713b1edbc | 11425 | /* ---------------------------------------------------------------------------- |
AnnaBridge | 171:3a7713b1edbc | 11426 | -- SDK Compatibility |
AnnaBridge | 171:3a7713b1edbc | 11427 | ---------------------------------------------------------------------------- */ |
AnnaBridge | 171:3a7713b1edbc | 11428 | |
AnnaBridge | 171:3a7713b1edbc | 11429 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11430 | * @addtogroup SDK_Compatibility_Symbols SDK Compatibility |
AnnaBridge | 171:3a7713b1edbc | 11431 | * @{ |
AnnaBridge | 171:3a7713b1edbc | 11432 | */ |
AnnaBridge | 171:3a7713b1edbc | 11433 | |
AnnaBridge | 171:3a7713b1edbc | 11434 | #define DSPI0 SPI0 |
AnnaBridge | 171:3a7713b1edbc | 11435 | #define DSPI1 SPI1 |
AnnaBridge | 171:3a7713b1edbc | 11436 | #define DMAMUX0 DMAMUX |
AnnaBridge | 171:3a7713b1edbc | 11437 | #define DMA0_04_IRQn DMA0_DMA4_IRQn |
AnnaBridge | 171:3a7713b1edbc | 11438 | #define DMA0_15_IRQn DMA1_DMA5_IRQn |
AnnaBridge | 171:3a7713b1edbc | 11439 | #define DMA0_26_IRQn DMA2_DMA6_IRQn |
AnnaBridge | 171:3a7713b1edbc | 11440 | #define DMA0_37_IRQn DMA3_DMA7_IRQn |
AnnaBridge | 171:3a7713b1edbc | 11441 | #define DMA0_04_DriverIRQHandler DMA0_DMA4_DriverIRQHandler |
AnnaBridge | 171:3a7713b1edbc | 11442 | #define DMA0_15_DriverIRQHandler DMA1_DMA5_DriverIRQHandler |
AnnaBridge | 171:3a7713b1edbc | 11443 | #define DMA0_26_DriverIRQHandler DMA2_DMA6_DriverIRQHandler |
AnnaBridge | 171:3a7713b1edbc | 11444 | #define DMA0_37_DriverIRQHandler DMA3_DMA7_DriverIRQHandler |
AnnaBridge | 171:3a7713b1edbc | 11445 | #define PIT PIT0 |
AnnaBridge | 171:3a7713b1edbc | 11446 | #define RTC_IRQn RTC_Alarm_IRQn |
AnnaBridge | 171:3a7713b1edbc | 11447 | #define RTC_IRQHandler RTC_Alarm_IRQHandler |
AnnaBridge | 171:3a7713b1edbc | 11448 | #define kDmaRequestMux0Group1LTC0InputFIFO kDmaRequestMux0LTC0InputFIFO |
AnnaBridge | 171:3a7713b1edbc | 11449 | #define kDmaRequestMux0Group1LTC0OutputFIFO kDmaRequestMux0LTC0OutputFIFO |
AnnaBridge | 171:3a7713b1edbc | 11450 | #define kDmaRequestMux0Group1LTC0PKHA kDmaRequestMux0LTC0PKHA |
AnnaBridge | 171:3a7713b1edbc | 11451 | |
AnnaBridge | 171:3a7713b1edbc | 11452 | /*! |
AnnaBridge | 171:3a7713b1edbc | 11453 | * @} |
AnnaBridge | 171:3a7713b1edbc | 11454 | */ /* end of group SDK_Compatibility_Symbols */ |
AnnaBridge | 171:3a7713b1edbc | 11455 | |
AnnaBridge | 171:3a7713b1edbc | 11456 | |
AnnaBridge | 171:3a7713b1edbc | 11457 | #endif /* _MKL82Z7_H_ */ |
AnnaBridge | 171:3a7713b1edbc | 11458 |