mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_TY51822R3/TOOLCHAIN_IAR/nrf51_bitfields.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_NRF51_DONGLE/TARGET_NORDIC/TARGET_NRF5x/TARGET_SDK_11/device/nrf51_bitfields.h@169:a7c7b631e539 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /*
AnnaBridge 143:86740a56073b 2 * Copyright (c) 2015 Nordic Semiconductor ASA
AnnaBridge 143:86740a56073b 3 * All rights reserved.
AnnaBridge 143:86740a56073b 4 *
AnnaBridge 143:86740a56073b 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 6 * are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 7 *
AnnaBridge 143:86740a56073b 8 * 1. Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 143:86740a56073b 9 * of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 10 *
AnnaBridge 143:86740a56073b 11 * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
AnnaBridge 143:86740a56073b 12 * integrated circuit in a product or a software update for such product, must reproduce
AnnaBridge 143:86740a56073b 13 * the above copyright notice, this list of conditions and the following disclaimer in
AnnaBridge 143:86740a56073b 14 * the documentation and/or other materials provided with the distribution.
AnnaBridge 143:86740a56073b 15 *
AnnaBridge 143:86740a56073b 16 * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
AnnaBridge 143:86740a56073b 17 * used to endorse or promote products derived from this software without specific prior
AnnaBridge 143:86740a56073b 18 * written permission.
AnnaBridge 143:86740a56073b 19 *
AnnaBridge 143:86740a56073b 20 * 4. This software, with or without modification, must only be used with a
AnnaBridge 143:86740a56073b 21 * Nordic Semiconductor ASA integrated circuit.
AnnaBridge 143:86740a56073b 22 *
AnnaBridge 143:86740a56073b 23 * 5. Any software provided in binary or object form under this license must not be reverse
AnnaBridge 143:86740a56073b 24 * engineered, decompiled, modified and/or disassembled.
AnnaBridge 143:86740a56073b 25 *
AnnaBridge 143:86740a56073b 26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 143:86740a56073b 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 143:86740a56073b 28 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 29 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 143:86740a56073b 30 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 143:86740a56073b 31 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 143:86740a56073b 32 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 143:86740a56073b 33 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 143:86740a56073b 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 143:86740a56073b 35 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 36 *
AnnaBridge 143:86740a56073b 37 */
AnnaBridge 143:86740a56073b 38
AnnaBridge 143:86740a56073b 39 #ifndef __NRF51_BITS_H
AnnaBridge 143:86740a56073b 40 #define __NRF51_BITS_H
AnnaBridge 143:86740a56073b 41
AnnaBridge 143:86740a56073b 42 /*lint ++flb "Enter library region" */
AnnaBridge 143:86740a56073b 43
AnnaBridge 143:86740a56073b 44 /* Peripheral: AAR */
AnnaBridge 143:86740a56073b 45 /* Description: Accelerated Address Resolver. */
AnnaBridge 143:86740a56073b 46
AnnaBridge 143:86740a56073b 47 /* Register: AAR_INTENSET */
AnnaBridge 143:86740a56073b 48 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 49
AnnaBridge 143:86740a56073b 50 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
AnnaBridge 143:86740a56073b 51 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 52 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 53 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 54 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 55 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 56
AnnaBridge 143:86740a56073b 57 /* Bit 1 : Enable interrupt on RESOLVED event. */
AnnaBridge 143:86740a56073b 58 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
AnnaBridge 143:86740a56073b 59 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
AnnaBridge 143:86740a56073b 60 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 61 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 62 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 63
AnnaBridge 143:86740a56073b 64 /* Bit 0 : Enable interrupt on END event. */
AnnaBridge 143:86740a56073b 65 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 66 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 67 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 68 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 69 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 70
AnnaBridge 143:86740a56073b 71 /* Register: AAR_INTENCLR */
AnnaBridge 143:86740a56073b 72 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 73
AnnaBridge 143:86740a56073b 74 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
AnnaBridge 143:86740a56073b 75 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 76 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
AnnaBridge 143:86740a56073b 77 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 78 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 79 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 80
AnnaBridge 143:86740a56073b 81 /* Bit 1 : Disable interrupt on RESOLVED event. */
AnnaBridge 143:86740a56073b 82 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
AnnaBridge 143:86740a56073b 83 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
AnnaBridge 143:86740a56073b 84 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 85 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 86 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 87
AnnaBridge 143:86740a56073b 88 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
AnnaBridge 143:86740a56073b 89 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 90 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 91 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 92 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 93 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 94
AnnaBridge 143:86740a56073b 95 /* Register: AAR_STATUS */
AnnaBridge 143:86740a56073b 96 /* Description: Resolution status. */
AnnaBridge 143:86740a56073b 97
AnnaBridge 143:86740a56073b 98 /* Bits 3..0 : The IRK used last time an address was resolved. */
AnnaBridge 143:86740a56073b 99 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 100 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 101
AnnaBridge 143:86740a56073b 102 /* Register: AAR_ENABLE */
AnnaBridge 143:86740a56073b 103 /* Description: Enable AAR. */
AnnaBridge 143:86740a56073b 104
AnnaBridge 143:86740a56073b 105 /* Bits 1..0 : Enable AAR. */
AnnaBridge 143:86740a56073b 106 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 107 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 108 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
AnnaBridge 143:86740a56073b 109 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
AnnaBridge 143:86740a56073b 110
AnnaBridge 143:86740a56073b 111 /* Register: AAR_NIRK */
AnnaBridge 143:86740a56073b 112 /* Description: Number of Identity root Keys in the IRK data structure. */
AnnaBridge 143:86740a56073b 113
AnnaBridge 143:86740a56073b 114 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
AnnaBridge 143:86740a56073b 115 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
AnnaBridge 143:86740a56073b 116 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
AnnaBridge 143:86740a56073b 117
AnnaBridge 143:86740a56073b 118 /* Register: AAR_POWER */
AnnaBridge 143:86740a56073b 119 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 120
AnnaBridge 143:86740a56073b 121 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 122 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 123 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 124 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 125 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 126
AnnaBridge 143:86740a56073b 127
AnnaBridge 143:86740a56073b 128 /* Peripheral: ADC */
AnnaBridge 143:86740a56073b 129 /* Description: Analog to digital converter. */
AnnaBridge 143:86740a56073b 130
AnnaBridge 143:86740a56073b 131 /* Register: ADC_INTENSET */
AnnaBridge 143:86740a56073b 132 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 133
AnnaBridge 143:86740a56073b 134 /* Bit 0 : Enable interrupt on END event. */
AnnaBridge 143:86740a56073b 135 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 136 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 137 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 138 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 139 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 140
AnnaBridge 143:86740a56073b 141 /* Register: ADC_INTENCLR */
AnnaBridge 143:86740a56073b 142 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 143
AnnaBridge 143:86740a56073b 144 /* Bit 0 : Disable interrupt on END event. */
AnnaBridge 143:86740a56073b 145 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 146 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 147 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 148 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 149 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 150
AnnaBridge 143:86740a56073b 151 /* Register: ADC_BUSY */
AnnaBridge 143:86740a56073b 152 /* Description: ADC busy register. */
AnnaBridge 143:86740a56073b 153
AnnaBridge 143:86740a56073b 154 /* Bit 0 : ADC busy register. */
AnnaBridge 143:86740a56073b 155 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
AnnaBridge 143:86740a56073b 156 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
AnnaBridge 143:86740a56073b 157 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
AnnaBridge 143:86740a56073b 158 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
AnnaBridge 143:86740a56073b 159
AnnaBridge 143:86740a56073b 160 /* Register: ADC_ENABLE */
AnnaBridge 143:86740a56073b 161 /* Description: ADC enable. */
AnnaBridge 143:86740a56073b 162
AnnaBridge 143:86740a56073b 163 /* Bits 1..0 : ADC enable. */
AnnaBridge 143:86740a56073b 164 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 165 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 166 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
AnnaBridge 143:86740a56073b 167 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
AnnaBridge 143:86740a56073b 168
AnnaBridge 143:86740a56073b 169 /* Register: ADC_CONFIG */
AnnaBridge 143:86740a56073b 170 /* Description: ADC configuration register. */
AnnaBridge 143:86740a56073b 171
AnnaBridge 143:86740a56073b 172 /* Bits 17..16 : ADC external reference pin selection. */
AnnaBridge 143:86740a56073b 173 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 174 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 175 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
AnnaBridge 143:86740a56073b 176 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
AnnaBridge 143:86740a56073b 177 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
AnnaBridge 143:86740a56073b 178
AnnaBridge 143:86740a56073b 179 /* Bits 15..8 : ADC analog pin selection. */
AnnaBridge 143:86740a56073b 180 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
AnnaBridge 143:86740a56073b 181 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
AnnaBridge 143:86740a56073b 182 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
AnnaBridge 143:86740a56073b 183 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
AnnaBridge 143:86740a56073b 184 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
AnnaBridge 143:86740a56073b 185 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
AnnaBridge 143:86740a56073b 186 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
AnnaBridge 143:86740a56073b 187 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
AnnaBridge 143:86740a56073b 188 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
AnnaBridge 143:86740a56073b 189 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
AnnaBridge 143:86740a56073b 190 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
AnnaBridge 143:86740a56073b 191
AnnaBridge 143:86740a56073b 192 /* Bits 6..5 : ADC reference selection. */
AnnaBridge 143:86740a56073b 193 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
AnnaBridge 143:86740a56073b 194 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
AnnaBridge 143:86740a56073b 195 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
AnnaBridge 143:86740a56073b 196 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
AnnaBridge 143:86740a56073b 197 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
AnnaBridge 143:86740a56073b 198 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
AnnaBridge 143:86740a56073b 199
AnnaBridge 143:86740a56073b 200 /* Bits 4..2 : ADC input selection. */
AnnaBridge 143:86740a56073b 201 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
AnnaBridge 143:86740a56073b 202 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
AnnaBridge 143:86740a56073b 203 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
AnnaBridge 143:86740a56073b 204 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
AnnaBridge 143:86740a56073b 205 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
AnnaBridge 143:86740a56073b 206 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
AnnaBridge 143:86740a56073b 207 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
AnnaBridge 143:86740a56073b 208
AnnaBridge 143:86740a56073b 209 /* Bits 1..0 : ADC resolution. */
AnnaBridge 143:86740a56073b 210 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
AnnaBridge 143:86740a56073b 211 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
AnnaBridge 143:86740a56073b 212 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
AnnaBridge 143:86740a56073b 213 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
AnnaBridge 143:86740a56073b 214 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
AnnaBridge 143:86740a56073b 215
AnnaBridge 143:86740a56073b 216 /* Register: ADC_RESULT */
AnnaBridge 143:86740a56073b 217 /* Description: Result of ADC conversion. */
AnnaBridge 143:86740a56073b 218
AnnaBridge 143:86740a56073b 219 /* Bits 9..0 : Result of ADC conversion. */
AnnaBridge 143:86740a56073b 220 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
AnnaBridge 143:86740a56073b 221 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
AnnaBridge 143:86740a56073b 222
AnnaBridge 143:86740a56073b 223 /* Register: ADC_POWER */
AnnaBridge 143:86740a56073b 224 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 225
AnnaBridge 143:86740a56073b 226 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 227 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 228 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 229 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 230 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 231
AnnaBridge 143:86740a56073b 232
AnnaBridge 143:86740a56073b 233 /* Peripheral: AMLI */
AnnaBridge 143:86740a56073b 234 /* Description: AHB Multi-Layer Interface. */
AnnaBridge 143:86740a56073b 235
AnnaBridge 143:86740a56073b 236 /* Register: AMLI_RAMPRI_CPU0 */
AnnaBridge 143:86740a56073b 237 /* Description: Configurable priority configuration register for CPU0. */
AnnaBridge 143:86740a56073b 238
AnnaBridge 143:86740a56073b 239 /* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge 143:86740a56073b 240 #define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 241 #define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 242 #define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 243 #define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 244 #define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 245 #define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 246 #define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 247 #define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 248 #define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 249 #define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 250
AnnaBridge 143:86740a56073b 251 /* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge 143:86740a56073b 252 #define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 253 #define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 254 #define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 255 #define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 256 #define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 257 #define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 258 #define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 259 #define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 260 #define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 261 #define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263 /* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge 143:86740a56073b 264 #define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 265 #define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 266 #define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 267 #define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 268 #define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 269 #define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 270 #define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 271 #define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 272 #define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 273 #define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 274
AnnaBridge 143:86740a56073b 275 /* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge 143:86740a56073b 276 #define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 277 #define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 278 #define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 279 #define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 280 #define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 281 #define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 282 #define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 283 #define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 284 #define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 285 #define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 286
AnnaBridge 143:86740a56073b 287 /* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge 143:86740a56073b 288 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 289 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 290 #define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 291 #define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 292 #define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 293 #define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 294 #define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 295 #define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 296 #define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 297 #define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 298
AnnaBridge 143:86740a56073b 299 /* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge 143:86740a56073b 300 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 301 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 302 #define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 303 #define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 304 #define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 305 #define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 306 #define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 307 #define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 308 #define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 309 #define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 310
AnnaBridge 143:86740a56073b 311 /* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge 143:86740a56073b 312 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 313 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 314 #define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 315 #define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 316 #define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 317 #define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 318 #define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 319 #define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 320 #define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 321 #define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 322
AnnaBridge 143:86740a56073b 323 /* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge 143:86740a56073b 324 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 325 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 326 #define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 327 #define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 328 #define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 329 #define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 330 #define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 331 #define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 332 #define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 333 #define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 334
AnnaBridge 143:86740a56073b 335 /* Register: AMLI_RAMPRI_SPIS1 */
AnnaBridge 143:86740a56073b 336 /* Description: Configurable priority configuration register for SPIS1. */
AnnaBridge 143:86740a56073b 337
AnnaBridge 143:86740a56073b 338 /* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge 143:86740a56073b 339 #define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 340 #define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 341 #define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 342 #define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 343 #define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 344 #define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 345 #define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 346 #define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 347 #define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 348 #define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 349
AnnaBridge 143:86740a56073b 350 /* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge 143:86740a56073b 351 #define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 352 #define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 353 #define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 354 #define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 355 #define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 356 #define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 357 #define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 358 #define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 359 #define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 360 #define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 361
AnnaBridge 143:86740a56073b 362 /* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge 143:86740a56073b 363 #define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 364 #define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 365 #define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 366 #define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 367 #define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 368 #define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 369 #define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 370 #define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 371 #define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 372 #define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 373
AnnaBridge 143:86740a56073b 374 /* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge 143:86740a56073b 375 #define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 376 #define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 377 #define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 378 #define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 379 #define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 380 #define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 381 #define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 382 #define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 383 #define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 384 #define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 385
AnnaBridge 143:86740a56073b 386 /* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge 143:86740a56073b 387 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 388 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 389 #define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 390 #define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 391 #define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 392 #define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 393 #define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 394 #define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 395 #define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 396 #define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 397
AnnaBridge 143:86740a56073b 398 /* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge 143:86740a56073b 399 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 400 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 401 #define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 402 #define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 403 #define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 404 #define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 405 #define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 406 #define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 407 #define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 408 #define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 409
AnnaBridge 143:86740a56073b 410 /* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge 143:86740a56073b 411 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 412 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 413 #define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 414 #define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 415 #define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 416 #define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 417 #define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 418 #define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 419 #define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 420 #define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 421
AnnaBridge 143:86740a56073b 422 /* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge 143:86740a56073b 423 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 424 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 425 #define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 426 #define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 427 #define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 428 #define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 429 #define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 430 #define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 431 #define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 432 #define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 433
AnnaBridge 143:86740a56073b 434 /* Register: AMLI_RAMPRI_RADIO */
AnnaBridge 143:86740a56073b 435 /* Description: Configurable priority configuration register for RADIO. */
AnnaBridge 143:86740a56073b 436
AnnaBridge 143:86740a56073b 437 /* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge 143:86740a56073b 438 #define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 439 #define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 440 #define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 441 #define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 442 #define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 443 #define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 444 #define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 445 #define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 446 #define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 447 #define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 448
AnnaBridge 143:86740a56073b 449 /* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge 143:86740a56073b 450 #define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 451 #define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 452 #define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 453 #define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 454 #define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 455 #define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 456 #define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 457 #define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 458 #define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 459 #define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 460
AnnaBridge 143:86740a56073b 461 /* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge 143:86740a56073b 462 #define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 463 #define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 464 #define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 465 #define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 466 #define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 467 #define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 468 #define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 469 #define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 470 #define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 471 #define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 472
AnnaBridge 143:86740a56073b 473 /* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge 143:86740a56073b 474 #define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 475 #define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 476 #define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 477 #define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 478 #define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 479 #define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 480 #define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 481 #define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 482 #define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 483 #define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 484
AnnaBridge 143:86740a56073b 485 /* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge 143:86740a56073b 486 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 487 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 488 #define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 489 #define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 490 #define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 491 #define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 492 #define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 493 #define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 494 #define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 495 #define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 496
AnnaBridge 143:86740a56073b 497 /* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge 143:86740a56073b 498 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 499 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 500 #define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 501 #define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 502 #define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 503 #define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 504 #define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 505 #define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 506 #define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 507 #define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 508
AnnaBridge 143:86740a56073b 509 /* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge 143:86740a56073b 510 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 511 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 512 #define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 513 #define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 514 #define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 515 #define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 516 #define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 517 #define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 518 #define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 519 #define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 520
AnnaBridge 143:86740a56073b 521 /* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge 143:86740a56073b 522 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 523 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 524 #define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 525 #define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 526 #define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 527 #define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 528 #define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 529 #define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 530 #define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 531 #define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 532
AnnaBridge 143:86740a56073b 533 /* Register: AMLI_RAMPRI_ECB */
AnnaBridge 143:86740a56073b 534 /* Description: Configurable priority configuration register for ECB. */
AnnaBridge 143:86740a56073b 535
AnnaBridge 143:86740a56073b 536 /* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge 143:86740a56073b 537 #define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 538 #define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 539 #define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 540 #define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 541 #define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 542 #define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 543 #define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 544 #define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 545 #define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 546 #define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 547
AnnaBridge 143:86740a56073b 548 /* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge 143:86740a56073b 549 #define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 550 #define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 551 #define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 552 #define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 553 #define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 554 #define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 555 #define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 556 #define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 557 #define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 558 #define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 559
AnnaBridge 143:86740a56073b 560 /* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge 143:86740a56073b 561 #define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 562 #define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 563 #define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 564 #define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 565 #define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 566 #define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 567 #define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 568 #define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 569 #define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 570 #define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 571
AnnaBridge 143:86740a56073b 572 /* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge 143:86740a56073b 573 #define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 574 #define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 575 #define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 576 #define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 577 #define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 578 #define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 579 #define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 580 #define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 581 #define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 582 #define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 583
AnnaBridge 143:86740a56073b 584 /* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge 143:86740a56073b 585 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 586 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 587 #define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 588 #define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 589 #define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 590 #define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 591 #define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 592 #define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 593 #define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 594 #define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 595
AnnaBridge 143:86740a56073b 596 /* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge 143:86740a56073b 597 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 598 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 599 #define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 600 #define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 601 #define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 602 #define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 603 #define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 604 #define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 605 #define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 606 #define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 607
AnnaBridge 143:86740a56073b 608 /* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge 143:86740a56073b 609 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 610 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 611 #define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 612 #define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 613 #define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 614 #define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 615 #define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 616 #define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 617 #define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 618 #define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 619
AnnaBridge 143:86740a56073b 620 /* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge 143:86740a56073b 621 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 622 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 623 #define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 624 #define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 625 #define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 626 #define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 627 #define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 628 #define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 629 #define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 630 #define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 631
AnnaBridge 143:86740a56073b 632 /* Register: AMLI_RAMPRI_CCM */
AnnaBridge 143:86740a56073b 633 /* Description: Configurable priority configuration register for CCM. */
AnnaBridge 143:86740a56073b 634
AnnaBridge 143:86740a56073b 635 /* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge 143:86740a56073b 636 #define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 637 #define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 638 #define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 639 #define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 640 #define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 641 #define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 642 #define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 643 #define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 644 #define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 645 #define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 646
AnnaBridge 143:86740a56073b 647 /* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge 143:86740a56073b 648 #define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 649 #define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 650 #define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 651 #define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 652 #define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 653 #define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 654 #define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 655 #define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 656 #define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 657 #define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 658
AnnaBridge 143:86740a56073b 659 /* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge 143:86740a56073b 660 #define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 661 #define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 662 #define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 663 #define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 664 #define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 665 #define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 666 #define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 667 #define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 668 #define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 669 #define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 670
AnnaBridge 143:86740a56073b 671 /* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge 143:86740a56073b 672 #define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 673 #define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 674 #define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 675 #define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 676 #define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 677 #define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 678 #define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 679 #define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 680 #define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 681 #define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 682
AnnaBridge 143:86740a56073b 683 /* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge 143:86740a56073b 684 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 685 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 686 #define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 687 #define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 688 #define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 689 #define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 690 #define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 691 #define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 692 #define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 693 #define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 694
AnnaBridge 143:86740a56073b 695 /* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge 143:86740a56073b 696 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 697 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 698 #define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 699 #define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 700 #define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 701 #define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 702 #define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 703 #define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 704 #define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 705 #define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 706
AnnaBridge 143:86740a56073b 707 /* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge 143:86740a56073b 708 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 709 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 710 #define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 711 #define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 712 #define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 713 #define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 714 #define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 715 #define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 716 #define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 717 #define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 718
AnnaBridge 143:86740a56073b 719 /* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge 143:86740a56073b 720 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 721 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 722 #define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 723 #define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 724 #define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 725 #define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 726 #define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 727 #define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 728 #define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 729 #define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 730
AnnaBridge 143:86740a56073b 731 /* Register: AMLI_RAMPRI_AAR */
AnnaBridge 143:86740a56073b 732 /* Description: Configurable priority configuration register for AAR. */
AnnaBridge 143:86740a56073b 733
AnnaBridge 143:86740a56073b 734 /* Bits 31..28 : Configuration field for RAM block 7. */
AnnaBridge 143:86740a56073b 735 #define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
AnnaBridge 143:86740a56073b 736 #define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
AnnaBridge 143:86740a56073b 737 #define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 738 #define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 739 #define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 740 #define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 741 #define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 742 #define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 743 #define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 744 #define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 745
AnnaBridge 143:86740a56073b 746 /* Bits 27..24 : Configuration field for RAM block 6. */
AnnaBridge 143:86740a56073b 747 #define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
AnnaBridge 143:86740a56073b 748 #define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
AnnaBridge 143:86740a56073b 749 #define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 750 #define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 751 #define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 752 #define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 753 #define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 754 #define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 755 #define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 756 #define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 757
AnnaBridge 143:86740a56073b 758 /* Bits 23..20 : Configuration field for RAM block 5. */
AnnaBridge 143:86740a56073b 759 #define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
AnnaBridge 143:86740a56073b 760 #define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
AnnaBridge 143:86740a56073b 761 #define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 762 #define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 763 #define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 764 #define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 765 #define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 766 #define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 767 #define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 768 #define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 769
AnnaBridge 143:86740a56073b 770 /* Bits 19..16 : Configuration field for RAM block 4. */
AnnaBridge 143:86740a56073b 771 #define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
AnnaBridge 143:86740a56073b 772 #define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
AnnaBridge 143:86740a56073b 773 #define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 774 #define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 775 #define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 776 #define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 777 #define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 778 #define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 779 #define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 780 #define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 781
AnnaBridge 143:86740a56073b 782 /* Bits 15..12 : Configuration field for RAM block 3. */
AnnaBridge 143:86740a56073b 783 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
AnnaBridge 143:86740a56073b 784 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
AnnaBridge 143:86740a56073b 785 #define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 786 #define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 787 #define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 788 #define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 789 #define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 790 #define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 791 #define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 792 #define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 793
AnnaBridge 143:86740a56073b 794 /* Bits 11..8 : Configuration field for RAM block 2. */
AnnaBridge 143:86740a56073b 795 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
AnnaBridge 143:86740a56073b 796 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
AnnaBridge 143:86740a56073b 797 #define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 798 #define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 799 #define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 800 #define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 801 #define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 802 #define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 803 #define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 804 #define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 805
AnnaBridge 143:86740a56073b 806 /* Bits 7..4 : Configuration field for RAM block 1. */
AnnaBridge 143:86740a56073b 807 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
AnnaBridge 143:86740a56073b 808 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
AnnaBridge 143:86740a56073b 809 #define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 810 #define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 811 #define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 812 #define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 813 #define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 814 #define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 815 #define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 816 #define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 817
AnnaBridge 143:86740a56073b 818 /* Bits 3..0 : Configuration field for RAM block 0. */
AnnaBridge 143:86740a56073b 819 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
AnnaBridge 143:86740a56073b 820 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
AnnaBridge 143:86740a56073b 821 #define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
AnnaBridge 143:86740a56073b 822 #define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
AnnaBridge 143:86740a56073b 823 #define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
AnnaBridge 143:86740a56073b 824 #define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
AnnaBridge 143:86740a56073b 825 #define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
AnnaBridge 143:86740a56073b 826 #define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
AnnaBridge 143:86740a56073b 827 #define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
AnnaBridge 143:86740a56073b 828 #define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
AnnaBridge 143:86740a56073b 829
AnnaBridge 143:86740a56073b 830
AnnaBridge 143:86740a56073b 831 /* Peripheral: CCM */
AnnaBridge 143:86740a56073b 832 /* Description: AES CCM Mode Encryption. */
AnnaBridge 143:86740a56073b 833
AnnaBridge 143:86740a56073b 834 /* Register: CCM_SHORTS */
AnnaBridge 143:86740a56073b 835 /* Description: Shortcuts for the CCM. */
AnnaBridge 143:86740a56073b 836
AnnaBridge 143:86740a56073b 837 /* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
AnnaBridge 143:86740a56073b 838 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
AnnaBridge 143:86740a56073b 839 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
AnnaBridge 143:86740a56073b 840 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 841 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 842
AnnaBridge 143:86740a56073b 843 /* Register: CCM_INTENSET */
AnnaBridge 143:86740a56073b 844 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 845
AnnaBridge 143:86740a56073b 846 /* Bit 2 : Enable interrupt on ERROR event. */
AnnaBridge 143:86740a56073b 847 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 848 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 849 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 850 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 851 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 852
AnnaBridge 143:86740a56073b 853 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
AnnaBridge 143:86740a56073b 854 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 855 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 856 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 857 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 858 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 859
AnnaBridge 143:86740a56073b 860 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
AnnaBridge 143:86740a56073b 861 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 862 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 863 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 864 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 865 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 866
AnnaBridge 143:86740a56073b 867 /* Register: CCM_INTENCLR */
AnnaBridge 143:86740a56073b 868 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 869
AnnaBridge 143:86740a56073b 870 /* Bit 2 : Disable interrupt on ERROR event. */
AnnaBridge 143:86740a56073b 871 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 872 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 873 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 874 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 875 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 876
AnnaBridge 143:86740a56073b 877 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
AnnaBridge 143:86740a56073b 878 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 879 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
AnnaBridge 143:86740a56073b 880 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 881 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 882 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 883
AnnaBridge 143:86740a56073b 884 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
AnnaBridge 143:86740a56073b 885 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 886 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
AnnaBridge 143:86740a56073b 887 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 888 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 889 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 890
AnnaBridge 143:86740a56073b 891 /* Register: CCM_MICSTATUS */
AnnaBridge 143:86740a56073b 892 /* Description: CCM RX MIC check result. */
AnnaBridge 143:86740a56073b 893
AnnaBridge 143:86740a56073b 894 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
AnnaBridge 143:86740a56073b 895 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
AnnaBridge 143:86740a56073b 896 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
AnnaBridge 143:86740a56073b 897 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
AnnaBridge 143:86740a56073b 898 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
AnnaBridge 143:86740a56073b 899
AnnaBridge 143:86740a56073b 900 /* Register: CCM_ENABLE */
AnnaBridge 143:86740a56073b 901 /* Description: CCM enable. */
AnnaBridge 143:86740a56073b 902
AnnaBridge 143:86740a56073b 903 /* Bits 1..0 : CCM enable. */
AnnaBridge 143:86740a56073b 904 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 905 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 906 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
AnnaBridge 143:86740a56073b 907 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
AnnaBridge 143:86740a56073b 908
AnnaBridge 143:86740a56073b 909 /* Register: CCM_MODE */
AnnaBridge 143:86740a56073b 910 /* Description: Operation mode. */
AnnaBridge 143:86740a56073b 911
AnnaBridge 143:86740a56073b 912 /* Bit 0 : CCM mode operation. */
AnnaBridge 143:86740a56073b 913 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 914 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 915 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
AnnaBridge 143:86740a56073b 916 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
AnnaBridge 143:86740a56073b 917
AnnaBridge 143:86740a56073b 918 /* Register: CCM_POWER */
AnnaBridge 143:86740a56073b 919 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 920
AnnaBridge 143:86740a56073b 921 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 922 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 923 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 924 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 925 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 926
AnnaBridge 143:86740a56073b 927
AnnaBridge 143:86740a56073b 928 /* Peripheral: CLOCK */
AnnaBridge 143:86740a56073b 929 /* Description: Clock control. */
AnnaBridge 143:86740a56073b 930
AnnaBridge 143:86740a56073b 931 /* Register: CLOCK_INTENSET */
AnnaBridge 143:86740a56073b 932 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 933
AnnaBridge 143:86740a56073b 934 /* Bit 4 : Enable interrupt on CTTO event. */
AnnaBridge 143:86740a56073b 935 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
AnnaBridge 143:86740a56073b 936 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
AnnaBridge 143:86740a56073b 937 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 938 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 939 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 940
AnnaBridge 143:86740a56073b 941 /* Bit 3 : Enable interrupt on DONE event. */
AnnaBridge 143:86740a56073b 942 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 943 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 944 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 945 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 946 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 947
AnnaBridge 143:86740a56073b 948 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
AnnaBridge 143:86740a56073b 949 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 950 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 951 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 952 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 953 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 954
AnnaBridge 143:86740a56073b 955 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
AnnaBridge 143:86740a56073b 956 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 957 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 958 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 959 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 960 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 961
AnnaBridge 143:86740a56073b 962 /* Register: CLOCK_INTENCLR */
AnnaBridge 143:86740a56073b 963 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 964
AnnaBridge 143:86740a56073b 965 /* Bit 4 : Disable interrupt on CTTO event. */
AnnaBridge 143:86740a56073b 966 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
AnnaBridge 143:86740a56073b 967 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
AnnaBridge 143:86740a56073b 968 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 969 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 970 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 971
AnnaBridge 143:86740a56073b 972 /* Bit 3 : Disable interrupt on DONE event. */
AnnaBridge 143:86740a56073b 973 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
AnnaBridge 143:86740a56073b 974 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
AnnaBridge 143:86740a56073b 975 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 976 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 977 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 978
AnnaBridge 143:86740a56073b 979 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
AnnaBridge 143:86740a56073b 980 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 981 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 982 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 983 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 984 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 985
AnnaBridge 143:86740a56073b 986 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
AnnaBridge 143:86740a56073b 987 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 988 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
AnnaBridge 143:86740a56073b 989 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 990 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 991 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 992
AnnaBridge 143:86740a56073b 993 /* Register: CLOCK_HFCLKRUN */
AnnaBridge 143:86740a56073b 994 /* Description: Task HFCLKSTART trigger status. */
AnnaBridge 143:86740a56073b 995
AnnaBridge 143:86740a56073b 996 /* Bit 0 : Task HFCLKSTART trigger status. */
AnnaBridge 143:86740a56073b 997 #define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 998 #define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 999 #define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
AnnaBridge 143:86740a56073b 1000 #define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
AnnaBridge 143:86740a56073b 1001
AnnaBridge 143:86740a56073b 1002 /* Register: CLOCK_HFCLKSTAT */
AnnaBridge 143:86740a56073b 1003 /* Description: High frequency clock status. */
AnnaBridge 143:86740a56073b 1004
AnnaBridge 143:86740a56073b 1005 /* Bit 16 : State for the HFCLK. */
AnnaBridge 143:86740a56073b 1006 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
AnnaBridge 143:86740a56073b 1007 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
AnnaBridge 143:86740a56073b 1008 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
AnnaBridge 143:86740a56073b 1009 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
AnnaBridge 143:86740a56073b 1010
AnnaBridge 143:86740a56073b 1011 /* Bit 0 : Active clock source for the HF clock. */
AnnaBridge 143:86740a56073b 1012 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 1013 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 1014 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
AnnaBridge 143:86740a56073b 1015 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
AnnaBridge 143:86740a56073b 1016
AnnaBridge 143:86740a56073b 1017 /* Register: CLOCK_LFCLKRUN */
AnnaBridge 143:86740a56073b 1018 /* Description: Task LFCLKSTART triggered status. */
AnnaBridge 143:86740a56073b 1019
AnnaBridge 143:86740a56073b 1020 /* Bit 0 : Task LFCLKSTART triggered status. */
AnnaBridge 143:86740a56073b 1021 #define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
AnnaBridge 143:86740a56073b 1022 #define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
AnnaBridge 143:86740a56073b 1023 #define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
AnnaBridge 143:86740a56073b 1024 #define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
AnnaBridge 143:86740a56073b 1025
AnnaBridge 143:86740a56073b 1026 /* Register: CLOCK_LFCLKSTAT */
AnnaBridge 143:86740a56073b 1027 /* Description: Low frequency clock status. */
AnnaBridge 143:86740a56073b 1028
AnnaBridge 143:86740a56073b 1029 /* Bit 16 : State for the LF clock. */
AnnaBridge 143:86740a56073b 1030 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
AnnaBridge 143:86740a56073b 1031 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
AnnaBridge 143:86740a56073b 1032 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
AnnaBridge 143:86740a56073b 1033 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
AnnaBridge 143:86740a56073b 1034
AnnaBridge 143:86740a56073b 1035 /* Bits 1..0 : Active clock source for the LF clock. */
AnnaBridge 143:86740a56073b 1036 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 1037 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 1038 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
AnnaBridge 143:86740a56073b 1039 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
AnnaBridge 143:86740a56073b 1040 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
AnnaBridge 143:86740a56073b 1041
AnnaBridge 143:86740a56073b 1042 /* Register: CLOCK_LFCLKSRCCOPY */
AnnaBridge 143:86740a56073b 1043 /* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
AnnaBridge 143:86740a56073b 1044
AnnaBridge 143:86740a56073b 1045 /* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
AnnaBridge 143:86740a56073b 1046 #define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 1047 #define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 1048 #define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
AnnaBridge 143:86740a56073b 1049 #define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
AnnaBridge 143:86740a56073b 1050 #define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
AnnaBridge 143:86740a56073b 1051
AnnaBridge 143:86740a56073b 1052 /* Register: CLOCK_LFCLKSRC */
AnnaBridge 143:86740a56073b 1053 /* Description: Clock source for the LFCLK clock. */
AnnaBridge 143:86740a56073b 1054
AnnaBridge 143:86740a56073b 1055 /* Bits 1..0 : Clock source. */
AnnaBridge 143:86740a56073b 1056 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
AnnaBridge 143:86740a56073b 1057 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
AnnaBridge 143:86740a56073b 1058 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
AnnaBridge 143:86740a56073b 1059 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
AnnaBridge 143:86740a56073b 1060 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
AnnaBridge 143:86740a56073b 1061
AnnaBridge 143:86740a56073b 1062 /* Register: CLOCK_CTIV */
AnnaBridge 143:86740a56073b 1063 /* Description: Calibration timer interval. */
AnnaBridge 143:86740a56073b 1064
AnnaBridge 143:86740a56073b 1065 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
AnnaBridge 143:86740a56073b 1066 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
AnnaBridge 143:86740a56073b 1067 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
AnnaBridge 143:86740a56073b 1068
AnnaBridge 143:86740a56073b 1069 /* Register: CLOCK_XTALFREQ */
AnnaBridge 143:86740a56073b 1070 /* Description: Crystal frequency. */
AnnaBridge 143:86740a56073b 1071
AnnaBridge 143:86740a56073b 1072 /* Bits 7..0 : External Xtal frequency selection. */
AnnaBridge 143:86740a56073b 1073 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
AnnaBridge 143:86740a56073b 1074 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
AnnaBridge 143:86740a56073b 1075 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
AnnaBridge 143:86740a56073b 1076 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
AnnaBridge 143:86740a56073b 1077
AnnaBridge 143:86740a56073b 1078
AnnaBridge 143:86740a56073b 1079 /* Peripheral: ECB */
AnnaBridge 143:86740a56073b 1080 /* Description: AES ECB Mode Encryption. */
AnnaBridge 143:86740a56073b 1081
AnnaBridge 143:86740a56073b 1082 /* Register: ECB_INTENSET */
AnnaBridge 143:86740a56073b 1083 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 1084
AnnaBridge 143:86740a56073b 1085 /* Bit 1 : Enable interrupt on ERRORECB event. */
AnnaBridge 143:86740a56073b 1086 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
AnnaBridge 143:86740a56073b 1087 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
AnnaBridge 143:86740a56073b 1088 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 1089 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 1090 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 1091
AnnaBridge 143:86740a56073b 1092 /* Bit 0 : Enable interrupt on ENDECB event. */
AnnaBridge 143:86740a56073b 1093 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
AnnaBridge 143:86740a56073b 1094 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
AnnaBridge 143:86740a56073b 1095 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 1096 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 1097 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 1098
AnnaBridge 143:86740a56073b 1099 /* Register: ECB_INTENCLR */
AnnaBridge 143:86740a56073b 1100 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 1101
AnnaBridge 143:86740a56073b 1102 /* Bit 1 : Disable interrupt on ERRORECB event. */
AnnaBridge 143:86740a56073b 1103 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
AnnaBridge 143:86740a56073b 1104 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
AnnaBridge 143:86740a56073b 1105 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 1106 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 1107 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 1108
AnnaBridge 143:86740a56073b 1109 /* Bit 0 : Disable interrupt on ENDECB event. */
AnnaBridge 143:86740a56073b 1110 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
AnnaBridge 143:86740a56073b 1111 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
AnnaBridge 143:86740a56073b 1112 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 1113 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 1114 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 1115
AnnaBridge 143:86740a56073b 1116 /* Register: ECB_POWER */
AnnaBridge 143:86740a56073b 1117 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 1118
AnnaBridge 143:86740a56073b 1119 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 1120 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 1121 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 1122 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 1123 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 1124
AnnaBridge 143:86740a56073b 1125
AnnaBridge 143:86740a56073b 1126 /* Peripheral: FICR */
AnnaBridge 143:86740a56073b 1127 /* Description: Factory Information Configuration. */
AnnaBridge 143:86740a56073b 1128
AnnaBridge 143:86740a56073b 1129 /* Register: FICR_PPFC */
AnnaBridge 143:86740a56073b 1130 /* Description: Pre-programmed factory code present. */
AnnaBridge 143:86740a56073b 1131
AnnaBridge 143:86740a56073b 1132 /* Bits 7..0 : Pre-programmed factory code present. */
AnnaBridge 143:86740a56073b 1133 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
AnnaBridge 143:86740a56073b 1134 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
AnnaBridge 143:86740a56073b 1135 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
AnnaBridge 143:86740a56073b 1136 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
AnnaBridge 143:86740a56073b 1137
AnnaBridge 143:86740a56073b 1138 /* Register: FICR_CONFIGID */
AnnaBridge 143:86740a56073b 1139 /* Description: Configuration identifier. */
AnnaBridge 143:86740a56073b 1140
AnnaBridge 143:86740a56073b 1141 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
AnnaBridge 143:86740a56073b 1142 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
AnnaBridge 143:86740a56073b 1143 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
AnnaBridge 143:86740a56073b 1144
AnnaBridge 143:86740a56073b 1145 /* Bits 15..0 : Hardware Identification Number. */
AnnaBridge 143:86740a56073b 1146 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
AnnaBridge 143:86740a56073b 1147 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
AnnaBridge 143:86740a56073b 1148
AnnaBridge 143:86740a56073b 1149 /* Register: FICR_DEVICEADDRTYPE */
AnnaBridge 143:86740a56073b 1150 /* Description: Device address type. */
AnnaBridge 143:86740a56073b 1151
AnnaBridge 143:86740a56073b 1152 /* Bit 0 : Device address type. */
AnnaBridge 143:86740a56073b 1153 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
AnnaBridge 143:86740a56073b 1154 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
AnnaBridge 143:86740a56073b 1155 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
AnnaBridge 143:86740a56073b 1156 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
AnnaBridge 143:86740a56073b 1157
AnnaBridge 143:86740a56073b 1158 /* Register: FICR_OVERRIDEEN */
AnnaBridge 143:86740a56073b 1159 /* Description: Radio calibration override enable. */
AnnaBridge 143:86740a56073b 1160
AnnaBridge 143:86740a56073b 1161 /* Bit 3 : Override default values for BLE_1Mbit mode. */
AnnaBridge 143:86740a56073b 1162 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
AnnaBridge 143:86740a56073b 1163 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
AnnaBridge 143:86740a56073b 1164 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
AnnaBridge 143:86740a56073b 1165 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
AnnaBridge 143:86740a56073b 1166
AnnaBridge 143:86740a56073b 1167 /* Bit 0 : Override default values for NRF_1Mbit mode. */
AnnaBridge 143:86740a56073b 1168 #define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
AnnaBridge 143:86740a56073b 1169 #define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
AnnaBridge 143:86740a56073b 1170 #define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
AnnaBridge 143:86740a56073b 1171 #define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
AnnaBridge 143:86740a56073b 1172
AnnaBridge 143:86740a56073b 1173
AnnaBridge 143:86740a56073b 1174 /* Peripheral: GPIO */
AnnaBridge 143:86740a56073b 1175 /* Description: General purpose input and output. */
AnnaBridge 143:86740a56073b 1176
AnnaBridge 143:86740a56073b 1177 /* Register: GPIO_OUT */
AnnaBridge 143:86740a56073b 1178 /* Description: Write GPIO port. */
AnnaBridge 143:86740a56073b 1179
AnnaBridge 143:86740a56073b 1180 /* Bit 31 : Pin 31. */
AnnaBridge 143:86740a56073b 1181 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 1182 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 1183 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1184 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1185
AnnaBridge 143:86740a56073b 1186 /* Bit 30 : Pin 30. */
AnnaBridge 143:86740a56073b 1187 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 1188 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 1189 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1190 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1191
AnnaBridge 143:86740a56073b 1192 /* Bit 29 : Pin 29. */
AnnaBridge 143:86740a56073b 1193 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 1194 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 1195 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1196 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1197
AnnaBridge 143:86740a56073b 1198 /* Bit 28 : Pin 28. */
AnnaBridge 143:86740a56073b 1199 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 1200 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 1201 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1202 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1203
AnnaBridge 143:86740a56073b 1204 /* Bit 27 : Pin 27. */
AnnaBridge 143:86740a56073b 1205 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 1206 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 1207 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1208 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1209
AnnaBridge 143:86740a56073b 1210 /* Bit 26 : Pin 26. */
AnnaBridge 143:86740a56073b 1211 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 1212 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 1213 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1214 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1215
AnnaBridge 143:86740a56073b 1216 /* Bit 25 : Pin 25. */
AnnaBridge 143:86740a56073b 1217 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 1218 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 1219 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1220 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1221
AnnaBridge 143:86740a56073b 1222 /* Bit 24 : Pin 24. */
AnnaBridge 143:86740a56073b 1223 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 1224 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 1225 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1226 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1227
AnnaBridge 143:86740a56073b 1228 /* Bit 23 : Pin 23. */
AnnaBridge 143:86740a56073b 1229 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 1230 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 1231 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1232 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1233
AnnaBridge 143:86740a56073b 1234 /* Bit 22 : Pin 22. */
AnnaBridge 143:86740a56073b 1235 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 1236 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 1237 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1238 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1239
AnnaBridge 143:86740a56073b 1240 /* Bit 21 : Pin 21. */
AnnaBridge 143:86740a56073b 1241 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 1242 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 1243 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1244 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1245
AnnaBridge 143:86740a56073b 1246 /* Bit 20 : Pin 20. */
AnnaBridge 143:86740a56073b 1247 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 1248 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 1249 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1250 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1251
AnnaBridge 143:86740a56073b 1252 /* Bit 19 : Pin 19. */
AnnaBridge 143:86740a56073b 1253 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 1254 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 1255 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1256 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1257
AnnaBridge 143:86740a56073b 1258 /* Bit 18 : Pin 18. */
AnnaBridge 143:86740a56073b 1259 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 1260 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 1261 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1262 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1263
AnnaBridge 143:86740a56073b 1264 /* Bit 17 : Pin 17. */
AnnaBridge 143:86740a56073b 1265 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 1266 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 1267 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1268 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1269
AnnaBridge 143:86740a56073b 1270 /* Bit 16 : Pin 16. */
AnnaBridge 143:86740a56073b 1271 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 1272 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 1273 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1274 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1275
AnnaBridge 143:86740a56073b 1276 /* Bit 15 : Pin 15. */
AnnaBridge 143:86740a56073b 1277 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 1278 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 1279 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1280 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1281
AnnaBridge 143:86740a56073b 1282 /* Bit 14 : Pin 14. */
AnnaBridge 143:86740a56073b 1283 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 1284 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 1285 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1286 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1287
AnnaBridge 143:86740a56073b 1288 /* Bit 13 : Pin 13. */
AnnaBridge 143:86740a56073b 1289 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 1290 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 1291 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1292 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1293
AnnaBridge 143:86740a56073b 1294 /* Bit 12 : Pin 12. */
AnnaBridge 143:86740a56073b 1295 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 1296 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 1297 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1298 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1299
AnnaBridge 143:86740a56073b 1300 /* Bit 11 : Pin 11. */
AnnaBridge 143:86740a56073b 1301 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 1302 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 1303 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1304 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1305
AnnaBridge 143:86740a56073b 1306 /* Bit 10 : Pin 10. */
AnnaBridge 143:86740a56073b 1307 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 1308 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 1309 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1310 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1311
AnnaBridge 143:86740a56073b 1312 /* Bit 9 : Pin 9. */
AnnaBridge 143:86740a56073b 1313 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 1314 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 1315 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1316 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1317
AnnaBridge 143:86740a56073b 1318 /* Bit 8 : Pin 8. */
AnnaBridge 143:86740a56073b 1319 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 1320 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 1321 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1322 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1323
AnnaBridge 143:86740a56073b 1324 /* Bit 7 : Pin 7. */
AnnaBridge 143:86740a56073b 1325 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 1326 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 1327 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1328 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1329
AnnaBridge 143:86740a56073b 1330 /* Bit 6 : Pin 6. */
AnnaBridge 143:86740a56073b 1331 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 1332 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 1333 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1334 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1335
AnnaBridge 143:86740a56073b 1336 /* Bit 5 : Pin 5. */
AnnaBridge 143:86740a56073b 1337 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 1338 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 1339 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1340 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1341
AnnaBridge 143:86740a56073b 1342 /* Bit 4 : Pin 4. */
AnnaBridge 143:86740a56073b 1343 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 1344 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 1345 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1346 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1347
AnnaBridge 143:86740a56073b 1348 /* Bit 3 : Pin 3. */
AnnaBridge 143:86740a56073b 1349 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 1350 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 1351 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1352 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1353
AnnaBridge 143:86740a56073b 1354 /* Bit 2 : Pin 2. */
AnnaBridge 143:86740a56073b 1355 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 1356 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 1357 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1358 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1359
AnnaBridge 143:86740a56073b 1360 /* Bit 1 : Pin 1. */
AnnaBridge 143:86740a56073b 1361 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 1362 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 1363 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1364 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1365
AnnaBridge 143:86740a56073b 1366 /* Bit 0 : Pin 0. */
AnnaBridge 143:86740a56073b 1367 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 1368 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 1369 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1370 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1371
AnnaBridge 143:86740a56073b 1372 /* Register: GPIO_OUTSET */
AnnaBridge 143:86740a56073b 1373 /* Description: Set individual bits in GPIO port. */
AnnaBridge 143:86740a56073b 1374
AnnaBridge 143:86740a56073b 1375 /* Bit 31 : Pin 31. */
AnnaBridge 143:86740a56073b 1376 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 1377 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 1378 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1379 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1380 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1381
AnnaBridge 143:86740a56073b 1382 /* Bit 30 : Pin 30. */
AnnaBridge 143:86740a56073b 1383 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 1384 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 1385 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1386 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1387 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1388
AnnaBridge 143:86740a56073b 1389 /* Bit 29 : Pin 29. */
AnnaBridge 143:86740a56073b 1390 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 1391 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 1392 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1393 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1394 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1395
AnnaBridge 143:86740a56073b 1396 /* Bit 28 : Pin 28. */
AnnaBridge 143:86740a56073b 1397 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 1398 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 1399 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1400 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1401 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1402
AnnaBridge 143:86740a56073b 1403 /* Bit 27 : Pin 27. */
AnnaBridge 143:86740a56073b 1404 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 1405 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 1406 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1407 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1408 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1409
AnnaBridge 143:86740a56073b 1410 /* Bit 26 : Pin 26. */
AnnaBridge 143:86740a56073b 1411 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 1412 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 1413 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1414 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1415 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1416
AnnaBridge 143:86740a56073b 1417 /* Bit 25 : Pin 25. */
AnnaBridge 143:86740a56073b 1418 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 1419 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 1420 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1421 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1422 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1423
AnnaBridge 143:86740a56073b 1424 /* Bit 24 : Pin 24. */
AnnaBridge 143:86740a56073b 1425 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 1426 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 1427 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1428 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1429 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1430
AnnaBridge 143:86740a56073b 1431 /* Bit 23 : Pin 23. */
AnnaBridge 143:86740a56073b 1432 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 1433 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 1434 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1435 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1436 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1437
AnnaBridge 143:86740a56073b 1438 /* Bit 22 : Pin 22. */
AnnaBridge 143:86740a56073b 1439 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 1440 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 1441 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1442 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1443 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1444
AnnaBridge 143:86740a56073b 1445 /* Bit 21 : Pin 21. */
AnnaBridge 143:86740a56073b 1446 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 1447 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 1448 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1449 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1450 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1451
AnnaBridge 143:86740a56073b 1452 /* Bit 20 : Pin 20. */
AnnaBridge 143:86740a56073b 1453 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 1454 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 1455 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1456 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1457 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1458
AnnaBridge 143:86740a56073b 1459 /* Bit 19 : Pin 19. */
AnnaBridge 143:86740a56073b 1460 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 1461 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 1462 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1463 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1464 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1465
AnnaBridge 143:86740a56073b 1466 /* Bit 18 : Pin 18. */
AnnaBridge 143:86740a56073b 1467 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 1468 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 1469 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1470 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1471 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1472
AnnaBridge 143:86740a56073b 1473 /* Bit 17 : Pin 17. */
AnnaBridge 143:86740a56073b 1474 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 1475 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 1476 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1477 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1478 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1479
AnnaBridge 143:86740a56073b 1480 /* Bit 16 : Pin 16. */
AnnaBridge 143:86740a56073b 1481 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 1482 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 1483 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1484 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1485 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1486
AnnaBridge 143:86740a56073b 1487 /* Bit 15 : Pin 15. */
AnnaBridge 143:86740a56073b 1488 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 1489 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 1490 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1491 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1492 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1493
AnnaBridge 143:86740a56073b 1494 /* Bit 14 : Pin 14. */
AnnaBridge 143:86740a56073b 1495 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 1496 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 1497 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1498 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1499 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1500
AnnaBridge 143:86740a56073b 1501 /* Bit 13 : Pin 13. */
AnnaBridge 143:86740a56073b 1502 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 1503 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 1504 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1505 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1506 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1507
AnnaBridge 143:86740a56073b 1508 /* Bit 12 : Pin 12. */
AnnaBridge 143:86740a56073b 1509 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 1510 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 1511 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1512 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1513 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1514
AnnaBridge 143:86740a56073b 1515 /* Bit 11 : Pin 11. */
AnnaBridge 143:86740a56073b 1516 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 1517 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 1518 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1519 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1520 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1521
AnnaBridge 143:86740a56073b 1522 /* Bit 10 : Pin 10. */
AnnaBridge 143:86740a56073b 1523 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 1524 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 1525 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1526 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1527 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1528
AnnaBridge 143:86740a56073b 1529 /* Bit 9 : Pin 9. */
AnnaBridge 143:86740a56073b 1530 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 1531 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 1532 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1533 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1534 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1535
AnnaBridge 143:86740a56073b 1536 /* Bit 8 : Pin 8. */
AnnaBridge 143:86740a56073b 1537 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 1538 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 1539 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1540 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1541 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1542
AnnaBridge 143:86740a56073b 1543 /* Bit 7 : Pin 7. */
AnnaBridge 143:86740a56073b 1544 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 1545 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 1546 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1547 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1548 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1549
AnnaBridge 143:86740a56073b 1550 /* Bit 6 : Pin 6. */
AnnaBridge 143:86740a56073b 1551 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 1552 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 1553 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1554 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1555 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1556
AnnaBridge 143:86740a56073b 1557 /* Bit 5 : Pin 5. */
AnnaBridge 143:86740a56073b 1558 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 1559 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 1560 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1561 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1562 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1563
AnnaBridge 143:86740a56073b 1564 /* Bit 4 : Pin 4. */
AnnaBridge 143:86740a56073b 1565 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 1566 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 1567 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1568 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1569 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1570
AnnaBridge 143:86740a56073b 1571 /* Bit 3 : Pin 3. */
AnnaBridge 143:86740a56073b 1572 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 1573 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 1574 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1575 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1576 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1577
AnnaBridge 143:86740a56073b 1578 /* Bit 2 : Pin 2. */
AnnaBridge 143:86740a56073b 1579 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 1580 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 1581 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1582 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1583 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1584
AnnaBridge 143:86740a56073b 1585 /* Bit 1 : Pin 1. */
AnnaBridge 143:86740a56073b 1586 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 1587 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 1588 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1589 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1590 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1591
AnnaBridge 143:86740a56073b 1592 /* Bit 0 : Pin 0. */
AnnaBridge 143:86740a56073b 1593 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 1594 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 1595 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1596 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1597 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
AnnaBridge 143:86740a56073b 1598
AnnaBridge 143:86740a56073b 1599 /* Register: GPIO_OUTCLR */
AnnaBridge 143:86740a56073b 1600 /* Description: Clear individual bits in GPIO port. */
AnnaBridge 143:86740a56073b 1601
AnnaBridge 143:86740a56073b 1602 /* Bit 31 : Pin 31. */
AnnaBridge 143:86740a56073b 1603 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 1604 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 1605 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1606 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1607 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1608
AnnaBridge 143:86740a56073b 1609 /* Bit 30 : Pin 30. */
AnnaBridge 143:86740a56073b 1610 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 1611 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 1612 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1613 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1614 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1615
AnnaBridge 143:86740a56073b 1616 /* Bit 29 : Pin 29. */
AnnaBridge 143:86740a56073b 1617 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 1618 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 1619 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1620 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1621 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1622
AnnaBridge 143:86740a56073b 1623 /* Bit 28 : Pin 28. */
AnnaBridge 143:86740a56073b 1624 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 1625 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 1626 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1627 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1628 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1629
AnnaBridge 143:86740a56073b 1630 /* Bit 27 : Pin 27. */
AnnaBridge 143:86740a56073b 1631 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 1632 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 1633 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1634 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1635 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1636
AnnaBridge 143:86740a56073b 1637 /* Bit 26 : Pin 26. */
AnnaBridge 143:86740a56073b 1638 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 1639 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 1640 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1641 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1642 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1643
AnnaBridge 143:86740a56073b 1644 /* Bit 25 : Pin 25. */
AnnaBridge 143:86740a56073b 1645 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 1646 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 1647 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1648 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1649 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1650
AnnaBridge 143:86740a56073b 1651 /* Bit 24 : Pin 24. */
AnnaBridge 143:86740a56073b 1652 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 1653 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 1654 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1655 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1656 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1657
AnnaBridge 143:86740a56073b 1658 /* Bit 23 : Pin 23. */
AnnaBridge 143:86740a56073b 1659 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 1660 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 1661 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1662 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1663 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1664
AnnaBridge 143:86740a56073b 1665 /* Bit 22 : Pin 22. */
AnnaBridge 143:86740a56073b 1666 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 1667 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 1668 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1669 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1670 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1671
AnnaBridge 143:86740a56073b 1672 /* Bit 21 : Pin 21. */
AnnaBridge 143:86740a56073b 1673 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 1674 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 1675 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1676 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1677 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1678
AnnaBridge 143:86740a56073b 1679 /* Bit 20 : Pin 20. */
AnnaBridge 143:86740a56073b 1680 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 1681 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 1682 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1683 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1684 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1685
AnnaBridge 143:86740a56073b 1686 /* Bit 19 : Pin 19. */
AnnaBridge 143:86740a56073b 1687 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 1688 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 1689 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1690 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1691 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1692
AnnaBridge 143:86740a56073b 1693 /* Bit 18 : Pin 18. */
AnnaBridge 143:86740a56073b 1694 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 1695 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 1696 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1697 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1698 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1699
AnnaBridge 143:86740a56073b 1700 /* Bit 17 : Pin 17. */
AnnaBridge 143:86740a56073b 1701 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 1702 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 1703 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1704 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1705 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1706
AnnaBridge 143:86740a56073b 1707 /* Bit 16 : Pin 16. */
AnnaBridge 143:86740a56073b 1708 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 1709 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 1710 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1711 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1712 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1713
AnnaBridge 143:86740a56073b 1714 /* Bit 15 : Pin 15. */
AnnaBridge 143:86740a56073b 1715 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 1716 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 1717 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1718 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1719 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1720
AnnaBridge 143:86740a56073b 1721 /* Bit 14 : Pin 14. */
AnnaBridge 143:86740a56073b 1722 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 1723 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 1724 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1725 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1726 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1727
AnnaBridge 143:86740a56073b 1728 /* Bit 13 : Pin 13. */
AnnaBridge 143:86740a56073b 1729 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 1730 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 1731 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1732 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1733 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1734
AnnaBridge 143:86740a56073b 1735 /* Bit 12 : Pin 12. */
AnnaBridge 143:86740a56073b 1736 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 1737 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 1738 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1739 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1740 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1741
AnnaBridge 143:86740a56073b 1742 /* Bit 11 : Pin 11. */
AnnaBridge 143:86740a56073b 1743 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 1744 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 1745 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1746 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1747 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1748
AnnaBridge 143:86740a56073b 1749 /* Bit 10 : Pin 10. */
AnnaBridge 143:86740a56073b 1750 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 1751 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 1752 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1753 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1754 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1755
AnnaBridge 143:86740a56073b 1756 /* Bit 9 : Pin 9. */
AnnaBridge 143:86740a56073b 1757 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 1758 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 1759 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1760 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1761 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1762
AnnaBridge 143:86740a56073b 1763 /* Bit 8 : Pin 8. */
AnnaBridge 143:86740a56073b 1764 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 1765 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 1766 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1767 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1768 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1769
AnnaBridge 143:86740a56073b 1770 /* Bit 7 : Pin 7. */
AnnaBridge 143:86740a56073b 1771 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 1772 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 1773 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1774 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1775 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1776
AnnaBridge 143:86740a56073b 1777 /* Bit 6 : Pin 6. */
AnnaBridge 143:86740a56073b 1778 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 1779 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 1780 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1781 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1782 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1783
AnnaBridge 143:86740a56073b 1784 /* Bit 5 : Pin 5. */
AnnaBridge 143:86740a56073b 1785 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 1786 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 1787 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1788 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1789 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1790
AnnaBridge 143:86740a56073b 1791 /* Bit 4 : Pin 4. */
AnnaBridge 143:86740a56073b 1792 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 1793 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 1794 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1795 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1796 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1797
AnnaBridge 143:86740a56073b 1798 /* Bit 3 : Pin 3. */
AnnaBridge 143:86740a56073b 1799 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 1800 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 1801 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1802 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1803 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1804
AnnaBridge 143:86740a56073b 1805 /* Bit 2 : Pin 2. */
AnnaBridge 143:86740a56073b 1806 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 1807 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 1808 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1809 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1810 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1811
AnnaBridge 143:86740a56073b 1812 /* Bit 1 : Pin 1. */
AnnaBridge 143:86740a56073b 1813 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 1814 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 1815 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1816 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1817 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1818
AnnaBridge 143:86740a56073b 1819 /* Bit 0 : Pin 0. */
AnnaBridge 143:86740a56073b 1820 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 1821 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 1822 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
AnnaBridge 143:86740a56073b 1823 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
AnnaBridge 143:86740a56073b 1824 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
AnnaBridge 143:86740a56073b 1825
AnnaBridge 143:86740a56073b 1826 /* Register: GPIO_IN */
AnnaBridge 143:86740a56073b 1827 /* Description: Read GPIO port. */
AnnaBridge 143:86740a56073b 1828
AnnaBridge 143:86740a56073b 1829 /* Bit 31 : Pin 31. */
AnnaBridge 143:86740a56073b 1830 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 1831 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 1832 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1833 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1834
AnnaBridge 143:86740a56073b 1835 /* Bit 30 : Pin 30. */
AnnaBridge 143:86740a56073b 1836 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 1837 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 1838 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1839 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1840
AnnaBridge 143:86740a56073b 1841 /* Bit 29 : Pin 29. */
AnnaBridge 143:86740a56073b 1842 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 1843 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 1844 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1845 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1846
AnnaBridge 143:86740a56073b 1847 /* Bit 28 : Pin 28. */
AnnaBridge 143:86740a56073b 1848 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 1849 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 1850 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1851 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1852
AnnaBridge 143:86740a56073b 1853 /* Bit 27 : Pin 27. */
AnnaBridge 143:86740a56073b 1854 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 1855 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 1856 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1857 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1858
AnnaBridge 143:86740a56073b 1859 /* Bit 26 : Pin 26. */
AnnaBridge 143:86740a56073b 1860 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 1861 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 1862 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1863 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1864
AnnaBridge 143:86740a56073b 1865 /* Bit 25 : Pin 25. */
AnnaBridge 143:86740a56073b 1866 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 1867 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 1868 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1869 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1870
AnnaBridge 143:86740a56073b 1871 /* Bit 24 : Pin 24. */
AnnaBridge 143:86740a56073b 1872 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 1873 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 1874 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1875 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1876
AnnaBridge 143:86740a56073b 1877 /* Bit 23 : Pin 23. */
AnnaBridge 143:86740a56073b 1878 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 1879 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 1880 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1881 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1882
AnnaBridge 143:86740a56073b 1883 /* Bit 22 : Pin 22. */
AnnaBridge 143:86740a56073b 1884 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 1885 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 1886 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1887 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1888
AnnaBridge 143:86740a56073b 1889 /* Bit 21 : Pin 21. */
AnnaBridge 143:86740a56073b 1890 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 1891 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 1892 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1893 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1894
AnnaBridge 143:86740a56073b 1895 /* Bit 20 : Pin 20. */
AnnaBridge 143:86740a56073b 1896 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 1897 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 1898 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1899 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1900
AnnaBridge 143:86740a56073b 1901 /* Bit 19 : Pin 19. */
AnnaBridge 143:86740a56073b 1902 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 1903 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 1904 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1905 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1906
AnnaBridge 143:86740a56073b 1907 /* Bit 18 : Pin 18. */
AnnaBridge 143:86740a56073b 1908 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 1909 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 1910 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1911 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1912
AnnaBridge 143:86740a56073b 1913 /* Bit 17 : Pin 17. */
AnnaBridge 143:86740a56073b 1914 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 1915 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 1916 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1917 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1918
AnnaBridge 143:86740a56073b 1919 /* Bit 16 : Pin 16. */
AnnaBridge 143:86740a56073b 1920 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 1921 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 1922 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1923 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1924
AnnaBridge 143:86740a56073b 1925 /* Bit 15 : Pin 15. */
AnnaBridge 143:86740a56073b 1926 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 1927 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 1928 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1929 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1930
AnnaBridge 143:86740a56073b 1931 /* Bit 14 : Pin 14. */
AnnaBridge 143:86740a56073b 1932 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 1933 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 1934 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1935 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1936
AnnaBridge 143:86740a56073b 1937 /* Bit 13 : Pin 13. */
AnnaBridge 143:86740a56073b 1938 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 1939 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 1940 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1941 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1942
AnnaBridge 143:86740a56073b 1943 /* Bit 12 : Pin 12. */
AnnaBridge 143:86740a56073b 1944 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 1945 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 1946 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1947 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1948
AnnaBridge 143:86740a56073b 1949 /* Bit 11 : Pin 11. */
AnnaBridge 143:86740a56073b 1950 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 1951 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 1952 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1953 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1954
AnnaBridge 143:86740a56073b 1955 /* Bit 10 : Pin 10. */
AnnaBridge 143:86740a56073b 1956 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 1957 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 1958 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1959 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1960
AnnaBridge 143:86740a56073b 1961 /* Bit 9 : Pin 9. */
AnnaBridge 143:86740a56073b 1962 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 1963 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 1964 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1965 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1966
AnnaBridge 143:86740a56073b 1967 /* Bit 8 : Pin 8. */
AnnaBridge 143:86740a56073b 1968 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 1969 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 1970 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1971 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1972
AnnaBridge 143:86740a56073b 1973 /* Bit 7 : Pin 7. */
AnnaBridge 143:86740a56073b 1974 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 1975 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 1976 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1977 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1978
AnnaBridge 143:86740a56073b 1979 /* Bit 6 : Pin 6. */
AnnaBridge 143:86740a56073b 1980 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 1981 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 1982 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1983 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1984
AnnaBridge 143:86740a56073b 1985 /* Bit 5 : Pin 5. */
AnnaBridge 143:86740a56073b 1986 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 1987 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 1988 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1989 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1990
AnnaBridge 143:86740a56073b 1991 /* Bit 4 : Pin 4. */
AnnaBridge 143:86740a56073b 1992 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 1993 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 1994 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 1995 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 1996
AnnaBridge 143:86740a56073b 1997 /* Bit 3 : Pin 3. */
AnnaBridge 143:86740a56073b 1998 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 1999 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 2000 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 2001 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 2002
AnnaBridge 143:86740a56073b 2003 /* Bit 2 : Pin 2. */
AnnaBridge 143:86740a56073b 2004 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 2005 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 2006 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 2007 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 2008
AnnaBridge 143:86740a56073b 2009 /* Bit 1 : Pin 1. */
AnnaBridge 143:86740a56073b 2010 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 2011 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 2012 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 2013 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 2014
AnnaBridge 143:86740a56073b 2015 /* Bit 0 : Pin 0. */
AnnaBridge 143:86740a56073b 2016 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 2017 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 2018 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
AnnaBridge 143:86740a56073b 2019 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
AnnaBridge 143:86740a56073b 2020
AnnaBridge 143:86740a56073b 2021 /* Register: GPIO_DIR */
AnnaBridge 143:86740a56073b 2022 /* Description: Direction of GPIO pins. */
AnnaBridge 143:86740a56073b 2023
AnnaBridge 143:86740a56073b 2024 /* Bit 31 : Pin 31. */
AnnaBridge 143:86740a56073b 2025 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 2026 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 2027 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2028 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2029
AnnaBridge 143:86740a56073b 2030 /* Bit 30 : Pin 30. */
AnnaBridge 143:86740a56073b 2031 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 2032 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 2033 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2034 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2035
AnnaBridge 143:86740a56073b 2036 /* Bit 29 : Pin 29. */
AnnaBridge 143:86740a56073b 2037 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 2038 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 2039 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2040 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2041
AnnaBridge 143:86740a56073b 2042 /* Bit 28 : Pin 28. */
AnnaBridge 143:86740a56073b 2043 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 2044 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 2045 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2046 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2047
AnnaBridge 143:86740a56073b 2048 /* Bit 27 : Pin 27. */
AnnaBridge 143:86740a56073b 2049 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 2050 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 2051 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2052 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2053
AnnaBridge 143:86740a56073b 2054 /* Bit 26 : Pin 26. */
AnnaBridge 143:86740a56073b 2055 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 2056 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 2057 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2058 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2059
AnnaBridge 143:86740a56073b 2060 /* Bit 25 : Pin 25. */
AnnaBridge 143:86740a56073b 2061 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 2062 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 2063 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2064 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2065
AnnaBridge 143:86740a56073b 2066 /* Bit 24 : Pin 24. */
AnnaBridge 143:86740a56073b 2067 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 2068 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 2069 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2070 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2071
AnnaBridge 143:86740a56073b 2072 /* Bit 23 : Pin 23. */
AnnaBridge 143:86740a56073b 2073 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 2074 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 2075 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2076 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2077
AnnaBridge 143:86740a56073b 2078 /* Bit 22 : Pin 22. */
AnnaBridge 143:86740a56073b 2079 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 2080 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 2081 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2082 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2083
AnnaBridge 143:86740a56073b 2084 /* Bit 21 : Pin 21. */
AnnaBridge 143:86740a56073b 2085 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 2086 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 2087 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2088 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2089
AnnaBridge 143:86740a56073b 2090 /* Bit 20 : Pin 20. */
AnnaBridge 143:86740a56073b 2091 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 2092 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 2093 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2094 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2095
AnnaBridge 143:86740a56073b 2096 /* Bit 19 : Pin 19. */
AnnaBridge 143:86740a56073b 2097 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 2098 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 2099 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2100 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2101
AnnaBridge 143:86740a56073b 2102 /* Bit 18 : Pin 18. */
AnnaBridge 143:86740a56073b 2103 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 2104 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 2105 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2106 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2107
AnnaBridge 143:86740a56073b 2108 /* Bit 17 : Pin 17. */
AnnaBridge 143:86740a56073b 2109 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 2110 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 2111 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2112 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2113
AnnaBridge 143:86740a56073b 2114 /* Bit 16 : Pin 16. */
AnnaBridge 143:86740a56073b 2115 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 2116 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 2117 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2118 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2119
AnnaBridge 143:86740a56073b 2120 /* Bit 15 : Pin 15. */
AnnaBridge 143:86740a56073b 2121 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 2122 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 2123 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2124 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2125
AnnaBridge 143:86740a56073b 2126 /* Bit 14 : Pin 14. */
AnnaBridge 143:86740a56073b 2127 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 2128 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 2129 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2130 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2131
AnnaBridge 143:86740a56073b 2132 /* Bit 13 : Pin 13. */
AnnaBridge 143:86740a56073b 2133 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 2134 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 2135 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2136 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2137
AnnaBridge 143:86740a56073b 2138 /* Bit 12 : Pin 12. */
AnnaBridge 143:86740a56073b 2139 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 2140 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 2141 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2142 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2143
AnnaBridge 143:86740a56073b 2144 /* Bit 11 : Pin 11. */
AnnaBridge 143:86740a56073b 2145 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 2146 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 2147 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2148 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2149
AnnaBridge 143:86740a56073b 2150 /* Bit 10 : Pin 10. */
AnnaBridge 143:86740a56073b 2151 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 2152 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 2153 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2154 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2155
AnnaBridge 143:86740a56073b 2156 /* Bit 9 : Pin 9. */
AnnaBridge 143:86740a56073b 2157 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 2158 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 2159 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2160 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2161
AnnaBridge 143:86740a56073b 2162 /* Bit 8 : Pin 8. */
AnnaBridge 143:86740a56073b 2163 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 2164 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 2165 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2166 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2167
AnnaBridge 143:86740a56073b 2168 /* Bit 7 : Pin 7. */
AnnaBridge 143:86740a56073b 2169 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 2170 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 2171 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2172 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2173
AnnaBridge 143:86740a56073b 2174 /* Bit 6 : Pin 6. */
AnnaBridge 143:86740a56073b 2175 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 2176 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 2177 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2178 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2179
AnnaBridge 143:86740a56073b 2180 /* Bit 5 : Pin 5. */
AnnaBridge 143:86740a56073b 2181 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 2182 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 2183 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2184 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2185
AnnaBridge 143:86740a56073b 2186 /* Bit 4 : Pin 4. */
AnnaBridge 143:86740a56073b 2187 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 2188 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 2189 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2190 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2191
AnnaBridge 143:86740a56073b 2192 /* Bit 3 : Pin 3. */
AnnaBridge 143:86740a56073b 2193 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 2194 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 2195 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2196 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2197
AnnaBridge 143:86740a56073b 2198 /* Bit 2 : Pin 2. */
AnnaBridge 143:86740a56073b 2199 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 2200 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 2201 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2202 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2203
AnnaBridge 143:86740a56073b 2204 /* Bit 1 : Pin 1. */
AnnaBridge 143:86740a56073b 2205 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 2206 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 2207 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2208 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2209
AnnaBridge 143:86740a56073b 2210 /* Bit 0 : Pin 0. */
AnnaBridge 143:86740a56073b 2211 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 2212 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 2213 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2214 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2215
AnnaBridge 143:86740a56073b 2216 /* Register: GPIO_DIRSET */
AnnaBridge 143:86740a56073b 2217 /* Description: DIR set register. */
AnnaBridge 143:86740a56073b 2218
AnnaBridge 143:86740a56073b 2219 /* Bit 31 : Set as output pin 31. */
AnnaBridge 143:86740a56073b 2220 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 2221 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 2222 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2223 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2224 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2225
AnnaBridge 143:86740a56073b 2226 /* Bit 30 : Set as output pin 30. */
AnnaBridge 143:86740a56073b 2227 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 2228 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 2229 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2230 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2231 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2232
AnnaBridge 143:86740a56073b 2233 /* Bit 29 : Set as output pin 29. */
AnnaBridge 143:86740a56073b 2234 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 2235 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 2236 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2237 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2238 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2239
AnnaBridge 143:86740a56073b 2240 /* Bit 28 : Set as output pin 28. */
AnnaBridge 143:86740a56073b 2241 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 2242 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 2243 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2244 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2245 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2246
AnnaBridge 143:86740a56073b 2247 /* Bit 27 : Set as output pin 27. */
AnnaBridge 143:86740a56073b 2248 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 2249 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 2250 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2251 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2252 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2253
AnnaBridge 143:86740a56073b 2254 /* Bit 26 : Set as output pin 26. */
AnnaBridge 143:86740a56073b 2255 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 2256 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 2257 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2258 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2259 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2260
AnnaBridge 143:86740a56073b 2261 /* Bit 25 : Set as output pin 25. */
AnnaBridge 143:86740a56073b 2262 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 2263 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 2264 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2265 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2266 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2267
AnnaBridge 143:86740a56073b 2268 /* Bit 24 : Set as output pin 24. */
AnnaBridge 143:86740a56073b 2269 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 2270 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 2271 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2272 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2273 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2274
AnnaBridge 143:86740a56073b 2275 /* Bit 23 : Set as output pin 23. */
AnnaBridge 143:86740a56073b 2276 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 2277 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 2278 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2279 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2280 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2281
AnnaBridge 143:86740a56073b 2282 /* Bit 22 : Set as output pin 22. */
AnnaBridge 143:86740a56073b 2283 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 2284 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 2285 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2286 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2287 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2288
AnnaBridge 143:86740a56073b 2289 /* Bit 21 : Set as output pin 21. */
AnnaBridge 143:86740a56073b 2290 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 2291 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 2292 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2293 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2294 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2295
AnnaBridge 143:86740a56073b 2296 /* Bit 20 : Set as output pin 20. */
AnnaBridge 143:86740a56073b 2297 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 2298 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 2299 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2300 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2301 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2302
AnnaBridge 143:86740a56073b 2303 /* Bit 19 : Set as output pin 19. */
AnnaBridge 143:86740a56073b 2304 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 2305 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 2306 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2307 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2308 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2309
AnnaBridge 143:86740a56073b 2310 /* Bit 18 : Set as output pin 18. */
AnnaBridge 143:86740a56073b 2311 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 2312 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 2313 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2314 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2315 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2316
AnnaBridge 143:86740a56073b 2317 /* Bit 17 : Set as output pin 17. */
AnnaBridge 143:86740a56073b 2318 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 2319 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 2320 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2321 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2322 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2323
AnnaBridge 143:86740a56073b 2324 /* Bit 16 : Set as output pin 16. */
AnnaBridge 143:86740a56073b 2325 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 2326 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 2327 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2328 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2329 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2330
AnnaBridge 143:86740a56073b 2331 /* Bit 15 : Set as output pin 15. */
AnnaBridge 143:86740a56073b 2332 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 2333 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 2334 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2335 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2336 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2337
AnnaBridge 143:86740a56073b 2338 /* Bit 14 : Set as output pin 14. */
AnnaBridge 143:86740a56073b 2339 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 2340 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 2341 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2342 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2343 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2344
AnnaBridge 143:86740a56073b 2345 /* Bit 13 : Set as output pin 13. */
AnnaBridge 143:86740a56073b 2346 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 2347 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 2348 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2349 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2350 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2351
AnnaBridge 143:86740a56073b 2352 /* Bit 12 : Set as output pin 12. */
AnnaBridge 143:86740a56073b 2353 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 2354 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 2355 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2356 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2357 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2358
AnnaBridge 143:86740a56073b 2359 /* Bit 11 : Set as output pin 11. */
AnnaBridge 143:86740a56073b 2360 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 2361 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 2362 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2363 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2364 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2365
AnnaBridge 143:86740a56073b 2366 /* Bit 10 : Set as output pin 10. */
AnnaBridge 143:86740a56073b 2367 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 2368 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 2369 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2370 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2371 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2372
AnnaBridge 143:86740a56073b 2373 /* Bit 9 : Set as output pin 9. */
AnnaBridge 143:86740a56073b 2374 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 2375 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 2376 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2377 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2378 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2379
AnnaBridge 143:86740a56073b 2380 /* Bit 8 : Set as output pin 8. */
AnnaBridge 143:86740a56073b 2381 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 2382 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 2383 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2384 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2385 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2386
AnnaBridge 143:86740a56073b 2387 /* Bit 7 : Set as output pin 7. */
AnnaBridge 143:86740a56073b 2388 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 2389 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 2390 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2391 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2392 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2393
AnnaBridge 143:86740a56073b 2394 /* Bit 6 : Set as output pin 6. */
AnnaBridge 143:86740a56073b 2395 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 2396 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 2397 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2398 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2399 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2400
AnnaBridge 143:86740a56073b 2401 /* Bit 5 : Set as output pin 5. */
AnnaBridge 143:86740a56073b 2402 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 2403 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 2404 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2405 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2406 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2407
AnnaBridge 143:86740a56073b 2408 /* Bit 4 : Set as output pin 4. */
AnnaBridge 143:86740a56073b 2409 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 2410 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 2411 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2412 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2413 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2414
AnnaBridge 143:86740a56073b 2415 /* Bit 3 : Set as output pin 3. */
AnnaBridge 143:86740a56073b 2416 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 2417 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 2418 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2419 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2420 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2421
AnnaBridge 143:86740a56073b 2422 /* Bit 2 : Set as output pin 2. */
AnnaBridge 143:86740a56073b 2423 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 2424 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 2425 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2426 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2427 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2428
AnnaBridge 143:86740a56073b 2429 /* Bit 1 : Set as output pin 1. */
AnnaBridge 143:86740a56073b 2430 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 2431 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 2432 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2433 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2434 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2435
AnnaBridge 143:86740a56073b 2436 /* Bit 0 : Set as output pin 0. */
AnnaBridge 143:86740a56073b 2437 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 2438 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 2439 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2440 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2441 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
AnnaBridge 143:86740a56073b 2442
AnnaBridge 143:86740a56073b 2443 /* Register: GPIO_DIRCLR */
AnnaBridge 143:86740a56073b 2444 /* Description: DIR clear register. */
AnnaBridge 143:86740a56073b 2445
AnnaBridge 143:86740a56073b 2446 /* Bit 31 : Set as input pin 31. */
AnnaBridge 143:86740a56073b 2447 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
AnnaBridge 143:86740a56073b 2448 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
AnnaBridge 143:86740a56073b 2449 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2450 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2451 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2452
AnnaBridge 143:86740a56073b 2453 /* Bit 30 : Set as input pin 30. */
AnnaBridge 143:86740a56073b 2454 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
AnnaBridge 143:86740a56073b 2455 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
AnnaBridge 143:86740a56073b 2456 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2457 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2458 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2459
AnnaBridge 143:86740a56073b 2460 /* Bit 29 : Set as input pin 29. */
AnnaBridge 143:86740a56073b 2461 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
AnnaBridge 143:86740a56073b 2462 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
AnnaBridge 143:86740a56073b 2463 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2464 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2465 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2466
AnnaBridge 143:86740a56073b 2467 /* Bit 28 : Set as input pin 28. */
AnnaBridge 143:86740a56073b 2468 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
AnnaBridge 143:86740a56073b 2469 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
AnnaBridge 143:86740a56073b 2470 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2471 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2472 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2473
AnnaBridge 143:86740a56073b 2474 /* Bit 27 : Set as input pin 27. */
AnnaBridge 143:86740a56073b 2475 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
AnnaBridge 143:86740a56073b 2476 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
AnnaBridge 143:86740a56073b 2477 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2478 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2479 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2480
AnnaBridge 143:86740a56073b 2481 /* Bit 26 : Set as input pin 26. */
AnnaBridge 143:86740a56073b 2482 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
AnnaBridge 143:86740a56073b 2483 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
AnnaBridge 143:86740a56073b 2484 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2485 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2486 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2487
AnnaBridge 143:86740a56073b 2488 /* Bit 25 : Set as input pin 25. */
AnnaBridge 143:86740a56073b 2489 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
AnnaBridge 143:86740a56073b 2490 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
AnnaBridge 143:86740a56073b 2491 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2492 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2493 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2494
AnnaBridge 143:86740a56073b 2495 /* Bit 24 : Set as input pin 24. */
AnnaBridge 143:86740a56073b 2496 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
AnnaBridge 143:86740a56073b 2497 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
AnnaBridge 143:86740a56073b 2498 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2499 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2500 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2501
AnnaBridge 143:86740a56073b 2502 /* Bit 23 : Set as input pin 23. */
AnnaBridge 143:86740a56073b 2503 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
AnnaBridge 143:86740a56073b 2504 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
AnnaBridge 143:86740a56073b 2505 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2506 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2507 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2508
AnnaBridge 143:86740a56073b 2509 /* Bit 22 : Set as input pin 22. */
AnnaBridge 143:86740a56073b 2510 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
AnnaBridge 143:86740a56073b 2511 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
AnnaBridge 143:86740a56073b 2512 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2513 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2514 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2515
AnnaBridge 143:86740a56073b 2516 /* Bit 21 : Set as input pin 21. */
AnnaBridge 143:86740a56073b 2517 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
AnnaBridge 143:86740a56073b 2518 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
AnnaBridge 143:86740a56073b 2519 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2520 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2521 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2522
AnnaBridge 143:86740a56073b 2523 /* Bit 20 : Set as input pin 20. */
AnnaBridge 143:86740a56073b 2524 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
AnnaBridge 143:86740a56073b 2525 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
AnnaBridge 143:86740a56073b 2526 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2527 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2528 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2529
AnnaBridge 143:86740a56073b 2530 /* Bit 19 : Set as input pin 19. */
AnnaBridge 143:86740a56073b 2531 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
AnnaBridge 143:86740a56073b 2532 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
AnnaBridge 143:86740a56073b 2533 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2534 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2535 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2536
AnnaBridge 143:86740a56073b 2537 /* Bit 18 : Set as input pin 18. */
AnnaBridge 143:86740a56073b 2538 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
AnnaBridge 143:86740a56073b 2539 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
AnnaBridge 143:86740a56073b 2540 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2541 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2542 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2543
AnnaBridge 143:86740a56073b 2544 /* Bit 17 : Set as input pin 17. */
AnnaBridge 143:86740a56073b 2545 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
AnnaBridge 143:86740a56073b 2546 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
AnnaBridge 143:86740a56073b 2547 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2548 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2549 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2550
AnnaBridge 143:86740a56073b 2551 /* Bit 16 : Set as input pin 16. */
AnnaBridge 143:86740a56073b 2552 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
AnnaBridge 143:86740a56073b 2553 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
AnnaBridge 143:86740a56073b 2554 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2555 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2556 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2557
AnnaBridge 143:86740a56073b 2558 /* Bit 15 : Set as input pin 15. */
AnnaBridge 143:86740a56073b 2559 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
AnnaBridge 143:86740a56073b 2560 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
AnnaBridge 143:86740a56073b 2561 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2562 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2563 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2564
AnnaBridge 143:86740a56073b 2565 /* Bit 14 : Set as input pin 14. */
AnnaBridge 143:86740a56073b 2566 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
AnnaBridge 143:86740a56073b 2567 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
AnnaBridge 143:86740a56073b 2568 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2569 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2570 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2571
AnnaBridge 143:86740a56073b 2572 /* Bit 13 : Set as input pin 13. */
AnnaBridge 143:86740a56073b 2573 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
AnnaBridge 143:86740a56073b 2574 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
AnnaBridge 143:86740a56073b 2575 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2576 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2577 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2578
AnnaBridge 143:86740a56073b 2579 /* Bit 12 : Set as input pin 12. */
AnnaBridge 143:86740a56073b 2580 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
AnnaBridge 143:86740a56073b 2581 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
AnnaBridge 143:86740a56073b 2582 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2583 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2584 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2585
AnnaBridge 143:86740a56073b 2586 /* Bit 11 : Set as input pin 11. */
AnnaBridge 143:86740a56073b 2587 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
AnnaBridge 143:86740a56073b 2588 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
AnnaBridge 143:86740a56073b 2589 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2590 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2591 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2592
AnnaBridge 143:86740a56073b 2593 /* Bit 10 : Set as input pin 10. */
AnnaBridge 143:86740a56073b 2594 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
AnnaBridge 143:86740a56073b 2595 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
AnnaBridge 143:86740a56073b 2596 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2597 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2598 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2599
AnnaBridge 143:86740a56073b 2600 /* Bit 9 : Set as input pin 9. */
AnnaBridge 143:86740a56073b 2601 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
AnnaBridge 143:86740a56073b 2602 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
AnnaBridge 143:86740a56073b 2603 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2604 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2605 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2606
AnnaBridge 143:86740a56073b 2607 /* Bit 8 : Set as input pin 8. */
AnnaBridge 143:86740a56073b 2608 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
AnnaBridge 143:86740a56073b 2609 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
AnnaBridge 143:86740a56073b 2610 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2611 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2612 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2613
AnnaBridge 143:86740a56073b 2614 /* Bit 7 : Set as input pin 7. */
AnnaBridge 143:86740a56073b 2615 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
AnnaBridge 143:86740a56073b 2616 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
AnnaBridge 143:86740a56073b 2617 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2618 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2619 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2620
AnnaBridge 143:86740a56073b 2621 /* Bit 6 : Set as input pin 6. */
AnnaBridge 143:86740a56073b 2622 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
AnnaBridge 143:86740a56073b 2623 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
AnnaBridge 143:86740a56073b 2624 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2625 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2626 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2627
AnnaBridge 143:86740a56073b 2628 /* Bit 5 : Set as input pin 5. */
AnnaBridge 143:86740a56073b 2629 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
AnnaBridge 143:86740a56073b 2630 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
AnnaBridge 143:86740a56073b 2631 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2632 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2633 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2634
AnnaBridge 143:86740a56073b 2635 /* Bit 4 : Set as input pin 4. */
AnnaBridge 143:86740a56073b 2636 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
AnnaBridge 143:86740a56073b 2637 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
AnnaBridge 143:86740a56073b 2638 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2639 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2640 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2641
AnnaBridge 143:86740a56073b 2642 /* Bit 3 : Set as input pin 3. */
AnnaBridge 143:86740a56073b 2643 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
AnnaBridge 143:86740a56073b 2644 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
AnnaBridge 143:86740a56073b 2645 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2646 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2647 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2648
AnnaBridge 143:86740a56073b 2649 /* Bit 2 : Set as input pin 2. */
AnnaBridge 143:86740a56073b 2650 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
AnnaBridge 143:86740a56073b 2651 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
AnnaBridge 143:86740a56073b 2652 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2653 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2654 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2655
AnnaBridge 143:86740a56073b 2656 /* Bit 1 : Set as input pin 1. */
AnnaBridge 143:86740a56073b 2657 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
AnnaBridge 143:86740a56073b 2658 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
AnnaBridge 143:86740a56073b 2659 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2660 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2661 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2662
AnnaBridge 143:86740a56073b 2663 /* Bit 0 : Set as input pin 0. */
AnnaBridge 143:86740a56073b 2664 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
AnnaBridge 143:86740a56073b 2665 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
AnnaBridge 143:86740a56073b 2666 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
AnnaBridge 143:86740a56073b 2667 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
AnnaBridge 143:86740a56073b 2668 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
AnnaBridge 143:86740a56073b 2669
AnnaBridge 143:86740a56073b 2670 /* Register: GPIO_PIN_CNF */
AnnaBridge 143:86740a56073b 2671 /* Description: Configuration of GPIO pins. */
AnnaBridge 143:86740a56073b 2672
AnnaBridge 143:86740a56073b 2673 /* Bits 17..16 : Pin sensing mechanism. */
AnnaBridge 143:86740a56073b 2674 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
AnnaBridge 143:86740a56073b 2675 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
AnnaBridge 143:86740a56073b 2676 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 2677 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
AnnaBridge 143:86740a56073b 2678 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
AnnaBridge 143:86740a56073b 2679
AnnaBridge 143:86740a56073b 2680 /* Bits 10..8 : Drive configuration. */
AnnaBridge 143:86740a56073b 2681 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
AnnaBridge 143:86740a56073b 2682 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
AnnaBridge 143:86740a56073b 2683 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
AnnaBridge 143:86740a56073b 2684 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
AnnaBridge 143:86740a56073b 2685 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
AnnaBridge 143:86740a56073b 2686 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
AnnaBridge 143:86740a56073b 2687 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
AnnaBridge 143:86740a56073b 2688 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
AnnaBridge 143:86740a56073b 2689 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
AnnaBridge 143:86740a56073b 2690 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
AnnaBridge 143:86740a56073b 2691
AnnaBridge 143:86740a56073b 2692 /* Bits 3..2 : Pull-up or -down configuration. */
AnnaBridge 143:86740a56073b 2693 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
AnnaBridge 143:86740a56073b 2694 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
AnnaBridge 143:86740a56073b 2695 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
AnnaBridge 143:86740a56073b 2696 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
AnnaBridge 143:86740a56073b 2697 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
AnnaBridge 143:86740a56073b 2698
AnnaBridge 143:86740a56073b 2699 /* Bit 1 : Connect or disconnect input path. */
AnnaBridge 143:86740a56073b 2700 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
AnnaBridge 143:86740a56073b 2701 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
AnnaBridge 143:86740a56073b 2702 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
AnnaBridge 143:86740a56073b 2703 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
AnnaBridge 143:86740a56073b 2704
AnnaBridge 143:86740a56073b 2705 /* Bit 0 : Pin direction. */
AnnaBridge 143:86740a56073b 2706 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
AnnaBridge 143:86740a56073b 2707 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
AnnaBridge 143:86740a56073b 2708 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
AnnaBridge 143:86740a56073b 2709 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
AnnaBridge 143:86740a56073b 2710
AnnaBridge 143:86740a56073b 2711
AnnaBridge 143:86740a56073b 2712 /* Peripheral: GPIOTE */
AnnaBridge 143:86740a56073b 2713 /* Description: GPIO tasks and events. */
AnnaBridge 143:86740a56073b 2714
AnnaBridge 143:86740a56073b 2715 /* Register: GPIOTE_INTENSET */
AnnaBridge 143:86740a56073b 2716 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 2717
AnnaBridge 143:86740a56073b 2718 /* Bit 31 : Enable interrupt on PORT event. */
AnnaBridge 143:86740a56073b 2719 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
AnnaBridge 143:86740a56073b 2720 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
AnnaBridge 143:86740a56073b 2721 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2722 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2723 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2724
AnnaBridge 143:86740a56073b 2725 /* Bit 3 : Enable interrupt on IN[3] event. */
AnnaBridge 143:86740a56073b 2726 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
AnnaBridge 143:86740a56073b 2727 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
AnnaBridge 143:86740a56073b 2728 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2729 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2730 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2731
AnnaBridge 143:86740a56073b 2732 /* Bit 2 : Enable interrupt on IN[2] event. */
AnnaBridge 143:86740a56073b 2733 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
AnnaBridge 143:86740a56073b 2734 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
AnnaBridge 143:86740a56073b 2735 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2736 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2737 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2738
AnnaBridge 143:86740a56073b 2739 /* Bit 1 : Enable interrupt on IN[1] event. */
AnnaBridge 143:86740a56073b 2740 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
AnnaBridge 143:86740a56073b 2741 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
AnnaBridge 143:86740a56073b 2742 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2743 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2744 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2745
AnnaBridge 143:86740a56073b 2746 /* Bit 0 : Enable interrupt on IN[0] event. */
AnnaBridge 143:86740a56073b 2747 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
AnnaBridge 143:86740a56073b 2748 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
AnnaBridge 143:86740a56073b 2749 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2750 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2751 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2752
AnnaBridge 143:86740a56073b 2753 /* Register: GPIOTE_INTENCLR */
AnnaBridge 143:86740a56073b 2754 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 2755
AnnaBridge 143:86740a56073b 2756 /* Bit 31 : Disable interrupt on PORT event. */
AnnaBridge 143:86740a56073b 2757 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
AnnaBridge 143:86740a56073b 2758 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
AnnaBridge 143:86740a56073b 2759 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2760 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2761 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2762
AnnaBridge 143:86740a56073b 2763 /* Bit 3 : Disable interrupt on IN[3] event. */
AnnaBridge 143:86740a56073b 2764 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
AnnaBridge 143:86740a56073b 2765 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
AnnaBridge 143:86740a56073b 2766 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2767 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2768 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2769
AnnaBridge 143:86740a56073b 2770 /* Bit 2 : Disable interrupt on IN[2] event. */
AnnaBridge 143:86740a56073b 2771 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
AnnaBridge 143:86740a56073b 2772 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
AnnaBridge 143:86740a56073b 2773 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2774 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2775 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2776
AnnaBridge 143:86740a56073b 2777 /* Bit 1 : Disable interrupt on IN[1] event. */
AnnaBridge 143:86740a56073b 2778 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
AnnaBridge 143:86740a56073b 2779 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
AnnaBridge 143:86740a56073b 2780 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2781 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2782 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2783
AnnaBridge 143:86740a56073b 2784 /* Bit 0 : Disable interrupt on IN[0] event. */
AnnaBridge 143:86740a56073b 2785 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
AnnaBridge 143:86740a56073b 2786 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
AnnaBridge 143:86740a56073b 2787 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2788 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2789 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2790
AnnaBridge 143:86740a56073b 2791 /* Register: GPIOTE_CONFIG */
AnnaBridge 143:86740a56073b 2792 /* Description: Channel configuration registers. */
AnnaBridge 143:86740a56073b 2793
AnnaBridge 143:86740a56073b 2794 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
AnnaBridge 143:86740a56073b 2795 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
AnnaBridge 143:86740a56073b 2796 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
AnnaBridge 143:86740a56073b 2797 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
AnnaBridge 143:86740a56073b 2798 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
AnnaBridge 143:86740a56073b 2799
AnnaBridge 143:86740a56073b 2800 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
AnnaBridge 143:86740a56073b 2801 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
AnnaBridge 143:86740a56073b 2802 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
AnnaBridge 143:86740a56073b 2803 #define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
AnnaBridge 143:86740a56073b 2804 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
AnnaBridge 143:86740a56073b 2805 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
AnnaBridge 143:86740a56073b 2806 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
AnnaBridge 143:86740a56073b 2807
AnnaBridge 143:86740a56073b 2808 /* Bits 12..8 : Pin select. */
AnnaBridge 143:86740a56073b 2809 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
AnnaBridge 143:86740a56073b 2810 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
AnnaBridge 143:86740a56073b 2811
AnnaBridge 143:86740a56073b 2812 /* Bits 1..0 : Mode */
AnnaBridge 143:86740a56073b 2813 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 2814 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 2815 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 2816 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
AnnaBridge 143:86740a56073b 2817 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
AnnaBridge 143:86740a56073b 2818
AnnaBridge 143:86740a56073b 2819 /* Register: GPIOTE_POWER */
AnnaBridge 143:86740a56073b 2820 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 2821
AnnaBridge 143:86740a56073b 2822 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 2823 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 2824 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 2825 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 2826 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 2827
AnnaBridge 143:86740a56073b 2828
AnnaBridge 143:86740a56073b 2829 /* Peripheral: LPCOMP */
AnnaBridge 143:86740a56073b 2830 /* Description: Low power comparator. */
AnnaBridge 143:86740a56073b 2831
AnnaBridge 143:86740a56073b 2832 /* Register: LPCOMP_SHORTS */
AnnaBridge 143:86740a56073b 2833 /* Description: Shortcuts for the LPCOMP. */
AnnaBridge 143:86740a56073b 2834
AnnaBridge 143:86740a56073b 2835 /* Bit 4 : Shortcut between CROSS event and STOP task. */
AnnaBridge 143:86740a56073b 2836 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
AnnaBridge 143:86740a56073b 2837 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
AnnaBridge 143:86740a56073b 2838 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 2839 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 2840
AnnaBridge 143:86740a56073b 2841 /* Bit 3 : Shortcut between UP event and STOP task. */
AnnaBridge 143:86740a56073b 2842 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
AnnaBridge 143:86740a56073b 2843 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
AnnaBridge 143:86740a56073b 2844 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 2845 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 2846
AnnaBridge 143:86740a56073b 2847 /* Bit 2 : Shortcut between DOWN event and STOP task. */
AnnaBridge 143:86740a56073b 2848 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
AnnaBridge 143:86740a56073b 2849 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
AnnaBridge 143:86740a56073b 2850 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 2851 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 2852
AnnaBridge 143:86740a56073b 2853 /* Bit 1 : Shortcut between RADY event and STOP task. */
AnnaBridge 143:86740a56073b 2854 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
AnnaBridge 143:86740a56073b 2855 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
AnnaBridge 143:86740a56073b 2856 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 2857 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 2858
AnnaBridge 143:86740a56073b 2859 /* Bit 0 : Shortcut between READY event and SAMPLE task. */
AnnaBridge 143:86740a56073b 2860 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
AnnaBridge 143:86740a56073b 2861 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
AnnaBridge 143:86740a56073b 2862 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 2863 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 2864
AnnaBridge 143:86740a56073b 2865 /* Register: LPCOMP_INTENSET */
AnnaBridge 143:86740a56073b 2866 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 2867
AnnaBridge 143:86740a56073b 2868 /* Bit 3 : Enable interrupt on CROSS event. */
AnnaBridge 143:86740a56073b 2869 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 2870 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 2871 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2872 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2873 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2874
AnnaBridge 143:86740a56073b 2875 /* Bit 2 : Enable interrupt on UP event. */
AnnaBridge 143:86740a56073b 2876 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 2877 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 2878 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2879 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2880 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2881
AnnaBridge 143:86740a56073b 2882 /* Bit 1 : Enable interrupt on DOWN event. */
AnnaBridge 143:86740a56073b 2883 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 2884 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 2885 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2886 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2887 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2888
AnnaBridge 143:86740a56073b 2889 /* Bit 0 : Enable interrupt on READY event. */
AnnaBridge 143:86740a56073b 2890 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 2891 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 2892 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2893 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2894 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 2895
AnnaBridge 143:86740a56073b 2896 /* Register: LPCOMP_INTENCLR */
AnnaBridge 143:86740a56073b 2897 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 2898
AnnaBridge 143:86740a56073b 2899 /* Bit 3 : Disable interrupt on CROSS event. */
AnnaBridge 143:86740a56073b 2900 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
AnnaBridge 143:86740a56073b 2901 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
AnnaBridge 143:86740a56073b 2902 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2903 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2904 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2905
AnnaBridge 143:86740a56073b 2906 /* Bit 2 : Disable interrupt on UP event. */
AnnaBridge 143:86740a56073b 2907 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
AnnaBridge 143:86740a56073b 2908 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
AnnaBridge 143:86740a56073b 2909 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2910 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2911 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2912
AnnaBridge 143:86740a56073b 2913 /* Bit 1 : Disable interrupt on DOWN event. */
AnnaBridge 143:86740a56073b 2914 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
AnnaBridge 143:86740a56073b 2915 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
AnnaBridge 143:86740a56073b 2916 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2917 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2918 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2919
AnnaBridge 143:86740a56073b 2920 /* Bit 0 : Disable interrupt on READY event. */
AnnaBridge 143:86740a56073b 2921 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 2922 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 2923 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 2924 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 2925 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 2926
AnnaBridge 143:86740a56073b 2927 /* Register: LPCOMP_RESULT */
AnnaBridge 143:86740a56073b 2928 /* Description: Result of last compare. */
AnnaBridge 143:86740a56073b 2929
AnnaBridge 143:86740a56073b 2930 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
AnnaBridge 143:86740a56073b 2931 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
AnnaBridge 143:86740a56073b 2932 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
AnnaBridge 143:86740a56073b 2933 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
AnnaBridge 143:86740a56073b 2934 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
AnnaBridge 143:86740a56073b 2935
AnnaBridge 143:86740a56073b 2936 /* Register: LPCOMP_ENABLE */
AnnaBridge 143:86740a56073b 2937 /* Description: Enable the LPCOMP. */
AnnaBridge 143:86740a56073b 2938
AnnaBridge 143:86740a56073b 2939 /* Bits 1..0 : Enable or disable LPCOMP. */
AnnaBridge 143:86740a56073b 2940 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 2941 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 2942 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
AnnaBridge 143:86740a56073b 2943 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
AnnaBridge 143:86740a56073b 2944
AnnaBridge 143:86740a56073b 2945 /* Register: LPCOMP_PSEL */
AnnaBridge 143:86740a56073b 2946 /* Description: Input pin select. */
AnnaBridge 143:86740a56073b 2947
AnnaBridge 143:86740a56073b 2948 /* Bits 2..0 : Analog input pin select. */
AnnaBridge 143:86740a56073b 2949 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
AnnaBridge 143:86740a56073b 2950 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
AnnaBridge 143:86740a56073b 2951 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
AnnaBridge 143:86740a56073b 2952 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
AnnaBridge 143:86740a56073b 2953 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
AnnaBridge 143:86740a56073b 2954 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
AnnaBridge 143:86740a56073b 2955 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
AnnaBridge 143:86740a56073b 2956 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
AnnaBridge 143:86740a56073b 2957 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
AnnaBridge 143:86740a56073b 2958 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
AnnaBridge 143:86740a56073b 2959
AnnaBridge 143:86740a56073b 2960 /* Register: LPCOMP_REFSEL */
AnnaBridge 143:86740a56073b 2961 /* Description: Reference select. */
AnnaBridge 143:86740a56073b 2962
AnnaBridge 143:86740a56073b 2963 /* Bits 2..0 : Reference select. */
AnnaBridge 143:86740a56073b 2964 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
AnnaBridge 143:86740a56073b 2965 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
AnnaBridge 143:86740a56073b 2966 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2967 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2968 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2969 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2970 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2971 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2972 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
AnnaBridge 143:86740a56073b 2973 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
AnnaBridge 143:86740a56073b 2974
AnnaBridge 143:86740a56073b 2975 /* Register: LPCOMP_EXTREFSEL */
AnnaBridge 143:86740a56073b 2976 /* Description: External reference select. */
AnnaBridge 143:86740a56073b 2977
AnnaBridge 143:86740a56073b 2978 /* Bit 0 : External analog reference pin selection. */
AnnaBridge 143:86740a56073b 2979 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 2980 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
AnnaBridge 143:86740a56073b 2981 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
AnnaBridge 143:86740a56073b 2982 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
AnnaBridge 143:86740a56073b 2983
AnnaBridge 143:86740a56073b 2984 /* Register: LPCOMP_ANADETECT */
AnnaBridge 143:86740a56073b 2985 /* Description: Analog detect configuration. */
AnnaBridge 143:86740a56073b 2986
AnnaBridge 143:86740a56073b 2987 /* Bits 1..0 : Analog detect configuration. */
AnnaBridge 143:86740a56073b 2988 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
AnnaBridge 143:86740a56073b 2989 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
AnnaBridge 143:86740a56073b 2990 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
AnnaBridge 143:86740a56073b 2991 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
AnnaBridge 143:86740a56073b 2992 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
AnnaBridge 143:86740a56073b 2993
AnnaBridge 143:86740a56073b 2994 /* Register: LPCOMP_POWER */
AnnaBridge 143:86740a56073b 2995 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 2996
AnnaBridge 143:86740a56073b 2997 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 2998 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 2999 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 3000 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 3001 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 3002
AnnaBridge 143:86740a56073b 3003
AnnaBridge 143:86740a56073b 3004 /* Peripheral: MPU */
AnnaBridge 143:86740a56073b 3005 /* Description: Memory Protection Unit. */
AnnaBridge 143:86740a56073b 3006
AnnaBridge 143:86740a56073b 3007 /* Register: MPU_PERR0 */
AnnaBridge 143:86740a56073b 3008 /* Description: Configuration of peripherals in mpu regions. */
AnnaBridge 143:86740a56073b 3009
AnnaBridge 143:86740a56073b 3010 /* Bit 31 : PPI region configuration. */
AnnaBridge 143:86740a56073b 3011 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
AnnaBridge 143:86740a56073b 3012 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
AnnaBridge 143:86740a56073b 3013 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3014 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3015
AnnaBridge 143:86740a56073b 3016 /* Bit 30 : NVMC region configuration. */
AnnaBridge 143:86740a56073b 3017 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
AnnaBridge 143:86740a56073b 3018 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
AnnaBridge 143:86740a56073b 3019 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3020 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3021
AnnaBridge 143:86740a56073b 3022 /* Bit 19 : LPCOMP region configuration. */
AnnaBridge 143:86740a56073b 3023 #define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
AnnaBridge 143:86740a56073b 3024 #define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
AnnaBridge 143:86740a56073b 3025 #define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3026 #define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3027
AnnaBridge 143:86740a56073b 3028 /* Bit 18 : QDEC region configuration. */
AnnaBridge 143:86740a56073b 3029 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
AnnaBridge 143:86740a56073b 3030 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
AnnaBridge 143:86740a56073b 3031 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3032 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3033
AnnaBridge 143:86740a56073b 3034 /* Bit 17 : RTC1 region configuration. */
AnnaBridge 143:86740a56073b 3035 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
AnnaBridge 143:86740a56073b 3036 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
AnnaBridge 143:86740a56073b 3037 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3038 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3039
AnnaBridge 143:86740a56073b 3040 /* Bit 16 : WDT region configuration. */
AnnaBridge 143:86740a56073b 3041 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
AnnaBridge 143:86740a56073b 3042 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
AnnaBridge 143:86740a56073b 3043 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3044 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3045
AnnaBridge 143:86740a56073b 3046 /* Bit 15 : CCM and AAR region configuration. */
AnnaBridge 143:86740a56073b 3047 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
AnnaBridge 143:86740a56073b 3048 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
AnnaBridge 143:86740a56073b 3049 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3050 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3051
AnnaBridge 143:86740a56073b 3052 /* Bit 14 : ECB region configuration. */
AnnaBridge 143:86740a56073b 3053 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
AnnaBridge 143:86740a56073b 3054 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
AnnaBridge 143:86740a56073b 3055 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3056 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3057
AnnaBridge 143:86740a56073b 3058 /* Bit 13 : RNG region configuration. */
AnnaBridge 143:86740a56073b 3059 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
AnnaBridge 143:86740a56073b 3060 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
AnnaBridge 143:86740a56073b 3061 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3062 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3063
AnnaBridge 143:86740a56073b 3064 /* Bit 12 : TEMP region configuration. */
AnnaBridge 143:86740a56073b 3065 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
AnnaBridge 143:86740a56073b 3066 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
AnnaBridge 143:86740a56073b 3067 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3068 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3069
AnnaBridge 143:86740a56073b 3070 /* Bit 11 : RTC0 region configuration. */
AnnaBridge 143:86740a56073b 3071 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
AnnaBridge 143:86740a56073b 3072 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
AnnaBridge 143:86740a56073b 3073 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3074 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3075
AnnaBridge 143:86740a56073b 3076 /* Bit 10 : TIMER2 region configuration. */
AnnaBridge 143:86740a56073b 3077 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
AnnaBridge 143:86740a56073b 3078 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
AnnaBridge 143:86740a56073b 3079 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3080 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3081
AnnaBridge 143:86740a56073b 3082 /* Bit 9 : TIMER1 region configuration. */
AnnaBridge 143:86740a56073b 3083 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
AnnaBridge 143:86740a56073b 3084 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
AnnaBridge 143:86740a56073b 3085 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3086 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3087
AnnaBridge 143:86740a56073b 3088 /* Bit 8 : TIMER0 region configuration. */
AnnaBridge 143:86740a56073b 3089 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
AnnaBridge 143:86740a56073b 3090 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
AnnaBridge 143:86740a56073b 3091 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3092 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3093
AnnaBridge 143:86740a56073b 3094 /* Bit 7 : ADC region configuration. */
AnnaBridge 143:86740a56073b 3095 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
AnnaBridge 143:86740a56073b 3096 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
AnnaBridge 143:86740a56073b 3097 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3098 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3099
AnnaBridge 143:86740a56073b 3100 /* Bit 6 : GPIOTE region configuration. */
AnnaBridge 143:86740a56073b 3101 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
AnnaBridge 143:86740a56073b 3102 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
AnnaBridge 143:86740a56073b 3103 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3104 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3105
AnnaBridge 143:86740a56073b 3106 /* Bit 4 : SPI1 and TWI1 region configuration. */
AnnaBridge 143:86740a56073b 3107 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
AnnaBridge 143:86740a56073b 3108 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
AnnaBridge 143:86740a56073b 3109 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3110 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3111
AnnaBridge 143:86740a56073b 3112 /* Bit 3 : SPI0 and TWI0 region configuration. */
AnnaBridge 143:86740a56073b 3113 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
AnnaBridge 143:86740a56073b 3114 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
AnnaBridge 143:86740a56073b 3115 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3116 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3117
AnnaBridge 143:86740a56073b 3118 /* Bit 2 : UART0 region configuration. */
AnnaBridge 143:86740a56073b 3119 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
AnnaBridge 143:86740a56073b 3120 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
AnnaBridge 143:86740a56073b 3121 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3122 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3123
AnnaBridge 143:86740a56073b 3124 /* Bit 1 : RADIO region configuration. */
AnnaBridge 143:86740a56073b 3125 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
AnnaBridge 143:86740a56073b 3126 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
AnnaBridge 143:86740a56073b 3127 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3128 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3129
AnnaBridge 143:86740a56073b 3130 /* Bit 0 : POWER_CLOCK region configuration. */
AnnaBridge 143:86740a56073b 3131 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
AnnaBridge 143:86740a56073b 3132 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
AnnaBridge 143:86740a56073b 3133 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
AnnaBridge 143:86740a56073b 3134 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
AnnaBridge 143:86740a56073b 3135
AnnaBridge 143:86740a56073b 3136 /* Register: MPU_PROTENSET0 */
AnnaBridge 143:86740a56073b 3137 /* Description: Erase and write protection bit enable set register. */
AnnaBridge 143:86740a56073b 3138
AnnaBridge 143:86740a56073b 3139 /* Bit 31 : Protection enable for region 31. */
AnnaBridge 143:86740a56073b 3140 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
AnnaBridge 143:86740a56073b 3141 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
AnnaBridge 143:86740a56073b 3142 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3143 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3144 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3145
AnnaBridge 143:86740a56073b 3146 /* Bit 30 : Protection enable for region 30. */
AnnaBridge 143:86740a56073b 3147 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
AnnaBridge 143:86740a56073b 3148 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
AnnaBridge 143:86740a56073b 3149 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3150 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3151 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3152
AnnaBridge 143:86740a56073b 3153 /* Bit 29 : Protection enable for region 29. */
AnnaBridge 143:86740a56073b 3154 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
AnnaBridge 143:86740a56073b 3155 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
AnnaBridge 143:86740a56073b 3156 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3157 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3158 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3159
AnnaBridge 143:86740a56073b 3160 /* Bit 28 : Protection enable for region 28. */
AnnaBridge 143:86740a56073b 3161 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
AnnaBridge 143:86740a56073b 3162 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
AnnaBridge 143:86740a56073b 3163 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3164 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3165 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3166
AnnaBridge 143:86740a56073b 3167 /* Bit 27 : Protection enable for region 27. */
AnnaBridge 143:86740a56073b 3168 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
AnnaBridge 143:86740a56073b 3169 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
AnnaBridge 143:86740a56073b 3170 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3171 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3172 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3173
AnnaBridge 143:86740a56073b 3174 /* Bit 26 : Protection enable for region 26. */
AnnaBridge 143:86740a56073b 3175 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
AnnaBridge 143:86740a56073b 3176 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
AnnaBridge 143:86740a56073b 3177 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3178 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3179 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3180
AnnaBridge 143:86740a56073b 3181 /* Bit 25 : Protection enable for region 25. */
AnnaBridge 143:86740a56073b 3182 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
AnnaBridge 143:86740a56073b 3183 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
AnnaBridge 143:86740a56073b 3184 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3185 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3186 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3187
AnnaBridge 143:86740a56073b 3188 /* Bit 24 : Protection enable for region 24. */
AnnaBridge 143:86740a56073b 3189 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
AnnaBridge 143:86740a56073b 3190 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
AnnaBridge 143:86740a56073b 3191 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3192 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3193 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3194
AnnaBridge 143:86740a56073b 3195 /* Bit 23 : Protection enable for region 23. */
AnnaBridge 143:86740a56073b 3196 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
AnnaBridge 143:86740a56073b 3197 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
AnnaBridge 143:86740a56073b 3198 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3199 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3200 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3201
AnnaBridge 143:86740a56073b 3202 /* Bit 22 : Protection enable for region 22. */
AnnaBridge 143:86740a56073b 3203 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
AnnaBridge 143:86740a56073b 3204 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
AnnaBridge 143:86740a56073b 3205 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3206 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3207 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3208
AnnaBridge 143:86740a56073b 3209 /* Bit 21 : Protection enable for region 21. */
AnnaBridge 143:86740a56073b 3210 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
AnnaBridge 143:86740a56073b 3211 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
AnnaBridge 143:86740a56073b 3212 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3213 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3214 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3215
AnnaBridge 143:86740a56073b 3216 /* Bit 20 : Protection enable for region 20. */
AnnaBridge 143:86740a56073b 3217 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
AnnaBridge 143:86740a56073b 3218 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
AnnaBridge 143:86740a56073b 3219 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3220 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3221 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3222
AnnaBridge 143:86740a56073b 3223 /* Bit 19 : Protection enable for region 19. */
AnnaBridge 143:86740a56073b 3224 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
AnnaBridge 143:86740a56073b 3225 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
AnnaBridge 143:86740a56073b 3226 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3227 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3228 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3229
AnnaBridge 143:86740a56073b 3230 /* Bit 18 : Protection enable for region 18. */
AnnaBridge 143:86740a56073b 3231 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
AnnaBridge 143:86740a56073b 3232 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
AnnaBridge 143:86740a56073b 3233 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3234 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3235 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3236
AnnaBridge 143:86740a56073b 3237 /* Bit 17 : Protection enable for region 17. */
AnnaBridge 143:86740a56073b 3238 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
AnnaBridge 143:86740a56073b 3239 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
AnnaBridge 143:86740a56073b 3240 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3241 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3242 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3243
AnnaBridge 143:86740a56073b 3244 /* Bit 16 : Protection enable for region 16. */
AnnaBridge 143:86740a56073b 3245 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
AnnaBridge 143:86740a56073b 3246 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
AnnaBridge 143:86740a56073b 3247 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3248 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3249 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3250
AnnaBridge 143:86740a56073b 3251 /* Bit 15 : Protection enable for region 15. */
AnnaBridge 143:86740a56073b 3252 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
AnnaBridge 143:86740a56073b 3253 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
AnnaBridge 143:86740a56073b 3254 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3255 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3256 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3257
AnnaBridge 143:86740a56073b 3258 /* Bit 14 : Protection enable for region 14. */
AnnaBridge 143:86740a56073b 3259 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
AnnaBridge 143:86740a56073b 3260 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
AnnaBridge 143:86740a56073b 3261 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3262 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3263 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3264
AnnaBridge 143:86740a56073b 3265 /* Bit 13 : Protection enable for region 13. */
AnnaBridge 143:86740a56073b 3266 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
AnnaBridge 143:86740a56073b 3267 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
AnnaBridge 143:86740a56073b 3268 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3269 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3270 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3271
AnnaBridge 143:86740a56073b 3272 /* Bit 12 : Protection enable for region 12. */
AnnaBridge 143:86740a56073b 3273 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
AnnaBridge 143:86740a56073b 3274 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
AnnaBridge 143:86740a56073b 3275 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3276 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3277 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3278
AnnaBridge 143:86740a56073b 3279 /* Bit 11 : Protection enable for region 11. */
AnnaBridge 143:86740a56073b 3280 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
AnnaBridge 143:86740a56073b 3281 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
AnnaBridge 143:86740a56073b 3282 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3283 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3284 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3285
AnnaBridge 143:86740a56073b 3286 /* Bit 10 : Protection enable for region 10. */
AnnaBridge 143:86740a56073b 3287 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
AnnaBridge 143:86740a56073b 3288 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
AnnaBridge 143:86740a56073b 3289 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3290 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3291 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3292
AnnaBridge 143:86740a56073b 3293 /* Bit 9 : Protection enable for region 9. */
AnnaBridge 143:86740a56073b 3294 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
AnnaBridge 143:86740a56073b 3295 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
AnnaBridge 143:86740a56073b 3296 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3297 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3298 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3299
AnnaBridge 143:86740a56073b 3300 /* Bit 8 : Protection enable for region 8. */
AnnaBridge 143:86740a56073b 3301 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
AnnaBridge 143:86740a56073b 3302 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
AnnaBridge 143:86740a56073b 3303 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3304 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3305 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3306
AnnaBridge 143:86740a56073b 3307 /* Bit 7 : Protection enable for region 7. */
AnnaBridge 143:86740a56073b 3308 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
AnnaBridge 143:86740a56073b 3309 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
AnnaBridge 143:86740a56073b 3310 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3311 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3312 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3313
AnnaBridge 143:86740a56073b 3314 /* Bit 6 : Protection enable for region 6. */
AnnaBridge 143:86740a56073b 3315 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
AnnaBridge 143:86740a56073b 3316 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
AnnaBridge 143:86740a56073b 3317 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3318 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3319 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3320
AnnaBridge 143:86740a56073b 3321 /* Bit 5 : Protection enable for region 5. */
AnnaBridge 143:86740a56073b 3322 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
AnnaBridge 143:86740a56073b 3323 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
AnnaBridge 143:86740a56073b 3324 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3325 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3326 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3327
AnnaBridge 143:86740a56073b 3328 /* Bit 4 : Protection enable for region 4. */
AnnaBridge 143:86740a56073b 3329 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
AnnaBridge 143:86740a56073b 3330 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
AnnaBridge 143:86740a56073b 3331 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3332 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3333 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3334
AnnaBridge 143:86740a56073b 3335 /* Bit 3 : Protection enable for region 3. */
AnnaBridge 143:86740a56073b 3336 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
AnnaBridge 143:86740a56073b 3337 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
AnnaBridge 143:86740a56073b 3338 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3339 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3340 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3341
AnnaBridge 143:86740a56073b 3342 /* Bit 2 : Protection enable for region 2. */
AnnaBridge 143:86740a56073b 3343 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
AnnaBridge 143:86740a56073b 3344 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
AnnaBridge 143:86740a56073b 3345 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3346 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3347 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3348
AnnaBridge 143:86740a56073b 3349 /* Bit 1 : Protection enable for region 1. */
AnnaBridge 143:86740a56073b 3350 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
AnnaBridge 143:86740a56073b 3351 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
AnnaBridge 143:86740a56073b 3352 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3353 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3354 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3355
AnnaBridge 143:86740a56073b 3356 /* Bit 0 : Protection enable for region 0. */
AnnaBridge 143:86740a56073b 3357 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
AnnaBridge 143:86740a56073b 3358 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
AnnaBridge 143:86740a56073b 3359 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3360 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3361 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3362
AnnaBridge 143:86740a56073b 3363 /* Register: MPU_PROTENSET1 */
AnnaBridge 143:86740a56073b 3364 /* Description: Erase and write protection bit enable set register. */
AnnaBridge 143:86740a56073b 3365
AnnaBridge 143:86740a56073b 3366 /* Bit 31 : Protection enable for region 63. */
AnnaBridge 143:86740a56073b 3367 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
AnnaBridge 143:86740a56073b 3368 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
AnnaBridge 143:86740a56073b 3369 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3370 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3371 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3372
AnnaBridge 143:86740a56073b 3373 /* Bit 30 : Protection enable for region 62. */
AnnaBridge 143:86740a56073b 3374 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
AnnaBridge 143:86740a56073b 3375 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
AnnaBridge 143:86740a56073b 3376 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3377 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3378 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3379
AnnaBridge 143:86740a56073b 3380 /* Bit 29 : Protection enable for region 61. */
AnnaBridge 143:86740a56073b 3381 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
AnnaBridge 143:86740a56073b 3382 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
AnnaBridge 143:86740a56073b 3383 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3384 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3385 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3386
AnnaBridge 143:86740a56073b 3387 /* Bit 28 : Protection enable for region 60. */
AnnaBridge 143:86740a56073b 3388 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
AnnaBridge 143:86740a56073b 3389 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
AnnaBridge 143:86740a56073b 3390 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3391 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3392 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3393
AnnaBridge 143:86740a56073b 3394 /* Bit 27 : Protection enable for region 59. */
AnnaBridge 143:86740a56073b 3395 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
AnnaBridge 143:86740a56073b 3396 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
AnnaBridge 143:86740a56073b 3397 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3398 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3399 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3400
AnnaBridge 143:86740a56073b 3401 /* Bit 26 : Protection enable for region 58. */
AnnaBridge 143:86740a56073b 3402 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
AnnaBridge 143:86740a56073b 3403 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
AnnaBridge 143:86740a56073b 3404 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3405 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3406 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3407
AnnaBridge 143:86740a56073b 3408 /* Bit 25 : Protection enable for region 57. */
AnnaBridge 143:86740a56073b 3409 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
AnnaBridge 143:86740a56073b 3410 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
AnnaBridge 143:86740a56073b 3411 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3412 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3413 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3414
AnnaBridge 143:86740a56073b 3415 /* Bit 24 : Protection enable for region 56. */
AnnaBridge 143:86740a56073b 3416 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
AnnaBridge 143:86740a56073b 3417 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
AnnaBridge 143:86740a56073b 3418 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3419 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3420 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3421
AnnaBridge 143:86740a56073b 3422 /* Bit 23 : Protection enable for region 55. */
AnnaBridge 143:86740a56073b 3423 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
AnnaBridge 143:86740a56073b 3424 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
AnnaBridge 143:86740a56073b 3425 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3426 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3427 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3428
AnnaBridge 143:86740a56073b 3429 /* Bit 22 : Protection enable for region 54. */
AnnaBridge 143:86740a56073b 3430 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
AnnaBridge 143:86740a56073b 3431 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
AnnaBridge 143:86740a56073b 3432 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3433 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3434 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3435
AnnaBridge 143:86740a56073b 3436 /* Bit 21 : Protection enable for region 53. */
AnnaBridge 143:86740a56073b 3437 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
AnnaBridge 143:86740a56073b 3438 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
AnnaBridge 143:86740a56073b 3439 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3440 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3441 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3442
AnnaBridge 143:86740a56073b 3443 /* Bit 20 : Protection enable for region 52. */
AnnaBridge 143:86740a56073b 3444 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
AnnaBridge 143:86740a56073b 3445 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
AnnaBridge 143:86740a56073b 3446 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3447 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3448 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3449
AnnaBridge 143:86740a56073b 3450 /* Bit 19 : Protection enable for region 51. */
AnnaBridge 143:86740a56073b 3451 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
AnnaBridge 143:86740a56073b 3452 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
AnnaBridge 143:86740a56073b 3453 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3454 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3455 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3456
AnnaBridge 143:86740a56073b 3457 /* Bit 18 : Protection enable for region 50. */
AnnaBridge 143:86740a56073b 3458 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
AnnaBridge 143:86740a56073b 3459 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
AnnaBridge 143:86740a56073b 3460 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3461 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3462 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3463
AnnaBridge 143:86740a56073b 3464 /* Bit 17 : Protection enable for region 49. */
AnnaBridge 143:86740a56073b 3465 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
AnnaBridge 143:86740a56073b 3466 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
AnnaBridge 143:86740a56073b 3467 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3468 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3469 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3470
AnnaBridge 143:86740a56073b 3471 /* Bit 16 : Protection enable for region 48. */
AnnaBridge 143:86740a56073b 3472 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
AnnaBridge 143:86740a56073b 3473 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
AnnaBridge 143:86740a56073b 3474 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3475 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3476 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3477
AnnaBridge 143:86740a56073b 3478 /* Bit 15 : Protection enable for region 47. */
AnnaBridge 143:86740a56073b 3479 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
AnnaBridge 143:86740a56073b 3480 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
AnnaBridge 143:86740a56073b 3481 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3482 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3483 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3484
AnnaBridge 143:86740a56073b 3485 /* Bit 14 : Protection enable for region 46. */
AnnaBridge 143:86740a56073b 3486 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
AnnaBridge 143:86740a56073b 3487 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
AnnaBridge 143:86740a56073b 3488 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3489 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3490 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3491
AnnaBridge 143:86740a56073b 3492 /* Bit 13 : Protection enable for region 45. */
AnnaBridge 143:86740a56073b 3493 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
AnnaBridge 143:86740a56073b 3494 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
AnnaBridge 143:86740a56073b 3495 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3496 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3497 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3498
AnnaBridge 143:86740a56073b 3499 /* Bit 12 : Protection enable for region 44. */
AnnaBridge 143:86740a56073b 3500 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
AnnaBridge 143:86740a56073b 3501 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
AnnaBridge 143:86740a56073b 3502 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3503 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3504 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3505
AnnaBridge 143:86740a56073b 3506 /* Bit 11 : Protection enable for region 43. */
AnnaBridge 143:86740a56073b 3507 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
AnnaBridge 143:86740a56073b 3508 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
AnnaBridge 143:86740a56073b 3509 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3510 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3511 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3512
AnnaBridge 143:86740a56073b 3513 /* Bit 10 : Protection enable for region 42. */
AnnaBridge 143:86740a56073b 3514 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
AnnaBridge 143:86740a56073b 3515 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
AnnaBridge 143:86740a56073b 3516 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3517 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3518 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3519
AnnaBridge 143:86740a56073b 3520 /* Bit 9 : Protection enable for region 41. */
AnnaBridge 143:86740a56073b 3521 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
AnnaBridge 143:86740a56073b 3522 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
AnnaBridge 143:86740a56073b 3523 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3524 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3525 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3526
AnnaBridge 143:86740a56073b 3527 /* Bit 8 : Protection enable for region 40. */
AnnaBridge 143:86740a56073b 3528 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
AnnaBridge 143:86740a56073b 3529 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
AnnaBridge 143:86740a56073b 3530 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3531 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3532 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3533
AnnaBridge 143:86740a56073b 3534 /* Bit 7 : Protection enable for region 39. */
AnnaBridge 143:86740a56073b 3535 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
AnnaBridge 143:86740a56073b 3536 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
AnnaBridge 143:86740a56073b 3537 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3538 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3539 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3540
AnnaBridge 143:86740a56073b 3541 /* Bit 6 : Protection enable for region 38. */
AnnaBridge 143:86740a56073b 3542 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
AnnaBridge 143:86740a56073b 3543 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
AnnaBridge 143:86740a56073b 3544 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3545 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3546 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3547
AnnaBridge 143:86740a56073b 3548 /* Bit 5 : Protection enable for region 37. */
AnnaBridge 143:86740a56073b 3549 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
AnnaBridge 143:86740a56073b 3550 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
AnnaBridge 143:86740a56073b 3551 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3552 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3553 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3554
AnnaBridge 143:86740a56073b 3555 /* Bit 4 : Protection enable for region 36. */
AnnaBridge 143:86740a56073b 3556 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
AnnaBridge 143:86740a56073b 3557 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
AnnaBridge 143:86740a56073b 3558 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3559 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3560 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3561
AnnaBridge 143:86740a56073b 3562 /* Bit 3 : Protection enable for region 35. */
AnnaBridge 143:86740a56073b 3563 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
AnnaBridge 143:86740a56073b 3564 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
AnnaBridge 143:86740a56073b 3565 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3566 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3567 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3568
AnnaBridge 143:86740a56073b 3569 /* Bit 2 : Protection enable for region 34. */
AnnaBridge 143:86740a56073b 3570 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
AnnaBridge 143:86740a56073b 3571 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
AnnaBridge 143:86740a56073b 3572 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3573 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3574 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3575
AnnaBridge 143:86740a56073b 3576 /* Bit 1 : Protection enable for region 33. */
AnnaBridge 143:86740a56073b 3577 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
AnnaBridge 143:86740a56073b 3578 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
AnnaBridge 143:86740a56073b 3579 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3580 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3581 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3582
AnnaBridge 143:86740a56073b 3583 /* Bit 0 : Protection enable for region 32. */
AnnaBridge 143:86740a56073b 3584 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
AnnaBridge 143:86740a56073b 3585 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
AnnaBridge 143:86740a56073b 3586 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3587 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3588 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
AnnaBridge 143:86740a56073b 3589
AnnaBridge 143:86740a56073b 3590 /* Register: MPU_DISABLEINDEBUG */
AnnaBridge 143:86740a56073b 3591 /* Description: Disable erase and write protection mechanism in debug mode. */
AnnaBridge 143:86740a56073b 3592
AnnaBridge 143:86740a56073b 3593 /* Bit 0 : Disable protection mechanism in debug mode. */
AnnaBridge 143:86740a56073b 3594 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
AnnaBridge 143:86740a56073b 3595 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
AnnaBridge 143:86740a56073b 3596 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
AnnaBridge 143:86740a56073b 3597 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
AnnaBridge 143:86740a56073b 3598
AnnaBridge 143:86740a56073b 3599 /* Register: MPU_PROTBLOCKSIZE */
AnnaBridge 143:86740a56073b 3600 /* Description: Erase and write protection block size. */
AnnaBridge 143:86740a56073b 3601
AnnaBridge 143:86740a56073b 3602 /* Bits 1..0 : Erase and write protection block size. */
AnnaBridge 143:86740a56073b 3603 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
AnnaBridge 143:86740a56073b 3604 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
AnnaBridge 143:86740a56073b 3605 #define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
AnnaBridge 143:86740a56073b 3606
AnnaBridge 143:86740a56073b 3607
AnnaBridge 143:86740a56073b 3608 /* Peripheral: NVMC */
AnnaBridge 143:86740a56073b 3609 /* Description: Non Volatile Memory Controller. */
AnnaBridge 143:86740a56073b 3610
AnnaBridge 143:86740a56073b 3611 /* Register: NVMC_READY */
AnnaBridge 143:86740a56073b 3612 /* Description: Ready flag. */
AnnaBridge 143:86740a56073b 3613
AnnaBridge 143:86740a56073b 3614 /* Bit 0 : NVMC ready. */
AnnaBridge 143:86740a56073b 3615 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 3616 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 3617 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
AnnaBridge 143:86740a56073b 3618 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
AnnaBridge 143:86740a56073b 3619
AnnaBridge 143:86740a56073b 3620 /* Register: NVMC_CONFIG */
AnnaBridge 143:86740a56073b 3621 /* Description: Configuration register. */
AnnaBridge 143:86740a56073b 3622
AnnaBridge 143:86740a56073b 3623 /* Bits 1..0 : Program write enable. */
AnnaBridge 143:86740a56073b 3624 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
AnnaBridge 143:86740a56073b 3625 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
AnnaBridge 143:86740a56073b 3626 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
AnnaBridge 143:86740a56073b 3627 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
AnnaBridge 143:86740a56073b 3628 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
AnnaBridge 143:86740a56073b 3629
AnnaBridge 143:86740a56073b 3630 /* Register: NVMC_ERASEALL */
AnnaBridge 143:86740a56073b 3631 /* Description: Register for erasing all non-volatile user memory. */
AnnaBridge 143:86740a56073b 3632
AnnaBridge 143:86740a56073b 3633 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
AnnaBridge 143:86740a56073b 3634 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
AnnaBridge 143:86740a56073b 3635 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
AnnaBridge 143:86740a56073b 3636 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
AnnaBridge 143:86740a56073b 3637 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
AnnaBridge 143:86740a56073b 3638
AnnaBridge 143:86740a56073b 3639 /* Register: NVMC_ERASEUICR */
AnnaBridge 143:86740a56073b 3640 /* Description: Register for start erasing User Information Congfiguration Registers. */
AnnaBridge 143:86740a56073b 3641
AnnaBridge 143:86740a56073b 3642 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
AnnaBridge 143:86740a56073b 3643 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
AnnaBridge 143:86740a56073b 3644 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
AnnaBridge 143:86740a56073b 3645 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
AnnaBridge 143:86740a56073b 3646 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
AnnaBridge 143:86740a56073b 3647
AnnaBridge 143:86740a56073b 3648
AnnaBridge 143:86740a56073b 3649 /* Peripheral: POWER */
AnnaBridge 143:86740a56073b 3650 /* Description: Power Control. */
AnnaBridge 143:86740a56073b 3651
AnnaBridge 143:86740a56073b 3652 /* Register: POWER_INTENSET */
AnnaBridge 143:86740a56073b 3653 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 3654
AnnaBridge 143:86740a56073b 3655 /* Bit 2 : Enable interrupt on POFWARN event. */
AnnaBridge 143:86740a56073b 3656 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
AnnaBridge 143:86740a56073b 3657 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
AnnaBridge 143:86740a56073b 3658 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 3659 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 3660 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 3661
AnnaBridge 143:86740a56073b 3662 /* Register: POWER_INTENCLR */
AnnaBridge 143:86740a56073b 3663 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 3664
AnnaBridge 143:86740a56073b 3665 /* Bit 2 : Disable interrupt on POFWARN event. */
AnnaBridge 143:86740a56073b 3666 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
AnnaBridge 143:86740a56073b 3667 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
AnnaBridge 143:86740a56073b 3668 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 3669 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 3670 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 3671
AnnaBridge 143:86740a56073b 3672 /* Register: POWER_RESETREAS */
AnnaBridge 143:86740a56073b 3673 /* Description: Reset reason. */
AnnaBridge 143:86740a56073b 3674
AnnaBridge 143:86740a56073b 3675 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
AnnaBridge 143:86740a56073b 3676 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
AnnaBridge 143:86740a56073b 3677 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
AnnaBridge 143:86740a56073b 3678 #define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3679 #define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3680
AnnaBridge 143:86740a56073b 3681 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
AnnaBridge 143:86740a56073b 3682 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
AnnaBridge 143:86740a56073b 3683 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
AnnaBridge 143:86740a56073b 3684 #define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3685 #define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3686
AnnaBridge 143:86740a56073b 3687 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
AnnaBridge 143:86740a56073b 3688 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
AnnaBridge 143:86740a56073b 3689 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
AnnaBridge 143:86740a56073b 3690 #define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3691 #define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3692
AnnaBridge 143:86740a56073b 3693 /* Bit 3 : Reset from CPU lock-up detected. */
AnnaBridge 143:86740a56073b 3694 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
AnnaBridge 143:86740a56073b 3695 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
AnnaBridge 143:86740a56073b 3696 #define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3697 #define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3698
AnnaBridge 143:86740a56073b 3699 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
AnnaBridge 143:86740a56073b 3700 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
AnnaBridge 143:86740a56073b 3701 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
AnnaBridge 143:86740a56073b 3702 #define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3703 #define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3704
AnnaBridge 143:86740a56073b 3705 /* Bit 1 : Reset from watchdog detected. */
AnnaBridge 143:86740a56073b 3706 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
AnnaBridge 143:86740a56073b 3707 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
AnnaBridge 143:86740a56073b 3708 #define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3709 #define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3710
AnnaBridge 143:86740a56073b 3711 /* Bit 0 : Reset from pin-reset detected. */
AnnaBridge 143:86740a56073b 3712 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
AnnaBridge 143:86740a56073b 3713 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
AnnaBridge 143:86740a56073b 3714 #define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
AnnaBridge 143:86740a56073b 3715 #define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
AnnaBridge 143:86740a56073b 3716
AnnaBridge 143:86740a56073b 3717 /* Register: POWER_RAMSTATUS */
AnnaBridge 143:86740a56073b 3718 /* Description: Ram status register. */
AnnaBridge 143:86740a56073b 3719
AnnaBridge 143:86740a56073b 3720 /* Bit 3 : RAM block 3 status. */
AnnaBridge 143:86740a56073b 3721 #define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
AnnaBridge 143:86740a56073b 3722 #define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
AnnaBridge 143:86740a56073b 3723 #define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
AnnaBridge 143:86740a56073b 3724 #define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
AnnaBridge 143:86740a56073b 3725
AnnaBridge 143:86740a56073b 3726 /* Bit 2 : RAM block 2 status. */
AnnaBridge 143:86740a56073b 3727 #define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
AnnaBridge 143:86740a56073b 3728 #define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
AnnaBridge 143:86740a56073b 3729 #define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
AnnaBridge 143:86740a56073b 3730 #define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
AnnaBridge 143:86740a56073b 3731
AnnaBridge 143:86740a56073b 3732 /* Bit 1 : RAM block 1 status. */
AnnaBridge 143:86740a56073b 3733 #define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
AnnaBridge 143:86740a56073b 3734 #define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
AnnaBridge 143:86740a56073b 3735 #define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
AnnaBridge 143:86740a56073b 3736 #define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
AnnaBridge 143:86740a56073b 3737
AnnaBridge 143:86740a56073b 3738 /* Bit 0 : RAM block 0 status. */
AnnaBridge 143:86740a56073b 3739 #define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
AnnaBridge 143:86740a56073b 3740 #define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
AnnaBridge 143:86740a56073b 3741 #define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
AnnaBridge 143:86740a56073b 3742 #define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
AnnaBridge 143:86740a56073b 3743
AnnaBridge 143:86740a56073b 3744 /* Register: POWER_SYSTEMOFF */
AnnaBridge 143:86740a56073b 3745 /* Description: System off register. */
AnnaBridge 143:86740a56073b 3746
AnnaBridge 143:86740a56073b 3747 /* Bit 0 : Enter system off mode. */
AnnaBridge 143:86740a56073b 3748 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
AnnaBridge 143:86740a56073b 3749 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
AnnaBridge 143:86740a56073b 3750 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
AnnaBridge 143:86740a56073b 3751
AnnaBridge 143:86740a56073b 3752 /* Register: POWER_POFCON */
AnnaBridge 143:86740a56073b 3753 /* Description: Power failure configuration. */
AnnaBridge 143:86740a56073b 3754
AnnaBridge 143:86740a56073b 3755 /* Bits 2..1 : Set threshold level. */
AnnaBridge 143:86740a56073b 3756 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
AnnaBridge 143:86740a56073b 3757 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
AnnaBridge 143:86740a56073b 3758 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
AnnaBridge 143:86740a56073b 3759 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
AnnaBridge 143:86740a56073b 3760 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
AnnaBridge 143:86740a56073b 3761 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
AnnaBridge 143:86740a56073b 3762
AnnaBridge 143:86740a56073b 3763 /* Bit 0 : Power failure comparator enable. */
AnnaBridge 143:86740a56073b 3764 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
AnnaBridge 143:86740a56073b 3765 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
AnnaBridge 143:86740a56073b 3766 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 3767 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 3768
AnnaBridge 143:86740a56073b 3769 /* Register: POWER_GPREGRET */
AnnaBridge 143:86740a56073b 3770 /* Description: General purpose retention register. This register is a retained register. */
AnnaBridge 143:86740a56073b 3771
AnnaBridge 143:86740a56073b 3772 /* Bits 7..0 : General purpose retention register. */
AnnaBridge 143:86740a56073b 3773 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
AnnaBridge 143:86740a56073b 3774 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
AnnaBridge 143:86740a56073b 3775
AnnaBridge 143:86740a56073b 3776 /* Register: POWER_RAMON */
AnnaBridge 143:86740a56073b 3777 /* Description: Ram on/off. */
AnnaBridge 143:86740a56073b 3778
AnnaBridge 143:86740a56073b 3779 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
AnnaBridge 143:86740a56073b 3780 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
AnnaBridge 143:86740a56073b 3781 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
AnnaBridge 143:86740a56073b 3782 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
AnnaBridge 143:86740a56073b 3783 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
AnnaBridge 143:86740a56073b 3784
AnnaBridge 143:86740a56073b 3785 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
AnnaBridge 143:86740a56073b 3786 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
AnnaBridge 143:86740a56073b 3787 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
AnnaBridge 143:86740a56073b 3788 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
AnnaBridge 143:86740a56073b 3789 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
AnnaBridge 143:86740a56073b 3790
AnnaBridge 143:86740a56073b 3791 /* Bit 1 : RAM block 1 behaviour in ON mode. */
AnnaBridge 143:86740a56073b 3792 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
AnnaBridge 143:86740a56073b 3793 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
AnnaBridge 143:86740a56073b 3794 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
AnnaBridge 143:86740a56073b 3795 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
AnnaBridge 143:86740a56073b 3796
AnnaBridge 143:86740a56073b 3797 /* Bit 0 : RAM block 0 behaviour in ON mode. */
AnnaBridge 143:86740a56073b 3798 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
AnnaBridge 143:86740a56073b 3799 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
AnnaBridge 143:86740a56073b 3800 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
AnnaBridge 143:86740a56073b 3801 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
AnnaBridge 143:86740a56073b 3802
AnnaBridge 143:86740a56073b 3803 /* Register: POWER_RESET */
AnnaBridge 143:86740a56073b 3804 /* Description: Pin reset functionality configuration register. This register is a retained register. */
AnnaBridge 143:86740a56073b 3805
AnnaBridge 143:86740a56073b 3806 /* Bit 0 : Enable or disable pin reset in debug interface mode. */
AnnaBridge 143:86740a56073b 3807 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
AnnaBridge 143:86740a56073b 3808 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
AnnaBridge 143:86740a56073b 3809 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
AnnaBridge 143:86740a56073b 3810 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
AnnaBridge 143:86740a56073b 3811
AnnaBridge 143:86740a56073b 3812 /* Register: POWER_RAMONB */
AnnaBridge 143:86740a56073b 3813 /* Description: Ram on/off. */
AnnaBridge 143:86740a56073b 3814
AnnaBridge 143:86740a56073b 3815 /* Bit 17 : RAM block 3 behaviour in OFF mode. */
AnnaBridge 143:86740a56073b 3816 #define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
AnnaBridge 143:86740a56073b 3817 #define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
AnnaBridge 143:86740a56073b 3818 #define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
AnnaBridge 143:86740a56073b 3819 #define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
AnnaBridge 143:86740a56073b 3820
AnnaBridge 143:86740a56073b 3821 /* Bit 16 : RAM block 2 behaviour in OFF mode. */
AnnaBridge 143:86740a56073b 3822 #define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
AnnaBridge 143:86740a56073b 3823 #define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
AnnaBridge 143:86740a56073b 3824 #define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
AnnaBridge 143:86740a56073b 3825 #define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
AnnaBridge 143:86740a56073b 3826
AnnaBridge 143:86740a56073b 3827 /* Bit 1 : RAM block 3 behaviour in ON mode. */
AnnaBridge 143:86740a56073b 3828 #define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
AnnaBridge 143:86740a56073b 3829 #define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
AnnaBridge 143:86740a56073b 3830 #define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
AnnaBridge 143:86740a56073b 3831 #define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
AnnaBridge 143:86740a56073b 3832
AnnaBridge 143:86740a56073b 3833 /* Bit 0 : RAM block 2 behaviour in ON mode. */
AnnaBridge 143:86740a56073b 3834 #define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
AnnaBridge 143:86740a56073b 3835 #define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
AnnaBridge 143:86740a56073b 3836 #define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
AnnaBridge 143:86740a56073b 3837 #define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
AnnaBridge 143:86740a56073b 3838
AnnaBridge 143:86740a56073b 3839 /* Register: POWER_DCDCEN */
AnnaBridge 143:86740a56073b 3840 /* Description: DCDC converter enable configuration register. */
AnnaBridge 143:86740a56073b 3841
AnnaBridge 143:86740a56073b 3842 /* Bit 0 : Enable DCDC converter. */
AnnaBridge 143:86740a56073b 3843 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
AnnaBridge 143:86740a56073b 3844 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
AnnaBridge 143:86740a56073b 3845 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
AnnaBridge 143:86740a56073b 3846 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
AnnaBridge 143:86740a56073b 3847
AnnaBridge 143:86740a56073b 3848 /* Register: POWER_DCDCFORCE */
AnnaBridge 143:86740a56073b 3849 /* Description: DCDC power-up force register. */
AnnaBridge 143:86740a56073b 3850
AnnaBridge 143:86740a56073b 3851 /* Bit 1 : DCDC power-up force on. */
AnnaBridge 143:86740a56073b 3852 #define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
AnnaBridge 143:86740a56073b 3853 #define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
AnnaBridge 143:86740a56073b 3854 #define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
AnnaBridge 143:86740a56073b 3855 #define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
AnnaBridge 143:86740a56073b 3856
AnnaBridge 143:86740a56073b 3857 /* Bit 0 : DCDC power-up force off. */
AnnaBridge 143:86740a56073b 3858 #define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
AnnaBridge 143:86740a56073b 3859 #define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
AnnaBridge 143:86740a56073b 3860 #define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
AnnaBridge 143:86740a56073b 3861 #define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
AnnaBridge 143:86740a56073b 3862
AnnaBridge 143:86740a56073b 3863
AnnaBridge 143:86740a56073b 3864 /* Peripheral: PPI */
AnnaBridge 143:86740a56073b 3865 /* Description: PPI controller. */
AnnaBridge 143:86740a56073b 3866
AnnaBridge 143:86740a56073b 3867 /* Register: PPI_CHEN */
AnnaBridge 143:86740a56073b 3868 /* Description: Channel enable. */
AnnaBridge 143:86740a56073b 3869
AnnaBridge 143:86740a56073b 3870 /* Bit 31 : Enable PPI channel 31. */
AnnaBridge 143:86740a56073b 3871 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 3872 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 3873 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3874 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3875
AnnaBridge 143:86740a56073b 3876 /* Bit 30 : Enable PPI channel 30. */
AnnaBridge 143:86740a56073b 3877 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 3878 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 3879 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3880 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3881
AnnaBridge 143:86740a56073b 3882 /* Bit 29 : Enable PPI channel 29. */
AnnaBridge 143:86740a56073b 3883 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 3884 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 3885 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3886 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3887
AnnaBridge 143:86740a56073b 3888 /* Bit 28 : Enable PPI channel 28. */
AnnaBridge 143:86740a56073b 3889 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 3890 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 3891 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3892 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3893
AnnaBridge 143:86740a56073b 3894 /* Bit 27 : Enable PPI channel 27. */
AnnaBridge 143:86740a56073b 3895 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 3896 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 3897 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3898 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3899
AnnaBridge 143:86740a56073b 3900 /* Bit 26 : Enable PPI channel 26. */
AnnaBridge 143:86740a56073b 3901 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 3902 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 3903 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3904 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3905
AnnaBridge 143:86740a56073b 3906 /* Bit 25 : Enable PPI channel 25. */
AnnaBridge 143:86740a56073b 3907 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 3908 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 3909 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3910 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3911
AnnaBridge 143:86740a56073b 3912 /* Bit 24 : Enable PPI channel 24. */
AnnaBridge 143:86740a56073b 3913 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 3914 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 3915 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3916 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3917
AnnaBridge 143:86740a56073b 3918 /* Bit 23 : Enable PPI channel 23. */
AnnaBridge 143:86740a56073b 3919 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 3920 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 3921 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3922 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3923
AnnaBridge 143:86740a56073b 3924 /* Bit 22 : Enable PPI channel 22. */
AnnaBridge 143:86740a56073b 3925 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 3926 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 3927 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3928 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3929
AnnaBridge 143:86740a56073b 3930 /* Bit 21 : Enable PPI channel 21. */
AnnaBridge 143:86740a56073b 3931 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 3932 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 3933 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3934 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3935
AnnaBridge 143:86740a56073b 3936 /* Bit 20 : Enable PPI channel 20. */
AnnaBridge 143:86740a56073b 3937 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 3938 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 3939 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3940 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3941
AnnaBridge 143:86740a56073b 3942 /* Bit 15 : Enable PPI channel 15. */
AnnaBridge 143:86740a56073b 3943 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 3944 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 3945 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3946 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3947
AnnaBridge 143:86740a56073b 3948 /* Bit 14 : Enable PPI channel 14. */
AnnaBridge 143:86740a56073b 3949 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 3950 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 3951 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3952 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3953
AnnaBridge 143:86740a56073b 3954 /* Bit 13 : Enable PPI channel 13. */
AnnaBridge 143:86740a56073b 3955 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 3956 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 3957 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3958 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3959
AnnaBridge 143:86740a56073b 3960 /* Bit 12 : Enable PPI channel 12. */
AnnaBridge 143:86740a56073b 3961 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 3962 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 3963 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3964 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3965
AnnaBridge 143:86740a56073b 3966 /* Bit 11 : Enable PPI channel 11. */
AnnaBridge 143:86740a56073b 3967 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 3968 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 3969 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3970 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3971
AnnaBridge 143:86740a56073b 3972 /* Bit 10 : Enable PPI channel 10. */
AnnaBridge 143:86740a56073b 3973 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 3974 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 3975 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3976 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3977
AnnaBridge 143:86740a56073b 3978 /* Bit 9 : Enable PPI channel 9. */
AnnaBridge 143:86740a56073b 3979 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 3980 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 3981 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3982 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3983
AnnaBridge 143:86740a56073b 3984 /* Bit 8 : Enable PPI channel 8. */
AnnaBridge 143:86740a56073b 3985 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 3986 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 3987 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3988 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3989
AnnaBridge 143:86740a56073b 3990 /* Bit 7 : Enable PPI channel 7. */
AnnaBridge 143:86740a56073b 3991 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 3992 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 3993 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 3994 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 3995
AnnaBridge 143:86740a56073b 3996 /* Bit 6 : Enable PPI channel 6. */
AnnaBridge 143:86740a56073b 3997 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 3998 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 3999 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4000 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4001
AnnaBridge 143:86740a56073b 4002 /* Bit 5 : Enable PPI channel 5. */
AnnaBridge 143:86740a56073b 4003 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 4004 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 4005 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4006 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4007
AnnaBridge 143:86740a56073b 4008 /* Bit 4 : Enable PPI channel 4. */
AnnaBridge 143:86740a56073b 4009 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 4010 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 4011 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4012 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4013
AnnaBridge 143:86740a56073b 4014 /* Bit 3 : Enable PPI channel 3. */
AnnaBridge 143:86740a56073b 4015 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 4016 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 4017 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
AnnaBridge 143:86740a56073b 4018 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
AnnaBridge 143:86740a56073b 4019
AnnaBridge 143:86740a56073b 4020 /* Bit 2 : Enable PPI channel 2. */
AnnaBridge 143:86740a56073b 4021 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 4022 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 4023 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4024 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4025
AnnaBridge 143:86740a56073b 4026 /* Bit 1 : Enable PPI channel 1. */
AnnaBridge 143:86740a56073b 4027 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 4028 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 4029 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4030 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4031
AnnaBridge 143:86740a56073b 4032 /* Bit 0 : Enable PPI channel 0. */
AnnaBridge 143:86740a56073b 4033 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 4034 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 4035 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4036 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4037
AnnaBridge 143:86740a56073b 4038 /* Register: PPI_CHENSET */
AnnaBridge 143:86740a56073b 4039 /* Description: Channel enable set. */
AnnaBridge 143:86740a56073b 4040
AnnaBridge 143:86740a56073b 4041 /* Bit 31 : Enable PPI channel 31. */
AnnaBridge 143:86740a56073b 4042 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 4043 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 4044 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4045 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4046 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4047
AnnaBridge 143:86740a56073b 4048 /* Bit 30 : Enable PPI channel 30. */
AnnaBridge 143:86740a56073b 4049 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 4050 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 4051 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4052 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4053 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4054
AnnaBridge 143:86740a56073b 4055 /* Bit 29 : Enable PPI channel 29. */
AnnaBridge 143:86740a56073b 4056 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 4057 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 4058 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4059 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4060 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4061
AnnaBridge 143:86740a56073b 4062 /* Bit 28 : Enable PPI channel 28. */
AnnaBridge 143:86740a56073b 4063 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 4064 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 4065 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4066 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4067 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4068
AnnaBridge 143:86740a56073b 4069 /* Bit 27 : Enable PPI channel 27. */
AnnaBridge 143:86740a56073b 4070 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 4071 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 4072 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4073 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4074 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4075
AnnaBridge 143:86740a56073b 4076 /* Bit 26 : Enable PPI channel 26. */
AnnaBridge 143:86740a56073b 4077 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 4078 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 4079 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4080 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4081 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4082
AnnaBridge 143:86740a56073b 4083 /* Bit 25 : Enable PPI channel 25. */
AnnaBridge 143:86740a56073b 4084 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 4085 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 4086 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4087 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4088 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4089
AnnaBridge 143:86740a56073b 4090 /* Bit 24 : Enable PPI channel 24. */
AnnaBridge 143:86740a56073b 4091 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 4092 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 4093 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4094 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4095 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4096
AnnaBridge 143:86740a56073b 4097 /* Bit 23 : Enable PPI channel 23. */
AnnaBridge 143:86740a56073b 4098 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 4099 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 4100 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4101 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4102 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4103
AnnaBridge 143:86740a56073b 4104 /* Bit 22 : Enable PPI channel 22. */
AnnaBridge 143:86740a56073b 4105 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 4106 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 4107 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4108 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4109 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4110
AnnaBridge 143:86740a56073b 4111 /* Bit 21 : Enable PPI channel 21. */
AnnaBridge 143:86740a56073b 4112 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 4113 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 4114 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4115 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4116 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4117
AnnaBridge 143:86740a56073b 4118 /* Bit 20 : Enable PPI channel 20. */
AnnaBridge 143:86740a56073b 4119 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 4120 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 4121 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4122 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4123 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4124
AnnaBridge 143:86740a56073b 4125 /* Bit 15 : Enable PPI channel 15. */
AnnaBridge 143:86740a56073b 4126 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 4127 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 4128 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4129 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4130 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4131
AnnaBridge 143:86740a56073b 4132 /* Bit 14 : Enable PPI channel 14. */
AnnaBridge 143:86740a56073b 4133 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 4134 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 4135 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4136 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4137 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4138
AnnaBridge 143:86740a56073b 4139 /* Bit 13 : Enable PPI channel 13. */
AnnaBridge 143:86740a56073b 4140 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 4141 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 4142 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4143 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4144 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4145
AnnaBridge 143:86740a56073b 4146 /* Bit 12 : Enable PPI channel 12. */
AnnaBridge 143:86740a56073b 4147 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 4148 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 4149 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4150 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4151 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4152
AnnaBridge 143:86740a56073b 4153 /* Bit 11 : Enable PPI channel 11. */
AnnaBridge 143:86740a56073b 4154 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 4155 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 4156 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4157 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4158 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4159
AnnaBridge 143:86740a56073b 4160 /* Bit 10 : Enable PPI channel 10. */
AnnaBridge 143:86740a56073b 4161 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 4162 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 4163 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4164 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4165 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4166
AnnaBridge 143:86740a56073b 4167 /* Bit 9 : Enable PPI channel 9. */
AnnaBridge 143:86740a56073b 4168 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 4169 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 4170 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4171 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4172 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4173
AnnaBridge 143:86740a56073b 4174 /* Bit 8 : Enable PPI channel 8. */
AnnaBridge 143:86740a56073b 4175 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 4176 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 4177 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4178 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4179 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4180
AnnaBridge 143:86740a56073b 4181 /* Bit 7 : Enable PPI channel 7. */
AnnaBridge 143:86740a56073b 4182 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 4183 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 4184 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4185 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4186 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4187
AnnaBridge 143:86740a56073b 4188 /* Bit 6 : Enable PPI channel 6. */
AnnaBridge 143:86740a56073b 4189 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 4190 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 4191 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4192 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4193 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4194
AnnaBridge 143:86740a56073b 4195 /* Bit 5 : Enable PPI channel 5. */
AnnaBridge 143:86740a56073b 4196 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 4197 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 4198 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4199 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4200 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4201
AnnaBridge 143:86740a56073b 4202 /* Bit 4 : Enable PPI channel 4. */
AnnaBridge 143:86740a56073b 4203 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 4204 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 4205 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4206 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4207 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4208
AnnaBridge 143:86740a56073b 4209 /* Bit 3 : Enable PPI channel 3. */
AnnaBridge 143:86740a56073b 4210 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 4211 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 4212 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4213 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4214 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4215
AnnaBridge 143:86740a56073b 4216 /* Bit 2 : Enable PPI channel 2. */
AnnaBridge 143:86740a56073b 4217 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 4218 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 4219 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4220 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4221 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4222
AnnaBridge 143:86740a56073b 4223 /* Bit 1 : Enable PPI channel 1. */
AnnaBridge 143:86740a56073b 4224 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 4225 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 4226 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4227 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4228 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4229
AnnaBridge 143:86740a56073b 4230 /* Bit 0 : Enable PPI channel 0. */
AnnaBridge 143:86740a56073b 4231 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 4232 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 4233 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4234 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4235 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
AnnaBridge 143:86740a56073b 4236
AnnaBridge 143:86740a56073b 4237 /* Register: PPI_CHENCLR */
AnnaBridge 143:86740a56073b 4238 /* Description: Channel enable clear. */
AnnaBridge 143:86740a56073b 4239
AnnaBridge 143:86740a56073b 4240 /* Bit 31 : Disable PPI channel 31. */
AnnaBridge 143:86740a56073b 4241 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 4242 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 4243 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4244 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4245 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4246
AnnaBridge 143:86740a56073b 4247 /* Bit 30 : Disable PPI channel 30. */
AnnaBridge 143:86740a56073b 4248 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 4249 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 4250 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4251 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4252 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4253
AnnaBridge 143:86740a56073b 4254 /* Bit 29 : Disable PPI channel 29. */
AnnaBridge 143:86740a56073b 4255 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 4256 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 4257 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4258 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4259 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4260
AnnaBridge 143:86740a56073b 4261 /* Bit 28 : Disable PPI channel 28. */
AnnaBridge 143:86740a56073b 4262 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 4263 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 4264 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4265 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4266 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4267
AnnaBridge 143:86740a56073b 4268 /* Bit 27 : Disable PPI channel 27. */
AnnaBridge 143:86740a56073b 4269 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 4270 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 4271 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4272 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4273 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4274
AnnaBridge 143:86740a56073b 4275 /* Bit 26 : Disable PPI channel 26. */
AnnaBridge 143:86740a56073b 4276 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 4277 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 4278 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4279 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4280 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4281
AnnaBridge 143:86740a56073b 4282 /* Bit 25 : Disable PPI channel 25. */
AnnaBridge 143:86740a56073b 4283 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 4284 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 4285 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4286 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4287 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4288
AnnaBridge 143:86740a56073b 4289 /* Bit 24 : Disable PPI channel 24. */
AnnaBridge 143:86740a56073b 4290 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 4291 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 4292 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4293 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4294 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4295
AnnaBridge 143:86740a56073b 4296 /* Bit 23 : Disable PPI channel 23. */
AnnaBridge 143:86740a56073b 4297 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 4298 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 4299 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4300 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4301 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4302
AnnaBridge 143:86740a56073b 4303 /* Bit 22 : Disable PPI channel 22. */
AnnaBridge 143:86740a56073b 4304 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 4305 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 4306 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4307 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4308 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4309
AnnaBridge 143:86740a56073b 4310 /* Bit 21 : Disable PPI channel 21. */
AnnaBridge 143:86740a56073b 4311 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 4312 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 4313 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4314 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4315 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4316
AnnaBridge 143:86740a56073b 4317 /* Bit 20 : Disable PPI channel 20. */
AnnaBridge 143:86740a56073b 4318 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 4319 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 4320 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4321 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4322 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4323
AnnaBridge 143:86740a56073b 4324 /* Bit 15 : Disable PPI channel 15. */
AnnaBridge 143:86740a56073b 4325 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 4326 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 4327 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4328 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4329 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4330
AnnaBridge 143:86740a56073b 4331 /* Bit 14 : Disable PPI channel 14. */
AnnaBridge 143:86740a56073b 4332 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 4333 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 4334 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4335 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4336 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4337
AnnaBridge 143:86740a56073b 4338 /* Bit 13 : Disable PPI channel 13. */
AnnaBridge 143:86740a56073b 4339 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 4340 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 4341 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4342 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4343 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4344
AnnaBridge 143:86740a56073b 4345 /* Bit 12 : Disable PPI channel 12. */
AnnaBridge 143:86740a56073b 4346 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 4347 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 4348 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4349 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4350 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4351
AnnaBridge 143:86740a56073b 4352 /* Bit 11 : Disable PPI channel 11. */
AnnaBridge 143:86740a56073b 4353 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 4354 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 4355 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4356 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4357 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4358
AnnaBridge 143:86740a56073b 4359 /* Bit 10 : Disable PPI channel 10. */
AnnaBridge 143:86740a56073b 4360 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 4361 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 4362 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4363 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4364 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4365
AnnaBridge 143:86740a56073b 4366 /* Bit 9 : Disable PPI channel 9. */
AnnaBridge 143:86740a56073b 4367 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 4368 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 4369 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4370 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4371 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4372
AnnaBridge 143:86740a56073b 4373 /* Bit 8 : Disable PPI channel 8. */
AnnaBridge 143:86740a56073b 4374 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 4375 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 4376 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4377 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4378 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4379
AnnaBridge 143:86740a56073b 4380 /* Bit 7 : Disable PPI channel 7. */
AnnaBridge 143:86740a56073b 4381 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 4382 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 4383 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4384 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4385 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4386
AnnaBridge 143:86740a56073b 4387 /* Bit 6 : Disable PPI channel 6. */
AnnaBridge 143:86740a56073b 4388 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 4389 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 4390 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4391 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4392 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4393
AnnaBridge 143:86740a56073b 4394 /* Bit 5 : Disable PPI channel 5. */
AnnaBridge 143:86740a56073b 4395 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 4396 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 4397 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4398 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4399 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4400
AnnaBridge 143:86740a56073b 4401 /* Bit 4 : Disable PPI channel 4. */
AnnaBridge 143:86740a56073b 4402 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 4403 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 4404 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4405 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4406 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4407
AnnaBridge 143:86740a56073b 4408 /* Bit 3 : Disable PPI channel 3. */
AnnaBridge 143:86740a56073b 4409 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 4410 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 4411 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4412 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4413 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4414
AnnaBridge 143:86740a56073b 4415 /* Bit 2 : Disable PPI channel 2. */
AnnaBridge 143:86740a56073b 4416 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 4417 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 4418 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4419 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4420 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4421
AnnaBridge 143:86740a56073b 4422 /* Bit 1 : Disable PPI channel 1. */
AnnaBridge 143:86740a56073b 4423 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 4424 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 4425 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4426 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4427 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4428
AnnaBridge 143:86740a56073b 4429 /* Bit 0 : Disable PPI channel 0. */
AnnaBridge 143:86740a56073b 4430 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 4431 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 4432 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
AnnaBridge 143:86740a56073b 4433 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
AnnaBridge 143:86740a56073b 4434 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
AnnaBridge 143:86740a56073b 4435
AnnaBridge 143:86740a56073b 4436 /* Register: PPI_CHG */
AnnaBridge 143:86740a56073b 4437 /* Description: Channel group configuration. */
AnnaBridge 143:86740a56073b 4438
AnnaBridge 143:86740a56073b 4439 /* Bit 31 : Include CH31 in channel group. */
AnnaBridge 143:86740a56073b 4440 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
AnnaBridge 143:86740a56073b 4441 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
AnnaBridge 143:86740a56073b 4442 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4443 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4444
AnnaBridge 143:86740a56073b 4445 /* Bit 30 : Include CH30 in channel group. */
AnnaBridge 143:86740a56073b 4446 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
AnnaBridge 143:86740a56073b 4447 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
AnnaBridge 143:86740a56073b 4448 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4449 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4450
AnnaBridge 143:86740a56073b 4451 /* Bit 29 : Include CH29 in channel group. */
AnnaBridge 143:86740a56073b 4452 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
AnnaBridge 143:86740a56073b 4453 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
AnnaBridge 143:86740a56073b 4454 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4455 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4456
AnnaBridge 143:86740a56073b 4457 /* Bit 28 : Include CH28 in channel group. */
AnnaBridge 143:86740a56073b 4458 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
AnnaBridge 143:86740a56073b 4459 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
AnnaBridge 143:86740a56073b 4460 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4461 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4462
AnnaBridge 143:86740a56073b 4463 /* Bit 27 : Include CH27 in channel group. */
AnnaBridge 143:86740a56073b 4464 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
AnnaBridge 143:86740a56073b 4465 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
AnnaBridge 143:86740a56073b 4466 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4467 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4468
AnnaBridge 143:86740a56073b 4469 /* Bit 26 : Include CH26 in channel group. */
AnnaBridge 143:86740a56073b 4470 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
AnnaBridge 143:86740a56073b 4471 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
AnnaBridge 143:86740a56073b 4472 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4473 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4474
AnnaBridge 143:86740a56073b 4475 /* Bit 25 : Include CH25 in channel group. */
AnnaBridge 143:86740a56073b 4476 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
AnnaBridge 143:86740a56073b 4477 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
AnnaBridge 143:86740a56073b 4478 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4479 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4480
AnnaBridge 143:86740a56073b 4481 /* Bit 24 : Include CH24 in channel group. */
AnnaBridge 143:86740a56073b 4482 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
AnnaBridge 143:86740a56073b 4483 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
AnnaBridge 143:86740a56073b 4484 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4485 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4486
AnnaBridge 143:86740a56073b 4487 /* Bit 23 : Include CH23 in channel group. */
AnnaBridge 143:86740a56073b 4488 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
AnnaBridge 143:86740a56073b 4489 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
AnnaBridge 143:86740a56073b 4490 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4491 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4492
AnnaBridge 143:86740a56073b 4493 /* Bit 22 : Include CH22 in channel group. */
AnnaBridge 143:86740a56073b 4494 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
AnnaBridge 143:86740a56073b 4495 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
AnnaBridge 143:86740a56073b 4496 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4497 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4498
AnnaBridge 143:86740a56073b 4499 /* Bit 21 : Include CH21 in channel group. */
AnnaBridge 143:86740a56073b 4500 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
AnnaBridge 143:86740a56073b 4501 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
AnnaBridge 143:86740a56073b 4502 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4503 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4504
AnnaBridge 143:86740a56073b 4505 /* Bit 20 : Include CH20 in channel group. */
AnnaBridge 143:86740a56073b 4506 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
AnnaBridge 143:86740a56073b 4507 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
AnnaBridge 143:86740a56073b 4508 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4509 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4510
AnnaBridge 143:86740a56073b 4511 /* Bit 15 : Include CH15 in channel group. */
AnnaBridge 143:86740a56073b 4512 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
AnnaBridge 143:86740a56073b 4513 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
AnnaBridge 143:86740a56073b 4514 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4515 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4516
AnnaBridge 143:86740a56073b 4517 /* Bit 14 : Include CH14 in channel group. */
AnnaBridge 143:86740a56073b 4518 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
AnnaBridge 143:86740a56073b 4519 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
AnnaBridge 143:86740a56073b 4520 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4521 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4522
AnnaBridge 143:86740a56073b 4523 /* Bit 13 : Include CH13 in channel group. */
AnnaBridge 143:86740a56073b 4524 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
AnnaBridge 143:86740a56073b 4525 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
AnnaBridge 143:86740a56073b 4526 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4527 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4528
AnnaBridge 143:86740a56073b 4529 /* Bit 12 : Include CH12 in channel group. */
AnnaBridge 143:86740a56073b 4530 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
AnnaBridge 143:86740a56073b 4531 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
AnnaBridge 143:86740a56073b 4532 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4533 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4534
AnnaBridge 143:86740a56073b 4535 /* Bit 11 : Include CH11 in channel group. */
AnnaBridge 143:86740a56073b 4536 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
AnnaBridge 143:86740a56073b 4537 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
AnnaBridge 143:86740a56073b 4538 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4539 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4540
AnnaBridge 143:86740a56073b 4541 /* Bit 10 : Include CH10 in channel group. */
AnnaBridge 143:86740a56073b 4542 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
AnnaBridge 143:86740a56073b 4543 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
AnnaBridge 143:86740a56073b 4544 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4545 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4546
AnnaBridge 143:86740a56073b 4547 /* Bit 9 : Include CH9 in channel group. */
AnnaBridge 143:86740a56073b 4548 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
AnnaBridge 143:86740a56073b 4549 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
AnnaBridge 143:86740a56073b 4550 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4551 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4552
AnnaBridge 143:86740a56073b 4553 /* Bit 8 : Include CH8 in channel group. */
AnnaBridge 143:86740a56073b 4554 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
AnnaBridge 143:86740a56073b 4555 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
AnnaBridge 143:86740a56073b 4556 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4557 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4558
AnnaBridge 143:86740a56073b 4559 /* Bit 7 : Include CH7 in channel group. */
AnnaBridge 143:86740a56073b 4560 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
AnnaBridge 143:86740a56073b 4561 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
AnnaBridge 143:86740a56073b 4562 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4563 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4564
AnnaBridge 143:86740a56073b 4565 /* Bit 6 : Include CH6 in channel group. */
AnnaBridge 143:86740a56073b 4566 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
AnnaBridge 143:86740a56073b 4567 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
AnnaBridge 143:86740a56073b 4568 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4569 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4570
AnnaBridge 143:86740a56073b 4571 /* Bit 5 : Include CH5 in channel group. */
AnnaBridge 143:86740a56073b 4572 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
AnnaBridge 143:86740a56073b 4573 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
AnnaBridge 143:86740a56073b 4574 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4575 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4576
AnnaBridge 143:86740a56073b 4577 /* Bit 4 : Include CH4 in channel group. */
AnnaBridge 143:86740a56073b 4578 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
AnnaBridge 143:86740a56073b 4579 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
AnnaBridge 143:86740a56073b 4580 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4581 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4582
AnnaBridge 143:86740a56073b 4583 /* Bit 3 : Include CH3 in channel group. */
AnnaBridge 143:86740a56073b 4584 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
AnnaBridge 143:86740a56073b 4585 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
AnnaBridge 143:86740a56073b 4586 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4587 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4588
AnnaBridge 143:86740a56073b 4589 /* Bit 2 : Include CH2 in channel group. */
AnnaBridge 143:86740a56073b 4590 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
AnnaBridge 143:86740a56073b 4591 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
AnnaBridge 143:86740a56073b 4592 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4593 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4594
AnnaBridge 143:86740a56073b 4595 /* Bit 1 : Include CH1 in channel group. */
AnnaBridge 143:86740a56073b 4596 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
AnnaBridge 143:86740a56073b 4597 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
AnnaBridge 143:86740a56073b 4598 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4599 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4600
AnnaBridge 143:86740a56073b 4601 /* Bit 0 : Include CH0 in channel group. */
AnnaBridge 143:86740a56073b 4602 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
AnnaBridge 143:86740a56073b 4603 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
AnnaBridge 143:86740a56073b 4604 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
AnnaBridge 143:86740a56073b 4605 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
AnnaBridge 143:86740a56073b 4606
AnnaBridge 143:86740a56073b 4607
AnnaBridge 143:86740a56073b 4608 /* Peripheral: QDEC */
AnnaBridge 143:86740a56073b 4609 /* Description: Rotary decoder. */
AnnaBridge 143:86740a56073b 4610
AnnaBridge 143:86740a56073b 4611 /* Register: QDEC_SHORTS */
AnnaBridge 143:86740a56073b 4612 /* Description: Shortcuts for the QDEC. */
AnnaBridge 143:86740a56073b 4613
AnnaBridge 143:86740a56073b 4614 /* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
AnnaBridge 143:86740a56073b 4615 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
AnnaBridge 143:86740a56073b 4616 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
AnnaBridge 143:86740a56073b 4617 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4618 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4619
AnnaBridge 143:86740a56073b 4620 /* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
AnnaBridge 143:86740a56073b 4621 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
AnnaBridge 143:86740a56073b 4622 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
AnnaBridge 143:86740a56073b 4623 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4624 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4625
AnnaBridge 143:86740a56073b 4626 /* Register: QDEC_INTENSET */
AnnaBridge 143:86740a56073b 4627 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 4628
AnnaBridge 143:86740a56073b 4629 /* Bit 2 : Enable interrupt on ACCOF event. */
AnnaBridge 143:86740a56073b 4630 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
AnnaBridge 143:86740a56073b 4631 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
AnnaBridge 143:86740a56073b 4632 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4633 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4634 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4635
AnnaBridge 143:86740a56073b 4636 /* Bit 1 : Enable interrupt on REPORTRDY event. */
AnnaBridge 143:86740a56073b 4637 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
AnnaBridge 143:86740a56073b 4638 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
AnnaBridge 143:86740a56073b 4639 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4640 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4641 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4642
AnnaBridge 143:86740a56073b 4643 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
AnnaBridge 143:86740a56073b 4644 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 4645 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 4646 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4647 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4648 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4649
AnnaBridge 143:86740a56073b 4650 /* Register: QDEC_INTENCLR */
AnnaBridge 143:86740a56073b 4651 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 4652
AnnaBridge 143:86740a56073b 4653 /* Bit 2 : Disable interrupt on ACCOF event. */
AnnaBridge 143:86740a56073b 4654 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
AnnaBridge 143:86740a56073b 4655 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
AnnaBridge 143:86740a56073b 4656 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4657 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4658 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4659
AnnaBridge 143:86740a56073b 4660 /* Bit 1 : Disable interrupt on REPORTRDY event. */
AnnaBridge 143:86740a56073b 4661 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
AnnaBridge 143:86740a56073b 4662 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
AnnaBridge 143:86740a56073b 4663 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4664 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4665 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4666
AnnaBridge 143:86740a56073b 4667 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
AnnaBridge 143:86740a56073b 4668 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 4669 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
AnnaBridge 143:86740a56073b 4670 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4671 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4672 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4673
AnnaBridge 143:86740a56073b 4674 /* Register: QDEC_ENABLE */
AnnaBridge 143:86740a56073b 4675 /* Description: Enable the QDEC. */
AnnaBridge 143:86740a56073b 4676
AnnaBridge 143:86740a56073b 4677 /* Bit 0 : Enable or disable QDEC. */
AnnaBridge 143:86740a56073b 4678 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 4679 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 4680 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
AnnaBridge 143:86740a56073b 4681 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
AnnaBridge 143:86740a56073b 4682
AnnaBridge 143:86740a56073b 4683 /* Register: QDEC_LEDPOL */
AnnaBridge 143:86740a56073b 4684 /* Description: LED output pin polarity. */
AnnaBridge 143:86740a56073b 4685
AnnaBridge 143:86740a56073b 4686 /* Bit 0 : LED output pin polarity. */
AnnaBridge 143:86740a56073b 4687 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
AnnaBridge 143:86740a56073b 4688 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
AnnaBridge 143:86740a56073b 4689 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
AnnaBridge 143:86740a56073b 4690 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
AnnaBridge 143:86740a56073b 4691
AnnaBridge 143:86740a56073b 4692 /* Register: QDEC_SAMPLEPER */
AnnaBridge 143:86740a56073b 4693 /* Description: Sample period. */
AnnaBridge 143:86740a56073b 4694
AnnaBridge 143:86740a56073b 4695 /* Bits 2..0 : Sample period. */
AnnaBridge 143:86740a56073b 4696 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
AnnaBridge 143:86740a56073b 4697 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
AnnaBridge 143:86740a56073b 4698 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
AnnaBridge 143:86740a56073b 4699 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
AnnaBridge 143:86740a56073b 4700 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
AnnaBridge 143:86740a56073b 4701 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
AnnaBridge 143:86740a56073b 4702 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
AnnaBridge 143:86740a56073b 4703 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
AnnaBridge 143:86740a56073b 4704 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
AnnaBridge 143:86740a56073b 4705 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
AnnaBridge 143:86740a56073b 4706
AnnaBridge 143:86740a56073b 4707 /* Register: QDEC_SAMPLE */
AnnaBridge 143:86740a56073b 4708 /* Description: Motion sample value. */
AnnaBridge 143:86740a56073b 4709
AnnaBridge 143:86740a56073b 4710 /* Bits 31..0 : Last sample taken in compliment to 2. */
AnnaBridge 143:86740a56073b 4711 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
AnnaBridge 143:86740a56073b 4712 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
AnnaBridge 143:86740a56073b 4713
AnnaBridge 143:86740a56073b 4714 /* Register: QDEC_REPORTPER */
AnnaBridge 143:86740a56073b 4715 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
AnnaBridge 143:86740a56073b 4716
AnnaBridge 143:86740a56073b 4717 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
AnnaBridge 143:86740a56073b 4718 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
AnnaBridge 143:86740a56073b 4719 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
AnnaBridge 143:86740a56073b 4720 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
AnnaBridge 143:86740a56073b 4721 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
AnnaBridge 143:86740a56073b 4722 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
AnnaBridge 143:86740a56073b 4723 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
AnnaBridge 143:86740a56073b 4724 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
AnnaBridge 143:86740a56073b 4725 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
AnnaBridge 143:86740a56073b 4726 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
AnnaBridge 143:86740a56073b 4727 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
AnnaBridge 143:86740a56073b 4728
AnnaBridge 143:86740a56073b 4729 /* Register: QDEC_DBFEN */
AnnaBridge 143:86740a56073b 4730 /* Description: Enable debouncer input filters. */
AnnaBridge 143:86740a56073b 4731
AnnaBridge 143:86740a56073b 4732 /* Bit 0 : Enable debounce input filters. */
AnnaBridge 143:86740a56073b 4733 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
AnnaBridge 143:86740a56073b 4734 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
AnnaBridge 143:86740a56073b 4735 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
AnnaBridge 143:86740a56073b 4736 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
AnnaBridge 143:86740a56073b 4737
AnnaBridge 143:86740a56073b 4738 /* Register: QDEC_LEDPRE */
AnnaBridge 143:86740a56073b 4739 /* Description: Time LED is switched ON before the sample. */
AnnaBridge 143:86740a56073b 4740
AnnaBridge 143:86740a56073b 4741 /* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
AnnaBridge 143:86740a56073b 4742 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
AnnaBridge 143:86740a56073b 4743 #define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
AnnaBridge 143:86740a56073b 4744
AnnaBridge 143:86740a56073b 4745 /* Register: QDEC_ACCDBL */
AnnaBridge 143:86740a56073b 4746 /* Description: Accumulated double (error) transitions register. */
AnnaBridge 143:86740a56073b 4747
AnnaBridge 143:86740a56073b 4748 /* Bits 3..0 : Accumulated double (error) transitions. */
AnnaBridge 143:86740a56073b 4749 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
AnnaBridge 143:86740a56073b 4750 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
AnnaBridge 143:86740a56073b 4751
AnnaBridge 143:86740a56073b 4752 /* Register: QDEC_ACCDBLREAD */
AnnaBridge 143:86740a56073b 4753 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
AnnaBridge 143:86740a56073b 4754
AnnaBridge 143:86740a56073b 4755 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
AnnaBridge 143:86740a56073b 4756 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
AnnaBridge 143:86740a56073b 4757 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
AnnaBridge 143:86740a56073b 4758
AnnaBridge 143:86740a56073b 4759 /* Register: QDEC_POWER */
AnnaBridge 143:86740a56073b 4760 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 4761
AnnaBridge 143:86740a56073b 4762 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 4763 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 4764 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 4765 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 4766 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 4767
AnnaBridge 143:86740a56073b 4768
AnnaBridge 143:86740a56073b 4769 /* Peripheral: RADIO */
AnnaBridge 143:86740a56073b 4770 /* Description: The radio. */
AnnaBridge 143:86740a56073b 4771
AnnaBridge 143:86740a56073b 4772 /* Register: RADIO_SHORTS */
AnnaBridge 143:86740a56073b 4773 /* Description: Shortcuts for the radio. */
AnnaBridge 143:86740a56073b 4774
AnnaBridge 143:86740a56073b 4775 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
AnnaBridge 143:86740a56073b 4776 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
AnnaBridge 143:86740a56073b 4777 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
AnnaBridge 143:86740a56073b 4778 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4779 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4780
AnnaBridge 143:86740a56073b 4781 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
AnnaBridge 143:86740a56073b 4782 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
AnnaBridge 143:86740a56073b 4783 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
AnnaBridge 143:86740a56073b 4784 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4785 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4786
AnnaBridge 143:86740a56073b 4787 /* Bit 5 : Shortcut between END event and START task. */
AnnaBridge 143:86740a56073b 4788 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
AnnaBridge 143:86740a56073b 4789 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
AnnaBridge 143:86740a56073b 4790 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4791 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4792
AnnaBridge 143:86740a56073b 4793 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
AnnaBridge 143:86740a56073b 4794 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
AnnaBridge 143:86740a56073b 4795 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
AnnaBridge 143:86740a56073b 4796 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4797 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4798
AnnaBridge 143:86740a56073b 4799 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
AnnaBridge 143:86740a56073b 4800 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
AnnaBridge 143:86740a56073b 4801 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
AnnaBridge 143:86740a56073b 4802 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4803 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4804
AnnaBridge 143:86740a56073b 4805 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
AnnaBridge 143:86740a56073b 4806 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
AnnaBridge 143:86740a56073b 4807 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
AnnaBridge 143:86740a56073b 4808 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4809 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4810
AnnaBridge 143:86740a56073b 4811 /* Bit 1 : Shortcut between END event and DISABLE task. */
AnnaBridge 143:86740a56073b 4812 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
AnnaBridge 143:86740a56073b 4813 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
AnnaBridge 143:86740a56073b 4814 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4815 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4816
AnnaBridge 143:86740a56073b 4817 /* Bit 0 : Shortcut between READY event and START task. */
AnnaBridge 143:86740a56073b 4818 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
AnnaBridge 143:86740a56073b 4819 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
AnnaBridge 143:86740a56073b 4820 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 4821 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 4822
AnnaBridge 143:86740a56073b 4823 /* Register: RADIO_INTENSET */
AnnaBridge 143:86740a56073b 4824 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 4825
AnnaBridge 143:86740a56073b 4826 /* Bit 10 : Enable interrupt on BCMATCH event. */
AnnaBridge 143:86740a56073b 4827 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
AnnaBridge 143:86740a56073b 4828 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
AnnaBridge 143:86740a56073b 4829 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4830 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4831 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4832
AnnaBridge 143:86740a56073b 4833 /* Bit 7 : Enable interrupt on RSSIEND event. */
AnnaBridge 143:86740a56073b 4834 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
AnnaBridge 143:86740a56073b 4835 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
AnnaBridge 143:86740a56073b 4836 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4837 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4838 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4839
AnnaBridge 143:86740a56073b 4840 /* Bit 6 : Enable interrupt on DEVMISS event. */
AnnaBridge 143:86740a56073b 4841 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
AnnaBridge 143:86740a56073b 4842 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
AnnaBridge 143:86740a56073b 4843 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4844 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4845 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4846
AnnaBridge 143:86740a56073b 4847 /* Bit 5 : Enable interrupt on DEVMATCH event. */
AnnaBridge 143:86740a56073b 4848 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
AnnaBridge 143:86740a56073b 4849 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
AnnaBridge 143:86740a56073b 4850 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4851 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4852 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4853
AnnaBridge 143:86740a56073b 4854 /* Bit 4 : Enable interrupt on DISABLED event. */
AnnaBridge 143:86740a56073b 4855 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
AnnaBridge 143:86740a56073b 4856 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
AnnaBridge 143:86740a56073b 4857 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4858 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4859 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4860
AnnaBridge 143:86740a56073b 4861 /* Bit 3 : Enable interrupt on END event. */
AnnaBridge 143:86740a56073b 4862 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 4863 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 4864 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4865 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4866 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4867
AnnaBridge 143:86740a56073b 4868 /* Bit 2 : Enable interrupt on PAYLOAD event. */
AnnaBridge 143:86740a56073b 4869 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
AnnaBridge 143:86740a56073b 4870 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
AnnaBridge 143:86740a56073b 4871 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4872 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4873 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4874
AnnaBridge 143:86740a56073b 4875 /* Bit 1 : Enable interrupt on ADDRESS event. */
AnnaBridge 143:86740a56073b 4876 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 4877 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 4878 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4879 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4880 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4881
AnnaBridge 143:86740a56073b 4882 /* Bit 0 : Enable interrupt on READY event. */
AnnaBridge 143:86740a56073b 4883 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 4884 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 4885 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4886 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4887 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 4888
AnnaBridge 143:86740a56073b 4889 /* Register: RADIO_INTENCLR */
AnnaBridge 143:86740a56073b 4890 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 4891
AnnaBridge 143:86740a56073b 4892 /* Bit 10 : Disable interrupt on BCMATCH event. */
AnnaBridge 143:86740a56073b 4893 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
AnnaBridge 143:86740a56073b 4894 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
AnnaBridge 143:86740a56073b 4895 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4896 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4897 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4898
AnnaBridge 143:86740a56073b 4899 /* Bit 7 : Disable interrupt on RSSIEND event. */
AnnaBridge 143:86740a56073b 4900 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
AnnaBridge 143:86740a56073b 4901 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
AnnaBridge 143:86740a56073b 4902 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4903 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4904 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4905
AnnaBridge 143:86740a56073b 4906 /* Bit 6 : Disable interrupt on DEVMISS event. */
AnnaBridge 143:86740a56073b 4907 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
AnnaBridge 143:86740a56073b 4908 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
AnnaBridge 143:86740a56073b 4909 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4910 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4911 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4912
AnnaBridge 143:86740a56073b 4913 /* Bit 5 : Disable interrupt on DEVMATCH event. */
AnnaBridge 143:86740a56073b 4914 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
AnnaBridge 143:86740a56073b 4915 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
AnnaBridge 143:86740a56073b 4916 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4917 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4918 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4919
AnnaBridge 143:86740a56073b 4920 /* Bit 4 : Disable interrupt on DISABLED event. */
AnnaBridge 143:86740a56073b 4921 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
AnnaBridge 143:86740a56073b 4922 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
AnnaBridge 143:86740a56073b 4923 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4924 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4925 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4926
AnnaBridge 143:86740a56073b 4927 /* Bit 3 : Disable interrupt on END event. */
AnnaBridge 143:86740a56073b 4928 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 4929 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 4930 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4931 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4932 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4933
AnnaBridge 143:86740a56073b 4934 /* Bit 2 : Disable interrupt on PAYLOAD event. */
AnnaBridge 143:86740a56073b 4935 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
AnnaBridge 143:86740a56073b 4936 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
AnnaBridge 143:86740a56073b 4937 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4938 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4939 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4940
AnnaBridge 143:86740a56073b 4941 /* Bit 1 : Disable interrupt on ADDRESS event. */
AnnaBridge 143:86740a56073b 4942 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 4943 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 4944 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4945 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4946 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4947
AnnaBridge 143:86740a56073b 4948 /* Bit 0 : Disable interrupt on READY event. */
AnnaBridge 143:86740a56073b 4949 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 4950 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 4951 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 4952 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 4953 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 4954
AnnaBridge 143:86740a56073b 4955 /* Register: RADIO_CRCSTATUS */
AnnaBridge 143:86740a56073b 4956 /* Description: CRC status of received packet. */
AnnaBridge 143:86740a56073b 4957
AnnaBridge 143:86740a56073b 4958 /* Bit 0 : CRC status of received packet. */
AnnaBridge 143:86740a56073b 4959 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
AnnaBridge 143:86740a56073b 4960 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
AnnaBridge 143:86740a56073b 4961 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
AnnaBridge 143:86740a56073b 4962 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
AnnaBridge 143:86740a56073b 4963
AnnaBridge 143:86740a56073b 4964 /* Register: RADIO_RXMATCH */
AnnaBridge 143:86740a56073b 4965 /* Description: Received address. */
AnnaBridge 143:86740a56073b 4966
AnnaBridge 143:86740a56073b 4967 /* Bits 2..0 : Logical address in which previous packet was received. */
AnnaBridge 143:86740a56073b 4968 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
AnnaBridge 143:86740a56073b 4969 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
AnnaBridge 143:86740a56073b 4970
AnnaBridge 143:86740a56073b 4971 /* Register: RADIO_RXCRC */
AnnaBridge 143:86740a56073b 4972 /* Description: Received CRC. */
AnnaBridge 143:86740a56073b 4973
AnnaBridge 143:86740a56073b 4974 /* Bits 23..0 : CRC field of previously received packet. */
AnnaBridge 143:86740a56073b 4975 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
AnnaBridge 143:86740a56073b 4976 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
AnnaBridge 143:86740a56073b 4977
AnnaBridge 143:86740a56073b 4978 /* Register: RADIO_DAI */
AnnaBridge 143:86740a56073b 4979 /* Description: Device address match index. */
AnnaBridge 143:86740a56073b 4980
AnnaBridge 143:86740a56073b 4981 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
AnnaBridge 143:86740a56073b 4982 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
AnnaBridge 143:86740a56073b 4983 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
AnnaBridge 143:86740a56073b 4984
AnnaBridge 143:86740a56073b 4985 /* Register: RADIO_FREQUENCY */
AnnaBridge 143:86740a56073b 4986 /* Description: Frequency. */
AnnaBridge 143:86740a56073b 4987
AnnaBridge 143:86740a56073b 4988 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
AnnaBridge 143:86740a56073b 4989 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 4990 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 4991
AnnaBridge 143:86740a56073b 4992 /* Register: RADIO_TXPOWER */
AnnaBridge 143:86740a56073b 4993 /* Description: Output power. */
AnnaBridge 143:86740a56073b 4994
AnnaBridge 143:86740a56073b 4995 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
AnnaBridge 143:86740a56073b 4996 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
AnnaBridge 143:86740a56073b 4997 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
AnnaBridge 143:86740a56073b 4998 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
AnnaBridge 143:86740a56073b 4999 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
AnnaBridge 143:86740a56073b 5000 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
AnnaBridge 143:86740a56073b 5001 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
AnnaBridge 143:86740a56073b 5002 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
AnnaBridge 143:86740a56073b 5003 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
AnnaBridge 143:86740a56073b 5004 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
AnnaBridge 143:86740a56073b 5005 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
AnnaBridge 143:86740a56073b 5006
AnnaBridge 143:86740a56073b 5007 /* Register: RADIO_MODE */
AnnaBridge 143:86740a56073b 5008 /* Description: Data rate and modulation. */
AnnaBridge 143:86740a56073b 5009
AnnaBridge 143:86740a56073b 5010 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
AnnaBridge 143:86740a56073b 5011 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 5012 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 5013 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
AnnaBridge 143:86740a56073b 5014 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
AnnaBridge 143:86740a56073b 5015 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
AnnaBridge 143:86740a56073b 5016 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
AnnaBridge 143:86740a56073b 5017
AnnaBridge 143:86740a56073b 5018 /* Register: RADIO_PCNF0 */
AnnaBridge 143:86740a56073b 5019 /* Description: Packet configuration 0. */
AnnaBridge 143:86740a56073b 5020
AnnaBridge 143:86740a56073b 5021 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
AnnaBridge 143:86740a56073b 5022 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
AnnaBridge 143:86740a56073b 5023 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
AnnaBridge 143:86740a56073b 5024
AnnaBridge 143:86740a56073b 5025 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
AnnaBridge 143:86740a56073b 5026 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
AnnaBridge 143:86740a56073b 5027 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
AnnaBridge 143:86740a56073b 5028
AnnaBridge 143:86740a56073b 5029 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
AnnaBridge 143:86740a56073b 5030 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
AnnaBridge 143:86740a56073b 5031 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
AnnaBridge 143:86740a56073b 5032
AnnaBridge 143:86740a56073b 5033 /* Register: RADIO_PCNF1 */
AnnaBridge 143:86740a56073b 5034 /* Description: Packet configuration 1. */
AnnaBridge 143:86740a56073b 5035
AnnaBridge 143:86740a56073b 5036 /* Bit 25 : Packet whitening enable. */
AnnaBridge 143:86740a56073b 5037 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
AnnaBridge 143:86740a56073b 5038 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
AnnaBridge 143:86740a56073b 5039 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
AnnaBridge 143:86740a56073b 5040 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
AnnaBridge 143:86740a56073b 5041
AnnaBridge 143:86740a56073b 5042 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
AnnaBridge 143:86740a56073b 5043 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
AnnaBridge 143:86740a56073b 5044 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
AnnaBridge 143:86740a56073b 5045 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
AnnaBridge 143:86740a56073b 5046 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
AnnaBridge 143:86740a56073b 5047
AnnaBridge 143:86740a56073b 5048 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
AnnaBridge 143:86740a56073b 5049 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
AnnaBridge 143:86740a56073b 5050 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
AnnaBridge 143:86740a56073b 5051
AnnaBridge 143:86740a56073b 5052 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
AnnaBridge 143:86740a56073b 5053 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
AnnaBridge 143:86740a56073b 5054 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
AnnaBridge 143:86740a56073b 5055
AnnaBridge 143:86740a56073b 5056 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
AnnaBridge 143:86740a56073b 5057 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
AnnaBridge 143:86740a56073b 5058 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
AnnaBridge 143:86740a56073b 5059
AnnaBridge 143:86740a56073b 5060 /* Register: RADIO_PREFIX0 */
AnnaBridge 143:86740a56073b 5061 /* Description: Prefixes bytes for logical addresses 0 to 3. */
AnnaBridge 143:86740a56073b 5062
AnnaBridge 143:86740a56073b 5063 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
AnnaBridge 143:86740a56073b 5064 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
AnnaBridge 143:86740a56073b 5065 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
AnnaBridge 143:86740a56073b 5066
AnnaBridge 143:86740a56073b 5067 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
AnnaBridge 143:86740a56073b 5068 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
AnnaBridge 143:86740a56073b 5069 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
AnnaBridge 143:86740a56073b 5070
AnnaBridge 143:86740a56073b 5071 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
AnnaBridge 143:86740a56073b 5072 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
AnnaBridge 143:86740a56073b 5073 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
AnnaBridge 143:86740a56073b 5074
AnnaBridge 143:86740a56073b 5075 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
AnnaBridge 143:86740a56073b 5076 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
AnnaBridge 143:86740a56073b 5077 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
AnnaBridge 143:86740a56073b 5078
AnnaBridge 143:86740a56073b 5079 /* Register: RADIO_PREFIX1 */
AnnaBridge 143:86740a56073b 5080 /* Description: Prefixes bytes for logical addresses 4 to 7. */
AnnaBridge 143:86740a56073b 5081
AnnaBridge 143:86740a56073b 5082 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
AnnaBridge 143:86740a56073b 5083 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
AnnaBridge 143:86740a56073b 5084 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
AnnaBridge 143:86740a56073b 5085
AnnaBridge 143:86740a56073b 5086 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
AnnaBridge 143:86740a56073b 5087 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
AnnaBridge 143:86740a56073b 5088 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
AnnaBridge 143:86740a56073b 5089
AnnaBridge 143:86740a56073b 5090 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
AnnaBridge 143:86740a56073b 5091 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
AnnaBridge 143:86740a56073b 5092 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
AnnaBridge 143:86740a56073b 5093
AnnaBridge 143:86740a56073b 5094 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
AnnaBridge 143:86740a56073b 5095 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
AnnaBridge 143:86740a56073b 5096 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
AnnaBridge 143:86740a56073b 5097
AnnaBridge 143:86740a56073b 5098 /* Register: RADIO_TXADDRESS */
AnnaBridge 143:86740a56073b 5099 /* Description: Transmit address select. */
AnnaBridge 143:86740a56073b 5100
AnnaBridge 143:86740a56073b 5101 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
AnnaBridge 143:86740a56073b 5102 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
AnnaBridge 143:86740a56073b 5103 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
AnnaBridge 143:86740a56073b 5104
AnnaBridge 143:86740a56073b 5105 /* Register: RADIO_RXADDRESSES */
AnnaBridge 143:86740a56073b 5106 /* Description: Receive address select. */
AnnaBridge 143:86740a56073b 5107
AnnaBridge 143:86740a56073b 5108 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
AnnaBridge 143:86740a56073b 5109 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
AnnaBridge 143:86740a56073b 5110 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
AnnaBridge 143:86740a56073b 5111 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5112 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5113
AnnaBridge 143:86740a56073b 5114 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
AnnaBridge 143:86740a56073b 5115 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
AnnaBridge 143:86740a56073b 5116 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
AnnaBridge 143:86740a56073b 5117 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5118 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5119
AnnaBridge 143:86740a56073b 5120 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
AnnaBridge 143:86740a56073b 5121 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
AnnaBridge 143:86740a56073b 5122 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
AnnaBridge 143:86740a56073b 5123 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5124 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5125
AnnaBridge 143:86740a56073b 5126 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
AnnaBridge 143:86740a56073b 5127 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
AnnaBridge 143:86740a56073b 5128 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
AnnaBridge 143:86740a56073b 5129 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5130 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5131
AnnaBridge 143:86740a56073b 5132 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
AnnaBridge 143:86740a56073b 5133 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
AnnaBridge 143:86740a56073b 5134 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
AnnaBridge 143:86740a56073b 5135 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5136 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5137
AnnaBridge 143:86740a56073b 5138 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
AnnaBridge 143:86740a56073b 5139 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
AnnaBridge 143:86740a56073b 5140 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
AnnaBridge 143:86740a56073b 5141 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5142 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5143
AnnaBridge 143:86740a56073b 5144 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
AnnaBridge 143:86740a56073b 5145 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
AnnaBridge 143:86740a56073b 5146 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
AnnaBridge 143:86740a56073b 5147 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5148 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5149
AnnaBridge 143:86740a56073b 5150 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
AnnaBridge 143:86740a56073b 5151 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
AnnaBridge 143:86740a56073b 5152 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
AnnaBridge 143:86740a56073b 5153 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
AnnaBridge 143:86740a56073b 5154 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
AnnaBridge 143:86740a56073b 5155
AnnaBridge 143:86740a56073b 5156 /* Register: RADIO_CRCCNF */
AnnaBridge 143:86740a56073b 5157 /* Description: CRC configuration. */
AnnaBridge 143:86740a56073b 5158
AnnaBridge 143:86740a56073b 5159 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
AnnaBridge 143:86740a56073b 5160 #define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
AnnaBridge 143:86740a56073b 5161 #define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
AnnaBridge 143:86740a56073b 5162 #define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
AnnaBridge 143:86740a56073b 5163 #define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
AnnaBridge 143:86740a56073b 5164
AnnaBridge 143:86740a56073b 5165 /* Bits 1..0 : CRC length. Decision point: START task. */
AnnaBridge 143:86740a56073b 5166 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
AnnaBridge 143:86740a56073b 5167 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
AnnaBridge 143:86740a56073b 5168 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
AnnaBridge 143:86740a56073b 5169 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
AnnaBridge 143:86740a56073b 5170 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
AnnaBridge 143:86740a56073b 5171 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
AnnaBridge 143:86740a56073b 5172
AnnaBridge 143:86740a56073b 5173 /* Register: RADIO_CRCPOLY */
AnnaBridge 143:86740a56073b 5174 /* Description: CRC polynomial. */
AnnaBridge 143:86740a56073b 5175
AnnaBridge 143:86740a56073b 5176 /* Bits 23..0 : CRC polynomial. Decision point: START task. */
AnnaBridge 143:86740a56073b 5177 #define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
AnnaBridge 143:86740a56073b 5178 #define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
AnnaBridge 143:86740a56073b 5179
AnnaBridge 143:86740a56073b 5180 /* Register: RADIO_CRCINIT */
AnnaBridge 143:86740a56073b 5181 /* Description: CRC initial value. */
AnnaBridge 143:86740a56073b 5182
AnnaBridge 143:86740a56073b 5183 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
AnnaBridge 143:86740a56073b 5184 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
AnnaBridge 143:86740a56073b 5185 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
AnnaBridge 143:86740a56073b 5186
AnnaBridge 143:86740a56073b 5187 /* Register: RADIO_TEST */
AnnaBridge 143:86740a56073b 5188 /* Description: Test features enable register. */
AnnaBridge 143:86740a56073b 5189
AnnaBridge 143:86740a56073b 5190 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
AnnaBridge 143:86740a56073b 5191 #define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
AnnaBridge 143:86740a56073b 5192 #define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
AnnaBridge 143:86740a56073b 5193 #define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
AnnaBridge 143:86740a56073b 5194 #define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
AnnaBridge 143:86740a56073b 5195
AnnaBridge 143:86740a56073b 5196 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
AnnaBridge 143:86740a56073b 5197 #define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
AnnaBridge 143:86740a56073b 5198 #define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
AnnaBridge 143:86740a56073b 5199 #define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
AnnaBridge 143:86740a56073b 5200 #define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
AnnaBridge 143:86740a56073b 5201
AnnaBridge 143:86740a56073b 5202 /* Register: RADIO_TIFS */
AnnaBridge 143:86740a56073b 5203 /* Description: Inter Frame Spacing in microseconds. */
AnnaBridge 143:86740a56073b 5204
AnnaBridge 143:86740a56073b 5205 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
AnnaBridge 143:86740a56073b 5206 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
AnnaBridge 143:86740a56073b 5207 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
AnnaBridge 143:86740a56073b 5208
AnnaBridge 143:86740a56073b 5209 /* Register: RADIO_RSSISAMPLE */
AnnaBridge 143:86740a56073b 5210 /* Description: RSSI sample. */
AnnaBridge 143:86740a56073b 5211
AnnaBridge 143:86740a56073b 5212 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
AnnaBridge 143:86740a56073b 5213 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
AnnaBridge 143:86740a56073b 5214 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
AnnaBridge 143:86740a56073b 5215
AnnaBridge 143:86740a56073b 5216 /* Register: RADIO_STATE */
AnnaBridge 143:86740a56073b 5217 /* Description: Current radio state. */
AnnaBridge 143:86740a56073b 5218
AnnaBridge 143:86740a56073b 5219 /* Bits 3..0 : Current radio state. */
AnnaBridge 143:86740a56073b 5220 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
AnnaBridge 143:86740a56073b 5221 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
AnnaBridge 143:86740a56073b 5222 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
AnnaBridge 143:86740a56073b 5223 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
AnnaBridge 143:86740a56073b 5224 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
AnnaBridge 143:86740a56073b 5225 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
AnnaBridge 143:86740a56073b 5226 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
AnnaBridge 143:86740a56073b 5227 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
AnnaBridge 143:86740a56073b 5228 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
AnnaBridge 143:86740a56073b 5229 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
AnnaBridge 143:86740a56073b 5230 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
AnnaBridge 143:86740a56073b 5231
AnnaBridge 143:86740a56073b 5232 /* Register: RADIO_DATAWHITEIV */
AnnaBridge 143:86740a56073b 5233 /* Description: Data whitening initial value. */
AnnaBridge 143:86740a56073b 5234
AnnaBridge 143:86740a56073b 5235 /* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
AnnaBridge 143:86740a56073b 5236 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
AnnaBridge 143:86740a56073b 5237 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
AnnaBridge 143:86740a56073b 5238
AnnaBridge 143:86740a56073b 5239 /* Register: RADIO_DAP */
AnnaBridge 143:86740a56073b 5240 /* Description: Device address prefix. */
AnnaBridge 143:86740a56073b 5241
AnnaBridge 143:86740a56073b 5242 /* Bits 15..0 : Device address prefix. */
AnnaBridge 143:86740a56073b 5243 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
AnnaBridge 143:86740a56073b 5244 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
AnnaBridge 143:86740a56073b 5245
AnnaBridge 143:86740a56073b 5246 /* Register: RADIO_DACNF */
AnnaBridge 143:86740a56073b 5247 /* Description: Device address match configuration. */
AnnaBridge 143:86740a56073b 5248
AnnaBridge 143:86740a56073b 5249 /* Bit 15 : TxAdd for device address 7. */
AnnaBridge 143:86740a56073b 5250 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
AnnaBridge 143:86740a56073b 5251 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
AnnaBridge 143:86740a56073b 5252
AnnaBridge 143:86740a56073b 5253 /* Bit 14 : TxAdd for device address 6. */
AnnaBridge 143:86740a56073b 5254 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
AnnaBridge 143:86740a56073b 5255 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
AnnaBridge 143:86740a56073b 5256
AnnaBridge 143:86740a56073b 5257 /* Bit 13 : TxAdd for device address 5. */
AnnaBridge 143:86740a56073b 5258 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
AnnaBridge 143:86740a56073b 5259 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
AnnaBridge 143:86740a56073b 5260
AnnaBridge 143:86740a56073b 5261 /* Bit 12 : TxAdd for device address 4. */
AnnaBridge 143:86740a56073b 5262 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
AnnaBridge 143:86740a56073b 5263 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
AnnaBridge 143:86740a56073b 5264
AnnaBridge 143:86740a56073b 5265 /* Bit 11 : TxAdd for device address 3. */
AnnaBridge 143:86740a56073b 5266 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
AnnaBridge 143:86740a56073b 5267 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
AnnaBridge 143:86740a56073b 5268
AnnaBridge 143:86740a56073b 5269 /* Bit 10 : TxAdd for device address 2. */
AnnaBridge 143:86740a56073b 5270 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
AnnaBridge 143:86740a56073b 5271 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
AnnaBridge 143:86740a56073b 5272
AnnaBridge 143:86740a56073b 5273 /* Bit 9 : TxAdd for device address 1. */
AnnaBridge 143:86740a56073b 5274 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
AnnaBridge 143:86740a56073b 5275 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
AnnaBridge 143:86740a56073b 5276
AnnaBridge 143:86740a56073b 5277 /* Bit 8 : TxAdd for device address 0. */
AnnaBridge 143:86740a56073b 5278 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
AnnaBridge 143:86740a56073b 5279 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
AnnaBridge 143:86740a56073b 5280
AnnaBridge 143:86740a56073b 5281 /* Bit 7 : Enable or disable device address matching using device address 7. */
AnnaBridge 143:86740a56073b 5282 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
AnnaBridge 143:86740a56073b 5283 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
AnnaBridge 143:86740a56073b 5284 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5285 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5286
AnnaBridge 143:86740a56073b 5287 /* Bit 6 : Enable or disable device address matching using device address 6. */
AnnaBridge 143:86740a56073b 5288 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
AnnaBridge 143:86740a56073b 5289 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
AnnaBridge 143:86740a56073b 5290 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5291 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5292
AnnaBridge 143:86740a56073b 5293 /* Bit 5 : Enable or disable device address matching using device address 5. */
AnnaBridge 143:86740a56073b 5294 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
AnnaBridge 143:86740a56073b 5295 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
AnnaBridge 143:86740a56073b 5296 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5297 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5298
AnnaBridge 143:86740a56073b 5299 /* Bit 4 : Enable or disable device address matching using device address 4. */
AnnaBridge 143:86740a56073b 5300 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
AnnaBridge 143:86740a56073b 5301 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
AnnaBridge 143:86740a56073b 5302 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5303 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5304
AnnaBridge 143:86740a56073b 5305 /* Bit 3 : Enable or disable device address matching using device address 3. */
AnnaBridge 143:86740a56073b 5306 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
AnnaBridge 143:86740a56073b 5307 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
AnnaBridge 143:86740a56073b 5308 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5309 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5310
AnnaBridge 143:86740a56073b 5311 /* Bit 2 : Enable or disable device address matching using device address 2. */
AnnaBridge 143:86740a56073b 5312 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
AnnaBridge 143:86740a56073b 5313 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
AnnaBridge 143:86740a56073b 5314 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5315 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5316
AnnaBridge 143:86740a56073b 5317 /* Bit 1 : Enable or disable device address matching using device address 1. */
AnnaBridge 143:86740a56073b 5318 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
AnnaBridge 143:86740a56073b 5319 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
AnnaBridge 143:86740a56073b 5320 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5321 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5322
AnnaBridge 143:86740a56073b 5323 /* Bit 0 : Enable or disable device address matching using device address 0. */
AnnaBridge 143:86740a56073b 5324 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
AnnaBridge 143:86740a56073b 5325 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
AnnaBridge 143:86740a56073b 5326 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 5327 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 5328
AnnaBridge 143:86740a56073b 5329 /* Register: RADIO_OVERRIDE0 */
AnnaBridge 143:86740a56073b 5330 /* Description: Trim value override register 0. */
AnnaBridge 143:86740a56073b 5331
AnnaBridge 143:86740a56073b 5332 /* Bits 31..0 : Trim value override 0. */
AnnaBridge 143:86740a56073b 5333 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
AnnaBridge 143:86740a56073b 5334 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
AnnaBridge 143:86740a56073b 5335
AnnaBridge 143:86740a56073b 5336 /* Register: RADIO_OVERRIDE1 */
AnnaBridge 143:86740a56073b 5337 /* Description: Trim value override register 1. */
AnnaBridge 143:86740a56073b 5338
AnnaBridge 143:86740a56073b 5339 /* Bits 31..0 : Trim value override 1. */
AnnaBridge 143:86740a56073b 5340 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
AnnaBridge 143:86740a56073b 5341 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
AnnaBridge 143:86740a56073b 5342
AnnaBridge 143:86740a56073b 5343 /* Register: RADIO_OVERRIDE2 */
AnnaBridge 143:86740a56073b 5344 /* Description: Trim value override register 2. */
AnnaBridge 143:86740a56073b 5345
AnnaBridge 143:86740a56073b 5346 /* Bits 31..0 : Trim value override 2. */
AnnaBridge 143:86740a56073b 5347 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
AnnaBridge 143:86740a56073b 5348 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
AnnaBridge 143:86740a56073b 5349
AnnaBridge 143:86740a56073b 5350 /* Register: RADIO_OVERRIDE3 */
AnnaBridge 143:86740a56073b 5351 /* Description: Trim value override register 3. */
AnnaBridge 143:86740a56073b 5352
AnnaBridge 143:86740a56073b 5353 /* Bits 31..0 : Trim value override 3. */
AnnaBridge 143:86740a56073b 5354 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
AnnaBridge 143:86740a56073b 5355 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
AnnaBridge 143:86740a56073b 5356
AnnaBridge 143:86740a56073b 5357 /* Register: RADIO_OVERRIDE4 */
AnnaBridge 143:86740a56073b 5358 /* Description: Trim value override register 4. */
AnnaBridge 143:86740a56073b 5359
AnnaBridge 143:86740a56073b 5360 /* Bit 31 : Enable or disable override of default trim values. */
AnnaBridge 143:86740a56073b 5361 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 5362 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 5363 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
AnnaBridge 143:86740a56073b 5364 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
AnnaBridge 143:86740a56073b 5365
AnnaBridge 143:86740a56073b 5366 /* Bits 27..0 : Trim value override 4. */
AnnaBridge 143:86740a56073b 5367 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
AnnaBridge 143:86740a56073b 5368 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
AnnaBridge 143:86740a56073b 5369
AnnaBridge 143:86740a56073b 5370 /* Register: RADIO_POWER */
AnnaBridge 143:86740a56073b 5371 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 5372
AnnaBridge 143:86740a56073b 5373 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 5374 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 5375 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 5376 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 5377 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 5378
AnnaBridge 143:86740a56073b 5379
AnnaBridge 143:86740a56073b 5380 /* Peripheral: RNG */
AnnaBridge 143:86740a56073b 5381 /* Description: Random Number Generator. */
AnnaBridge 143:86740a56073b 5382
AnnaBridge 143:86740a56073b 5383 /* Register: RNG_SHORTS */
AnnaBridge 143:86740a56073b 5384 /* Description: Shortcuts for the RNG. */
AnnaBridge 143:86740a56073b 5385
AnnaBridge 143:86740a56073b 5386 /* Bit 0 : Shortcut between VALRDY event and STOP task. */
AnnaBridge 143:86740a56073b 5387 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
AnnaBridge 143:86740a56073b 5388 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
AnnaBridge 143:86740a56073b 5389 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 5390 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 5391
AnnaBridge 143:86740a56073b 5392 /* Register: RNG_INTENSET */
AnnaBridge 143:86740a56073b 5393 /* Description: Interrupt enable set register */
AnnaBridge 143:86740a56073b 5394
AnnaBridge 143:86740a56073b 5395 /* Bit 0 : Enable interrupt on VALRDY event. */
AnnaBridge 143:86740a56073b 5396 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
AnnaBridge 143:86740a56073b 5397 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
AnnaBridge 143:86740a56073b 5398 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5399 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5400 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5401
AnnaBridge 143:86740a56073b 5402 /* Register: RNG_INTENCLR */
AnnaBridge 143:86740a56073b 5403 /* Description: Interrupt enable clear register */
AnnaBridge 143:86740a56073b 5404
AnnaBridge 143:86740a56073b 5405 /* Bit 0 : Disable interrupt on VALRDY event. */
AnnaBridge 143:86740a56073b 5406 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
AnnaBridge 143:86740a56073b 5407 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
AnnaBridge 143:86740a56073b 5408 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5409 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5410 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5411
AnnaBridge 143:86740a56073b 5412 /* Register: RNG_CONFIG */
AnnaBridge 143:86740a56073b 5413 /* Description: Configuration register. */
AnnaBridge 143:86740a56073b 5414
AnnaBridge 143:86740a56073b 5415 /* Bit 0 : Digital error correction enable. */
AnnaBridge 143:86740a56073b 5416 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
AnnaBridge 143:86740a56073b 5417 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
AnnaBridge 143:86740a56073b 5418 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
AnnaBridge 143:86740a56073b 5419 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
AnnaBridge 143:86740a56073b 5420
AnnaBridge 143:86740a56073b 5421 /* Register: RNG_VALUE */
AnnaBridge 143:86740a56073b 5422 /* Description: RNG random number. */
AnnaBridge 143:86740a56073b 5423
AnnaBridge 143:86740a56073b 5424 /* Bits 7..0 : Generated random number. */
AnnaBridge 143:86740a56073b 5425 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
AnnaBridge 143:86740a56073b 5426 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
AnnaBridge 143:86740a56073b 5427
AnnaBridge 143:86740a56073b 5428 /* Register: RNG_POWER */
AnnaBridge 143:86740a56073b 5429 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 5430
AnnaBridge 143:86740a56073b 5431 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 5432 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 5433 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 5434 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 5435 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 5436
AnnaBridge 143:86740a56073b 5437
AnnaBridge 143:86740a56073b 5438 /* Peripheral: RTC */
AnnaBridge 143:86740a56073b 5439 /* Description: Real time counter 0. */
AnnaBridge 143:86740a56073b 5440
AnnaBridge 143:86740a56073b 5441 /* Register: RTC_INTENSET */
AnnaBridge 143:86740a56073b 5442 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 5443
AnnaBridge 143:86740a56073b 5444 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
AnnaBridge 143:86740a56073b 5445 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5446 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5447 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5448 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5449 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5450
AnnaBridge 143:86740a56073b 5451 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
AnnaBridge 143:86740a56073b 5452 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5453 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5454 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5455 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5456 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5457
AnnaBridge 143:86740a56073b 5458 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
AnnaBridge 143:86740a56073b 5459 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5460 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5461 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5462 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5463 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5464
AnnaBridge 143:86740a56073b 5465 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
AnnaBridge 143:86740a56073b 5466 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5467 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5468 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5469 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5470 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5471
AnnaBridge 143:86740a56073b 5472 /* Bit 1 : Enable interrupt on OVRFLW event. */
AnnaBridge 143:86740a56073b 5473 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 5474 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 5475 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5476 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5477 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5478
AnnaBridge 143:86740a56073b 5479 /* Bit 0 : Enable interrupt on TICK event. */
AnnaBridge 143:86740a56073b 5480 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 5481 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 5482 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5483 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5484 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5485
AnnaBridge 143:86740a56073b 5486 /* Register: RTC_INTENCLR */
AnnaBridge 143:86740a56073b 5487 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 5488
AnnaBridge 143:86740a56073b 5489 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
AnnaBridge 143:86740a56073b 5490 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5491 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5492 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5493 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5494 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5495
AnnaBridge 143:86740a56073b 5496 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
AnnaBridge 143:86740a56073b 5497 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5498 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5499 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5500 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5501 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5502
AnnaBridge 143:86740a56073b 5503 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
AnnaBridge 143:86740a56073b 5504 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5505 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5506 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5507 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5508 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5509
AnnaBridge 143:86740a56073b 5510 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
AnnaBridge 143:86740a56073b 5511 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5512 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5513 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5514 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5515 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5516
AnnaBridge 143:86740a56073b 5517 /* Bit 1 : Disable interrupt on OVRFLW event. */
AnnaBridge 143:86740a56073b 5518 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 5519 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 5520 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5521 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5522 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5523
AnnaBridge 143:86740a56073b 5524 /* Bit 0 : Disable interrupt on TICK event. */
AnnaBridge 143:86740a56073b 5525 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 5526 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 5527 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5528 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5529 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5530
AnnaBridge 143:86740a56073b 5531 /* Register: RTC_EVTEN */
AnnaBridge 143:86740a56073b 5532 /* Description: Configures event enable routing to PPI for each RTC event. */
AnnaBridge 143:86740a56073b 5533
AnnaBridge 143:86740a56073b 5534 /* Bit 19 : COMPARE[3] event enable. */
AnnaBridge 143:86740a56073b 5535 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5536 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5537 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5538 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5539
AnnaBridge 143:86740a56073b 5540 /* Bit 18 : COMPARE[2] event enable. */
AnnaBridge 143:86740a56073b 5541 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5542 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5543 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5544 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5545
AnnaBridge 143:86740a56073b 5546 /* Bit 17 : COMPARE[1] event enable. */
AnnaBridge 143:86740a56073b 5547 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5548 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5549 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5550 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5551
AnnaBridge 143:86740a56073b 5552 /* Bit 16 : COMPARE[0] event enable. */
AnnaBridge 143:86740a56073b 5553 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5554 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5555 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5556 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5557
AnnaBridge 143:86740a56073b 5558 /* Bit 1 : OVRFLW event enable. */
AnnaBridge 143:86740a56073b 5559 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 5560 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 5561 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5562 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5563
AnnaBridge 143:86740a56073b 5564 /* Bit 0 : TICK event enable. */
AnnaBridge 143:86740a56073b 5565 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 5566 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 5567 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5568 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5569
AnnaBridge 143:86740a56073b 5570 /* Register: RTC_EVTENSET */
AnnaBridge 143:86740a56073b 5571 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
AnnaBridge 143:86740a56073b 5572
AnnaBridge 143:86740a56073b 5573 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
AnnaBridge 143:86740a56073b 5574 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5575 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5576 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5577 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5578 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
AnnaBridge 143:86740a56073b 5579
AnnaBridge 143:86740a56073b 5580 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
AnnaBridge 143:86740a56073b 5581 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5582 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5583 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5584 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5585 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
AnnaBridge 143:86740a56073b 5586
AnnaBridge 143:86740a56073b 5587 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
AnnaBridge 143:86740a56073b 5588 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5589 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5590 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5591 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5592 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
AnnaBridge 143:86740a56073b 5593
AnnaBridge 143:86740a56073b 5594 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
AnnaBridge 143:86740a56073b 5595 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5596 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5597 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5598 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5599 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
AnnaBridge 143:86740a56073b 5600
AnnaBridge 143:86740a56073b 5601 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
AnnaBridge 143:86740a56073b 5602 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 5603 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 5604 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5605 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5606 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
AnnaBridge 143:86740a56073b 5607
AnnaBridge 143:86740a56073b 5608 /* Bit 0 : Enable routing to PPI of TICK event. */
AnnaBridge 143:86740a56073b 5609 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 5610 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 5611 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5612 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5613 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
AnnaBridge 143:86740a56073b 5614
AnnaBridge 143:86740a56073b 5615 /* Register: RTC_EVTENCLR */
AnnaBridge 143:86740a56073b 5616 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
AnnaBridge 143:86740a56073b 5617
AnnaBridge 143:86740a56073b 5618 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
AnnaBridge 143:86740a56073b 5619 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5620 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 5621 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5622 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5623 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
AnnaBridge 143:86740a56073b 5624
AnnaBridge 143:86740a56073b 5625 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
AnnaBridge 143:86740a56073b 5626 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5627 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 5628 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5629 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5630 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
AnnaBridge 143:86740a56073b 5631
AnnaBridge 143:86740a56073b 5632 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
AnnaBridge 143:86740a56073b 5633 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5634 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 5635 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5636 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5637 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
AnnaBridge 143:86740a56073b 5638
AnnaBridge 143:86740a56073b 5639 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
AnnaBridge 143:86740a56073b 5640 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5641 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 5642 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5643 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5644 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
AnnaBridge 143:86740a56073b 5645
AnnaBridge 143:86740a56073b 5646 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
AnnaBridge 143:86740a56073b 5647 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
AnnaBridge 143:86740a56073b 5648 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
AnnaBridge 143:86740a56073b 5649 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5650 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5651 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
AnnaBridge 143:86740a56073b 5652
AnnaBridge 143:86740a56073b 5653 /* Bit 0 : Disable routing to PPI of TICK event. */
AnnaBridge 143:86740a56073b 5654 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
AnnaBridge 143:86740a56073b 5655 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
AnnaBridge 143:86740a56073b 5656 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
AnnaBridge 143:86740a56073b 5657 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
AnnaBridge 143:86740a56073b 5658 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
AnnaBridge 143:86740a56073b 5659
AnnaBridge 143:86740a56073b 5660 /* Register: RTC_COUNTER */
AnnaBridge 143:86740a56073b 5661 /* Description: Current COUNTER value. */
AnnaBridge 143:86740a56073b 5662
AnnaBridge 143:86740a56073b 5663 /* Bits 23..0 : Counter value. */
AnnaBridge 143:86740a56073b 5664 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
AnnaBridge 143:86740a56073b 5665 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
AnnaBridge 143:86740a56073b 5666
AnnaBridge 143:86740a56073b 5667 /* Register: RTC_PRESCALER */
AnnaBridge 143:86740a56073b 5668 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
AnnaBridge 143:86740a56073b 5669
AnnaBridge 143:86740a56073b 5670 /* Bits 11..0 : RTC PRESCALER value. */
AnnaBridge 143:86740a56073b 5671 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
AnnaBridge 143:86740a56073b 5672 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
AnnaBridge 143:86740a56073b 5673
AnnaBridge 143:86740a56073b 5674 /* Register: RTC_CC */
AnnaBridge 143:86740a56073b 5675 /* Description: Capture/compare registers. */
AnnaBridge 143:86740a56073b 5676
AnnaBridge 143:86740a56073b 5677 /* Bits 23..0 : Compare value. */
AnnaBridge 143:86740a56073b 5678 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
AnnaBridge 143:86740a56073b 5679 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
AnnaBridge 143:86740a56073b 5680
AnnaBridge 143:86740a56073b 5681 /* Register: RTC_POWER */
AnnaBridge 143:86740a56073b 5682 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 5683
AnnaBridge 143:86740a56073b 5684 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 5685 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 5686 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 5687 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 5688 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 5689
AnnaBridge 143:86740a56073b 5690
AnnaBridge 143:86740a56073b 5691 /* Peripheral: SPI */
AnnaBridge 143:86740a56073b 5692 /* Description: SPI master 0. */
AnnaBridge 143:86740a56073b 5693
AnnaBridge 143:86740a56073b 5694 /* Register: SPI_INTENSET */
AnnaBridge 143:86740a56073b 5695 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 5696
AnnaBridge 143:86740a56073b 5697 /* Bit 2 : Enable interrupt on READY event. */
AnnaBridge 143:86740a56073b 5698 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 5699 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 5700 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5701 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5702 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5703
AnnaBridge 143:86740a56073b 5704 /* Register: SPI_INTENCLR */
AnnaBridge 143:86740a56073b 5705 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 5706
AnnaBridge 143:86740a56073b 5707 /* Bit 2 : Disable interrupt on READY event. */
AnnaBridge 143:86740a56073b 5708 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
AnnaBridge 143:86740a56073b 5709 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
AnnaBridge 143:86740a56073b 5710 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5711 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5712 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5713
AnnaBridge 143:86740a56073b 5714 /* Register: SPI_ENABLE */
AnnaBridge 143:86740a56073b 5715 /* Description: Enable SPI. */
AnnaBridge 143:86740a56073b 5716
AnnaBridge 143:86740a56073b 5717 /* Bits 2..0 : Enable or disable SPI. */
AnnaBridge 143:86740a56073b 5718 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 5719 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 5720 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
AnnaBridge 143:86740a56073b 5721 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
AnnaBridge 143:86740a56073b 5722
AnnaBridge 143:86740a56073b 5723 /* Register: SPI_RXD */
AnnaBridge 143:86740a56073b 5724 /* Description: RX data. */
AnnaBridge 143:86740a56073b 5725
AnnaBridge 143:86740a56073b 5726 /* Bits 7..0 : RX data from last transfer. */
AnnaBridge 143:86740a56073b 5727 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
AnnaBridge 143:86740a56073b 5728 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
AnnaBridge 143:86740a56073b 5729
AnnaBridge 143:86740a56073b 5730 /* Register: SPI_TXD */
AnnaBridge 143:86740a56073b 5731 /* Description: TX data. */
AnnaBridge 143:86740a56073b 5732
AnnaBridge 143:86740a56073b 5733 /* Bits 7..0 : TX data for next transfer. */
AnnaBridge 143:86740a56073b 5734 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
AnnaBridge 143:86740a56073b 5735 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
AnnaBridge 143:86740a56073b 5736
AnnaBridge 143:86740a56073b 5737 /* Register: SPI_FREQUENCY */
AnnaBridge 143:86740a56073b 5738 /* Description: SPI frequency */
AnnaBridge 143:86740a56073b 5739
AnnaBridge 143:86740a56073b 5740 /* Bits 31..0 : SPI data rate. */
AnnaBridge 143:86740a56073b 5741 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 5742 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 5743 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
AnnaBridge 143:86740a56073b 5744 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
AnnaBridge 143:86740a56073b 5745 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
AnnaBridge 143:86740a56073b 5746 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
AnnaBridge 143:86740a56073b 5747 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
AnnaBridge 143:86740a56073b 5748 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
AnnaBridge 143:86740a56073b 5749 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
AnnaBridge 143:86740a56073b 5750
AnnaBridge 143:86740a56073b 5751 /* Register: SPI_CONFIG */
AnnaBridge 143:86740a56073b 5752 /* Description: Configuration register. */
AnnaBridge 143:86740a56073b 5753
AnnaBridge 143:86740a56073b 5754 /* Bit 2 : Serial clock (SCK) polarity. */
AnnaBridge 143:86740a56073b 5755 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
AnnaBridge 143:86740a56073b 5756 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
AnnaBridge 143:86740a56073b 5757 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
AnnaBridge 143:86740a56073b 5758 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
AnnaBridge 143:86740a56073b 5759
AnnaBridge 143:86740a56073b 5760 /* Bit 1 : Serial clock (SCK) phase. */
AnnaBridge 143:86740a56073b 5761 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
AnnaBridge 143:86740a56073b 5762 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
AnnaBridge 143:86740a56073b 5763 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
AnnaBridge 143:86740a56073b 5764 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
AnnaBridge 143:86740a56073b 5765
AnnaBridge 143:86740a56073b 5766 /* Bit 0 : Bit order. */
AnnaBridge 143:86740a56073b 5767 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
AnnaBridge 143:86740a56073b 5768 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
AnnaBridge 143:86740a56073b 5769 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
AnnaBridge 143:86740a56073b 5770 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
AnnaBridge 143:86740a56073b 5771
AnnaBridge 143:86740a56073b 5772 /* Register: SPI_POWER */
AnnaBridge 143:86740a56073b 5773 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 5774
AnnaBridge 143:86740a56073b 5775 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 5776 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 5777 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 5778 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 5779 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 5780
AnnaBridge 143:86740a56073b 5781
AnnaBridge 143:86740a56073b 5782 /* Peripheral: SPIM */
AnnaBridge 143:86740a56073b 5783 /* Description: SPI master with easyDMA 1. */
AnnaBridge 143:86740a56073b 5784
AnnaBridge 143:86740a56073b 5785 /* Register: SPIM_INTENSET */
AnnaBridge 143:86740a56073b 5786 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 5787
AnnaBridge 143:86740a56073b 5788 /* Bit 19 : Enable interrupt on STARTED event. */
AnnaBridge 143:86740a56073b 5789 #define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 5790 #define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 5791 #define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5792 #define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5793 #define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5794
AnnaBridge 143:86740a56073b 5795 /* Bit 8 : Enable interrupt on ENDTX event. */
AnnaBridge 143:86740a56073b 5796 #define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 5797 #define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 5798 #define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5799 #define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5800 #define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5801
AnnaBridge 143:86740a56073b 5802 /* Bit 4 : Enable interrupt on ENDRX event. */
AnnaBridge 143:86740a56073b 5803 #define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 5804 #define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 5805 #define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5806 #define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5807 #define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5808
AnnaBridge 143:86740a56073b 5809 /* Bit 1 : Enable interrupt on STOPPED event. */
AnnaBridge 143:86740a56073b 5810 #define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 5811 #define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 5812 #define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5813 #define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5814 #define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5815
AnnaBridge 143:86740a56073b 5816 /* Register: SPIM_INTENCLR */
AnnaBridge 143:86740a56073b 5817 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 5818
AnnaBridge 143:86740a56073b 5819 /* Bit 19 : Disable interrupt on STARTED event. */
AnnaBridge 143:86740a56073b 5820 #define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
AnnaBridge 143:86740a56073b 5821 #define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
AnnaBridge 143:86740a56073b 5822 #define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5823 #define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5824 #define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5825
AnnaBridge 143:86740a56073b 5826 /* Bit 8 : Disable interrupt on ENDTX event. */
AnnaBridge 143:86740a56073b 5827 #define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
AnnaBridge 143:86740a56073b 5828 #define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
AnnaBridge 143:86740a56073b 5829 #define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5830 #define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5831 #define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5832
AnnaBridge 143:86740a56073b 5833 /* Bit 4 : Disable interrupt on ENDRX event. */
AnnaBridge 143:86740a56073b 5834 #define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 5835 #define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 5836 #define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5837 #define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5838 #define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5839
AnnaBridge 143:86740a56073b 5840 /* Bit 1 : Disable interrupt on STOPPED event. */
AnnaBridge 143:86740a56073b 5841 #define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 5842 #define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 5843 #define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5844 #define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5845 #define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5846
AnnaBridge 143:86740a56073b 5847 /* Register: SPIM_ENABLE */
AnnaBridge 143:86740a56073b 5848 /* Description: Enable SPIM. */
AnnaBridge 143:86740a56073b 5849
AnnaBridge 143:86740a56073b 5850 /* Bits 3..0 : Enable or disable SPIM. */
AnnaBridge 143:86740a56073b 5851 #define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 5852 #define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 5853 #define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
AnnaBridge 143:86740a56073b 5854 #define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
AnnaBridge 143:86740a56073b 5855
AnnaBridge 143:86740a56073b 5856 /* Register: SPIM_FREQUENCY */
AnnaBridge 143:86740a56073b 5857 /* Description: SPI frequency. */
AnnaBridge 143:86740a56073b 5858
AnnaBridge 143:86740a56073b 5859 /* Bits 31..0 : SPI master data rate. */
AnnaBridge 143:86740a56073b 5860 #define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 5861 #define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 5862 #define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
AnnaBridge 143:86740a56073b 5863 #define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
AnnaBridge 143:86740a56073b 5864 #define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
AnnaBridge 143:86740a56073b 5865 #define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
AnnaBridge 143:86740a56073b 5866 #define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
AnnaBridge 143:86740a56073b 5867 #define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
AnnaBridge 143:86740a56073b 5868 #define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
AnnaBridge 143:86740a56073b 5869
AnnaBridge 143:86740a56073b 5870 /* Register: SPIM_RXD_PTR */
AnnaBridge 143:86740a56073b 5871 /* Description: Data pointer. */
AnnaBridge 143:86740a56073b 5872
AnnaBridge 143:86740a56073b 5873 /* Bits 31..0 : Data pointer. */
AnnaBridge 143:86740a56073b 5874 #define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 5875 #define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 5876
AnnaBridge 143:86740a56073b 5877 /* Register: SPIM_RXD_MAXCNT */
AnnaBridge 143:86740a56073b 5878 /* Description: Maximum number of buffer bytes to receive. */
AnnaBridge 143:86740a56073b 5879
AnnaBridge 143:86740a56073b 5880 /* Bits 7..0 : Maximum number of buffer bytes to receive. */
AnnaBridge 143:86740a56073b 5881 #define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 5882 #define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 5883
AnnaBridge 143:86740a56073b 5884 /* Register: SPIM_RXD_AMOUNT */
AnnaBridge 143:86740a56073b 5885 /* Description: Number of bytes received in the last transaction. */
AnnaBridge 143:86740a56073b 5886
AnnaBridge 143:86740a56073b 5887 /* Bits 7..0 : Number of bytes received in the last transaction. */
AnnaBridge 143:86740a56073b 5888 #define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 5889 #define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 5890
AnnaBridge 143:86740a56073b 5891 /* Register: SPIM_TXD_PTR */
AnnaBridge 143:86740a56073b 5892 /* Description: Data pointer. */
AnnaBridge 143:86740a56073b 5893
AnnaBridge 143:86740a56073b 5894 /* Bits 31..0 : Data pointer. */
AnnaBridge 143:86740a56073b 5895 #define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
AnnaBridge 143:86740a56073b 5896 #define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
AnnaBridge 143:86740a56073b 5897
AnnaBridge 143:86740a56073b 5898 /* Register: SPIM_TXD_MAXCNT */
AnnaBridge 143:86740a56073b 5899 /* Description: Maximum number of buffer bytes to send. */
AnnaBridge 143:86740a56073b 5900
AnnaBridge 143:86740a56073b 5901 /* Bits 7..0 : Maximum number of buffer bytes to send. */
AnnaBridge 143:86740a56073b 5902 #define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
AnnaBridge 143:86740a56073b 5903 #define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
AnnaBridge 143:86740a56073b 5904
AnnaBridge 143:86740a56073b 5905 /* Register: SPIM_TXD_AMOUNT */
AnnaBridge 143:86740a56073b 5906 /* Description: Number of bytes sent in the last transaction. */
AnnaBridge 143:86740a56073b 5907
AnnaBridge 143:86740a56073b 5908 /* Bits 7..0 : Number of bytes sent in the last transaction. */
AnnaBridge 143:86740a56073b 5909 #define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
AnnaBridge 143:86740a56073b 5910 #define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
AnnaBridge 143:86740a56073b 5911
AnnaBridge 143:86740a56073b 5912 /* Register: SPIM_CONFIG */
AnnaBridge 143:86740a56073b 5913 /* Description: Configuration register. */
AnnaBridge 143:86740a56073b 5914
AnnaBridge 143:86740a56073b 5915 /* Bit 2 : Serial clock (SCK) polarity. */
AnnaBridge 143:86740a56073b 5916 #define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
AnnaBridge 143:86740a56073b 5917 #define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
AnnaBridge 143:86740a56073b 5918 #define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
AnnaBridge 143:86740a56073b 5919 #define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
AnnaBridge 143:86740a56073b 5920
AnnaBridge 143:86740a56073b 5921 /* Bit 1 : Serial clock (SCK) phase. */
AnnaBridge 143:86740a56073b 5922 #define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
AnnaBridge 143:86740a56073b 5923 #define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
AnnaBridge 143:86740a56073b 5924 #define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
AnnaBridge 143:86740a56073b 5925 #define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
AnnaBridge 143:86740a56073b 5926
AnnaBridge 143:86740a56073b 5927 /* Bit 0 : Bit order. */
AnnaBridge 143:86740a56073b 5928 #define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
AnnaBridge 143:86740a56073b 5929 #define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
AnnaBridge 143:86740a56073b 5930 #define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
AnnaBridge 143:86740a56073b 5931 #define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
AnnaBridge 143:86740a56073b 5932
AnnaBridge 143:86740a56073b 5933 /* Register: SPIM_ORC */
AnnaBridge 143:86740a56073b 5934 /* Description: Over-read character. */
AnnaBridge 143:86740a56073b 5935
AnnaBridge 143:86740a56073b 5936 /* Bits 7..0 : Over-read character. */
AnnaBridge 143:86740a56073b 5937 #define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
AnnaBridge 143:86740a56073b 5938 #define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
AnnaBridge 143:86740a56073b 5939
AnnaBridge 143:86740a56073b 5940 /* Register: SPIM_POWER */
AnnaBridge 143:86740a56073b 5941 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 5942
AnnaBridge 143:86740a56073b 5943 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 5944 #define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 5945 #define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 5946 #define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 5947 #define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 5948
AnnaBridge 143:86740a56073b 5949
AnnaBridge 143:86740a56073b 5950 /* Peripheral: SPIS */
AnnaBridge 143:86740a56073b 5951 /* Description: SPI slave 1. */
AnnaBridge 143:86740a56073b 5952
AnnaBridge 143:86740a56073b 5953 /* Register: SPIS_SHORTS */
AnnaBridge 143:86740a56073b 5954 /* Description: Shortcuts for SPIS. */
AnnaBridge 143:86740a56073b 5955
AnnaBridge 143:86740a56073b 5956 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
AnnaBridge 143:86740a56073b 5957 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
AnnaBridge 143:86740a56073b 5958 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
AnnaBridge 143:86740a56073b 5959 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 5960 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 5961
AnnaBridge 143:86740a56073b 5962 /* Register: SPIS_INTENSET */
AnnaBridge 143:86740a56073b 5963 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 5964
AnnaBridge 143:86740a56073b 5965 /* Bit 10 : Enable interrupt on ACQUIRED event. */
AnnaBridge 143:86740a56073b 5966 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
AnnaBridge 143:86740a56073b 5967 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
AnnaBridge 143:86740a56073b 5968 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5969 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5970 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5971
AnnaBridge 143:86740a56073b 5972 /* Bit 4 : enable interrupt on ENDRX event. */
AnnaBridge 143:86740a56073b 5973 #define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 5974 #define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 5975 #define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5976 #define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5977 #define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5978
AnnaBridge 143:86740a56073b 5979 /* Bit 1 : Enable interrupt on END event. */
AnnaBridge 143:86740a56073b 5980 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 5981 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 5982 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5983 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5984 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 5985
AnnaBridge 143:86740a56073b 5986 /* Register: SPIS_INTENCLR */
AnnaBridge 143:86740a56073b 5987 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 5988
AnnaBridge 143:86740a56073b 5989 /* Bit 10 : Disable interrupt on ACQUIRED event. */
AnnaBridge 143:86740a56073b 5990 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
AnnaBridge 143:86740a56073b 5991 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
AnnaBridge 143:86740a56073b 5992 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 5993 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 5994 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 5995
AnnaBridge 143:86740a56073b 5996 /* Bit 4 : Disable interrupt on ENDRX event. */
AnnaBridge 143:86740a56073b 5997 #define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
AnnaBridge 143:86740a56073b 5998 #define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
AnnaBridge 143:86740a56073b 5999 #define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6000 #define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6001 #define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6002
AnnaBridge 143:86740a56073b 6003 /* Bit 1 : Disable interrupt on END event. */
AnnaBridge 143:86740a56073b 6004 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
AnnaBridge 143:86740a56073b 6005 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
AnnaBridge 143:86740a56073b 6006 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6007 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6008 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6009
AnnaBridge 143:86740a56073b 6010 /* Register: SPIS_SEMSTAT */
AnnaBridge 143:86740a56073b 6011 /* Description: Semaphore status. */
AnnaBridge 143:86740a56073b 6012
AnnaBridge 143:86740a56073b 6013 /* Bits 1..0 : Semaphore status. */
AnnaBridge 143:86740a56073b 6014 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
AnnaBridge 143:86740a56073b 6015 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
AnnaBridge 143:86740a56073b 6016 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
AnnaBridge 143:86740a56073b 6017 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
AnnaBridge 143:86740a56073b 6018 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
AnnaBridge 143:86740a56073b 6019 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
AnnaBridge 143:86740a56073b 6020
AnnaBridge 143:86740a56073b 6021 /* Register: SPIS_STATUS */
AnnaBridge 143:86740a56073b 6022 /* Description: Status from last transaction. */
AnnaBridge 143:86740a56073b 6023
AnnaBridge 143:86740a56073b 6024 /* Bit 1 : RX buffer overflow detected, and prevented. */
AnnaBridge 143:86740a56073b 6025 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
AnnaBridge 143:86740a56073b 6026 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
AnnaBridge 143:86740a56073b 6027 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6028 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6029 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
AnnaBridge 143:86740a56073b 6030
AnnaBridge 143:86740a56073b 6031 /* Bit 0 : TX buffer overread detected, and prevented. */
AnnaBridge 143:86740a56073b 6032 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
AnnaBridge 143:86740a56073b 6033 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
AnnaBridge 143:86740a56073b 6034 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6035 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6036 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
AnnaBridge 143:86740a56073b 6037
AnnaBridge 143:86740a56073b 6038 /* Register: SPIS_ENABLE */
AnnaBridge 143:86740a56073b 6039 /* Description: Enable SPIS. */
AnnaBridge 143:86740a56073b 6040
AnnaBridge 143:86740a56073b 6041 /* Bits 2..0 : Enable or disable SPIS. */
AnnaBridge 143:86740a56073b 6042 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 6043 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 6044 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
AnnaBridge 143:86740a56073b 6045 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
AnnaBridge 143:86740a56073b 6046
AnnaBridge 143:86740a56073b 6047 /* Register: SPIS_MAXRX */
AnnaBridge 143:86740a56073b 6048 /* Description: Maximum number of bytes in the receive buffer. */
AnnaBridge 143:86740a56073b 6049
AnnaBridge 143:86740a56073b 6050 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
AnnaBridge 143:86740a56073b 6051 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
AnnaBridge 143:86740a56073b 6052 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
AnnaBridge 143:86740a56073b 6053
AnnaBridge 143:86740a56073b 6054 /* Register: SPIS_AMOUNTRX */
AnnaBridge 143:86740a56073b 6055 /* Description: Number of bytes received in last granted transaction. */
AnnaBridge 143:86740a56073b 6056
AnnaBridge 143:86740a56073b 6057 /* Bits 7..0 : Number of bytes received in last granted transaction. */
AnnaBridge 143:86740a56073b 6058 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
AnnaBridge 143:86740a56073b 6059 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
AnnaBridge 143:86740a56073b 6060
AnnaBridge 143:86740a56073b 6061 /* Register: SPIS_MAXTX */
AnnaBridge 143:86740a56073b 6062 /* Description: Maximum number of bytes in the transmit buffer. */
AnnaBridge 143:86740a56073b 6063
AnnaBridge 143:86740a56073b 6064 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
AnnaBridge 143:86740a56073b 6065 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
AnnaBridge 143:86740a56073b 6066 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
AnnaBridge 143:86740a56073b 6067
AnnaBridge 143:86740a56073b 6068 /* Register: SPIS_AMOUNTTX */
AnnaBridge 143:86740a56073b 6069 /* Description: Number of bytes transmitted in last granted transaction. */
AnnaBridge 143:86740a56073b 6070
AnnaBridge 143:86740a56073b 6071 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
AnnaBridge 143:86740a56073b 6072 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
AnnaBridge 143:86740a56073b 6073 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
AnnaBridge 143:86740a56073b 6074
AnnaBridge 143:86740a56073b 6075 /* Register: SPIS_CONFIG */
AnnaBridge 143:86740a56073b 6076 /* Description: Configuration register. */
AnnaBridge 143:86740a56073b 6077
AnnaBridge 143:86740a56073b 6078 /* Bit 2 : Serial clock (SCK) polarity. */
AnnaBridge 143:86740a56073b 6079 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
AnnaBridge 143:86740a56073b 6080 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
AnnaBridge 143:86740a56073b 6081 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
AnnaBridge 143:86740a56073b 6082 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
AnnaBridge 143:86740a56073b 6083
AnnaBridge 143:86740a56073b 6084 /* Bit 1 : Serial clock (SCK) phase. */
AnnaBridge 143:86740a56073b 6085 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
AnnaBridge 143:86740a56073b 6086 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
AnnaBridge 143:86740a56073b 6087 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
AnnaBridge 143:86740a56073b 6088 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
AnnaBridge 143:86740a56073b 6089
AnnaBridge 143:86740a56073b 6090 /* Bit 0 : Bit order. */
AnnaBridge 143:86740a56073b 6091 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
AnnaBridge 143:86740a56073b 6092 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
AnnaBridge 143:86740a56073b 6093 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
AnnaBridge 143:86740a56073b 6094 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
AnnaBridge 143:86740a56073b 6095
AnnaBridge 143:86740a56073b 6096 /* Register: SPIS_DEF */
AnnaBridge 143:86740a56073b 6097 /* Description: Default character. */
AnnaBridge 143:86740a56073b 6098
AnnaBridge 143:86740a56073b 6099 /* Bits 7..0 : Default character. */
AnnaBridge 143:86740a56073b 6100 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
AnnaBridge 143:86740a56073b 6101 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
AnnaBridge 143:86740a56073b 6102
AnnaBridge 143:86740a56073b 6103 /* Register: SPIS_ORC */
AnnaBridge 143:86740a56073b 6104 /* Description: Over-read character. */
AnnaBridge 143:86740a56073b 6105
AnnaBridge 143:86740a56073b 6106 /* Bits 7..0 : Over-read character. */
AnnaBridge 143:86740a56073b 6107 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
AnnaBridge 143:86740a56073b 6108 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
AnnaBridge 143:86740a56073b 6109
AnnaBridge 143:86740a56073b 6110 /* Register: SPIS_POWER */
AnnaBridge 143:86740a56073b 6111 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 6112
AnnaBridge 143:86740a56073b 6113 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 6114 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 6115 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 6116 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 6117 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 6118
AnnaBridge 143:86740a56073b 6119
AnnaBridge 143:86740a56073b 6120 /* Peripheral: TEMP */
AnnaBridge 143:86740a56073b 6121 /* Description: Temperature Sensor. */
AnnaBridge 143:86740a56073b 6122
AnnaBridge 143:86740a56073b 6123 /* Register: TEMP_INTENSET */
AnnaBridge 143:86740a56073b 6124 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 6125
AnnaBridge 143:86740a56073b 6126 /* Bit 0 : Enable interrupt on DATARDY event. */
AnnaBridge 143:86740a56073b 6127 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
AnnaBridge 143:86740a56073b 6128 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
AnnaBridge 143:86740a56073b 6129 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6130 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6131 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6132
AnnaBridge 143:86740a56073b 6133 /* Register: TEMP_INTENCLR */
AnnaBridge 143:86740a56073b 6134 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 6135
AnnaBridge 143:86740a56073b 6136 /* Bit 0 : Disable interrupt on DATARDY event. */
AnnaBridge 143:86740a56073b 6137 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
AnnaBridge 143:86740a56073b 6138 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
AnnaBridge 143:86740a56073b 6139 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6140 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6141 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6142
AnnaBridge 143:86740a56073b 6143 /* Register: TEMP_POWER */
AnnaBridge 143:86740a56073b 6144 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 6145
AnnaBridge 143:86740a56073b 6146 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 6147 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 6148 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 6149 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 6150 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 6151
AnnaBridge 143:86740a56073b 6152
AnnaBridge 143:86740a56073b 6153 /* Peripheral: TIMER */
AnnaBridge 143:86740a56073b 6154 /* Description: Timer 0. */
AnnaBridge 143:86740a56073b 6155
AnnaBridge 143:86740a56073b 6156 /* Register: TIMER_SHORTS */
AnnaBridge 143:86740a56073b 6157 /* Description: Shortcuts for Timer. */
AnnaBridge 143:86740a56073b 6158
AnnaBridge 143:86740a56073b 6159 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
AnnaBridge 143:86740a56073b 6160 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
AnnaBridge 143:86740a56073b 6161 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
AnnaBridge 143:86740a56073b 6162 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6163 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6164
AnnaBridge 143:86740a56073b 6165 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
AnnaBridge 143:86740a56073b 6166 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
AnnaBridge 143:86740a56073b 6167 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
AnnaBridge 143:86740a56073b 6168 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6169 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6170
AnnaBridge 143:86740a56073b 6171 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
AnnaBridge 143:86740a56073b 6172 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
AnnaBridge 143:86740a56073b 6173 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
AnnaBridge 143:86740a56073b 6174 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6175 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6176
AnnaBridge 143:86740a56073b 6177 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
AnnaBridge 143:86740a56073b 6178 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
AnnaBridge 143:86740a56073b 6179 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
AnnaBridge 143:86740a56073b 6180 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6181 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6182
AnnaBridge 143:86740a56073b 6183 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
AnnaBridge 143:86740a56073b 6184 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
AnnaBridge 143:86740a56073b 6185 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
AnnaBridge 143:86740a56073b 6186 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6187 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6188
AnnaBridge 143:86740a56073b 6189 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
AnnaBridge 143:86740a56073b 6190 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
AnnaBridge 143:86740a56073b 6191 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
AnnaBridge 143:86740a56073b 6192 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6193 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6194
AnnaBridge 143:86740a56073b 6195 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
AnnaBridge 143:86740a56073b 6196 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
AnnaBridge 143:86740a56073b 6197 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
AnnaBridge 143:86740a56073b 6198 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6199 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6200
AnnaBridge 143:86740a56073b 6201 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
AnnaBridge 143:86740a56073b 6202 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
AnnaBridge 143:86740a56073b 6203 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
AnnaBridge 143:86740a56073b 6204 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6205 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6206
AnnaBridge 143:86740a56073b 6207 /* Register: TIMER_INTENSET */
AnnaBridge 143:86740a56073b 6208 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 6209
AnnaBridge 143:86740a56073b 6210 /* Bit 19 : Enable interrupt on COMPARE[3] */
AnnaBridge 143:86740a56073b 6211 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 6212 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 6213 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6214 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6215 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6216
AnnaBridge 143:86740a56073b 6217 /* Bit 18 : Enable interrupt on COMPARE[2] */
AnnaBridge 143:86740a56073b 6218 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 6219 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 6220 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6221 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6222 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6223
AnnaBridge 143:86740a56073b 6224 /* Bit 17 : Enable interrupt on COMPARE[1] */
AnnaBridge 143:86740a56073b 6225 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 6226 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 6227 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6228 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6229 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6230
AnnaBridge 143:86740a56073b 6231 /* Bit 16 : Enable interrupt on COMPARE[0] */
AnnaBridge 143:86740a56073b 6232 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 6233 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 6234 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6235 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6236 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6237
AnnaBridge 143:86740a56073b 6238 /* Register: TIMER_INTENCLR */
AnnaBridge 143:86740a56073b 6239 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 6240
AnnaBridge 143:86740a56073b 6241 /* Bit 19 : Disable interrupt on COMPARE[3] */
AnnaBridge 143:86740a56073b 6242 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
AnnaBridge 143:86740a56073b 6243 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
AnnaBridge 143:86740a56073b 6244 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6245 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6246 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6247
AnnaBridge 143:86740a56073b 6248 /* Bit 18 : Disable interrupt on COMPARE[2] */
AnnaBridge 143:86740a56073b 6249 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
AnnaBridge 143:86740a56073b 6250 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
AnnaBridge 143:86740a56073b 6251 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6252 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6253 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6254
AnnaBridge 143:86740a56073b 6255 /* Bit 17 : Disable interrupt on COMPARE[1] */
AnnaBridge 143:86740a56073b 6256 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
AnnaBridge 143:86740a56073b 6257 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
AnnaBridge 143:86740a56073b 6258 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6259 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6260 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6261
AnnaBridge 143:86740a56073b 6262 /* Bit 16 : Disable interrupt on COMPARE[0] */
AnnaBridge 143:86740a56073b 6263 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
AnnaBridge 143:86740a56073b 6264 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
AnnaBridge 143:86740a56073b 6265 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6266 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6267 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6268
AnnaBridge 143:86740a56073b 6269 /* Register: TIMER_MODE */
AnnaBridge 143:86740a56073b 6270 /* Description: Timer Mode selection. */
AnnaBridge 143:86740a56073b 6271
AnnaBridge 143:86740a56073b 6272 /* Bit 0 : Select Normal or Counter mode. */
AnnaBridge 143:86740a56073b 6273 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
AnnaBridge 143:86740a56073b 6274 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
AnnaBridge 143:86740a56073b 6275 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
AnnaBridge 143:86740a56073b 6276 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
AnnaBridge 143:86740a56073b 6277
AnnaBridge 143:86740a56073b 6278 /* Register: TIMER_BITMODE */
AnnaBridge 143:86740a56073b 6279 /* Description: Sets timer behaviour. */
AnnaBridge 143:86740a56073b 6280
AnnaBridge 143:86740a56073b 6281 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
AnnaBridge 143:86740a56073b 6282 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
AnnaBridge 143:86740a56073b 6283 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
AnnaBridge 143:86740a56073b 6284 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
AnnaBridge 143:86740a56073b 6285 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
AnnaBridge 143:86740a56073b 6286 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
AnnaBridge 143:86740a56073b 6287 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
AnnaBridge 143:86740a56073b 6288
AnnaBridge 143:86740a56073b 6289 /* Register: TIMER_PRESCALER */
AnnaBridge 143:86740a56073b 6290 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
AnnaBridge 143:86740a56073b 6291
AnnaBridge 143:86740a56073b 6292 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
AnnaBridge 143:86740a56073b 6293 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
AnnaBridge 143:86740a56073b 6294 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
AnnaBridge 143:86740a56073b 6295
AnnaBridge 143:86740a56073b 6296 /* Register: TIMER_POWER */
AnnaBridge 143:86740a56073b 6297 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 6298
AnnaBridge 143:86740a56073b 6299 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 6300 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 6301 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 6302 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 6303 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 6304
AnnaBridge 143:86740a56073b 6305
AnnaBridge 143:86740a56073b 6306 /* Peripheral: TWI */
AnnaBridge 143:86740a56073b 6307 /* Description: Two-wire interface master 0. */
AnnaBridge 143:86740a56073b 6308
AnnaBridge 143:86740a56073b 6309 /* Register: TWI_SHORTS */
AnnaBridge 143:86740a56073b 6310 /* Description: Shortcuts for TWI. */
AnnaBridge 143:86740a56073b 6311
AnnaBridge 143:86740a56073b 6312 /* Bit 1 : Shortcut between BB event and the STOP task. */
AnnaBridge 143:86740a56073b 6313 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
AnnaBridge 143:86740a56073b 6314 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
AnnaBridge 143:86740a56073b 6315 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6316 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6317
AnnaBridge 143:86740a56073b 6318 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
AnnaBridge 143:86740a56073b 6319 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
AnnaBridge 143:86740a56073b 6320 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
AnnaBridge 143:86740a56073b 6321 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6322 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6323
AnnaBridge 143:86740a56073b 6324 /* Register: TWI_INTENSET */
AnnaBridge 143:86740a56073b 6325 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 6326
AnnaBridge 143:86740a56073b 6327 /* Bit 18 : Enable interrupt on SUSPENDED event. */
AnnaBridge 143:86740a56073b 6328 #define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 6329 #define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 6330 #define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6331 #define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6332 #define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6333
AnnaBridge 143:86740a56073b 6334 /* Bit 14 : Enable interrupt on BB event. */
AnnaBridge 143:86740a56073b 6335 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
AnnaBridge 143:86740a56073b 6336 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
AnnaBridge 143:86740a56073b 6337 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6338 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6339 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6340
AnnaBridge 143:86740a56073b 6341 /* Bit 9 : Enable interrupt on ERROR event. */
AnnaBridge 143:86740a56073b 6342 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6343 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6344 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6345 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6346 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6347
AnnaBridge 143:86740a56073b 6348 /* Bit 7 : Enable interrupt on TXDSENT event. */
AnnaBridge 143:86740a56073b 6349 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
AnnaBridge 143:86740a56073b 6350 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
AnnaBridge 143:86740a56073b 6351 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6352 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6353 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6354
AnnaBridge 143:86740a56073b 6355 /* Bit 2 : Enable interrupt on READY event. */
AnnaBridge 143:86740a56073b 6356 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
AnnaBridge 143:86740a56073b 6357 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
AnnaBridge 143:86740a56073b 6358 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6359 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6360 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6361
AnnaBridge 143:86740a56073b 6362 /* Bit 1 : Enable interrupt on STOPPED event. */
AnnaBridge 143:86740a56073b 6363 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 6364 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 6365 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6366 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6367 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6368
AnnaBridge 143:86740a56073b 6369 /* Register: TWI_INTENCLR */
AnnaBridge 143:86740a56073b 6370 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 6371
AnnaBridge 143:86740a56073b 6372 /* Bit 18 : Disable interrupt on SUSPENDED event. */
AnnaBridge 143:86740a56073b 6373 #define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
AnnaBridge 143:86740a56073b 6374 #define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
AnnaBridge 143:86740a56073b 6375 #define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6376 #define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6377 #define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6378
AnnaBridge 143:86740a56073b 6379 /* Bit 14 : Disable interrupt on BB event. */
AnnaBridge 143:86740a56073b 6380 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
AnnaBridge 143:86740a56073b 6381 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
AnnaBridge 143:86740a56073b 6382 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6383 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6384 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6385
AnnaBridge 143:86740a56073b 6386 /* Bit 9 : Disable interrupt on ERROR event. */
AnnaBridge 143:86740a56073b 6387 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6388 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6389 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6390 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6391 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6392
AnnaBridge 143:86740a56073b 6393 /* Bit 7 : Disable interrupt on TXDSENT event. */
AnnaBridge 143:86740a56073b 6394 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
AnnaBridge 143:86740a56073b 6395 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
AnnaBridge 143:86740a56073b 6396 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6397 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6398 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6399
AnnaBridge 143:86740a56073b 6400 /* Bit 2 : Disable interrupt on RXDREADY event. */
AnnaBridge 143:86740a56073b 6401 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
AnnaBridge 143:86740a56073b 6402 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
AnnaBridge 143:86740a56073b 6403 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6404 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6405 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6406
AnnaBridge 143:86740a56073b 6407 /* Bit 1 : Disable interrupt on STOPPED event. */
AnnaBridge 143:86740a56073b 6408 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
AnnaBridge 143:86740a56073b 6409 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
AnnaBridge 143:86740a56073b 6410 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6411 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6412 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6413
AnnaBridge 143:86740a56073b 6414 /* Register: TWI_ERRORSRC */
AnnaBridge 143:86740a56073b 6415 /* Description: Two-wire error source. Write error field to 1 to clear error. */
AnnaBridge 143:86740a56073b 6416
AnnaBridge 143:86740a56073b 6417 /* Bit 2 : NACK received after sending a data byte. */
AnnaBridge 143:86740a56073b 6418 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
AnnaBridge 143:86740a56073b 6419 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
AnnaBridge 143:86740a56073b 6420 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6421 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6422 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6423
AnnaBridge 143:86740a56073b 6424 /* Bit 1 : NACK received after sending the address. */
AnnaBridge 143:86740a56073b 6425 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
AnnaBridge 143:86740a56073b 6426 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
AnnaBridge 143:86740a56073b 6427 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6428 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6429 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6430
AnnaBridge 143:86740a56073b 6431 /* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
AnnaBridge 143:86740a56073b 6432 #define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
AnnaBridge 143:86740a56073b 6433 #define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
AnnaBridge 143:86740a56073b 6434 #define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6435 #define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6436 #define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6437
AnnaBridge 143:86740a56073b 6438 /* Register: TWI_ENABLE */
AnnaBridge 143:86740a56073b 6439 /* Description: Enable two-wire master. */
AnnaBridge 143:86740a56073b 6440
AnnaBridge 143:86740a56073b 6441 /* Bits 2..0 : Enable or disable W2M */
AnnaBridge 143:86740a56073b 6442 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 6443 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 6444 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 6445 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 6446
AnnaBridge 143:86740a56073b 6447 /* Register: TWI_RXD */
AnnaBridge 143:86740a56073b 6448 /* Description: RX data register. */
AnnaBridge 143:86740a56073b 6449
AnnaBridge 143:86740a56073b 6450 /* Bits 7..0 : RX data from last transfer. */
AnnaBridge 143:86740a56073b 6451 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
AnnaBridge 143:86740a56073b 6452 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
AnnaBridge 143:86740a56073b 6453
AnnaBridge 143:86740a56073b 6454 /* Register: TWI_TXD */
AnnaBridge 143:86740a56073b 6455 /* Description: TX data register. */
AnnaBridge 143:86740a56073b 6456
AnnaBridge 143:86740a56073b 6457 /* Bits 7..0 : TX data for next transfer. */
AnnaBridge 143:86740a56073b 6458 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
AnnaBridge 143:86740a56073b 6459 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
AnnaBridge 143:86740a56073b 6460
AnnaBridge 143:86740a56073b 6461 /* Register: TWI_FREQUENCY */
AnnaBridge 143:86740a56073b 6462 /* Description: Two-wire frequency. */
AnnaBridge 143:86740a56073b 6463
AnnaBridge 143:86740a56073b 6464 /* Bits 31..0 : Two-wire master clock frequency. */
AnnaBridge 143:86740a56073b 6465 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
AnnaBridge 143:86740a56073b 6466 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
AnnaBridge 143:86740a56073b 6467 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
AnnaBridge 143:86740a56073b 6468 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
AnnaBridge 143:86740a56073b 6469 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
AnnaBridge 143:86740a56073b 6470
AnnaBridge 143:86740a56073b 6471 /* Register: TWI_ADDRESS */
AnnaBridge 143:86740a56073b 6472 /* Description: Address used in the two-wire transfer. */
AnnaBridge 143:86740a56073b 6473
AnnaBridge 143:86740a56073b 6474 /* Bits 6..0 : Two-wire address. */
AnnaBridge 143:86740a56073b 6475 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
AnnaBridge 143:86740a56073b 6476 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
AnnaBridge 143:86740a56073b 6477
AnnaBridge 143:86740a56073b 6478 /* Register: TWI_POWER */
AnnaBridge 143:86740a56073b 6479 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 6480
AnnaBridge 143:86740a56073b 6481 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 6482 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 6483 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 6484 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 6485 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 6486
AnnaBridge 143:86740a56073b 6487
AnnaBridge 143:86740a56073b 6488 /* Peripheral: UART */
AnnaBridge 143:86740a56073b 6489 /* Description: Universal Asynchronous Receiver/Transmitter. */
AnnaBridge 143:86740a56073b 6490
AnnaBridge 143:86740a56073b 6491 /* Register: UART_SHORTS */
AnnaBridge 143:86740a56073b 6492 /* Description: Shortcuts for UART. */
AnnaBridge 143:86740a56073b 6493
AnnaBridge 143:86740a56073b 6494 /* Bit 4 : Shortcut between NCTS event and STOPRX task. */
AnnaBridge 143:86740a56073b 6495 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
AnnaBridge 143:86740a56073b 6496 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
AnnaBridge 143:86740a56073b 6497 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6498 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6499
AnnaBridge 143:86740a56073b 6500 /* Bit 3 : Shortcut between CTS event and STARTRX task. */
AnnaBridge 143:86740a56073b 6501 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
AnnaBridge 143:86740a56073b 6502 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
AnnaBridge 143:86740a56073b 6503 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
AnnaBridge 143:86740a56073b 6504 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
AnnaBridge 143:86740a56073b 6505
AnnaBridge 143:86740a56073b 6506 /* Register: UART_INTENSET */
AnnaBridge 143:86740a56073b 6507 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 6508
AnnaBridge 143:86740a56073b 6509 /* Bit 17 : Enable interrupt on RXTO event. */
AnnaBridge 143:86740a56073b 6510 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 6511 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 6512 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6513 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6514 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6515
AnnaBridge 143:86740a56073b 6516 /* Bit 9 : Enable interrupt on ERROR event. */
AnnaBridge 143:86740a56073b 6517 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6518 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6519 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6520 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6521 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6522
AnnaBridge 143:86740a56073b 6523 /* Bit 7 : Enable interrupt on TXRDY event. */
AnnaBridge 143:86740a56073b 6524 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
AnnaBridge 143:86740a56073b 6525 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
AnnaBridge 143:86740a56073b 6526 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6527 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6528 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6529
AnnaBridge 143:86740a56073b 6530 /* Bit 2 : Enable interrupt on RXRDY event. */
AnnaBridge 143:86740a56073b 6531 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
AnnaBridge 143:86740a56073b 6532 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
AnnaBridge 143:86740a56073b 6533 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6534 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6535 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6536
AnnaBridge 143:86740a56073b 6537 /* Bit 1 : Enable interrupt on NCTS event. */
AnnaBridge 143:86740a56073b 6538 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 6539 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 6540 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6541 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6542 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6543
AnnaBridge 143:86740a56073b 6544 /* Bit 0 : Enable interrupt on CTS event. */
AnnaBridge 143:86740a56073b 6545 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 6546 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 6547 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6548 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6549 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6550
AnnaBridge 143:86740a56073b 6551 /* Register: UART_INTENCLR */
AnnaBridge 143:86740a56073b 6552 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 6553
AnnaBridge 143:86740a56073b 6554 /* Bit 17 : Disable interrupt on RXTO event. */
AnnaBridge 143:86740a56073b 6555 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
AnnaBridge 143:86740a56073b 6556 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
AnnaBridge 143:86740a56073b 6557 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6558 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6559 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6560
AnnaBridge 143:86740a56073b 6561 /* Bit 9 : Disable interrupt on ERROR event. */
AnnaBridge 143:86740a56073b 6562 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
AnnaBridge 143:86740a56073b 6563 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
AnnaBridge 143:86740a56073b 6564 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6565 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6566 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6567
AnnaBridge 143:86740a56073b 6568 /* Bit 7 : Disable interrupt on TXRDY event. */
AnnaBridge 143:86740a56073b 6569 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
AnnaBridge 143:86740a56073b 6570 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
AnnaBridge 143:86740a56073b 6571 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6572 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6573 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6574
AnnaBridge 143:86740a56073b 6575 /* Bit 2 : Disable interrupt on RXRDY event. */
AnnaBridge 143:86740a56073b 6576 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
AnnaBridge 143:86740a56073b 6577 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
AnnaBridge 143:86740a56073b 6578 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6579 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6580 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6581
AnnaBridge 143:86740a56073b 6582 /* Bit 1 : Disable interrupt on NCTS event. */
AnnaBridge 143:86740a56073b 6583 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
AnnaBridge 143:86740a56073b 6584 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
AnnaBridge 143:86740a56073b 6585 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6586 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6587 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6588
AnnaBridge 143:86740a56073b 6589 /* Bit 0 : Disable interrupt on CTS event. */
AnnaBridge 143:86740a56073b 6590 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
AnnaBridge 143:86740a56073b 6591 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
AnnaBridge 143:86740a56073b 6592 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6593 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6594 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6595
AnnaBridge 143:86740a56073b 6596 /* Register: UART_ERRORSRC */
AnnaBridge 143:86740a56073b 6597 /* Description: Error source. Write error field to 1 to clear error. */
AnnaBridge 143:86740a56073b 6598
AnnaBridge 143:86740a56073b 6599 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
AnnaBridge 143:86740a56073b 6600 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
AnnaBridge 143:86740a56073b 6601 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
AnnaBridge 143:86740a56073b 6602 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6603 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6604 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6605
AnnaBridge 143:86740a56073b 6606 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
AnnaBridge 143:86740a56073b 6607 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
AnnaBridge 143:86740a56073b 6608 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
AnnaBridge 143:86740a56073b 6609 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6610 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6611 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6612
AnnaBridge 143:86740a56073b 6613 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
AnnaBridge 143:86740a56073b 6614 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 6615 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 6616 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6617 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6618 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6619
AnnaBridge 143:86740a56073b 6620 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
AnnaBridge 143:86740a56073b 6621 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
AnnaBridge 143:86740a56073b 6622 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
AnnaBridge 143:86740a56073b 6623 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
AnnaBridge 143:86740a56073b 6624 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
AnnaBridge 143:86740a56073b 6625 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
AnnaBridge 143:86740a56073b 6626
AnnaBridge 143:86740a56073b 6627 /* Register: UART_ENABLE */
AnnaBridge 143:86740a56073b 6628 /* Description: Enable UART and acquire IOs. */
AnnaBridge 143:86740a56073b 6629
AnnaBridge 143:86740a56073b 6630 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
AnnaBridge 143:86740a56073b 6631 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
AnnaBridge 143:86740a56073b 6632 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
AnnaBridge 143:86740a56073b 6633 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
AnnaBridge 143:86740a56073b 6634 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
AnnaBridge 143:86740a56073b 6635
AnnaBridge 143:86740a56073b 6636 /* Register: UART_RXD */
AnnaBridge 143:86740a56073b 6637 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
AnnaBridge 143:86740a56073b 6638
AnnaBridge 143:86740a56073b 6639 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
AnnaBridge 143:86740a56073b 6640 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
AnnaBridge 143:86740a56073b 6641 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
AnnaBridge 143:86740a56073b 6642
AnnaBridge 143:86740a56073b 6643 /* Register: UART_TXD */
AnnaBridge 143:86740a56073b 6644 /* Description: TXD register. */
AnnaBridge 143:86740a56073b 6645
AnnaBridge 143:86740a56073b 6646 /* Bits 7..0 : TX data for transfer. */
AnnaBridge 143:86740a56073b 6647 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
AnnaBridge 143:86740a56073b 6648 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
AnnaBridge 143:86740a56073b 6649
AnnaBridge 143:86740a56073b 6650 /* Register: UART_BAUDRATE */
AnnaBridge 143:86740a56073b 6651 /* Description: UART Baudrate. */
AnnaBridge 143:86740a56073b 6652
AnnaBridge 143:86740a56073b 6653 /* Bits 31..0 : UART baudrate. */
AnnaBridge 143:86740a56073b 6654 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
AnnaBridge 143:86740a56073b 6655 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
AnnaBridge 143:86740a56073b 6656 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
AnnaBridge 143:86740a56073b 6657 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
AnnaBridge 143:86740a56073b 6658 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
AnnaBridge 143:86740a56073b 6659 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
AnnaBridge 143:86740a56073b 6660 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
AnnaBridge 143:86740a56073b 6661 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
AnnaBridge 143:86740a56073b 6662 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
AnnaBridge 143:86740a56073b 6663 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
AnnaBridge 143:86740a56073b 6664 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
AnnaBridge 143:86740a56073b 6665 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
AnnaBridge 143:86740a56073b 6666 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
AnnaBridge 143:86740a56073b 6667 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
AnnaBridge 143:86740a56073b 6668 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
AnnaBridge 143:86740a56073b 6669 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
AnnaBridge 143:86740a56073b 6670 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
AnnaBridge 143:86740a56073b 6671 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
AnnaBridge 143:86740a56073b 6672
AnnaBridge 143:86740a56073b 6673 /* Register: UART_CONFIG */
AnnaBridge 143:86740a56073b 6674 /* Description: Configuration of parity and hardware flow control register. */
AnnaBridge 143:86740a56073b 6675
AnnaBridge 143:86740a56073b 6676 /* Bits 3..1 : Include parity bit. */
AnnaBridge 143:86740a56073b 6677 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
AnnaBridge 143:86740a56073b 6678 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
AnnaBridge 143:86740a56073b 6679 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
AnnaBridge 143:86740a56073b 6680 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
AnnaBridge 143:86740a56073b 6681
AnnaBridge 143:86740a56073b 6682 /* Bit 0 : Hardware flow control. */
AnnaBridge 143:86740a56073b 6683 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
AnnaBridge 143:86740a56073b 6684 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
AnnaBridge 143:86740a56073b 6685 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
AnnaBridge 143:86740a56073b 6686 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
AnnaBridge 143:86740a56073b 6687
AnnaBridge 143:86740a56073b 6688 /* Register: UART_POWER */
AnnaBridge 143:86740a56073b 6689 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 6690
AnnaBridge 143:86740a56073b 6691 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 6692 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 6693 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 6694 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 6695 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 6696
AnnaBridge 143:86740a56073b 6697
AnnaBridge 143:86740a56073b 6698 /* Peripheral: UICR */
AnnaBridge 143:86740a56073b 6699 /* Description: User Information Configuration. */
AnnaBridge 143:86740a56073b 6700
AnnaBridge 143:86740a56073b 6701 /* Register: UICR_RBPCONF */
AnnaBridge 143:86740a56073b 6702 /* Description: Readback protection configuration. */
AnnaBridge 143:86740a56073b 6703
AnnaBridge 143:86740a56073b 6704 /* Bits 15..8 : Readback protect all code in the device. */
AnnaBridge 143:86740a56073b 6705 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
AnnaBridge 143:86740a56073b 6706 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
AnnaBridge 143:86740a56073b 6707 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 6708 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 6709
AnnaBridge 143:86740a56073b 6710 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
AnnaBridge 143:86740a56073b 6711 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
AnnaBridge 143:86740a56073b 6712 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
AnnaBridge 143:86740a56073b 6713 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
AnnaBridge 143:86740a56073b 6714 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
AnnaBridge 143:86740a56073b 6715
AnnaBridge 143:86740a56073b 6716 /* Register: UICR_XTALFREQ */
AnnaBridge 143:86740a56073b 6717 /* Description: Reset value for CLOCK XTALFREQ register. */
AnnaBridge 143:86740a56073b 6718
AnnaBridge 143:86740a56073b 6719 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
AnnaBridge 143:86740a56073b 6720 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
AnnaBridge 143:86740a56073b 6721 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
AnnaBridge 143:86740a56073b 6722 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
AnnaBridge 143:86740a56073b 6723 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
AnnaBridge 143:86740a56073b 6724
AnnaBridge 143:86740a56073b 6725 /* Register: UICR_FWID */
AnnaBridge 143:86740a56073b 6726 /* Description: Firmware ID. */
AnnaBridge 143:86740a56073b 6727
AnnaBridge 143:86740a56073b 6728 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
AnnaBridge 143:86740a56073b 6729 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
AnnaBridge 143:86740a56073b 6730 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
AnnaBridge 143:86740a56073b 6731
AnnaBridge 143:86740a56073b 6732
AnnaBridge 143:86740a56073b 6733 /* Peripheral: WDT */
AnnaBridge 143:86740a56073b 6734 /* Description: Watchdog Timer. */
AnnaBridge 143:86740a56073b 6735
AnnaBridge 143:86740a56073b 6736 /* Register: WDT_INTENSET */
AnnaBridge 143:86740a56073b 6737 /* Description: Interrupt enable set register. */
AnnaBridge 143:86740a56073b 6738
AnnaBridge 143:86740a56073b 6739 /* Bit 0 : Enable interrupt on TIMEOUT event. */
AnnaBridge 143:86740a56073b 6740 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
AnnaBridge 143:86740a56073b 6741 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
AnnaBridge 143:86740a56073b 6742 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6743 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6744 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
AnnaBridge 143:86740a56073b 6745
AnnaBridge 143:86740a56073b 6746 /* Register: WDT_INTENCLR */
AnnaBridge 143:86740a56073b 6747 /* Description: Interrupt enable clear register. */
AnnaBridge 143:86740a56073b 6748
AnnaBridge 143:86740a56073b 6749 /* Bit 0 : Disable interrupt on TIMEOUT event. */
AnnaBridge 143:86740a56073b 6750 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
AnnaBridge 143:86740a56073b 6751 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
AnnaBridge 143:86740a56073b 6752 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
AnnaBridge 143:86740a56073b 6753 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
AnnaBridge 143:86740a56073b 6754 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
AnnaBridge 143:86740a56073b 6755
AnnaBridge 143:86740a56073b 6756 /* Register: WDT_RUNSTATUS */
AnnaBridge 143:86740a56073b 6757 /* Description: Watchdog running status. */
AnnaBridge 143:86740a56073b 6758
AnnaBridge 143:86740a56073b 6759 /* Bit 0 : Watchdog running status. */
AnnaBridge 143:86740a56073b 6760 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
AnnaBridge 143:86740a56073b 6761 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
AnnaBridge 143:86740a56073b 6762 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
AnnaBridge 143:86740a56073b 6763 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
AnnaBridge 143:86740a56073b 6764
AnnaBridge 143:86740a56073b 6765 /* Register: WDT_REQSTATUS */
AnnaBridge 143:86740a56073b 6766 /* Description: Request status. */
AnnaBridge 143:86740a56073b 6767
AnnaBridge 143:86740a56073b 6768 /* Bit 7 : Request status for RR[7]. */
AnnaBridge 143:86740a56073b 6769 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
AnnaBridge 143:86740a56073b 6770 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
AnnaBridge 143:86740a56073b 6771 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6772 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6773
AnnaBridge 143:86740a56073b 6774 /* Bit 6 : Request status for RR[6]. */
AnnaBridge 143:86740a56073b 6775 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
AnnaBridge 143:86740a56073b 6776 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
AnnaBridge 143:86740a56073b 6777 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6778 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6779
AnnaBridge 143:86740a56073b 6780 /* Bit 5 : Request status for RR[5]. */
AnnaBridge 143:86740a56073b 6781 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
AnnaBridge 143:86740a56073b 6782 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
AnnaBridge 143:86740a56073b 6783 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6784 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6785
AnnaBridge 143:86740a56073b 6786 /* Bit 4 : Request status for RR[4]. */
AnnaBridge 143:86740a56073b 6787 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
AnnaBridge 143:86740a56073b 6788 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
AnnaBridge 143:86740a56073b 6789 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6790 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6791
AnnaBridge 143:86740a56073b 6792 /* Bit 3 : Request status for RR[3]. */
AnnaBridge 143:86740a56073b 6793 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
AnnaBridge 143:86740a56073b 6794 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
AnnaBridge 143:86740a56073b 6795 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6796 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6797
AnnaBridge 143:86740a56073b 6798 /* Bit 2 : Request status for RR[2]. */
AnnaBridge 143:86740a56073b 6799 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
AnnaBridge 143:86740a56073b 6800 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
AnnaBridge 143:86740a56073b 6801 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6802 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6803
AnnaBridge 143:86740a56073b 6804 /* Bit 1 : Request status for RR[1]. */
AnnaBridge 143:86740a56073b 6805 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
AnnaBridge 143:86740a56073b 6806 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
AnnaBridge 143:86740a56073b 6807 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6808 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6809
AnnaBridge 143:86740a56073b 6810 /* Bit 0 : Request status for RR[0]. */
AnnaBridge 143:86740a56073b 6811 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
AnnaBridge 143:86740a56073b 6812 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
AnnaBridge 143:86740a56073b 6813 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
AnnaBridge 143:86740a56073b 6814 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
AnnaBridge 143:86740a56073b 6815
AnnaBridge 143:86740a56073b 6816 /* Register: WDT_RREN */
AnnaBridge 143:86740a56073b 6817 /* Description: Reload request enable. */
AnnaBridge 143:86740a56073b 6818
AnnaBridge 143:86740a56073b 6819 /* Bit 7 : Enable or disable RR[7] register. */
AnnaBridge 143:86740a56073b 6820 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
AnnaBridge 143:86740a56073b 6821 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
AnnaBridge 143:86740a56073b 6822 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
AnnaBridge 143:86740a56073b 6823 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
AnnaBridge 143:86740a56073b 6824
AnnaBridge 143:86740a56073b 6825 /* Bit 6 : Enable or disable RR[6] register. */
AnnaBridge 143:86740a56073b 6826 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
AnnaBridge 143:86740a56073b 6827 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
AnnaBridge 143:86740a56073b 6828 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
AnnaBridge 143:86740a56073b 6829 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
AnnaBridge 143:86740a56073b 6830
AnnaBridge 143:86740a56073b 6831 /* Bit 5 : Enable or disable RR[5] register. */
AnnaBridge 143:86740a56073b 6832 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
AnnaBridge 143:86740a56073b 6833 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
AnnaBridge 143:86740a56073b 6834 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
AnnaBridge 143:86740a56073b 6835 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
AnnaBridge 143:86740a56073b 6836
AnnaBridge 143:86740a56073b 6837 /* Bit 4 : Enable or disable RR[4] register. */
AnnaBridge 143:86740a56073b 6838 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
AnnaBridge 143:86740a56073b 6839 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
AnnaBridge 143:86740a56073b 6840 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
AnnaBridge 143:86740a56073b 6841 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
AnnaBridge 143:86740a56073b 6842
AnnaBridge 143:86740a56073b 6843 /* Bit 3 : Enable or disable RR[3] register. */
AnnaBridge 143:86740a56073b 6844 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
AnnaBridge 143:86740a56073b 6845 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
AnnaBridge 143:86740a56073b 6846 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
AnnaBridge 143:86740a56073b 6847 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
AnnaBridge 143:86740a56073b 6848
AnnaBridge 143:86740a56073b 6849 /* Bit 2 : Enable or disable RR[2] register. */
AnnaBridge 143:86740a56073b 6850 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
AnnaBridge 143:86740a56073b 6851 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
AnnaBridge 143:86740a56073b 6852 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
AnnaBridge 143:86740a56073b 6853 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
AnnaBridge 143:86740a56073b 6854
AnnaBridge 143:86740a56073b 6855 /* Bit 1 : Enable or disable RR[1] register. */
AnnaBridge 143:86740a56073b 6856 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
AnnaBridge 143:86740a56073b 6857 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
AnnaBridge 143:86740a56073b 6858 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
AnnaBridge 143:86740a56073b 6859 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
AnnaBridge 143:86740a56073b 6860
AnnaBridge 143:86740a56073b 6861 /* Bit 0 : Enable or disable RR[0] register. */
AnnaBridge 143:86740a56073b 6862 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
AnnaBridge 143:86740a56073b 6863 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
AnnaBridge 143:86740a56073b 6864 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
AnnaBridge 143:86740a56073b 6865 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
AnnaBridge 143:86740a56073b 6866
AnnaBridge 143:86740a56073b 6867 /* Register: WDT_CONFIG */
AnnaBridge 143:86740a56073b 6868 /* Description: Configuration register. */
AnnaBridge 143:86740a56073b 6869
AnnaBridge 143:86740a56073b 6870 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
AnnaBridge 143:86740a56073b 6871 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
AnnaBridge 143:86740a56073b 6872 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
AnnaBridge 143:86740a56073b 6873 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
AnnaBridge 143:86740a56073b 6874 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
AnnaBridge 143:86740a56073b 6875
AnnaBridge 143:86740a56073b 6876 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
AnnaBridge 143:86740a56073b 6877 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
AnnaBridge 143:86740a56073b 6878 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
AnnaBridge 143:86740a56073b 6879 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
AnnaBridge 143:86740a56073b 6880 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
AnnaBridge 143:86740a56073b 6881
AnnaBridge 143:86740a56073b 6882 /* Register: WDT_RR */
AnnaBridge 143:86740a56073b 6883 /* Description: Reload requests registers. */
AnnaBridge 143:86740a56073b 6884
AnnaBridge 143:86740a56073b 6885 /* Bits 31..0 : Reload register. */
AnnaBridge 143:86740a56073b 6886 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
AnnaBridge 143:86740a56073b 6887 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
AnnaBridge 143:86740a56073b 6888 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
AnnaBridge 143:86740a56073b 6889
AnnaBridge 143:86740a56073b 6890 /* Register: WDT_POWER */
AnnaBridge 143:86740a56073b 6891 /* Description: Peripheral power control. */
AnnaBridge 143:86740a56073b 6892
AnnaBridge 143:86740a56073b 6893 /* Bit 0 : Peripheral power control. */
AnnaBridge 143:86740a56073b 6894 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
AnnaBridge 143:86740a56073b 6895 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
AnnaBridge 143:86740a56073b 6896 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
AnnaBridge 143:86740a56073b 6897 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
AnnaBridge 143:86740a56073b 6898
AnnaBridge 143:86740a56073b 6899
AnnaBridge 143:86740a56073b 6900 /*lint --flb "Leave library region" */
AnnaBridge 143:86740a56073b 6901 #endif