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TARGET_SDT32625B/TOOLCHAIN_IAR/wdt2_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_MAX32625PICO_NO_BOOT/TARGET_Maxim/TARGET_MAX32625/device/wdt2_regs.h@169:a7c7b631e539
mbed library. Release version 164
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
| Anna Bridge |
169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
| Anna Bridge |
169:a7c7b631e539 | 3 | * |
| Anna Bridge |
169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
| Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
| Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
| Anna Bridge |
169:a7c7b631e539 | 10 | * |
| Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
| Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
| Anna Bridge |
169:a7c7b631e539 | 13 | * |
| Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
| Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
| Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| Anna Bridge |
169:a7c7b631e539 | 21 | * |
| Anna Bridge |
169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
| Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
| Anna Bridge |
169:a7c7b631e539 | 25 | * |
| Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
| Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
| Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
| Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
| Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
| Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
| Anna Bridge |
169:a7c7b631e539 | 32 | |
| Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_WDT2_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_WDT2_REGS_H_ |
| Anna Bridge |
169:a7c7b631e539 | 35 | |
| Anna Bridge |
169:a7c7b631e539 | 36 | #ifdef __cplusplus |
| Anna Bridge |
169:a7c7b631e539 | 37 | extern "C" { |
| Anna Bridge |
169:a7c7b631e539 | 38 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 39 | |
| Anna Bridge |
169:a7c7b631e539 | 40 | #include <stdint.h> |
| Anna Bridge |
169:a7c7b631e539 | 41 | #include "mxc_device.h" |
| Anna Bridge |
169:a7c7b631e539 | 42 | |
| Anna Bridge |
169:a7c7b631e539 | 43 | /* |
| Anna Bridge |
169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
| Anna Bridge |
169:a7c7b631e539 | 45 | */ |
| Anna Bridge |
169:a7c7b631e539 | 46 | #ifndef __IO |
| Anna Bridge |
169:a7c7b631e539 | 47 | #define __IO volatile |
| Anna Bridge |
169:a7c7b631e539 | 48 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 49 | #ifndef __I |
| Anna Bridge |
169:a7c7b631e539 | 50 | #define __I volatile const |
| Anna Bridge |
169:a7c7b631e539 | 51 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 52 | #ifndef __O |
| Anna Bridge |
169:a7c7b631e539 | 53 | #define __O volatile |
| Anna Bridge |
169:a7c7b631e539 | 54 | #endif |
| Anna Bridge |
169:a7c7b631e539 | 55 | |
| Anna Bridge |
169:a7c7b631e539 | 56 | |
| Anna Bridge |
169:a7c7b631e539 | 57 | /* |
| Anna Bridge |
169:a7c7b631e539 | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
| Anna Bridge |
169:a7c7b631e539 | 59 | access to each register in module. |
| Anna Bridge |
169:a7c7b631e539 | 60 | */ |
| Anna Bridge |
169:a7c7b631e539 | 61 | |
| Anna Bridge |
169:a7c7b631e539 | 62 | /* Offset Register Description |
| Anna Bridge |
169:a7c7b631e539 | 63 | ============= ============================================================================ */ |
| Anna Bridge |
169:a7c7b631e539 | 64 | typedef struct { |
| Anna Bridge |
169:a7c7b631e539 | 65 | __IO uint32_t ctrl; /* 0x0000 Watchdog Timer 2 Control Register */ |
| Anna Bridge |
169:a7c7b631e539 | 66 | __IO uint32_t clear; /* 0x0004 Watchdog Timer 2 Clear Register (Feed Dog) */ |
| Anna Bridge |
169:a7c7b631e539 | 67 | __IO uint32_t flags; /* 0x0008 Watchdog Timer 2 Interrupt and Reset Flags */ |
| Anna Bridge |
169:a7c7b631e539 | 68 | __IO uint32_t enable; /* 0x000C Watchdog Timer 2 Interrupt/Reset Enable/Disable Controls */ |
| Anna Bridge |
169:a7c7b631e539 | 69 | __I uint32_t rsv010; /* 0x0010 */ |
| Anna Bridge |
169:a7c7b631e539 | 70 | __IO uint32_t lock_ctrl; /* 0x0014 Watchdog Timer 2 Register Setting Lock for Control Register */ |
| Anna Bridge |
169:a7c7b631e539 | 71 | } mxc_wdt2_regs_t; |
| Anna Bridge |
169:a7c7b631e539 | 72 | |
| Anna Bridge |
169:a7c7b631e539 | 73 | |
| Anna Bridge |
169:a7c7b631e539 | 74 | /* |
| Anna Bridge |
169:a7c7b631e539 | 75 | Register offsets for module WDT2. |
| Anna Bridge |
169:a7c7b631e539 | 76 | */ |
| Anna Bridge |
169:a7c7b631e539 | 77 | |
| Anna Bridge |
169:a7c7b631e539 | 78 | #define MXC_R_WDT2_OFFS_CTRL ((uint32_t)0x00000000UL) |
| Anna Bridge |
169:a7c7b631e539 | 79 | #define MXC_R_WDT2_OFFS_CLEAR ((uint32_t)0x00000004UL) |
| Anna Bridge |
169:a7c7b631e539 | 80 | #define MXC_R_WDT2_OFFS_FLAGS ((uint32_t)0x00000008UL) |
| Anna Bridge |
169:a7c7b631e539 | 81 | #define MXC_R_WDT2_OFFS_ENABLE ((uint32_t)0x0000000CUL) |
| Anna Bridge |
169:a7c7b631e539 | 82 | #define MXC_R_WDT2_OFFS_LOCK_CTRL ((uint32_t)0x00000014UL) |
| Anna Bridge |
169:a7c7b631e539 | 83 | |
| Anna Bridge |
169:a7c7b631e539 | 84 | |
| Anna Bridge |
169:a7c7b631e539 | 85 | /* |
| Anna Bridge |
169:a7c7b631e539 | 86 | Field positions and masks for module WDT2. |
| Anna Bridge |
169:a7c7b631e539 | 87 | */ |
| Anna Bridge |
169:a7c7b631e539 | 88 | |
| Anna Bridge |
169:a7c7b631e539 | 89 | #define MXC_F_WDT2_CTRL_INT_PERIOD_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 90 | #define MXC_F_WDT2_CTRL_INT_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 91 | #define MXC_F_WDT2_CTRL_RST_PERIOD_POS 4 |
| Anna Bridge |
169:a7c7b631e539 | 92 | #define MXC_F_WDT2_CTRL_RST_PERIOD ((uint32_t)(0x0000000FUL << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 93 | #define MXC_F_WDT2_CTRL_EN_TIMER_POS 8 |
| Anna Bridge |
169:a7c7b631e539 | 94 | #define MXC_F_WDT2_CTRL_EN_TIMER ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 95 | #define MXC_F_WDT2_CTRL_EN_CLOCK_POS 9 |
| Anna Bridge |
169:a7c7b631e539 | 96 | #define MXC_F_WDT2_CTRL_EN_CLOCK ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_CLOCK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 97 | #define MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS 10 |
| Anna Bridge |
169:a7c7b631e539 | 98 | #define MXC_F_WDT2_CTRL_EN_TIMER_SLP ((uint32_t)(0x00000001UL << MXC_F_WDT2_CTRL_EN_TIMER_SLP_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 99 | |
| Anna Bridge |
169:a7c7b631e539 | 100 | #define MXC_F_WDT2_FLAGS_TIMEOUT_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 101 | #define MXC_F_WDT2_FLAGS_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_TIMEOUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 102 | #define MXC_F_WDT2_FLAGS_RESET_OUT_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 103 | #define MXC_F_WDT2_FLAGS_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_FLAGS_RESET_OUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 104 | |
| Anna Bridge |
169:a7c7b631e539 | 105 | #define MXC_F_WDT2_ENABLE_TIMEOUT_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 106 | #define MXC_F_WDT2_ENABLE_TIMEOUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_TIMEOUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 107 | #define MXC_F_WDT2_ENABLE_RESET_OUT_POS 2 |
| Anna Bridge |
169:a7c7b631e539 | 108 | #define MXC_F_WDT2_ENABLE_RESET_OUT ((uint32_t)(0x00000001UL << MXC_F_WDT2_ENABLE_RESET_OUT_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 109 | |
| Anna Bridge |
169:a7c7b631e539 | 110 | #define MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS 0 |
| Anna Bridge |
169:a7c7b631e539 | 111 | #define MXC_F_WDT2_LOCK_CTRL_WDLOCK ((uint32_t)(0x000000FFUL << MXC_F_WDT2_LOCK_CTRL_WDLOCK_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 112 | |
| Anna Bridge |
169:a7c7b631e539 | 113 | |
| Anna Bridge |
169:a7c7b631e539 | 114 | |
| Anna Bridge |
169:a7c7b631e539 | 115 | /* |
| Anna Bridge |
169:a7c7b631e539 | 116 | Field values and shifted values for module WDT2. |
| Anna Bridge |
169:a7c7b631e539 | 117 | */ |
| Anna Bridge |
169:a7c7b631e539 | 118 | |
| Anna Bridge |
169:a7c7b631e539 | 119 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 120 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 121 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) |
| Anna Bridge |
169:a7c7b631e539 | 122 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) |
| Anna Bridge |
169:a7c7b631e539 | 123 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) |
| Anna Bridge |
169:a7c7b631e539 | 124 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) |
| Anna Bridge |
169:a7c7b631e539 | 125 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) |
| Anna Bridge |
169:a7c7b631e539 | 126 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) |
| Anna Bridge |
169:a7c7b631e539 | 127 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) |
| Anna Bridge |
169:a7c7b631e539 | 128 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) |
| Anna Bridge |
169:a7c7b631e539 | 129 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) |
| Anna Bridge |
169:a7c7b631e539 | 130 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) |
| Anna Bridge |
169:a7c7b631e539 | 131 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) |
| Anna Bridge |
169:a7c7b631e539 | 132 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) |
| Anna Bridge |
169:a7c7b631e539 | 133 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) |
| Anna Bridge |
169:a7c7b631e539 | 134 | #define MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) |
| Anna Bridge |
169:a7c7b631e539 | 135 | |
| Anna Bridge |
169:a7c7b631e539 | 136 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 137 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 138 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 139 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 140 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 141 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 142 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 143 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 144 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 145 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 146 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 147 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 148 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 149 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 150 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 151 | #define MXC_S_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_INT_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_INT_PERIOD_POS)) |
| Anna Bridge |
169:a7c7b631e539 | 152 | |
| Anna Bridge |
169:a7c7b631e539 | 153 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(0x00000000UL)) |
| Anna Bridge |
169:a7c7b631e539 | 154 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(0x00000001UL)) |
| Anna Bridge |
169:a7c7b631e539 | 155 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(0x00000002UL)) |
| Anna Bridge |
169:a7c7b631e539 | 156 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(0x00000003UL)) |
| Anna Bridge |
169:a7c7b631e539 | 157 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(0x00000004UL)) |
| Anna Bridge |
169:a7c7b631e539 | 158 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(0x00000005UL)) |
| Anna Bridge |
169:a7c7b631e539 | 159 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(0x00000006UL)) |
| Anna Bridge |
169:a7c7b631e539 | 160 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(0x00000007UL)) |
| Anna Bridge |
169:a7c7b631e539 | 161 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(0x00000008UL)) |
| Anna Bridge |
169:a7c7b631e539 | 162 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(0x00000009UL)) |
| Anna Bridge |
169:a7c7b631e539 | 163 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(0x0000000AUL)) |
| Anna Bridge |
169:a7c7b631e539 | 164 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(0x0000000BUL)) |
| Anna Bridge |
169:a7c7b631e539 | 165 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(0x0000000CUL)) |
| Anna Bridge |
169:a7c7b631e539 | 166 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(0x0000000DUL)) |
| Anna Bridge |
169:a7c7b631e539 | 167 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(0x0000000EUL)) |
| Anna Bridge |
169:a7c7b631e539 | 168 | #define MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(0x0000000FUL)) |
| Anna Bridge |
169:a7c7b631e539 | 169 | |
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169:a7c7b631e539 | 170 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_25_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 171 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_24_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 172 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_23_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 173 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_22_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 174 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_21_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 175 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_20_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 176 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_19_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 177 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_18_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 178 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_17_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 179 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_16_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 180 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_15_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 181 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_14_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 182 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_13_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 183 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_12_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 184 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_11_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 185 | #define MXC_S_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS ((uint32_t)(MXC_V_WDT2_CTRL_RST_PERIOD_2_10_NANO_CLKS << MXC_F_WDT2_CTRL_RST_PERIOD_POS)) |
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169:a7c7b631e539 | 186 | |
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169:a7c7b631e539 | 187 | |
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169:a7c7b631e539 | 188 | #define MXC_V_WDT2_LOCK_KEY 0x24 |
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169:a7c7b631e539 | 189 | #define MXC_V_WDT2_UNLOCK_KEY 0x42 |
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169:a7c7b631e539 | 190 | |
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169:a7c7b631e539 | 191 | #define MXC_V_WDT2_RESET_KEY_0 0xA5 |
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169:a7c7b631e539 | 192 | #define MXC_V_WDT2_RESET_KEY_1 0x5A |
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169:a7c7b631e539 | 193 | |
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169:a7c7b631e539 | 194 | |
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169:a7c7b631e539 | 195 | #ifdef __cplusplus |
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169:a7c7b631e539 | 196 | } |
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169:a7c7b631e539 | 197 | #endif |
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169:a7c7b631e539 | 198 | |
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169:a7c7b631e539 | 199 | #endif /* _MXC_WDT2_REGS_H_ */ |
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169:a7c7b631e539 | 200 |
