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TARGET_SDT32625B/TOOLCHAIN_IAR/pt_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_MAX32625PICO/TARGET_Maxim/TARGET_MAX32625/device/pt_regs.h@169:a7c7b631e539
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
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169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
Anna Bridge |
169:a7c7b631e539 | 3 | * |
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169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
Anna Bridge |
169:a7c7b631e539 | 10 | * |
Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
Anna Bridge |
169:a7c7b631e539 | 13 | * |
Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Anna Bridge |
169:a7c7b631e539 | 21 | * |
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169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
Anna Bridge |
169:a7c7b631e539 | 25 | * |
Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
Anna Bridge |
169:a7c7b631e539 | 32 | |
Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_PT_REGS_H_ |
Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_PT_REGS_H_ |
Anna Bridge |
169:a7c7b631e539 | 35 | |
Anna Bridge |
169:a7c7b631e539 | 36 | #ifdef __cplusplus |
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169:a7c7b631e539 | 37 | extern "C" { |
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169:a7c7b631e539 | 38 | #endif |
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169:a7c7b631e539 | 39 | |
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169:a7c7b631e539 | 40 | #include <stdint.h> |
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169:a7c7b631e539 | 41 | #include "mxc_device.h" |
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169:a7c7b631e539 | 42 | |
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169:a7c7b631e539 | 43 | /* |
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169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
Anna Bridge |
169:a7c7b631e539 | 45 | */ |
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169:a7c7b631e539 | 46 | #ifndef __IO |
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169:a7c7b631e539 | 47 | #define __IO volatile |
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169:a7c7b631e539 | 48 | #endif |
Anna Bridge |
169:a7c7b631e539 | 49 | #ifndef __I |
Anna Bridge |
169:a7c7b631e539 | 50 | #define __I volatile const |
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169:a7c7b631e539 | 51 | #endif |
Anna Bridge |
169:a7c7b631e539 | 52 | #ifndef __O |
Anna Bridge |
169:a7c7b631e539 | 53 | #define __O volatile |
Anna Bridge |
169:a7c7b631e539 | 54 | #endif |
Anna Bridge |
169:a7c7b631e539 | 55 | |
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169:a7c7b631e539 | 56 | |
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169:a7c7b631e539 | 57 | /* |
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169:a7c7b631e539 | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
Anna Bridge |
169:a7c7b631e539 | 59 | access to each register in module. |
Anna Bridge |
169:a7c7b631e539 | 60 | */ |
Anna Bridge |
169:a7c7b631e539 | 61 | |
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169:a7c7b631e539 | 62 | /* Offset Register Description |
Anna Bridge |
169:a7c7b631e539 | 63 | ============= ============================================================================ */ |
Anna Bridge |
169:a7c7b631e539 | 64 | typedef struct { |
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169:a7c7b631e539 | 65 | __IO uint32_t enable; /* 0x0000 Global Enable/Disable Controls for All Pulse Trains */ |
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169:a7c7b631e539 | 66 | __IO uint32_t resync; /* 0x0004 Global Resync (All Pulse Trains) Control */ |
Anna Bridge |
169:a7c7b631e539 | 67 | __IO uint32_t intfl; /* 0x0008 Pulse Train Interrupt Flags */ |
Anna Bridge |
169:a7c7b631e539 | 68 | __IO uint32_t inten; /* 0x000C Pulse Train Interrupt Enable/Disable */ |
Anna Bridge |
169:a7c7b631e539 | 69 | } mxc_ptg_regs_t; |
Anna Bridge |
169:a7c7b631e539 | 70 | |
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169:a7c7b631e539 | 71 | |
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169:a7c7b631e539 | 72 | /* Offset Register Description |
Anna Bridge |
169:a7c7b631e539 | 73 | ============= ============================================================================ */ |
Anna Bridge |
169:a7c7b631e539 | 74 | typedef struct { |
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169:a7c7b631e539 | 75 | __IO uint32_t rate_length; /* 0x0000 Pulse Train Configuration */ |
Anna Bridge |
169:a7c7b631e539 | 76 | __IO uint32_t train; /* 0x0004 Pulse Train Output Pattern */ |
Anna Bridge |
169:a7c7b631e539 | 77 | __IO uint32_t loop; /* 0x0008 Pulse Train Loop Configuration */ |
Anna Bridge |
169:a7c7b631e539 | 78 | __IO uint32_t restart; /* 0x000C Pulse Train Auto-Restart Configuration */ |
Anna Bridge |
169:a7c7b631e539 | 79 | } mxc_pt_regs_t; |
Anna Bridge |
169:a7c7b631e539 | 80 | |
Anna Bridge |
169:a7c7b631e539 | 81 | |
Anna Bridge |
169:a7c7b631e539 | 82 | /* |
Anna Bridge |
169:a7c7b631e539 | 83 | Register offsets for module PT. |
Anna Bridge |
169:a7c7b631e539 | 84 | */ |
Anna Bridge |
169:a7c7b631e539 | 85 | |
Anna Bridge |
169:a7c7b631e539 | 86 | #define MXC_R_PTG_OFFS_ENABLE ((uint32_t)0x00000000UL) |
Anna Bridge |
169:a7c7b631e539 | 87 | #define MXC_R_PTG_OFFS_RESYNC ((uint32_t)0x00000004UL) |
Anna Bridge |
169:a7c7b631e539 | 88 | #define MXC_R_PTG_OFFS_INTFL ((uint32_t)0x00000008UL) |
Anna Bridge |
169:a7c7b631e539 | 89 | #define MXC_R_PTG_OFFS_INTEN ((uint32_t)0x0000000CUL) |
Anna Bridge |
169:a7c7b631e539 | 90 | #define MXC_R_PT_OFFS_RATE_LENGTH ((uint32_t)0x00000000UL) |
Anna Bridge |
169:a7c7b631e539 | 91 | #define MXC_R_PT_OFFS_TRAIN ((uint32_t)0x00000004UL) |
Anna Bridge |
169:a7c7b631e539 | 92 | #define MXC_R_PT_OFFS_LOOP ((uint32_t)0x00000008UL) |
Anna Bridge |
169:a7c7b631e539 | 93 | #define MXC_R_PT_OFFS_RESTART ((uint32_t)0x0000000CUL) |
Anna Bridge |
169:a7c7b631e539 | 94 | |
Anna Bridge |
169:a7c7b631e539 | 95 | |
Anna Bridge |
169:a7c7b631e539 | 96 | /* |
Anna Bridge |
169:a7c7b631e539 | 97 | Field positions and masks for module PT. |
Anna Bridge |
169:a7c7b631e539 | 98 | */ |
Anna Bridge |
169:a7c7b631e539 | 99 | |
Anna Bridge |
169:a7c7b631e539 | 100 | #define MXC_F_PT_ENABLE_PT0_POS 0 |
Anna Bridge |
169:a7c7b631e539 | 101 | #define MXC_F_PT_ENABLE_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT0_POS)) |
Anna Bridge |
169:a7c7b631e539 | 102 | #define MXC_F_PT_ENABLE_PT1_POS 1 |
Anna Bridge |
169:a7c7b631e539 | 103 | #define MXC_F_PT_ENABLE_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT1_POS)) |
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169:a7c7b631e539 | 104 | #define MXC_F_PT_ENABLE_PT2_POS 2 |
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169:a7c7b631e539 | 105 | #define MXC_F_PT_ENABLE_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT2_POS)) |
Anna Bridge |
169:a7c7b631e539 | 106 | #define MXC_F_PT_ENABLE_PT3_POS 3 |
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169:a7c7b631e539 | 107 | #define MXC_F_PT_ENABLE_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT3_POS)) |
Anna Bridge |
169:a7c7b631e539 | 108 | #define MXC_F_PT_ENABLE_PT4_POS 4 |
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169:a7c7b631e539 | 109 | #define MXC_F_PT_ENABLE_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT4_POS)) |
Anna Bridge |
169:a7c7b631e539 | 110 | #define MXC_F_PT_ENABLE_PT5_POS 5 |
Anna Bridge |
169:a7c7b631e539 | 111 | #define MXC_F_PT_ENABLE_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT5_POS)) |
Anna Bridge |
169:a7c7b631e539 | 112 | #define MXC_F_PT_ENABLE_PT6_POS 6 |
Anna Bridge |
169:a7c7b631e539 | 113 | #define MXC_F_PT_ENABLE_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT6_POS)) |
Anna Bridge |
169:a7c7b631e539 | 114 | #define MXC_F_PT_ENABLE_PT7_POS 7 |
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169:a7c7b631e539 | 115 | #define MXC_F_PT_ENABLE_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT7_POS)) |
Anna Bridge |
169:a7c7b631e539 | 116 | #define MXC_F_PT_ENABLE_PT8_POS 8 |
Anna Bridge |
169:a7c7b631e539 | 117 | #define MXC_F_PT_ENABLE_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT8_POS)) |
Anna Bridge |
169:a7c7b631e539 | 118 | #define MXC_F_PT_ENABLE_PT9_POS 9 |
Anna Bridge |
169:a7c7b631e539 | 119 | #define MXC_F_PT_ENABLE_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT9_POS)) |
Anna Bridge |
169:a7c7b631e539 | 120 | #define MXC_F_PT_ENABLE_PT10_POS 10 |
Anna Bridge |
169:a7c7b631e539 | 121 | #define MXC_F_PT_ENABLE_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT10_POS)) |
Anna Bridge |
169:a7c7b631e539 | 122 | #define MXC_F_PT_ENABLE_PT11_POS 11 |
Anna Bridge |
169:a7c7b631e539 | 123 | #define MXC_F_PT_ENABLE_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT11_POS)) |
Anna Bridge |
169:a7c7b631e539 | 124 | #define MXC_F_PT_ENABLE_PT12_POS 12 |
Anna Bridge |
169:a7c7b631e539 | 125 | #define MXC_F_PT_ENABLE_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT12_POS)) |
Anna Bridge |
169:a7c7b631e539 | 126 | #define MXC_F_PT_ENABLE_PT13_POS 13 |
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169:a7c7b631e539 | 127 | #define MXC_F_PT_ENABLE_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT13_POS)) |
Anna Bridge |
169:a7c7b631e539 | 128 | #define MXC_F_PT_ENABLE_PT14_POS 14 |
Anna Bridge |
169:a7c7b631e539 | 129 | #define MXC_F_PT_ENABLE_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT14_POS)) |
Anna Bridge |
169:a7c7b631e539 | 130 | #define MXC_F_PT_ENABLE_PT15_POS 15 |
Anna Bridge |
169:a7c7b631e539 | 131 | #define MXC_F_PT_ENABLE_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_ENABLE_PT15_POS)) |
Anna Bridge |
169:a7c7b631e539 | 132 | |
Anna Bridge |
169:a7c7b631e539 | 133 | #define MXC_F_PT_RESYNC_PT0_POS 0 |
Anna Bridge |
169:a7c7b631e539 | 134 | #define MXC_F_PT_RESYNC_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT0_POS)) |
Anna Bridge |
169:a7c7b631e539 | 135 | #define MXC_F_PT_RESYNC_PT1_POS 1 |
Anna Bridge |
169:a7c7b631e539 | 136 | #define MXC_F_PT_RESYNC_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT1_POS)) |
Anna Bridge |
169:a7c7b631e539 | 137 | #define MXC_F_PT_RESYNC_PT2_POS 2 |
Anna Bridge |
169:a7c7b631e539 | 138 | #define MXC_F_PT_RESYNC_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT2_POS)) |
Anna Bridge |
169:a7c7b631e539 | 139 | #define MXC_F_PT_RESYNC_PT3_POS 3 |
Anna Bridge |
169:a7c7b631e539 | 140 | #define MXC_F_PT_RESYNC_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT3_POS)) |
Anna Bridge |
169:a7c7b631e539 | 141 | #define MXC_F_PT_RESYNC_PT4_POS 4 |
Anna Bridge |
169:a7c7b631e539 | 142 | #define MXC_F_PT_RESYNC_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT4_POS)) |
Anna Bridge |
169:a7c7b631e539 | 143 | #define MXC_F_PT_RESYNC_PT5_POS 5 |
Anna Bridge |
169:a7c7b631e539 | 144 | #define MXC_F_PT_RESYNC_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT5_POS)) |
Anna Bridge |
169:a7c7b631e539 | 145 | #define MXC_F_PT_RESYNC_PT6_POS 6 |
Anna Bridge |
169:a7c7b631e539 | 146 | #define MXC_F_PT_RESYNC_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT6_POS)) |
Anna Bridge |
169:a7c7b631e539 | 147 | #define MXC_F_PT_RESYNC_PT7_POS 7 |
Anna Bridge |
169:a7c7b631e539 | 148 | #define MXC_F_PT_RESYNC_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT7_POS)) |
Anna Bridge |
169:a7c7b631e539 | 149 | #define MXC_F_PT_RESYNC_PT8_POS 8 |
Anna Bridge |
169:a7c7b631e539 | 150 | #define MXC_F_PT_RESYNC_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT8_POS)) |
Anna Bridge |
169:a7c7b631e539 | 151 | #define MXC_F_PT_RESYNC_PT9_POS 9 |
Anna Bridge |
169:a7c7b631e539 | 152 | #define MXC_F_PT_RESYNC_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT9_POS)) |
Anna Bridge |
169:a7c7b631e539 | 153 | #define MXC_F_PT_RESYNC_PT10_POS 10 |
Anna Bridge |
169:a7c7b631e539 | 154 | #define MXC_F_PT_RESYNC_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT10_POS)) |
Anna Bridge |
169:a7c7b631e539 | 155 | #define MXC_F_PT_RESYNC_PT11_POS 11 |
Anna Bridge |
169:a7c7b631e539 | 156 | #define MXC_F_PT_RESYNC_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT11_POS)) |
Anna Bridge |
169:a7c7b631e539 | 157 | #define MXC_F_PT_RESYNC_PT12_POS 12 |
Anna Bridge |
169:a7c7b631e539 | 158 | #define MXC_F_PT_RESYNC_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT12_POS)) |
Anna Bridge |
169:a7c7b631e539 | 159 | #define MXC_F_PT_RESYNC_PT13_POS 13 |
Anna Bridge |
169:a7c7b631e539 | 160 | #define MXC_F_PT_RESYNC_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT13_POS)) |
Anna Bridge |
169:a7c7b631e539 | 161 | #define MXC_F_PT_RESYNC_PT14_POS 14 |
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169:a7c7b631e539 | 162 | #define MXC_F_PT_RESYNC_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT14_POS)) |
Anna Bridge |
169:a7c7b631e539 | 163 | #define MXC_F_PT_RESYNC_PT15_POS 15 |
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169:a7c7b631e539 | 164 | #define MXC_F_PT_RESYNC_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_RESYNC_PT15_POS)) |
Anna Bridge |
169:a7c7b631e539 | 165 | |
Anna Bridge |
169:a7c7b631e539 | 166 | #define MXC_F_PT_INTFL_PT0_POS 0 |
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169:a7c7b631e539 | 167 | #define MXC_F_PT_INTFL_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT0_POS)) |
Anna Bridge |
169:a7c7b631e539 | 168 | #define MXC_F_PT_INTFL_PT1_POS 1 |
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169:a7c7b631e539 | 169 | #define MXC_F_PT_INTFL_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT1_POS)) |
Anna Bridge |
169:a7c7b631e539 | 170 | #define MXC_F_PT_INTFL_PT2_POS 2 |
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169:a7c7b631e539 | 171 | #define MXC_F_PT_INTFL_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT2_POS)) |
Anna Bridge |
169:a7c7b631e539 | 172 | #define MXC_F_PT_INTFL_PT3_POS 3 |
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169:a7c7b631e539 | 173 | #define MXC_F_PT_INTFL_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT3_POS)) |
Anna Bridge |
169:a7c7b631e539 | 174 | #define MXC_F_PT_INTFL_PT4_POS 4 |
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169:a7c7b631e539 | 175 | #define MXC_F_PT_INTFL_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT4_POS)) |
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169:a7c7b631e539 | 176 | #define MXC_F_PT_INTFL_PT5_POS 5 |
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169:a7c7b631e539 | 177 | #define MXC_F_PT_INTFL_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT5_POS)) |
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169:a7c7b631e539 | 178 | #define MXC_F_PT_INTFL_PT6_POS 6 |
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169:a7c7b631e539 | 179 | #define MXC_F_PT_INTFL_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT6_POS)) |
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169:a7c7b631e539 | 180 | #define MXC_F_PT_INTFL_PT7_POS 7 |
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169:a7c7b631e539 | 181 | #define MXC_F_PT_INTFL_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT7_POS)) |
Anna Bridge |
169:a7c7b631e539 | 182 | #define MXC_F_PT_INTFL_PT8_POS 8 |
Anna Bridge |
169:a7c7b631e539 | 183 | #define MXC_F_PT_INTFL_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT8_POS)) |
Anna Bridge |
169:a7c7b631e539 | 184 | #define MXC_F_PT_INTFL_PT9_POS 9 |
Anna Bridge |
169:a7c7b631e539 | 185 | #define MXC_F_PT_INTFL_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT9_POS)) |
Anna Bridge |
169:a7c7b631e539 | 186 | #define MXC_F_PT_INTFL_PT10_POS 10 |
Anna Bridge |
169:a7c7b631e539 | 187 | #define MXC_F_PT_INTFL_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT10_POS)) |
Anna Bridge |
169:a7c7b631e539 | 188 | #define MXC_F_PT_INTFL_PT11_POS 11 |
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169:a7c7b631e539 | 189 | #define MXC_F_PT_INTFL_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT11_POS)) |
Anna Bridge |
169:a7c7b631e539 | 190 | #define MXC_F_PT_INTFL_PT12_POS 12 |
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169:a7c7b631e539 | 191 | #define MXC_F_PT_INTFL_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT12_POS)) |
Anna Bridge |
169:a7c7b631e539 | 192 | #define MXC_F_PT_INTFL_PT13_POS 13 |
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169:a7c7b631e539 | 193 | #define MXC_F_PT_INTFL_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT13_POS)) |
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169:a7c7b631e539 | 194 | #define MXC_F_PT_INTFL_PT14_POS 14 |
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169:a7c7b631e539 | 195 | #define MXC_F_PT_INTFL_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT14_POS)) |
Anna Bridge |
169:a7c7b631e539 | 196 | #define MXC_F_PT_INTFL_PT15_POS 15 |
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169:a7c7b631e539 | 197 | #define MXC_F_PT_INTFL_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTFL_PT15_POS)) |
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169:a7c7b631e539 | 198 | |
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169:a7c7b631e539 | 199 | #define MXC_F_PT_INTEN_PT0_POS 0 |
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169:a7c7b631e539 | 200 | #define MXC_F_PT_INTEN_PT0 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT0_POS)) |
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169:a7c7b631e539 | 201 | #define MXC_F_PT_INTEN_PT1_POS 1 |
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169:a7c7b631e539 | 202 | #define MXC_F_PT_INTEN_PT1 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT1_POS)) |
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169:a7c7b631e539 | 203 | #define MXC_F_PT_INTEN_PT2_POS 2 |
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169:a7c7b631e539 | 204 | #define MXC_F_PT_INTEN_PT2 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT2_POS)) |
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169:a7c7b631e539 | 205 | #define MXC_F_PT_INTEN_PT3_POS 3 |
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169:a7c7b631e539 | 206 | #define MXC_F_PT_INTEN_PT3 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT3_POS)) |
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169:a7c7b631e539 | 207 | #define MXC_F_PT_INTEN_PT4_POS 4 |
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169:a7c7b631e539 | 208 | #define MXC_F_PT_INTEN_PT4 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT4_POS)) |
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169:a7c7b631e539 | 209 | #define MXC_F_PT_INTEN_PT5_POS 5 |
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169:a7c7b631e539 | 210 | #define MXC_F_PT_INTEN_PT5 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT5_POS)) |
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169:a7c7b631e539 | 211 | #define MXC_F_PT_INTEN_PT6_POS 6 |
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169:a7c7b631e539 | 212 | #define MXC_F_PT_INTEN_PT6 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT6_POS)) |
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169:a7c7b631e539 | 213 | #define MXC_F_PT_INTEN_PT7_POS 7 |
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169:a7c7b631e539 | 214 | #define MXC_F_PT_INTEN_PT7 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT7_POS)) |
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169:a7c7b631e539 | 215 | #define MXC_F_PT_INTEN_PT8_POS 8 |
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169:a7c7b631e539 | 216 | #define MXC_F_PT_INTEN_PT8 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT8_POS)) |
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169:a7c7b631e539 | 217 | #define MXC_F_PT_INTEN_PT9_POS 9 |
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169:a7c7b631e539 | 218 | #define MXC_F_PT_INTEN_PT9 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT9_POS)) |
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169:a7c7b631e539 | 219 | #define MXC_F_PT_INTEN_PT10_POS 10 |
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169:a7c7b631e539 | 220 | #define MXC_F_PT_INTEN_PT10 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT10_POS)) |
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169:a7c7b631e539 | 221 | #define MXC_F_PT_INTEN_PT11_POS 11 |
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169:a7c7b631e539 | 222 | #define MXC_F_PT_INTEN_PT11 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT11_POS)) |
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169:a7c7b631e539 | 223 | #define MXC_F_PT_INTEN_PT12_POS 12 |
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169:a7c7b631e539 | 224 | #define MXC_F_PT_INTEN_PT12 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT12_POS)) |
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169:a7c7b631e539 | 225 | #define MXC_F_PT_INTEN_PT13_POS 13 |
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169:a7c7b631e539 | 226 | #define MXC_F_PT_INTEN_PT13 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT13_POS)) |
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169:a7c7b631e539 | 227 | #define MXC_F_PT_INTEN_PT14_POS 14 |
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169:a7c7b631e539 | 228 | #define MXC_F_PT_INTEN_PT14 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT14_POS)) |
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169:a7c7b631e539 | 229 | #define MXC_F_PT_INTEN_PT15_POS 15 |
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169:a7c7b631e539 | 230 | #define MXC_F_PT_INTEN_PT15 ((uint32_t)(0x00000001UL << MXC_F_PT_INTEN_PT15_POS)) |
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169:a7c7b631e539 | 231 | |
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169:a7c7b631e539 | 232 | #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS 0 |
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169:a7c7b631e539 | 233 | #define MXC_F_PT_RATE_LENGTH_RATE_CONTROL ((uint32_t)(0x07FFFFFFUL << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)) |
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169:a7c7b631e539 | 234 | #define MXC_F_PT_RATE_LENGTH_MODE_POS 27 |
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169:a7c7b631e539 | 235 | #define MXC_F_PT_RATE_LENGTH_MODE ((uint32_t)(0x0000001FUL << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 236 | |
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169:a7c7b631e539 | 237 | #define MXC_F_PT_LOOP_COUNT_POS 0 |
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169:a7c7b631e539 | 238 | #define MXC_F_PT_LOOP_COUNT ((uint32_t)(0x0000FFFFUL << MXC_F_PT_LOOP_COUNT_POS)) |
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169:a7c7b631e539 | 239 | #define MXC_F_PT_LOOP_DELAY_POS 16 |
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169:a7c7b631e539 | 240 | #define MXC_F_PT_LOOP_DELAY ((uint32_t)(0x00000FFFUL << MXC_F_PT_LOOP_DELAY_POS)) |
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169:a7c7b631e539 | 241 | |
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169:a7c7b631e539 | 242 | #define MXC_F_PT_RESTART_PT_X_SELECT_POS 0 |
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169:a7c7b631e539 | 243 | #define MXC_F_PT_RESTART_PT_X_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_X_SELECT_POS)) |
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169:a7c7b631e539 | 244 | #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS 7 |
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169:a7c7b631e539 | 245 | #define MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_X_LOOP_EXIT_POS)) |
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169:a7c7b631e539 | 246 | #define MXC_F_PT_RESTART_PT_Y_SELECT_POS 8 |
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169:a7c7b631e539 | 247 | #define MXC_F_PT_RESTART_PT_Y_SELECT ((uint32_t)(0x0000001FUL << MXC_F_PT_RESTART_PT_Y_SELECT_POS)) |
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169:a7c7b631e539 | 248 | #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS 15 |
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169:a7c7b631e539 | 249 | #define MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT ((uint32_t)(0x00000001UL << MXC_F_PT_RESTART_ON_PT_Y_LOOP_EXIT_POS)) |
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169:a7c7b631e539 | 250 | |
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169:a7c7b631e539 | 251 | |
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169:a7c7b631e539 | 252 | |
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169:a7c7b631e539 | 253 | /* |
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169:a7c7b631e539 | 254 | Field values and shifted values for module PT. |
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169:a7c7b631e539 | 255 | */ |
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169:a7c7b631e539 | 256 | |
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169:a7c7b631e539 | 257 | #define MXC_V_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(0x00000000UL)) |
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169:a7c7b631e539 | 258 | #define MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(0x00000001UL)) |
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169:a7c7b631e539 | 259 | #define MXC_V_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(0x00000002UL)) |
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169:a7c7b631e539 | 260 | #define MXC_V_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(0x00000003UL)) |
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169:a7c7b631e539 | 261 | #define MXC_V_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(0x00000004UL)) |
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169:a7c7b631e539 | 262 | #define MXC_V_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(0x00000005UL)) |
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169:a7c7b631e539 | 263 | #define MXC_V_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(0x00000006UL)) |
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169:a7c7b631e539 | 264 | #define MXC_V_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(0x00000007UL)) |
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169:a7c7b631e539 | 265 | #define MXC_V_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(0x00000008UL)) |
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169:a7c7b631e539 | 266 | #define MXC_V_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(0x00000009UL)) |
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169:a7c7b631e539 | 267 | #define MXC_V_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(0x0000000AUL)) |
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169:a7c7b631e539 | 268 | #define MXC_V_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(0x0000000BUL)) |
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169:a7c7b631e539 | 269 | #define MXC_V_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(0x0000000CUL)) |
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169:a7c7b631e539 | 270 | #define MXC_V_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(0x0000000DUL)) |
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169:a7c7b631e539 | 271 | #define MXC_V_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(0x0000000EUL)) |
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169:a7c7b631e539 | 272 | #define MXC_V_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(0x0000000FUL)) |
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169:a7c7b631e539 | 273 | #define MXC_V_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(0x00000010UL)) |
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169:a7c7b631e539 | 274 | #define MXC_V_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(0x00000011UL)) |
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169:a7c7b631e539 | 275 | #define MXC_V_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(0x00000012UL)) |
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169:a7c7b631e539 | 276 | #define MXC_V_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(0x00000013UL)) |
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169:a7c7b631e539 | 277 | #define MXC_V_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(0x00000014UL)) |
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169:a7c7b631e539 | 278 | #define MXC_V_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(0x00000015UL)) |
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169:a7c7b631e539 | 279 | #define MXC_V_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(0x00000016UL)) |
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169:a7c7b631e539 | 280 | #define MXC_V_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(0x00000017UL)) |
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169:a7c7b631e539 | 281 | #define MXC_V_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(0x00000018UL)) |
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169:a7c7b631e539 | 282 | #define MXC_V_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(0x00000019UL)) |
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169:a7c7b631e539 | 283 | #define MXC_V_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(0x0000001AUL)) |
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169:a7c7b631e539 | 284 | #define MXC_V_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(0x0000001BUL)) |
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169:a7c7b631e539 | 285 | #define MXC_V_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(0x0000001CUL)) |
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169:a7c7b631e539 | 286 | #define MXC_V_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(0x0000001DUL)) |
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169:a7c7b631e539 | 287 | #define MXC_V_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(0x0000001EUL)) |
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169:a7c7b631e539 | 288 | #define MXC_V_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(0x0000001FUL)) |
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169:a7c7b631e539 | 289 | |
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169:a7c7b631e539 | 290 | #define MXC_S_PT_RATE_LENGTH_MODE_32_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_32_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 291 | #define MXC_S_PT_RATE_LENGTH_MODE_SQUARE_WAVE ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 292 | #define MXC_S_PT_RATE_LENGTH_MODE_2_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_2_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 293 | #define MXC_S_PT_RATE_LENGTH_MODE_3_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_3_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 294 | #define MXC_S_PT_RATE_LENGTH_MODE_4_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_4_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 295 | #define MXC_S_PT_RATE_LENGTH_MODE_5_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_5_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 296 | #define MXC_S_PT_RATE_LENGTH_MODE_6_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_6_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 297 | #define MXC_S_PT_RATE_LENGTH_MODE_7_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_7_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 298 | #define MXC_S_PT_RATE_LENGTH_MODE_8_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_8_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 299 | #define MXC_S_PT_RATE_LENGTH_MODE_9_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_9_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 300 | #define MXC_S_PT_RATE_LENGTH_MODE_10_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_10_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 301 | #define MXC_S_PT_RATE_LENGTH_MODE_11_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_11_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 302 | #define MXC_S_PT_RATE_LENGTH_MODE_12_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_12_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 303 | #define MXC_S_PT_RATE_LENGTH_MODE_13_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_13_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 304 | #define MXC_S_PT_RATE_LENGTH_MODE_14_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_14_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 305 | #define MXC_S_PT_RATE_LENGTH_MODE_15_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_15_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 306 | #define MXC_S_PT_RATE_LENGTH_MODE_16_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_16_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 307 | #define MXC_S_PT_RATE_LENGTH_MODE_17_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_17_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 308 | #define MXC_S_PT_RATE_LENGTH_MODE_18_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_18_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 309 | #define MXC_S_PT_RATE_LENGTH_MODE_19_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_19_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 310 | #define MXC_S_PT_RATE_LENGTH_MODE_20_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_20_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 311 | #define MXC_S_PT_RATE_LENGTH_MODE_21_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_21_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 312 | #define MXC_S_PT_RATE_LENGTH_MODE_22_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_22_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 313 | #define MXC_S_PT_RATE_LENGTH_MODE_23_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_23_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 314 | #define MXC_S_PT_RATE_LENGTH_MODE_24_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_24_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 315 | #define MXC_S_PT_RATE_LENGTH_MODE_25_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_25_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 316 | #define MXC_S_PT_RATE_LENGTH_MODE_26_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_26_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 317 | #define MXC_S_PT_RATE_LENGTH_MODE_27_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_27_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 318 | #define MXC_S_PT_RATE_LENGTH_MODE_28_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_28_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 319 | #define MXC_S_PT_RATE_LENGTH_MODE_29_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_29_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 320 | #define MXC_S_PT_RATE_LENGTH_MODE_30_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_30_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 321 | #define MXC_S_PT_RATE_LENGTH_MODE_31_BIT ((uint32_t)(MXC_V_PT_RATE_LENGTH_MODE_31_BIT << MXC_F_PT_RATE_LENGTH_MODE_POS)) |
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169:a7c7b631e539 | 322 | |
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169:a7c7b631e539 | 323 | |
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169:a7c7b631e539 | 324 | |
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169:a7c7b631e539 | 325 | #ifdef __cplusplus |
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169:a7c7b631e539 | 326 | } |
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169:a7c7b631e539 | 327 | #endif |
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169:a7c7b631e539 | 328 | |
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169:a7c7b631e539 | 329 | #endif /* _MXC_PT_REGS_H_ */ |
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169:a7c7b631e539 | 330 |