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TARGET_SDT32625B/TOOLCHAIN_IAR/i2cs_regs.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
- Parent:
- TARGET_MAX32625PICO/TARGET_Maxim/TARGET_MAX32625/device/i2cs_regs.h@169:a7c7b631e539
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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Anna Bridge |
169:a7c7b631e539 | 1 | /******************************************************************************* |
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169:a7c7b631e539 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
Anna Bridge |
169:a7c7b631e539 | 3 | * |
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169:a7c7b631e539 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
Anna Bridge |
169:a7c7b631e539 | 5 | * copy of this software and associated documentation files (the "Software"), |
Anna Bridge |
169:a7c7b631e539 | 6 | * to deal in the Software without restriction, including without limitation |
Anna Bridge |
169:a7c7b631e539 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
Anna Bridge |
169:a7c7b631e539 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
Anna Bridge |
169:a7c7b631e539 | 9 | * Software is furnished to do so, subject to the following conditions: |
Anna Bridge |
169:a7c7b631e539 | 10 | * |
Anna Bridge |
169:a7c7b631e539 | 11 | * The above copyright notice and this permission notice shall be included |
Anna Bridge |
169:a7c7b631e539 | 12 | * in all copies or substantial portions of the Software. |
Anna Bridge |
169:a7c7b631e539 | 13 | * |
Anna Bridge |
169:a7c7b631e539 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
Anna Bridge |
169:a7c7b631e539 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
Anna Bridge |
169:a7c7b631e539 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
Anna Bridge |
169:a7c7b631e539 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
Anna Bridge |
169:a7c7b631e539 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
Anna Bridge |
169:a7c7b631e539 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
Anna Bridge |
169:a7c7b631e539 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
Anna Bridge |
169:a7c7b631e539 | 21 | * |
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169:a7c7b631e539 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
Anna Bridge |
169:a7c7b631e539 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
Anna Bridge |
169:a7c7b631e539 | 24 | * Products, Inc. Branding Policy. |
Anna Bridge |
169:a7c7b631e539 | 25 | * |
Anna Bridge |
169:a7c7b631e539 | 26 | * The mere transfer of this software does not imply any licenses |
Anna Bridge |
169:a7c7b631e539 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
Anna Bridge |
169:a7c7b631e539 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
Anna Bridge |
169:a7c7b631e539 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
Anna Bridge |
169:a7c7b631e539 | 30 | * ownership rights. |
Anna Bridge |
169:a7c7b631e539 | 31 | ******************************************************************************/ |
Anna Bridge |
169:a7c7b631e539 | 32 | |
Anna Bridge |
169:a7c7b631e539 | 33 | #ifndef _MXC_I2CS_REGS_H_ |
Anna Bridge |
169:a7c7b631e539 | 34 | #define _MXC_I2CS_REGS_H_ |
Anna Bridge |
169:a7c7b631e539 | 35 | |
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169:a7c7b631e539 | 36 | #ifdef __cplusplus |
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169:a7c7b631e539 | 37 | extern "C" { |
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169:a7c7b631e539 | 38 | #endif |
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169:a7c7b631e539 | 39 | |
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169:a7c7b631e539 | 40 | #include <stdint.h> |
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169:a7c7b631e539 | 41 | #include "mxc_device.h" |
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169:a7c7b631e539 | 42 | |
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169:a7c7b631e539 | 43 | /* |
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169:a7c7b631e539 | 44 | If types are not defined elsewhere (CMSIS) define them here |
Anna Bridge |
169:a7c7b631e539 | 45 | */ |
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169:a7c7b631e539 | 46 | #ifndef __IO |
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169:a7c7b631e539 | 47 | #define __IO volatile |
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169:a7c7b631e539 | 48 | #endif |
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169:a7c7b631e539 | 49 | #ifndef __I |
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169:a7c7b631e539 | 50 | #define __I volatile const |
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169:a7c7b631e539 | 51 | #endif |
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169:a7c7b631e539 | 52 | #ifndef __O |
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169:a7c7b631e539 | 53 | #define __O volatile |
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169:a7c7b631e539 | 54 | #endif |
Anna Bridge |
169:a7c7b631e539 | 55 | |
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169:a7c7b631e539 | 56 | |
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169:a7c7b631e539 | 57 | /* |
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169:a7c7b631e539 | 58 | Typedefed structure(s) for module registers (per instance or section) with direct 32-bit |
Anna Bridge |
169:a7c7b631e539 | 59 | access to each register in module. |
Anna Bridge |
169:a7c7b631e539 | 60 | */ |
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169:a7c7b631e539 | 61 | |
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169:a7c7b631e539 | 62 | /* Offset Register Description |
Anna Bridge |
169:a7c7b631e539 | 63 | ============= ============================================================================ */ |
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169:a7c7b631e539 | 64 | typedef struct { |
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169:a7c7b631e539 | 65 | __IO uint32_t clk_div; /* 0x0000 I2C Slave Clock Divisor Control */ |
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169:a7c7b631e539 | 66 | __IO uint32_t dev_id; /* 0x0004 I2C Slave Device ID Register */ |
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169:a7c7b631e539 | 67 | __IO uint32_t intfl; /* 0x0008 I2CS Interrupt Flags */ |
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169:a7c7b631e539 | 68 | __IO uint32_t inten; /* 0x000C I2CS Interrupt Enable/Disable Controls */ |
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169:a7c7b631e539 | 69 | __IO uint32_t data_byte[32]; /* 0x0010-0x008C I2CS Data Byte */ |
Anna Bridge |
169:a7c7b631e539 | 70 | } mxc_i2cs_regs_t; |
Anna Bridge |
169:a7c7b631e539 | 71 | |
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169:a7c7b631e539 | 72 | |
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169:a7c7b631e539 | 73 | /* |
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169:a7c7b631e539 | 74 | Register offsets for module I2CS. |
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169:a7c7b631e539 | 75 | */ |
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169:a7c7b631e539 | 76 | |
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169:a7c7b631e539 | 77 | #define MXC_R_I2CS_OFFS_CLK_DIV ((uint32_t)0x00000000UL) |
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169:a7c7b631e539 | 78 | #define MXC_R_I2CS_OFFS_DEV_ID ((uint32_t)0x00000004UL) |
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169:a7c7b631e539 | 79 | #define MXC_R_I2CS_OFFS_INTFL ((uint32_t)0x00000008UL) |
Anna Bridge |
169:a7c7b631e539 | 80 | #define MXC_R_I2CS_OFFS_INTEN ((uint32_t)0x0000000CUL) |
Anna Bridge |
169:a7c7b631e539 | 81 | #define MXC_R_I2CS_OFFS_DATA_BYTE ((uint32_t)0x00000010UL) |
Anna Bridge |
169:a7c7b631e539 | 82 | |
Anna Bridge |
169:a7c7b631e539 | 83 | |
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169:a7c7b631e539 | 84 | /* |
Anna Bridge |
169:a7c7b631e539 | 85 | Field positions and masks for module I2CS. |
Anna Bridge |
169:a7c7b631e539 | 86 | */ |
Anna Bridge |
169:a7c7b631e539 | 87 | |
Anna Bridge |
169:a7c7b631e539 | 88 | #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS 0 |
Anna Bridge |
169:a7c7b631e539 | 89 | #define MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV ((uint32_t)(0x000000FFUL << MXC_F_I2CS_CLK_DIV_FS_FILTER_CLOCK_DIV_POS)) |
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169:a7c7b631e539 | 90 | |
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169:a7c7b631e539 | 91 | #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS 0 |
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169:a7c7b631e539 | 92 | #define MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID ((uint32_t)(0x000003FFUL << MXC_F_I2CS_DEV_ID_SLAVE_DEV_ID_POS)) |
Anna Bridge |
169:a7c7b631e539 | 93 | #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS 12 |
Anna Bridge |
169:a7c7b631e539 | 94 | #define MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_TEN_BIT_ID_MODE_POS)) |
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169:a7c7b631e539 | 95 | #define MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS 14 |
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169:a7c7b631e539 | 96 | #define MXC_F_I2CS_DEV_ID_SLAVE_RESET ((uint32_t)(0x00000001UL << MXC_F_I2CS_DEV_ID_SLAVE_RESET_POS)) |
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169:a7c7b631e539 | 97 | |
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169:a7c7b631e539 | 98 | #define MXC_F_I2CS_INTFL_BYTE0_POS 0 |
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169:a7c7b631e539 | 99 | #define MXC_F_I2CS_INTFL_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE0_POS)) |
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169:a7c7b631e539 | 100 | #define MXC_F_I2CS_INTFL_BYTE1_POS 1 |
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169:a7c7b631e539 | 101 | #define MXC_F_I2CS_INTFL_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE1_POS)) |
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169:a7c7b631e539 | 102 | #define MXC_F_I2CS_INTFL_BYTE2_POS 2 |
Anna Bridge |
169:a7c7b631e539 | 103 | #define MXC_F_I2CS_INTFL_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE2_POS)) |
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169:a7c7b631e539 | 104 | #define MXC_F_I2CS_INTFL_BYTE3_POS 3 |
Anna Bridge |
169:a7c7b631e539 | 105 | #define MXC_F_I2CS_INTFL_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE3_POS)) |
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169:a7c7b631e539 | 106 | #define MXC_F_I2CS_INTFL_BYTE4_POS 4 |
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169:a7c7b631e539 | 107 | #define MXC_F_I2CS_INTFL_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE4_POS)) |
Anna Bridge |
169:a7c7b631e539 | 108 | #define MXC_F_I2CS_INTFL_BYTE5_POS 5 |
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169:a7c7b631e539 | 109 | #define MXC_F_I2CS_INTFL_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE5_POS)) |
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169:a7c7b631e539 | 110 | #define MXC_F_I2CS_INTFL_BYTE6_POS 6 |
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169:a7c7b631e539 | 111 | #define MXC_F_I2CS_INTFL_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE6_POS)) |
Anna Bridge |
169:a7c7b631e539 | 112 | #define MXC_F_I2CS_INTFL_BYTE7_POS 7 |
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169:a7c7b631e539 | 113 | #define MXC_F_I2CS_INTFL_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE7_POS)) |
Anna Bridge |
169:a7c7b631e539 | 114 | #define MXC_F_I2CS_INTFL_BYTE8_POS 8 |
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169:a7c7b631e539 | 115 | #define MXC_F_I2CS_INTFL_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE8_POS)) |
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169:a7c7b631e539 | 116 | #define MXC_F_I2CS_INTFL_BYTE9_POS 9 |
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169:a7c7b631e539 | 117 | #define MXC_F_I2CS_INTFL_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE9_POS)) |
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169:a7c7b631e539 | 118 | #define MXC_F_I2CS_INTFL_BYTE10_POS 10 |
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169:a7c7b631e539 | 119 | #define MXC_F_I2CS_INTFL_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE10_POS)) |
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169:a7c7b631e539 | 120 | #define MXC_F_I2CS_INTFL_BYTE11_POS 11 |
Anna Bridge |
169:a7c7b631e539 | 121 | #define MXC_F_I2CS_INTFL_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE11_POS)) |
Anna Bridge |
169:a7c7b631e539 | 122 | #define MXC_F_I2CS_INTFL_BYTE12_POS 12 |
Anna Bridge |
169:a7c7b631e539 | 123 | #define MXC_F_I2CS_INTFL_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE12_POS)) |
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169:a7c7b631e539 | 124 | #define MXC_F_I2CS_INTFL_BYTE13_POS 13 |
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169:a7c7b631e539 | 125 | #define MXC_F_I2CS_INTFL_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE13_POS)) |
Anna Bridge |
169:a7c7b631e539 | 126 | #define MXC_F_I2CS_INTFL_BYTE14_POS 14 |
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169:a7c7b631e539 | 127 | #define MXC_F_I2CS_INTFL_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE14_POS)) |
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169:a7c7b631e539 | 128 | #define MXC_F_I2CS_INTFL_BYTE15_POS 15 |
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169:a7c7b631e539 | 129 | #define MXC_F_I2CS_INTFL_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE15_POS)) |
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169:a7c7b631e539 | 130 | #define MXC_F_I2CS_INTFL_BYTE16_POS 16 |
Anna Bridge |
169:a7c7b631e539 | 131 | #define MXC_F_I2CS_INTFL_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE16_POS)) |
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169:a7c7b631e539 | 132 | #define MXC_F_I2CS_INTFL_BYTE17_POS 17 |
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169:a7c7b631e539 | 133 | #define MXC_F_I2CS_INTFL_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE17_POS)) |
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169:a7c7b631e539 | 134 | #define MXC_F_I2CS_INTFL_BYTE18_POS 18 |
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169:a7c7b631e539 | 135 | #define MXC_F_I2CS_INTFL_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE18_POS)) |
Anna Bridge |
169:a7c7b631e539 | 136 | #define MXC_F_I2CS_INTFL_BYTE19_POS 19 |
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169:a7c7b631e539 | 137 | #define MXC_F_I2CS_INTFL_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE19_POS)) |
Anna Bridge |
169:a7c7b631e539 | 138 | #define MXC_F_I2CS_INTFL_BYTE20_POS 20 |
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169:a7c7b631e539 | 139 | #define MXC_F_I2CS_INTFL_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE20_POS)) |
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169:a7c7b631e539 | 140 | #define MXC_F_I2CS_INTFL_BYTE21_POS 21 |
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169:a7c7b631e539 | 141 | #define MXC_F_I2CS_INTFL_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE21_POS)) |
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169:a7c7b631e539 | 142 | #define MXC_F_I2CS_INTFL_BYTE22_POS 22 |
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169:a7c7b631e539 | 143 | #define MXC_F_I2CS_INTFL_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE22_POS)) |
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169:a7c7b631e539 | 144 | #define MXC_F_I2CS_INTFL_BYTE23_POS 23 |
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169:a7c7b631e539 | 145 | #define MXC_F_I2CS_INTFL_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE23_POS)) |
Anna Bridge |
169:a7c7b631e539 | 146 | #define MXC_F_I2CS_INTFL_BYTE24_POS 24 |
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169:a7c7b631e539 | 147 | #define MXC_F_I2CS_INTFL_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE24_POS)) |
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169:a7c7b631e539 | 148 | #define MXC_F_I2CS_INTFL_BYTE25_POS 25 |
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169:a7c7b631e539 | 149 | #define MXC_F_I2CS_INTFL_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE25_POS)) |
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169:a7c7b631e539 | 150 | #define MXC_F_I2CS_INTFL_BYTE26_POS 26 |
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169:a7c7b631e539 | 151 | #define MXC_F_I2CS_INTFL_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE26_POS)) |
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169:a7c7b631e539 | 152 | #define MXC_F_I2CS_INTFL_BYTE27_POS 27 |
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169:a7c7b631e539 | 153 | #define MXC_F_I2CS_INTFL_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE27_POS)) |
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169:a7c7b631e539 | 154 | #define MXC_F_I2CS_INTFL_BYTE28_POS 28 |
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169:a7c7b631e539 | 155 | #define MXC_F_I2CS_INTFL_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE28_POS)) |
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169:a7c7b631e539 | 156 | #define MXC_F_I2CS_INTFL_BYTE29_POS 29 |
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169:a7c7b631e539 | 157 | #define MXC_F_I2CS_INTFL_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE29_POS)) |
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169:a7c7b631e539 | 158 | #define MXC_F_I2CS_INTFL_BYTE30_POS 30 |
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169:a7c7b631e539 | 159 | #define MXC_F_I2CS_INTFL_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE30_POS)) |
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169:a7c7b631e539 | 160 | #define MXC_F_I2CS_INTFL_BYTE31_POS 31 |
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169:a7c7b631e539 | 161 | #define MXC_F_I2CS_INTFL_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTFL_BYTE31_POS)) |
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169:a7c7b631e539 | 162 | |
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169:a7c7b631e539 | 163 | #define MXC_F_I2CS_INTEN_BYTE0_POS 0 |
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169:a7c7b631e539 | 164 | #define MXC_F_I2CS_INTEN_BYTE0 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE0_POS)) |
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169:a7c7b631e539 | 165 | #define MXC_F_I2CS_INTEN_BYTE1_POS 1 |
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169:a7c7b631e539 | 166 | #define MXC_F_I2CS_INTEN_BYTE1 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE1_POS)) |
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169:a7c7b631e539 | 167 | #define MXC_F_I2CS_INTEN_BYTE2_POS 2 |
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169:a7c7b631e539 | 168 | #define MXC_F_I2CS_INTEN_BYTE2 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE2_POS)) |
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169:a7c7b631e539 | 169 | #define MXC_F_I2CS_INTEN_BYTE3_POS 3 |
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169:a7c7b631e539 | 170 | #define MXC_F_I2CS_INTEN_BYTE3 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE3_POS)) |
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169:a7c7b631e539 | 171 | #define MXC_F_I2CS_INTEN_BYTE4_POS 4 |
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169:a7c7b631e539 | 172 | #define MXC_F_I2CS_INTEN_BYTE4 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE4_POS)) |
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169:a7c7b631e539 | 173 | #define MXC_F_I2CS_INTEN_BYTE5_POS 5 |
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169:a7c7b631e539 | 174 | #define MXC_F_I2CS_INTEN_BYTE5 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE5_POS)) |
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169:a7c7b631e539 | 175 | #define MXC_F_I2CS_INTEN_BYTE6_POS 6 |
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169:a7c7b631e539 | 176 | #define MXC_F_I2CS_INTEN_BYTE6 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE6_POS)) |
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169:a7c7b631e539 | 177 | #define MXC_F_I2CS_INTEN_BYTE7_POS 7 |
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169:a7c7b631e539 | 178 | #define MXC_F_I2CS_INTEN_BYTE7 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE7_POS)) |
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169:a7c7b631e539 | 179 | #define MXC_F_I2CS_INTEN_BYTE8_POS 8 |
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169:a7c7b631e539 | 180 | #define MXC_F_I2CS_INTEN_BYTE8 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE8_POS)) |
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169:a7c7b631e539 | 181 | #define MXC_F_I2CS_INTEN_BYTE9_POS 9 |
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169:a7c7b631e539 | 182 | #define MXC_F_I2CS_INTEN_BYTE9 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE9_POS)) |
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169:a7c7b631e539 | 183 | #define MXC_F_I2CS_INTEN_BYTE10_POS 10 |
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169:a7c7b631e539 | 184 | #define MXC_F_I2CS_INTEN_BYTE10 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE10_POS)) |
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169:a7c7b631e539 | 185 | #define MXC_F_I2CS_INTEN_BYTE11_POS 11 |
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169:a7c7b631e539 | 186 | #define MXC_F_I2CS_INTEN_BYTE11 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE11_POS)) |
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169:a7c7b631e539 | 187 | #define MXC_F_I2CS_INTEN_BYTE12_POS 12 |
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169:a7c7b631e539 | 188 | #define MXC_F_I2CS_INTEN_BYTE12 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE12_POS)) |
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169:a7c7b631e539 | 189 | #define MXC_F_I2CS_INTEN_BYTE13_POS 13 |
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169:a7c7b631e539 | 190 | #define MXC_F_I2CS_INTEN_BYTE13 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE13_POS)) |
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169:a7c7b631e539 | 191 | #define MXC_F_I2CS_INTEN_BYTE14_POS 14 |
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169:a7c7b631e539 | 192 | #define MXC_F_I2CS_INTEN_BYTE14 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE14_POS)) |
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169:a7c7b631e539 | 193 | #define MXC_F_I2CS_INTEN_BYTE15_POS 15 |
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169:a7c7b631e539 | 194 | #define MXC_F_I2CS_INTEN_BYTE15 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE15_POS)) |
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169:a7c7b631e539 | 195 | #define MXC_F_I2CS_INTEN_BYTE16_POS 16 |
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169:a7c7b631e539 | 196 | #define MXC_F_I2CS_INTEN_BYTE16 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE16_POS)) |
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169:a7c7b631e539 | 197 | #define MXC_F_I2CS_INTEN_BYTE17_POS 17 |
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169:a7c7b631e539 | 198 | #define MXC_F_I2CS_INTEN_BYTE17 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE17_POS)) |
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169:a7c7b631e539 | 199 | #define MXC_F_I2CS_INTEN_BYTE18_POS 18 |
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169:a7c7b631e539 | 200 | #define MXC_F_I2CS_INTEN_BYTE18 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE18_POS)) |
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169:a7c7b631e539 | 201 | #define MXC_F_I2CS_INTEN_BYTE19_POS 19 |
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169:a7c7b631e539 | 202 | #define MXC_F_I2CS_INTEN_BYTE19 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE19_POS)) |
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169:a7c7b631e539 | 203 | #define MXC_F_I2CS_INTEN_BYTE20_POS 20 |
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169:a7c7b631e539 | 204 | #define MXC_F_I2CS_INTEN_BYTE20 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE20_POS)) |
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169:a7c7b631e539 | 205 | #define MXC_F_I2CS_INTEN_BYTE21_POS 21 |
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169:a7c7b631e539 | 206 | #define MXC_F_I2CS_INTEN_BYTE21 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE21_POS)) |
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169:a7c7b631e539 | 207 | #define MXC_F_I2CS_INTEN_BYTE22_POS 22 |
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169:a7c7b631e539 | 208 | #define MXC_F_I2CS_INTEN_BYTE22 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE22_POS)) |
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169:a7c7b631e539 | 209 | #define MXC_F_I2CS_INTEN_BYTE23_POS 23 |
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169:a7c7b631e539 | 210 | #define MXC_F_I2CS_INTEN_BYTE23 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE23_POS)) |
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169:a7c7b631e539 | 211 | #define MXC_F_I2CS_INTEN_BYTE24_POS 24 |
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169:a7c7b631e539 | 212 | #define MXC_F_I2CS_INTEN_BYTE24 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE24_POS)) |
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169:a7c7b631e539 | 213 | #define MXC_F_I2CS_INTEN_BYTE25_POS 25 |
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169:a7c7b631e539 | 214 | #define MXC_F_I2CS_INTEN_BYTE25 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE25_POS)) |
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169:a7c7b631e539 | 215 | #define MXC_F_I2CS_INTEN_BYTE26_POS 26 |
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169:a7c7b631e539 | 216 | #define MXC_F_I2CS_INTEN_BYTE26 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE26_POS)) |
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169:a7c7b631e539 | 217 | #define MXC_F_I2CS_INTEN_BYTE27_POS 27 |
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169:a7c7b631e539 | 218 | #define MXC_F_I2CS_INTEN_BYTE27 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE27_POS)) |
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169:a7c7b631e539 | 219 | #define MXC_F_I2CS_INTEN_BYTE28_POS 28 |
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169:a7c7b631e539 | 220 | #define MXC_F_I2CS_INTEN_BYTE28 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE28_POS)) |
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169:a7c7b631e539 | 221 | #define MXC_F_I2CS_INTEN_BYTE29_POS 29 |
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169:a7c7b631e539 | 222 | #define MXC_F_I2CS_INTEN_BYTE29 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE29_POS)) |
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169:a7c7b631e539 | 223 | #define MXC_F_I2CS_INTEN_BYTE30_POS 30 |
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169:a7c7b631e539 | 224 | #define MXC_F_I2CS_INTEN_BYTE30 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE30_POS)) |
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169:a7c7b631e539 | 225 | #define MXC_F_I2CS_INTEN_BYTE31_POS 31 |
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169:a7c7b631e539 | 226 | #define MXC_F_I2CS_INTEN_BYTE31 ((uint32_t)(0x00000001UL << MXC_F_I2CS_INTEN_BYTE31_POS)) |
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169:a7c7b631e539 | 227 | |
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169:a7c7b631e539 | 228 | #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS 0 |
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169:a7c7b631e539 | 229 | #define MXC_F_I2CS_DATA_BYTE_DATA_FIELD ((uint32_t)(0x000000FFUL << MXC_F_I2CS_DATA_BYTE_DATA_FIELD_POS)) |
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169:a7c7b631e539 | 230 | #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS 8 |
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169:a7c7b631e539 | 231 | #define MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_READ_ONLY_FL_POS)) |
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169:a7c7b631e539 | 232 | #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS 9 |
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169:a7c7b631e539 | 233 | #define MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL ((uint32_t)(0x00000001UL << MXC_F_I2CS_DATA_BYTE_DATA_UPDATED_FL_POS)) |
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169:a7c7b631e539 | 234 | |
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169:a7c7b631e539 | 235 | |
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169:a7c7b631e539 | 236 | |
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169:a7c7b631e539 | 237 | #ifdef __cplusplus |
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169:a7c7b631e539 | 238 | } |
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169:a7c7b631e539 | 239 | #endif |
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169:a7c7b631e539 | 240 | |
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169:a7c7b631e539 | 241 | #endif /* _MXC_I2CS_REGS_H_ */ |
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169:a7c7b631e539 | 242 |