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mbed 2

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TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/comp_wdt.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for WDT
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_WDT_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_WDT_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR WDT */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_WDT Watchdog Timer */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define WDT_U2203
AnnaBridge 171:3a7713b1edbc 54 #define REV_WDT 0x200
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint8_t :1; /*!< bit: 0 Reserved */
AnnaBridge 171:3a7713b1edbc 61 uint8_t ENABLE:1; /*!< bit: 1 Enable */
AnnaBridge 171:3a7713b1edbc 62 uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
AnnaBridge 171:3a7713b1edbc 63 uint8_t :4; /*!< bit: 3.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 64 uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
AnnaBridge 171:3a7713b1edbc 65 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 66 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 67 } WDT_CTRL_Type;
AnnaBridge 171:3a7713b1edbc 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 #define WDT_CTRL_OFFSET 0x0 /**< \brief (WDT_CTRL offset) Control */
AnnaBridge 171:3a7713b1edbc 71 #define WDT_CTRL_RESETVALUE 0x00ul /**< \brief (WDT_CTRL reset_value) Control */
AnnaBridge 171:3a7713b1edbc 72
AnnaBridge 171:3a7713b1edbc 73 #define WDT_CTRL_ENABLE_Pos 1 /**< \brief (WDT_CTRL) Enable */
AnnaBridge 171:3a7713b1edbc 74 #define WDT_CTRL_ENABLE (0x1ul << WDT_CTRL_ENABLE_Pos)
AnnaBridge 171:3a7713b1edbc 75 #define WDT_CTRL_WEN_Pos 2 /**< \brief (WDT_CTRL) Watchdog Timer Window Mode Enable */
AnnaBridge 171:3a7713b1edbc 76 #define WDT_CTRL_WEN (0x1ul << WDT_CTRL_WEN_Pos)
AnnaBridge 171:3a7713b1edbc 77 #define WDT_CTRL_ALWAYSON_Pos 7 /**< \brief (WDT_CTRL) Always-On */
AnnaBridge 171:3a7713b1edbc 78 #define WDT_CTRL_ALWAYSON (0x1ul << WDT_CTRL_ALWAYSON_Pos)
AnnaBridge 171:3a7713b1edbc 79 #define WDT_CTRL_MASK 0x86ul /**< \brief (WDT_CTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
AnnaBridge 171:3a7713b1edbc 82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 83 typedef union {
AnnaBridge 171:3a7713b1edbc 84 struct {
AnnaBridge 171:3a7713b1edbc 85 uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
AnnaBridge 171:3a7713b1edbc 86 uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
AnnaBridge 171:3a7713b1edbc 87 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 88 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 89 } WDT_CONFIG_Type;
AnnaBridge 171:3a7713b1edbc 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 91
AnnaBridge 171:3a7713b1edbc 92 #define WDT_CONFIG_OFFSET 0x1 /**< \brief (WDT_CONFIG offset) Configuration */
AnnaBridge 171:3a7713b1edbc 93 #define WDT_CONFIG_RESETVALUE 0xBBul /**< \brief (WDT_CONFIG reset_value) Configuration */
AnnaBridge 171:3a7713b1edbc 94
AnnaBridge 171:3a7713b1edbc 95 #define WDT_CONFIG_PER_Pos 0 /**< \brief (WDT_CONFIG) Time-Out Period */
AnnaBridge 171:3a7713b1edbc 96 #define WDT_CONFIG_PER_Msk (0xFul << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 97 #define WDT_CONFIG_PER(value) (WDT_CONFIG_PER_Msk & ((value) << WDT_CONFIG_PER_Pos))
AnnaBridge 171:3a7713b1edbc 98 #define WDT_CONFIG_PER_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
AnnaBridge 171:3a7713b1edbc 99 #define WDT_CONFIG_PER_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
AnnaBridge 171:3a7713b1edbc 100 #define WDT_CONFIG_PER_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
AnnaBridge 171:3a7713b1edbc 101 #define WDT_CONFIG_PER_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
AnnaBridge 171:3a7713b1edbc 102 #define WDT_CONFIG_PER_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
AnnaBridge 171:3a7713b1edbc 103 #define WDT_CONFIG_PER_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
AnnaBridge 171:3a7713b1edbc 104 #define WDT_CONFIG_PER_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
AnnaBridge 171:3a7713b1edbc 105 #define WDT_CONFIG_PER_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
AnnaBridge 171:3a7713b1edbc 106 #define WDT_CONFIG_PER_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
AnnaBridge 171:3a7713b1edbc 107 #define WDT_CONFIG_PER_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
AnnaBridge 171:3a7713b1edbc 108 #define WDT_CONFIG_PER_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
AnnaBridge 171:3a7713b1edbc 109 #define WDT_CONFIG_PER_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
AnnaBridge 171:3a7713b1edbc 110 #define WDT_CONFIG_PER_8 (WDT_CONFIG_PER_8_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 111 #define WDT_CONFIG_PER_16 (WDT_CONFIG_PER_16_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 112 #define WDT_CONFIG_PER_32 (WDT_CONFIG_PER_32_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 113 #define WDT_CONFIG_PER_64 (WDT_CONFIG_PER_64_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 114 #define WDT_CONFIG_PER_128 (WDT_CONFIG_PER_128_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 115 #define WDT_CONFIG_PER_256 (WDT_CONFIG_PER_256_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 116 #define WDT_CONFIG_PER_512 (WDT_CONFIG_PER_512_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 117 #define WDT_CONFIG_PER_1K (WDT_CONFIG_PER_1K_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 118 #define WDT_CONFIG_PER_2K (WDT_CONFIG_PER_2K_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 119 #define WDT_CONFIG_PER_4K (WDT_CONFIG_PER_4K_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 120 #define WDT_CONFIG_PER_8K (WDT_CONFIG_PER_8K_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 121 #define WDT_CONFIG_PER_16K (WDT_CONFIG_PER_16K_Val << WDT_CONFIG_PER_Pos)
AnnaBridge 171:3a7713b1edbc 122 #define WDT_CONFIG_WINDOW_Pos 4 /**< \brief (WDT_CONFIG) Window Mode Time-Out Period */
AnnaBridge 171:3a7713b1edbc 123 #define WDT_CONFIG_WINDOW_Msk (0xFul << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 124 #define WDT_CONFIG_WINDOW(value) (WDT_CONFIG_WINDOW_Msk & ((value) << WDT_CONFIG_WINDOW_Pos))
AnnaBridge 171:3a7713b1edbc 125 #define WDT_CONFIG_WINDOW_8_Val 0x0ul /**< \brief (WDT_CONFIG) 8 clock cycles */
AnnaBridge 171:3a7713b1edbc 126 #define WDT_CONFIG_WINDOW_16_Val 0x1ul /**< \brief (WDT_CONFIG) 16 clock cycles */
AnnaBridge 171:3a7713b1edbc 127 #define WDT_CONFIG_WINDOW_32_Val 0x2ul /**< \brief (WDT_CONFIG) 32 clock cycles */
AnnaBridge 171:3a7713b1edbc 128 #define WDT_CONFIG_WINDOW_64_Val 0x3ul /**< \brief (WDT_CONFIG) 64 clock cycles */
AnnaBridge 171:3a7713b1edbc 129 #define WDT_CONFIG_WINDOW_128_Val 0x4ul /**< \brief (WDT_CONFIG) 128 clock cycles */
AnnaBridge 171:3a7713b1edbc 130 #define WDT_CONFIG_WINDOW_256_Val 0x5ul /**< \brief (WDT_CONFIG) 256 clock cycles */
AnnaBridge 171:3a7713b1edbc 131 #define WDT_CONFIG_WINDOW_512_Val 0x6ul /**< \brief (WDT_CONFIG) 512 clock cycles */
AnnaBridge 171:3a7713b1edbc 132 #define WDT_CONFIG_WINDOW_1K_Val 0x7ul /**< \brief (WDT_CONFIG) 1024 clock cycles */
AnnaBridge 171:3a7713b1edbc 133 #define WDT_CONFIG_WINDOW_2K_Val 0x8ul /**< \brief (WDT_CONFIG) 2048 clock cycles */
AnnaBridge 171:3a7713b1edbc 134 #define WDT_CONFIG_WINDOW_4K_Val 0x9ul /**< \brief (WDT_CONFIG) 4096 clock cycles */
AnnaBridge 171:3a7713b1edbc 135 #define WDT_CONFIG_WINDOW_8K_Val 0xAul /**< \brief (WDT_CONFIG) 8192 clock cycles */
AnnaBridge 171:3a7713b1edbc 136 #define WDT_CONFIG_WINDOW_16K_Val 0xBul /**< \brief (WDT_CONFIG) 16384 clock cycles */
AnnaBridge 171:3a7713b1edbc 137 #define WDT_CONFIG_WINDOW_8 (WDT_CONFIG_WINDOW_8_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 138 #define WDT_CONFIG_WINDOW_16 (WDT_CONFIG_WINDOW_16_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 139 #define WDT_CONFIG_WINDOW_32 (WDT_CONFIG_WINDOW_32_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 140 #define WDT_CONFIG_WINDOW_64 (WDT_CONFIG_WINDOW_64_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 141 #define WDT_CONFIG_WINDOW_128 (WDT_CONFIG_WINDOW_128_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 142 #define WDT_CONFIG_WINDOW_256 (WDT_CONFIG_WINDOW_256_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 143 #define WDT_CONFIG_WINDOW_512 (WDT_CONFIG_WINDOW_512_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 144 #define WDT_CONFIG_WINDOW_1K (WDT_CONFIG_WINDOW_1K_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 145 #define WDT_CONFIG_WINDOW_2K (WDT_CONFIG_WINDOW_2K_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 146 #define WDT_CONFIG_WINDOW_4K (WDT_CONFIG_WINDOW_4K_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 147 #define WDT_CONFIG_WINDOW_8K (WDT_CONFIG_WINDOW_8K_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 148 #define WDT_CONFIG_WINDOW_16K (WDT_CONFIG_WINDOW_16K_Val << WDT_CONFIG_WINDOW_Pos)
AnnaBridge 171:3a7713b1edbc 149 #define WDT_CONFIG_MASK 0xFFul /**< \brief (WDT_CONFIG) MASK Register */
AnnaBridge 171:3a7713b1edbc 150
AnnaBridge 171:3a7713b1edbc 151 /* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
AnnaBridge 171:3a7713b1edbc 152 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 153 typedef union {
AnnaBridge 171:3a7713b1edbc 154 struct {
AnnaBridge 171:3a7713b1edbc 155 uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
AnnaBridge 171:3a7713b1edbc 156 uint8_t :4; /*!< bit: 4.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 157 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 158 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 159 } WDT_EWCTRL_Type;
AnnaBridge 171:3a7713b1edbc 160 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 161
AnnaBridge 171:3a7713b1edbc 162 #define WDT_EWCTRL_OFFSET 0x2 /**< \brief (WDT_EWCTRL offset) Early Warning Interrupt Control */
AnnaBridge 171:3a7713b1edbc 163 #define WDT_EWCTRL_RESETVALUE 0x0Bul /**< \brief (WDT_EWCTRL reset_value) Early Warning Interrupt Control */
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165 #define WDT_EWCTRL_EWOFFSET_Pos 0 /**< \brief (WDT_EWCTRL) Early Warning Interrupt Time Offset */
AnnaBridge 171:3a7713b1edbc 166 #define WDT_EWCTRL_EWOFFSET_Msk (0xFul << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 167 #define WDT_EWCTRL_EWOFFSET(value) (WDT_EWCTRL_EWOFFSET_Msk & ((value) << WDT_EWCTRL_EWOFFSET_Pos))
AnnaBridge 171:3a7713b1edbc 168 #define WDT_EWCTRL_EWOFFSET_8_Val 0x0ul /**< \brief (WDT_EWCTRL) 8 clock cycles */
AnnaBridge 171:3a7713b1edbc 169 #define WDT_EWCTRL_EWOFFSET_16_Val 0x1ul /**< \brief (WDT_EWCTRL) 16 clock cycles */
AnnaBridge 171:3a7713b1edbc 170 #define WDT_EWCTRL_EWOFFSET_32_Val 0x2ul /**< \brief (WDT_EWCTRL) 32 clock cycles */
AnnaBridge 171:3a7713b1edbc 171 #define WDT_EWCTRL_EWOFFSET_64_Val 0x3ul /**< \brief (WDT_EWCTRL) 64 clock cycles */
AnnaBridge 171:3a7713b1edbc 172 #define WDT_EWCTRL_EWOFFSET_128_Val 0x4ul /**< \brief (WDT_EWCTRL) 128 clock cycles */
AnnaBridge 171:3a7713b1edbc 173 #define WDT_EWCTRL_EWOFFSET_256_Val 0x5ul /**< \brief (WDT_EWCTRL) 256 clock cycles */
AnnaBridge 171:3a7713b1edbc 174 #define WDT_EWCTRL_EWOFFSET_512_Val 0x6ul /**< \brief (WDT_EWCTRL) 512 clock cycles */
AnnaBridge 171:3a7713b1edbc 175 #define WDT_EWCTRL_EWOFFSET_1K_Val 0x7ul /**< \brief (WDT_EWCTRL) 1024 clock cycles */
AnnaBridge 171:3a7713b1edbc 176 #define WDT_EWCTRL_EWOFFSET_2K_Val 0x8ul /**< \brief (WDT_EWCTRL) 2048 clock cycles */
AnnaBridge 171:3a7713b1edbc 177 #define WDT_EWCTRL_EWOFFSET_4K_Val 0x9ul /**< \brief (WDT_EWCTRL) 4096 clock cycles */
AnnaBridge 171:3a7713b1edbc 178 #define WDT_EWCTRL_EWOFFSET_8K_Val 0xAul /**< \brief (WDT_EWCTRL) 8192 clock cycles */
AnnaBridge 171:3a7713b1edbc 179 #define WDT_EWCTRL_EWOFFSET_16K_Val 0xBul /**< \brief (WDT_EWCTRL) 16384 clock cycles */
AnnaBridge 171:3a7713b1edbc 180 #define WDT_EWCTRL_EWOFFSET_8 (WDT_EWCTRL_EWOFFSET_8_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 181 #define WDT_EWCTRL_EWOFFSET_16 (WDT_EWCTRL_EWOFFSET_16_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 182 #define WDT_EWCTRL_EWOFFSET_32 (WDT_EWCTRL_EWOFFSET_32_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 183 #define WDT_EWCTRL_EWOFFSET_64 (WDT_EWCTRL_EWOFFSET_64_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 184 #define WDT_EWCTRL_EWOFFSET_128 (WDT_EWCTRL_EWOFFSET_128_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 185 #define WDT_EWCTRL_EWOFFSET_256 (WDT_EWCTRL_EWOFFSET_256_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 186 #define WDT_EWCTRL_EWOFFSET_512 (WDT_EWCTRL_EWOFFSET_512_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 187 #define WDT_EWCTRL_EWOFFSET_1K (WDT_EWCTRL_EWOFFSET_1K_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 188 #define WDT_EWCTRL_EWOFFSET_2K (WDT_EWCTRL_EWOFFSET_2K_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 189 #define WDT_EWCTRL_EWOFFSET_4K (WDT_EWCTRL_EWOFFSET_4K_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 190 #define WDT_EWCTRL_EWOFFSET_8K (WDT_EWCTRL_EWOFFSET_8K_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 191 #define WDT_EWCTRL_EWOFFSET_16K (WDT_EWCTRL_EWOFFSET_16K_Val << WDT_EWCTRL_EWOFFSET_Pos)
AnnaBridge 171:3a7713b1edbc 192 #define WDT_EWCTRL_MASK 0x0Ful /**< \brief (WDT_EWCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 193
AnnaBridge 171:3a7713b1edbc 194 /* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
AnnaBridge 171:3a7713b1edbc 195 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 196 typedef union {
AnnaBridge 171:3a7713b1edbc 197 struct {
AnnaBridge 171:3a7713b1edbc 198 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 199 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 200 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 201 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 202 } WDT_INTENCLR_Type;
AnnaBridge 171:3a7713b1edbc 203 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 204
AnnaBridge 171:3a7713b1edbc 205 #define WDT_INTENCLR_OFFSET 0x4 /**< \brief (WDT_INTENCLR offset) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 206 #define WDT_INTENCLR_RESETVALUE 0x00ul /**< \brief (WDT_INTENCLR reset_value) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208 #define WDT_INTENCLR_EW_Pos 0 /**< \brief (WDT_INTENCLR) Early Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 209 #define WDT_INTENCLR_EW (0x1ul << WDT_INTENCLR_EW_Pos)
AnnaBridge 171:3a7713b1edbc 210 #define WDT_INTENCLR_MASK 0x01ul /**< \brief (WDT_INTENCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 211
AnnaBridge 171:3a7713b1edbc 212 /* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
AnnaBridge 171:3a7713b1edbc 213 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 214 typedef union {
AnnaBridge 171:3a7713b1edbc 215 struct {
AnnaBridge 171:3a7713b1edbc 216 uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 217 uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 218 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 219 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 220 } WDT_INTENSET_Type;
AnnaBridge 171:3a7713b1edbc 221 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 222
AnnaBridge 171:3a7713b1edbc 223 #define WDT_INTENSET_OFFSET 0x5 /**< \brief (WDT_INTENSET offset) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 224 #define WDT_INTENSET_RESETVALUE 0x00ul /**< \brief (WDT_INTENSET reset_value) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 #define WDT_INTENSET_EW_Pos 0 /**< \brief (WDT_INTENSET) Early Warning Interrupt Enable */
AnnaBridge 171:3a7713b1edbc 227 #define WDT_INTENSET_EW (0x1ul << WDT_INTENSET_EW_Pos)
AnnaBridge 171:3a7713b1edbc 228 #define WDT_INTENSET_MASK 0x01ul /**< \brief (WDT_INTENSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 229
AnnaBridge 171:3a7713b1edbc 230 /* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
AnnaBridge 171:3a7713b1edbc 231 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 232 typedef union { // __I to avoid read-modify-write on write-to-clear register
AnnaBridge 171:3a7713b1edbc 233 struct {
AnnaBridge 171:3a7713b1edbc 234 __I uint8_t EW:1; /*!< bit: 0 Early Warning */
AnnaBridge 171:3a7713b1edbc 235 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */
AnnaBridge 171:3a7713b1edbc 236 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 237 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 238 } WDT_INTFLAG_Type;
AnnaBridge 171:3a7713b1edbc 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 240
AnnaBridge 171:3a7713b1edbc 241 #define WDT_INTFLAG_OFFSET 0x6 /**< \brief (WDT_INTFLAG offset) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 242 #define WDT_INTFLAG_RESETVALUE 0x00ul /**< \brief (WDT_INTFLAG reset_value) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 243
AnnaBridge 171:3a7713b1edbc 244 #define WDT_INTFLAG_EW_Pos 0 /**< \brief (WDT_INTFLAG) Early Warning */
AnnaBridge 171:3a7713b1edbc 245 #define WDT_INTFLAG_EW (0x1ul << WDT_INTFLAG_EW_Pos)
AnnaBridge 171:3a7713b1edbc 246 #define WDT_INTFLAG_MASK 0x01ul /**< \brief (WDT_INTFLAG) MASK Register */
AnnaBridge 171:3a7713b1edbc 247
AnnaBridge 171:3a7713b1edbc 248 /* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
AnnaBridge 171:3a7713b1edbc 249 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 250 typedef union {
AnnaBridge 171:3a7713b1edbc 251 struct {
AnnaBridge 171:3a7713b1edbc 252 uint8_t :7; /*!< bit: 0.. 6 Reserved */
AnnaBridge 171:3a7713b1edbc 253 uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 254 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 255 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 256 } WDT_STATUS_Type;
AnnaBridge 171:3a7713b1edbc 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 #define WDT_STATUS_OFFSET 0x7 /**< \brief (WDT_STATUS offset) Status */
AnnaBridge 171:3a7713b1edbc 260 #define WDT_STATUS_RESETVALUE 0x00ul /**< \brief (WDT_STATUS reset_value) Status */
AnnaBridge 171:3a7713b1edbc 261
AnnaBridge 171:3a7713b1edbc 262 #define WDT_STATUS_SYNCBUSY_Pos 7 /**< \brief (WDT_STATUS) Synchronization Busy */
AnnaBridge 171:3a7713b1edbc 263 #define WDT_STATUS_SYNCBUSY (0x1ul << WDT_STATUS_SYNCBUSY_Pos)
AnnaBridge 171:3a7713b1edbc 264 #define WDT_STATUS_MASK 0x80ul /**< \brief (WDT_STATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 /* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
AnnaBridge 171:3a7713b1edbc 267 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 268 typedef union {
AnnaBridge 171:3a7713b1edbc 269 struct {
AnnaBridge 171:3a7713b1edbc 270 uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
AnnaBridge 171:3a7713b1edbc 271 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 272 uint8_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 273 } WDT_CLEAR_Type;
AnnaBridge 171:3a7713b1edbc 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #define WDT_CLEAR_OFFSET 0x8 /**< \brief (WDT_CLEAR offset) Clear */
AnnaBridge 171:3a7713b1edbc 277 #define WDT_CLEAR_RESETVALUE 0x00ul /**< \brief (WDT_CLEAR reset_value) Clear */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 #define WDT_CLEAR_CLEAR_Pos 0 /**< \brief (WDT_CLEAR) Watchdog Clear */
AnnaBridge 171:3a7713b1edbc 280 #define WDT_CLEAR_CLEAR_Msk (0xFFul << WDT_CLEAR_CLEAR_Pos)
AnnaBridge 171:3a7713b1edbc 281 #define WDT_CLEAR_CLEAR(value) (WDT_CLEAR_CLEAR_Msk & ((value) << WDT_CLEAR_CLEAR_Pos))
AnnaBridge 171:3a7713b1edbc 282 #define WDT_CLEAR_CLEAR_KEY_Val 0xA5ul /**< \brief (WDT_CLEAR) Clear Key */
AnnaBridge 171:3a7713b1edbc 283 #define WDT_CLEAR_CLEAR_KEY (WDT_CLEAR_CLEAR_KEY_Val << WDT_CLEAR_CLEAR_Pos)
AnnaBridge 171:3a7713b1edbc 284 #define WDT_CLEAR_MASK 0xFFul /**< \brief (WDT_CLEAR) MASK Register */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 /** \brief WDT hardware registers */
AnnaBridge 171:3a7713b1edbc 287 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 288 typedef struct {
AnnaBridge 171:3a7713b1edbc 289 __IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
AnnaBridge 171:3a7713b1edbc 290 __IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
AnnaBridge 171:3a7713b1edbc 291 __IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
AnnaBridge 171:3a7713b1edbc 292 RoReg8 Reserved1[0x1];
AnnaBridge 171:3a7713b1edbc 293 __IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
AnnaBridge 171:3a7713b1edbc 294 __IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
AnnaBridge 171:3a7713b1edbc 295 __IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
AnnaBridge 171:3a7713b1edbc 296 __I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
AnnaBridge 171:3a7713b1edbc 297 __O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
AnnaBridge 171:3a7713b1edbc 298 } Wdt;
AnnaBridge 171:3a7713b1edbc 299 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 300
AnnaBridge 171:3a7713b1edbc 301 /*@}*/
AnnaBridge 171:3a7713b1edbc 302
AnnaBridge 171:3a7713b1edbc 303 #endif /* _SAMR21_WDT_COMPONENT_ */