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mbed 2

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TARGET_SAMR21G18A/TOOLCHAIN_ARM_STD/comp_mtb.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /**
AnnaBridge 171:3a7713b1edbc 2 * \file
AnnaBridge 171:3a7713b1edbc 3 *
AnnaBridge 171:3a7713b1edbc 4 * \brief Component description for MTB
AnnaBridge 171:3a7713b1edbc 5 *
AnnaBridge 171:3a7713b1edbc 6 * Copyright (c) 2015 Atmel Corporation. All rights reserved.
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * \asf_license_start
AnnaBridge 171:3a7713b1edbc 9 *
AnnaBridge 171:3a7713b1edbc 10 * \page License
AnnaBridge 171:3a7713b1edbc 11 *
AnnaBridge 171:3a7713b1edbc 12 * Redistribution and use in source and binary forms, with or without
AnnaBridge 171:3a7713b1edbc 13 * modification, are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 171:3a7713b1edbc 16 * this list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 17 *
AnnaBridge 171:3a7713b1edbc 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 171:3a7713b1edbc 19 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 171:3a7713b1edbc 20 * and/or other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 21 *
AnnaBridge 171:3a7713b1edbc 22 * 3. The name of Atmel may not be used to endorse or promote products derived
AnnaBridge 171:3a7713b1edbc 23 * from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 24 *
AnnaBridge 171:3a7713b1edbc 25 * 4. This software may only be redistributed and used in connection with an
AnnaBridge 171:3a7713b1edbc 26 * Atmel microcontroller product.
AnnaBridge 171:3a7713b1edbc 27 *
AnnaBridge 171:3a7713b1edbc 28 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
AnnaBridge 171:3a7713b1edbc 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
AnnaBridge 171:3a7713b1edbc 30 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
AnnaBridge 171:3a7713b1edbc 31 * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 32 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 171:3a7713b1edbc 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
AnnaBridge 171:3a7713b1edbc 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
AnnaBridge 171:3a7713b1edbc 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
AnnaBridge 171:3a7713b1edbc 36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
AnnaBridge 171:3a7713b1edbc 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
AnnaBridge 171:3a7713b1edbc 38 * POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 39 *
AnnaBridge 171:3a7713b1edbc 40 * \asf_license_stop
AnnaBridge 171:3a7713b1edbc 41 *
AnnaBridge 171:3a7713b1edbc 42 */
AnnaBridge 171:3a7713b1edbc 43
AnnaBridge 171:3a7713b1edbc 44 #ifndef _SAMR21_MTB_COMPONENT_
AnnaBridge 171:3a7713b1edbc 45 #define _SAMR21_MTB_COMPONENT_
AnnaBridge 171:3a7713b1edbc 46
AnnaBridge 171:3a7713b1edbc 47 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 48 /** SOFTWARE API DEFINITION FOR MTB */
AnnaBridge 171:3a7713b1edbc 49 /* ========================================================================== */
AnnaBridge 171:3a7713b1edbc 50 /** \addtogroup SAMR21_MTB Cortex-M0+ Micro-Trace Buffer */
AnnaBridge 171:3a7713b1edbc 51 /*@{*/
AnnaBridge 171:3a7713b1edbc 52
AnnaBridge 171:3a7713b1edbc 53 #define MTB_U2002
AnnaBridge 171:3a7713b1edbc 54 #define REV_MTB 0x100
AnnaBridge 171:3a7713b1edbc 55
AnnaBridge 171:3a7713b1edbc 56 /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
AnnaBridge 171:3a7713b1edbc 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 58 typedef union {
AnnaBridge 171:3a7713b1edbc 59 struct {
AnnaBridge 171:3a7713b1edbc 60 uint32_t :2; /*!< bit: 0.. 1 Reserved */
AnnaBridge 171:3a7713b1edbc 61 uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
AnnaBridge 171:3a7713b1edbc 62 uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
AnnaBridge 171:3a7713b1edbc 63 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 64 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 65 } MTB_POSITION_Type;
AnnaBridge 171:3a7713b1edbc 66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 67
AnnaBridge 171:3a7713b1edbc 68 #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */
AnnaBridge 171:3a7713b1edbc 69
AnnaBridge 171:3a7713b1edbc 70 #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */
AnnaBridge 171:3a7713b1edbc 71 #define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos)
AnnaBridge 171:3a7713b1edbc 72 #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */
AnnaBridge 171:3a7713b1edbc 73 #define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos)
AnnaBridge 171:3a7713b1edbc 74 #define MTB_POSITION_POINTER(value) (MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))
AnnaBridge 171:3a7713b1edbc 75 #define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */
AnnaBridge 171:3a7713b1edbc 76
AnnaBridge 171:3a7713b1edbc 77 /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
AnnaBridge 171:3a7713b1edbc 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 79 typedef union {
AnnaBridge 171:3a7713b1edbc 80 struct {
AnnaBridge 171:3a7713b1edbc 81 uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
AnnaBridge 171:3a7713b1edbc 82 uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
AnnaBridge 171:3a7713b1edbc 83 uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
AnnaBridge 171:3a7713b1edbc 84 uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
AnnaBridge 171:3a7713b1edbc 85 uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
AnnaBridge 171:3a7713b1edbc 86 uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
AnnaBridge 171:3a7713b1edbc 87 uint32_t :21; /*!< bit: 10..30 Reserved */
AnnaBridge 171:3a7713b1edbc 88 uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
AnnaBridge 171:3a7713b1edbc 89 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 90 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 91 } MTB_MASTER_Type;
AnnaBridge 171:3a7713b1edbc 92 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 93
AnnaBridge 171:3a7713b1edbc 94 #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */
AnnaBridge 171:3a7713b1edbc 95 #define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */
AnnaBridge 171:3a7713b1edbc 98 #define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos)
AnnaBridge 171:3a7713b1edbc 99 #define MTB_MASTER_MASK(value) (MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))
AnnaBridge 171:3a7713b1edbc 100 #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */
AnnaBridge 171:3a7713b1edbc 101 #define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos)
AnnaBridge 171:3a7713b1edbc 102 #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */
AnnaBridge 171:3a7713b1edbc 103 #define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos)
AnnaBridge 171:3a7713b1edbc 104 #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */
AnnaBridge 171:3a7713b1edbc 105 #define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos)
AnnaBridge 171:3a7713b1edbc 106 #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */
AnnaBridge 171:3a7713b1edbc 107 #define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos)
AnnaBridge 171:3a7713b1edbc 108 #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */
AnnaBridge 171:3a7713b1edbc 109 #define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos)
AnnaBridge 171:3a7713b1edbc 110 #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */
AnnaBridge 171:3a7713b1edbc 111 #define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos)
AnnaBridge 171:3a7713b1edbc 112 #define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */
AnnaBridge 171:3a7713b1edbc 113
AnnaBridge 171:3a7713b1edbc 114 /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
AnnaBridge 171:3a7713b1edbc 115 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 116 typedef union {
AnnaBridge 171:3a7713b1edbc 117 struct {
AnnaBridge 171:3a7713b1edbc 118 uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
AnnaBridge 171:3a7713b1edbc 119 uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
AnnaBridge 171:3a7713b1edbc 120 uint32_t :1; /*!< bit: 2 Reserved */
AnnaBridge 171:3a7713b1edbc 121 uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
AnnaBridge 171:3a7713b1edbc 122 } bit; /*!< Structure used for bit access */
AnnaBridge 171:3a7713b1edbc 123 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 124 } MTB_FLOW_Type;
AnnaBridge 171:3a7713b1edbc 125 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127 #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */
AnnaBridge 171:3a7713b1edbc 128 #define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */
AnnaBridge 171:3a7713b1edbc 129
AnnaBridge 171:3a7713b1edbc 130 #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */
AnnaBridge 171:3a7713b1edbc 131 #define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos)
AnnaBridge 171:3a7713b1edbc 132 #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */
AnnaBridge 171:3a7713b1edbc 133 #define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos)
AnnaBridge 171:3a7713b1edbc 134 #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */
AnnaBridge 171:3a7713b1edbc 135 #define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos)
AnnaBridge 171:3a7713b1edbc 136 #define MTB_FLOW_WATERMARK(value) (MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))
AnnaBridge 171:3a7713b1edbc 137 #define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */
AnnaBridge 171:3a7713b1edbc 138
AnnaBridge 171:3a7713b1edbc 139 /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
AnnaBridge 171:3a7713b1edbc 140 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 141 typedef union {
AnnaBridge 171:3a7713b1edbc 142 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 143 } MTB_BASE_Type;
AnnaBridge 171:3a7713b1edbc 144 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 145
AnnaBridge 171:3a7713b1edbc 146 #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */
AnnaBridge 171:3a7713b1edbc 147 #define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
AnnaBridge 171:3a7713b1edbc 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 151 typedef union {
AnnaBridge 171:3a7713b1edbc 152 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 153 } MTB_ITCTRL_Type;
AnnaBridge 171:3a7713b1edbc 154 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 155
AnnaBridge 171:3a7713b1edbc 156 #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */
AnnaBridge 171:3a7713b1edbc 157 #define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */
AnnaBridge 171:3a7713b1edbc 158
AnnaBridge 171:3a7713b1edbc 159 /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
AnnaBridge 171:3a7713b1edbc 160 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 161 typedef union {
AnnaBridge 171:3a7713b1edbc 162 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 163 } MTB_CLAIMSET_Type;
AnnaBridge 171:3a7713b1edbc 164 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */
AnnaBridge 171:3a7713b1edbc 167 #define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */
AnnaBridge 171:3a7713b1edbc 168
AnnaBridge 171:3a7713b1edbc 169 /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
AnnaBridge 171:3a7713b1edbc 170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 171 typedef union {
AnnaBridge 171:3a7713b1edbc 172 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 173 } MTB_CLAIMCLR_Type;
AnnaBridge 171:3a7713b1edbc 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 175
AnnaBridge 171:3a7713b1edbc 176 #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */
AnnaBridge 171:3a7713b1edbc 177 #define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */
AnnaBridge 171:3a7713b1edbc 178
AnnaBridge 171:3a7713b1edbc 179 /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
AnnaBridge 171:3a7713b1edbc 180 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 181 typedef union {
AnnaBridge 171:3a7713b1edbc 182 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 183 } MTB_LOCKACCESS_Type;
AnnaBridge 171:3a7713b1edbc 184 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 185
AnnaBridge 171:3a7713b1edbc 186 #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */
AnnaBridge 171:3a7713b1edbc 187 #define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */
AnnaBridge 171:3a7713b1edbc 188
AnnaBridge 171:3a7713b1edbc 189 /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
AnnaBridge 171:3a7713b1edbc 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 191 typedef union {
AnnaBridge 171:3a7713b1edbc 192 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 193 } MTB_LOCKSTATUS_Type;
AnnaBridge 171:3a7713b1edbc 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 195
AnnaBridge 171:3a7713b1edbc 196 #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */
AnnaBridge 171:3a7713b1edbc 197 #define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 198
AnnaBridge 171:3a7713b1edbc 199 /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
AnnaBridge 171:3a7713b1edbc 200 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 201 typedef union {
AnnaBridge 171:3a7713b1edbc 202 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 203 } MTB_AUTHSTATUS_Type;
AnnaBridge 171:3a7713b1edbc 204 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 205
AnnaBridge 171:3a7713b1edbc 206 #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */
AnnaBridge 171:3a7713b1edbc 207 #define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
AnnaBridge 171:3a7713b1edbc 210 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 211 typedef union {
AnnaBridge 171:3a7713b1edbc 212 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 213 } MTB_DEVARCH_Type;
AnnaBridge 171:3a7713b1edbc 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 215
AnnaBridge 171:3a7713b1edbc 216 #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */
AnnaBridge 171:3a7713b1edbc 217 #define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */
AnnaBridge 171:3a7713b1edbc 218
AnnaBridge 171:3a7713b1edbc 219 /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
AnnaBridge 171:3a7713b1edbc 220 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 221 typedef union {
AnnaBridge 171:3a7713b1edbc 222 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 223 } MTB_DEVID_Type;
AnnaBridge 171:3a7713b1edbc 224 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 225
AnnaBridge 171:3a7713b1edbc 226 #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */
AnnaBridge 171:3a7713b1edbc 227 #define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */
AnnaBridge 171:3a7713b1edbc 228
AnnaBridge 171:3a7713b1edbc 229 /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
AnnaBridge 171:3a7713b1edbc 230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 231 typedef union {
AnnaBridge 171:3a7713b1edbc 232 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 233 } MTB_DEVTYPE_Type;
AnnaBridge 171:3a7713b1edbc 234 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 235
AnnaBridge 171:3a7713b1edbc 236 #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */
AnnaBridge 171:3a7713b1edbc 237 #define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */
AnnaBridge 171:3a7713b1edbc 238
AnnaBridge 171:3a7713b1edbc 239 /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 240 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 241 typedef union {
AnnaBridge 171:3a7713b1edbc 242 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 243 } MTB_PID4_Type;
AnnaBridge 171:3a7713b1edbc 244 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 245
AnnaBridge 171:3a7713b1edbc 246 #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 247 #define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */
AnnaBridge 171:3a7713b1edbc 248
AnnaBridge 171:3a7713b1edbc 249 /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 250 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 251 typedef union {
AnnaBridge 171:3a7713b1edbc 252 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 253 } MTB_PID5_Type;
AnnaBridge 171:3a7713b1edbc 254 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256 #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 257 #define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */
AnnaBridge 171:3a7713b1edbc 258
AnnaBridge 171:3a7713b1edbc 259 /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 260 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 261 typedef union {
AnnaBridge 171:3a7713b1edbc 262 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 263 } MTB_PID6_Type;
AnnaBridge 171:3a7713b1edbc 264 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 265
AnnaBridge 171:3a7713b1edbc 266 #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 267 #define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */
AnnaBridge 171:3a7713b1edbc 268
AnnaBridge 171:3a7713b1edbc 269 /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 270 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 271 typedef union {
AnnaBridge 171:3a7713b1edbc 272 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 273 } MTB_PID7_Type;
AnnaBridge 171:3a7713b1edbc 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 275
AnnaBridge 171:3a7713b1edbc 276 #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 277 #define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */
AnnaBridge 171:3a7713b1edbc 278
AnnaBridge 171:3a7713b1edbc 279 /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 280 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 281 typedef union {
AnnaBridge 171:3a7713b1edbc 282 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 283 } MTB_PID0_Type;
AnnaBridge 171:3a7713b1edbc 284 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 285
AnnaBridge 171:3a7713b1edbc 286 #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 287 #define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */
AnnaBridge 171:3a7713b1edbc 288
AnnaBridge 171:3a7713b1edbc 289 /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 290 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 291 typedef union {
AnnaBridge 171:3a7713b1edbc 292 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 293 } MTB_PID1_Type;
AnnaBridge 171:3a7713b1edbc 294 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 295
AnnaBridge 171:3a7713b1edbc 296 #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 297 #define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */
AnnaBridge 171:3a7713b1edbc 298
AnnaBridge 171:3a7713b1edbc 299 /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 300 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 301 typedef union {
AnnaBridge 171:3a7713b1edbc 302 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 303 } MTB_PID2_Type;
AnnaBridge 171:3a7713b1edbc 304 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 305
AnnaBridge 171:3a7713b1edbc 306 #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 307 #define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */
AnnaBridge 171:3a7713b1edbc 308
AnnaBridge 171:3a7713b1edbc 309 /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 310 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 311 typedef union {
AnnaBridge 171:3a7713b1edbc 312 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 313 } MTB_PID3_Type;
AnnaBridge 171:3a7713b1edbc 314 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 315
AnnaBridge 171:3a7713b1edbc 316 #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 317 #define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */
AnnaBridge 171:3a7713b1edbc 318
AnnaBridge 171:3a7713b1edbc 319 /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 320 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 321 typedef union {
AnnaBridge 171:3a7713b1edbc 322 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 323 } MTB_CID0_Type;
AnnaBridge 171:3a7713b1edbc 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 325
AnnaBridge 171:3a7713b1edbc 326 #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 327 #define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */
AnnaBridge 171:3a7713b1edbc 328
AnnaBridge 171:3a7713b1edbc 329 /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 330 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 331 typedef union {
AnnaBridge 171:3a7713b1edbc 332 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 333 } MTB_CID1_Type;
AnnaBridge 171:3a7713b1edbc 334 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 335
AnnaBridge 171:3a7713b1edbc 336 #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 337 #define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */
AnnaBridge 171:3a7713b1edbc 338
AnnaBridge 171:3a7713b1edbc 339 /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 340 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 341 typedef union {
AnnaBridge 171:3a7713b1edbc 342 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 343 } MTB_CID2_Type;
AnnaBridge 171:3a7713b1edbc 344 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 345
AnnaBridge 171:3a7713b1edbc 346 #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 347 #define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */
AnnaBridge 171:3a7713b1edbc 348
AnnaBridge 171:3a7713b1edbc 349 /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
AnnaBridge 171:3a7713b1edbc 350 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 351 typedef union {
AnnaBridge 171:3a7713b1edbc 352 uint32_t reg; /*!< Type used for register access */
AnnaBridge 171:3a7713b1edbc 353 } MTB_CID3_Type;
AnnaBridge 171:3a7713b1edbc 354 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 355
AnnaBridge 171:3a7713b1edbc 356 #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */
AnnaBridge 171:3a7713b1edbc 357 #define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */
AnnaBridge 171:3a7713b1edbc 358
AnnaBridge 171:3a7713b1edbc 359 /** \brief MTB hardware registers */
AnnaBridge 171:3a7713b1edbc 360 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
AnnaBridge 171:3a7713b1edbc 361 typedef struct {
AnnaBridge 171:3a7713b1edbc 362 __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
AnnaBridge 171:3a7713b1edbc 363 __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
AnnaBridge 171:3a7713b1edbc 364 __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
AnnaBridge 171:3a7713b1edbc 365 __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
AnnaBridge 171:3a7713b1edbc 366 RoReg8 Reserved1[0xEF0];
AnnaBridge 171:3a7713b1edbc 367 __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
AnnaBridge 171:3a7713b1edbc 368 RoReg8 Reserved2[0x9C];
AnnaBridge 171:3a7713b1edbc 369 __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
AnnaBridge 171:3a7713b1edbc 370 __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
AnnaBridge 171:3a7713b1edbc 371 RoReg8 Reserved3[0x8];
AnnaBridge 171:3a7713b1edbc 372 __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
AnnaBridge 171:3a7713b1edbc 373 __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
AnnaBridge 171:3a7713b1edbc 374 __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
AnnaBridge 171:3a7713b1edbc 375 __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
AnnaBridge 171:3a7713b1edbc 376 RoReg8 Reserved4[0x8];
AnnaBridge 171:3a7713b1edbc 377 __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
AnnaBridge 171:3a7713b1edbc 378 __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
AnnaBridge 171:3a7713b1edbc 379 __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 380 __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 381 __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 382 __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 383 __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 384 __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 385 __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 386 __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 387 __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 388 __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 389 __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 390 __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
AnnaBridge 171:3a7713b1edbc 391 } Mtb;
AnnaBridge 171:3a7713b1edbc 392 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
AnnaBridge 171:3a7713b1edbc 393
AnnaBridge 171:3a7713b1edbc 394 /*@}*/
AnnaBridge 171:3a7713b1edbc 395
AnnaBridge 171:3a7713b1edbc 396 #endif /* _SAMR21_MTB_COMPONENT_ */