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mbed 2
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TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/samd21j17a.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Header file for SAMD21J17A |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21J17A_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21J17A_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /** |
AnnaBridge | 171:3a7713b1edbc | 51 | * \ingroup SAMD21_definitions |
AnnaBridge | 171:3a7713b1edbc | 52 | * \addtogroup SAMD21J17A_definitions SAMD21J17A definitions |
AnnaBridge | 171:3a7713b1edbc | 53 | * This file defines all structures and symbols for SAMD21J17A: |
AnnaBridge | 171:3a7713b1edbc | 54 | * - registers and bitfields |
AnnaBridge | 171:3a7713b1edbc | 55 | * - peripheral base address |
AnnaBridge | 171:3a7713b1edbc | 56 | * - peripheral ID |
AnnaBridge | 171:3a7713b1edbc | 57 | * - PIO definitions |
AnnaBridge | 171:3a7713b1edbc | 58 | */ |
AnnaBridge | 171:3a7713b1edbc | 59 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 60 | |
AnnaBridge | 171:3a7713b1edbc | 61 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 62 | extern "C" { |
AnnaBridge | 171:3a7713b1edbc | 63 | #endif |
AnnaBridge | 171:3a7713b1edbc | 64 | |
AnnaBridge | 171:3a7713b1edbc | 65 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 66 | #include <stdint.h> |
AnnaBridge | 171:3a7713b1edbc | 67 | #ifndef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 68 | typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 69 | typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 70 | typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #else |
AnnaBridge | 171:3a7713b1edbc | 72 | typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 73 | typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 74 | typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #endif |
AnnaBridge | 171:3a7713b1edbc | 76 | typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 77 | typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 78 | typedef volatile uint32_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 79 | typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 80 | typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 81 | typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define CAST(type, value) ((type *)(value)) |
AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_ACCESS(type, address) (*(type*)(address)) /**< C code: Register value */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #else |
AnnaBridge | 171:3a7713b1edbc | 85 | #define CAST(type, value) (value) |
AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_ACCESS(type, address) (address) /**< Assembly code: Register address */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #endif |
AnnaBridge | 171:3a7713b1edbc | 88 | |
AnnaBridge | 171:3a7713b1edbc | 89 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 90 | /** CMSIS DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 91 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 92 | /** \defgroup SAMD21J17A_cmsis CMSIS Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 93 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | /** Interrupt Number Definition */ |
AnnaBridge | 171:3a7713b1edbc | 96 | typedef enum IRQn { |
AnnaBridge | 171:3a7713b1edbc | 97 | /****** Cortex-M0+ Processor Exceptions Numbers ******************************/ |
AnnaBridge | 171:3a7713b1edbc | 98 | NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 99 | HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 100 | SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 101 | PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 102 | SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 103 | /****** SAMD21J17A-specific Interrupt Numbers ***********************/ |
AnnaBridge | 171:3a7713b1edbc | 104 | PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */ |
AnnaBridge | 171:3a7713b1edbc | 105 | SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */ |
AnnaBridge | 171:3a7713b1edbc | 106 | WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */ |
AnnaBridge | 171:3a7713b1edbc | 107 | RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */ |
AnnaBridge | 171:3a7713b1edbc | 108 | EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */ |
AnnaBridge | 171:3a7713b1edbc | 109 | NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */ |
AnnaBridge | 171:3a7713b1edbc | 110 | DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */ |
AnnaBridge | 171:3a7713b1edbc | 111 | USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */ |
AnnaBridge | 171:3a7713b1edbc | 112 | EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */ |
AnnaBridge | 171:3a7713b1edbc | 113 | SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */ |
AnnaBridge | 171:3a7713b1edbc | 114 | SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */ |
AnnaBridge | 171:3a7713b1edbc | 115 | SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */ |
AnnaBridge | 171:3a7713b1edbc | 116 | SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */ |
AnnaBridge | 171:3a7713b1edbc | 117 | SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */ |
AnnaBridge | 171:3a7713b1edbc | 118 | SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */ |
AnnaBridge | 171:3a7713b1edbc | 119 | TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */ |
AnnaBridge | 171:3a7713b1edbc | 120 | TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */ |
AnnaBridge | 171:3a7713b1edbc | 121 | TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */ |
AnnaBridge | 171:3a7713b1edbc | 122 | TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */ |
AnnaBridge | 171:3a7713b1edbc | 123 | TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */ |
AnnaBridge | 171:3a7713b1edbc | 124 | TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */ |
AnnaBridge | 171:3a7713b1edbc | 125 | TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */ |
AnnaBridge | 171:3a7713b1edbc | 126 | TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */ |
AnnaBridge | 171:3a7713b1edbc | 127 | ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */ |
AnnaBridge | 171:3a7713b1edbc | 128 | AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */ |
AnnaBridge | 171:3a7713b1edbc | 129 | DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */ |
AnnaBridge | 171:3a7713b1edbc | 130 | PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */ |
AnnaBridge | 171:3a7713b1edbc | 131 | I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */ |
AnnaBridge | 171:3a7713b1edbc | 132 | |
AnnaBridge | 171:3a7713b1edbc | 133 | PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */ |
AnnaBridge | 171:3a7713b1edbc | 134 | } IRQn_Type; |
AnnaBridge | 171:3a7713b1edbc | 135 | |
AnnaBridge | 171:3a7713b1edbc | 136 | typedef struct _DeviceVectors { |
AnnaBridge | 171:3a7713b1edbc | 137 | /* Stack pointer */ |
AnnaBridge | 171:3a7713b1edbc | 138 | void* pvStack; |
AnnaBridge | 171:3a7713b1edbc | 139 | |
AnnaBridge | 171:3a7713b1edbc | 140 | /* Cortex-M handlers */ |
AnnaBridge | 171:3a7713b1edbc | 141 | void* pfnReset_Handler; |
AnnaBridge | 171:3a7713b1edbc | 142 | void* pfnNMI_Handler; |
AnnaBridge | 171:3a7713b1edbc | 143 | void* pfnHardFault_Handler; |
AnnaBridge | 171:3a7713b1edbc | 144 | void* pfnReservedM12; |
AnnaBridge | 171:3a7713b1edbc | 145 | void* pfnReservedM11; |
AnnaBridge | 171:3a7713b1edbc | 146 | void* pfnReservedM10; |
AnnaBridge | 171:3a7713b1edbc | 147 | void* pfnReservedM9; |
AnnaBridge | 171:3a7713b1edbc | 148 | void* pfnReservedM8; |
AnnaBridge | 171:3a7713b1edbc | 149 | void* pfnReservedM7; |
AnnaBridge | 171:3a7713b1edbc | 150 | void* pfnReservedM6; |
AnnaBridge | 171:3a7713b1edbc | 151 | void* pfnSVC_Handler; |
AnnaBridge | 171:3a7713b1edbc | 152 | void* pfnReservedM4; |
AnnaBridge | 171:3a7713b1edbc | 153 | void* pfnReservedM3; |
AnnaBridge | 171:3a7713b1edbc | 154 | void* pfnPendSV_Handler; |
AnnaBridge | 171:3a7713b1edbc | 155 | void* pfnSysTick_Handler; |
AnnaBridge | 171:3a7713b1edbc | 156 | |
AnnaBridge | 171:3a7713b1edbc | 157 | /* Peripheral handlers */ |
AnnaBridge | 171:3a7713b1edbc | 158 | void* pfnPM_Handler; /* 0 Power Manager */ |
AnnaBridge | 171:3a7713b1edbc | 159 | void* pfnSYSCTRL_Handler; /* 1 System Control */ |
AnnaBridge | 171:3a7713b1edbc | 160 | void* pfnWDT_Handler; /* 2 Watchdog Timer */ |
AnnaBridge | 171:3a7713b1edbc | 161 | void* pfnRTC_Handler; /* 3 Real-Time Counter */ |
AnnaBridge | 171:3a7713b1edbc | 162 | void* pfnEIC_Handler; /* 4 External Interrupt Controller */ |
AnnaBridge | 171:3a7713b1edbc | 163 | void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */ |
AnnaBridge | 171:3a7713b1edbc | 164 | void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */ |
AnnaBridge | 171:3a7713b1edbc | 165 | void* pfnUSB_Handler; /* 7 Universal Serial Bus */ |
AnnaBridge | 171:3a7713b1edbc | 166 | void* pfnEVSYS_Handler; /* 8 Event System Interface */ |
AnnaBridge | 171:3a7713b1edbc | 167 | void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */ |
AnnaBridge | 171:3a7713b1edbc | 168 | void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */ |
AnnaBridge | 171:3a7713b1edbc | 169 | void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */ |
AnnaBridge | 171:3a7713b1edbc | 170 | void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */ |
AnnaBridge | 171:3a7713b1edbc | 171 | void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */ |
AnnaBridge | 171:3a7713b1edbc | 172 | void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */ |
AnnaBridge | 171:3a7713b1edbc | 173 | void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */ |
AnnaBridge | 171:3a7713b1edbc | 174 | void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */ |
AnnaBridge | 171:3a7713b1edbc | 175 | void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */ |
AnnaBridge | 171:3a7713b1edbc | 176 | void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */ |
AnnaBridge | 171:3a7713b1edbc | 177 | void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */ |
AnnaBridge | 171:3a7713b1edbc | 178 | void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */ |
AnnaBridge | 171:3a7713b1edbc | 179 | void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */ |
AnnaBridge | 171:3a7713b1edbc | 180 | void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */ |
AnnaBridge | 171:3a7713b1edbc | 181 | void* pfnADC_Handler; /* 23 Analog Digital Converter */ |
AnnaBridge | 171:3a7713b1edbc | 182 | void* pfnAC_Handler; /* 24 Analog Comparators */ |
AnnaBridge | 171:3a7713b1edbc | 183 | void* pfnDAC_Handler; /* 25 Digital Analog Converter */ |
AnnaBridge | 171:3a7713b1edbc | 184 | void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */ |
AnnaBridge | 171:3a7713b1edbc | 185 | void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */ |
AnnaBridge | 171:3a7713b1edbc | 186 | } DeviceVectors; |
AnnaBridge | 171:3a7713b1edbc | 187 | |
AnnaBridge | 171:3a7713b1edbc | 188 | /* Cortex-M0+ processor handlers */ |
AnnaBridge | 171:3a7713b1edbc | 189 | void Reset_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 190 | void NMI_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 191 | void HardFault_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 192 | void SVC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 193 | void PendSV_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 194 | void SysTick_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 195 | |
AnnaBridge | 171:3a7713b1edbc | 196 | /* Peripherals handlers */ |
AnnaBridge | 171:3a7713b1edbc | 197 | void PM_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 198 | void SYSCTRL_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 199 | void WDT_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 200 | void RTC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 201 | void EIC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 202 | void NVMCTRL_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 203 | void DMAC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 204 | void USB_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 205 | void EVSYS_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 206 | void SERCOM0_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 207 | void SERCOM1_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 208 | void SERCOM2_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 209 | void SERCOM3_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 210 | void SERCOM4_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 211 | void SERCOM5_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 212 | void TCC0_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 213 | void TCC1_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 214 | void TCC2_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 215 | void TC3_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 216 | void TC4_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 217 | void TC5_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 218 | void TC6_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 219 | void TC7_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 220 | void ADC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 221 | void AC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 222 | void DAC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 223 | void PTC_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 224 | void I2S_Handler ( void ); |
AnnaBridge | 171:3a7713b1edbc | 225 | |
AnnaBridge | 171:3a7713b1edbc | 226 | /* |
AnnaBridge | 171:3a7713b1edbc | 227 | * \brief Configuration of the Cortex-M0+ Processor and Core Peripherals |
AnnaBridge | 171:3a7713b1edbc | 228 | */ |
AnnaBridge | 171:3a7713b1edbc | 229 | |
AnnaBridge | 171:3a7713b1edbc | 230 | #define LITTLE_ENDIAN 1 |
AnnaBridge | 171:3a7713b1edbc | 231 | #define __CM0PLUS_REV 1 /*!< Core revision r0p1 */ |
AnnaBridge | 171:3a7713b1edbc | 232 | #define __MPU_PRESENT 0 /*!< MPU present or not */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */ |
AnnaBridge | 171:3a7713b1edbc | 234 | #define __VTOR_PRESENT 1 /*!< VTOR present or not */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ |
AnnaBridge | 171:3a7713b1edbc | 236 | |
AnnaBridge | 171:3a7713b1edbc | 237 | /** |
AnnaBridge | 171:3a7713b1edbc | 238 | * \brief CMSIS includes |
AnnaBridge | 171:3a7713b1edbc | 239 | */ |
AnnaBridge | 171:3a7713b1edbc | 240 | |
AnnaBridge | 171:3a7713b1edbc | 241 | #include <core_cm0plus.h> |
AnnaBridge | 171:3a7713b1edbc | 242 | #if !defined DONT_USE_CMSIS_INIT |
AnnaBridge | 171:3a7713b1edbc | 243 | #include "system_samd21.h" |
AnnaBridge | 171:3a7713b1edbc | 244 | #endif /* DONT_USE_CMSIS_INIT */ |
AnnaBridge | 171:3a7713b1edbc | 245 | |
AnnaBridge | 171:3a7713b1edbc | 246 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 247 | |
AnnaBridge | 171:3a7713b1edbc | 248 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 249 | /** SOFTWARE PERIPHERAL API DEFINITION FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 250 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 251 | /** \defgroup SAMD21J17A_api Peripheral Software API */ |
AnnaBridge | 171:3a7713b1edbc | 252 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 253 | |
AnnaBridge | 171:3a7713b1edbc | 254 | #include "comp_ac.h" |
AnnaBridge | 171:3a7713b1edbc | 255 | #include "comp_adc.h" |
AnnaBridge | 171:3a7713b1edbc | 256 | #include "comp_dac.h" |
AnnaBridge | 171:3a7713b1edbc | 257 | #include "comp_dmac.h" |
AnnaBridge | 171:3a7713b1edbc | 258 | #include "comp_dsu.h" |
AnnaBridge | 171:3a7713b1edbc | 259 | #include "comp_eic.h" |
AnnaBridge | 171:3a7713b1edbc | 260 | #include "comp_evsys.h" |
AnnaBridge | 171:3a7713b1edbc | 261 | #include "comp_gclk.h" |
AnnaBridge | 171:3a7713b1edbc | 262 | #include "comp_hmatrixb.h" |
AnnaBridge | 171:3a7713b1edbc | 263 | #include "comp_i2s.h" |
AnnaBridge | 171:3a7713b1edbc | 264 | #include "comp_mtb.h" |
AnnaBridge | 171:3a7713b1edbc | 265 | #include "comp_nvmctrl.h" |
AnnaBridge | 171:3a7713b1edbc | 266 | #include "comp_pac.h" |
AnnaBridge | 171:3a7713b1edbc | 267 | #include "comp_pm.h" |
AnnaBridge | 171:3a7713b1edbc | 268 | #include "comp_port.h" |
AnnaBridge | 171:3a7713b1edbc | 269 | #include "comp_rtc.h" |
AnnaBridge | 171:3a7713b1edbc | 270 | #include "comp_sercom.h" |
AnnaBridge | 171:3a7713b1edbc | 271 | #include "comp_sysctrl.h" |
AnnaBridge | 171:3a7713b1edbc | 272 | #include "comp_tc.h" |
AnnaBridge | 171:3a7713b1edbc | 273 | #include "comp_tcc.h" |
AnnaBridge | 171:3a7713b1edbc | 274 | #include "comp_usb.h" |
AnnaBridge | 171:3a7713b1edbc | 275 | #include "comp_wdt.h" |
AnnaBridge | 171:3a7713b1edbc | 276 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 277 | |
AnnaBridge | 171:3a7713b1edbc | 278 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 279 | /** REGISTERS ACCESS DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 280 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 281 | /** \defgroup SAMD21J17A_reg Registers Access Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 282 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 283 | |
AnnaBridge | 171:3a7713b1edbc | 284 | #include "ins_ac.h" |
AnnaBridge | 171:3a7713b1edbc | 285 | #include "ins_adc.h" |
AnnaBridge | 171:3a7713b1edbc | 286 | #include "ins_dac.h" |
AnnaBridge | 171:3a7713b1edbc | 287 | #include "ins_dmac.h" |
AnnaBridge | 171:3a7713b1edbc | 288 | #include "ins_dsu.h" |
AnnaBridge | 171:3a7713b1edbc | 289 | #include "ins_eic.h" |
AnnaBridge | 171:3a7713b1edbc | 290 | #include "ins_evsys.h" |
AnnaBridge | 171:3a7713b1edbc | 291 | #include "ins_gclk.h" |
AnnaBridge | 171:3a7713b1edbc | 292 | #include "ins_sbmatrix.h" |
AnnaBridge | 171:3a7713b1edbc | 293 | #include "ins_i2s.h" |
AnnaBridge | 171:3a7713b1edbc | 294 | #include "ins_mtb.h" |
AnnaBridge | 171:3a7713b1edbc | 295 | #include "ins_nvmctrl.h" |
AnnaBridge | 171:3a7713b1edbc | 296 | #include "ins_pac0.h" |
AnnaBridge | 171:3a7713b1edbc | 297 | #include "ins_pac1.h" |
AnnaBridge | 171:3a7713b1edbc | 298 | #include "ins_pac2.h" |
AnnaBridge | 171:3a7713b1edbc | 299 | #include "ins_pm.h" |
AnnaBridge | 171:3a7713b1edbc | 300 | #include "ins_port.h" |
AnnaBridge | 171:3a7713b1edbc | 301 | #include "ins_rtc.h" |
AnnaBridge | 171:3a7713b1edbc | 302 | #include "ins_sercom0.h" |
AnnaBridge | 171:3a7713b1edbc | 303 | #include "ins_sercom1.h" |
AnnaBridge | 171:3a7713b1edbc | 304 | #include "ins_sercom2.h" |
AnnaBridge | 171:3a7713b1edbc | 305 | #include "ins_sercom3.h" |
AnnaBridge | 171:3a7713b1edbc | 306 | #include "ins_sercom4.h" |
AnnaBridge | 171:3a7713b1edbc | 307 | #include "ins_sercom5.h" |
AnnaBridge | 171:3a7713b1edbc | 308 | #include "ins_sysctrl.h" |
AnnaBridge | 171:3a7713b1edbc | 309 | #include "ins_tc3.h" |
AnnaBridge | 171:3a7713b1edbc | 310 | #include "ins_tc4.h" |
AnnaBridge | 171:3a7713b1edbc | 311 | #include "ins_tc5.h" |
AnnaBridge | 171:3a7713b1edbc | 312 | #include "ins_tc6.h" |
AnnaBridge | 171:3a7713b1edbc | 313 | #include "ins_tc7.h" |
AnnaBridge | 171:3a7713b1edbc | 314 | #include "ins_tcc0.h" |
AnnaBridge | 171:3a7713b1edbc | 315 | #include "ins_tcc1.h" |
AnnaBridge | 171:3a7713b1edbc | 316 | #include "ins_tcc2.h" |
AnnaBridge | 171:3a7713b1edbc | 317 | #include "ins_usb.h" |
AnnaBridge | 171:3a7713b1edbc | 318 | #include "ins_wdt.h" |
AnnaBridge | 171:3a7713b1edbc | 319 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 320 | |
AnnaBridge | 171:3a7713b1edbc | 321 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 322 | /** PERIPHERAL ID DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 323 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 324 | /** \defgroup SAMD21J17A_id Peripheral Ids Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 325 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 326 | |
AnnaBridge | 171:3a7713b1edbc | 327 | // Peripheral instances on HPB0 bridge |
AnnaBridge | 171:3a7713b1edbc | 328 | #define ID_PAC0 0 /**< \brief Peripheral Access Controller 0 (PAC0) */ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define ID_PM 1 /**< \brief Power Manager (PM) */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define ID_SYSCTRL 2 /**< \brief System Control (SYSCTRL) */ |
AnnaBridge | 171:3a7713b1edbc | 331 | #define ID_GCLK 3 /**< \brief Generic Clock Generator (GCLK) */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define ID_WDT 4 /**< \brief Watchdog Timer (WDT) */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define ID_RTC 5 /**< \brief Real-Time Counter (RTC) */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define ID_EIC 6 /**< \brief External Interrupt Controller (EIC) */ |
AnnaBridge | 171:3a7713b1edbc | 335 | |
AnnaBridge | 171:3a7713b1edbc | 336 | // Peripheral instances on HPB1 bridge |
AnnaBridge | 171:3a7713b1edbc | 337 | #define ID_PAC1 32 /**< \brief Peripheral Access Controller 1 (PAC1) */ |
AnnaBridge | 171:3a7713b1edbc | 338 | #define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ |
AnnaBridge | 171:3a7713b1edbc | 339 | #define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define ID_PORT 35 /**< \brief Port Module (PORT) */ |
AnnaBridge | 171:3a7713b1edbc | 341 | #define ID_DMAC 36 /**< \brief Direct Memory Access Controller (DMAC) */ |
AnnaBridge | 171:3a7713b1edbc | 342 | #define ID_USB 37 /**< \brief Universal Serial Bus (USB) */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #define ID_MTB 38 /**< \brief Cortex-M0+ Micro-Trace Buffer (MTB) */ |
AnnaBridge | 171:3a7713b1edbc | 344 | #define ID_SBMATRIX 39 /**< \brief HSB Matrix (SBMATRIX) */ |
AnnaBridge | 171:3a7713b1edbc | 345 | |
AnnaBridge | 171:3a7713b1edbc | 346 | // Peripheral instances on HPB2 bridge |
AnnaBridge | 171:3a7713b1edbc | 347 | #define ID_PAC2 64 /**< \brief Peripheral Access Controller 2 (PAC2) */ |
AnnaBridge | 171:3a7713b1edbc | 348 | #define ID_EVSYS 65 /**< \brief Event System Interface (EVSYS) */ |
AnnaBridge | 171:3a7713b1edbc | 349 | #define ID_SERCOM0 66 /**< \brief Serial Communication Interface 0 (SERCOM0) */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define ID_SERCOM1 67 /**< \brief Serial Communication Interface 1 (SERCOM1) */ |
AnnaBridge | 171:3a7713b1edbc | 351 | #define ID_SERCOM2 68 /**< \brief Serial Communication Interface 2 (SERCOM2) */ |
AnnaBridge | 171:3a7713b1edbc | 352 | #define ID_SERCOM3 69 /**< \brief Serial Communication Interface 3 (SERCOM3) */ |
AnnaBridge | 171:3a7713b1edbc | 353 | #define ID_SERCOM4 70 /**< \brief Serial Communication Interface 4 (SERCOM4) */ |
AnnaBridge | 171:3a7713b1edbc | 354 | #define ID_SERCOM5 71 /**< \brief Serial Communication Interface 5 (SERCOM5) */ |
AnnaBridge | 171:3a7713b1edbc | 355 | #define ID_TCC0 72 /**< \brief Timer Counter Control 0 (TCC0) */ |
AnnaBridge | 171:3a7713b1edbc | 356 | #define ID_TCC1 73 /**< \brief Timer Counter Control 1 (TCC1) */ |
AnnaBridge | 171:3a7713b1edbc | 357 | #define ID_TCC2 74 /**< \brief Timer Counter Control 2 (TCC2) */ |
AnnaBridge | 171:3a7713b1edbc | 358 | #define ID_TC3 75 /**< \brief Basic Timer Counter 3 (TC3) */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define ID_TC4 76 /**< \brief Basic Timer Counter 4 (TC4) */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define ID_TC5 77 /**< \brief Basic Timer Counter 5 (TC5) */ |
AnnaBridge | 171:3a7713b1edbc | 361 | #define ID_TC6 78 /**< \brief Basic Timer Counter 6 (TC6) */ |
AnnaBridge | 171:3a7713b1edbc | 362 | #define ID_TC7 79 /**< \brief Basic Timer Counter 7 (TC7) */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #define ID_ADC 80 /**< \brief Analog Digital Converter (ADC) */ |
AnnaBridge | 171:3a7713b1edbc | 364 | #define ID_AC 81 /**< \brief Analog Comparators (AC) */ |
AnnaBridge | 171:3a7713b1edbc | 365 | #define ID_DAC 82 /**< \brief Digital Analog Converter (DAC) */ |
AnnaBridge | 171:3a7713b1edbc | 366 | #define ID_PTC 83 /**< \brief Peripheral Touch Controller (PTC) */ |
AnnaBridge | 171:3a7713b1edbc | 367 | #define ID_I2S 84 /**< \brief Inter-IC Sound Interface (I2S) */ |
AnnaBridge | 171:3a7713b1edbc | 368 | |
AnnaBridge | 171:3a7713b1edbc | 369 | #define ID_PERIPH_COUNT 85 /**< \brief Number of peripheral IDs */ |
AnnaBridge | 171:3a7713b1edbc | 370 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 371 | |
AnnaBridge | 171:3a7713b1edbc | 372 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 373 | /** BASE ADDRESS DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 374 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 375 | /** \defgroup SAMD21J17A_base Peripheral Base Address Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 376 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 377 | |
AnnaBridge | 171:3a7713b1edbc | 378 | #if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) |
AnnaBridge | 171:3a7713b1edbc | 379 | #define AC (0x42004400UL) /**< \brief (AC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 380 | #define ADC (0x42004000UL) /**< \brief (ADC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define DAC (0x42004800UL) /**< \brief (DAC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define DMAC (0x41004800UL) /**< \brief (DMAC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define DSU (0x41002000UL) /**< \brief (DSU) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define EIC (0x40001800UL) /**< \brief (EIC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define EVSYS (0x42000400UL) /**< \brief (EVSYS) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define GCLK (0x40000C00UL) /**< \brief (GCLK) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 387 | #define SBMATRIX (0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 388 | #define I2S (0x42005000UL) /**< \brief (I2S) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 389 | #define MTB (0x41006000UL) /**< \brief (MTB) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 390 | #define NVMCTRL (0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 391 | #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 392 | #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 393 | #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 394 | #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 395 | #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 396 | #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 397 | #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 398 | #define PAC0 (0x40000000UL) /**< \brief (PAC0) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 399 | #define PAC1 (0x41000000UL) /**< \brief (PAC1) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 400 | #define PAC2 (0x42000000UL) /**< \brief (PAC2) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 401 | #define PM (0x40000400UL) /**< \brief (PM) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 402 | #define PORT (0x41004400UL) /**< \brief (PORT) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 403 | #define PORT_IOBUS (0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 404 | #define RTC (0x40001400UL) /**< \brief (RTC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 405 | #define SERCOM0 (0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 406 | #define SERCOM1 (0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 407 | #define SERCOM2 (0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 408 | #define SERCOM3 (0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 409 | #define SERCOM4 (0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define SERCOM5 (0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 411 | #define SYSCTRL (0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 412 | #define TC3 (0x42002C00UL) /**< \brief (TC3) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define TC4 (0x42003000UL) /**< \brief (TC4) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 414 | #define TC5 (0x42003400UL) /**< \brief (TC5) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 415 | #define TC6 (0x42003800UL) /**< \brief (TC6) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 416 | #define TC7 (0x42003C00UL) /**< \brief (TC7) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 417 | #define TCC0 (0x42002000UL) /**< \brief (TCC0) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 418 | #define TCC1 (0x42002400UL) /**< \brief (TCC1) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define TCC2 (0x42002800UL) /**< \brief (TCC2) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 420 | #define USB (0x41005000UL) /**< \brief (USB) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 421 | #define WDT (0x40001000UL) /**< \brief (WDT) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 422 | #else |
AnnaBridge | 171:3a7713b1edbc | 423 | #define AC ((Ac *)0x42004400UL) /**< \brief (AC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 424 | #define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 425 | #define AC_INSTS { AC } /**< \brief (AC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 426 | |
AnnaBridge | 171:3a7713b1edbc | 427 | #define ADC ((Adc *)0x42004000UL) /**< \brief (ADC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 428 | #define ADC_INST_NUM 1 /**< \brief (ADC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 429 | #define ADC_INSTS { ADC } /**< \brief (ADC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 430 | |
AnnaBridge | 171:3a7713b1edbc | 431 | #define DAC ((Dac *)0x42004800UL) /**< \brief (DAC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 432 | #define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 433 | #define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 434 | |
AnnaBridge | 171:3a7713b1edbc | 435 | #define DMAC ((Dmac *)0x41004800UL) /**< \brief (DMAC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 436 | #define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 437 | #define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 438 | |
AnnaBridge | 171:3a7713b1edbc | 439 | #define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 440 | #define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 442 | |
AnnaBridge | 171:3a7713b1edbc | 443 | #define EIC ((Eic *)0x40001800UL) /**< \brief (EIC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 444 | #define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 445 | #define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 446 | |
AnnaBridge | 171:3a7713b1edbc | 447 | #define EVSYS ((Evsys *)0x42000400UL) /**< \brief (EVSYS) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 448 | #define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 449 | #define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 450 | |
AnnaBridge | 171:3a7713b1edbc | 451 | #define GCLK ((Gclk *)0x40000C00UL) /**< \brief (GCLK) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 452 | #define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 453 | #define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 454 | |
AnnaBridge | 171:3a7713b1edbc | 455 | #define SBMATRIX ((Hmatrixb *)0x41007000UL) /**< \brief (SBMATRIX) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 456 | #define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 457 | #define HMATRIXB_INSTS { SBMATRIX } /**< \brief (HMATRIXB) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 458 | |
AnnaBridge | 171:3a7713b1edbc | 459 | #define I2S ((I2s *)0x42005000UL) /**< \brief (I2S) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 460 | #define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 461 | #define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 462 | |
AnnaBridge | 171:3a7713b1edbc | 463 | #define MTB ((Mtb *)0x41006000UL) /**< \brief (MTB) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 464 | #define MTB_INST_NUM 1 /**< \brief (MTB) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 465 | #define MTB_INSTS { MTB } /**< \brief (MTB) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 466 | |
AnnaBridge | 171:3a7713b1edbc | 467 | #define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 468 | #define NVMCTRL_CAL (0x00800000UL) /**< \brief (NVMCTRL) CAL Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 469 | #define NVMCTRL_LOCKBIT (0x00802000UL) /**< \brief (NVMCTRL) LOCKBIT Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 470 | #define NVMCTRL_OTP1 (0x00806000UL) /**< \brief (NVMCTRL) OTP1 Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 471 | #define NVMCTRL_OTP2 (0x00806008UL) /**< \brief (NVMCTRL) OTP2 Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 472 | #define NVMCTRL_OTP4 (0x00806020UL) /**< \brief (NVMCTRL) OTP4 Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 473 | #define NVMCTRL_TEMP_LOG (0x00806030UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 474 | #define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 475 | #define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 476 | #define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 477 | |
AnnaBridge | 171:3a7713b1edbc | 478 | #define PAC0 ((Pac *)0x40000000UL) /**< \brief (PAC0) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 479 | #define PAC1 ((Pac *)0x41000000UL) /**< \brief (PAC1) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 480 | #define PAC2 ((Pac *)0x42000000UL) /**< \brief (PAC2) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 481 | #define PAC_INST_NUM 3 /**< \brief (PAC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 482 | #define PAC_INSTS { PAC0, PAC1, PAC2 } /**< \brief (PAC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 483 | |
AnnaBridge | 171:3a7713b1edbc | 484 | #define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 485 | #define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 486 | #define PM_INSTS { PM } /**< \brief (PM) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 487 | |
AnnaBridge | 171:3a7713b1edbc | 488 | #define PORT ((Port *)0x41004400UL) /**< \brief (PORT) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 489 | #define PORT_IOBUS ((Port *)0x60000000UL) /**< \brief (PORT) IOBUS Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 490 | #define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 491 | #define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 492 | |
AnnaBridge | 171:3a7713b1edbc | 493 | #define PTC_GCLK_ID 34 |
AnnaBridge | 171:3a7713b1edbc | 494 | #define PTC_INST_NUM 1 /**< \brief (PTC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #define PTC_INSTS { PTC } /**< \brief (PTC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 496 | |
AnnaBridge | 171:3a7713b1edbc | 497 | #define RTC ((Rtc *)0x40001400UL) /**< \brief (RTC) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 498 | #define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 499 | #define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 500 | |
AnnaBridge | 171:3a7713b1edbc | 501 | #define SERCOM0 ((Sercom *)0x42000800UL) /**< \brief (SERCOM0) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 502 | #define SERCOM1 ((Sercom *)0x42000C00UL) /**< \brief (SERCOM1) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 503 | #define SERCOM2 ((Sercom *)0x42001000UL) /**< \brief (SERCOM2) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 504 | #define SERCOM3 ((Sercom *)0x42001400UL) /**< \brief (SERCOM3) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 505 | #define SERCOM4 ((Sercom *)0x42001800UL) /**< \brief (SERCOM4) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 506 | #define SERCOM5 ((Sercom *)0x42001C00UL) /**< \brief (SERCOM5) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 507 | #define SERCOM_INST_NUM 6 /**< \brief (SERCOM) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 508 | #define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5 } /**< \brief (SERCOM) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 509 | |
AnnaBridge | 171:3a7713b1edbc | 510 | #define SYSCTRL ((Sysctrl *)0x40000800UL) /**< \brief (SYSCTRL) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 511 | #define SYSCTRL_INST_NUM 1 /**< \brief (SYSCTRL) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 512 | #define SYSCTRL_INSTS { SYSCTRL } /**< \brief (SYSCTRL) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 513 | |
AnnaBridge | 171:3a7713b1edbc | 514 | #define TC3 ((Tc *)0x42002C00UL) /**< \brief (TC3) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 515 | #define TC4 ((Tc *)0x42003000UL) /**< \brief (TC4) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 516 | #define TC5 ((Tc *)0x42003400UL) /**< \brief (TC5) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 517 | #define TC6 ((Tc *)0x42003800UL) /**< \brief (TC6) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 518 | #define TC7 ((Tc *)0x42003C00UL) /**< \brief (TC7) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 519 | #define TC_INST_NUM 5 /**< \brief (TC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 520 | #define TC_INSTS { TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 521 | |
AnnaBridge | 171:3a7713b1edbc | 522 | #define TCC0 ((Tcc *)0x42002000UL) /**< \brief (TCC0) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 523 | #define TCC1 ((Tcc *)0x42002400UL) /**< \brief (TCC1) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 524 | #define TCC2 ((Tcc *)0x42002800UL) /**< \brief (TCC2) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 525 | #define TCC_INST_NUM 3 /**< \brief (TCC) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 526 | #define TCC_INSTS { TCC0, TCC1, TCC2 } /**< \brief (TCC) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 527 | |
AnnaBridge | 171:3a7713b1edbc | 528 | #define USB ((Usb *)0x41005000UL) /**< \brief (USB) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 529 | #define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 530 | #define USB_INSTS { USB } /**< \brief (USB) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 531 | |
AnnaBridge | 171:3a7713b1edbc | 532 | #define WDT ((Wdt *)0x40001000UL) /**< \brief (WDT) APB Base Address */ |
AnnaBridge | 171:3a7713b1edbc | 533 | #define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ |
AnnaBridge | 171:3a7713b1edbc | 534 | #define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ |
AnnaBridge | 171:3a7713b1edbc | 535 | |
AnnaBridge | 171:3a7713b1edbc | 536 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 537 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 538 | |
AnnaBridge | 171:3a7713b1edbc | 539 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 540 | /** PORT DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 541 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 542 | /** \defgroup SAMD21J17A_port PORT Definitions */ |
AnnaBridge | 171:3a7713b1edbc | 543 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 544 | |
AnnaBridge | 171:3a7713b1edbc | 545 | #include "pio_samd21j17a.h" |
AnnaBridge | 171:3a7713b1edbc | 546 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 547 | |
AnnaBridge | 171:3a7713b1edbc | 548 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 549 | /** MEMORY MAPPING DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 550 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 551 | |
AnnaBridge | 171:3a7713b1edbc | 552 | #define FLASH_SIZE 0x20000UL /* 128 kB */ |
AnnaBridge | 171:3a7713b1edbc | 553 | #define FLASH_PAGE_SIZE 64 |
AnnaBridge | 171:3a7713b1edbc | 554 | #define FLASH_NB_OF_PAGES 2048 |
AnnaBridge | 171:3a7713b1edbc | 555 | #define FLASH_USER_PAGE_SIZE 64 |
AnnaBridge | 171:3a7713b1edbc | 556 | #define HMCRAMC0_SIZE 0x4000UL /* 16 kB */ |
AnnaBridge | 171:3a7713b1edbc | 557 | #define FLASH_ADDR (0x00000000UL) /**< FLASH base address */ |
AnnaBridge | 171:3a7713b1edbc | 558 | #define FLASH_USER_PAGE_ADDR (0x00800000UL) /**< FLASH_USER_PAGE base address */ |
AnnaBridge | 171:3a7713b1edbc | 559 | #define HMCRAMC0_ADDR (0x20000000UL) /**< HMCRAMC0 base address */ |
AnnaBridge | 171:3a7713b1edbc | 560 | |
AnnaBridge | 171:3a7713b1edbc | 561 | #define DSU_DID_RESETVALUE 0x10010001UL |
AnnaBridge | 171:3a7713b1edbc | 562 | #define EIC_EXTINT_NUM 16 |
AnnaBridge | 171:3a7713b1edbc | 563 | #define PORT_GROUPS 2 |
AnnaBridge | 171:3a7713b1edbc | 564 | |
AnnaBridge | 171:3a7713b1edbc | 565 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 566 | /** ELECTRICAL DEFINITIONS FOR SAMD21J17A */ |
AnnaBridge | 171:3a7713b1edbc | 567 | /* ************************************************************************** */ |
AnnaBridge | 171:3a7713b1edbc | 568 | |
AnnaBridge | 171:3a7713b1edbc | 569 | |
AnnaBridge | 171:3a7713b1edbc | 570 | #ifdef __cplusplus |
AnnaBridge | 171:3a7713b1edbc | 571 | } |
AnnaBridge | 171:3a7713b1edbc | 572 | #endif |
AnnaBridge | 171:3a7713b1edbc | 573 | |
AnnaBridge | 171:3a7713b1edbc | 574 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 575 | |
AnnaBridge | 171:3a7713b1edbc | 576 | #endif /* SAMD21J17A_H */ |