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TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/comp_usb.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Component description for USB |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_USB_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_USB_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | /** SOFTWARE API DEFINITION FOR USB */ |
AnnaBridge | 171:3a7713b1edbc | 52 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 53 | /** \addtogroup SAMD21_USB Universal Serial Bus */ |
AnnaBridge | 171:3a7713b1edbc | 54 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | #define USB_U2222 |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REV_USB 0x103 |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | /* -------- USB_CTRLA : (USB Offset: 0x000) (R/W 8) Control A -------- */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 61 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 62 | struct { |
AnnaBridge | 171:3a7713b1edbc | 63 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
AnnaBridge | 171:3a7713b1edbc | 64 | uint8_t ENABLE:1; /*!< bit: 1 Enable */ |
AnnaBridge | 171:3a7713b1edbc | 65 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby Mode */ |
AnnaBridge | 171:3a7713b1edbc | 66 | uint8_t :4; /*!< bit: 3.. 6 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 67 | uint8_t MODE:1; /*!< bit: 7 Operating Mode */ |
AnnaBridge | 171:3a7713b1edbc | 68 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 69 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 70 | } USB_CTRLA_Type; |
AnnaBridge | 171:3a7713b1edbc | 71 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 72 | |
AnnaBridge | 171:3a7713b1edbc | 73 | #define USB_CTRLA_OFFSET 0x000 /**< \brief (USB_CTRLA offset) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define USB_CTRLA_RESETVALUE 0x00ul /**< \brief (USB_CTRLA reset_value) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 75 | |
AnnaBridge | 171:3a7713b1edbc | 76 | #define USB_CTRLA_SWRST_Pos 0 /**< \brief (USB_CTRLA) Software Reset */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define USB_CTRLA_SWRST (0x1ul << USB_CTRLA_SWRST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 78 | #define USB_CTRLA_ENABLE_Pos 1 /**< \brief (USB_CTRLA) Enable */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define USB_CTRLA_ENABLE (0x1ul << USB_CTRLA_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 80 | #define USB_CTRLA_RUNSTDBY_Pos 2 /**< \brief (USB_CTRLA) Run in Standby Mode */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define USB_CTRLA_RUNSTDBY (0x1ul << USB_CTRLA_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 82 | #define USB_CTRLA_MODE_Pos 7 /**< \brief (USB_CTRLA) Operating Mode */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define USB_CTRLA_MODE (0x1ul << USB_CTRLA_MODE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 84 | #define USB_CTRLA_MODE_DEVICE_Val 0x0ul /**< \brief (USB_CTRLA) Device Mode */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define USB_CTRLA_MODE_HOST_Val 0x1ul /**< \brief (USB_CTRLA) Host Mode */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define USB_CTRLA_MODE_DEVICE (USB_CTRLA_MODE_DEVICE_Val << USB_CTRLA_MODE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 87 | #define USB_CTRLA_MODE_HOST (USB_CTRLA_MODE_HOST_Val << USB_CTRLA_MODE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 88 | #define USB_CTRLA_MASK 0x87ul /**< \brief (USB_CTRLA) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 89 | |
AnnaBridge | 171:3a7713b1edbc | 90 | /* -------- USB_SYNCBUSY : (USB Offset: 0x002) (R/ 8) Synchronization Busy -------- */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 92 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 93 | struct { |
AnnaBridge | 171:3a7713b1edbc | 94 | uint8_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 95 | uint8_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 96 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 97 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 98 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 99 | } USB_SYNCBUSY_Type; |
AnnaBridge | 171:3a7713b1edbc | 100 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 101 | |
AnnaBridge | 171:3a7713b1edbc | 102 | #define USB_SYNCBUSY_OFFSET 0x002 /**< \brief (USB_SYNCBUSY offset) Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define USB_SYNCBUSY_RESETVALUE 0x00ul /**< \brief (USB_SYNCBUSY reset_value) Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 104 | |
AnnaBridge | 171:3a7713b1edbc | 105 | #define USB_SYNCBUSY_SWRST_Pos 0 /**< \brief (USB_SYNCBUSY) Software Reset Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define USB_SYNCBUSY_SWRST (0x1ul << USB_SYNCBUSY_SWRST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 107 | #define USB_SYNCBUSY_ENABLE_Pos 1 /**< \brief (USB_SYNCBUSY) Enable Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define USB_SYNCBUSY_ENABLE (0x1ul << USB_SYNCBUSY_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 109 | #define USB_SYNCBUSY_MASK 0x03ul /**< \brief (USB_SYNCBUSY) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 110 | |
AnnaBridge | 171:3a7713b1edbc | 111 | /* -------- USB_QOSCTRL : (USB Offset: 0x003) (R/W 8) USB Quality Of Service -------- */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 113 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 114 | struct { |
AnnaBridge | 171:3a7713b1edbc | 115 | uint8_t CQOS:2; /*!< bit: 0.. 1 Configuration Quality of Service */ |
AnnaBridge | 171:3a7713b1edbc | 116 | uint8_t DQOS:2; /*!< bit: 2.. 3 Data Quality of Service */ |
AnnaBridge | 171:3a7713b1edbc | 117 | uint8_t :4; /*!< bit: 4.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 118 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 119 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 120 | } USB_QOSCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 121 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | #define USB_QOSCTRL_OFFSET 0x003 /**< \brief (USB_QOSCTRL offset) USB Quality Of Service */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define USB_QOSCTRL_RESETVALUE 0x05ul /**< \brief (USB_QOSCTRL reset_value) USB Quality Of Service */ |
AnnaBridge | 171:3a7713b1edbc | 125 | |
AnnaBridge | 171:3a7713b1edbc | 126 | #define USB_QOSCTRL_CQOS_Pos 0 /**< \brief (USB_QOSCTRL) Configuration Quality of Service */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define USB_QOSCTRL_CQOS_Msk (0x3ul << USB_QOSCTRL_CQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 128 | #define USB_QOSCTRL_CQOS(value) ((USB_QOSCTRL_CQOS_Msk & ((value) << USB_QOSCTRL_CQOS_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 129 | #define USB_QOSCTRL_CQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define USB_QOSCTRL_CQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define USB_QOSCTRL_CQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define USB_QOSCTRL_CQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define USB_QOSCTRL_CQOS_DISABLE (USB_QOSCTRL_CQOS_DISABLE_Val << USB_QOSCTRL_CQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 134 | #define USB_QOSCTRL_CQOS_LOW (USB_QOSCTRL_CQOS_LOW_Val << USB_QOSCTRL_CQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 135 | #define USB_QOSCTRL_CQOS_MEDIUM (USB_QOSCTRL_CQOS_MEDIUM_Val << USB_QOSCTRL_CQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 136 | #define USB_QOSCTRL_CQOS_HIGH (USB_QOSCTRL_CQOS_HIGH_Val << USB_QOSCTRL_CQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 137 | #define USB_QOSCTRL_DQOS_Pos 2 /**< \brief (USB_QOSCTRL) Data Quality of Service */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define USB_QOSCTRL_DQOS_Msk (0x3ul << USB_QOSCTRL_DQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 139 | #define USB_QOSCTRL_DQOS(value) ((USB_QOSCTRL_DQOS_Msk & ((value) << USB_QOSCTRL_DQOS_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 140 | #define USB_QOSCTRL_DQOS_DISABLE_Val 0x0ul /**< \brief (USB_QOSCTRL) Background (no sensitive operation) */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define USB_QOSCTRL_DQOS_LOW_Val 0x1ul /**< \brief (USB_QOSCTRL) Sensitive Bandwidth */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define USB_QOSCTRL_DQOS_MEDIUM_Val 0x2ul /**< \brief (USB_QOSCTRL) Sensitive Latency */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define USB_QOSCTRL_DQOS_HIGH_Val 0x3ul /**< \brief (USB_QOSCTRL) Critical Latency */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define USB_QOSCTRL_DQOS_DISABLE (USB_QOSCTRL_DQOS_DISABLE_Val << USB_QOSCTRL_DQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 145 | #define USB_QOSCTRL_DQOS_LOW (USB_QOSCTRL_DQOS_LOW_Val << USB_QOSCTRL_DQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 146 | #define USB_QOSCTRL_DQOS_MEDIUM (USB_QOSCTRL_DQOS_MEDIUM_Val << USB_QOSCTRL_DQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 147 | #define USB_QOSCTRL_DQOS_HIGH (USB_QOSCTRL_DQOS_HIGH_Val << USB_QOSCTRL_DQOS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 148 | #define USB_QOSCTRL_MASK 0x0Ful /**< \brief (USB_QOSCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 149 | |
AnnaBridge | 171:3a7713b1edbc | 150 | /* -------- USB_DEVICE_CTRLB : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE Control B -------- */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 152 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 153 | struct { |
AnnaBridge | 171:3a7713b1edbc | 154 | uint16_t DETACH:1; /*!< bit: 0 Detach */ |
AnnaBridge | 171:3a7713b1edbc | 155 | uint16_t UPRSM:1; /*!< bit: 1 Upstream Resume */ |
AnnaBridge | 171:3a7713b1edbc | 156 | uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 157 | uint16_t NREPLY:1; /*!< bit: 4 No Reply */ |
AnnaBridge | 171:3a7713b1edbc | 158 | uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ |
AnnaBridge | 171:3a7713b1edbc | 159 | uint16_t TSTK:1; /*!< bit: 6 Test mode K */ |
AnnaBridge | 171:3a7713b1edbc | 160 | uint16_t TSTPCKT:1; /*!< bit: 7 Test packet mode */ |
AnnaBridge | 171:3a7713b1edbc | 161 | uint16_t OPMODE2:1; /*!< bit: 8 Specific Operational Mode */ |
AnnaBridge | 171:3a7713b1edbc | 162 | uint16_t GNAK:1; /*!< bit: 9 Global NAK */ |
AnnaBridge | 171:3a7713b1edbc | 163 | uint16_t LPMHDSK:2; /*!< bit: 10..11 Link Power Management Handshake */ |
AnnaBridge | 171:3a7713b1edbc | 164 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 165 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 166 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 167 | } USB_DEVICE_CTRLB_Type; |
AnnaBridge | 171:3a7713b1edbc | 168 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 169 | |
AnnaBridge | 171:3a7713b1edbc | 170 | #define USB_DEVICE_CTRLB_OFFSET 0x008 /**< \brief (USB_DEVICE_CTRLB offset) DEVICE Control B */ |
AnnaBridge | 171:3a7713b1edbc | 171 | #define USB_DEVICE_CTRLB_RESETVALUE 0x0001ul /**< \brief (USB_DEVICE_CTRLB reset_value) DEVICE Control B */ |
AnnaBridge | 171:3a7713b1edbc | 172 | |
AnnaBridge | 171:3a7713b1edbc | 173 | #define USB_DEVICE_CTRLB_DETACH_Pos 0 /**< \brief (USB_DEVICE_CTRLB) Detach */ |
AnnaBridge | 171:3a7713b1edbc | 174 | #define USB_DEVICE_CTRLB_DETACH (0x1ul << USB_DEVICE_CTRLB_DETACH_Pos) |
AnnaBridge | 171:3a7713b1edbc | 175 | #define USB_DEVICE_CTRLB_UPRSM_Pos 1 /**< \brief (USB_DEVICE_CTRLB) Upstream Resume */ |
AnnaBridge | 171:3a7713b1edbc | 176 | #define USB_DEVICE_CTRLB_UPRSM (0x1ul << USB_DEVICE_CTRLB_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 177 | #define USB_DEVICE_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_DEVICE_CTRLB) Speed Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 178 | #define USB_DEVICE_CTRLB_SPDCONF_Msk (0x3ul << USB_DEVICE_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 179 | #define USB_DEVICE_CTRLB_SPDCONF(value) ((USB_DEVICE_CTRLB_SPDCONF_Msk & ((value) << USB_DEVICE_CTRLB_SPDCONF_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 180 | #define USB_DEVICE_CTRLB_SPDCONF_FS_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) FS : Full Speed */ |
AnnaBridge | 171:3a7713b1edbc | 181 | #define USB_DEVICE_CTRLB_SPDCONF_LS_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) LS : Low Speed */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define USB_DEVICE_CTRLB_SPDCONF_HS_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) HS : High Speed capable */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #define USB_DEVICE_CTRLB_SPDCONF_HSTM_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) HSTM: High Speed Test Mode (force high-speed mode for test mode) */ |
AnnaBridge | 171:3a7713b1edbc | 184 | #define USB_DEVICE_CTRLB_SPDCONF_FS (USB_DEVICE_CTRLB_SPDCONF_FS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 185 | #define USB_DEVICE_CTRLB_SPDCONF_LS (USB_DEVICE_CTRLB_SPDCONF_LS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 186 | #define USB_DEVICE_CTRLB_SPDCONF_HS (USB_DEVICE_CTRLB_SPDCONF_HS_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 187 | #define USB_DEVICE_CTRLB_SPDCONF_HSTM (USB_DEVICE_CTRLB_SPDCONF_HSTM_Val << USB_DEVICE_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 188 | #define USB_DEVICE_CTRLB_NREPLY_Pos 4 /**< \brief (USB_DEVICE_CTRLB) No Reply */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define USB_DEVICE_CTRLB_NREPLY (0x1ul << USB_DEVICE_CTRLB_NREPLY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 190 | #define USB_DEVICE_CTRLB_TSTJ_Pos 5 /**< \brief (USB_DEVICE_CTRLB) Test mode J */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define USB_DEVICE_CTRLB_TSTJ (0x1ul << USB_DEVICE_CTRLB_TSTJ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 192 | #define USB_DEVICE_CTRLB_TSTK_Pos 6 /**< \brief (USB_DEVICE_CTRLB) Test mode K */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #define USB_DEVICE_CTRLB_TSTK (0x1ul << USB_DEVICE_CTRLB_TSTK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 194 | #define USB_DEVICE_CTRLB_TSTPCKT_Pos 7 /**< \brief (USB_DEVICE_CTRLB) Test packet mode */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define USB_DEVICE_CTRLB_TSTPCKT (0x1ul << USB_DEVICE_CTRLB_TSTPCKT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 196 | #define USB_DEVICE_CTRLB_OPMODE2_Pos 8 /**< \brief (USB_DEVICE_CTRLB) Specific Operational Mode */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define USB_DEVICE_CTRLB_OPMODE2 (0x1ul << USB_DEVICE_CTRLB_OPMODE2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 198 | #define USB_DEVICE_CTRLB_GNAK_Pos 9 /**< \brief (USB_DEVICE_CTRLB) Global NAK */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define USB_DEVICE_CTRLB_GNAK (0x1ul << USB_DEVICE_CTRLB_GNAK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 200 | #define USB_DEVICE_CTRLB_LPMHDSK_Pos 10 /**< \brief (USB_DEVICE_CTRLB) Link Power Management Handshake */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define USB_DEVICE_CTRLB_LPMHDSK_Msk (0x3ul << USB_DEVICE_CTRLB_LPMHDSK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 202 | #define USB_DEVICE_CTRLB_LPMHDSK(value) ((USB_DEVICE_CTRLB_LPMHDSK_Msk & ((value) << USB_DEVICE_CTRLB_LPMHDSK_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 203 | #define USB_DEVICE_CTRLB_LPMHDSK_NO_Val 0x0ul /**< \brief (USB_DEVICE_CTRLB) No handshake. LPM is not supported */ |
AnnaBridge | 171:3a7713b1edbc | 204 | #define USB_DEVICE_CTRLB_LPMHDSK_ACK_Val 0x1ul /**< \brief (USB_DEVICE_CTRLB) ACK */ |
AnnaBridge | 171:3a7713b1edbc | 205 | #define USB_DEVICE_CTRLB_LPMHDSK_NYET_Val 0x2ul /**< \brief (USB_DEVICE_CTRLB) NYET */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define USB_DEVICE_CTRLB_LPMHDSK_STALL_Val 0x3ul /**< \brief (USB_DEVICE_CTRLB) STALL */ |
AnnaBridge | 171:3a7713b1edbc | 207 | #define USB_DEVICE_CTRLB_LPMHDSK_NO (USB_DEVICE_CTRLB_LPMHDSK_NO_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 208 | #define USB_DEVICE_CTRLB_LPMHDSK_ACK (USB_DEVICE_CTRLB_LPMHDSK_ACK_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 209 | #define USB_DEVICE_CTRLB_LPMHDSK_NYET (USB_DEVICE_CTRLB_LPMHDSK_NYET_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 210 | #define USB_DEVICE_CTRLB_LPMHDSK_STALL (USB_DEVICE_CTRLB_LPMHDSK_STALL_Val << USB_DEVICE_CTRLB_LPMHDSK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 211 | #define USB_DEVICE_CTRLB_MASK 0x0FFFul /**< \brief (USB_DEVICE_CTRLB) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 212 | |
AnnaBridge | 171:3a7713b1edbc | 213 | /* -------- USB_HOST_CTRLB : (USB Offset: 0x008) (R/W 16) HOST HOST Control B -------- */ |
AnnaBridge | 171:3a7713b1edbc | 214 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 215 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 216 | struct { |
AnnaBridge | 171:3a7713b1edbc | 217 | uint16_t :1; /*!< bit: 0 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 218 | uint16_t RESUME:1; /*!< bit: 1 Send USB Resume */ |
AnnaBridge | 171:3a7713b1edbc | 219 | uint16_t SPDCONF:2; /*!< bit: 2.. 3 Speed Configuration for Host */ |
AnnaBridge | 171:3a7713b1edbc | 220 | uint16_t :1; /*!< bit: 4 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 221 | uint16_t TSTJ:1; /*!< bit: 5 Test mode J */ |
AnnaBridge | 171:3a7713b1edbc | 222 | uint16_t TSTK:1; /*!< bit: 6 Test mode K */ |
AnnaBridge | 171:3a7713b1edbc | 223 | uint16_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 224 | uint16_t SOFE:1; /*!< bit: 8 Start of Frame Generation Enable */ |
AnnaBridge | 171:3a7713b1edbc | 225 | uint16_t BUSRESET:1; /*!< bit: 9 Send USB Reset */ |
AnnaBridge | 171:3a7713b1edbc | 226 | uint16_t VBUSOK:1; /*!< bit: 10 VBUS is OK */ |
AnnaBridge | 171:3a7713b1edbc | 227 | uint16_t L1RESUME:1; /*!< bit: 11 Send L1 Resume */ |
AnnaBridge | 171:3a7713b1edbc | 228 | uint16_t :4; /*!< bit: 12..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 229 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 230 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 231 | } USB_HOST_CTRLB_Type; |
AnnaBridge | 171:3a7713b1edbc | 232 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 233 | |
AnnaBridge | 171:3a7713b1edbc | 234 | #define USB_HOST_CTRLB_OFFSET 0x008 /**< \brief (USB_HOST_CTRLB offset) HOST Control B */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #define USB_HOST_CTRLB_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRLB reset_value) HOST Control B */ |
AnnaBridge | 171:3a7713b1edbc | 236 | |
AnnaBridge | 171:3a7713b1edbc | 237 | #define USB_HOST_CTRLB_RESUME_Pos 1 /**< \brief (USB_HOST_CTRLB) Send USB Resume */ |
AnnaBridge | 171:3a7713b1edbc | 238 | #define USB_HOST_CTRLB_RESUME (0x1ul << USB_HOST_CTRLB_RESUME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 239 | #define USB_HOST_CTRLB_SPDCONF_Pos 2 /**< \brief (USB_HOST_CTRLB) Speed Configuration for Host */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define USB_HOST_CTRLB_SPDCONF_Msk (0x3ul << USB_HOST_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 241 | #define USB_HOST_CTRLB_SPDCONF(value) ((USB_HOST_CTRLB_SPDCONF_Msk & ((value) << USB_HOST_CTRLB_SPDCONF_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 242 | #define USB_HOST_CTRLB_SPDCONF_NORMAL_Val 0x0ul /**< \brief (USB_HOST_CTRLB) Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #define USB_HOST_CTRLB_SPDCONF_FS_Val 0x3ul /**< \brief (USB_HOST_CTRLB) Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. */ |
AnnaBridge | 171:3a7713b1edbc | 244 | #define USB_HOST_CTRLB_SPDCONF_NORMAL (USB_HOST_CTRLB_SPDCONF_NORMAL_Val << USB_HOST_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 245 | #define USB_HOST_CTRLB_SPDCONF_FS (USB_HOST_CTRLB_SPDCONF_FS_Val << USB_HOST_CTRLB_SPDCONF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 246 | #define USB_HOST_CTRLB_TSTJ_Pos 5 /**< \brief (USB_HOST_CTRLB) Test mode J */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define USB_HOST_CTRLB_TSTJ (0x1ul << USB_HOST_CTRLB_TSTJ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 248 | #define USB_HOST_CTRLB_TSTK_Pos 6 /**< \brief (USB_HOST_CTRLB) Test mode K */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define USB_HOST_CTRLB_TSTK (0x1ul << USB_HOST_CTRLB_TSTK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 250 | #define USB_HOST_CTRLB_SOFE_Pos 8 /**< \brief (USB_HOST_CTRLB) Start of Frame Generation Enable */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define USB_HOST_CTRLB_SOFE (0x1ul << USB_HOST_CTRLB_SOFE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 252 | #define USB_HOST_CTRLB_BUSRESET_Pos 9 /**< \brief (USB_HOST_CTRLB) Send USB Reset */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define USB_HOST_CTRLB_BUSRESET (0x1ul << USB_HOST_CTRLB_BUSRESET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 254 | #define USB_HOST_CTRLB_VBUSOK_Pos 10 /**< \brief (USB_HOST_CTRLB) VBUS is OK */ |
AnnaBridge | 171:3a7713b1edbc | 255 | #define USB_HOST_CTRLB_VBUSOK (0x1ul << USB_HOST_CTRLB_VBUSOK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 256 | #define USB_HOST_CTRLB_L1RESUME_Pos 11 /**< \brief (USB_HOST_CTRLB) Send L1 Resume */ |
AnnaBridge | 171:3a7713b1edbc | 257 | #define USB_HOST_CTRLB_L1RESUME (0x1ul << USB_HOST_CTRLB_L1RESUME_Pos) |
AnnaBridge | 171:3a7713b1edbc | 258 | #define USB_HOST_CTRLB_MASK 0x0F6Eul /**< \brief (USB_HOST_CTRLB) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 259 | |
AnnaBridge | 171:3a7713b1edbc | 260 | /* -------- USB_DEVICE_DADD : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE Device Address -------- */ |
AnnaBridge | 171:3a7713b1edbc | 261 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 262 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 263 | struct { |
AnnaBridge | 171:3a7713b1edbc | 264 | uint8_t DADD:7; /*!< bit: 0.. 6 Device Address */ |
AnnaBridge | 171:3a7713b1edbc | 265 | uint8_t ADDEN:1; /*!< bit: 7 Device Address Enable */ |
AnnaBridge | 171:3a7713b1edbc | 266 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 267 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 268 | } USB_DEVICE_DADD_Type; |
AnnaBridge | 171:3a7713b1edbc | 269 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 270 | |
AnnaBridge | 171:3a7713b1edbc | 271 | #define USB_DEVICE_DADD_OFFSET 0x00A /**< \brief (USB_DEVICE_DADD offset) DEVICE Device Address */ |
AnnaBridge | 171:3a7713b1edbc | 272 | #define USB_DEVICE_DADD_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_DADD reset_value) DEVICE Device Address */ |
AnnaBridge | 171:3a7713b1edbc | 273 | |
AnnaBridge | 171:3a7713b1edbc | 274 | #define USB_DEVICE_DADD_DADD_Pos 0 /**< \brief (USB_DEVICE_DADD) Device Address */ |
AnnaBridge | 171:3a7713b1edbc | 275 | #define USB_DEVICE_DADD_DADD_Msk (0x7Ful << USB_DEVICE_DADD_DADD_Pos) |
AnnaBridge | 171:3a7713b1edbc | 276 | #define USB_DEVICE_DADD_DADD(value) ((USB_DEVICE_DADD_DADD_Msk & ((value) << USB_DEVICE_DADD_DADD_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 277 | #define USB_DEVICE_DADD_ADDEN_Pos 7 /**< \brief (USB_DEVICE_DADD) Device Address Enable */ |
AnnaBridge | 171:3a7713b1edbc | 278 | #define USB_DEVICE_DADD_ADDEN (0x1ul << USB_DEVICE_DADD_ADDEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 279 | #define USB_DEVICE_DADD_MASK 0xFFul /**< \brief (USB_DEVICE_DADD) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 280 | |
AnnaBridge | 171:3a7713b1edbc | 281 | /* -------- USB_HOST_HSOFC : (USB Offset: 0x00A) (R/W 8) HOST HOST Host Start Of Frame Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 282 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 283 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 284 | struct { |
AnnaBridge | 171:3a7713b1edbc | 285 | uint8_t FLENC:4; /*!< bit: 0.. 3 Frame Length Control */ |
AnnaBridge | 171:3a7713b1edbc | 286 | uint8_t :3; /*!< bit: 4.. 6 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 287 | uint8_t FLENCE:1; /*!< bit: 7 Frame Length Control Enable */ |
AnnaBridge | 171:3a7713b1edbc | 288 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 289 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 290 | } USB_HOST_HSOFC_Type; |
AnnaBridge | 171:3a7713b1edbc | 291 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 292 | |
AnnaBridge | 171:3a7713b1edbc | 293 | #define USB_HOST_HSOFC_OFFSET 0x00A /**< \brief (USB_HOST_HSOFC offset) HOST Host Start Of Frame Control */ |
AnnaBridge | 171:3a7713b1edbc | 294 | #define USB_HOST_HSOFC_RESETVALUE 0x00ul /**< \brief (USB_HOST_HSOFC reset_value) HOST Host Start Of Frame Control */ |
AnnaBridge | 171:3a7713b1edbc | 295 | |
AnnaBridge | 171:3a7713b1edbc | 296 | #define USB_HOST_HSOFC_FLENC_Pos 0 /**< \brief (USB_HOST_HSOFC) Frame Length Control */ |
AnnaBridge | 171:3a7713b1edbc | 297 | #define USB_HOST_HSOFC_FLENC_Msk (0xFul << USB_HOST_HSOFC_FLENC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 298 | #define USB_HOST_HSOFC_FLENC(value) ((USB_HOST_HSOFC_FLENC_Msk & ((value) << USB_HOST_HSOFC_FLENC_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 299 | #define USB_HOST_HSOFC_FLENCE_Pos 7 /**< \brief (USB_HOST_HSOFC) Frame Length Control Enable */ |
AnnaBridge | 171:3a7713b1edbc | 300 | #define USB_HOST_HSOFC_FLENCE (0x1ul << USB_HOST_HSOFC_FLENCE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 301 | #define USB_HOST_HSOFC_MASK 0x8Ful /**< \brief (USB_HOST_HSOFC) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 302 | |
AnnaBridge | 171:3a7713b1edbc | 303 | /* -------- USB_DEVICE_STATUS : (USB Offset: 0x00C) (R/ 8) DEVICE DEVICE Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 304 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 305 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 306 | struct { |
AnnaBridge | 171:3a7713b1edbc | 307 | uint8_t :2; /*!< bit: 0.. 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 308 | uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ |
AnnaBridge | 171:3a7713b1edbc | 309 | uint8_t :2; /*!< bit: 4.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 310 | uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ |
AnnaBridge | 171:3a7713b1edbc | 311 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 312 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 313 | } USB_DEVICE_STATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 314 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 315 | |
AnnaBridge | 171:3a7713b1edbc | 316 | #define USB_DEVICE_STATUS_OFFSET 0x00C /**< \brief (USB_DEVICE_STATUS offset) DEVICE Status */ |
AnnaBridge | 171:3a7713b1edbc | 317 | #define USB_DEVICE_STATUS_RESETVALUE 0x40ul /**< \brief (USB_DEVICE_STATUS reset_value) DEVICE Status */ |
AnnaBridge | 171:3a7713b1edbc | 318 | |
AnnaBridge | 171:3a7713b1edbc | 319 | #define USB_DEVICE_STATUS_SPEED_Pos 2 /**< \brief (USB_DEVICE_STATUS) Speed Status */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define USB_DEVICE_STATUS_SPEED_Msk (0x3ul << USB_DEVICE_STATUS_SPEED_Pos) |
AnnaBridge | 171:3a7713b1edbc | 321 | #define USB_DEVICE_STATUS_SPEED(value) ((USB_DEVICE_STATUS_SPEED_Msk & ((value) << USB_DEVICE_STATUS_SPEED_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 322 | #define USB_DEVICE_STATUS_SPEED_FS_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) Full-speed mode */ |
AnnaBridge | 171:3a7713b1edbc | 323 | #define USB_DEVICE_STATUS_SPEED_HS_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) High-speed mode */ |
AnnaBridge | 171:3a7713b1edbc | 324 | #define USB_DEVICE_STATUS_SPEED_LS_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) Low-speed mode */ |
AnnaBridge | 171:3a7713b1edbc | 325 | #define USB_DEVICE_STATUS_SPEED_FS (USB_DEVICE_STATUS_SPEED_FS_Val << USB_DEVICE_STATUS_SPEED_Pos) |
AnnaBridge | 171:3a7713b1edbc | 326 | #define USB_DEVICE_STATUS_SPEED_HS (USB_DEVICE_STATUS_SPEED_HS_Val << USB_DEVICE_STATUS_SPEED_Pos) |
AnnaBridge | 171:3a7713b1edbc | 327 | #define USB_DEVICE_STATUS_SPEED_LS (USB_DEVICE_STATUS_SPEED_LS_Val << USB_DEVICE_STATUS_SPEED_Pos) |
AnnaBridge | 171:3a7713b1edbc | 328 | #define USB_DEVICE_STATUS_LINESTATE_Pos 6 /**< \brief (USB_DEVICE_STATUS) USB Line State Status */ |
AnnaBridge | 171:3a7713b1edbc | 329 | #define USB_DEVICE_STATUS_LINESTATE_Msk (0x3ul << USB_DEVICE_STATUS_LINESTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 330 | #define USB_DEVICE_STATUS_LINESTATE(value) ((USB_DEVICE_STATUS_LINESTATE_Msk & ((value) << USB_DEVICE_STATUS_LINESTATE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 331 | #define USB_DEVICE_STATUS_LINESTATE_0_Val 0x0ul /**< \brief (USB_DEVICE_STATUS) SE0/RESET */ |
AnnaBridge | 171:3a7713b1edbc | 332 | #define USB_DEVICE_STATUS_LINESTATE_1_Val 0x1ul /**< \brief (USB_DEVICE_STATUS) FS-J or LS-K State */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #define USB_DEVICE_STATUS_LINESTATE_2_Val 0x2ul /**< \brief (USB_DEVICE_STATUS) FS-K or LS-J State */ |
AnnaBridge | 171:3a7713b1edbc | 334 | #define USB_DEVICE_STATUS_LINESTATE_0 (USB_DEVICE_STATUS_LINESTATE_0_Val << USB_DEVICE_STATUS_LINESTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 335 | #define USB_DEVICE_STATUS_LINESTATE_1 (USB_DEVICE_STATUS_LINESTATE_1_Val << USB_DEVICE_STATUS_LINESTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 336 | #define USB_DEVICE_STATUS_LINESTATE_2 (USB_DEVICE_STATUS_LINESTATE_2_Val << USB_DEVICE_STATUS_LINESTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 337 | #define USB_DEVICE_STATUS_MASK 0xCCul /**< \brief (USB_DEVICE_STATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 338 | |
AnnaBridge | 171:3a7713b1edbc | 339 | /* -------- USB_HOST_STATUS : (USB Offset: 0x00C) (R/W 8) HOST HOST Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 341 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 342 | struct { |
AnnaBridge | 171:3a7713b1edbc | 343 | uint8_t :2; /*!< bit: 0.. 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 344 | uint8_t SPEED:2; /*!< bit: 2.. 3 Speed Status */ |
AnnaBridge | 171:3a7713b1edbc | 345 | uint8_t :2; /*!< bit: 4.. 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 346 | uint8_t LINESTATE:2; /*!< bit: 6.. 7 USB Line State Status */ |
AnnaBridge | 171:3a7713b1edbc | 347 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 348 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 349 | } USB_HOST_STATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 350 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 351 | |
AnnaBridge | 171:3a7713b1edbc | 352 | #define USB_HOST_STATUS_OFFSET 0x00C /**< \brief (USB_HOST_STATUS offset) HOST Status */ |
AnnaBridge | 171:3a7713b1edbc | 353 | #define USB_HOST_STATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_STATUS reset_value) HOST Status */ |
AnnaBridge | 171:3a7713b1edbc | 354 | |
AnnaBridge | 171:3a7713b1edbc | 355 | #define USB_HOST_STATUS_SPEED_Pos 2 /**< \brief (USB_HOST_STATUS) Speed Status */ |
AnnaBridge | 171:3a7713b1edbc | 356 | #define USB_HOST_STATUS_SPEED_Msk (0x3ul << USB_HOST_STATUS_SPEED_Pos) |
AnnaBridge | 171:3a7713b1edbc | 357 | #define USB_HOST_STATUS_SPEED(value) ((USB_HOST_STATUS_SPEED_Msk & ((value) << USB_HOST_STATUS_SPEED_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 358 | #define USB_HOST_STATUS_LINESTATE_Pos 6 /**< \brief (USB_HOST_STATUS) USB Line State Status */ |
AnnaBridge | 171:3a7713b1edbc | 359 | #define USB_HOST_STATUS_LINESTATE_Msk (0x3ul << USB_HOST_STATUS_LINESTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 360 | #define USB_HOST_STATUS_LINESTATE(value) ((USB_HOST_STATUS_LINESTATE_Msk & ((value) << USB_HOST_STATUS_LINESTATE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 361 | #define USB_HOST_STATUS_MASK 0xCCul /**< \brief (USB_HOST_STATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 362 | |
AnnaBridge | 171:3a7713b1edbc | 363 | /* -------- USB_FSMSTATUS : (USB Offset: 0x00D) (R/ 8) Finite State Machine Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 364 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 365 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 366 | struct { |
AnnaBridge | 171:3a7713b1edbc | 367 | uint8_t FSMSTATE:6; /*!< bit: 0.. 5 Fine State Machine Status */ |
AnnaBridge | 171:3a7713b1edbc | 368 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 369 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 370 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 371 | } USB_FSMSTATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 372 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 373 | |
AnnaBridge | 171:3a7713b1edbc | 374 | #define USB_FSMSTATUS_OFFSET 0x00D /**< \brief (USB_FSMSTATUS offset) Finite State Machine Status */ |
AnnaBridge | 171:3a7713b1edbc | 375 | #define USB_FSMSTATUS_RESETVALUE 0x01ul /**< \brief (USB_FSMSTATUS reset_value) Finite State Machine Status */ |
AnnaBridge | 171:3a7713b1edbc | 376 | |
AnnaBridge | 171:3a7713b1edbc | 377 | #define USB_FSMSTATUS_FSMSTATE_Pos 0 /**< \brief (USB_FSMSTATUS) Fine State Machine Status */ |
AnnaBridge | 171:3a7713b1edbc | 378 | #define USB_FSMSTATUS_FSMSTATE_Msk (0x3Ful << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 379 | #define USB_FSMSTATUS_FSMSTATE(value) ((USB_FSMSTATUS_FSMSTATE_Msk & ((value) << USB_FSMSTATUS_FSMSTATE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 380 | #define USB_FSMSTATUS_FSMSTATE_OFF_Val 0x1ul /**< \brief (USB_FSMSTATUS) OFF (L3). It corresponds to the powered-off, disconnected, and disabled state */ |
AnnaBridge | 171:3a7713b1edbc | 381 | #define USB_FSMSTATUS_FSMSTATE_ON_Val 0x2ul /**< \brief (USB_FSMSTATUS) ON (L0). It corresponds to the Idle and Active states */ |
AnnaBridge | 171:3a7713b1edbc | 382 | #define USB_FSMSTATUS_FSMSTATE_SUSPEND_Val 0x4ul /**< \brief (USB_FSMSTATUS) SUSPEND (L2) */ |
AnnaBridge | 171:3a7713b1edbc | 383 | #define USB_FSMSTATUS_FSMSTATE_SLEEP_Val 0x8ul /**< \brief (USB_FSMSTATUS) SLEEP (L1) */ |
AnnaBridge | 171:3a7713b1edbc | 384 | #define USB_FSMSTATUS_FSMSTATE_DNRESUME_Val 0x10ul /**< \brief (USB_FSMSTATUS) DNRESUME. Down Stream Resume. */ |
AnnaBridge | 171:3a7713b1edbc | 385 | #define USB_FSMSTATUS_FSMSTATE_UPRESUME_Val 0x20ul /**< \brief (USB_FSMSTATUS) UPRESUME. Up Stream Resume. */ |
AnnaBridge | 171:3a7713b1edbc | 386 | #define USB_FSMSTATUS_FSMSTATE_RESET_Val 0x40ul /**< \brief (USB_FSMSTATUS) RESET. USB lines Reset. */ |
AnnaBridge | 171:3a7713b1edbc | 387 | #define USB_FSMSTATUS_FSMSTATE_OFF (USB_FSMSTATUS_FSMSTATE_OFF_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 388 | #define USB_FSMSTATUS_FSMSTATE_ON (USB_FSMSTATUS_FSMSTATE_ON_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 389 | #define USB_FSMSTATUS_FSMSTATE_SUSPEND (USB_FSMSTATUS_FSMSTATE_SUSPEND_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 390 | #define USB_FSMSTATUS_FSMSTATE_SLEEP (USB_FSMSTATUS_FSMSTATE_SLEEP_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 391 | #define USB_FSMSTATUS_FSMSTATE_DNRESUME (USB_FSMSTATUS_FSMSTATE_DNRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 392 | #define USB_FSMSTATUS_FSMSTATE_UPRESUME (USB_FSMSTATUS_FSMSTATE_UPRESUME_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 393 | #define USB_FSMSTATUS_FSMSTATE_RESET (USB_FSMSTATUS_FSMSTATE_RESET_Val << USB_FSMSTATUS_FSMSTATE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 394 | #define USB_FSMSTATUS_MASK 0x3Ful /**< \brief (USB_FSMSTATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 395 | |
AnnaBridge | 171:3a7713b1edbc | 396 | /* -------- USB_DEVICE_FNUM : (USB Offset: 0x010) (R/ 16) DEVICE DEVICE Device Frame Number -------- */ |
AnnaBridge | 171:3a7713b1edbc | 397 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 398 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 399 | struct { |
AnnaBridge | 171:3a7713b1edbc | 400 | uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 401 | uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 402 | uint16_t :1; /*!< bit: 14 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 403 | uint16_t FNCERR:1; /*!< bit: 15 Frame Number CRC Error */ |
AnnaBridge | 171:3a7713b1edbc | 404 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 405 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 406 | } USB_DEVICE_FNUM_Type; |
AnnaBridge | 171:3a7713b1edbc | 407 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 408 | |
AnnaBridge | 171:3a7713b1edbc | 409 | #define USB_DEVICE_FNUM_OFFSET 0x010 /**< \brief (USB_DEVICE_FNUM offset) DEVICE Device Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 410 | #define USB_DEVICE_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_FNUM reset_value) DEVICE Device Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 411 | |
AnnaBridge | 171:3a7713b1edbc | 412 | #define USB_DEVICE_FNUM_MFNUM_Pos 0 /**< \brief (USB_DEVICE_FNUM) Micro Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 413 | #define USB_DEVICE_FNUM_MFNUM_Msk (0x7ul << USB_DEVICE_FNUM_MFNUM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 414 | #define USB_DEVICE_FNUM_MFNUM(value) ((USB_DEVICE_FNUM_MFNUM_Msk & ((value) << USB_DEVICE_FNUM_MFNUM_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 415 | #define USB_DEVICE_FNUM_FNUM_Pos 3 /**< \brief (USB_DEVICE_FNUM) Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 416 | #define USB_DEVICE_FNUM_FNUM_Msk (0x7FFul << USB_DEVICE_FNUM_FNUM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 417 | #define USB_DEVICE_FNUM_FNUM(value) ((USB_DEVICE_FNUM_FNUM_Msk & ((value) << USB_DEVICE_FNUM_FNUM_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 418 | #define USB_DEVICE_FNUM_FNCERR_Pos 15 /**< \brief (USB_DEVICE_FNUM) Frame Number CRC Error */ |
AnnaBridge | 171:3a7713b1edbc | 419 | #define USB_DEVICE_FNUM_FNCERR (0x1ul << USB_DEVICE_FNUM_FNCERR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 420 | #define USB_DEVICE_FNUM_MASK 0xBFFFul /**< \brief (USB_DEVICE_FNUM) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 421 | |
AnnaBridge | 171:3a7713b1edbc | 422 | /* -------- USB_HOST_FNUM : (USB Offset: 0x010) (R/W 16) HOST HOST Host Frame Number -------- */ |
AnnaBridge | 171:3a7713b1edbc | 423 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 424 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 425 | struct { |
AnnaBridge | 171:3a7713b1edbc | 426 | uint16_t MFNUM:3; /*!< bit: 0.. 2 Micro Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 427 | uint16_t FNUM:11; /*!< bit: 3..13 Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 428 | uint16_t :2; /*!< bit: 14..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 429 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 430 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 431 | } USB_HOST_FNUM_Type; |
AnnaBridge | 171:3a7713b1edbc | 432 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 433 | |
AnnaBridge | 171:3a7713b1edbc | 434 | #define USB_HOST_FNUM_OFFSET 0x010 /**< \brief (USB_HOST_FNUM offset) HOST Host Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 435 | #define USB_HOST_FNUM_RESETVALUE 0x0000ul /**< \brief (USB_HOST_FNUM reset_value) HOST Host Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 436 | |
AnnaBridge | 171:3a7713b1edbc | 437 | #define USB_HOST_FNUM_MFNUM_Pos 0 /**< \brief (USB_HOST_FNUM) Micro Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 438 | #define USB_HOST_FNUM_MFNUM_Msk (0x7ul << USB_HOST_FNUM_MFNUM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 439 | #define USB_HOST_FNUM_MFNUM(value) ((USB_HOST_FNUM_MFNUM_Msk & ((value) << USB_HOST_FNUM_MFNUM_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 440 | #define USB_HOST_FNUM_FNUM_Pos 3 /**< \brief (USB_HOST_FNUM) Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 441 | #define USB_HOST_FNUM_FNUM_Msk (0x7FFul << USB_HOST_FNUM_FNUM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 442 | #define USB_HOST_FNUM_FNUM(value) ((USB_HOST_FNUM_FNUM_Msk & ((value) << USB_HOST_FNUM_FNUM_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 443 | #define USB_HOST_FNUM_MASK 0x3FFFul /**< \brief (USB_HOST_FNUM) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 444 | |
AnnaBridge | 171:3a7713b1edbc | 445 | /* -------- USB_HOST_FLENHIGH : (USB Offset: 0x012) (R/ 8) HOST HOST Host Frame Length -------- */ |
AnnaBridge | 171:3a7713b1edbc | 446 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 447 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 448 | struct { |
AnnaBridge | 171:3a7713b1edbc | 449 | uint8_t FLENHIGH:8; /*!< bit: 0.. 7 Frame Length */ |
AnnaBridge | 171:3a7713b1edbc | 450 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 451 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 452 | } USB_HOST_FLENHIGH_Type; |
AnnaBridge | 171:3a7713b1edbc | 453 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 454 | |
AnnaBridge | 171:3a7713b1edbc | 455 | #define USB_HOST_FLENHIGH_OFFSET 0x012 /**< \brief (USB_HOST_FLENHIGH offset) HOST Host Frame Length */ |
AnnaBridge | 171:3a7713b1edbc | 456 | #define USB_HOST_FLENHIGH_RESETVALUE 0x00ul /**< \brief (USB_HOST_FLENHIGH reset_value) HOST Host Frame Length */ |
AnnaBridge | 171:3a7713b1edbc | 457 | |
AnnaBridge | 171:3a7713b1edbc | 458 | #define USB_HOST_FLENHIGH_FLENHIGH_Pos 0 /**< \brief (USB_HOST_FLENHIGH) Frame Length */ |
AnnaBridge | 171:3a7713b1edbc | 459 | #define USB_HOST_FLENHIGH_FLENHIGH_Msk (0xFFul << USB_HOST_FLENHIGH_FLENHIGH_Pos) |
AnnaBridge | 171:3a7713b1edbc | 460 | #define USB_HOST_FLENHIGH_FLENHIGH(value) ((USB_HOST_FLENHIGH_FLENHIGH_Msk & ((value) << USB_HOST_FLENHIGH_FLENHIGH_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 461 | #define USB_HOST_FLENHIGH_MASK 0xFFul /**< \brief (USB_HOST_FLENHIGH) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 462 | |
AnnaBridge | 171:3a7713b1edbc | 463 | /* -------- USB_DEVICE_INTENCLR : (USB Offset: 0x014) (R/W 16) DEVICE DEVICE Device Interrupt Enable Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 464 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 465 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 466 | struct { |
AnnaBridge | 171:3a7713b1edbc | 467 | uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 468 | uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ |
AnnaBridge | 171:3a7713b1edbc | 469 | uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 470 | uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 471 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 472 | uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 473 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 474 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 475 | uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 476 | uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 477 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 478 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 479 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 480 | } USB_DEVICE_INTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 481 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 482 | |
AnnaBridge | 171:3a7713b1edbc | 483 | #define USB_DEVICE_INTENCLR_OFFSET 0x014 /**< \brief (USB_DEVICE_INTENCLR offset) DEVICE Device Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 484 | #define USB_DEVICE_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENCLR reset_value) DEVICE Device Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 485 | |
AnnaBridge | 171:3a7713b1edbc | 486 | #define USB_DEVICE_INTENCLR_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENCLR) Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 487 | #define USB_DEVICE_INTENCLR_SUSPEND (0x1ul << USB_DEVICE_INTENCLR_SUSPEND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 488 | #define USB_DEVICE_INTENCLR_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENCLR) Micro Start of Frame Interrupt Enable in High Speed Mode */ |
AnnaBridge | 171:3a7713b1edbc | 489 | #define USB_DEVICE_INTENCLR_MSOF (0x1ul << USB_DEVICE_INTENCLR_MSOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 490 | #define USB_DEVICE_INTENCLR_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENCLR) Start Of Frame Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 491 | #define USB_DEVICE_INTENCLR_SOF (0x1ul << USB_DEVICE_INTENCLR_SOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 492 | #define USB_DEVICE_INTENCLR_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENCLR) End of Reset Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 493 | #define USB_DEVICE_INTENCLR_EORST (0x1ul << USB_DEVICE_INTENCLR_EORST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 494 | #define USB_DEVICE_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENCLR) Wake Up Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 495 | #define USB_DEVICE_INTENCLR_WAKEUP (0x1ul << USB_DEVICE_INTENCLR_WAKEUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 496 | #define USB_DEVICE_INTENCLR_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENCLR) End Of Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 497 | #define USB_DEVICE_INTENCLR_EORSM (0x1ul << USB_DEVICE_INTENCLR_EORSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 498 | #define USB_DEVICE_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENCLR) Upstream Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 499 | #define USB_DEVICE_INTENCLR_UPRSM (0x1ul << USB_DEVICE_INTENCLR_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 500 | #define USB_DEVICE_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENCLR) Ram Access Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 501 | #define USB_DEVICE_INTENCLR_RAMACER (0x1ul << USB_DEVICE_INTENCLR_RAMACER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 502 | #define USB_DEVICE_INTENCLR_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Not Yet Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 503 | #define USB_DEVICE_INTENCLR_LPMNYET (0x1ul << USB_DEVICE_INTENCLR_LPMNYET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 504 | #define USB_DEVICE_INTENCLR_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENCLR) Link Power Management Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 505 | #define USB_DEVICE_INTENCLR_LPMSUSP (0x1ul << USB_DEVICE_INTENCLR_LPMSUSP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 506 | #define USB_DEVICE_INTENCLR_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 507 | |
AnnaBridge | 171:3a7713b1edbc | 508 | /* -------- USB_HOST_INTENCLR : (USB Offset: 0x014) (R/W 16) HOST HOST Host Interrupt Enable Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 509 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 510 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 511 | struct { |
AnnaBridge | 171:3a7713b1edbc | 512 | uint16_t :2; /*!< bit: 0.. 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 513 | uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 514 | uint16_t RST:1; /*!< bit: 3 BUS Reset Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 515 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 516 | uint16_t DNRSM:1; /*!< bit: 5 DownStream to Device Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 517 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from Device Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 518 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 519 | uint16_t DCONN:1; /*!< bit: 8 Device Connection Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 520 | uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 521 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 522 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 523 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 524 | } USB_HOST_INTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 525 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 526 | |
AnnaBridge | 171:3a7713b1edbc | 527 | #define USB_HOST_INTENCLR_OFFSET 0x014 /**< \brief (USB_HOST_INTENCLR offset) HOST Host Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 528 | #define USB_HOST_INTENCLR_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENCLR reset_value) HOST Host Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 529 | |
AnnaBridge | 171:3a7713b1edbc | 530 | #define USB_HOST_INTENCLR_HSOF_Pos 2 /**< \brief (USB_HOST_INTENCLR) Host Start Of Frame Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 531 | #define USB_HOST_INTENCLR_HSOF (0x1ul << USB_HOST_INTENCLR_HSOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 532 | #define USB_HOST_INTENCLR_RST_Pos 3 /**< \brief (USB_HOST_INTENCLR) BUS Reset Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 533 | #define USB_HOST_INTENCLR_RST (0x1ul << USB_HOST_INTENCLR_RST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 534 | #define USB_HOST_INTENCLR_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENCLR) Wake Up Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 535 | #define USB_HOST_INTENCLR_WAKEUP (0x1ul << USB_HOST_INTENCLR_WAKEUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 536 | #define USB_HOST_INTENCLR_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENCLR) DownStream to Device Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 537 | #define USB_HOST_INTENCLR_DNRSM (0x1ul << USB_HOST_INTENCLR_DNRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 538 | #define USB_HOST_INTENCLR_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENCLR) Upstream Resume from Device Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 539 | #define USB_HOST_INTENCLR_UPRSM (0x1ul << USB_HOST_INTENCLR_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 540 | #define USB_HOST_INTENCLR_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENCLR) Ram Access Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 541 | #define USB_HOST_INTENCLR_RAMACER (0x1ul << USB_HOST_INTENCLR_RAMACER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 542 | #define USB_HOST_INTENCLR_DCONN_Pos 8 /**< \brief (USB_HOST_INTENCLR) Device Connection Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 543 | #define USB_HOST_INTENCLR_DCONN (0x1ul << USB_HOST_INTENCLR_DCONN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 544 | #define USB_HOST_INTENCLR_DDISC_Pos 9 /**< \brief (USB_HOST_INTENCLR) Device Disconnection Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 545 | #define USB_HOST_INTENCLR_DDISC (0x1ul << USB_HOST_INTENCLR_DDISC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 546 | #define USB_HOST_INTENCLR_MASK 0x03FCul /**< \brief (USB_HOST_INTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 547 | |
AnnaBridge | 171:3a7713b1edbc | 548 | /* -------- USB_DEVICE_INTENSET : (USB Offset: 0x018) (R/W 16) DEVICE DEVICE Device Interrupt Enable Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 549 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 550 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 551 | struct { |
AnnaBridge | 171:3a7713b1edbc | 552 | uint16_t SUSPEND:1; /*!< bit: 0 Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 553 | uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame Interrupt Enable in High Speed Mode */ |
AnnaBridge | 171:3a7713b1edbc | 554 | uint16_t SOF:1; /*!< bit: 2 Start Of Frame Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 555 | uint16_t EORST:1; /*!< bit: 3 End of Reset Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 556 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 557 | uint16_t EORSM:1; /*!< bit: 5 End Of Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 558 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 559 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 560 | uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 561 | uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 562 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 563 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 564 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 565 | } USB_DEVICE_INTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 566 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 567 | |
AnnaBridge | 171:3a7713b1edbc | 568 | #define USB_DEVICE_INTENSET_OFFSET 0x018 /**< \brief (USB_DEVICE_INTENSET offset) DEVICE Device Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 569 | #define USB_DEVICE_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTENSET reset_value) DEVICE Device Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 570 | |
AnnaBridge | 171:3a7713b1edbc | 571 | #define USB_DEVICE_INTENSET_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTENSET) Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 572 | #define USB_DEVICE_INTENSET_SUSPEND (0x1ul << USB_DEVICE_INTENSET_SUSPEND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 573 | #define USB_DEVICE_INTENSET_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTENSET) Micro Start of Frame Interrupt Enable in High Speed Mode */ |
AnnaBridge | 171:3a7713b1edbc | 574 | #define USB_DEVICE_INTENSET_MSOF (0x1ul << USB_DEVICE_INTENSET_MSOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 575 | #define USB_DEVICE_INTENSET_SOF_Pos 2 /**< \brief (USB_DEVICE_INTENSET) Start Of Frame Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 576 | #define USB_DEVICE_INTENSET_SOF (0x1ul << USB_DEVICE_INTENSET_SOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 577 | #define USB_DEVICE_INTENSET_EORST_Pos 3 /**< \brief (USB_DEVICE_INTENSET) End of Reset Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 578 | #define USB_DEVICE_INTENSET_EORST (0x1ul << USB_DEVICE_INTENSET_EORST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 579 | #define USB_DEVICE_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTENSET) Wake Up Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 580 | #define USB_DEVICE_INTENSET_WAKEUP (0x1ul << USB_DEVICE_INTENSET_WAKEUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 581 | #define USB_DEVICE_INTENSET_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTENSET) End Of Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 582 | #define USB_DEVICE_INTENSET_EORSM (0x1ul << USB_DEVICE_INTENSET_EORSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 583 | #define USB_DEVICE_INTENSET_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTENSET) Upstream Resume Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 584 | #define USB_DEVICE_INTENSET_UPRSM (0x1ul << USB_DEVICE_INTENSET_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 585 | #define USB_DEVICE_INTENSET_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTENSET) Ram Access Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 586 | #define USB_DEVICE_INTENSET_RAMACER (0x1ul << USB_DEVICE_INTENSET_RAMACER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 587 | #define USB_DEVICE_INTENSET_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Not Yet Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 588 | #define USB_DEVICE_INTENSET_LPMNYET (0x1ul << USB_DEVICE_INTENSET_LPMNYET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 589 | #define USB_DEVICE_INTENSET_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTENSET) Link Power Management Suspend Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 590 | #define USB_DEVICE_INTENSET_LPMSUSP (0x1ul << USB_DEVICE_INTENSET_LPMSUSP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 591 | #define USB_DEVICE_INTENSET_MASK 0x03FFul /**< \brief (USB_DEVICE_INTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 592 | |
AnnaBridge | 171:3a7713b1edbc | 593 | /* -------- USB_HOST_INTENSET : (USB Offset: 0x018) (R/W 16) HOST HOST Host Interrupt Enable Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 594 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 595 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 596 | struct { |
AnnaBridge | 171:3a7713b1edbc | 597 | uint16_t :2; /*!< bit: 0.. 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 598 | uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 599 | uint16_t RST:1; /*!< bit: 3 Bus Reset Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 600 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 601 | uint16_t DNRSM:1; /*!< bit: 5 DownStream to the Device Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 602 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume fromthe device Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 603 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 604 | uint16_t DCONN:1; /*!< bit: 8 Link Power Management Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 605 | uint16_t DDISC:1; /*!< bit: 9 Device Disconnection Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 606 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 607 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 608 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 609 | } USB_HOST_INTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 610 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 611 | |
AnnaBridge | 171:3a7713b1edbc | 612 | #define USB_HOST_INTENSET_OFFSET 0x018 /**< \brief (USB_HOST_INTENSET offset) HOST Host Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 613 | #define USB_HOST_INTENSET_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTENSET reset_value) HOST Host Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 614 | |
AnnaBridge | 171:3a7713b1edbc | 615 | #define USB_HOST_INTENSET_HSOF_Pos 2 /**< \brief (USB_HOST_INTENSET) Host Start Of Frame Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 616 | #define USB_HOST_INTENSET_HSOF (0x1ul << USB_HOST_INTENSET_HSOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 617 | #define USB_HOST_INTENSET_RST_Pos 3 /**< \brief (USB_HOST_INTENSET) Bus Reset Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 618 | #define USB_HOST_INTENSET_RST (0x1ul << USB_HOST_INTENSET_RST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 619 | #define USB_HOST_INTENSET_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTENSET) Wake Up Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 620 | #define USB_HOST_INTENSET_WAKEUP (0x1ul << USB_HOST_INTENSET_WAKEUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 621 | #define USB_HOST_INTENSET_DNRSM_Pos 5 /**< \brief (USB_HOST_INTENSET) DownStream to the Device Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 622 | #define USB_HOST_INTENSET_DNRSM (0x1ul << USB_HOST_INTENSET_DNRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 623 | #define USB_HOST_INTENSET_UPRSM_Pos 6 /**< \brief (USB_HOST_INTENSET) Upstream Resume fromthe device Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 624 | #define USB_HOST_INTENSET_UPRSM (0x1ul << USB_HOST_INTENSET_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 625 | #define USB_HOST_INTENSET_RAMACER_Pos 7 /**< \brief (USB_HOST_INTENSET) Ram Access Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 626 | #define USB_HOST_INTENSET_RAMACER (0x1ul << USB_HOST_INTENSET_RAMACER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 627 | #define USB_HOST_INTENSET_DCONN_Pos 8 /**< \brief (USB_HOST_INTENSET) Link Power Management Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 628 | #define USB_HOST_INTENSET_DCONN (0x1ul << USB_HOST_INTENSET_DCONN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 629 | #define USB_HOST_INTENSET_DDISC_Pos 9 /**< \brief (USB_HOST_INTENSET) Device Disconnection Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 630 | #define USB_HOST_INTENSET_DDISC (0x1ul << USB_HOST_INTENSET_DDISC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 631 | #define USB_HOST_INTENSET_MASK 0x03FCul /**< \brief (USB_HOST_INTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 632 | |
AnnaBridge | 171:3a7713b1edbc | 633 | /* -------- USB_DEVICE_INTFLAG : (USB Offset: 0x01C) (R/W 16) DEVICE DEVICE Device Interrupt Flag -------- */ |
AnnaBridge | 171:3a7713b1edbc | 634 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 635 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 636 | struct { |
AnnaBridge | 171:3a7713b1edbc | 637 | uint16_t SUSPEND:1; /*!< bit: 0 Suspend */ |
AnnaBridge | 171:3a7713b1edbc | 638 | uint16_t MSOF:1; /*!< bit: 1 Micro Start of Frame in High Speed Mode */ |
AnnaBridge | 171:3a7713b1edbc | 639 | uint16_t SOF:1; /*!< bit: 2 Start Of Frame */ |
AnnaBridge | 171:3a7713b1edbc | 640 | uint16_t EORST:1; /*!< bit: 3 End of Reset */ |
AnnaBridge | 171:3a7713b1edbc | 641 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ |
AnnaBridge | 171:3a7713b1edbc | 642 | uint16_t EORSM:1; /*!< bit: 5 End Of Resume */ |
AnnaBridge | 171:3a7713b1edbc | 643 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume */ |
AnnaBridge | 171:3a7713b1edbc | 644 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ |
AnnaBridge | 171:3a7713b1edbc | 645 | uint16_t LPMNYET:1; /*!< bit: 8 Link Power Management Not Yet */ |
AnnaBridge | 171:3a7713b1edbc | 646 | uint16_t LPMSUSP:1; /*!< bit: 9 Link Power Management Suspend */ |
AnnaBridge | 171:3a7713b1edbc | 647 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 648 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 649 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 650 | } USB_DEVICE_INTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 651 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 652 | |
AnnaBridge | 171:3a7713b1edbc | 653 | #define USB_DEVICE_INTFLAG_OFFSET 0x01C /**< \brief (USB_DEVICE_INTFLAG offset) DEVICE Device Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 654 | #define USB_DEVICE_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_INTFLAG reset_value) DEVICE Device Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 655 | |
AnnaBridge | 171:3a7713b1edbc | 656 | #define USB_DEVICE_INTFLAG_SUSPEND_Pos 0 /**< \brief (USB_DEVICE_INTFLAG) Suspend */ |
AnnaBridge | 171:3a7713b1edbc | 657 | #define USB_DEVICE_INTFLAG_SUSPEND (0x1ul << USB_DEVICE_INTFLAG_SUSPEND_Pos) |
AnnaBridge | 171:3a7713b1edbc | 658 | #define USB_DEVICE_INTFLAG_MSOF_Pos 1 /**< \brief (USB_DEVICE_INTFLAG) Micro Start of Frame in High Speed Mode */ |
AnnaBridge | 171:3a7713b1edbc | 659 | #define USB_DEVICE_INTFLAG_MSOF (0x1ul << USB_DEVICE_INTFLAG_MSOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 660 | #define USB_DEVICE_INTFLAG_SOF_Pos 2 /**< \brief (USB_DEVICE_INTFLAG) Start Of Frame */ |
AnnaBridge | 171:3a7713b1edbc | 661 | #define USB_DEVICE_INTFLAG_SOF (0x1ul << USB_DEVICE_INTFLAG_SOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 662 | #define USB_DEVICE_INTFLAG_EORST_Pos 3 /**< \brief (USB_DEVICE_INTFLAG) End of Reset */ |
AnnaBridge | 171:3a7713b1edbc | 663 | #define USB_DEVICE_INTFLAG_EORST (0x1ul << USB_DEVICE_INTFLAG_EORST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 664 | #define USB_DEVICE_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_DEVICE_INTFLAG) Wake Up */ |
AnnaBridge | 171:3a7713b1edbc | 665 | #define USB_DEVICE_INTFLAG_WAKEUP (0x1ul << USB_DEVICE_INTFLAG_WAKEUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 666 | #define USB_DEVICE_INTFLAG_EORSM_Pos 5 /**< \brief (USB_DEVICE_INTFLAG) End Of Resume */ |
AnnaBridge | 171:3a7713b1edbc | 667 | #define USB_DEVICE_INTFLAG_EORSM (0x1ul << USB_DEVICE_INTFLAG_EORSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 668 | #define USB_DEVICE_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_DEVICE_INTFLAG) Upstream Resume */ |
AnnaBridge | 171:3a7713b1edbc | 669 | #define USB_DEVICE_INTFLAG_UPRSM (0x1ul << USB_DEVICE_INTFLAG_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 670 | #define USB_DEVICE_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_DEVICE_INTFLAG) Ram Access */ |
AnnaBridge | 171:3a7713b1edbc | 671 | #define USB_DEVICE_INTFLAG_RAMACER (0x1ul << USB_DEVICE_INTFLAG_RAMACER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 672 | #define USB_DEVICE_INTFLAG_LPMNYET_Pos 8 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Not Yet */ |
AnnaBridge | 171:3a7713b1edbc | 673 | #define USB_DEVICE_INTFLAG_LPMNYET (0x1ul << USB_DEVICE_INTFLAG_LPMNYET_Pos) |
AnnaBridge | 171:3a7713b1edbc | 674 | #define USB_DEVICE_INTFLAG_LPMSUSP_Pos 9 /**< \brief (USB_DEVICE_INTFLAG) Link Power Management Suspend */ |
AnnaBridge | 171:3a7713b1edbc | 675 | #define USB_DEVICE_INTFLAG_LPMSUSP (0x1ul << USB_DEVICE_INTFLAG_LPMSUSP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 676 | #define USB_DEVICE_INTFLAG_MASK 0x03FFul /**< \brief (USB_DEVICE_INTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 677 | |
AnnaBridge | 171:3a7713b1edbc | 678 | /* -------- USB_HOST_INTFLAG : (USB Offset: 0x01C) (R/W 16) HOST HOST Host Interrupt Flag -------- */ |
AnnaBridge | 171:3a7713b1edbc | 679 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 680 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 681 | struct { |
AnnaBridge | 171:3a7713b1edbc | 682 | uint16_t :2; /*!< bit: 0.. 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 683 | uint16_t HSOF:1; /*!< bit: 2 Host Start Of Frame */ |
AnnaBridge | 171:3a7713b1edbc | 684 | uint16_t RST:1; /*!< bit: 3 Bus Reset */ |
AnnaBridge | 171:3a7713b1edbc | 685 | uint16_t WAKEUP:1; /*!< bit: 4 Wake Up */ |
AnnaBridge | 171:3a7713b1edbc | 686 | uint16_t DNRSM:1; /*!< bit: 5 Downstream */ |
AnnaBridge | 171:3a7713b1edbc | 687 | uint16_t UPRSM:1; /*!< bit: 6 Upstream Resume from the Device */ |
AnnaBridge | 171:3a7713b1edbc | 688 | uint16_t RAMACER:1; /*!< bit: 7 Ram Access */ |
AnnaBridge | 171:3a7713b1edbc | 689 | uint16_t DCONN:1; /*!< bit: 8 Device Connection */ |
AnnaBridge | 171:3a7713b1edbc | 690 | uint16_t DDISC:1; /*!< bit: 9 Device Disconnection */ |
AnnaBridge | 171:3a7713b1edbc | 691 | uint16_t :6; /*!< bit: 10..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 692 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 693 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 694 | } USB_HOST_INTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 695 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 696 | |
AnnaBridge | 171:3a7713b1edbc | 697 | #define USB_HOST_INTFLAG_OFFSET 0x01C /**< \brief (USB_HOST_INTFLAG offset) HOST Host Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 698 | #define USB_HOST_INTFLAG_RESETVALUE 0x0000ul /**< \brief (USB_HOST_INTFLAG reset_value) HOST Host Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 699 | |
AnnaBridge | 171:3a7713b1edbc | 700 | #define USB_HOST_INTFLAG_HSOF_Pos 2 /**< \brief (USB_HOST_INTFLAG) Host Start Of Frame */ |
AnnaBridge | 171:3a7713b1edbc | 701 | #define USB_HOST_INTFLAG_HSOF (0x1ul << USB_HOST_INTFLAG_HSOF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 702 | #define USB_HOST_INTFLAG_RST_Pos 3 /**< \brief (USB_HOST_INTFLAG) Bus Reset */ |
AnnaBridge | 171:3a7713b1edbc | 703 | #define USB_HOST_INTFLAG_RST (0x1ul << USB_HOST_INTFLAG_RST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 704 | #define USB_HOST_INTFLAG_WAKEUP_Pos 4 /**< \brief (USB_HOST_INTFLAG) Wake Up */ |
AnnaBridge | 171:3a7713b1edbc | 705 | #define USB_HOST_INTFLAG_WAKEUP (0x1ul << USB_HOST_INTFLAG_WAKEUP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 706 | #define USB_HOST_INTFLAG_DNRSM_Pos 5 /**< \brief (USB_HOST_INTFLAG) Downstream */ |
AnnaBridge | 171:3a7713b1edbc | 707 | #define USB_HOST_INTFLAG_DNRSM (0x1ul << USB_HOST_INTFLAG_DNRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 708 | #define USB_HOST_INTFLAG_UPRSM_Pos 6 /**< \brief (USB_HOST_INTFLAG) Upstream Resume from the Device */ |
AnnaBridge | 171:3a7713b1edbc | 709 | #define USB_HOST_INTFLAG_UPRSM (0x1ul << USB_HOST_INTFLAG_UPRSM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 710 | #define USB_HOST_INTFLAG_RAMACER_Pos 7 /**< \brief (USB_HOST_INTFLAG) Ram Access */ |
AnnaBridge | 171:3a7713b1edbc | 711 | #define USB_HOST_INTFLAG_RAMACER (0x1ul << USB_HOST_INTFLAG_RAMACER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 712 | #define USB_HOST_INTFLAG_DCONN_Pos 8 /**< \brief (USB_HOST_INTFLAG) Device Connection */ |
AnnaBridge | 171:3a7713b1edbc | 713 | #define USB_HOST_INTFLAG_DCONN (0x1ul << USB_HOST_INTFLAG_DCONN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 714 | #define USB_HOST_INTFLAG_DDISC_Pos 9 /**< \brief (USB_HOST_INTFLAG) Device Disconnection */ |
AnnaBridge | 171:3a7713b1edbc | 715 | #define USB_HOST_INTFLAG_DDISC (0x1ul << USB_HOST_INTFLAG_DDISC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 716 | #define USB_HOST_INTFLAG_MASK 0x03FCul /**< \brief (USB_HOST_INTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 717 | |
AnnaBridge | 171:3a7713b1edbc | 718 | /* -------- USB_DEVICE_EPINTSMRY : (USB Offset: 0x020) (R/ 16) DEVICE DEVICE End Point Interrupt Summary -------- */ |
AnnaBridge | 171:3a7713b1edbc | 719 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 720 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 721 | struct { |
AnnaBridge | 171:3a7713b1edbc | 722 | uint16_t EPINT0:1; /*!< bit: 0 End Point 0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 723 | uint16_t EPINT1:1; /*!< bit: 1 End Point 1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 724 | uint16_t EPINT2:1; /*!< bit: 2 End Point 2 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 725 | uint16_t EPINT3:1; /*!< bit: 3 End Point 3 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 726 | uint16_t EPINT4:1; /*!< bit: 4 End Point 4 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 727 | uint16_t EPINT5:1; /*!< bit: 5 End Point 5 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 728 | uint16_t EPINT6:1; /*!< bit: 6 End Point 6 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 729 | uint16_t EPINT7:1; /*!< bit: 7 End Point 7 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 730 | uint16_t :8; /*!< bit: 8..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 731 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 732 | struct { |
AnnaBridge | 171:3a7713b1edbc | 733 | uint16_t EPINT:8; /*!< bit: 0.. 7 End Point x Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 734 | uint16_t :8; /*!< bit: 8..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 735 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 736 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 737 | } USB_DEVICE_EPINTSMRY_Type; |
AnnaBridge | 171:3a7713b1edbc | 738 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 739 | |
AnnaBridge | 171:3a7713b1edbc | 740 | #define USB_DEVICE_EPINTSMRY_OFFSET 0x020 /**< \brief (USB_DEVICE_EPINTSMRY offset) DEVICE End Point Interrupt Summary */ |
AnnaBridge | 171:3a7713b1edbc | 741 | #define USB_DEVICE_EPINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_DEVICE_EPINTSMRY reset_value) DEVICE End Point Interrupt Summary */ |
AnnaBridge | 171:3a7713b1edbc | 742 | |
AnnaBridge | 171:3a7713b1edbc | 743 | #define USB_DEVICE_EPINTSMRY_EPINT0_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 744 | #define USB_DEVICE_EPINTSMRY_EPINT0 (1 << USB_DEVICE_EPINTSMRY_EPINT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 745 | #define USB_DEVICE_EPINTSMRY_EPINT1_Pos 1 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 746 | #define USB_DEVICE_EPINTSMRY_EPINT1 (1 << USB_DEVICE_EPINTSMRY_EPINT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 747 | #define USB_DEVICE_EPINTSMRY_EPINT2_Pos 2 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 2 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 748 | #define USB_DEVICE_EPINTSMRY_EPINT2 (1 << USB_DEVICE_EPINTSMRY_EPINT2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 749 | #define USB_DEVICE_EPINTSMRY_EPINT3_Pos 3 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 3 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 750 | #define USB_DEVICE_EPINTSMRY_EPINT3 (1 << USB_DEVICE_EPINTSMRY_EPINT3_Pos) |
AnnaBridge | 171:3a7713b1edbc | 751 | #define USB_DEVICE_EPINTSMRY_EPINT4_Pos 4 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 4 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 752 | #define USB_DEVICE_EPINTSMRY_EPINT4 (1 << USB_DEVICE_EPINTSMRY_EPINT4_Pos) |
AnnaBridge | 171:3a7713b1edbc | 753 | #define USB_DEVICE_EPINTSMRY_EPINT5_Pos 5 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 5 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 754 | #define USB_DEVICE_EPINTSMRY_EPINT5 (1 << USB_DEVICE_EPINTSMRY_EPINT5_Pos) |
AnnaBridge | 171:3a7713b1edbc | 755 | #define USB_DEVICE_EPINTSMRY_EPINT6_Pos 6 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 6 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 756 | #define USB_DEVICE_EPINTSMRY_EPINT6 (1 << USB_DEVICE_EPINTSMRY_EPINT6_Pos) |
AnnaBridge | 171:3a7713b1edbc | 757 | #define USB_DEVICE_EPINTSMRY_EPINT7_Pos 7 /**< \brief (USB_DEVICE_EPINTSMRY) End Point 7 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 758 | #define USB_DEVICE_EPINTSMRY_EPINT7 (1 << USB_DEVICE_EPINTSMRY_EPINT7_Pos) |
AnnaBridge | 171:3a7713b1edbc | 759 | #define USB_DEVICE_EPINTSMRY_EPINT_Pos 0 /**< \brief (USB_DEVICE_EPINTSMRY) End Point x Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 760 | #define USB_DEVICE_EPINTSMRY_EPINT_Msk (0xFFul << USB_DEVICE_EPINTSMRY_EPINT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 761 | #define USB_DEVICE_EPINTSMRY_EPINT(value) ((USB_DEVICE_EPINTSMRY_EPINT_Msk & ((value) << USB_DEVICE_EPINTSMRY_EPINT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 762 | #define USB_DEVICE_EPINTSMRY_MASK 0x00FFul /**< \brief (USB_DEVICE_EPINTSMRY) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 763 | |
AnnaBridge | 171:3a7713b1edbc | 764 | /* -------- USB_HOST_PINTSMRY : (USB Offset: 0x020) (R/ 16) HOST HOST Pipe Interrupt Summary -------- */ |
AnnaBridge | 171:3a7713b1edbc | 765 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 766 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 767 | struct { |
AnnaBridge | 171:3a7713b1edbc | 768 | uint16_t EPINT0:1; /*!< bit: 0 Pipe 0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 769 | uint16_t EPINT1:1; /*!< bit: 1 Pipe 1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 770 | uint16_t EPINT2:1; /*!< bit: 2 Pipe 2 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 771 | uint16_t EPINT3:1; /*!< bit: 3 Pipe 3 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 772 | uint16_t EPINT4:1; /*!< bit: 4 Pipe 4 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 773 | uint16_t EPINT5:1; /*!< bit: 5 Pipe 5 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 774 | uint16_t EPINT6:1; /*!< bit: 6 Pipe 6 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 775 | uint16_t EPINT7:1; /*!< bit: 7 Pipe 7 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 776 | uint16_t :8; /*!< bit: 8..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 777 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 778 | struct { |
AnnaBridge | 171:3a7713b1edbc | 779 | uint16_t EPINT:8; /*!< bit: 0.. 7 Pipe x Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 780 | uint16_t :8; /*!< bit: 8..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 781 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 782 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 783 | } USB_HOST_PINTSMRY_Type; |
AnnaBridge | 171:3a7713b1edbc | 784 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 785 | |
AnnaBridge | 171:3a7713b1edbc | 786 | #define USB_HOST_PINTSMRY_OFFSET 0x020 /**< \brief (USB_HOST_PINTSMRY offset) HOST Pipe Interrupt Summary */ |
AnnaBridge | 171:3a7713b1edbc | 787 | #define USB_HOST_PINTSMRY_RESETVALUE 0x0000ul /**< \brief (USB_HOST_PINTSMRY reset_value) HOST Pipe Interrupt Summary */ |
AnnaBridge | 171:3a7713b1edbc | 788 | |
AnnaBridge | 171:3a7713b1edbc | 789 | #define USB_HOST_PINTSMRY_EPINT0_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe 0 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 790 | #define USB_HOST_PINTSMRY_EPINT0 (1 << USB_HOST_PINTSMRY_EPINT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 791 | #define USB_HOST_PINTSMRY_EPINT1_Pos 1 /**< \brief (USB_HOST_PINTSMRY) Pipe 1 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 792 | #define USB_HOST_PINTSMRY_EPINT1 (1 << USB_HOST_PINTSMRY_EPINT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 793 | #define USB_HOST_PINTSMRY_EPINT2_Pos 2 /**< \brief (USB_HOST_PINTSMRY) Pipe 2 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 794 | #define USB_HOST_PINTSMRY_EPINT2 (1 << USB_HOST_PINTSMRY_EPINT2_Pos) |
AnnaBridge | 171:3a7713b1edbc | 795 | #define USB_HOST_PINTSMRY_EPINT3_Pos 3 /**< \brief (USB_HOST_PINTSMRY) Pipe 3 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 796 | #define USB_HOST_PINTSMRY_EPINT3 (1 << USB_HOST_PINTSMRY_EPINT3_Pos) |
AnnaBridge | 171:3a7713b1edbc | 797 | #define USB_HOST_PINTSMRY_EPINT4_Pos 4 /**< \brief (USB_HOST_PINTSMRY) Pipe 4 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 798 | #define USB_HOST_PINTSMRY_EPINT4 (1 << USB_HOST_PINTSMRY_EPINT4_Pos) |
AnnaBridge | 171:3a7713b1edbc | 799 | #define USB_HOST_PINTSMRY_EPINT5_Pos 5 /**< \brief (USB_HOST_PINTSMRY) Pipe 5 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 800 | #define USB_HOST_PINTSMRY_EPINT5 (1 << USB_HOST_PINTSMRY_EPINT5_Pos) |
AnnaBridge | 171:3a7713b1edbc | 801 | #define USB_HOST_PINTSMRY_EPINT6_Pos 6 /**< \brief (USB_HOST_PINTSMRY) Pipe 6 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 802 | #define USB_HOST_PINTSMRY_EPINT6 (1 << USB_HOST_PINTSMRY_EPINT6_Pos) |
AnnaBridge | 171:3a7713b1edbc | 803 | #define USB_HOST_PINTSMRY_EPINT7_Pos 7 /**< \brief (USB_HOST_PINTSMRY) Pipe 7 Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 804 | #define USB_HOST_PINTSMRY_EPINT7 (1 << USB_HOST_PINTSMRY_EPINT7_Pos) |
AnnaBridge | 171:3a7713b1edbc | 805 | #define USB_HOST_PINTSMRY_EPINT_Pos 0 /**< \brief (USB_HOST_PINTSMRY) Pipe x Interrupt */ |
AnnaBridge | 171:3a7713b1edbc | 806 | #define USB_HOST_PINTSMRY_EPINT_Msk (0xFFul << USB_HOST_PINTSMRY_EPINT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 807 | #define USB_HOST_PINTSMRY_EPINT(value) ((USB_HOST_PINTSMRY_EPINT_Msk & ((value) << USB_HOST_PINTSMRY_EPINT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 808 | #define USB_HOST_PINTSMRY_MASK 0x00FFul /**< \brief (USB_HOST_PINTSMRY) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 809 | |
AnnaBridge | 171:3a7713b1edbc | 810 | /* -------- USB_DESCADD : (USB Offset: 0x024) (R/W 32) Descriptor Address -------- */ |
AnnaBridge | 171:3a7713b1edbc | 811 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 812 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 813 | struct { |
AnnaBridge | 171:3a7713b1edbc | 814 | uint32_t DESCADD:32; /*!< bit: 0..31 Descriptor Address Value */ |
AnnaBridge | 171:3a7713b1edbc | 815 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 816 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 817 | } USB_DESCADD_Type; |
AnnaBridge | 171:3a7713b1edbc | 818 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 819 | |
AnnaBridge | 171:3a7713b1edbc | 820 | #define USB_DESCADD_OFFSET 0x024 /**< \brief (USB_DESCADD offset) Descriptor Address */ |
AnnaBridge | 171:3a7713b1edbc | 821 | #define USB_DESCADD_RESETVALUE 0x00000000ul /**< \brief (USB_DESCADD reset_value) Descriptor Address */ |
AnnaBridge | 171:3a7713b1edbc | 822 | |
AnnaBridge | 171:3a7713b1edbc | 823 | #define USB_DESCADD_DESCADD_Pos 0 /**< \brief (USB_DESCADD) Descriptor Address Value */ |
AnnaBridge | 171:3a7713b1edbc | 824 | #define USB_DESCADD_DESCADD_Msk (0xFFFFFFFFul << USB_DESCADD_DESCADD_Pos) |
AnnaBridge | 171:3a7713b1edbc | 825 | #define USB_DESCADD_DESCADD(value) ((USB_DESCADD_DESCADD_Msk & ((value) << USB_DESCADD_DESCADD_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 826 | #define USB_DESCADD_MASK 0xFFFFFFFFul /**< \brief (USB_DESCADD) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 827 | |
AnnaBridge | 171:3a7713b1edbc | 828 | /* -------- USB_PADCAL : (USB Offset: 0x028) (R/W 16) USB PAD Calibration -------- */ |
AnnaBridge | 171:3a7713b1edbc | 829 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 830 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 831 | struct { |
AnnaBridge | 171:3a7713b1edbc | 832 | uint16_t TRANSP:5; /*!< bit: 0.. 4 USB Pad Transp calibration */ |
AnnaBridge | 171:3a7713b1edbc | 833 | uint16_t :1; /*!< bit: 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 834 | uint16_t TRANSN:5; /*!< bit: 6..10 USB Pad Transn calibration */ |
AnnaBridge | 171:3a7713b1edbc | 835 | uint16_t :1; /*!< bit: 11 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 836 | uint16_t TRIM:3; /*!< bit: 12..14 USB Pad Trim calibration */ |
AnnaBridge | 171:3a7713b1edbc | 837 | uint16_t :1; /*!< bit: 15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 838 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 839 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 840 | } USB_PADCAL_Type; |
AnnaBridge | 171:3a7713b1edbc | 841 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 842 | |
AnnaBridge | 171:3a7713b1edbc | 843 | #define USB_PADCAL_OFFSET 0x028 /**< \brief (USB_PADCAL offset) USB PAD Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 844 | #define USB_PADCAL_RESETVALUE 0x0000ul /**< \brief (USB_PADCAL reset_value) USB PAD Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 845 | |
AnnaBridge | 171:3a7713b1edbc | 846 | #define USB_PADCAL_TRANSP_Pos 0 /**< \brief (USB_PADCAL) USB Pad Transp calibration */ |
AnnaBridge | 171:3a7713b1edbc | 847 | #define USB_PADCAL_TRANSP_Msk (0x1Ful << USB_PADCAL_TRANSP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 848 | #define USB_PADCAL_TRANSP(value) ((USB_PADCAL_TRANSP_Msk & ((value) << USB_PADCAL_TRANSP_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 849 | #define USB_PADCAL_TRANSN_Pos 6 /**< \brief (USB_PADCAL) USB Pad Transn calibration */ |
AnnaBridge | 171:3a7713b1edbc | 850 | #define USB_PADCAL_TRANSN_Msk (0x1Ful << USB_PADCAL_TRANSN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 851 | #define USB_PADCAL_TRANSN(value) ((USB_PADCAL_TRANSN_Msk & ((value) << USB_PADCAL_TRANSN_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 852 | #define USB_PADCAL_TRIM_Pos 12 /**< \brief (USB_PADCAL) USB Pad Trim calibration */ |
AnnaBridge | 171:3a7713b1edbc | 853 | #define USB_PADCAL_TRIM_Msk (0x7ul << USB_PADCAL_TRIM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 854 | #define USB_PADCAL_TRIM(value) ((USB_PADCAL_TRIM_Msk & ((value) << USB_PADCAL_TRIM_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 855 | #define USB_PADCAL_MASK 0x77DFul /**< \brief (USB_PADCAL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 856 | |
AnnaBridge | 171:3a7713b1edbc | 857 | /* -------- USB_DEVICE_EPCFG : (USB Offset: 0x100) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Configuration -------- */ |
AnnaBridge | 171:3a7713b1edbc | 858 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 859 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 860 | struct { |
AnnaBridge | 171:3a7713b1edbc | 861 | uint8_t EPTYPE0:3; /*!< bit: 0.. 2 End Point Type0 */ |
AnnaBridge | 171:3a7713b1edbc | 862 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 863 | uint8_t EPTYPE1:3; /*!< bit: 4.. 6 End Point Type1 */ |
AnnaBridge | 171:3a7713b1edbc | 864 | uint8_t NYETDIS:1; /*!< bit: 7 NYET Token Disable */ |
AnnaBridge | 171:3a7713b1edbc | 865 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 866 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 867 | } USB_DEVICE_EPCFG_Type; |
AnnaBridge | 171:3a7713b1edbc | 868 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 869 | |
AnnaBridge | 171:3a7713b1edbc | 870 | #define USB_DEVICE_EPCFG_OFFSET 0x100 /**< \brief (USB_DEVICE_EPCFG offset) DEVICE_ENDPOINT End Point Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 871 | #define USB_DEVICE_EPCFG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPCFG reset_value) DEVICE_ENDPOINT End Point Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 872 | |
AnnaBridge | 171:3a7713b1edbc | 873 | #define USB_DEVICE_EPCFG_EPTYPE0_Pos 0 /**< \brief (USB_DEVICE_EPCFG) End Point Type0 */ |
AnnaBridge | 171:3a7713b1edbc | 874 | #define USB_DEVICE_EPCFG_EPTYPE0_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 875 | #define USB_DEVICE_EPCFG_EPTYPE0(value) ((USB_DEVICE_EPCFG_EPTYPE0_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE0_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 876 | #define USB_DEVICE_EPCFG_EPTYPE1_Pos 4 /**< \brief (USB_DEVICE_EPCFG) End Point Type1 */ |
AnnaBridge | 171:3a7713b1edbc | 877 | #define USB_DEVICE_EPCFG_EPTYPE1_Msk (0x7ul << USB_DEVICE_EPCFG_EPTYPE1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 878 | #define USB_DEVICE_EPCFG_EPTYPE1(value) ((USB_DEVICE_EPCFG_EPTYPE1_Msk & ((value) << USB_DEVICE_EPCFG_EPTYPE1_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 879 | #define USB_DEVICE_EPCFG_NYETDIS_Pos 7 /**< \brief (USB_DEVICE_EPCFG) NYET Token Disable */ |
AnnaBridge | 171:3a7713b1edbc | 880 | #define USB_DEVICE_EPCFG_NYETDIS (0x1ul << USB_DEVICE_EPCFG_NYETDIS_Pos) |
AnnaBridge | 171:3a7713b1edbc | 881 | #define USB_DEVICE_EPCFG_MASK 0xF7ul /**< \brief (USB_DEVICE_EPCFG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 882 | |
AnnaBridge | 171:3a7713b1edbc | 883 | /* -------- USB_HOST_PCFG : (USB Offset: 0x100) (R/W 8) HOST HOST_PIPE End Point Configuration -------- */ |
AnnaBridge | 171:3a7713b1edbc | 884 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 885 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 886 | struct { |
AnnaBridge | 171:3a7713b1edbc | 887 | uint8_t PTOKEN:2; /*!< bit: 0.. 1 Pipe Token */ |
AnnaBridge | 171:3a7713b1edbc | 888 | uint8_t BK:1; /*!< bit: 2 Pipe Bank */ |
AnnaBridge | 171:3a7713b1edbc | 889 | uint8_t PTYPE:3; /*!< bit: 3.. 5 Pipe Type */ |
AnnaBridge | 171:3a7713b1edbc | 890 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 891 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 892 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 893 | } USB_HOST_PCFG_Type; |
AnnaBridge | 171:3a7713b1edbc | 894 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 895 | |
AnnaBridge | 171:3a7713b1edbc | 896 | #define USB_HOST_PCFG_OFFSET 0x100 /**< \brief (USB_HOST_PCFG offset) HOST_PIPE End Point Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 897 | #define USB_HOST_PCFG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PCFG reset_value) HOST_PIPE End Point Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 898 | |
AnnaBridge | 171:3a7713b1edbc | 899 | #define USB_HOST_PCFG_PTOKEN_Pos 0 /**< \brief (USB_HOST_PCFG) Pipe Token */ |
AnnaBridge | 171:3a7713b1edbc | 900 | #define USB_HOST_PCFG_PTOKEN_Msk (0x3ul << USB_HOST_PCFG_PTOKEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 901 | #define USB_HOST_PCFG_PTOKEN(value) ((USB_HOST_PCFG_PTOKEN_Msk & ((value) << USB_HOST_PCFG_PTOKEN_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 902 | #define USB_HOST_PCFG_BK_Pos 2 /**< \brief (USB_HOST_PCFG) Pipe Bank */ |
AnnaBridge | 171:3a7713b1edbc | 903 | #define USB_HOST_PCFG_BK (0x1ul << USB_HOST_PCFG_BK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 904 | #define USB_HOST_PCFG_PTYPE_Pos 3 /**< \brief (USB_HOST_PCFG) Pipe Type */ |
AnnaBridge | 171:3a7713b1edbc | 905 | #define USB_HOST_PCFG_PTYPE_Msk (0x7ul << USB_HOST_PCFG_PTYPE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 906 | #define USB_HOST_PCFG_PTYPE(value) ((USB_HOST_PCFG_PTYPE_Msk & ((value) << USB_HOST_PCFG_PTYPE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 907 | #define USB_HOST_PCFG_MASK 0x3Ful /**< \brief (USB_HOST_PCFG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 908 | |
AnnaBridge | 171:3a7713b1edbc | 909 | /* -------- USB_HOST_BINTERVAL : (USB Offset: 0x103) (R/W 8) HOST HOST_PIPE Bus Access Period of Pipe -------- */ |
AnnaBridge | 171:3a7713b1edbc | 910 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 911 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 912 | struct { |
AnnaBridge | 171:3a7713b1edbc | 913 | uint8_t BITINTERVAL:8; /*!< bit: 0.. 7 Bit Interval */ |
AnnaBridge | 171:3a7713b1edbc | 914 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 915 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 916 | } USB_HOST_BINTERVAL_Type; |
AnnaBridge | 171:3a7713b1edbc | 917 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 918 | |
AnnaBridge | 171:3a7713b1edbc | 919 | #define USB_HOST_BINTERVAL_OFFSET 0x103 /**< \brief (USB_HOST_BINTERVAL offset) HOST_PIPE Bus Access Period of Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 920 | #define USB_HOST_BINTERVAL_RESETVALUE 0x00ul /**< \brief (USB_HOST_BINTERVAL reset_value) HOST_PIPE Bus Access Period of Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 921 | |
AnnaBridge | 171:3a7713b1edbc | 922 | #define USB_HOST_BINTERVAL_BITINTERVAL_Pos 0 /**< \brief (USB_HOST_BINTERVAL) Bit Interval */ |
AnnaBridge | 171:3a7713b1edbc | 923 | #define USB_HOST_BINTERVAL_BITINTERVAL_Msk (0xFFul << USB_HOST_BINTERVAL_BITINTERVAL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 924 | #define USB_HOST_BINTERVAL_BITINTERVAL(value) ((USB_HOST_BINTERVAL_BITINTERVAL_Msk & ((value) << USB_HOST_BINTERVAL_BITINTERVAL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 925 | #define USB_HOST_BINTERVAL_MASK 0xFFul /**< \brief (USB_HOST_BINTERVAL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 926 | |
AnnaBridge | 171:3a7713b1edbc | 927 | /* -------- USB_DEVICE_EPSTATUSCLR : (USB Offset: 0x104) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 928 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 929 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 930 | struct { |
AnnaBridge | 171:3a7713b1edbc | 931 | uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Clear */ |
AnnaBridge | 171:3a7713b1edbc | 932 | uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Clear */ |
AnnaBridge | 171:3a7713b1edbc | 933 | uint8_t CURBK:1; /*!< bit: 2 Curren Bank Clear */ |
AnnaBridge | 171:3a7713b1edbc | 934 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 935 | uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Clear */ |
AnnaBridge | 171:3a7713b1edbc | 936 | uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Clear */ |
AnnaBridge | 171:3a7713b1edbc | 937 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 938 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 939 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 940 | struct { |
AnnaBridge | 171:3a7713b1edbc | 941 | uint8_t :4; /*!< bit: 0.. 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 942 | uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Clear */ |
AnnaBridge | 171:3a7713b1edbc | 943 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 944 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 945 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 946 | } USB_DEVICE_EPSTATUSCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 947 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 948 | |
AnnaBridge | 171:3a7713b1edbc | 949 | #define USB_DEVICE_EPSTATUSCLR_OFFSET 0x104 /**< \brief (USB_DEVICE_EPSTATUSCLR offset) DEVICE_ENDPOINT End Point Pipe Status Clear */ |
AnnaBridge | 171:3a7713b1edbc | 950 | #define USB_DEVICE_EPSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSCLR reset_value) DEVICE_ENDPOINT End Point Pipe Status Clear */ |
AnnaBridge | 171:3a7713b1edbc | 951 | |
AnnaBridge | 171:3a7713b1edbc | 952 | #define USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle OUT Clear */ |
AnnaBridge | 171:3a7713b1edbc | 953 | #define USB_DEVICE_EPSTATUSCLR_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLOUT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 954 | #define USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSCLR) Data Toggle IN Clear */ |
AnnaBridge | 171:3a7713b1edbc | 955 | #define USB_DEVICE_EPSTATUSCLR_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSCLR_DTGLIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 956 | #define USB_DEVICE_EPSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSCLR) Curren Bank Clear */ |
AnnaBridge | 171:3a7713b1edbc | 957 | #define USB_DEVICE_EPSTATUSCLR_CURBK (0x1ul << USB_DEVICE_EPSTATUSCLR_CURBK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 958 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 0 Request Clear */ |
AnnaBridge | 171:3a7713b1edbc | 959 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ0 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 960 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall 1 Request Clear */ |
AnnaBridge | 171:3a7713b1edbc | 961 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ1 (1 << USB_DEVICE_EPSTATUSCLR_STALLRQ1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 962 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSCLR) Stall x Request Clear */ |
AnnaBridge | 171:3a7713b1edbc | 963 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 964 | #define USB_DEVICE_EPSTATUSCLR_STALLRQ(value) ((USB_DEVICE_EPSTATUSCLR_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSCLR_STALLRQ_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 965 | #define USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 0 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 966 | #define USB_DEVICE_EPSTATUSCLR_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK0RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 967 | #define USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSCLR) Bank 1 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 968 | #define USB_DEVICE_EPSTATUSCLR_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSCLR_BK1RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 969 | #define USB_DEVICE_EPSTATUSCLR_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 970 | |
AnnaBridge | 171:3a7713b1edbc | 971 | /* -------- USB_HOST_PSTATUSCLR : (USB Offset: 0x104) ( /W 8) HOST HOST_PIPE End Point Pipe Status Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 972 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 973 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 974 | struct { |
AnnaBridge | 171:3a7713b1edbc | 975 | uint8_t DTGL:1; /*!< bit: 0 Data Toggle clear */ |
AnnaBridge | 171:3a7713b1edbc | 976 | uint8_t :1; /*!< bit: 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 977 | uint8_t CURBK:1; /*!< bit: 2 Curren Bank clear */ |
AnnaBridge | 171:3a7713b1edbc | 978 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 979 | uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Clear */ |
AnnaBridge | 171:3a7713b1edbc | 980 | uint8_t :1; /*!< bit: 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 981 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 982 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 983 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 984 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 985 | } USB_HOST_PSTATUSCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 986 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 987 | |
AnnaBridge | 171:3a7713b1edbc | 988 | #define USB_HOST_PSTATUSCLR_OFFSET 0x104 /**< \brief (USB_HOST_PSTATUSCLR offset) HOST_PIPE End Point Pipe Status Clear */ |
AnnaBridge | 171:3a7713b1edbc | 989 | #define USB_HOST_PSTATUSCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSCLR reset_value) HOST_PIPE End Point Pipe Status Clear */ |
AnnaBridge | 171:3a7713b1edbc | 990 | |
AnnaBridge | 171:3a7713b1edbc | 991 | #define USB_HOST_PSTATUSCLR_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSCLR) Data Toggle clear */ |
AnnaBridge | 171:3a7713b1edbc | 992 | #define USB_HOST_PSTATUSCLR_DTGL (0x1ul << USB_HOST_PSTATUSCLR_DTGL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 993 | #define USB_HOST_PSTATUSCLR_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSCLR) Curren Bank clear */ |
AnnaBridge | 171:3a7713b1edbc | 994 | #define USB_HOST_PSTATUSCLR_CURBK (0x1ul << USB_HOST_PSTATUSCLR_CURBK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 995 | #define USB_HOST_PSTATUSCLR_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSCLR) Pipe Freeze Clear */ |
AnnaBridge | 171:3a7713b1edbc | 996 | #define USB_HOST_PSTATUSCLR_PFREEZE (0x1ul << USB_HOST_PSTATUSCLR_PFREEZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 997 | #define USB_HOST_PSTATUSCLR_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSCLR) Bank 0 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 998 | #define USB_HOST_PSTATUSCLR_BK0RDY (0x1ul << USB_HOST_PSTATUSCLR_BK0RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 999 | #define USB_HOST_PSTATUSCLR_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSCLR) Bank 1 Ready Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1000 | #define USB_HOST_PSTATUSCLR_BK1RDY (0x1ul << USB_HOST_PSTATUSCLR_BK1RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1001 | #define USB_HOST_PSTATUSCLR_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1002 | |
AnnaBridge | 171:3a7713b1edbc | 1003 | /* -------- USB_DEVICE_EPSTATUSSET : (USB Offset: 0x105) ( /W 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1004 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1005 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1006 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1007 | uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle OUT Set */ |
AnnaBridge | 171:3a7713b1edbc | 1008 | uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle IN Set */ |
AnnaBridge | 171:3a7713b1edbc | 1009 | uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ |
AnnaBridge | 171:3a7713b1edbc | 1010 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1011 | uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request Set */ |
AnnaBridge | 171:3a7713b1edbc | 1012 | uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request Set */ |
AnnaBridge | 171:3a7713b1edbc | 1013 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1014 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1015 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1016 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1017 | uint8_t :4; /*!< bit: 0.. 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1018 | uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request Set */ |
AnnaBridge | 171:3a7713b1edbc | 1019 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1020 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1021 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1022 | } USB_DEVICE_EPSTATUSSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 1023 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1024 | |
AnnaBridge | 171:3a7713b1edbc | 1025 | #define USB_DEVICE_EPSTATUSSET_OFFSET 0x105 /**< \brief (USB_DEVICE_EPSTATUSSET offset) DEVICE_ENDPOINT End Point Pipe Status Set */ |
AnnaBridge | 171:3a7713b1edbc | 1026 | #define USB_DEVICE_EPSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUSSET reset_value) DEVICE_ENDPOINT End Point Pipe Status Set */ |
AnnaBridge | 171:3a7713b1edbc | 1027 | |
AnnaBridge | 171:3a7713b1edbc | 1028 | #define USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle OUT Set */ |
AnnaBridge | 171:3a7713b1edbc | 1029 | #define USB_DEVICE_EPSTATUSSET_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLOUT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1030 | #define USB_DEVICE_EPSTATUSSET_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUSSET) Data Toggle IN Set */ |
AnnaBridge | 171:3a7713b1edbc | 1031 | #define USB_DEVICE_EPSTATUSSET_DTGLIN (0x1ul << USB_DEVICE_EPSTATUSSET_DTGLIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1032 | #define USB_DEVICE_EPSTATUSSET_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUSSET) Current Bank Set */ |
AnnaBridge | 171:3a7713b1edbc | 1033 | #define USB_DEVICE_EPSTATUSSET_CURBK (0x1ul << USB_DEVICE_EPSTATUSSET_CURBK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1034 | #define USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 0 Request Set */ |
AnnaBridge | 171:3a7713b1edbc | 1035 | #define USB_DEVICE_EPSTATUSSET_STALLRQ0 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1036 | #define USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall 1 Request Set */ |
AnnaBridge | 171:3a7713b1edbc | 1037 | #define USB_DEVICE_EPSTATUSSET_STALLRQ1 (1 << USB_DEVICE_EPSTATUSSET_STALLRQ1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1038 | #define USB_DEVICE_EPSTATUSSET_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUSSET) Stall x Request Set */ |
AnnaBridge | 171:3a7713b1edbc | 1039 | #define USB_DEVICE_EPSTATUSSET_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1040 | #define USB_DEVICE_EPSTATUSSET_STALLRQ(value) ((USB_DEVICE_EPSTATUSSET_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUSSET_STALLRQ_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1041 | #define USB_DEVICE_EPSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 0 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1042 | #define USB_DEVICE_EPSTATUSSET_BK0RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK0RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1043 | #define USB_DEVICE_EPSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUSSET) Bank 1 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1044 | #define USB_DEVICE_EPSTATUSSET_BK1RDY (0x1ul << USB_DEVICE_EPSTATUSSET_BK1RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1045 | #define USB_DEVICE_EPSTATUSSET_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUSSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1046 | |
AnnaBridge | 171:3a7713b1edbc | 1047 | /* -------- USB_HOST_PSTATUSSET : (USB Offset: 0x105) ( /W 8) HOST HOST_PIPE End Point Pipe Status Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1048 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1049 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1050 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1051 | uint8_t DTGL:1; /*!< bit: 0 Data Toggle Set */ |
AnnaBridge | 171:3a7713b1edbc | 1052 | uint8_t :1; /*!< bit: 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1053 | uint8_t CURBK:1; /*!< bit: 2 Current Bank Set */ |
AnnaBridge | 171:3a7713b1edbc | 1054 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1055 | uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze Set */ |
AnnaBridge | 171:3a7713b1edbc | 1056 | uint8_t :1; /*!< bit: 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1057 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1058 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1059 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1060 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1061 | } USB_HOST_PSTATUSSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 1062 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1063 | |
AnnaBridge | 171:3a7713b1edbc | 1064 | #define USB_HOST_PSTATUSSET_OFFSET 0x105 /**< \brief (USB_HOST_PSTATUSSET offset) HOST_PIPE End Point Pipe Status Set */ |
AnnaBridge | 171:3a7713b1edbc | 1065 | #define USB_HOST_PSTATUSSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUSSET reset_value) HOST_PIPE End Point Pipe Status Set */ |
AnnaBridge | 171:3a7713b1edbc | 1066 | |
AnnaBridge | 171:3a7713b1edbc | 1067 | #define USB_HOST_PSTATUSSET_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUSSET) Data Toggle Set */ |
AnnaBridge | 171:3a7713b1edbc | 1068 | #define USB_HOST_PSTATUSSET_DTGL (0x1ul << USB_HOST_PSTATUSSET_DTGL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1069 | #define USB_HOST_PSTATUSSET_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUSSET) Current Bank Set */ |
AnnaBridge | 171:3a7713b1edbc | 1070 | #define USB_HOST_PSTATUSSET_CURBK (0x1ul << USB_HOST_PSTATUSSET_CURBK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1071 | #define USB_HOST_PSTATUSSET_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUSSET) Pipe Freeze Set */ |
AnnaBridge | 171:3a7713b1edbc | 1072 | #define USB_HOST_PSTATUSSET_PFREEZE (0x1ul << USB_HOST_PSTATUSSET_PFREEZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1073 | #define USB_HOST_PSTATUSSET_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUSSET) Bank 0 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1074 | #define USB_HOST_PSTATUSSET_BK0RDY (0x1ul << USB_HOST_PSTATUSSET_BK0RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1075 | #define USB_HOST_PSTATUSSET_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUSSET) Bank 1 Ready Set */ |
AnnaBridge | 171:3a7713b1edbc | 1076 | #define USB_HOST_PSTATUSSET_BK1RDY (0x1ul << USB_HOST_PSTATUSSET_BK1RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1077 | #define USB_HOST_PSTATUSSET_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUSSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1078 | |
AnnaBridge | 171:3a7713b1edbc | 1079 | /* -------- USB_DEVICE_EPSTATUS : (USB Offset: 0x106) (R/ 8) DEVICE DEVICE_ENDPOINT End Point Pipe Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1080 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1081 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1082 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1083 | uint8_t DTGLOUT:1; /*!< bit: 0 Data Toggle Out */ |
AnnaBridge | 171:3a7713b1edbc | 1084 | uint8_t DTGLIN:1; /*!< bit: 1 Data Toggle In */ |
AnnaBridge | 171:3a7713b1edbc | 1085 | uint8_t CURBK:1; /*!< bit: 2 Current Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1086 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1087 | uint8_t STALLRQ0:1; /*!< bit: 4 Stall 0 Request */ |
AnnaBridge | 171:3a7713b1edbc | 1088 | uint8_t STALLRQ1:1; /*!< bit: 5 Stall 1 Request */ |
AnnaBridge | 171:3a7713b1edbc | 1089 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1090 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1091 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1092 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1093 | uint8_t :4; /*!< bit: 0.. 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1094 | uint8_t STALLRQ:2; /*!< bit: 4.. 5 Stall x Request */ |
AnnaBridge | 171:3a7713b1edbc | 1095 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1096 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1097 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1098 | } USB_DEVICE_EPSTATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 1099 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1100 | |
AnnaBridge | 171:3a7713b1edbc | 1101 | #define USB_DEVICE_EPSTATUS_OFFSET 0x106 /**< \brief (USB_DEVICE_EPSTATUS offset) DEVICE_ENDPOINT End Point Pipe Status */ |
AnnaBridge | 171:3a7713b1edbc | 1102 | #define USB_DEVICE_EPSTATUS_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPSTATUS reset_value) DEVICE_ENDPOINT End Point Pipe Status */ |
AnnaBridge | 171:3a7713b1edbc | 1103 | |
AnnaBridge | 171:3a7713b1edbc | 1104 | #define USB_DEVICE_EPSTATUS_DTGLOUT_Pos 0 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle Out */ |
AnnaBridge | 171:3a7713b1edbc | 1105 | #define USB_DEVICE_EPSTATUS_DTGLOUT (0x1ul << USB_DEVICE_EPSTATUS_DTGLOUT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1106 | #define USB_DEVICE_EPSTATUS_DTGLIN_Pos 1 /**< \brief (USB_DEVICE_EPSTATUS) Data Toggle In */ |
AnnaBridge | 171:3a7713b1edbc | 1107 | #define USB_DEVICE_EPSTATUS_DTGLIN (0x1ul << USB_DEVICE_EPSTATUS_DTGLIN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1108 | #define USB_DEVICE_EPSTATUS_CURBK_Pos 2 /**< \brief (USB_DEVICE_EPSTATUS) Current Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1109 | #define USB_DEVICE_EPSTATUS_CURBK (0x1ul << USB_DEVICE_EPSTATUS_CURBK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1110 | #define USB_DEVICE_EPSTATUS_STALLRQ0_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall 0 Request */ |
AnnaBridge | 171:3a7713b1edbc | 1111 | #define USB_DEVICE_EPSTATUS_STALLRQ0 (1 << USB_DEVICE_EPSTATUS_STALLRQ0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1112 | #define USB_DEVICE_EPSTATUS_STALLRQ1_Pos 5 /**< \brief (USB_DEVICE_EPSTATUS) Stall 1 Request */ |
AnnaBridge | 171:3a7713b1edbc | 1113 | #define USB_DEVICE_EPSTATUS_STALLRQ1 (1 << USB_DEVICE_EPSTATUS_STALLRQ1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1114 | #define USB_DEVICE_EPSTATUS_STALLRQ_Pos 4 /**< \brief (USB_DEVICE_EPSTATUS) Stall x Request */ |
AnnaBridge | 171:3a7713b1edbc | 1115 | #define USB_DEVICE_EPSTATUS_STALLRQ_Msk (0x3ul << USB_DEVICE_EPSTATUS_STALLRQ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1116 | #define USB_DEVICE_EPSTATUS_STALLRQ(value) ((USB_DEVICE_EPSTATUS_STALLRQ_Msk & ((value) << USB_DEVICE_EPSTATUS_STALLRQ_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1117 | #define USB_DEVICE_EPSTATUS_BK0RDY_Pos 6 /**< \brief (USB_DEVICE_EPSTATUS) Bank 0 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1118 | #define USB_DEVICE_EPSTATUS_BK0RDY (0x1ul << USB_DEVICE_EPSTATUS_BK0RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1119 | #define USB_DEVICE_EPSTATUS_BK1RDY_Pos 7 /**< \brief (USB_DEVICE_EPSTATUS) Bank 1 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1120 | #define USB_DEVICE_EPSTATUS_BK1RDY (0x1ul << USB_DEVICE_EPSTATUS_BK1RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1121 | #define USB_DEVICE_EPSTATUS_MASK 0xF7ul /**< \brief (USB_DEVICE_EPSTATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1122 | |
AnnaBridge | 171:3a7713b1edbc | 1123 | /* -------- USB_HOST_PSTATUS : (USB Offset: 0x106) (R/ 8) HOST HOST_PIPE End Point Pipe Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1124 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1125 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1126 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1127 | uint8_t DTGL:1; /*!< bit: 0 Data Toggle */ |
AnnaBridge | 171:3a7713b1edbc | 1128 | uint8_t :1; /*!< bit: 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1129 | uint8_t CURBK:1; /*!< bit: 2 Current Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1130 | uint8_t :1; /*!< bit: 3 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1131 | uint8_t PFREEZE:1; /*!< bit: 4 Pipe Freeze */ |
AnnaBridge | 171:3a7713b1edbc | 1132 | uint8_t :1; /*!< bit: 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1133 | uint8_t BK0RDY:1; /*!< bit: 6 Bank 0 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1134 | uint8_t BK1RDY:1; /*!< bit: 7 Bank 1 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1135 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1136 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1137 | } USB_HOST_PSTATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 1138 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1139 | |
AnnaBridge | 171:3a7713b1edbc | 1140 | #define USB_HOST_PSTATUS_OFFSET 0x106 /**< \brief (USB_HOST_PSTATUS offset) HOST_PIPE End Point Pipe Status */ |
AnnaBridge | 171:3a7713b1edbc | 1141 | #define USB_HOST_PSTATUS_RESETVALUE 0x00ul /**< \brief (USB_HOST_PSTATUS reset_value) HOST_PIPE End Point Pipe Status */ |
AnnaBridge | 171:3a7713b1edbc | 1142 | |
AnnaBridge | 171:3a7713b1edbc | 1143 | #define USB_HOST_PSTATUS_DTGL_Pos 0 /**< \brief (USB_HOST_PSTATUS) Data Toggle */ |
AnnaBridge | 171:3a7713b1edbc | 1144 | #define USB_HOST_PSTATUS_DTGL (0x1ul << USB_HOST_PSTATUS_DTGL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1145 | #define USB_HOST_PSTATUS_CURBK_Pos 2 /**< \brief (USB_HOST_PSTATUS) Current Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1146 | #define USB_HOST_PSTATUS_CURBK (0x1ul << USB_HOST_PSTATUS_CURBK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1147 | #define USB_HOST_PSTATUS_PFREEZE_Pos 4 /**< \brief (USB_HOST_PSTATUS) Pipe Freeze */ |
AnnaBridge | 171:3a7713b1edbc | 1148 | #define USB_HOST_PSTATUS_PFREEZE (0x1ul << USB_HOST_PSTATUS_PFREEZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1149 | #define USB_HOST_PSTATUS_BK0RDY_Pos 6 /**< \brief (USB_HOST_PSTATUS) Bank 0 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1150 | #define USB_HOST_PSTATUS_BK0RDY (0x1ul << USB_HOST_PSTATUS_BK0RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1151 | #define USB_HOST_PSTATUS_BK1RDY_Pos 7 /**< \brief (USB_HOST_PSTATUS) Bank 1 ready */ |
AnnaBridge | 171:3a7713b1edbc | 1152 | #define USB_HOST_PSTATUS_BK1RDY (0x1ul << USB_HOST_PSTATUS_BK1RDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1153 | #define USB_HOST_PSTATUS_MASK 0xD5ul /**< \brief (USB_HOST_PSTATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1154 | |
AnnaBridge | 171:3a7713b1edbc | 1155 | /* -------- USB_DEVICE_EPINTFLAG : (USB Offset: 0x107) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Flag -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1156 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1157 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1158 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1159 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */ |
AnnaBridge | 171:3a7713b1edbc | 1160 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */ |
AnnaBridge | 171:3a7713b1edbc | 1161 | uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */ |
AnnaBridge | 171:3a7713b1edbc | 1162 | uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */ |
AnnaBridge | 171:3a7713b1edbc | 1163 | uint8_t RXSTP:1; /*!< bit: 4 Received Setup */ |
AnnaBridge | 171:3a7713b1edbc | 1164 | uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */ |
AnnaBridge | 171:3a7713b1edbc | 1165 | uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */ |
AnnaBridge | 171:3a7713b1edbc | 1166 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1167 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1168 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1169 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */ |
AnnaBridge | 171:3a7713b1edbc | 1170 | uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */ |
AnnaBridge | 171:3a7713b1edbc | 1171 | uint8_t :1; /*!< bit: 4 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1172 | uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out */ |
AnnaBridge | 171:3a7713b1edbc | 1173 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1174 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1175 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1176 | } USB_DEVICE_EPINTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 1177 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1178 | |
AnnaBridge | 171:3a7713b1edbc | 1179 | #define USB_DEVICE_EPINTFLAG_OFFSET 0x107 /**< \brief (USB_DEVICE_EPINTFLAG offset) DEVICE_ENDPOINT End Point Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1180 | #define USB_DEVICE_EPINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTFLAG reset_value) DEVICE_ENDPOINT End Point Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1181 | |
AnnaBridge | 171:3a7713b1edbc | 1182 | #define USB_DEVICE_EPINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 0 */ |
AnnaBridge | 171:3a7713b1edbc | 1183 | #define USB_DEVICE_EPINTFLAG_TRCPT0 (1 << USB_DEVICE_EPINTFLAG_TRCPT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1184 | #define USB_DEVICE_EPINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete 1 */ |
AnnaBridge | 171:3a7713b1edbc | 1185 | #define USB_DEVICE_EPINTFLAG_TRCPT1 (1 << USB_DEVICE_EPINTFLAG_TRCPT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1186 | #define USB_DEVICE_EPINTFLAG_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTFLAG) Transfer Complete x */ |
AnnaBridge | 171:3a7713b1edbc | 1187 | #define USB_DEVICE_EPINTFLAG_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRCPT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1188 | #define USB_DEVICE_EPINTFLAG_TRCPT(value) ((USB_DEVICE_EPINTFLAG_TRCPT_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRCPT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1189 | #define USB_DEVICE_EPINTFLAG_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 0 */ |
AnnaBridge | 171:3a7713b1edbc | 1190 | #define USB_DEVICE_EPINTFLAG_TRFAIL0 (1 << USB_DEVICE_EPINTFLAG_TRFAIL0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1191 | #define USB_DEVICE_EPINTFLAG_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow 1 */ |
AnnaBridge | 171:3a7713b1edbc | 1192 | #define USB_DEVICE_EPINTFLAG_TRFAIL1 (1 << USB_DEVICE_EPINTFLAG_TRFAIL1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1193 | #define USB_DEVICE_EPINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTFLAG) Error Flow x */ |
AnnaBridge | 171:3a7713b1edbc | 1194 | #define USB_DEVICE_EPINTFLAG_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_TRFAIL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1195 | #define USB_DEVICE_EPINTFLAG_TRFAIL(value) ((USB_DEVICE_EPINTFLAG_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTFLAG_TRFAIL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1196 | #define USB_DEVICE_EPINTFLAG_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTFLAG) Received Setup */ |
AnnaBridge | 171:3a7713b1edbc | 1197 | #define USB_DEVICE_EPINTFLAG_RXSTP (0x1ul << USB_DEVICE_EPINTFLAG_RXSTP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1198 | #define USB_DEVICE_EPINTFLAG_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 0 In/out */ |
AnnaBridge | 171:3a7713b1edbc | 1199 | #define USB_DEVICE_EPINTFLAG_STALL0 (1 << USB_DEVICE_EPINTFLAG_STALL0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1200 | #define USB_DEVICE_EPINTFLAG_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTFLAG) Stall 1 In/out */ |
AnnaBridge | 171:3a7713b1edbc | 1201 | #define USB_DEVICE_EPINTFLAG_STALL1 (1 << USB_DEVICE_EPINTFLAG_STALL1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1202 | #define USB_DEVICE_EPINTFLAG_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTFLAG) Stall x In/out */ |
AnnaBridge | 171:3a7713b1edbc | 1203 | #define USB_DEVICE_EPINTFLAG_STALL_Msk (0x3ul << USB_DEVICE_EPINTFLAG_STALL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1204 | #define USB_DEVICE_EPINTFLAG_STALL(value) ((USB_DEVICE_EPINTFLAG_STALL_Msk & ((value) << USB_DEVICE_EPINTFLAG_STALL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1205 | #define USB_DEVICE_EPINTFLAG_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1206 | |
AnnaBridge | 171:3a7713b1edbc | 1207 | /* -------- USB_HOST_PINTFLAG : (USB Offset: 0x107) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1208 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1209 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1210 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1211 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1212 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1213 | uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1214 | uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1215 | uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1216 | uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1217 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1218 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1219 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1220 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1221 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1222 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1223 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1224 | } USB_HOST_PINTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 1225 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1226 | |
AnnaBridge | 171:3a7713b1edbc | 1227 | #define USB_HOST_PINTFLAG_OFFSET 0x107 /**< \brief (USB_HOST_PINTFLAG offset) HOST_PIPE Pipe Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1228 | #define USB_HOST_PINTFLAG_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTFLAG reset_value) HOST_PIPE Pipe Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1229 | |
AnnaBridge | 171:3a7713b1edbc | 1230 | #define USB_HOST_PINTFLAG_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 0 Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1231 | #define USB_HOST_PINTFLAG_TRCPT0 (1 << USB_HOST_PINTFLAG_TRCPT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1232 | #define USB_HOST_PINTFLAG_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete 1 Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1233 | #define USB_HOST_PINTFLAG_TRCPT1 (1 << USB_HOST_PINTFLAG_TRCPT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1234 | #define USB_HOST_PINTFLAG_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTFLAG) Transfer Complete x Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1235 | #define USB_HOST_PINTFLAG_TRCPT_Msk (0x3ul << USB_HOST_PINTFLAG_TRCPT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1236 | #define USB_HOST_PINTFLAG_TRCPT(value) ((USB_HOST_PINTFLAG_TRCPT_Msk & ((value) << USB_HOST_PINTFLAG_TRCPT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1237 | #define USB_HOST_PINTFLAG_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTFLAG) Error Flow Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1238 | #define USB_HOST_PINTFLAG_TRFAIL (0x1ul << USB_HOST_PINTFLAG_TRFAIL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1239 | #define USB_HOST_PINTFLAG_PERR_Pos 3 /**< \brief (USB_HOST_PINTFLAG) Pipe Error Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1240 | #define USB_HOST_PINTFLAG_PERR (0x1ul << USB_HOST_PINTFLAG_PERR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1241 | #define USB_HOST_PINTFLAG_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTFLAG) Transmit Setup Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1242 | #define USB_HOST_PINTFLAG_TXSTP (0x1ul << USB_HOST_PINTFLAG_TXSTP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1243 | #define USB_HOST_PINTFLAG_STALL_Pos 5 /**< \brief (USB_HOST_PINTFLAG) Stall Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1244 | #define USB_HOST_PINTFLAG_STALL (0x1ul << USB_HOST_PINTFLAG_STALL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1245 | #define USB_HOST_PINTFLAG_MASK 0x3Ful /**< \brief (USB_HOST_PINTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1246 | |
AnnaBridge | 171:3a7713b1edbc | 1247 | /* -------- USB_DEVICE_EPINTENCLR : (USB Offset: 0x108) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Clear Flag -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1248 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1249 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1250 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1251 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1252 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1253 | uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1254 | uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1255 | uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1256 | uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/Out Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1257 | uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/Out Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1258 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1259 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1260 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1261 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1262 | uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1263 | uint8_t :1; /*!< bit: 4 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1264 | uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/Out Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1265 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1266 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1267 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1268 | } USB_DEVICE_EPINTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 1269 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1270 | |
AnnaBridge | 171:3a7713b1edbc | 1271 | #define USB_DEVICE_EPINTENCLR_OFFSET 0x108 /**< \brief (USB_DEVICE_EPINTENCLR offset) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1272 | #define USB_DEVICE_EPINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENCLR reset_value) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1273 | |
AnnaBridge | 171:3a7713b1edbc | 1274 | #define USB_DEVICE_EPINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 0 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1275 | #define USB_DEVICE_EPINTENCLR_TRCPT0 (1 << USB_DEVICE_EPINTENCLR_TRCPT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1276 | #define USB_DEVICE_EPINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete 1 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1277 | #define USB_DEVICE_EPINTENCLR_TRCPT1 (1 << USB_DEVICE_EPINTENCLR_TRCPT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1278 | #define USB_DEVICE_EPINTENCLR_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENCLR) Transfer Complete x Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1279 | #define USB_DEVICE_EPINTENCLR_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRCPT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1280 | #define USB_DEVICE_EPINTENCLR_TRCPT(value) ((USB_DEVICE_EPINTENCLR_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRCPT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1281 | #define USB_DEVICE_EPINTENCLR_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 0 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1282 | #define USB_DEVICE_EPINTENCLR_TRFAIL0 (1 << USB_DEVICE_EPINTENCLR_TRFAIL0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1283 | #define USB_DEVICE_EPINTENCLR_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow 1 Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1284 | #define USB_DEVICE_EPINTENCLR_TRFAIL1 (1 << USB_DEVICE_EPINTENCLR_TRFAIL1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1285 | #define USB_DEVICE_EPINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENCLR) Error Flow x Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1286 | #define USB_DEVICE_EPINTENCLR_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_TRFAIL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1287 | #define USB_DEVICE_EPINTENCLR_TRFAIL(value) ((USB_DEVICE_EPINTENCLR_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENCLR_TRFAIL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1288 | #define USB_DEVICE_EPINTENCLR_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENCLR) Received Setup Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1289 | #define USB_DEVICE_EPINTENCLR_RXSTP (0x1ul << USB_DEVICE_EPINTENCLR_RXSTP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1290 | #define USB_DEVICE_EPINTENCLR_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 0 In/Out Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1291 | #define USB_DEVICE_EPINTENCLR_STALL0 (1 << USB_DEVICE_EPINTENCLR_STALL0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1292 | #define USB_DEVICE_EPINTENCLR_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENCLR) Stall 1 In/Out Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1293 | #define USB_DEVICE_EPINTENCLR_STALL1 (1 << USB_DEVICE_EPINTENCLR_STALL1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1294 | #define USB_DEVICE_EPINTENCLR_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENCLR) Stall x In/Out Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1295 | #define USB_DEVICE_EPINTENCLR_STALL_Msk (0x3ul << USB_DEVICE_EPINTENCLR_STALL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1296 | #define USB_DEVICE_EPINTENCLR_STALL(value) ((USB_DEVICE_EPINTENCLR_STALL_Msk & ((value) << USB_DEVICE_EPINTENCLR_STALL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1297 | #define USB_DEVICE_EPINTENCLR_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1298 | |
AnnaBridge | 171:3a7713b1edbc | 1299 | /* -------- USB_HOST_PINTENCLR : (USB Offset: 0x108) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1300 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1301 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1302 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1303 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1304 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1305 | uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1306 | uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1307 | uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1308 | uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1309 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1310 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1311 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1312 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1313 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1314 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1315 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1316 | } USB_HOST_PINTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 1317 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1318 | |
AnnaBridge | 171:3a7713b1edbc | 1319 | #define USB_HOST_PINTENCLR_OFFSET 0x108 /**< \brief (USB_HOST_PINTENCLR offset) HOST_PIPE Pipe Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1320 | #define USB_HOST_PINTENCLR_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENCLR reset_value) HOST_PIPE Pipe Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1321 | |
AnnaBridge | 171:3a7713b1edbc | 1322 | #define USB_HOST_PINTENCLR_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 0 Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1323 | #define USB_HOST_PINTENCLR_TRCPT0 (1 << USB_HOST_PINTENCLR_TRCPT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1324 | #define USB_HOST_PINTENCLR_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete 1 Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1325 | #define USB_HOST_PINTENCLR_TRCPT1 (1 << USB_HOST_PINTENCLR_TRCPT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1326 | #define USB_HOST_PINTENCLR_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENCLR) Transfer Complete x Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1327 | #define USB_HOST_PINTENCLR_TRCPT_Msk (0x3ul << USB_HOST_PINTENCLR_TRCPT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1328 | #define USB_HOST_PINTENCLR_TRCPT(value) ((USB_HOST_PINTENCLR_TRCPT_Msk & ((value) << USB_HOST_PINTENCLR_TRCPT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1329 | #define USB_HOST_PINTENCLR_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENCLR) Error Flow Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1330 | #define USB_HOST_PINTENCLR_TRFAIL (0x1ul << USB_HOST_PINTENCLR_TRFAIL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1331 | #define USB_HOST_PINTENCLR_PERR_Pos 3 /**< \brief (USB_HOST_PINTENCLR) Pipe Error Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1332 | #define USB_HOST_PINTENCLR_PERR (0x1ul << USB_HOST_PINTENCLR_PERR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1333 | #define USB_HOST_PINTENCLR_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENCLR) Transmit Setup Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1334 | #define USB_HOST_PINTENCLR_TXSTP (0x1ul << USB_HOST_PINTENCLR_TXSTP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1335 | #define USB_HOST_PINTENCLR_STALL_Pos 5 /**< \brief (USB_HOST_PINTENCLR) Stall Interrupt Disable */ |
AnnaBridge | 171:3a7713b1edbc | 1336 | #define USB_HOST_PINTENCLR_STALL (0x1ul << USB_HOST_PINTENCLR_STALL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1337 | #define USB_HOST_PINTENCLR_MASK 0x3Ful /**< \brief (USB_HOST_PINTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1338 | |
AnnaBridge | 171:3a7713b1edbc | 1339 | /* -------- USB_DEVICE_EPINTENSET : (USB Offset: 0x109) (R/W 8) DEVICE DEVICE_ENDPOINT End Point Interrupt Set Flag -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1340 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1341 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1342 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1343 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1344 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1345 | uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1346 | uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1347 | uint8_t RXSTP:1; /*!< bit: 4 Received Setup Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1348 | uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out Interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1349 | uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out Interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1350 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1351 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1352 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1353 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1354 | uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1355 | uint8_t :1; /*!< bit: 4 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1356 | uint8_t STALL:2; /*!< bit: 5.. 6 Stall x In/out Interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1357 | uint8_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1358 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1359 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1360 | } USB_DEVICE_EPINTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 1361 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1362 | |
AnnaBridge | 171:3a7713b1edbc | 1363 | #define USB_DEVICE_EPINTENSET_OFFSET 0x109 /**< \brief (USB_DEVICE_EPINTENSET offset) DEVICE_ENDPOINT End Point Interrupt Set Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1364 | #define USB_DEVICE_EPINTENSET_RESETVALUE 0x00ul /**< \brief (USB_DEVICE_EPINTENSET reset_value) DEVICE_ENDPOINT End Point Interrupt Set Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1365 | |
AnnaBridge | 171:3a7713b1edbc | 1366 | #define USB_DEVICE_EPINTENSET_TRCPT0_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 0 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1367 | #define USB_DEVICE_EPINTENSET_TRCPT0 (1 << USB_DEVICE_EPINTENSET_TRCPT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1368 | #define USB_DEVICE_EPINTENSET_TRCPT1_Pos 1 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete 1 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1369 | #define USB_DEVICE_EPINTENSET_TRCPT1 (1 << USB_DEVICE_EPINTENSET_TRCPT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1370 | #define USB_DEVICE_EPINTENSET_TRCPT_Pos 0 /**< \brief (USB_DEVICE_EPINTENSET) Transfer Complete x Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1371 | #define USB_DEVICE_EPINTENSET_TRCPT_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRCPT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1372 | #define USB_DEVICE_EPINTENSET_TRCPT(value) ((USB_DEVICE_EPINTENSET_TRCPT_Msk & ((value) << USB_DEVICE_EPINTENSET_TRCPT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1373 | #define USB_DEVICE_EPINTENSET_TRFAIL0_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 0 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1374 | #define USB_DEVICE_EPINTENSET_TRFAIL0 (1 << USB_DEVICE_EPINTENSET_TRFAIL0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1375 | #define USB_DEVICE_EPINTENSET_TRFAIL1_Pos 3 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow 1 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1376 | #define USB_DEVICE_EPINTENSET_TRFAIL1 (1 << USB_DEVICE_EPINTENSET_TRFAIL1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1377 | #define USB_DEVICE_EPINTENSET_TRFAIL_Pos 2 /**< \brief (USB_DEVICE_EPINTENSET) Error Flow x Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1378 | #define USB_DEVICE_EPINTENSET_TRFAIL_Msk (0x3ul << USB_DEVICE_EPINTENSET_TRFAIL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1379 | #define USB_DEVICE_EPINTENSET_TRFAIL(value) ((USB_DEVICE_EPINTENSET_TRFAIL_Msk & ((value) << USB_DEVICE_EPINTENSET_TRFAIL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1380 | #define USB_DEVICE_EPINTENSET_RXSTP_Pos 4 /**< \brief (USB_DEVICE_EPINTENSET) Received Setup Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1381 | #define USB_DEVICE_EPINTENSET_RXSTP (0x1ul << USB_DEVICE_EPINTENSET_RXSTP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1382 | #define USB_DEVICE_EPINTENSET_STALL0_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall 0 In/out Interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1383 | #define USB_DEVICE_EPINTENSET_STALL0 (1 << USB_DEVICE_EPINTENSET_STALL0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1384 | #define USB_DEVICE_EPINTENSET_STALL1_Pos 6 /**< \brief (USB_DEVICE_EPINTENSET) Stall 1 In/out Interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1385 | #define USB_DEVICE_EPINTENSET_STALL1 (1 << USB_DEVICE_EPINTENSET_STALL1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1386 | #define USB_DEVICE_EPINTENSET_STALL_Pos 5 /**< \brief (USB_DEVICE_EPINTENSET) Stall x In/out Interrupt enable */ |
AnnaBridge | 171:3a7713b1edbc | 1387 | #define USB_DEVICE_EPINTENSET_STALL_Msk (0x3ul << USB_DEVICE_EPINTENSET_STALL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1388 | #define USB_DEVICE_EPINTENSET_STALL(value) ((USB_DEVICE_EPINTENSET_STALL_Msk & ((value) << USB_DEVICE_EPINTENSET_STALL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1389 | #define USB_DEVICE_EPINTENSET_MASK 0x7Ful /**< \brief (USB_DEVICE_EPINTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1390 | |
AnnaBridge | 171:3a7713b1edbc | 1391 | /* -------- USB_HOST_PINTENSET : (USB Offset: 0x109) (R/W 8) HOST HOST_PIPE Pipe Interrupt Flag Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1392 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1393 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1394 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1395 | uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1396 | uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1397 | uint8_t TRFAIL:1; /*!< bit: 2 Error Flow Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1398 | uint8_t PERR:1; /*!< bit: 3 Pipe Error Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1399 | uint8_t TXSTP:1; /*!< bit: 4 Transmit Setup Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1400 | uint8_t STALL:1; /*!< bit: 5 Stall Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1401 | uint8_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1402 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1403 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1404 | uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1405 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1406 | } vec; /*!< Structure used for vec access */ |
AnnaBridge | 171:3a7713b1edbc | 1407 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1408 | } USB_HOST_PINTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 1409 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1410 | |
AnnaBridge | 171:3a7713b1edbc | 1411 | #define USB_HOST_PINTENSET_OFFSET 0x109 /**< \brief (USB_HOST_PINTENSET offset) HOST_PIPE Pipe Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1412 | #define USB_HOST_PINTENSET_RESETVALUE 0x00ul /**< \brief (USB_HOST_PINTENSET reset_value) HOST_PIPE Pipe Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1413 | |
AnnaBridge | 171:3a7713b1edbc | 1414 | #define USB_HOST_PINTENSET_TRCPT0_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 0 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1415 | #define USB_HOST_PINTENSET_TRCPT0 (1 << USB_HOST_PINTENSET_TRCPT0_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1416 | #define USB_HOST_PINTENSET_TRCPT1_Pos 1 /**< \brief (USB_HOST_PINTENSET) Transfer Complete 1 Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1417 | #define USB_HOST_PINTENSET_TRCPT1 (1 << USB_HOST_PINTENSET_TRCPT1_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1418 | #define USB_HOST_PINTENSET_TRCPT_Pos 0 /**< \brief (USB_HOST_PINTENSET) Transfer Complete x Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1419 | #define USB_HOST_PINTENSET_TRCPT_Msk (0x3ul << USB_HOST_PINTENSET_TRCPT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1420 | #define USB_HOST_PINTENSET_TRCPT(value) ((USB_HOST_PINTENSET_TRCPT_Msk & ((value) << USB_HOST_PINTENSET_TRCPT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1421 | #define USB_HOST_PINTENSET_TRFAIL_Pos 2 /**< \brief (USB_HOST_PINTENSET) Error Flow Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1422 | #define USB_HOST_PINTENSET_TRFAIL (0x1ul << USB_HOST_PINTENSET_TRFAIL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1423 | #define USB_HOST_PINTENSET_PERR_Pos 3 /**< \brief (USB_HOST_PINTENSET) Pipe Error Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1424 | #define USB_HOST_PINTENSET_PERR (0x1ul << USB_HOST_PINTENSET_PERR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1425 | #define USB_HOST_PINTENSET_TXSTP_Pos 4 /**< \brief (USB_HOST_PINTENSET) Transmit Setup Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1426 | #define USB_HOST_PINTENSET_TXSTP (0x1ul << USB_HOST_PINTENSET_TXSTP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1427 | #define USB_HOST_PINTENSET_STALL_Pos 5 /**< \brief (USB_HOST_PINTENSET) Stall Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 1428 | #define USB_HOST_PINTENSET_STALL (0x1ul << USB_HOST_PINTENSET_STALL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1429 | #define USB_HOST_PINTENSET_MASK 0x3Ful /**< \brief (USB_HOST_PINTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1430 | |
AnnaBridge | 171:3a7713b1edbc | 1431 | /* -------- USB_DEVICE_ADDR : (USB Offset: 0x000) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1432 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1433 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1434 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1435 | uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1436 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1437 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1438 | } USB_DEVICE_ADDR_Type; |
AnnaBridge | 171:3a7713b1edbc | 1439 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1440 | |
AnnaBridge | 171:3a7713b1edbc | 1441 | #define USB_DEVICE_ADDR_OFFSET 0x000 /**< \brief (USB_DEVICE_ADDR offset) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1442 | |
AnnaBridge | 171:3a7713b1edbc | 1443 | #define USB_DEVICE_ADDR_ADDR_Pos 0 /**< \brief (USB_DEVICE_ADDR) Adress of data buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1444 | #define USB_DEVICE_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_DEVICE_ADDR_ADDR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1445 | #define USB_DEVICE_ADDR_ADDR(value) ((USB_DEVICE_ADDR_ADDR_Msk & ((value) << USB_DEVICE_ADDR_ADDR_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1446 | #define USB_DEVICE_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_ADDR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1447 | |
AnnaBridge | 171:3a7713b1edbc | 1448 | /* -------- USB_HOST_ADDR : (USB Offset: 0x000) (R/W 32) HOST HOST_DESC_BANK Host Bank, Adress of Data Buffer -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1449 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1450 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1451 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1452 | uint32_t ADDR:32; /*!< bit: 0..31 Adress of data buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1453 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1454 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1455 | } USB_HOST_ADDR_Type; |
AnnaBridge | 171:3a7713b1edbc | 1456 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1457 | |
AnnaBridge | 171:3a7713b1edbc | 1458 | #define USB_HOST_ADDR_OFFSET 0x000 /**< \brief (USB_HOST_ADDR offset) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1459 | |
AnnaBridge | 171:3a7713b1edbc | 1460 | #define USB_HOST_ADDR_ADDR_Pos 0 /**< \brief (USB_HOST_ADDR) Adress of data buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1461 | #define USB_HOST_ADDR_ADDR_Msk (0xFFFFFFFFul << USB_HOST_ADDR_ADDR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1462 | #define USB_HOST_ADDR_ADDR(value) ((USB_HOST_ADDR_ADDR_Msk & ((value) << USB_HOST_ADDR_ADDR_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1463 | #define USB_HOST_ADDR_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_ADDR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1464 | |
AnnaBridge | 171:3a7713b1edbc | 1465 | /* -------- USB_DEVICE_PCKSIZE : (USB Offset: 0x004) (R/W 32) DEVICE DEVICE_DESC_BANK Endpoint Bank, Packet Size -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1466 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1467 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1468 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1469 | uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ |
AnnaBridge | 171:3a7713b1edbc | 1470 | uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ |
AnnaBridge | 171:3a7713b1edbc | 1471 | uint32_t SIZE:3; /*!< bit: 28..30 Enpoint size */ |
AnnaBridge | 171:3a7713b1edbc | 1472 | uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ |
AnnaBridge | 171:3a7713b1edbc | 1473 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1474 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1475 | } USB_DEVICE_PCKSIZE_Type; |
AnnaBridge | 171:3a7713b1edbc | 1476 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1477 | |
AnnaBridge | 171:3a7713b1edbc | 1478 | #define USB_DEVICE_PCKSIZE_OFFSET 0x004 /**< \brief (USB_DEVICE_PCKSIZE offset) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ |
AnnaBridge | 171:3a7713b1edbc | 1479 | |
AnnaBridge | 171:3a7713b1edbc | 1480 | #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_DEVICE_PCKSIZE) Byte Count */ |
AnnaBridge | 171:3a7713b1edbc | 1481 | #define USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1482 | #define USB_DEVICE_PCKSIZE_BYTE_COUNT(value) ((USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1483 | #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_DEVICE_PCKSIZE) Multi Packet In or Out size */ |
AnnaBridge | 171:3a7713b1edbc | 1484 | #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1485 | #define USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1486 | #define USB_DEVICE_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_DEVICE_PCKSIZE) Enpoint size */ |
AnnaBridge | 171:3a7713b1edbc | 1487 | #define USB_DEVICE_PCKSIZE_SIZE_Msk (0x7ul << USB_DEVICE_PCKSIZE_SIZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1488 | #define USB_DEVICE_PCKSIZE_SIZE(value) ((USB_DEVICE_PCKSIZE_SIZE_Msk & ((value) << USB_DEVICE_PCKSIZE_SIZE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1489 | #define USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_DEVICE_PCKSIZE) Automatic Zero Length Packet */ |
AnnaBridge | 171:3a7713b1edbc | 1490 | #define USB_DEVICE_PCKSIZE_AUTO_ZLP (0x1ul << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1491 | #define USB_DEVICE_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_DEVICE_PCKSIZE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1492 | |
AnnaBridge | 171:3a7713b1edbc | 1493 | /* -------- USB_HOST_PCKSIZE : (USB Offset: 0x004) (R/W 32) HOST HOST_DESC_BANK Host Bank, Packet Size -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1494 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1495 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1496 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1497 | uint32_t BYTE_COUNT:14; /*!< bit: 0..13 Byte Count */ |
AnnaBridge | 171:3a7713b1edbc | 1498 | uint32_t MULTI_PACKET_SIZE:14; /*!< bit: 14..27 Multi Packet In or Out size */ |
AnnaBridge | 171:3a7713b1edbc | 1499 | uint32_t SIZE:3; /*!< bit: 28..30 Pipe size */ |
AnnaBridge | 171:3a7713b1edbc | 1500 | uint32_t AUTO_ZLP:1; /*!< bit: 31 Automatic Zero Length Packet */ |
AnnaBridge | 171:3a7713b1edbc | 1501 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1502 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1503 | } USB_HOST_PCKSIZE_Type; |
AnnaBridge | 171:3a7713b1edbc | 1504 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1505 | |
AnnaBridge | 171:3a7713b1edbc | 1506 | #define USB_HOST_PCKSIZE_OFFSET 0x004 /**< \brief (USB_HOST_PCKSIZE offset) HOST_DESC_BANK Host Bank, Packet Size */ |
AnnaBridge | 171:3a7713b1edbc | 1507 | |
AnnaBridge | 171:3a7713b1edbc | 1508 | #define USB_HOST_PCKSIZE_BYTE_COUNT_Pos 0 /**< \brief (USB_HOST_PCKSIZE) Byte Count */ |
AnnaBridge | 171:3a7713b1edbc | 1509 | #define USB_HOST_PCKSIZE_BYTE_COUNT_Msk (0x3FFFul << USB_HOST_PCKSIZE_BYTE_COUNT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1510 | #define USB_HOST_PCKSIZE_BYTE_COUNT(value) ((USB_HOST_PCKSIZE_BYTE_COUNT_Msk & ((value) << USB_HOST_PCKSIZE_BYTE_COUNT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1511 | #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos 14 /**< \brief (USB_HOST_PCKSIZE) Multi Packet In or Out size */ |
AnnaBridge | 171:3a7713b1edbc | 1512 | #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk (0x3FFFul << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1513 | #define USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(value) ((USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1514 | #define USB_HOST_PCKSIZE_SIZE_Pos 28 /**< \brief (USB_HOST_PCKSIZE) Pipe size */ |
AnnaBridge | 171:3a7713b1edbc | 1515 | #define USB_HOST_PCKSIZE_SIZE_Msk (0x7ul << USB_HOST_PCKSIZE_SIZE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1516 | #define USB_HOST_PCKSIZE_SIZE(value) ((USB_HOST_PCKSIZE_SIZE_Msk & ((value) << USB_HOST_PCKSIZE_SIZE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1517 | #define USB_HOST_PCKSIZE_AUTO_ZLP_Pos 31 /**< \brief (USB_HOST_PCKSIZE) Automatic Zero Length Packet */ |
AnnaBridge | 171:3a7713b1edbc | 1518 | #define USB_HOST_PCKSIZE_AUTO_ZLP (0x1ul << USB_HOST_PCKSIZE_AUTO_ZLP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1519 | #define USB_HOST_PCKSIZE_MASK 0xFFFFFFFFul /**< \brief (USB_HOST_PCKSIZE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1520 | |
AnnaBridge | 171:3a7713b1edbc | 1521 | /* -------- USB_DEVICE_EXTREG : (USB Offset: 0x008) (R/W 16) DEVICE DEVICE_DESC_BANK Endpoint Bank, Extended -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1522 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1523 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1524 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1525 | uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1526 | uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1527 | uint16_t :1; /*!< bit: 15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1528 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1529 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1530 | } USB_DEVICE_EXTREG_Type; |
AnnaBridge | 171:3a7713b1edbc | 1531 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1532 | |
AnnaBridge | 171:3a7713b1edbc | 1533 | #define USB_DEVICE_EXTREG_OFFSET 0x008 /**< \brief (USB_DEVICE_EXTREG offset) DEVICE_DESC_BANK Endpoint Bank, Extended */ |
AnnaBridge | 171:3a7713b1edbc | 1534 | |
AnnaBridge | 171:3a7713b1edbc | 1535 | #define USB_DEVICE_EXTREG_SUBPID_Pos 0 /**< \brief (USB_DEVICE_EXTREG) SUBPID field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1536 | #define USB_DEVICE_EXTREG_SUBPID_Msk (0xFul << USB_DEVICE_EXTREG_SUBPID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1537 | #define USB_DEVICE_EXTREG_SUBPID(value) ((USB_DEVICE_EXTREG_SUBPID_Msk & ((value) << USB_DEVICE_EXTREG_SUBPID_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1538 | #define USB_DEVICE_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_DEVICE_EXTREG) Variable field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1539 | #define USB_DEVICE_EXTREG_VARIABLE_Msk (0x7FFul << USB_DEVICE_EXTREG_VARIABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1540 | #define USB_DEVICE_EXTREG_VARIABLE(value) ((USB_DEVICE_EXTREG_VARIABLE_Msk & ((value) << USB_DEVICE_EXTREG_VARIABLE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1541 | #define USB_DEVICE_EXTREG_MASK 0x7FFFul /**< \brief (USB_DEVICE_EXTREG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1542 | |
AnnaBridge | 171:3a7713b1edbc | 1543 | /* -------- USB_HOST_EXTREG : (USB Offset: 0x008) (R/W 16) HOST HOST_DESC_BANK Host Bank, Extended -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1544 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1545 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1546 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1547 | uint16_t SUBPID:4; /*!< bit: 0.. 3 SUBPID field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1548 | uint16_t VARIABLE:11; /*!< bit: 4..14 Variable field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1549 | uint16_t :1; /*!< bit: 15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1550 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1551 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1552 | } USB_HOST_EXTREG_Type; |
AnnaBridge | 171:3a7713b1edbc | 1553 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1554 | |
AnnaBridge | 171:3a7713b1edbc | 1555 | #define USB_HOST_EXTREG_OFFSET 0x008 /**< \brief (USB_HOST_EXTREG offset) HOST_DESC_BANK Host Bank, Extended */ |
AnnaBridge | 171:3a7713b1edbc | 1556 | |
AnnaBridge | 171:3a7713b1edbc | 1557 | #define USB_HOST_EXTREG_SUBPID_Pos 0 /**< \brief (USB_HOST_EXTREG) SUBPID field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1558 | #define USB_HOST_EXTREG_SUBPID_Msk (0xFul << USB_HOST_EXTREG_SUBPID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1559 | #define USB_HOST_EXTREG_SUBPID(value) ((USB_HOST_EXTREG_SUBPID_Msk & ((value) << USB_HOST_EXTREG_SUBPID_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1560 | #define USB_HOST_EXTREG_VARIABLE_Pos 4 /**< \brief (USB_HOST_EXTREG) Variable field send with extended token */ |
AnnaBridge | 171:3a7713b1edbc | 1561 | #define USB_HOST_EXTREG_VARIABLE_Msk (0x7FFul << USB_HOST_EXTREG_VARIABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1562 | #define USB_HOST_EXTREG_VARIABLE(value) ((USB_HOST_EXTREG_VARIABLE_Msk & ((value) << USB_HOST_EXTREG_VARIABLE_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1563 | #define USB_HOST_EXTREG_MASK 0x7FFFul /**< \brief (USB_HOST_EXTREG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1564 | |
AnnaBridge | 171:3a7713b1edbc | 1565 | /* -------- USB_DEVICE_STATUS_BK : (USB Offset: 0x00A) (R/W 8) DEVICE DEVICE_DESC_BANK Enpoint Bank, Status of Bank -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1566 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1567 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1568 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1569 | uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ |
AnnaBridge | 171:3a7713b1edbc | 1570 | uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ |
AnnaBridge | 171:3a7713b1edbc | 1571 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1572 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1573 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1574 | } USB_DEVICE_STATUS_BK_Type; |
AnnaBridge | 171:3a7713b1edbc | 1575 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1576 | |
AnnaBridge | 171:3a7713b1edbc | 1577 | #define USB_DEVICE_STATUS_BK_OFFSET 0x00A /**< \brief (USB_DEVICE_STATUS_BK offset) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1578 | |
AnnaBridge | 171:3a7713b1edbc | 1579 | #define USB_DEVICE_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_DEVICE_STATUS_BK) CRC Error Status */ |
AnnaBridge | 171:3a7713b1edbc | 1580 | #define USB_DEVICE_STATUS_BK_CRCERR (0x1ul << USB_DEVICE_STATUS_BK_CRCERR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1581 | #define USB_DEVICE_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_DEVICE_STATUS_BK) Error Flow Status */ |
AnnaBridge | 171:3a7713b1edbc | 1582 | #define USB_DEVICE_STATUS_BK_ERRORFLOW (0x1ul << USB_DEVICE_STATUS_BK_ERRORFLOW_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1583 | #define USB_DEVICE_STATUS_BK_MASK 0x03ul /**< \brief (USB_DEVICE_STATUS_BK) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1584 | |
AnnaBridge | 171:3a7713b1edbc | 1585 | /* -------- USB_HOST_STATUS_BK : (USB Offset: 0x00A) (R/W 8) HOST HOST_DESC_BANK Host Bank, Status of Bank -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1586 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1587 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1588 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1589 | uint8_t CRCERR:1; /*!< bit: 0 CRC Error Status */ |
AnnaBridge | 171:3a7713b1edbc | 1590 | uint8_t ERRORFLOW:1; /*!< bit: 1 Error Flow Status */ |
AnnaBridge | 171:3a7713b1edbc | 1591 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1592 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1593 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1594 | } USB_HOST_STATUS_BK_Type; |
AnnaBridge | 171:3a7713b1edbc | 1595 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1596 | |
AnnaBridge | 171:3a7713b1edbc | 1597 | #define USB_HOST_STATUS_BK_OFFSET 0x00A /**< \brief (USB_HOST_STATUS_BK offset) HOST_DESC_BANK Host Bank, Status of Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1598 | |
AnnaBridge | 171:3a7713b1edbc | 1599 | #define USB_HOST_STATUS_BK_CRCERR_Pos 0 /**< \brief (USB_HOST_STATUS_BK) CRC Error Status */ |
AnnaBridge | 171:3a7713b1edbc | 1600 | #define USB_HOST_STATUS_BK_CRCERR (0x1ul << USB_HOST_STATUS_BK_CRCERR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1601 | #define USB_HOST_STATUS_BK_ERRORFLOW_Pos 1 /**< \brief (USB_HOST_STATUS_BK) Error Flow Status */ |
AnnaBridge | 171:3a7713b1edbc | 1602 | #define USB_HOST_STATUS_BK_ERRORFLOW (0x1ul << USB_HOST_STATUS_BK_ERRORFLOW_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1603 | #define USB_HOST_STATUS_BK_MASK 0x03ul /**< \brief (USB_HOST_STATUS_BK) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1604 | |
AnnaBridge | 171:3a7713b1edbc | 1605 | /* -------- USB_HOST_CTRL_PIPE : (USB Offset: 0x00C) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Control Pipe -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1606 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1607 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1608 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1609 | uint16_t PDADDR:7; /*!< bit: 0.. 6 Pipe Device Adress */ |
AnnaBridge | 171:3a7713b1edbc | 1610 | uint16_t :1; /*!< bit: 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1611 | uint16_t PEPNUM:4; /*!< bit: 8..11 Pipe Endpoint Number */ |
AnnaBridge | 171:3a7713b1edbc | 1612 | uint16_t PERMAX:4; /*!< bit: 12..15 Pipe Error Max Number */ |
AnnaBridge | 171:3a7713b1edbc | 1613 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1614 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1615 | } USB_HOST_CTRL_PIPE_Type; |
AnnaBridge | 171:3a7713b1edbc | 1616 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1617 | |
AnnaBridge | 171:3a7713b1edbc | 1618 | #define USB_HOST_CTRL_PIPE_OFFSET 0x00C /**< \brief (USB_HOST_CTRL_PIPE offset) HOST_DESC_BANK Host Bank, Host Control Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 1619 | #define USB_HOST_CTRL_PIPE_RESETVALUE 0x0000ul /**< \brief (USB_HOST_CTRL_PIPE reset_value) HOST_DESC_BANK Host Bank, Host Control Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 1620 | |
AnnaBridge | 171:3a7713b1edbc | 1621 | #define USB_HOST_CTRL_PIPE_PDADDR_Pos 0 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Device Adress */ |
AnnaBridge | 171:3a7713b1edbc | 1622 | #define USB_HOST_CTRL_PIPE_PDADDR_Msk (0x7Ful << USB_HOST_CTRL_PIPE_PDADDR_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1623 | #define USB_HOST_CTRL_PIPE_PDADDR(value) ((USB_HOST_CTRL_PIPE_PDADDR_Msk & ((value) << USB_HOST_CTRL_PIPE_PDADDR_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1624 | #define USB_HOST_CTRL_PIPE_PEPNUM_Pos 8 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Endpoint Number */ |
AnnaBridge | 171:3a7713b1edbc | 1625 | #define USB_HOST_CTRL_PIPE_PEPNUM_Msk (0xFul << USB_HOST_CTRL_PIPE_PEPNUM_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1626 | #define USB_HOST_CTRL_PIPE_PEPNUM(value) ((USB_HOST_CTRL_PIPE_PEPNUM_Msk & ((value) << USB_HOST_CTRL_PIPE_PEPNUM_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1627 | #define USB_HOST_CTRL_PIPE_PERMAX_Pos 12 /**< \brief (USB_HOST_CTRL_PIPE) Pipe Error Max Number */ |
AnnaBridge | 171:3a7713b1edbc | 1628 | #define USB_HOST_CTRL_PIPE_PERMAX_Msk (0xFul << USB_HOST_CTRL_PIPE_PERMAX_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1629 | #define USB_HOST_CTRL_PIPE_PERMAX(value) ((USB_HOST_CTRL_PIPE_PERMAX_Msk & ((value) << USB_HOST_CTRL_PIPE_PERMAX_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1630 | #define USB_HOST_CTRL_PIPE_MASK 0xFF7Ful /**< \brief (USB_HOST_CTRL_PIPE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1631 | |
AnnaBridge | 171:3a7713b1edbc | 1632 | /* -------- USB_HOST_STATUS_PIPE : (USB Offset: 0x00E) (R/W 16) HOST HOST_DESC_BANK Host Bank, Host Status Pipe -------- */ |
AnnaBridge | 171:3a7713b1edbc | 1633 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1634 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1635 | struct { |
AnnaBridge | 171:3a7713b1edbc | 1636 | uint16_t DTGLER:1; /*!< bit: 0 Data Toggle Error */ |
AnnaBridge | 171:3a7713b1edbc | 1637 | uint16_t DAPIDER:1; /*!< bit: 1 Data PID Error */ |
AnnaBridge | 171:3a7713b1edbc | 1638 | uint16_t PIDER:1; /*!< bit: 2 PID Error */ |
AnnaBridge | 171:3a7713b1edbc | 1639 | uint16_t TOUTER:1; /*!< bit: 3 Time Out Error */ |
AnnaBridge | 171:3a7713b1edbc | 1640 | uint16_t CRC16ER:1; /*!< bit: 4 CRC16 Error */ |
AnnaBridge | 171:3a7713b1edbc | 1641 | uint16_t ERCNT:3; /*!< bit: 5.. 7 Pipe Error Count */ |
AnnaBridge | 171:3a7713b1edbc | 1642 | uint16_t :8; /*!< bit: 8..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 1643 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 1644 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 1645 | } USB_HOST_STATUS_PIPE_Type; |
AnnaBridge | 171:3a7713b1edbc | 1646 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1647 | |
AnnaBridge | 171:3a7713b1edbc | 1648 | #define USB_HOST_STATUS_PIPE_OFFSET 0x00E /**< \brief (USB_HOST_STATUS_PIPE offset) HOST_DESC_BANK Host Bank, Host Status Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 1649 | |
AnnaBridge | 171:3a7713b1edbc | 1650 | #define USB_HOST_STATUS_PIPE_DTGLER_Pos 0 /**< \brief (USB_HOST_STATUS_PIPE) Data Toggle Error */ |
AnnaBridge | 171:3a7713b1edbc | 1651 | #define USB_HOST_STATUS_PIPE_DTGLER (0x1ul << USB_HOST_STATUS_PIPE_DTGLER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1652 | #define USB_HOST_STATUS_PIPE_DAPIDER_Pos 1 /**< \brief (USB_HOST_STATUS_PIPE) Data PID Error */ |
AnnaBridge | 171:3a7713b1edbc | 1653 | #define USB_HOST_STATUS_PIPE_DAPIDER (0x1ul << USB_HOST_STATUS_PIPE_DAPIDER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1654 | #define USB_HOST_STATUS_PIPE_PIDER_Pos 2 /**< \brief (USB_HOST_STATUS_PIPE) PID Error */ |
AnnaBridge | 171:3a7713b1edbc | 1655 | #define USB_HOST_STATUS_PIPE_PIDER (0x1ul << USB_HOST_STATUS_PIPE_PIDER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1656 | #define USB_HOST_STATUS_PIPE_TOUTER_Pos 3 /**< \brief (USB_HOST_STATUS_PIPE) Time Out Error */ |
AnnaBridge | 171:3a7713b1edbc | 1657 | #define USB_HOST_STATUS_PIPE_TOUTER (0x1ul << USB_HOST_STATUS_PIPE_TOUTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1658 | #define USB_HOST_STATUS_PIPE_CRC16ER_Pos 4 /**< \brief (USB_HOST_STATUS_PIPE) CRC16 Error */ |
AnnaBridge | 171:3a7713b1edbc | 1659 | #define USB_HOST_STATUS_PIPE_CRC16ER (0x1ul << USB_HOST_STATUS_PIPE_CRC16ER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1660 | #define USB_HOST_STATUS_PIPE_ERCNT_Pos 5 /**< \brief (USB_HOST_STATUS_PIPE) Pipe Error Count */ |
AnnaBridge | 171:3a7713b1edbc | 1661 | #define USB_HOST_STATUS_PIPE_ERCNT_Msk (0x7ul << USB_HOST_STATUS_PIPE_ERCNT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 1662 | #define USB_HOST_STATUS_PIPE_ERCNT(value) ((USB_HOST_STATUS_PIPE_ERCNT_Msk & ((value) << USB_HOST_STATUS_PIPE_ERCNT_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 1663 | #define USB_HOST_STATUS_PIPE_MASK 0x00FFul /**< \brief (USB_HOST_STATUS_PIPE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 1664 | |
AnnaBridge | 171:3a7713b1edbc | 1665 | /** \brief UsbDeviceDescBank SRAM registers */ |
AnnaBridge | 171:3a7713b1edbc | 1666 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1667 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 1668 | __IO USB_DEVICE_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Adress of Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1669 | __IO USB_DEVICE_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) DEVICE_DESC_BANK Endpoint Bank, Packet Size */ |
AnnaBridge | 171:3a7713b1edbc | 1670 | __IO USB_DEVICE_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) DEVICE_DESC_BANK Endpoint Bank, Extended */ |
AnnaBridge | 171:3a7713b1edbc | 1671 | __IO USB_DEVICE_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) DEVICE_DESC_BANK Enpoint Bank, Status of Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1672 | RoReg8 Reserved1[0x5]; |
AnnaBridge | 171:3a7713b1edbc | 1673 | } UsbDeviceDescBank; |
AnnaBridge | 171:3a7713b1edbc | 1674 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1675 | |
AnnaBridge | 171:3a7713b1edbc | 1676 | /** \brief UsbHostDescBank SRAM registers */ |
AnnaBridge | 171:3a7713b1edbc | 1677 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1678 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 1679 | __IO USB_HOST_ADDR_Type ADDR; /**< \brief Offset: 0x000 (R/W 32) HOST_DESC_BANK Host Bank, Adress of Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 1680 | __IO USB_HOST_PCKSIZE_Type PCKSIZE; /**< \brief Offset: 0x004 (R/W 32) HOST_DESC_BANK Host Bank, Packet Size */ |
AnnaBridge | 171:3a7713b1edbc | 1681 | __IO USB_HOST_EXTREG_Type EXTREG; /**< \brief Offset: 0x008 (R/W 16) HOST_DESC_BANK Host Bank, Extended */ |
AnnaBridge | 171:3a7713b1edbc | 1682 | __IO USB_HOST_STATUS_BK_Type STATUS_BK; /**< \brief Offset: 0x00A (R/W 8) HOST_DESC_BANK Host Bank, Status of Bank */ |
AnnaBridge | 171:3a7713b1edbc | 1683 | RoReg8 Reserved1[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 1684 | __IO USB_HOST_CTRL_PIPE_Type CTRL_PIPE; /**< \brief Offset: 0x00C (R/W 16) HOST_DESC_BANK Host Bank, Host Control Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 1685 | __IO USB_HOST_STATUS_PIPE_Type STATUS_PIPE; /**< \brief Offset: 0x00E (R/W 16) HOST_DESC_BANK Host Bank, Host Status Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 1686 | } UsbHostDescBank; |
AnnaBridge | 171:3a7713b1edbc | 1687 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1688 | |
AnnaBridge | 171:3a7713b1edbc | 1689 | /** \brief UsbDeviceEndpoint hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 1690 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1691 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 1692 | __IO USB_DEVICE_EPCFG_Type EPCFG; /**< \brief Offset: 0x000 (R/W 8) DEVICE_ENDPOINT End Point Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 1693 | RoReg8 Reserved1[0x3]; |
AnnaBridge | 171:3a7713b1edbc | 1694 | __O USB_DEVICE_EPSTATUSCLR_Type EPSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1695 | __O USB_DEVICE_EPSTATUSSET_Type EPSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) DEVICE_ENDPOINT End Point Pipe Status Set */ |
AnnaBridge | 171:3a7713b1edbc | 1696 | __I USB_DEVICE_EPSTATUS_Type EPSTATUS; /**< \brief Offset: 0x006 (R/ 8) DEVICE_ENDPOINT End Point Pipe Status */ |
AnnaBridge | 171:3a7713b1edbc | 1697 | __IO USB_DEVICE_EPINTFLAG_Type EPINTFLAG; /**< \brief Offset: 0x007 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1698 | __IO USB_DEVICE_EPINTENCLR_Type EPINTENCLR; /**< \brief Offset: 0x008 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Clear Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1699 | __IO USB_DEVICE_EPINTENSET_Type EPINTENSET; /**< \brief Offset: 0x009 (R/W 8) DEVICE_ENDPOINT End Point Interrupt Set Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1700 | RoReg8 Reserved2[0x16]; |
AnnaBridge | 171:3a7713b1edbc | 1701 | } UsbDeviceEndpoint; |
AnnaBridge | 171:3a7713b1edbc | 1702 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1703 | |
AnnaBridge | 171:3a7713b1edbc | 1704 | /** \brief UsbHostPipe hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 1705 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1706 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 1707 | __IO USB_HOST_PCFG_Type PCFG; /**< \brief Offset: 0x000 (R/W 8) HOST_PIPE End Point Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 1708 | RoReg8 Reserved1[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1709 | __IO USB_HOST_BINTERVAL_Type BINTERVAL; /**< \brief Offset: 0x003 (R/W 8) HOST_PIPE Bus Access Period of Pipe */ |
AnnaBridge | 171:3a7713b1edbc | 1710 | __O USB_HOST_PSTATUSCLR_Type PSTATUSCLR; /**< \brief Offset: 0x004 ( /W 8) HOST_PIPE End Point Pipe Status Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1711 | __O USB_HOST_PSTATUSSET_Type PSTATUSSET; /**< \brief Offset: 0x005 ( /W 8) HOST_PIPE End Point Pipe Status Set */ |
AnnaBridge | 171:3a7713b1edbc | 1712 | __I USB_HOST_PSTATUS_Type PSTATUS; /**< \brief Offset: 0x006 (R/ 8) HOST_PIPE End Point Pipe Status */ |
AnnaBridge | 171:3a7713b1edbc | 1713 | __IO USB_HOST_PINTFLAG_Type PINTFLAG; /**< \brief Offset: 0x007 (R/W 8) HOST_PIPE Pipe Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1714 | __IO USB_HOST_PINTENCLR_Type PINTENCLR; /**< \brief Offset: 0x008 (R/W 8) HOST_PIPE Pipe Interrupt Flag Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1715 | __IO USB_HOST_PINTENSET_Type PINTENSET; /**< \brief Offset: 0x009 (R/W 8) HOST_PIPE Pipe Interrupt Flag Set */ |
AnnaBridge | 171:3a7713b1edbc | 1716 | RoReg8 Reserved2[0x16]; |
AnnaBridge | 171:3a7713b1edbc | 1717 | } UsbHostPipe; |
AnnaBridge | 171:3a7713b1edbc | 1718 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1719 | |
AnnaBridge | 171:3a7713b1edbc | 1720 | /** \brief USB_DEVICE APB hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 1721 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1722 | typedef struct { /* USB is Device */ |
AnnaBridge | 171:3a7713b1edbc | 1723 | __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 1724 | RoReg8 Reserved1[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 1725 | __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1726 | __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ |
AnnaBridge | 171:3a7713b1edbc | 1727 | RoReg8 Reserved2[0x4]; |
AnnaBridge | 171:3a7713b1edbc | 1728 | __IO USB_DEVICE_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) DEVICE Control B */ |
AnnaBridge | 171:3a7713b1edbc | 1729 | __IO USB_DEVICE_DADD_Type DADD; /**< \brief Offset: 0x00A (R/W 8) DEVICE Device Address */ |
AnnaBridge | 171:3a7713b1edbc | 1730 | RoReg8 Reserved3[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 1731 | __I USB_DEVICE_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/ 8) DEVICE Status */ |
AnnaBridge | 171:3a7713b1edbc | 1732 | __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ |
AnnaBridge | 171:3a7713b1edbc | 1733 | RoReg8 Reserved4[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1734 | __I USB_DEVICE_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/ 16) DEVICE Device Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 1735 | RoReg8 Reserved5[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1736 | __IO USB_DEVICE_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) DEVICE Device Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1737 | RoReg8 Reserved6[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1738 | __IO USB_DEVICE_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) DEVICE Device Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 1739 | RoReg8 Reserved7[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1740 | __IO USB_DEVICE_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) DEVICE Device Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1741 | RoReg8 Reserved8[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1742 | __I USB_DEVICE_EPINTSMRY_Type EPINTSMRY; /**< \brief Offset: 0x020 (R/ 16) DEVICE End Point Interrupt Summary */ |
AnnaBridge | 171:3a7713b1edbc | 1743 | RoReg8 Reserved9[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1744 | __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ |
AnnaBridge | 171:3a7713b1edbc | 1745 | __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 1746 | RoReg8 Reserved10[0xD6]; |
AnnaBridge | 171:3a7713b1edbc | 1747 | UsbDeviceEndpoint DeviceEndpoint[8]; /**< \brief Offset: 0x100 UsbDeviceEndpoint groups [EPT_NUM] */ |
AnnaBridge | 171:3a7713b1edbc | 1748 | } UsbDevice; |
AnnaBridge | 171:3a7713b1edbc | 1749 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1750 | |
AnnaBridge | 171:3a7713b1edbc | 1751 | /** \brief USB_HOST hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 1752 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1753 | typedef struct { /* USB is Host */ |
AnnaBridge | 171:3a7713b1edbc | 1754 | __IO USB_CTRLA_Type CTRLA; /**< \brief Offset: 0x000 (R/W 8) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 1755 | RoReg8 Reserved1[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 1756 | __I USB_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x002 (R/ 8) Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 1757 | __IO USB_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x003 (R/W 8) USB Quality Of Service */ |
AnnaBridge | 171:3a7713b1edbc | 1758 | RoReg8 Reserved2[0x4]; |
AnnaBridge | 171:3a7713b1edbc | 1759 | __IO USB_HOST_CTRLB_Type CTRLB; /**< \brief Offset: 0x008 (R/W 16) HOST Control B */ |
AnnaBridge | 171:3a7713b1edbc | 1760 | __IO USB_HOST_HSOFC_Type HSOFC; /**< \brief Offset: 0x00A (R/W 8) HOST Host Start Of Frame Control */ |
AnnaBridge | 171:3a7713b1edbc | 1761 | RoReg8 Reserved3[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 1762 | __IO USB_HOST_STATUS_Type STATUS; /**< \brief Offset: 0x00C (R/W 8) HOST Status */ |
AnnaBridge | 171:3a7713b1edbc | 1763 | __I USB_FSMSTATUS_Type FSMSTATUS; /**< \brief Offset: 0x00D (R/ 8) Finite State Machine Status */ |
AnnaBridge | 171:3a7713b1edbc | 1764 | RoReg8 Reserved4[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1765 | __IO USB_HOST_FNUM_Type FNUM; /**< \brief Offset: 0x010 (R/W 16) HOST Host Frame Number */ |
AnnaBridge | 171:3a7713b1edbc | 1766 | __I USB_HOST_FLENHIGH_Type FLENHIGH; /**< \brief Offset: 0x012 (R/ 8) HOST Host Frame Length */ |
AnnaBridge | 171:3a7713b1edbc | 1767 | RoReg8 Reserved5[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 1768 | __IO USB_HOST_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x014 (R/W 16) HOST Host Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 1769 | RoReg8 Reserved6[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1770 | __IO USB_HOST_INTENSET_Type INTENSET; /**< \brief Offset: 0x018 (R/W 16) HOST Host Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 1771 | RoReg8 Reserved7[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1772 | __IO USB_HOST_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x01C (R/W 16) HOST Host Interrupt Flag */ |
AnnaBridge | 171:3a7713b1edbc | 1773 | RoReg8 Reserved8[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1774 | __I USB_HOST_PINTSMRY_Type PINTSMRY; /**< \brief Offset: 0x020 (R/ 16) HOST Pipe Interrupt Summary */ |
AnnaBridge | 171:3a7713b1edbc | 1775 | RoReg8 Reserved9[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 1776 | __IO USB_DESCADD_Type DESCADD; /**< \brief Offset: 0x024 (R/W 32) Descriptor Address */ |
AnnaBridge | 171:3a7713b1edbc | 1777 | __IO USB_PADCAL_Type PADCAL; /**< \brief Offset: 0x028 (R/W 16) USB PAD Calibration */ |
AnnaBridge | 171:3a7713b1edbc | 1778 | RoReg8 Reserved10[0xD6]; |
AnnaBridge | 171:3a7713b1edbc | 1779 | UsbHostPipe HostPipe[8]; /**< \brief Offset: 0x100 UsbHostPipe groups [EPT_NUM*HOST_IMPLEMENTED] */ |
AnnaBridge | 171:3a7713b1edbc | 1780 | } UsbHost; |
AnnaBridge | 171:3a7713b1edbc | 1781 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1782 | |
AnnaBridge | 171:3a7713b1edbc | 1783 | /** \brief USB_DEVICE Descriptor SRAM registers */ |
AnnaBridge | 171:3a7713b1edbc | 1784 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1785 | typedef struct { /* USB is Device */ |
AnnaBridge | 171:3a7713b1edbc | 1786 | UsbDeviceDescBank DeviceDescBank[2]; /**< \brief Offset: 0x000 UsbDeviceDescBank groups */ |
AnnaBridge | 171:3a7713b1edbc | 1787 | } UsbDeviceDescriptor; |
AnnaBridge | 171:3a7713b1edbc | 1788 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1789 | |
AnnaBridge | 171:3a7713b1edbc | 1790 | /** \brief USB_HOST Descriptor SRAM registers */ |
AnnaBridge | 171:3a7713b1edbc | 1791 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1792 | typedef struct { /* USB is Host */ |
AnnaBridge | 171:3a7713b1edbc | 1793 | UsbHostDescBank HostDescBank[2]; /**< \brief Offset: 0x000 UsbHostDescBank groups [2*HOST_IMPLEMENTED] */ |
AnnaBridge | 171:3a7713b1edbc | 1794 | } UsbHostDescriptor; |
AnnaBridge | 171:3a7713b1edbc | 1795 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1796 | #define SECTION_USB_DESCRIPTOR |
AnnaBridge | 171:3a7713b1edbc | 1797 | |
AnnaBridge | 171:3a7713b1edbc | 1798 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 1799 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 1800 | UsbDevice DEVICE; /**< \brief Offset: 0x000 USB is Device */ |
AnnaBridge | 171:3a7713b1edbc | 1801 | UsbHost HOST; /**< \brief Offset: 0x000 USB is Host */ |
AnnaBridge | 171:3a7713b1edbc | 1802 | } Usb; |
AnnaBridge | 171:3a7713b1edbc | 1803 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 1804 | |
AnnaBridge | 171:3a7713b1edbc | 1805 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 1806 | |
AnnaBridge | 171:3a7713b1edbc | 1807 | #endif /* _SAMD21_USB_COMPONENT_ */ |