The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.
Dependents: hello SerialTestv11 SerialTestv12 Sierpinski ... more
mbed 2
This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.
TARGET_SAMD21G18A/TOOLCHAIN_GCC_ARM/comp_gclk.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Component description for GCLK |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_GCLK_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_GCLK_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | /** SOFTWARE API DEFINITION FOR GCLK */ |
AnnaBridge | 171:3a7713b1edbc | 52 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 53 | /** \addtogroup SAMD21_GCLK Generic Clock Generator */ |
AnnaBridge | 171:3a7713b1edbc | 54 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | #define GCLK_U2102 |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REV_GCLK 0x210 |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | /* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 61 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 62 | struct { |
AnnaBridge | 171:3a7713b1edbc | 63 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
AnnaBridge | 171:3a7713b1edbc | 64 | uint8_t :7; /*!< bit: 1.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 65 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 66 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 67 | } GCLK_CTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 68 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 69 | |
AnnaBridge | 171:3a7713b1edbc | 70 | #define GCLK_CTRL_OFFSET 0x0 /**< \brief (GCLK_CTRL offset) Control */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define GCLK_CTRL_RESETVALUE 0x00ul /**< \brief (GCLK_CTRL reset_value) Control */ |
AnnaBridge | 171:3a7713b1edbc | 72 | |
AnnaBridge | 171:3a7713b1edbc | 73 | #define GCLK_CTRL_SWRST_Pos 0 /**< \brief (GCLK_CTRL) Software Reset */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define GCLK_CTRL_SWRST (0x1ul << GCLK_CTRL_SWRST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 75 | #define GCLK_CTRL_MASK 0x01ul /**< \brief (GCLK_CTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 76 | |
AnnaBridge | 171:3a7713b1edbc | 77 | /* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 79 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 80 | struct { |
AnnaBridge | 171:3a7713b1edbc | 81 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 82 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ |
AnnaBridge | 171:3a7713b1edbc | 83 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 84 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 85 | } GCLK_STATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 86 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 87 | |
AnnaBridge | 171:3a7713b1edbc | 88 | #define GCLK_STATUS_OFFSET 0x1 /**< \brief (GCLK_STATUS offset) Status */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define GCLK_STATUS_RESETVALUE 0x00ul /**< \brief (GCLK_STATUS reset_value) Status */ |
AnnaBridge | 171:3a7713b1edbc | 90 | |
AnnaBridge | 171:3a7713b1edbc | 91 | #define GCLK_STATUS_SYNCBUSY_Pos 7 /**< \brief (GCLK_STATUS) Synchronization Busy Status */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define GCLK_STATUS_SYNCBUSY (0x1ul << GCLK_STATUS_SYNCBUSY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 93 | #define GCLK_STATUS_MASK 0x80ul /**< \brief (GCLK_STATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | /* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 97 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 98 | struct { |
AnnaBridge | 171:3a7713b1edbc | 99 | uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */ |
AnnaBridge | 171:3a7713b1edbc | 100 | uint16_t :2; /*!< bit: 6.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 101 | uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */ |
AnnaBridge | 171:3a7713b1edbc | 102 | uint16_t :2; /*!< bit: 12..13 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 103 | uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 104 | uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 105 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 106 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 107 | } GCLK_CLKCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 108 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 109 | |
AnnaBridge | 171:3a7713b1edbc | 110 | #define GCLK_CLKCTRL_OFFSET 0x2 /**< \brief (GCLK_CLKCTRL offset) Generic Clock Control */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define GCLK_CLKCTRL_RESETVALUE 0x0000ul /**< \brief (GCLK_CLKCTRL reset_value) Generic Clock Control */ |
AnnaBridge | 171:3a7713b1edbc | 112 | |
AnnaBridge | 171:3a7713b1edbc | 113 | #define GCLK_CLKCTRL_ID_Pos 0 /**< \brief (GCLK_CLKCTRL) Generic Clock Selection ID */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define GCLK_CLKCTRL_ID_Msk (0x3Ful << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 115 | #define GCLK_CLKCTRL_ID(value) ((GCLK_CLKCTRL_ID_Msk & ((value) << GCLK_CLKCTRL_ID_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 116 | #define GCLK_CLKCTRL_ID_DFLL48_Val 0x0ul /**< \brief (GCLK_CLKCTRL) DFLL48 */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define GCLK_CLKCTRL_ID_FDPLL_Val 0x1ul /**< \brief (GCLK_CLKCTRL) FDPLL */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #define GCLK_CLKCTRL_ID_FDPLL32K_Val 0x2ul /**< \brief (GCLK_CLKCTRL) FDPLL32K */ |
AnnaBridge | 171:3a7713b1edbc | 119 | #define GCLK_CLKCTRL_ID_WDT_Val 0x3ul /**< \brief (GCLK_CLKCTRL) WDT */ |
AnnaBridge | 171:3a7713b1edbc | 120 | #define GCLK_CLKCTRL_ID_RTC_Val 0x4ul /**< \brief (GCLK_CLKCTRL) RTC */ |
AnnaBridge | 171:3a7713b1edbc | 121 | #define GCLK_CLKCTRL_ID_EIC_Val 0x5ul /**< \brief (GCLK_CLKCTRL) EIC */ |
AnnaBridge | 171:3a7713b1edbc | 122 | #define GCLK_CLKCTRL_ID_USB_Val 0x6ul /**< \brief (GCLK_CLKCTRL) USB */ |
AnnaBridge | 171:3a7713b1edbc | 123 | #define GCLK_CLKCTRL_ID_EVSYS_0_Val 0x7ul /**< \brief (GCLK_CLKCTRL) EVSYS_0 */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #define GCLK_CLKCTRL_ID_EVSYS_1_Val 0x8ul /**< \brief (GCLK_CLKCTRL) EVSYS_1 */ |
AnnaBridge | 171:3a7713b1edbc | 125 | #define GCLK_CLKCTRL_ID_EVSYS_2_Val 0x9ul /**< \brief (GCLK_CLKCTRL) EVSYS_2 */ |
AnnaBridge | 171:3a7713b1edbc | 126 | #define GCLK_CLKCTRL_ID_EVSYS_3_Val 0xAul /**< \brief (GCLK_CLKCTRL) EVSYS_3 */ |
AnnaBridge | 171:3a7713b1edbc | 127 | #define GCLK_CLKCTRL_ID_EVSYS_4_Val 0xBul /**< \brief (GCLK_CLKCTRL) EVSYS_4 */ |
AnnaBridge | 171:3a7713b1edbc | 128 | #define GCLK_CLKCTRL_ID_EVSYS_5_Val 0xCul /**< \brief (GCLK_CLKCTRL) EVSYS_5 */ |
AnnaBridge | 171:3a7713b1edbc | 129 | #define GCLK_CLKCTRL_ID_EVSYS_6_Val 0xDul /**< \brief (GCLK_CLKCTRL) EVSYS_6 */ |
AnnaBridge | 171:3a7713b1edbc | 130 | #define GCLK_CLKCTRL_ID_EVSYS_7_Val 0xEul /**< \brief (GCLK_CLKCTRL) EVSYS_7 */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define GCLK_CLKCTRL_ID_EVSYS_8_Val 0xFul /**< \brief (GCLK_CLKCTRL) EVSYS_8 */ |
AnnaBridge | 171:3a7713b1edbc | 132 | #define GCLK_CLKCTRL_ID_EVSYS_9_Val 0x10ul /**< \brief (GCLK_CLKCTRL) EVSYS_9 */ |
AnnaBridge | 171:3a7713b1edbc | 133 | #define GCLK_CLKCTRL_ID_EVSYS_10_Val 0x11ul /**< \brief (GCLK_CLKCTRL) EVSYS_10 */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define GCLK_CLKCTRL_ID_EVSYS_11_Val 0x12ul /**< \brief (GCLK_CLKCTRL) EVSYS_11 */ |
AnnaBridge | 171:3a7713b1edbc | 135 | #define GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val 0x13ul /**< \brief (GCLK_CLKCTRL) SERCOMX_SLOW */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define GCLK_CLKCTRL_ID_SERCOM0_CORE_Val 0x14ul /**< \brief (GCLK_CLKCTRL) SERCOM0_CORE */ |
AnnaBridge | 171:3a7713b1edbc | 137 | #define GCLK_CLKCTRL_ID_SERCOM1_CORE_Val 0x15ul /**< \brief (GCLK_CLKCTRL) SERCOM1_CORE */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define GCLK_CLKCTRL_ID_SERCOM2_CORE_Val 0x16ul /**< \brief (GCLK_CLKCTRL) SERCOM2_CORE */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define GCLK_CLKCTRL_ID_SERCOM3_CORE_Val 0x17ul /**< \brief (GCLK_CLKCTRL) SERCOM3_CORE */ |
AnnaBridge | 171:3a7713b1edbc | 140 | #define GCLK_CLKCTRL_ID_SERCOM4_CORE_Val 0x18ul /**< \brief (GCLK_CLKCTRL) SERCOM4_CORE */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define GCLK_CLKCTRL_ID_SERCOM5_CORE_Val 0x19ul /**< \brief (GCLK_CLKCTRL) SERCOM5_CORE */ |
AnnaBridge | 171:3a7713b1edbc | 142 | #define GCLK_CLKCTRL_ID_TCC0_TCC1_Val 0x1Aul /**< \brief (GCLK_CLKCTRL) TCC0_TCC1 */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #define GCLK_CLKCTRL_ID_TCC2_TC3_Val 0x1Bul /**< \brief (GCLK_CLKCTRL) TCC2_TC3 */ |
AnnaBridge | 171:3a7713b1edbc | 144 | #define GCLK_CLKCTRL_ID_TC4_TC5_Val 0x1Cul /**< \brief (GCLK_CLKCTRL) TC4_TC5 */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #define GCLK_CLKCTRL_ID_TC6_TC7_Val 0x1Dul /**< \brief (GCLK_CLKCTRL) TC6_TC7 */ |
AnnaBridge | 171:3a7713b1edbc | 146 | #define GCLK_CLKCTRL_ID_ADC_Val 0x1Eul /**< \brief (GCLK_CLKCTRL) ADC */ |
AnnaBridge | 171:3a7713b1edbc | 147 | #define GCLK_CLKCTRL_ID_AC_DIG_Val 0x1Ful /**< \brief (GCLK_CLKCTRL) AC_DIG */ |
AnnaBridge | 171:3a7713b1edbc | 148 | #define GCLK_CLKCTRL_ID_AC_ANA_Val 0x20ul /**< \brief (GCLK_CLKCTRL) AC_ANA */ |
AnnaBridge | 171:3a7713b1edbc | 149 | #define GCLK_CLKCTRL_ID_DAC_Val 0x21ul /**< \brief (GCLK_CLKCTRL) DAC */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define GCLK_CLKCTRL_ID_PTC_Val 0x22ul /**< \brief (GCLK_CLKCTRL) PTC */ |
AnnaBridge | 171:3a7713b1edbc | 151 | #define GCLK_CLKCTRL_ID_I2S_0_Val 0x23ul /**< \brief (GCLK_CLKCTRL) I2S_0 */ |
AnnaBridge | 171:3a7713b1edbc | 152 | #define GCLK_CLKCTRL_ID_I2S_1_Val 0x24ul /**< \brief (GCLK_CLKCTRL) I2S_1 */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #define GCLK_CLKCTRL_ID_DFLL48 (GCLK_CLKCTRL_ID_DFLL48_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 154 | #define GCLK_CLKCTRL_ID_FDPLL (GCLK_CLKCTRL_ID_FDPLL_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 155 | #define GCLK_CLKCTRL_ID_FDPLL32K (GCLK_CLKCTRL_ID_FDPLL32K_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 156 | #define GCLK_CLKCTRL_ID_WDT (GCLK_CLKCTRL_ID_WDT_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 157 | #define GCLK_CLKCTRL_ID_RTC (GCLK_CLKCTRL_ID_RTC_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 158 | #define GCLK_CLKCTRL_ID_EIC (GCLK_CLKCTRL_ID_EIC_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 159 | #define GCLK_CLKCTRL_ID_USB (GCLK_CLKCTRL_ID_USB_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 160 | #define GCLK_CLKCTRL_ID_EVSYS_0 (GCLK_CLKCTRL_ID_EVSYS_0_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 161 | #define GCLK_CLKCTRL_ID_EVSYS_1 (GCLK_CLKCTRL_ID_EVSYS_1_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 162 | #define GCLK_CLKCTRL_ID_EVSYS_2 (GCLK_CLKCTRL_ID_EVSYS_2_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 163 | #define GCLK_CLKCTRL_ID_EVSYS_3 (GCLK_CLKCTRL_ID_EVSYS_3_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 164 | #define GCLK_CLKCTRL_ID_EVSYS_4 (GCLK_CLKCTRL_ID_EVSYS_4_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 165 | #define GCLK_CLKCTRL_ID_EVSYS_5 (GCLK_CLKCTRL_ID_EVSYS_5_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 166 | #define GCLK_CLKCTRL_ID_EVSYS_6 (GCLK_CLKCTRL_ID_EVSYS_6_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 167 | #define GCLK_CLKCTRL_ID_EVSYS_7 (GCLK_CLKCTRL_ID_EVSYS_7_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 168 | #define GCLK_CLKCTRL_ID_EVSYS_8 (GCLK_CLKCTRL_ID_EVSYS_8_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 169 | #define GCLK_CLKCTRL_ID_EVSYS_9 (GCLK_CLKCTRL_ID_EVSYS_9_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 170 | #define GCLK_CLKCTRL_ID_EVSYS_10 (GCLK_CLKCTRL_ID_EVSYS_10_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 171 | #define GCLK_CLKCTRL_ID_EVSYS_11 (GCLK_CLKCTRL_ID_EVSYS_11_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 172 | #define GCLK_CLKCTRL_ID_SERCOMX_SLOW (GCLK_CLKCTRL_ID_SERCOMX_SLOW_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 173 | #define GCLK_CLKCTRL_ID_SERCOM0_CORE (GCLK_CLKCTRL_ID_SERCOM0_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 174 | #define GCLK_CLKCTRL_ID_SERCOM1_CORE (GCLK_CLKCTRL_ID_SERCOM1_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 175 | #define GCLK_CLKCTRL_ID_SERCOM2_CORE (GCLK_CLKCTRL_ID_SERCOM2_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 176 | #define GCLK_CLKCTRL_ID_SERCOM3_CORE (GCLK_CLKCTRL_ID_SERCOM3_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 177 | #define GCLK_CLKCTRL_ID_SERCOM4_CORE (GCLK_CLKCTRL_ID_SERCOM4_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 178 | #define GCLK_CLKCTRL_ID_SERCOM5_CORE (GCLK_CLKCTRL_ID_SERCOM5_CORE_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 179 | #define GCLK_CLKCTRL_ID_TCC0_TCC1 (GCLK_CLKCTRL_ID_TCC0_TCC1_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 180 | #define GCLK_CLKCTRL_ID_TCC2_TC3 (GCLK_CLKCTRL_ID_TCC2_TC3_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 181 | #define GCLK_CLKCTRL_ID_TC4_TC5 (GCLK_CLKCTRL_ID_TC4_TC5_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 182 | #define GCLK_CLKCTRL_ID_TC6_TC7 (GCLK_CLKCTRL_ID_TC6_TC7_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 183 | #define GCLK_CLKCTRL_ID_ADC (GCLK_CLKCTRL_ID_ADC_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 184 | #define GCLK_CLKCTRL_ID_AC_DIG (GCLK_CLKCTRL_ID_AC_DIG_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 185 | #define GCLK_CLKCTRL_ID_AC_ANA (GCLK_CLKCTRL_ID_AC_ANA_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 186 | #define GCLK_CLKCTRL_ID_DAC (GCLK_CLKCTRL_ID_DAC_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 187 | #define GCLK_CLKCTRL_ID_PTC (GCLK_CLKCTRL_ID_PTC_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 188 | #define GCLK_CLKCTRL_ID_I2S_0 (GCLK_CLKCTRL_ID_I2S_0_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 189 | #define GCLK_CLKCTRL_ID_I2S_1 (GCLK_CLKCTRL_ID_I2S_1_Val << GCLK_CLKCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 190 | #define GCLK_CLKCTRL_GEN_Pos 8 /**< \brief (GCLK_CLKCTRL) Generic Clock Generator */ |
AnnaBridge | 171:3a7713b1edbc | 191 | #define GCLK_CLKCTRL_GEN_Msk (0xFul << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 192 | #define GCLK_CLKCTRL_GEN(value) ((GCLK_CLKCTRL_GEN_Msk & ((value) << GCLK_CLKCTRL_GEN_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 193 | #define GCLK_CLKCTRL_GEN_GCLK0_Val 0x0ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 0 */ |
AnnaBridge | 171:3a7713b1edbc | 194 | #define GCLK_CLKCTRL_GEN_GCLK1_Val 0x1ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 1 */ |
AnnaBridge | 171:3a7713b1edbc | 195 | #define GCLK_CLKCTRL_GEN_GCLK2_Val 0x2ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 2 */ |
AnnaBridge | 171:3a7713b1edbc | 196 | #define GCLK_CLKCTRL_GEN_GCLK3_Val 0x3ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 3 */ |
AnnaBridge | 171:3a7713b1edbc | 197 | #define GCLK_CLKCTRL_GEN_GCLK4_Val 0x4ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 4 */ |
AnnaBridge | 171:3a7713b1edbc | 198 | #define GCLK_CLKCTRL_GEN_GCLK5_Val 0x5ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 5 */ |
AnnaBridge | 171:3a7713b1edbc | 199 | #define GCLK_CLKCTRL_GEN_GCLK6_Val 0x6ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 6 */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define GCLK_CLKCTRL_GEN_GCLK7_Val 0x7ul /**< \brief (GCLK_CLKCTRL) Generic clock generator 7 */ |
AnnaBridge | 171:3a7713b1edbc | 201 | #define GCLK_CLKCTRL_GEN_GCLK0 (GCLK_CLKCTRL_GEN_GCLK0_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 202 | #define GCLK_CLKCTRL_GEN_GCLK1 (GCLK_CLKCTRL_GEN_GCLK1_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 203 | #define GCLK_CLKCTRL_GEN_GCLK2 (GCLK_CLKCTRL_GEN_GCLK2_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 204 | #define GCLK_CLKCTRL_GEN_GCLK3 (GCLK_CLKCTRL_GEN_GCLK3_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 205 | #define GCLK_CLKCTRL_GEN_GCLK4 (GCLK_CLKCTRL_GEN_GCLK4_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 206 | #define GCLK_CLKCTRL_GEN_GCLK5 (GCLK_CLKCTRL_GEN_GCLK5_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 207 | #define GCLK_CLKCTRL_GEN_GCLK6 (GCLK_CLKCTRL_GEN_GCLK6_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 208 | #define GCLK_CLKCTRL_GEN_GCLK7 (GCLK_CLKCTRL_GEN_GCLK7_Val << GCLK_CLKCTRL_GEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 209 | #define GCLK_CLKCTRL_CLKEN_Pos 14 /**< \brief (GCLK_CLKCTRL) Clock Enable */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define GCLK_CLKCTRL_CLKEN (0x1ul << GCLK_CLKCTRL_CLKEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 211 | #define GCLK_CLKCTRL_WRTLOCK_Pos 15 /**< \brief (GCLK_CLKCTRL) Write Lock */ |
AnnaBridge | 171:3a7713b1edbc | 212 | #define GCLK_CLKCTRL_WRTLOCK (0x1ul << GCLK_CLKCTRL_WRTLOCK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 213 | #define GCLK_CLKCTRL_MASK 0xCF3Ful /**< \brief (GCLK_CLKCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 214 | |
AnnaBridge | 171:3a7713b1edbc | 215 | /* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 216 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 217 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 218 | struct { |
AnnaBridge | 171:3a7713b1edbc | 219 | uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ |
AnnaBridge | 171:3a7713b1edbc | 220 | uint32_t :4; /*!< bit: 4.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 221 | uint32_t SRC:5; /*!< bit: 8..12 Source Select */ |
AnnaBridge | 171:3a7713b1edbc | 222 | uint32_t :3; /*!< bit: 13..15 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 223 | uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 224 | uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */ |
AnnaBridge | 171:3a7713b1edbc | 225 | uint32_t OOV:1; /*!< bit: 18 Output Off Value */ |
AnnaBridge | 171:3a7713b1edbc | 226 | uint32_t OE:1; /*!< bit: 19 Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 227 | uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */ |
AnnaBridge | 171:3a7713b1edbc | 228 | uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 229 | uint32_t :10; /*!< bit: 22..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 230 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 231 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 232 | } GCLK_GENCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 233 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 234 | |
AnnaBridge | 171:3a7713b1edbc | 235 | #define GCLK_GENCTRL_OFFSET 0x4 /**< \brief (GCLK_GENCTRL offset) Generic Clock Generator Control */ |
AnnaBridge | 171:3a7713b1edbc | 236 | #define GCLK_GENCTRL_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENCTRL reset_value) Generic Clock Generator Control */ |
AnnaBridge | 171:3a7713b1edbc | 237 | |
AnnaBridge | 171:3a7713b1edbc | 238 | #define GCLK_GENCTRL_ID_Pos 0 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Selection */ |
AnnaBridge | 171:3a7713b1edbc | 239 | #define GCLK_GENCTRL_ID_Msk (0xFul << GCLK_GENCTRL_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 240 | #define GCLK_GENCTRL_ID(value) ((GCLK_GENCTRL_ID_Msk & ((value) << GCLK_GENCTRL_ID_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 241 | #define GCLK_GENCTRL_SRC_Pos 8 /**< \brief (GCLK_GENCTRL) Source Select */ |
AnnaBridge | 171:3a7713b1edbc | 242 | #define GCLK_GENCTRL_SRC_Msk (0x1Ful << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 243 | #define GCLK_GENCTRL_SRC(value) ((GCLK_GENCTRL_SRC_Msk & ((value) << GCLK_GENCTRL_SRC_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 244 | #define GCLK_GENCTRL_SRC_XOSC_Val 0x0ul /**< \brief (GCLK_GENCTRL) XOSC oscillator output */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define GCLK_GENCTRL_SRC_GCLKIN_Val 0x1ul /**< \brief (GCLK_GENCTRL) Generator input pad */ |
AnnaBridge | 171:3a7713b1edbc | 246 | #define GCLK_GENCTRL_SRC_GCLKGEN1_Val 0x2ul /**< \brief (GCLK_GENCTRL) Generic clock generator 1 output */ |
AnnaBridge | 171:3a7713b1edbc | 247 | #define GCLK_GENCTRL_SRC_OSCULP32K_Val 0x3ul /**< \brief (GCLK_GENCTRL) OSCULP32K oscillator output */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define GCLK_GENCTRL_SRC_OSC32K_Val 0x4ul /**< \brief (GCLK_GENCTRL) OSC32K oscillator output */ |
AnnaBridge | 171:3a7713b1edbc | 249 | #define GCLK_GENCTRL_SRC_XOSC32K_Val 0x5ul /**< \brief (GCLK_GENCTRL) XOSC32K oscillator output */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define GCLK_GENCTRL_SRC_OSC8M_Val 0x6ul /**< \brief (GCLK_GENCTRL) OSC8M oscillator output */ |
AnnaBridge | 171:3a7713b1edbc | 251 | #define GCLK_GENCTRL_SRC_DFLL48M_Val 0x7ul /**< \brief (GCLK_GENCTRL) DFLL48M output */ |
AnnaBridge | 171:3a7713b1edbc | 252 | #define GCLK_GENCTRL_SRC_FDPLL_Val 0x8ul /**< \brief (GCLK_GENCTRL) FDPLL output */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #define GCLK_GENCTRL_SRC_XOSC (GCLK_GENCTRL_SRC_XOSC_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 254 | #define GCLK_GENCTRL_SRC_GCLKIN (GCLK_GENCTRL_SRC_GCLKIN_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 255 | #define GCLK_GENCTRL_SRC_GCLKGEN1 (GCLK_GENCTRL_SRC_GCLKGEN1_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 256 | #define GCLK_GENCTRL_SRC_OSCULP32K (GCLK_GENCTRL_SRC_OSCULP32K_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 257 | #define GCLK_GENCTRL_SRC_OSC32K (GCLK_GENCTRL_SRC_OSC32K_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 258 | #define GCLK_GENCTRL_SRC_XOSC32K (GCLK_GENCTRL_SRC_XOSC32K_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 259 | #define GCLK_GENCTRL_SRC_OSC8M (GCLK_GENCTRL_SRC_OSC8M_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 260 | #define GCLK_GENCTRL_SRC_DFLL48M (GCLK_GENCTRL_SRC_DFLL48M_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 261 | #define GCLK_GENCTRL_SRC_FDPLL (GCLK_GENCTRL_SRC_FDPLL_Val << GCLK_GENCTRL_SRC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 262 | #define GCLK_GENCTRL_GENEN_Pos 16 /**< \brief (GCLK_GENCTRL) Generic Clock Generator Enable */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define GCLK_GENCTRL_GENEN (0x1ul << GCLK_GENCTRL_GENEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 264 | #define GCLK_GENCTRL_IDC_Pos 17 /**< \brief (GCLK_GENCTRL) Improve Duty Cycle */ |
AnnaBridge | 171:3a7713b1edbc | 265 | #define GCLK_GENCTRL_IDC (0x1ul << GCLK_GENCTRL_IDC_Pos) |
AnnaBridge | 171:3a7713b1edbc | 266 | #define GCLK_GENCTRL_OOV_Pos 18 /**< \brief (GCLK_GENCTRL) Output Off Value */ |
AnnaBridge | 171:3a7713b1edbc | 267 | #define GCLK_GENCTRL_OOV (0x1ul << GCLK_GENCTRL_OOV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 268 | #define GCLK_GENCTRL_OE_Pos 19 /**< \brief (GCLK_GENCTRL) Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 269 | #define GCLK_GENCTRL_OE (0x1ul << GCLK_GENCTRL_OE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 270 | #define GCLK_GENCTRL_DIVSEL_Pos 20 /**< \brief (GCLK_GENCTRL) Divide Selection */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #define GCLK_GENCTRL_DIVSEL (0x1ul << GCLK_GENCTRL_DIVSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 272 | #define GCLK_GENCTRL_RUNSTDBY_Pos 21 /**< \brief (GCLK_GENCTRL) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #define GCLK_GENCTRL_RUNSTDBY (0x1ul << GCLK_GENCTRL_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 274 | #define GCLK_GENCTRL_MASK 0x003F1F0Ful /**< \brief (GCLK_GENCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 275 | |
AnnaBridge | 171:3a7713b1edbc | 276 | /* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */ |
AnnaBridge | 171:3a7713b1edbc | 277 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 278 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 279 | struct { |
AnnaBridge | 171:3a7713b1edbc | 280 | uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */ |
AnnaBridge | 171:3a7713b1edbc | 281 | uint32_t :4; /*!< bit: 4.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 282 | uint32_t DIV:16; /*!< bit: 8..23 Division Factor */ |
AnnaBridge | 171:3a7713b1edbc | 283 | uint32_t :8; /*!< bit: 24..31 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 284 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 285 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 286 | } GCLK_GENDIV_Type; |
AnnaBridge | 171:3a7713b1edbc | 287 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 288 | |
AnnaBridge | 171:3a7713b1edbc | 289 | #define GCLK_GENDIV_OFFSET 0x8 /**< \brief (GCLK_GENDIV offset) Generic Clock Generator Division */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define GCLK_GENDIV_RESETVALUE 0x00000000ul /**< \brief (GCLK_GENDIV reset_value) Generic Clock Generator Division */ |
AnnaBridge | 171:3a7713b1edbc | 291 | |
AnnaBridge | 171:3a7713b1edbc | 292 | #define GCLK_GENDIV_ID_Pos 0 /**< \brief (GCLK_GENDIV) Generic Clock Generator Selection */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #define GCLK_GENDIV_ID_Msk (0xFul << GCLK_GENDIV_ID_Pos) |
AnnaBridge | 171:3a7713b1edbc | 294 | #define GCLK_GENDIV_ID(value) ((GCLK_GENDIV_ID_Msk & ((value) << GCLK_GENDIV_ID_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 295 | #define GCLK_GENDIV_DIV_Pos 8 /**< \brief (GCLK_GENDIV) Division Factor */ |
AnnaBridge | 171:3a7713b1edbc | 296 | #define GCLK_GENDIV_DIV_Msk (0xFFFFul << GCLK_GENDIV_DIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 297 | #define GCLK_GENDIV_DIV(value) ((GCLK_GENDIV_DIV_Msk & ((value) << GCLK_GENDIV_DIV_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 298 | #define GCLK_GENDIV_MASK 0x00FFFF0Ful /**< \brief (GCLK_GENDIV) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 299 | |
AnnaBridge | 171:3a7713b1edbc | 300 | /** \brief GCLK hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 301 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 302 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 303 | __IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ |
AnnaBridge | 171:3a7713b1edbc | 304 | __I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */ |
AnnaBridge | 171:3a7713b1edbc | 305 | __IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */ |
AnnaBridge | 171:3a7713b1edbc | 306 | __IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */ |
AnnaBridge | 171:3a7713b1edbc | 307 | __IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */ |
AnnaBridge | 171:3a7713b1edbc | 308 | } Gclk; |
AnnaBridge | 171:3a7713b1edbc | 309 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 310 | |
AnnaBridge | 171:3a7713b1edbc | 311 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 312 | |
AnnaBridge | 171:3a7713b1edbc | 313 | #endif /* _SAMD21_GCLK_COMPONENT_ */ |