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TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/ins_tcc1.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for TCC1 |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_TCC1_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_TCC1_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========== Register definition for TCC1 peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_TCC1_CTRLA (0x42002400U) /**< \brief (TCC1) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_TCC1_CTRLBCLR (0x42002404U) /**< \brief (TCC1) Control B Clear */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_TCC1_CTRLBSET (0x42002405U) /**< \brief (TCC1) Control B Set */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_TCC1_SYNCBUSY (0x42002408U) /**< \brief (TCC1) Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_TCC1_FCTRLA (0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_TCC1_FCTRLB (0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_TCC1_DRVCTRL (0x42002418U) /**< \brief (TCC1) Driver Control */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_TCC1_DBGCTRL (0x4200241EU) /**< \brief (TCC1) Debug Control */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_TCC1_EVCTRL (0x42002420U) /**< \brief (TCC1) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_TCC1_INTENCLR (0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_TCC1_INTENSET (0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_TCC1_INTFLAG (0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_TCC1_STATUS (0x42002430U) /**< \brief (TCC1) Status */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_TCC1_COUNT (0x42002434U) /**< \brief (TCC1) Count */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_TCC1_PATT (0x42002438U) /**< \brief (TCC1) Pattern */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_TCC1_WAVE (0x4200243CU) /**< \brief (TCC1) Waveform Control */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_TCC1_PER (0x42002440U) /**< \brief (TCC1) Period */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_TCC1_CC0 (0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_TCC1_CC1 (0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_TCC1_PATTB (0x42002464U) /**< \brief (TCC1) Pattern Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define REG_TCC1_WAVEB (0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_TCC1_PERB (0x4200246CU) /**< \brief (TCC1) Period Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_TCC1_CCB0 (0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_TCC1_CCB1 (0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #else |
AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_TCC1_CTRLA (*(RwReg *)0x42002400U) /**< \brief (TCC1) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x42002404U) /**< \brief (TCC1) Control B Clear */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x42002405U) /**< \brief (TCC1) Control B Set */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_TCC1_SYNCBUSY (*(RoReg *)0x42002408U) /**< \brief (TCC1) Synchronization Busy */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_TCC1_FCTRLA (*(RwReg *)0x4200240CU) /**< \brief (TCC1) Recoverable Fault A Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_TCC1_FCTRLB (*(RwReg *)0x42002410U) /**< \brief (TCC1) Recoverable Fault B Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_TCC1_DRVCTRL (*(RwReg *)0x42002418U) /**< \brief (TCC1) Driver Control */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4200241EU) /**< \brief (TCC1) Debug Control */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_TCC1_EVCTRL (*(RwReg *)0x42002420U) /**< \brief (TCC1) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_TCC1_INTENCLR (*(RwReg *)0x42002424U) /**< \brief (TCC1) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_TCC1_INTENSET (*(RwReg *)0x42002428U) /**< \brief (TCC1) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_TCC1_INTFLAG (*(RwReg *)0x4200242CU) /**< \brief (TCC1) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_TCC1_STATUS (*(RwReg *)0x42002430U) /**< \brief (TCC1) Status */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define REG_TCC1_COUNT (*(RwReg *)0x42002434U) /**< \brief (TCC1) Count */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define REG_TCC1_PATT (*(RwReg16*)0x42002438U) /**< \brief (TCC1) Pattern */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define REG_TCC1_WAVE (*(RwReg *)0x4200243CU) /**< \brief (TCC1) Waveform Control */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define REG_TCC1_PER (*(RwReg *)0x42002440U) /**< \brief (TCC1) Period */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define REG_TCC1_CC0 (*(RwReg *)0x42002444U) /**< \brief (TCC1) Compare and Capture 0 */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define REG_TCC1_CC1 (*(RwReg *)0x42002448U) /**< \brief (TCC1) Compare and Capture 1 */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define REG_TCC1_PATTB (*(RwReg16*)0x42002464U) /**< \brief (TCC1) Pattern Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #define REG_TCC1_WAVEB (*(RwReg *)0x42002468U) /**< \brief (TCC1) Waveform Control Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define REG_TCC1_PERB (*(RwReg *)0x4200246CU) /**< \brief (TCC1) Period Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 99 | #define REG_TCC1_CCB0 (*(RwReg *)0x42002470U) /**< \brief (TCC1) Compare and Capture Buffer 0 */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define REG_TCC1_CCB1 (*(RwReg *)0x42002474U) /**< \brief (TCC1) Compare and Capture Buffer 1 */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 102 | |
AnnaBridge | 171:3a7713b1edbc | 103 | /* ========== Instance parameters for TCC1 peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define TCC1_CC_NUM 2 // Number of Compare/Capture units |
AnnaBridge | 171:3a7713b1edbc | 105 | #define TCC1_DITHERING 1 // Dithering feature implemented |
AnnaBridge | 171:3a7713b1edbc | 106 | #define TCC1_DMAC_ID_MC_0 19 |
AnnaBridge | 171:3a7713b1edbc | 107 | #define TCC1_DMAC_ID_MC_1 20 |
AnnaBridge | 171:3a7713b1edbc | 108 | #define TCC1_DMAC_ID_MC_LSB 19 |
AnnaBridge | 171:3a7713b1edbc | 109 | #define TCC1_DMAC_ID_MC_MSB 20 |
AnnaBridge | 171:3a7713b1edbc | 110 | #define TCC1_DMAC_ID_MC_SIZE 2 |
AnnaBridge | 171:3a7713b1edbc | 111 | #define TCC1_DMAC_ID_OVF 18 // DMA overflow/underflow/retrigger trigger |
AnnaBridge | 171:3a7713b1edbc | 112 | #define TCC1_DTI 0 // Dead-Time-Insertion feature implemented |
AnnaBridge | 171:3a7713b1edbc | 113 | #define TCC1_EXT 24 // Coding of implemented extended features |
AnnaBridge | 171:3a7713b1edbc | 114 | #define TCC1_GCLK_ID 26 // Index of Generic Clock |
AnnaBridge | 171:3a7713b1edbc | 115 | #define TCC1_MASTER 1 |
AnnaBridge | 171:3a7713b1edbc | 116 | #define TCC1_OTMX 0 // Output Matrix feature implemented |
AnnaBridge | 171:3a7713b1edbc | 117 | #define TCC1_OW_NUM 4 // Number of Output Waveforms |
AnnaBridge | 171:3a7713b1edbc | 118 | #define TCC1_PG 1 // Pattern Generation feature implemented |
AnnaBridge | 171:3a7713b1edbc | 119 | #define TCC1_SIZE 24 |
AnnaBridge | 171:3a7713b1edbc | 120 | #define TCC1_SWAP 0 // DTI outputs swap feature implemented |
AnnaBridge | 171:3a7713b1edbc | 121 | #define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | #endif /* _SAMD21_TCC1_INSTANCE_ */ |