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TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/ins_sysctrl.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for SYSCTRL |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_SYSCTRL_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_SYSCTRL_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========== Register definition for SYSCTRL peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_SYSCTRL_INTENCLR (0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_SYSCTRL_INTENSET (0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_SYSCTRL_INTFLAG (0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_SYSCTRL_PCLKSR (0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_SYSCTRL_XOSC (0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_SYSCTRL_XOSC32K (0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_SYSCTRL_OSC32K (0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_SYSCTRL_OSCULP32K (0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_SYSCTRL_OSC8M (0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_SYSCTRL_DFLLCTRL (0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_SYSCTRL_DFLLVAL (0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_SYSCTRL_DFLLMUL (0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_SYSCTRL_DFLLSYNC (0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_SYSCTRL_BOD33 (0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_SYSCTRL_VREG (0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_SYSCTRL_VREF (0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_SYSCTRL_DPLLCTRLA (0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_SYSCTRL_DPLLRATIO (0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_SYSCTRL_DPLLCTRLB (0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_SYSCTRL_DPLLSTATUS (0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #else |
AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_SYSCTRL_INTENCLR (*(RwReg *)0x40000800U) /**< \brief (SYSCTRL) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define REG_SYSCTRL_INTENSET (*(RwReg *)0x40000804U) /**< \brief (SYSCTRL) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_SYSCTRL_INTFLAG (*(RwReg *)0x40000808U) /**< \brief (SYSCTRL) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_SYSCTRL_PCLKSR (*(RoReg *)0x4000080CU) /**< \brief (SYSCTRL) Power and Clocks Status */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_SYSCTRL_XOSC (*(RwReg16*)0x40000810U) /**< \brief (SYSCTRL) External Multipurpose Crystal Oscillator (XOSC) Control */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_SYSCTRL_XOSC32K (*(RwReg16*)0x40000814U) /**< \brief (SYSCTRL) 32kHz External Crystal Oscillator (XOSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_SYSCTRL_OSC32K (*(RwReg *)0x40000818U) /**< \brief (SYSCTRL) 32kHz Internal Oscillator (OSC32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_SYSCTRL_OSCULP32K (*(RwReg8 *)0x4000081CU) /**< \brief (SYSCTRL) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_SYSCTRL_OSC8M (*(RwReg *)0x40000820U) /**< \brief (SYSCTRL) 8MHz Internal Oscillator (OSC8M) Control */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_SYSCTRL_DFLLCTRL (*(RwReg16*)0x40000824U) /**< \brief (SYSCTRL) DFLL48M Control */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_SYSCTRL_DFLLVAL (*(RwReg *)0x40000828U) /**< \brief (SYSCTRL) DFLL48M Value */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_SYSCTRL_DFLLMUL (*(RwReg *)0x4000082CU) /**< \brief (SYSCTRL) DFLL48M Multiplier */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_SYSCTRL_DFLLSYNC (*(RwReg8 *)0x40000830U) /**< \brief (SYSCTRL) DFLL48M Synchronization */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_SYSCTRL_BOD33 (*(RwReg *)0x40000834U) /**< \brief (SYSCTRL) 3.3V Brown-Out Detector (BOD33) Control */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_SYSCTRL_VREG (*(RwReg16*)0x4000083CU) /**< \brief (SYSCTRL) Voltage Regulator System (VREG) Control */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_SYSCTRL_VREF (*(RwReg *)0x40000840U) /**< \brief (SYSCTRL) Voltage References System (VREF) Control */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_SYSCTRL_DPLLCTRLA (*(RwReg8 *)0x40000844U) /**< \brief (SYSCTRL) DPLL Control A */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define REG_SYSCTRL_DPLLRATIO (*(RwReg *)0x40000848U) /**< \brief (SYSCTRL) DPLL Ratio Control */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define REG_SYSCTRL_DPLLCTRLB (*(RwReg *)0x4000084CU) /**< \brief (SYSCTRL) DPLL Control B */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define REG_SYSCTRL_DPLLSTATUS (*(RoReg8 *)0x40000850U) /**< \brief (SYSCTRL) DPLL Status */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 94 | |
AnnaBridge | 171:3a7713b1edbc | 95 | /* ========== Instance parameters for SYSCTRL peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define SYSCTRL_BGAP_CALIB_MSB 11 |
AnnaBridge | 171:3a7713b1edbc | 97 | #define SYSCTRL_BOD33_CALIB_MSB 5 |
AnnaBridge | 171:3a7713b1edbc | 98 | #define SYSCTRL_DFLL48M_COARSE_MSB 5 |
AnnaBridge | 171:3a7713b1edbc | 99 | #define SYSCTRL_DFLL48M_FINE_MSB 9 |
AnnaBridge | 171:3a7713b1edbc | 100 | #define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48 |
AnnaBridge | 171:3a7713b1edbc | 101 | #define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL |
AnnaBridge | 171:3a7713b1edbc | 102 | #define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K |
AnnaBridge | 171:3a7713b1edbc | 103 | #define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6 |
AnnaBridge | 171:3a7713b1edbc | 104 | #define SYSCTRL_POR33_ENTEST_MSB 1 |
AnnaBridge | 171:3a7713b1edbc | 105 | #define SYSCTRL_ULPVREF_DIVLEV_MSB 3 |
AnnaBridge | 171:3a7713b1edbc | 106 | #define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1 |
AnnaBridge | 171:3a7713b1edbc | 107 | #define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2 |
AnnaBridge | 171:3a7713b1edbc | 108 | #define SYSCTRL_VREF_CONTROL_MSB 48 |
AnnaBridge | 171:3a7713b1edbc | 109 | #define SYSCTRL_VREF_STATUS_MSB 7 |
AnnaBridge | 171:3a7713b1edbc | 110 | #define SYSCTRL_VREG_LEVEL_MSB 2 |
AnnaBridge | 171:3a7713b1edbc | 111 | #define SYSCTRL_BOD12_VERSION 0x111 |
AnnaBridge | 171:3a7713b1edbc | 112 | #define SYSCTRL_BOD33_VERSION 0x111 |
AnnaBridge | 171:3a7713b1edbc | 113 | #define SYSCTRL_DFLL48M_VERSION 0x301 |
AnnaBridge | 171:3a7713b1edbc | 114 | #define SYSCTRL_FDPLL_VERSION 0x111 |
AnnaBridge | 171:3a7713b1edbc | 115 | #define SYSCTRL_OSCULP32K_VERSION 0x111 |
AnnaBridge | 171:3a7713b1edbc | 116 | #define SYSCTRL_OSC8M_VERSION 0x120 |
AnnaBridge | 171:3a7713b1edbc | 117 | #define SYSCTRL_OSC32K_VERSION 0x112 |
AnnaBridge | 171:3a7713b1edbc | 118 | #define SYSCTRL_VREF_VERSION 0x201 |
AnnaBridge | 171:3a7713b1edbc | 119 | #define SYSCTRL_VREG_VERSION 0x201 |
AnnaBridge | 171:3a7713b1edbc | 120 | #define SYSCTRL_XOSC_VERSION 0x114 |
AnnaBridge | 171:3a7713b1edbc | 121 | #define SYSCTRL_XOSC32K_VERSION 0x113 |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | #endif /* _SAMD21_SYSCTRL_INSTANCE_ */ |