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TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/ins_dsu.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Instance description for DSU |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_DSU_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_DSU_INSTANCE_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========== Register definition for DSU peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 52 | #define REG_DSU_CTRL (0x41002000U) /**< \brief (DSU) Control */ |
AnnaBridge | 171:3a7713b1edbc | 53 | #define REG_DSU_STATUSA (0x41002001U) /**< \brief (DSU) Status A */ |
AnnaBridge | 171:3a7713b1edbc | 54 | #define REG_DSU_STATUSB (0x41002002U) /**< \brief (DSU) Status B */ |
AnnaBridge | 171:3a7713b1edbc | 55 | #define REG_DSU_ADDR (0x41002004U) /**< \brief (DSU) Address */ |
AnnaBridge | 171:3a7713b1edbc | 56 | #define REG_DSU_LENGTH (0x41002008U) /**< \brief (DSU) Length */ |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REG_DSU_DATA (0x4100200CU) /**< \brief (DSU) Data */ |
AnnaBridge | 171:3a7713b1edbc | 58 | #define REG_DSU_DCC0 (0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ |
AnnaBridge | 171:3a7713b1edbc | 59 | #define REG_DSU_DCC1 (0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #define REG_DSU_DID (0x41002018U) /**< \brief (DSU) Device Identification */ |
AnnaBridge | 171:3a7713b1edbc | 61 | #define REG_DSU_ENTRY0 (0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ |
AnnaBridge | 171:3a7713b1edbc | 62 | #define REG_DSU_ENTRY1 (0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ |
AnnaBridge | 171:3a7713b1edbc | 63 | #define REG_DSU_END (0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ |
AnnaBridge | 171:3a7713b1edbc | 64 | #define REG_DSU_MEMTYPE (0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ |
AnnaBridge | 171:3a7713b1edbc | 65 | #define REG_DSU_PID4 (0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ |
AnnaBridge | 171:3a7713b1edbc | 66 | #define REG_DSU_PID0 (0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ |
AnnaBridge | 171:3a7713b1edbc | 67 | #define REG_DSU_PID1 (0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ |
AnnaBridge | 171:3a7713b1edbc | 68 | #define REG_DSU_PID2 (0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ |
AnnaBridge | 171:3a7713b1edbc | 69 | #define REG_DSU_PID3 (0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ |
AnnaBridge | 171:3a7713b1edbc | 70 | #define REG_DSU_CID0 (0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ |
AnnaBridge | 171:3a7713b1edbc | 71 | #define REG_DSU_CID1 (0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ |
AnnaBridge | 171:3a7713b1edbc | 72 | #define REG_DSU_CID2 (0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define REG_DSU_CID3 (0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #else |
AnnaBridge | 171:3a7713b1edbc | 75 | #define REG_DSU_CTRL (*(WoReg8 *)0x41002000U) /**< \brief (DSU) Control */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define REG_DSU_STATUSA (*(RwReg8 *)0x41002001U) /**< \brief (DSU) Status A */ |
AnnaBridge | 171:3a7713b1edbc | 77 | #define REG_DSU_STATUSB (*(RoReg8 *)0x41002002U) /**< \brief (DSU) Status B */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define REG_DSU_ADDR (*(RwReg *)0x41002004U) /**< \brief (DSU) Address */ |
AnnaBridge | 171:3a7713b1edbc | 79 | #define REG_DSU_LENGTH (*(RwReg *)0x41002008U) /**< \brief (DSU) Length */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define REG_DSU_DATA (*(RwReg *)0x4100200CU) /**< \brief (DSU) Data */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #define REG_DSU_DCC0 (*(RwReg *)0x41002010U) /**< \brief (DSU) Debug Communication Channel 0 */ |
AnnaBridge | 171:3a7713b1edbc | 82 | #define REG_DSU_DCC1 (*(RwReg *)0x41002014U) /**< \brief (DSU) Debug Communication Channel 1 */ |
AnnaBridge | 171:3a7713b1edbc | 83 | #define REG_DSU_DID (*(RoReg *)0x41002018U) /**< \brief (DSU) Device Identification */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #define REG_DSU_ENTRY0 (*(RoReg *)0x41003000U) /**< \brief (DSU) Coresight ROM Table Entry 0 */ |
AnnaBridge | 171:3a7713b1edbc | 85 | #define REG_DSU_ENTRY1 (*(RoReg *)0x41003004U) /**< \brief (DSU) Coresight ROM Table Entry 1 */ |
AnnaBridge | 171:3a7713b1edbc | 86 | #define REG_DSU_END (*(RoReg *)0x41003008U) /**< \brief (DSU) Coresight ROM Table End */ |
AnnaBridge | 171:3a7713b1edbc | 87 | #define REG_DSU_MEMTYPE (*(RoReg *)0x41003FCCU) /**< \brief (DSU) Coresight ROM Table Memory Type */ |
AnnaBridge | 171:3a7713b1edbc | 88 | #define REG_DSU_PID4 (*(RoReg *)0x41003FD0U) /**< \brief (DSU) Peripheral Identification 4 */ |
AnnaBridge | 171:3a7713b1edbc | 89 | #define REG_DSU_PID0 (*(RoReg *)0x41003FE0U) /**< \brief (DSU) Peripheral Identification 0 */ |
AnnaBridge | 171:3a7713b1edbc | 90 | #define REG_DSU_PID1 (*(RoReg *)0x41003FE4U) /**< \brief (DSU) Peripheral Identification 1 */ |
AnnaBridge | 171:3a7713b1edbc | 91 | #define REG_DSU_PID2 (*(RoReg *)0x41003FE8U) /**< \brief (DSU) Peripheral Identification 2 */ |
AnnaBridge | 171:3a7713b1edbc | 92 | #define REG_DSU_PID3 (*(RoReg *)0x41003FECU) /**< \brief (DSU) Peripheral Identification 3 */ |
AnnaBridge | 171:3a7713b1edbc | 93 | #define REG_DSU_CID0 (*(RoReg *)0x41003FF0U) /**< \brief (DSU) Component Identification 0 */ |
AnnaBridge | 171:3a7713b1edbc | 94 | #define REG_DSU_CID1 (*(RoReg *)0x41003FF4U) /**< \brief (DSU) Component Identification 1 */ |
AnnaBridge | 171:3a7713b1edbc | 95 | #define REG_DSU_CID2 (*(RoReg *)0x41003FF8U) /**< \brief (DSU) Component Identification 2 */ |
AnnaBridge | 171:3a7713b1edbc | 96 | #define REG_DSU_CID3 (*(RoReg *)0x41003FFCU) /**< \brief (DSU) Component Identification 3 */ |
AnnaBridge | 171:3a7713b1edbc | 97 | #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 98 | |
AnnaBridge | 171:3a7713b1edbc | 99 | /* ========== Instance parameters for DSU peripheral ========== */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define DSU_CLK_HSB_ID 3 // Index of AHB clock in PM.AHBMASK register |
AnnaBridge | 171:3a7713b1edbc | 101 | |
AnnaBridge | 171:3a7713b1edbc | 102 | #endif /* _SAMD21_DSU_INSTANCE_ */ |