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mbed 2
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TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/comp_mtb.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Component description for MTB |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_MTB_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_MTB_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | /** SOFTWARE API DEFINITION FOR MTB */ |
AnnaBridge | 171:3a7713b1edbc | 52 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 53 | /** \addtogroup SAMD21_MTB Cortex-M0+ Micro-Trace Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 54 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | #define MTB_U2002 |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REV_MTB 0x100 |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | /* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 61 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 62 | struct { |
AnnaBridge | 171:3a7713b1edbc | 63 | uint32_t :2; /*!< bit: 0.. 1 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 64 | uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */ |
AnnaBridge | 171:3a7713b1edbc | 65 | uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */ |
AnnaBridge | 171:3a7713b1edbc | 66 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 67 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 68 | } MTB_POSITION_Type; |
AnnaBridge | 171:3a7713b1edbc | 69 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 70 | |
AnnaBridge | 171:3a7713b1edbc | 71 | #define MTB_POSITION_OFFSET 0x000 /**< \brief (MTB_POSITION offset) MTB Position */ |
AnnaBridge | 171:3a7713b1edbc | 72 | |
AnnaBridge | 171:3a7713b1edbc | 73 | #define MTB_POSITION_WRAP_Pos 2 /**< \brief (MTB_POSITION) Pointer Value Wraps */ |
AnnaBridge | 171:3a7713b1edbc | 74 | #define MTB_POSITION_WRAP (0x1ul << MTB_POSITION_WRAP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 75 | #define MTB_POSITION_POINTER_Pos 3 /**< \brief (MTB_POSITION) Trace Packet Location Pointer */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define MTB_POSITION_POINTER_Msk (0x1FFFFFFFul << MTB_POSITION_POINTER_Pos) |
AnnaBridge | 171:3a7713b1edbc | 77 | #define MTB_POSITION_POINTER(value) ((MTB_POSITION_POINTER_Msk & ((value) << MTB_POSITION_POINTER_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 78 | #define MTB_POSITION_MASK 0xFFFFFFFCul /**< \brief (MTB_POSITION) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 79 | |
AnnaBridge | 171:3a7713b1edbc | 80 | /* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */ |
AnnaBridge | 171:3a7713b1edbc | 81 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 82 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 83 | struct { |
AnnaBridge | 171:3a7713b1edbc | 84 | uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */ |
AnnaBridge | 171:3a7713b1edbc | 85 | uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */ |
AnnaBridge | 171:3a7713b1edbc | 86 | uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */ |
AnnaBridge | 171:3a7713b1edbc | 87 | uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */ |
AnnaBridge | 171:3a7713b1edbc | 88 | uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */ |
AnnaBridge | 171:3a7713b1edbc | 89 | uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */ |
AnnaBridge | 171:3a7713b1edbc | 90 | uint32_t :21; /*!< bit: 10..30 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 91 | uint32_t EN:1; /*!< bit: 31 Main Trace Enable */ |
AnnaBridge | 171:3a7713b1edbc | 92 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 93 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 94 | } MTB_MASTER_Type; |
AnnaBridge | 171:3a7713b1edbc | 95 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 96 | |
AnnaBridge | 171:3a7713b1edbc | 97 | #define MTB_MASTER_OFFSET 0x004 /**< \brief (MTB_MASTER offset) MTB Master */ |
AnnaBridge | 171:3a7713b1edbc | 98 | #define MTB_MASTER_RESETVALUE 0x00000000ul /**< \brief (MTB_MASTER reset_value) MTB Master */ |
AnnaBridge | 171:3a7713b1edbc | 99 | |
AnnaBridge | 171:3a7713b1edbc | 100 | #define MTB_MASTER_MASK_Pos 0 /**< \brief (MTB_MASTER) Maximum Value of the Trace Buffer in SRAM */ |
AnnaBridge | 171:3a7713b1edbc | 101 | #define MTB_MASTER_MASK_Msk (0x1Ful << MTB_MASTER_MASK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 102 | #define MTB_MASTER_MASK(value) ((MTB_MASTER_MASK_Msk & ((value) << MTB_MASTER_MASK_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 103 | #define MTB_MASTER_TSTARTEN_Pos 5 /**< \brief (MTB_MASTER) Trace Start Input Enable */ |
AnnaBridge | 171:3a7713b1edbc | 104 | #define MTB_MASTER_TSTARTEN (0x1ul << MTB_MASTER_TSTARTEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 105 | #define MTB_MASTER_TSTOPEN_Pos 6 /**< \brief (MTB_MASTER) Trace Stop Input Enable */ |
AnnaBridge | 171:3a7713b1edbc | 106 | #define MTB_MASTER_TSTOPEN (0x1ul << MTB_MASTER_TSTOPEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 107 | #define MTB_MASTER_SFRWPRIV_Pos 7 /**< \brief (MTB_MASTER) Special Function Register Write Privilege */ |
AnnaBridge | 171:3a7713b1edbc | 108 | #define MTB_MASTER_SFRWPRIV (0x1ul << MTB_MASTER_SFRWPRIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 109 | #define MTB_MASTER_RAMPRIV_Pos 8 /**< \brief (MTB_MASTER) SRAM Privilege */ |
AnnaBridge | 171:3a7713b1edbc | 110 | #define MTB_MASTER_RAMPRIV (0x1ul << MTB_MASTER_RAMPRIV_Pos) |
AnnaBridge | 171:3a7713b1edbc | 111 | #define MTB_MASTER_HALTREQ_Pos 9 /**< \brief (MTB_MASTER) Halt Request */ |
AnnaBridge | 171:3a7713b1edbc | 112 | #define MTB_MASTER_HALTREQ (0x1ul << MTB_MASTER_HALTREQ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 113 | #define MTB_MASTER_EN_Pos 31 /**< \brief (MTB_MASTER) Main Trace Enable */ |
AnnaBridge | 171:3a7713b1edbc | 114 | #define MTB_MASTER_EN (0x1ul << MTB_MASTER_EN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 115 | #define MTB_MASTER_MASK_ 0x800003FFul /**< \brief (MTB_MASTER) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 116 | |
AnnaBridge | 171:3a7713b1edbc | 117 | /* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 119 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 120 | struct { |
AnnaBridge | 171:3a7713b1edbc | 121 | uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */ |
AnnaBridge | 171:3a7713b1edbc | 122 | uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */ |
AnnaBridge | 171:3a7713b1edbc | 123 | uint32_t :1; /*!< bit: 2 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 124 | uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */ |
AnnaBridge | 171:3a7713b1edbc | 125 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 126 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 127 | } MTB_FLOW_Type; |
AnnaBridge | 171:3a7713b1edbc | 128 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 129 | |
AnnaBridge | 171:3a7713b1edbc | 130 | #define MTB_FLOW_OFFSET 0x008 /**< \brief (MTB_FLOW offset) MTB Flow */ |
AnnaBridge | 171:3a7713b1edbc | 131 | #define MTB_FLOW_RESETVALUE 0x00000000ul /**< \brief (MTB_FLOW reset_value) MTB Flow */ |
AnnaBridge | 171:3a7713b1edbc | 132 | |
AnnaBridge | 171:3a7713b1edbc | 133 | #define MTB_FLOW_AUTOSTOP_Pos 0 /**< \brief (MTB_FLOW) Auto Stop Tracing */ |
AnnaBridge | 171:3a7713b1edbc | 134 | #define MTB_FLOW_AUTOSTOP (0x1ul << MTB_FLOW_AUTOSTOP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 135 | #define MTB_FLOW_AUTOHALT_Pos 1 /**< \brief (MTB_FLOW) Auto Halt Request */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define MTB_FLOW_AUTOHALT (0x1ul << MTB_FLOW_AUTOHALT_Pos) |
AnnaBridge | 171:3a7713b1edbc | 137 | #define MTB_FLOW_WATERMARK_Pos 3 /**< \brief (MTB_FLOW) Watermark value */ |
AnnaBridge | 171:3a7713b1edbc | 138 | #define MTB_FLOW_WATERMARK_Msk (0x1FFFFFFFul << MTB_FLOW_WATERMARK_Pos) |
AnnaBridge | 171:3a7713b1edbc | 139 | #define MTB_FLOW_WATERMARK(value) ((MTB_FLOW_WATERMARK_Msk & ((value) << MTB_FLOW_WATERMARK_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 140 | #define MTB_FLOW_MASK 0xFFFFFFFBul /**< \brief (MTB_FLOW) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 141 | |
AnnaBridge | 171:3a7713b1edbc | 142 | /* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */ |
AnnaBridge | 171:3a7713b1edbc | 143 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 144 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 145 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 146 | } MTB_BASE_Type; |
AnnaBridge | 171:3a7713b1edbc | 147 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 148 | |
AnnaBridge | 171:3a7713b1edbc | 149 | #define MTB_BASE_OFFSET 0x00C /**< \brief (MTB_BASE offset) MTB Base */ |
AnnaBridge | 171:3a7713b1edbc | 150 | #define MTB_BASE_MASK 0xFFFFFFFFul /**< \brief (MTB_BASE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 151 | |
AnnaBridge | 171:3a7713b1edbc | 152 | /* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 153 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 154 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 155 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 156 | } MTB_ITCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 157 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 158 | |
AnnaBridge | 171:3a7713b1edbc | 159 | #define MTB_ITCTRL_OFFSET 0xF00 /**< \brief (MTB_ITCTRL offset) MTB Integration Mode Control */ |
AnnaBridge | 171:3a7713b1edbc | 160 | #define MTB_ITCTRL_MASK 0xFFFFFFFFul /**< \brief (MTB_ITCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 161 | |
AnnaBridge | 171:3a7713b1edbc | 162 | /* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 164 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 165 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 166 | } MTB_CLAIMSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 167 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 168 | |
AnnaBridge | 171:3a7713b1edbc | 169 | #define MTB_CLAIMSET_OFFSET 0xFA0 /**< \brief (MTB_CLAIMSET offset) MTB Claim Set */ |
AnnaBridge | 171:3a7713b1edbc | 170 | #define MTB_CLAIMSET_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 171 | |
AnnaBridge | 171:3a7713b1edbc | 172 | /* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 173 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 174 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 175 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 176 | } MTB_CLAIMCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 177 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 178 | |
AnnaBridge | 171:3a7713b1edbc | 179 | #define MTB_CLAIMCLR_OFFSET 0xFA4 /**< \brief (MTB_CLAIMCLR offset) MTB Claim Clear */ |
AnnaBridge | 171:3a7713b1edbc | 180 | #define MTB_CLAIMCLR_MASK 0xFFFFFFFFul /**< \brief (MTB_CLAIMCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 181 | |
AnnaBridge | 171:3a7713b1edbc | 182 | /* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */ |
AnnaBridge | 171:3a7713b1edbc | 183 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 184 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 185 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 186 | } MTB_LOCKACCESS_Type; |
AnnaBridge | 171:3a7713b1edbc | 187 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 188 | |
AnnaBridge | 171:3a7713b1edbc | 189 | #define MTB_LOCKACCESS_OFFSET 0xFB0 /**< \brief (MTB_LOCKACCESS offset) MTB Lock Access */ |
AnnaBridge | 171:3a7713b1edbc | 190 | #define MTB_LOCKACCESS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKACCESS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 191 | |
AnnaBridge | 171:3a7713b1edbc | 192 | /* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 194 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 195 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 196 | } MTB_LOCKSTATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 197 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 198 | |
AnnaBridge | 171:3a7713b1edbc | 199 | #define MTB_LOCKSTATUS_OFFSET 0xFB4 /**< \brief (MTB_LOCKSTATUS offset) MTB Lock Status */ |
AnnaBridge | 171:3a7713b1edbc | 200 | #define MTB_LOCKSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_LOCKSTATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 201 | |
AnnaBridge | 171:3a7713b1edbc | 202 | /* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 203 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 204 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 205 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 206 | } MTB_AUTHSTATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 208 | |
AnnaBridge | 171:3a7713b1edbc | 209 | #define MTB_AUTHSTATUS_OFFSET 0xFB8 /**< \brief (MTB_AUTHSTATUS offset) MTB Authentication Status */ |
AnnaBridge | 171:3a7713b1edbc | 210 | #define MTB_AUTHSTATUS_MASK 0xFFFFFFFFul /**< \brief (MTB_AUTHSTATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 211 | |
AnnaBridge | 171:3a7713b1edbc | 212 | /* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 214 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 215 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 216 | } MTB_DEVARCH_Type; |
AnnaBridge | 171:3a7713b1edbc | 217 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 218 | |
AnnaBridge | 171:3a7713b1edbc | 219 | #define MTB_DEVARCH_OFFSET 0xFBC /**< \brief (MTB_DEVARCH offset) MTB Device Architecture */ |
AnnaBridge | 171:3a7713b1edbc | 220 | #define MTB_DEVARCH_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVARCH) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 221 | |
AnnaBridge | 171:3a7713b1edbc | 222 | /* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */ |
AnnaBridge | 171:3a7713b1edbc | 223 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 224 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 225 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 226 | } MTB_DEVID_Type; |
AnnaBridge | 171:3a7713b1edbc | 227 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 228 | |
AnnaBridge | 171:3a7713b1edbc | 229 | #define MTB_DEVID_OFFSET 0xFC8 /**< \brief (MTB_DEVID offset) MTB Device Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 230 | #define MTB_DEVID_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVID) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 231 | |
AnnaBridge | 171:3a7713b1edbc | 232 | /* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */ |
AnnaBridge | 171:3a7713b1edbc | 233 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 234 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 235 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 236 | } MTB_DEVTYPE_Type; |
AnnaBridge | 171:3a7713b1edbc | 237 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 238 | |
AnnaBridge | 171:3a7713b1edbc | 239 | #define MTB_DEVTYPE_OFFSET 0xFCC /**< \brief (MTB_DEVTYPE offset) MTB Device Type */ |
AnnaBridge | 171:3a7713b1edbc | 240 | #define MTB_DEVTYPE_MASK 0xFFFFFFFFul /**< \brief (MTB_DEVTYPE) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 241 | |
AnnaBridge | 171:3a7713b1edbc | 242 | /* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 243 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 244 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 245 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 246 | } MTB_PID4_Type; |
AnnaBridge | 171:3a7713b1edbc | 247 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 248 | |
AnnaBridge | 171:3a7713b1edbc | 249 | #define MTB_PID4_OFFSET 0xFD0 /**< \brief (MTB_PID4 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 250 | #define MTB_PID4_MASK 0xFFFFFFFFul /**< \brief (MTB_PID4) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | /* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 254 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 255 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 256 | } MTB_PID5_Type; |
AnnaBridge | 171:3a7713b1edbc | 257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 258 | |
AnnaBridge | 171:3a7713b1edbc | 259 | #define MTB_PID5_OFFSET 0xFD4 /**< \brief (MTB_PID5 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 260 | #define MTB_PID5_MASK 0xFFFFFFFFul /**< \brief (MTB_PID5) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 261 | |
AnnaBridge | 171:3a7713b1edbc | 262 | /* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 264 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 265 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 266 | } MTB_PID6_Type; |
AnnaBridge | 171:3a7713b1edbc | 267 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 268 | |
AnnaBridge | 171:3a7713b1edbc | 269 | #define MTB_PID6_OFFSET 0xFD8 /**< \brief (MTB_PID6 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 270 | #define MTB_PID6_MASK 0xFFFFFFFFul /**< \brief (MTB_PID6) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 271 | |
AnnaBridge | 171:3a7713b1edbc | 272 | /* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 273 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 274 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 275 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 276 | } MTB_PID7_Type; |
AnnaBridge | 171:3a7713b1edbc | 277 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 278 | |
AnnaBridge | 171:3a7713b1edbc | 279 | #define MTB_PID7_OFFSET 0xFDC /**< \brief (MTB_PID7 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 280 | #define MTB_PID7_MASK 0xFFFFFFFFul /**< \brief (MTB_PID7) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 281 | |
AnnaBridge | 171:3a7713b1edbc | 282 | /* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 283 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 284 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 285 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 286 | } MTB_PID0_Type; |
AnnaBridge | 171:3a7713b1edbc | 287 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 288 | |
AnnaBridge | 171:3a7713b1edbc | 289 | #define MTB_PID0_OFFSET 0xFE0 /**< \brief (MTB_PID0 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 290 | #define MTB_PID0_MASK 0xFFFFFFFFul /**< \brief (MTB_PID0) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 291 | |
AnnaBridge | 171:3a7713b1edbc | 292 | /* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 293 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 294 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 295 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 296 | } MTB_PID1_Type; |
AnnaBridge | 171:3a7713b1edbc | 297 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 298 | |
AnnaBridge | 171:3a7713b1edbc | 299 | #define MTB_PID1_OFFSET 0xFE4 /**< \brief (MTB_PID1 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 300 | #define MTB_PID1_MASK 0xFFFFFFFFul /**< \brief (MTB_PID1) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 301 | |
AnnaBridge | 171:3a7713b1edbc | 302 | /* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 303 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 304 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 305 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 306 | } MTB_PID2_Type; |
AnnaBridge | 171:3a7713b1edbc | 307 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 308 | |
AnnaBridge | 171:3a7713b1edbc | 309 | #define MTB_PID2_OFFSET 0xFE8 /**< \brief (MTB_PID2 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 310 | #define MTB_PID2_MASK 0xFFFFFFFFul /**< \brief (MTB_PID2) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 311 | |
AnnaBridge | 171:3a7713b1edbc | 312 | /* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 313 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 314 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 315 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 316 | } MTB_PID3_Type; |
AnnaBridge | 171:3a7713b1edbc | 317 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 318 | |
AnnaBridge | 171:3a7713b1edbc | 319 | #define MTB_PID3_OFFSET 0xFEC /**< \brief (MTB_PID3 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 320 | #define MTB_PID3_MASK 0xFFFFFFFFul /**< \brief (MTB_PID3) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 321 | |
AnnaBridge | 171:3a7713b1edbc | 322 | /* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 323 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 324 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 325 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 326 | } MTB_CID0_Type; |
AnnaBridge | 171:3a7713b1edbc | 327 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 328 | |
AnnaBridge | 171:3a7713b1edbc | 329 | #define MTB_CID0_OFFSET 0xFF0 /**< \brief (MTB_CID0 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 330 | #define MTB_CID0_MASK 0xFFFFFFFFul /**< \brief (MTB_CID0) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 331 | |
AnnaBridge | 171:3a7713b1edbc | 332 | /* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 333 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 334 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 335 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 336 | } MTB_CID1_Type; |
AnnaBridge | 171:3a7713b1edbc | 337 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 338 | |
AnnaBridge | 171:3a7713b1edbc | 339 | #define MTB_CID1_OFFSET 0xFF4 /**< \brief (MTB_CID1 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 340 | #define MTB_CID1_MASK 0xFFFFFFFFul /**< \brief (MTB_CID1) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 341 | |
AnnaBridge | 171:3a7713b1edbc | 342 | /* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 343 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 344 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 345 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 346 | } MTB_CID2_Type; |
AnnaBridge | 171:3a7713b1edbc | 347 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 348 | |
AnnaBridge | 171:3a7713b1edbc | 349 | #define MTB_CID2_OFFSET 0xFF8 /**< \brief (MTB_CID2 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 350 | #define MTB_CID2_MASK 0xFFFFFFFFul /**< \brief (MTB_CID2) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 351 | |
AnnaBridge | 171:3a7713b1edbc | 352 | /* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */ |
AnnaBridge | 171:3a7713b1edbc | 353 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 354 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 355 | uint32_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 356 | } MTB_CID3_Type; |
AnnaBridge | 171:3a7713b1edbc | 357 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 358 | |
AnnaBridge | 171:3a7713b1edbc | 359 | #define MTB_CID3_OFFSET 0xFFC /**< \brief (MTB_CID3 offset) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 360 | #define MTB_CID3_MASK 0xFFFFFFFFul /**< \brief (MTB_CID3) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 361 | |
AnnaBridge | 171:3a7713b1edbc | 362 | /** \brief MTB hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 363 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 364 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 365 | __IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */ |
AnnaBridge | 171:3a7713b1edbc | 366 | __IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */ |
AnnaBridge | 171:3a7713b1edbc | 367 | __IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */ |
AnnaBridge | 171:3a7713b1edbc | 368 | __I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */ |
AnnaBridge | 171:3a7713b1edbc | 369 | RoReg8 Reserved1[0xEF0]; |
AnnaBridge | 171:3a7713b1edbc | 370 | __IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */ |
AnnaBridge | 171:3a7713b1edbc | 371 | RoReg8 Reserved2[0x9C]; |
AnnaBridge | 171:3a7713b1edbc | 372 | __IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */ |
AnnaBridge | 171:3a7713b1edbc | 373 | __IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */ |
AnnaBridge | 171:3a7713b1edbc | 374 | RoReg8 Reserved3[0x8]; |
AnnaBridge | 171:3a7713b1edbc | 375 | __IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */ |
AnnaBridge | 171:3a7713b1edbc | 376 | __I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */ |
AnnaBridge | 171:3a7713b1edbc | 377 | __I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */ |
AnnaBridge | 171:3a7713b1edbc | 378 | __I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */ |
AnnaBridge | 171:3a7713b1edbc | 379 | RoReg8 Reserved4[0x8]; |
AnnaBridge | 171:3a7713b1edbc | 380 | __I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */ |
AnnaBridge | 171:3a7713b1edbc | 381 | __I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */ |
AnnaBridge | 171:3a7713b1edbc | 382 | __I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 383 | __I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 384 | __I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 385 | __I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 386 | __I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 387 | __I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 388 | __I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 389 | __I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 390 | __I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 391 | __I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 392 | __I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 393 | __I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */ |
AnnaBridge | 171:3a7713b1edbc | 394 | } Mtb; |
AnnaBridge | 171:3a7713b1edbc | 395 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 396 | |
AnnaBridge | 171:3a7713b1edbc | 397 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 398 | |
AnnaBridge | 171:3a7713b1edbc | 399 | #endif /* _SAMD21_MTB_COMPONENT_ */ |