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TARGET_SAMD21G18A/TOOLCHAIN_ARM_MICRO/comp_dac.h@171:3a7713b1edbc, 2018-11-08 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 08 11:45:42 2018 +0000
- Revision:
- 171:3a7713b1edbc
mbed library. Release version 164
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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AnnaBridge | 171:3a7713b1edbc | 1 | /** |
AnnaBridge | 171:3a7713b1edbc | 2 | * \file |
AnnaBridge | 171:3a7713b1edbc | 3 | * |
AnnaBridge | 171:3a7713b1edbc | 4 | * \brief Component description for DAC |
AnnaBridge | 171:3a7713b1edbc | 5 | * |
AnnaBridge | 171:3a7713b1edbc | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
AnnaBridge | 171:3a7713b1edbc | 7 | * |
AnnaBridge | 171:3a7713b1edbc | 8 | * \asf_license_start |
AnnaBridge | 171:3a7713b1edbc | 9 | * |
AnnaBridge | 171:3a7713b1edbc | 10 | * \page License |
AnnaBridge | 171:3a7713b1edbc | 11 | * |
AnnaBridge | 171:3a7713b1edbc | 12 | * Redistribution and use in source and binary forms, with or without |
AnnaBridge | 171:3a7713b1edbc | 13 | * modification, are permitted provided that the following conditions are met: |
AnnaBridge | 171:3a7713b1edbc | 14 | * |
AnnaBridge | 171:3a7713b1edbc | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 171:3a7713b1edbc | 17 | * |
AnnaBridge | 171:3a7713b1edbc | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 171:3a7713b1edbc | 19 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 171:3a7713b1edbc | 20 | * and/or other materials provided with the distribution. |
AnnaBridge | 171:3a7713b1edbc | 21 | * |
AnnaBridge | 171:3a7713b1edbc | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
AnnaBridge | 171:3a7713b1edbc | 23 | * from this software without specific prior written permission. |
AnnaBridge | 171:3a7713b1edbc | 24 | * |
AnnaBridge | 171:3a7713b1edbc | 25 | * 4. This software may only be redistributed and used in connection with an |
AnnaBridge | 171:3a7713b1edbc | 26 | * Atmel microcontroller product. |
AnnaBridge | 171:3a7713b1edbc | 27 | * |
AnnaBridge | 171:3a7713b1edbc | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
AnnaBridge | 171:3a7713b1edbc | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
AnnaBridge | 171:3a7713b1edbc | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
AnnaBridge | 171:3a7713b1edbc | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
AnnaBridge | 171:3a7713b1edbc | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 171:3a7713b1edbc | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
AnnaBridge | 171:3a7713b1edbc | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
AnnaBridge | 171:3a7713b1edbc | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
AnnaBridge | 171:3a7713b1edbc | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
AnnaBridge | 171:3a7713b1edbc | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
AnnaBridge | 171:3a7713b1edbc | 38 | * POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 171:3a7713b1edbc | 39 | * |
AnnaBridge | 171:3a7713b1edbc | 40 | * \asf_license_stop |
AnnaBridge | 171:3a7713b1edbc | 41 | * |
AnnaBridge | 171:3a7713b1edbc | 42 | */ |
AnnaBridge | 171:3a7713b1edbc | 43 | /* |
AnnaBridge | 171:3a7713b1edbc | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
AnnaBridge | 171:3a7713b1edbc | 45 | */ |
AnnaBridge | 171:3a7713b1edbc | 46 | |
AnnaBridge | 171:3a7713b1edbc | 47 | #ifndef _SAMD21_DAC_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 48 | #define _SAMD21_DAC_COMPONENT_ |
AnnaBridge | 171:3a7713b1edbc | 49 | |
AnnaBridge | 171:3a7713b1edbc | 50 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 51 | /** SOFTWARE API DEFINITION FOR DAC */ |
AnnaBridge | 171:3a7713b1edbc | 52 | /* ========================================================================== */ |
AnnaBridge | 171:3a7713b1edbc | 53 | /** \addtogroup SAMD21_DAC Digital Analog Converter */ |
AnnaBridge | 171:3a7713b1edbc | 54 | /*@{*/ |
AnnaBridge | 171:3a7713b1edbc | 55 | |
AnnaBridge | 171:3a7713b1edbc | 56 | #define DAC_U2214 |
AnnaBridge | 171:3a7713b1edbc | 57 | #define REV_DAC 0x110 |
AnnaBridge | 171:3a7713b1edbc | 58 | |
AnnaBridge | 171:3a7713b1edbc | 59 | /* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */ |
AnnaBridge | 171:3a7713b1edbc | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 61 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 62 | struct { |
AnnaBridge | 171:3a7713b1edbc | 63 | uint8_t SWRST:1; /*!< bit: 0 Software Reset */ |
AnnaBridge | 171:3a7713b1edbc | 64 | uint8_t ENABLE:1; /*!< bit: 1 Enable */ |
AnnaBridge | 171:3a7713b1edbc | 65 | uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 66 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 67 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 68 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 69 | } DAC_CTRLA_Type; |
AnnaBridge | 171:3a7713b1edbc | 70 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 71 | |
AnnaBridge | 171:3a7713b1edbc | 72 | #define DAC_CTRLA_OFFSET 0x0 /**< \brief (DAC_CTRLA offset) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 73 | #define DAC_CTRLA_RESETVALUE 0x00ul /**< \brief (DAC_CTRLA reset_value) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 74 | |
AnnaBridge | 171:3a7713b1edbc | 75 | #define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ |
AnnaBridge | 171:3a7713b1edbc | 76 | #define DAC_CTRLA_SWRST (0x1ul << DAC_CTRLA_SWRST_Pos) |
AnnaBridge | 171:3a7713b1edbc | 77 | #define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable */ |
AnnaBridge | 171:3a7713b1edbc | 78 | #define DAC_CTRLA_ENABLE (0x1ul << DAC_CTRLA_ENABLE_Pos) |
AnnaBridge | 171:3a7713b1edbc | 79 | #define DAC_CTRLA_RUNSTDBY_Pos 2 /**< \brief (DAC_CTRLA) Run in Standby */ |
AnnaBridge | 171:3a7713b1edbc | 80 | #define DAC_CTRLA_RUNSTDBY (0x1ul << DAC_CTRLA_RUNSTDBY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 81 | #define DAC_CTRLA_MASK 0x07ul /**< \brief (DAC_CTRLA) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 82 | |
AnnaBridge | 171:3a7713b1edbc | 83 | /* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */ |
AnnaBridge | 171:3a7713b1edbc | 84 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 85 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 86 | struct { |
AnnaBridge | 171:3a7713b1edbc | 87 | uint8_t EOEN:1; /*!< bit: 0 External Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 88 | uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 89 | uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */ |
AnnaBridge | 171:3a7713b1edbc | 90 | uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */ |
AnnaBridge | 171:3a7713b1edbc | 91 | uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */ |
AnnaBridge | 171:3a7713b1edbc | 92 | uint8_t :1; /*!< bit: 5 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 93 | uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */ |
AnnaBridge | 171:3a7713b1edbc | 94 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 95 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 96 | } DAC_CTRLB_Type; |
AnnaBridge | 171:3a7713b1edbc | 97 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 98 | |
AnnaBridge | 171:3a7713b1edbc | 99 | #define DAC_CTRLB_OFFSET 0x1 /**< \brief (DAC_CTRLB offset) Control B */ |
AnnaBridge | 171:3a7713b1edbc | 100 | #define DAC_CTRLB_RESETVALUE 0x00ul /**< \brief (DAC_CTRLB reset_value) Control B */ |
AnnaBridge | 171:3a7713b1edbc | 101 | |
AnnaBridge | 171:3a7713b1edbc | 102 | #define DAC_CTRLB_EOEN_Pos 0 /**< \brief (DAC_CTRLB) External Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 103 | #define DAC_CTRLB_EOEN (0x1ul << DAC_CTRLB_EOEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 104 | #define DAC_CTRLB_IOEN_Pos 1 /**< \brief (DAC_CTRLB) Internal Output Enable */ |
AnnaBridge | 171:3a7713b1edbc | 105 | #define DAC_CTRLB_IOEN (0x1ul << DAC_CTRLB_IOEN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 106 | #define DAC_CTRLB_LEFTADJ_Pos 2 /**< \brief (DAC_CTRLB) Left Adjusted Data */ |
AnnaBridge | 171:3a7713b1edbc | 107 | #define DAC_CTRLB_LEFTADJ (0x1ul << DAC_CTRLB_LEFTADJ_Pos) |
AnnaBridge | 171:3a7713b1edbc | 108 | #define DAC_CTRLB_VPD_Pos 3 /**< \brief (DAC_CTRLB) Voltage Pump Disable */ |
AnnaBridge | 171:3a7713b1edbc | 109 | #define DAC_CTRLB_VPD (0x1ul << DAC_CTRLB_VPD_Pos) |
AnnaBridge | 171:3a7713b1edbc | 110 | #define DAC_CTRLB_BDWP_Pos 4 /**< \brief (DAC_CTRLB) Bypass DATABUF Write Protection */ |
AnnaBridge | 171:3a7713b1edbc | 111 | #define DAC_CTRLB_BDWP (0x1ul << DAC_CTRLB_BDWP_Pos) |
AnnaBridge | 171:3a7713b1edbc | 112 | #define DAC_CTRLB_REFSEL_Pos 6 /**< \brief (DAC_CTRLB) Reference Selection */ |
AnnaBridge | 171:3a7713b1edbc | 113 | #define DAC_CTRLB_REFSEL_Msk (0x3ul << DAC_CTRLB_REFSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 114 | #define DAC_CTRLB_REFSEL(value) ((DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 115 | #define DAC_CTRLB_REFSEL_INT1V_Val 0x0ul /**< \brief (DAC_CTRLB) Internal 1.0V reference */ |
AnnaBridge | 171:3a7713b1edbc | 116 | #define DAC_CTRLB_REFSEL_AVCC_Val 0x1ul /**< \brief (DAC_CTRLB) AVCC */ |
AnnaBridge | 171:3a7713b1edbc | 117 | #define DAC_CTRLB_REFSEL_VREFP_Val 0x2ul /**< \brief (DAC_CTRLB) External reference */ |
AnnaBridge | 171:3a7713b1edbc | 118 | #define DAC_CTRLB_REFSEL_INT1V (DAC_CTRLB_REFSEL_INT1V_Val << DAC_CTRLB_REFSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 119 | #define DAC_CTRLB_REFSEL_AVCC (DAC_CTRLB_REFSEL_AVCC_Val << DAC_CTRLB_REFSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 120 | #define DAC_CTRLB_REFSEL_VREFP (DAC_CTRLB_REFSEL_VREFP_Val << DAC_CTRLB_REFSEL_Pos) |
AnnaBridge | 171:3a7713b1edbc | 121 | #define DAC_CTRLB_MASK 0xDFul /**< \brief (DAC_CTRLB) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 122 | |
AnnaBridge | 171:3a7713b1edbc | 123 | /* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */ |
AnnaBridge | 171:3a7713b1edbc | 124 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 125 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 126 | struct { |
AnnaBridge | 171:3a7713b1edbc | 127 | uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */ |
AnnaBridge | 171:3a7713b1edbc | 128 | uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */ |
AnnaBridge | 171:3a7713b1edbc | 129 | uint8_t :6; /*!< bit: 2.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 130 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 131 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 132 | } DAC_EVCTRL_Type; |
AnnaBridge | 171:3a7713b1edbc | 133 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 134 | |
AnnaBridge | 171:3a7713b1edbc | 135 | #define DAC_EVCTRL_OFFSET 0x2 /**< \brief (DAC_EVCTRL offset) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 136 | #define DAC_EVCTRL_RESETVALUE 0x00ul /**< \brief (DAC_EVCTRL reset_value) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 137 | |
AnnaBridge | 171:3a7713b1edbc | 138 | #define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input */ |
AnnaBridge | 171:3a7713b1edbc | 139 | #define DAC_EVCTRL_STARTEI (0x1ul << DAC_EVCTRL_STARTEI_Pos) |
AnnaBridge | 171:3a7713b1edbc | 140 | #define DAC_EVCTRL_EMPTYEO_Pos 1 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output */ |
AnnaBridge | 171:3a7713b1edbc | 141 | #define DAC_EVCTRL_EMPTYEO (0x1ul << DAC_EVCTRL_EMPTYEO_Pos) |
AnnaBridge | 171:3a7713b1edbc | 142 | #define DAC_EVCTRL_MASK 0x03ul /**< \brief (DAC_EVCTRL) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 143 | |
AnnaBridge | 171:3a7713b1edbc | 144 | /* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 145 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 146 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 147 | struct { |
AnnaBridge | 171:3a7713b1edbc | 148 | uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 149 | uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 150 | uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 151 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 152 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 153 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 154 | } DAC_INTENCLR_Type; |
AnnaBridge | 171:3a7713b1edbc | 155 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 156 | |
AnnaBridge | 171:3a7713b1edbc | 157 | #define DAC_INTENCLR_OFFSET 0x4 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 158 | #define DAC_INTENCLR_RESETVALUE 0x00ul /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 159 | |
AnnaBridge | 171:3a7713b1edbc | 160 | #define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 161 | #define DAC_INTENCLR_UNDERRUN (0x1ul << DAC_INTENCLR_UNDERRUN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 162 | #define DAC_INTENCLR_EMPTY_Pos 1 /**< \brief (DAC_INTENCLR) Data Buffer Empty Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 163 | #define DAC_INTENCLR_EMPTY (0x1ul << DAC_INTENCLR_EMPTY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 164 | #define DAC_INTENCLR_SYNCRDY_Pos 2 /**< \brief (DAC_INTENCLR) Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 165 | #define DAC_INTENCLR_SYNCRDY (0x1ul << DAC_INTENCLR_SYNCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 166 | #define DAC_INTENCLR_MASK 0x07ul /**< \brief (DAC_INTENCLR) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 167 | |
AnnaBridge | 171:3a7713b1edbc | 168 | /* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */ |
AnnaBridge | 171:3a7713b1edbc | 169 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 170 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 171 | struct { |
AnnaBridge | 171:3a7713b1edbc | 172 | uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 173 | uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 174 | uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 175 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 176 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 177 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 178 | } DAC_INTENSET_Type; |
AnnaBridge | 171:3a7713b1edbc | 179 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 180 | |
AnnaBridge | 171:3a7713b1edbc | 181 | #define DAC_INTENSET_OFFSET 0x5 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 182 | #define DAC_INTENSET_RESETVALUE 0x00ul /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 183 | |
AnnaBridge | 171:3a7713b1edbc | 184 | #define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 185 | #define DAC_INTENSET_UNDERRUN (0x1ul << DAC_INTENSET_UNDERRUN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 186 | #define DAC_INTENSET_EMPTY_Pos 1 /**< \brief (DAC_INTENSET) Data Buffer Empty Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 187 | #define DAC_INTENSET_EMPTY (0x1ul << DAC_INTENSET_EMPTY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 188 | #define DAC_INTENSET_SYNCRDY_Pos 2 /**< \brief (DAC_INTENSET) Synchronization Ready Interrupt Enable */ |
AnnaBridge | 171:3a7713b1edbc | 189 | #define DAC_INTENSET_SYNCRDY (0x1ul << DAC_INTENSET_SYNCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 190 | #define DAC_INTENSET_MASK 0x07ul /**< \brief (DAC_INTENSET) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 191 | |
AnnaBridge | 171:3a7713b1edbc | 192 | /* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */ |
AnnaBridge | 171:3a7713b1edbc | 193 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 194 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 195 | struct { |
AnnaBridge | 171:3a7713b1edbc | 196 | uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */ |
AnnaBridge | 171:3a7713b1edbc | 197 | uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */ |
AnnaBridge | 171:3a7713b1edbc | 198 | uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */ |
AnnaBridge | 171:3a7713b1edbc | 199 | uint8_t :5; /*!< bit: 3.. 7 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 200 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 201 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 202 | } DAC_INTFLAG_Type; |
AnnaBridge | 171:3a7713b1edbc | 203 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 204 | |
AnnaBridge | 171:3a7713b1edbc | 205 | #define DAC_INTFLAG_OFFSET 0x6 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 206 | #define DAC_INTFLAG_RESETVALUE 0x00ul /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 207 | |
AnnaBridge | 171:3a7713b1edbc | 208 | #define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Underrun */ |
AnnaBridge | 171:3a7713b1edbc | 209 | #define DAC_INTFLAG_UNDERRUN (0x1ul << DAC_INTFLAG_UNDERRUN_Pos) |
AnnaBridge | 171:3a7713b1edbc | 210 | #define DAC_INTFLAG_EMPTY_Pos 1 /**< \brief (DAC_INTFLAG) Data Buffer Empty */ |
AnnaBridge | 171:3a7713b1edbc | 211 | #define DAC_INTFLAG_EMPTY (0x1ul << DAC_INTFLAG_EMPTY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 212 | #define DAC_INTFLAG_SYNCRDY_Pos 2 /**< \brief (DAC_INTFLAG) Synchronization Ready */ |
AnnaBridge | 171:3a7713b1edbc | 213 | #define DAC_INTFLAG_SYNCRDY (0x1ul << DAC_INTFLAG_SYNCRDY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 214 | #define DAC_INTFLAG_MASK 0x07ul /**< \brief (DAC_INTFLAG) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 215 | |
AnnaBridge | 171:3a7713b1edbc | 216 | /* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */ |
AnnaBridge | 171:3a7713b1edbc | 217 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 218 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 219 | struct { |
AnnaBridge | 171:3a7713b1edbc | 220 | uint8_t :7; /*!< bit: 0.. 6 Reserved */ |
AnnaBridge | 171:3a7713b1edbc | 221 | uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */ |
AnnaBridge | 171:3a7713b1edbc | 222 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 223 | uint8_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 224 | } DAC_STATUS_Type; |
AnnaBridge | 171:3a7713b1edbc | 225 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 226 | |
AnnaBridge | 171:3a7713b1edbc | 227 | #define DAC_STATUS_OFFSET 0x7 /**< \brief (DAC_STATUS offset) Status */ |
AnnaBridge | 171:3a7713b1edbc | 228 | #define DAC_STATUS_RESETVALUE 0x00ul /**< \brief (DAC_STATUS reset_value) Status */ |
AnnaBridge | 171:3a7713b1edbc | 229 | |
AnnaBridge | 171:3a7713b1edbc | 230 | #define DAC_STATUS_SYNCBUSY_Pos 7 /**< \brief (DAC_STATUS) Synchronization Busy Status */ |
AnnaBridge | 171:3a7713b1edbc | 231 | #define DAC_STATUS_SYNCBUSY (0x1ul << DAC_STATUS_SYNCBUSY_Pos) |
AnnaBridge | 171:3a7713b1edbc | 232 | #define DAC_STATUS_MASK 0x80ul /**< \brief (DAC_STATUS) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 233 | |
AnnaBridge | 171:3a7713b1edbc | 234 | /* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */ |
AnnaBridge | 171:3a7713b1edbc | 235 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 236 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 237 | struct { |
AnnaBridge | 171:3a7713b1edbc | 238 | uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */ |
AnnaBridge | 171:3a7713b1edbc | 239 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 240 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 241 | } DAC_DATA_Type; |
AnnaBridge | 171:3a7713b1edbc | 242 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 243 | |
AnnaBridge | 171:3a7713b1edbc | 244 | #define DAC_DATA_OFFSET 0x8 /**< \brief (DAC_DATA offset) Data */ |
AnnaBridge | 171:3a7713b1edbc | 245 | #define DAC_DATA_RESETVALUE 0x0000ul /**< \brief (DAC_DATA reset_value) Data */ |
AnnaBridge | 171:3a7713b1edbc | 246 | |
AnnaBridge | 171:3a7713b1edbc | 247 | #define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) Data value to be converted */ |
AnnaBridge | 171:3a7713b1edbc | 248 | #define DAC_DATA_DATA_Msk (0xFFFFul << DAC_DATA_DATA_Pos) |
AnnaBridge | 171:3a7713b1edbc | 249 | #define DAC_DATA_DATA(value) ((DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 250 | #define DAC_DATA_MASK 0xFFFFul /**< \brief (DAC_DATA) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 251 | |
AnnaBridge | 171:3a7713b1edbc | 252 | /* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */ |
AnnaBridge | 171:3a7713b1edbc | 253 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 254 | typedef union { |
AnnaBridge | 171:3a7713b1edbc | 255 | struct { |
AnnaBridge | 171:3a7713b1edbc | 256 | uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 257 | } bit; /*!< Structure used for bit access */ |
AnnaBridge | 171:3a7713b1edbc | 258 | uint16_t reg; /*!< Type used for register access */ |
AnnaBridge | 171:3a7713b1edbc | 259 | } DAC_DATABUF_Type; |
AnnaBridge | 171:3a7713b1edbc | 260 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 261 | |
AnnaBridge | 171:3a7713b1edbc | 262 | #define DAC_DATABUF_OFFSET 0xC /**< \brief (DAC_DATABUF offset) Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 263 | #define DAC_DATABUF_RESETVALUE 0x0000ul /**< \brief (DAC_DATABUF reset_value) Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 264 | |
AnnaBridge | 171:3a7713b1edbc | 265 | #define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 266 | #define DAC_DATABUF_DATABUF_Msk (0xFFFFul << DAC_DATABUF_DATABUF_Pos) |
AnnaBridge | 171:3a7713b1edbc | 267 | #define DAC_DATABUF_DATABUF(value) ((DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos))) |
AnnaBridge | 171:3a7713b1edbc | 268 | #define DAC_DATABUF_MASK 0xFFFFul /**< \brief (DAC_DATABUF) MASK Register */ |
AnnaBridge | 171:3a7713b1edbc | 269 | |
AnnaBridge | 171:3a7713b1edbc | 270 | /** \brief DAC hardware registers */ |
AnnaBridge | 171:3a7713b1edbc | 271 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
AnnaBridge | 171:3a7713b1edbc | 272 | typedef struct { |
AnnaBridge | 171:3a7713b1edbc | 273 | __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */ |
AnnaBridge | 171:3a7713b1edbc | 274 | __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */ |
AnnaBridge | 171:3a7713b1edbc | 275 | __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */ |
AnnaBridge | 171:3a7713b1edbc | 276 | RoReg8 Reserved1[0x1]; |
AnnaBridge | 171:3a7713b1edbc | 277 | __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */ |
AnnaBridge | 171:3a7713b1edbc | 278 | __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */ |
AnnaBridge | 171:3a7713b1edbc | 279 | __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */ |
AnnaBridge | 171:3a7713b1edbc | 280 | __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */ |
AnnaBridge | 171:3a7713b1edbc | 281 | __IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */ |
AnnaBridge | 171:3a7713b1edbc | 282 | RoReg8 Reserved2[0x2]; |
AnnaBridge | 171:3a7713b1edbc | 283 | __IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */ |
AnnaBridge | 171:3a7713b1edbc | 284 | } Dac; |
AnnaBridge | 171:3a7713b1edbc | 285 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
AnnaBridge | 171:3a7713b1edbc | 286 | |
AnnaBridge | 171:3a7713b1edbc | 287 | /*@}*/ |
AnnaBridge | 171:3a7713b1edbc | 288 | |
AnnaBridge | 171:3a7713b1edbc | 289 | #endif /* _SAMD21_DAC_COMPONENT_ */ |