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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_ll_rcc.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_rcc.h@165:d1b4690b3f8b

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/**
AnnaBridge	165:d1b4690b3f8b	2	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	3	* @file stm32l4xx_ll_rcc.h
AnnaBridge	165:d1b4690b3f8b	4	* @author MCD Application Team
AnnaBridge	165:d1b4690b3f8b	5	* @brief Header file of RCC LL module.
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	7	* @attention
AnnaBridge	165:d1b4690b3f8b	8	*
AnnaBridge	165:d1b4690b3f8b	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	165:d1b4690b3f8b	10	*
AnnaBridge	165:d1b4690b3f8b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:d1b4690b3f8b	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:d1b4690b3f8b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:d1b4690b3f8b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:d1b4690b3f8b	17	* and/or other materials provided with the distribution.
AnnaBridge	165:d1b4690b3f8b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:d1b4690b3f8b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:d1b4690b3f8b	20	* without specific prior written permission.
AnnaBridge	165:d1b4690b3f8b	21	*
AnnaBridge	165:d1b4690b3f8b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:d1b4690b3f8b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:d1b4690b3f8b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:d1b4690b3f8b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:d1b4690b3f8b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:d1b4690b3f8b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:d1b4690b3f8b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:d1b4690b3f8b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:d1b4690b3f8b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:d1b4690b3f8b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:d1b4690b3f8b	32	*
AnnaBridge	165:d1b4690b3f8b	33	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	34	*/
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	37	#ifndef __STM32L4xx_LL_RCC_H
AnnaBridge	165:d1b4690b3f8b	38	#define __STM32L4xx_LL_RCC_H
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	41	extern "C" {
AnnaBridge	165:d1b4690b3f8b	42	#endif
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	45	#include "stm32l4xx.h"
AnnaBridge	165:d1b4690b3f8b	46
AnnaBridge	165:d1b4690b3f8b	47	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	165:d1b4690b3f8b	48	* @{
AnnaBridge	165:d1b4690b3f8b	49	*/
AnnaBridge	165:d1b4690b3f8b	50
AnnaBridge	165:d1b4690b3f8b	51	#if defined(RCC)
AnnaBridge	165:d1b4690b3f8b	52
AnnaBridge	165:d1b4690b3f8b	53	/** @defgroup RCC_LL RCC
AnnaBridge	165:d1b4690b3f8b	54	* @{
AnnaBridge	165:d1b4690b3f8b	55	*/
AnnaBridge	165:d1b4690b3f8b	56
AnnaBridge	165:d1b4690b3f8b	57	/* Private types -------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	58	/* Private variables ---------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	59	/** @defgroup RCC_LL_Private_Variables RCC Private Variables
AnnaBridge	165:d1b4690b3f8b	60	* @{
AnnaBridge	165:d1b4690b3f8b	61	*/
AnnaBridge	165:d1b4690b3f8b	62
AnnaBridge	165:d1b4690b3f8b	63	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	165:d1b4690b3f8b	64	static const uint8_t aRCC_PLLSAI2DIVRPrescTable[4] = {2, 4, 8, 16};
AnnaBridge	165:d1b4690b3f8b	65	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	165:d1b4690b3f8b	66
AnnaBridge	165:d1b4690b3f8b	67	/**
AnnaBridge	165:d1b4690b3f8b	68	* @}
AnnaBridge	165:d1b4690b3f8b	69	*/
AnnaBridge	165:d1b4690b3f8b	70
AnnaBridge	165:d1b4690b3f8b	71	/* Private constants ---------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	72	/** @defgroup RCC_LL_Private_Constants RCC Private Constants
AnnaBridge	165:d1b4690b3f8b	73	* @{
AnnaBridge	165:d1b4690b3f8b	74	*/
AnnaBridge	165:d1b4690b3f8b	75	/* Defines used to perform offsets*/
AnnaBridge	165:d1b4690b3f8b	76	/* Offset used to access to RCC_CCIPR and RCC_CCIPR2 registers */
AnnaBridge	165:d1b4690b3f8b	77	#define RCC_OFFSET_CCIPR 0U
AnnaBridge	165:d1b4690b3f8b	78	#define RCC_OFFSET_CCIPR2 0x14U
AnnaBridge	165:d1b4690b3f8b	79
AnnaBridge	165:d1b4690b3f8b	80	/**
AnnaBridge	165:d1b4690b3f8b	81	* @}
AnnaBridge	165:d1b4690b3f8b	82	*/
AnnaBridge	165:d1b4690b3f8b	83
AnnaBridge	165:d1b4690b3f8b	84	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	85	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	86	/** @defgroup RCC_LL_Private_Macros RCC Private Macros
AnnaBridge	165:d1b4690b3f8b	87	* @{
AnnaBridge	165:d1b4690b3f8b	88	*/
AnnaBridge	165:d1b4690b3f8b	89	/**
AnnaBridge	165:d1b4690b3f8b	90	* @}
AnnaBridge	165:d1b4690b3f8b	91	*/
AnnaBridge	165:d1b4690b3f8b	92	#endif /USE_FULL_LL_DRIVER/
AnnaBridge	165:d1b4690b3f8b	93
AnnaBridge	165:d1b4690b3f8b	94	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	95	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	96	/** @defgroup RCC_LL_Exported_Types RCC Exported Types
AnnaBridge	165:d1b4690b3f8b	97	* @{
AnnaBridge	165:d1b4690b3f8b	98	*/
AnnaBridge	165:d1b4690b3f8b	99
AnnaBridge	165:d1b4690b3f8b	100	/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
AnnaBridge	165:d1b4690b3f8b	101	* @{
AnnaBridge	165:d1b4690b3f8b	102	*/
AnnaBridge	165:d1b4690b3f8b	103
AnnaBridge	165:d1b4690b3f8b	104	/**
AnnaBridge	165:d1b4690b3f8b	105	* @brief RCC Clocks Frequency Structure
AnnaBridge	165:d1b4690b3f8b	106	*/
AnnaBridge	165:d1b4690b3f8b	107	typedef struct
AnnaBridge	165:d1b4690b3f8b	108	{
AnnaBridge	165:d1b4690b3f8b	109	uint32_t SYSCLK_Frequency; /!< SYSCLK clock frequency /
AnnaBridge	165:d1b4690b3f8b	110	uint32_t HCLK_Frequency; /!< HCLK clock frequency /
AnnaBridge	165:d1b4690b3f8b	111	uint32_t PCLK1_Frequency; /!< PCLK1 clock frequency /
AnnaBridge	165:d1b4690b3f8b	112	uint32_t PCLK2_Frequency; /!< PCLK2 clock frequency /
AnnaBridge	165:d1b4690b3f8b	113	} LL_RCC_ClocksTypeDef;
AnnaBridge	165:d1b4690b3f8b	114
AnnaBridge	165:d1b4690b3f8b	115	/**
AnnaBridge	165:d1b4690b3f8b	116	* @}
AnnaBridge	165:d1b4690b3f8b	117	*/
AnnaBridge	165:d1b4690b3f8b	118
AnnaBridge	165:d1b4690b3f8b	119	/**
AnnaBridge	165:d1b4690b3f8b	120	* @}
AnnaBridge	165:d1b4690b3f8b	121	*/
AnnaBridge	165:d1b4690b3f8b	122	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	123
AnnaBridge	165:d1b4690b3f8b	124	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	125	/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
AnnaBridge	165:d1b4690b3f8b	126	* @{
AnnaBridge	165:d1b4690b3f8b	127	*/
AnnaBridge	165:d1b4690b3f8b	128
AnnaBridge	165:d1b4690b3f8b	129	/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
AnnaBridge	165:d1b4690b3f8b	130	* @brief Defines used to adapt values of different oscillators
AnnaBridge	165:d1b4690b3f8b	131	* @note These values could be modified in the user environment according to
AnnaBridge	165:d1b4690b3f8b	132	* HW set-up.
AnnaBridge	165:d1b4690b3f8b	133	* @{
AnnaBridge	165:d1b4690b3f8b	134	*/
AnnaBridge	165:d1b4690b3f8b	135	#if !defined (HSE_VALUE)
AnnaBridge	165:d1b4690b3f8b	136	#define HSE_VALUE 8000000U /!< Value of the HSE oscillator in Hz /
AnnaBridge	165:d1b4690b3f8b	137	#endif /* HSE_VALUE */
AnnaBridge	165:d1b4690b3f8b	138
AnnaBridge	165:d1b4690b3f8b	139	#if !defined (HSI_VALUE)
AnnaBridge	165:d1b4690b3f8b	140	#define HSI_VALUE 16000000U /!< Value of the HSI oscillator in Hz /
AnnaBridge	165:d1b4690b3f8b	141	#endif /* HSI_VALUE */
AnnaBridge	165:d1b4690b3f8b	142
AnnaBridge	165:d1b4690b3f8b	143	#if !defined (LSE_VALUE)
AnnaBridge	165:d1b4690b3f8b	144	#define LSE_VALUE 32768U /!< Value of the LSE oscillator in Hz /
AnnaBridge	165:d1b4690b3f8b	145	#endif /* LSE_VALUE */
AnnaBridge	165:d1b4690b3f8b	146
AnnaBridge	165:d1b4690b3f8b	147	#if !defined (LSI_VALUE)
AnnaBridge	165:d1b4690b3f8b	148	#define LSI_VALUE 32000U /!< Value of the LSI oscillator in Hz /
AnnaBridge	165:d1b4690b3f8b	149	#endif /* LSI_VALUE */
AnnaBridge	165:d1b4690b3f8b	150	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	151
AnnaBridge	165:d1b4690b3f8b	152	#if !defined (HSI48_VALUE)
AnnaBridge	165:d1b4690b3f8b	153	#define HSI48_VALUE 48000000U /!< Value of the HSI48 oscillator in Hz /
AnnaBridge	165:d1b4690b3f8b	154	#endif /* HSI48_VALUE */
AnnaBridge	165:d1b4690b3f8b	155	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	156	/**
AnnaBridge	165:d1b4690b3f8b	157	* @}
AnnaBridge	165:d1b4690b3f8b	158	*/
AnnaBridge	165:d1b4690b3f8b	159
AnnaBridge	165:d1b4690b3f8b	160	/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
AnnaBridge	165:d1b4690b3f8b	161	* @brief Flags defines which can be used with LL_RCC_WriteReg function
AnnaBridge	165:d1b4690b3f8b	162	* @{
AnnaBridge	165:d1b4690b3f8b	163	*/
AnnaBridge	165:d1b4690b3f8b	164	#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /!< LSI Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	165	#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /!< LSE Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	166	#define LL_RCC_CICR_MSIRDYC RCC_CICR_MSIRDYC /!< MSI Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	167	#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /!< HSI Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	168	#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /!< HSE Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	169	#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /!< PLL Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	170	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	171	#define LL_RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC /!< HSI48 Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	172	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	173	#define LL_RCC_CICR_PLLSAI1RDYC RCC_CICR_PLLSAI1RDYC /!< PLLSAI1 Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	174	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	175	#define LL_RCC_CICR_PLLSAI2RDYC RCC_CICR_PLLSAI2RDYC /!< PLLSAI2 Ready Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	176	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	177	#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /!< LSE Clock Security System Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	178	#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /!< Clock Security System Interrupt Clear /
AnnaBridge	165:d1b4690b3f8b	179	/**
AnnaBridge	165:d1b4690b3f8b	180	* @}
AnnaBridge	165:d1b4690b3f8b	181	*/
AnnaBridge	165:d1b4690b3f8b	182
AnnaBridge	165:d1b4690b3f8b	183	/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
AnnaBridge	165:d1b4690b3f8b	184	* @brief Flags defines which can be used with LL_RCC_ReadReg function
AnnaBridge	165:d1b4690b3f8b	185	* @{
AnnaBridge	165:d1b4690b3f8b	186	*/
AnnaBridge	165:d1b4690b3f8b	187	#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /!< LSI Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	188	#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /!< LSE Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	189	#define LL_RCC_CIFR_MSIRDYF RCC_CIFR_MSIRDYF /!< MSI Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	190	#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /!< HSI Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	191	#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /!< HSE Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	192	#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /!< PLL Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	193	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	194	#define LL_RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF /!< HSI48 Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	195	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	196	#define LL_RCC_CIFR_PLLSAI1RDYF RCC_CIFR_PLLSAI1RDYF /!< PLLSAI1 Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	197	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	198	#define LL_RCC_CIFR_PLLSAI2RDYF RCC_CIFR_PLLSAI2RDYF /!< PLLSAI2 Ready Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	199	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	200	#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /!< LSE Clock Security System Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	201	#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /!< Clock Security System Interrupt flag /
AnnaBridge	165:d1b4690b3f8b	202	#define LL_RCC_CSR_FWRSTF RCC_CSR_FWRSTF /!< Firewall reset flag /
AnnaBridge	165:d1b4690b3f8b	203	#define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /!< Low-Power reset flag /
AnnaBridge	165:d1b4690b3f8b	204	#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /!< OBL reset flag /
AnnaBridge	165:d1b4690b3f8b	205	#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /!< PIN reset flag /
AnnaBridge	165:d1b4690b3f8b	206	#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /!< Software Reset flag /
AnnaBridge	165:d1b4690b3f8b	207	#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /!< Independent Watchdog reset flag /
AnnaBridge	165:d1b4690b3f8b	208	#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /!< Window watchdog reset flag /
AnnaBridge	165:d1b4690b3f8b	209	#define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /!< BOR reset flag /
AnnaBridge	165:d1b4690b3f8b	210	/**
AnnaBridge	165:d1b4690b3f8b	211	* @}
AnnaBridge	165:d1b4690b3f8b	212	*/
AnnaBridge	165:d1b4690b3f8b	213
AnnaBridge	165:d1b4690b3f8b	214	/** @defgroup RCC_LL_EC_IT IT Defines
AnnaBridge	165:d1b4690b3f8b	215	* @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
AnnaBridge	165:d1b4690b3f8b	216	* @{
AnnaBridge	165:d1b4690b3f8b	217	*/
AnnaBridge	165:d1b4690b3f8b	218	#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /!< LSI Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	219	#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /!< LSE Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	220	#define LL_RCC_CIER_MSIRDYIE RCC_CIER_MSIRDYIE /!< MSI Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	221	#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /!< HSI Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	222	#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /!< HSE Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	223	#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /!< PLL Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	224	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	225	#define LL_RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE /!< HSI48 Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	226	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	227	#define LL_RCC_CIER_PLLSAI1RDYIE RCC_CIER_PLLSAI1RDYIE /!< PLLSAI1 Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	228	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	229	#define LL_RCC_CIER_PLLSAI2RDYIE RCC_CIER_PLLSAI2RDYIE /!< PLLSAI2 Ready Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	230	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	231	#define LL_RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE /!< LSE CSS Interrupt Enable /
AnnaBridge	165:d1b4690b3f8b	232	/**
AnnaBridge	165:d1b4690b3f8b	233	* @}
AnnaBridge	165:d1b4690b3f8b	234	*/
AnnaBridge	165:d1b4690b3f8b	235
AnnaBridge	165:d1b4690b3f8b	236	/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
AnnaBridge	165:d1b4690b3f8b	237	* @{
AnnaBridge	165:d1b4690b3f8b	238	*/
AnnaBridge	165:d1b4690b3f8b	239	#define LL_RCC_LSEDRIVE_LOW 0x00000000U /!< Xtal mode lower driving capability /
AnnaBridge	165:d1b4690b3f8b	240	#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /!< Xtal mode medium low driving capability /
AnnaBridge	165:d1b4690b3f8b	241	#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /!< Xtal mode medium high driving capability /
AnnaBridge	165:d1b4690b3f8b	242	#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /!< Xtal mode higher driving capability /
AnnaBridge	165:d1b4690b3f8b	243	/**
AnnaBridge	165:d1b4690b3f8b	244	* @}
AnnaBridge	165:d1b4690b3f8b	245	*/
AnnaBridge	165:d1b4690b3f8b	246
AnnaBridge	165:d1b4690b3f8b	247	/** @defgroup RCC_LL_EC_MSIRANGE MSI clock ranges
AnnaBridge	165:d1b4690b3f8b	248	* @{
AnnaBridge	165:d1b4690b3f8b	249	*/
AnnaBridge	165:d1b4690b3f8b	250	#define LL_RCC_MSIRANGE_0 RCC_CR_MSIRANGE_0 /!< MSI = 100 KHz /
AnnaBridge	165:d1b4690b3f8b	251	#define LL_RCC_MSIRANGE_1 RCC_CR_MSIRANGE_1 /!< MSI = 200 KHz /
AnnaBridge	165:d1b4690b3f8b	252	#define LL_RCC_MSIRANGE_2 RCC_CR_MSIRANGE_2 /!< MSI = 400 KHz /
AnnaBridge	165:d1b4690b3f8b	253	#define LL_RCC_MSIRANGE_3 RCC_CR_MSIRANGE_3 /!< MSI = 800 KHz /
AnnaBridge	165:d1b4690b3f8b	254	#define LL_RCC_MSIRANGE_4 RCC_CR_MSIRANGE_4 /!< MSI = 1 MHz /
AnnaBridge	165:d1b4690b3f8b	255	#define LL_RCC_MSIRANGE_5 RCC_CR_MSIRANGE_5 /!< MSI = 2 MHz /
AnnaBridge	165:d1b4690b3f8b	256	#define LL_RCC_MSIRANGE_6 RCC_CR_MSIRANGE_6 /!< MSI = 4 MHz /
AnnaBridge	165:d1b4690b3f8b	257	#define LL_RCC_MSIRANGE_7 RCC_CR_MSIRANGE_7 /!< MSI = 8 MHz /
AnnaBridge	165:d1b4690b3f8b	258	#define LL_RCC_MSIRANGE_8 RCC_CR_MSIRANGE_8 /!< MSI = 16 MHz /
AnnaBridge	165:d1b4690b3f8b	259	#define LL_RCC_MSIRANGE_9 RCC_CR_MSIRANGE_9 /!< MSI = 24 MHz /
AnnaBridge	165:d1b4690b3f8b	260	#define LL_RCC_MSIRANGE_10 RCC_CR_MSIRANGE_10 /!< MSI = 32 MHz /
AnnaBridge	165:d1b4690b3f8b	261	#define LL_RCC_MSIRANGE_11 RCC_CR_MSIRANGE_11 /!< MSI = 48 MHz /
AnnaBridge	165:d1b4690b3f8b	262	/**
AnnaBridge	165:d1b4690b3f8b	263	* @}
AnnaBridge	165:d1b4690b3f8b	264	*/
AnnaBridge	165:d1b4690b3f8b	265
AnnaBridge	165:d1b4690b3f8b	266	/** @defgroup RCC_LL_EC_MSISRANGE MSI range after Standby mode
AnnaBridge	165:d1b4690b3f8b	267	* @{
AnnaBridge	165:d1b4690b3f8b	268	*/
AnnaBridge	165:d1b4690b3f8b	269	#define LL_RCC_MSISRANGE_4 RCC_CSR_MSISRANGE_1 /!< MSI = 1 MHz /
AnnaBridge	165:d1b4690b3f8b	270	#define LL_RCC_MSISRANGE_5 RCC_CSR_MSISRANGE_2 /!< MSI = 2 MHz /
AnnaBridge	165:d1b4690b3f8b	271	#define LL_RCC_MSISRANGE_6 RCC_CSR_MSISRANGE_4 /!< MSI = 4 MHz /
AnnaBridge	165:d1b4690b3f8b	272	#define LL_RCC_MSISRANGE_7 RCC_CSR_MSISRANGE_8 /!< MSI = 8 MHz /
AnnaBridge	165:d1b4690b3f8b	273	/**
AnnaBridge	165:d1b4690b3f8b	274	* @}
AnnaBridge	165:d1b4690b3f8b	275	*/
AnnaBridge	165:d1b4690b3f8b	276
AnnaBridge	165:d1b4690b3f8b	277	/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection
AnnaBridge	165:d1b4690b3f8b	278	* @{
AnnaBridge	165:d1b4690b3f8b	279	*/
AnnaBridge	165:d1b4690b3f8b	280	#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /!< LSI selection for low speed clock /
AnnaBridge	165:d1b4690b3f8b	281	#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /!< LSE selection for low speed clock /
AnnaBridge	165:d1b4690b3f8b	282	/**
AnnaBridge	165:d1b4690b3f8b	283	* @}
AnnaBridge	165:d1b4690b3f8b	284	*/
AnnaBridge	165:d1b4690b3f8b	285
AnnaBridge	165:d1b4690b3f8b	286	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
AnnaBridge	165:d1b4690b3f8b	287	* @{
AnnaBridge	165:d1b4690b3f8b	288	*/
AnnaBridge	165:d1b4690b3f8b	289	#define LL_RCC_SYS_CLKSOURCE_MSI RCC_CFGR_SW_MSI /!< MSI selection as system clock /
AnnaBridge	165:d1b4690b3f8b	290	#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /!< HSI selection as system clock /
AnnaBridge	165:d1b4690b3f8b	291	#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /!< HSE selection as system clock /
AnnaBridge	165:d1b4690b3f8b	292	#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /!< PLL selection as system clock /
AnnaBridge	165:d1b4690b3f8b	293	/**
AnnaBridge	165:d1b4690b3f8b	294	* @}
AnnaBridge	165:d1b4690b3f8b	295	*/
AnnaBridge	165:d1b4690b3f8b	296
AnnaBridge	165:d1b4690b3f8b	297	/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
AnnaBridge	165:d1b4690b3f8b	298	* @{
AnnaBridge	165:d1b4690b3f8b	299	*/
AnnaBridge	165:d1b4690b3f8b	300	#define LL_RCC_SYS_CLKSOURCE_STATUS_MSI RCC_CFGR_SWS_MSI /!< MSI used as system clock /
AnnaBridge	165:d1b4690b3f8b	301	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /!< HSI used as system clock /
AnnaBridge	165:d1b4690b3f8b	302	#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /!< HSE used as system clock /
AnnaBridge	165:d1b4690b3f8b	303	#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /!< PLL used as system clock /
AnnaBridge	165:d1b4690b3f8b	304	/**
AnnaBridge	165:d1b4690b3f8b	305	* @}
AnnaBridge	165:d1b4690b3f8b	306	*/
AnnaBridge	165:d1b4690b3f8b	307
AnnaBridge	165:d1b4690b3f8b	308	/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
AnnaBridge	165:d1b4690b3f8b	309	* @{
AnnaBridge	165:d1b4690b3f8b	310	*/
AnnaBridge	165:d1b4690b3f8b	311	#define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /!< SYSCLK not divided /
AnnaBridge	165:d1b4690b3f8b	312	#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /!< SYSCLK divided by 2 /
AnnaBridge	165:d1b4690b3f8b	313	#define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /!< SYSCLK divided by 4 /
AnnaBridge	165:d1b4690b3f8b	314	#define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /!< SYSCLK divided by 8 /
AnnaBridge	165:d1b4690b3f8b	315	#define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /!< SYSCLK divided by 16 /
AnnaBridge	165:d1b4690b3f8b	316	#define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /!< SYSCLK divided by 64 /
AnnaBridge	165:d1b4690b3f8b	317	#define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /!< SYSCLK divided by 128 /
AnnaBridge	165:d1b4690b3f8b	318	#define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /!< SYSCLK divided by 256 /
AnnaBridge	165:d1b4690b3f8b	319	#define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /!< SYSCLK divided by 512 /
AnnaBridge	165:d1b4690b3f8b	320	/**
AnnaBridge	165:d1b4690b3f8b	321	* @}
AnnaBridge	165:d1b4690b3f8b	322	*/
AnnaBridge	165:d1b4690b3f8b	323
AnnaBridge	165:d1b4690b3f8b	324	/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
AnnaBridge	165:d1b4690b3f8b	325	* @{
AnnaBridge	165:d1b4690b3f8b	326	*/
AnnaBridge	165:d1b4690b3f8b	327	#define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /!< HCLK not divided /
AnnaBridge	165:d1b4690b3f8b	328	#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /!< HCLK divided by 2 /
AnnaBridge	165:d1b4690b3f8b	329	#define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /!< HCLK divided by 4 /
AnnaBridge	165:d1b4690b3f8b	330	#define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /!< HCLK divided by 8 /
AnnaBridge	165:d1b4690b3f8b	331	#define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /!< HCLK divided by 16 /
AnnaBridge	165:d1b4690b3f8b	332	/**
AnnaBridge	165:d1b4690b3f8b	333	* @}
AnnaBridge	165:d1b4690b3f8b	334	*/
AnnaBridge	165:d1b4690b3f8b	335
AnnaBridge	165:d1b4690b3f8b	336	/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
AnnaBridge	165:d1b4690b3f8b	337	* @{
AnnaBridge	165:d1b4690b3f8b	338	*/
AnnaBridge	165:d1b4690b3f8b	339	#define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /!< HCLK not divided /
AnnaBridge	165:d1b4690b3f8b	340	#define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /!< HCLK divided by 2 /
AnnaBridge	165:d1b4690b3f8b	341	#define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /!< HCLK divided by 4 /
AnnaBridge	165:d1b4690b3f8b	342	#define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /!< HCLK divided by 8 /
AnnaBridge	165:d1b4690b3f8b	343	#define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /!< HCLK divided by 16 /
AnnaBridge	165:d1b4690b3f8b	344	/**
AnnaBridge	165:d1b4690b3f8b	345	* @}
AnnaBridge	165:d1b4690b3f8b	346	*/
AnnaBridge	165:d1b4690b3f8b	347
AnnaBridge	165:d1b4690b3f8b	348	/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection
AnnaBridge	165:d1b4690b3f8b	349	* @{
AnnaBridge	165:d1b4690b3f8b	350	*/
AnnaBridge	165:d1b4690b3f8b	351	#define LL_RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /!< MSI selection after wake-up from STOP /
AnnaBridge	165:d1b4690b3f8b	352	#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK /!< HSI selection after wake-up from STOP /
AnnaBridge	165:d1b4690b3f8b	353	/**
AnnaBridge	165:d1b4690b3f8b	354	* @}
AnnaBridge	165:d1b4690b3f8b	355	*/
AnnaBridge	165:d1b4690b3f8b	356
AnnaBridge	165:d1b4690b3f8b	357	/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection
AnnaBridge	165:d1b4690b3f8b	358	* @{
AnnaBridge	165:d1b4690b3f8b	359	*/
AnnaBridge	165:d1b4690b3f8b	360	#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /!< MCO output disabled, no clock on MCO /
AnnaBridge	165:d1b4690b3f8b	361	#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /!< SYSCLK selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	362	#define LL_RCC_MCO1SOURCE_MSI RCC_CFGR_MCOSEL_1 /!< MSI selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	363	#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0\| RCC_CFGR_MCOSEL_1) /!< HSI16 selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	364	#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /!< HSE selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	365	#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_2) /!< Main PLL selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	366	#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSI selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	367	#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0\|RCC_CFGR_MCOSEL_1\|RCC_CFGR_MCOSEL_2) /!< LSE selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	368	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	369	#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR_MCOSEL_3 /!< HSI48 selection as MCO1 source /
AnnaBridge	165:d1b4690b3f8b	370	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	371	/**
AnnaBridge	165:d1b4690b3f8b	372	* @}
AnnaBridge	165:d1b4690b3f8b	373	*/
AnnaBridge	165:d1b4690b3f8b	374
AnnaBridge	165:d1b4690b3f8b	375	/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler
AnnaBridge	165:d1b4690b3f8b	376	* @{
AnnaBridge	165:d1b4690b3f8b	377	*/
AnnaBridge	165:d1b4690b3f8b	378	#define LL_RCC_MCO1_DIV_1 RCC_CFGR_MCOPRE_DIV1 /!< MCO not divided /
AnnaBridge	165:d1b4690b3f8b	379	#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_DIV2 /!< MCO divided by 2 /
AnnaBridge	165:d1b4690b3f8b	380	#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_DIV4 /!< MCO divided by 4 /
AnnaBridge	165:d1b4690b3f8b	381	#define LL_RCC_MCO1_DIV_8 RCC_CFGR_MCOPRE_DIV8 /!< MCO divided by 8 /
AnnaBridge	165:d1b4690b3f8b	382	#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_DIV16 /!< MCO divided by 16 /
AnnaBridge	165:d1b4690b3f8b	383	/**
AnnaBridge	165:d1b4690b3f8b	384	* @}
AnnaBridge	165:d1b4690b3f8b	385	*/
AnnaBridge	165:d1b4690b3f8b	386
AnnaBridge	165:d1b4690b3f8b	387	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	388	/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
AnnaBridge	165:d1b4690b3f8b	389	* @{
AnnaBridge	165:d1b4690b3f8b	390	*/
AnnaBridge	165:d1b4690b3f8b	391	#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /!< No clock enabled for the peripheral /
AnnaBridge	165:d1b4690b3f8b	392	#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /!< Frequency cannot be provided as external clock /
AnnaBridge	165:d1b4690b3f8b	393	/**
AnnaBridge	165:d1b4690b3f8b	394	* @}
AnnaBridge	165:d1b4690b3f8b	395	*/
AnnaBridge	165:d1b4690b3f8b	396	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	397
AnnaBridge	165:d1b4690b3f8b	398	/** @defgroup RCC_LL_EC_USART1_CLKSOURCE Peripheral USART clock source selection
AnnaBridge	165:d1b4690b3f8b	399	* @{
AnnaBridge	165:d1b4690b3f8b	400	*/
AnnaBridge	165:d1b4690b3f8b	401	#define LL_RCC_USART1_CLKSOURCE_PCLK2 (RCC_CCIPR_USART1SEL << 16U) /!< PCLK2 clock used as USART1 clock source /
AnnaBridge	165:d1b4690b3f8b	402	#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_0) /!< SYSCLK clock used as USART1 clock source /
AnnaBridge	165:d1b4690b3f8b	403	#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL_1) /!< HSI clock used as USART1 clock source /
AnnaBridge	165:d1b4690b3f8b	404	#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_CCIPR_USART1SEL << 16U) \| RCC_CCIPR_USART1SEL) /!< LSE clock used as USART1 clock source /
AnnaBridge	165:d1b4690b3f8b	405	#define LL_RCC_USART2_CLKSOURCE_PCLK1 (RCC_CCIPR_USART2SEL << 16U) /!< PCLK1 clock used as USART2 clock source /
AnnaBridge	165:d1b4690b3f8b	406	#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_0) /!< SYSCLK clock used as USART2 clock source /
AnnaBridge	165:d1b4690b3f8b	407	#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL_1) /!< HSI clock used as USART2 clock source /
AnnaBridge	165:d1b4690b3f8b	408	#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_CCIPR_USART2SEL << 16U) \| RCC_CCIPR_USART2SEL) /!< LSE clock used as USART2 clock source /
AnnaBridge	165:d1b4690b3f8b	409	#if defined(RCC_CCIPR_USART3SEL)
AnnaBridge	165:d1b4690b3f8b	410	#define LL_RCC_USART3_CLKSOURCE_PCLK1 (RCC_CCIPR_USART3SEL << 16U) /!< PCLK1 clock used as USART3 clock source /
AnnaBridge	165:d1b4690b3f8b	411	#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_0) /!< SYSCLK clock used as USART3 clock source /
AnnaBridge	165:d1b4690b3f8b	412	#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL_1) /!< HSI clock used as USART3 clock source /
AnnaBridge	165:d1b4690b3f8b	413	#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_CCIPR_USART3SEL << 16U) \| RCC_CCIPR_USART3SEL) /!< LSE clock used as USART3 clock source /
AnnaBridge	165:d1b4690b3f8b	414	#endif /* RCC_CCIPR_USART3SEL */
AnnaBridge	165:d1b4690b3f8b	415	/**
AnnaBridge	165:d1b4690b3f8b	416	* @}
AnnaBridge	165:d1b4690b3f8b	417	*/
AnnaBridge	165:d1b4690b3f8b	418
AnnaBridge	165:d1b4690b3f8b	419	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
AnnaBridge	165:d1b4690b3f8b	420	/** @defgroup RCC_LL_EC_UART4_CLKSOURCE Peripheral UART clock source selection
AnnaBridge	165:d1b4690b3f8b	421	* @{
AnnaBridge	165:d1b4690b3f8b	422	*/
AnnaBridge	165:d1b4690b3f8b	423	#if defined(RCC_CCIPR_UART4SEL)
AnnaBridge	165:d1b4690b3f8b	424	#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR_UART4SEL << 16U) /!< PCLK1 clock used as UART4 clock source /
AnnaBridge	165:d1b4690b3f8b	425	#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_0) /!< SYSCLK clock used as UART4 clock source /
AnnaBridge	165:d1b4690b3f8b	426	#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL_1) /!< HSI clock used as UART4 clock source /
AnnaBridge	165:d1b4690b3f8b	427	#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR_UART4SEL << 16U) \| RCC_CCIPR_UART4SEL) /!< LSE clock used as UART4 clock source /
AnnaBridge	165:d1b4690b3f8b	428	#endif /* RCC_CCIPR_UART4SEL */
AnnaBridge	165:d1b4690b3f8b	429	#if defined(RCC_CCIPR_UART5SEL)
AnnaBridge	165:d1b4690b3f8b	430	#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR_UART5SEL << 16U) /!< PCLK1 clock used as UART5 clock source /
AnnaBridge	165:d1b4690b3f8b	431	#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_0) /!< SYSCLK clock used as UART5 clock source /
AnnaBridge	165:d1b4690b3f8b	432	#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL_1) /!< HSI clock used as UART5 clock source /
AnnaBridge	165:d1b4690b3f8b	433	#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR_UART5SEL << 16U) \| RCC_CCIPR_UART5SEL) /!< LSE clock used as UART5 clock source /
AnnaBridge	165:d1b4690b3f8b	434	#endif /* RCC_CCIPR_UART5SEL */
AnnaBridge	165:d1b4690b3f8b	435	/**
AnnaBridge	165:d1b4690b3f8b	436	* @}
AnnaBridge	165:d1b4690b3f8b	437	*/
AnnaBridge	165:d1b4690b3f8b	438	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
AnnaBridge	165:d1b4690b3f8b	439
AnnaBridge	165:d1b4690b3f8b	440	/** @defgroup RCC_LL_EC_LPUART1_CLKSOURCE Peripheral LPUART clock source selection
AnnaBridge	165:d1b4690b3f8b	441	* @{
AnnaBridge	165:d1b4690b3f8b	442	*/
AnnaBridge	165:d1b4690b3f8b	443	#define LL_RCC_LPUART1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 clock used as LPUART1 clock source /
AnnaBridge	165:d1b4690b3f8b	444	#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0 /!< SYSCLK clock used as LPUART1 clock source /
AnnaBridge	165:d1b4690b3f8b	445	#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1 /!< HSI clock used as LPUART1 clock source /
AnnaBridge	165:d1b4690b3f8b	446	#define LL_RCC_LPUART1_CLKSOURCE_LSE RCC_CCIPR_LPUART1SEL /!< LSE clock used as LPUART1 clock source /
AnnaBridge	165:d1b4690b3f8b	447	/**
AnnaBridge	165:d1b4690b3f8b	448	* @}
AnnaBridge	165:d1b4690b3f8b	449	*/
AnnaBridge	165:d1b4690b3f8b	450
AnnaBridge	165:d1b4690b3f8b	451	/** @defgroup RCC_LL_EC_I2C1_CLKSOURCE Peripheral I2C clock source selection
AnnaBridge	165:d1b4690b3f8b	452	* @{
AnnaBridge	165:d1b4690b3f8b	453	*/
AnnaBridge	165:d1b4690b3f8b	454	#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U)) /!< PCLK1 clock used as I2C1 clock source /
AnnaBridge	165:d1b4690b3f8b	455	#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_0 >> RCC_CCIPR_I2C1SEL_Pos)) /!< SYSCLK clock used as I2C1 clock source /
AnnaBridge	165:d1b4690b3f8b	456	#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL_1 >> RCC_CCIPR_I2C1SEL_Pos)) /!< HSI clock used as I2C1 clock source /
AnnaBridge	165:d1b4690b3f8b	457	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	165:d1b4690b3f8b	458	#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U)) /!< PCLK1 clock used as I2C2 clock source /
AnnaBridge	165:d1b4690b3f8b	459	#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_0 >> RCC_CCIPR_I2C2SEL_Pos)) /!< SYSCLK clock used as I2C2 clock source /
AnnaBridge	165:d1b4690b3f8b	460	#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL_1 >> RCC_CCIPR_I2C2SEL_Pos)) /!< HSI clock used as I2C2 clock source /
AnnaBridge	165:d1b4690b3f8b	461	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	165:d1b4690b3f8b	462	#define LL_RCC_I2C3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U)) /!< PCLK1 clock used as I2C3 clock source /
AnnaBridge	165:d1b4690b3f8b	463	#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_0 >> RCC_CCIPR_I2C3SEL_Pos)) /!< SYSCLK clock used as I2C3 clock source /
AnnaBridge	165:d1b4690b3f8b	464	#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL_1 >> RCC_CCIPR_I2C3SEL_Pos)) /!< HSI clock used as I2C3 clock source /
AnnaBridge	165:d1b4690b3f8b	465	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	165:d1b4690b3f8b	466	#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U)) /!< PCLK1 clock used as I2C4 clock source /
AnnaBridge	165:d1b4690b3f8b	467	#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_0 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< SYSCLK clock used as I2C4 clock source /
AnnaBridge	165:d1b4690b3f8b	468	#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL_1 >> RCC_CCIPR2_I2C4SEL_Pos)) /!< HSI clock used as I2C4 clock source /
AnnaBridge	165:d1b4690b3f8b	469	#endif /* RCC_CCIPR2_I2C4SEL */
AnnaBridge	165:d1b4690b3f8b	470	/**
AnnaBridge	165:d1b4690b3f8b	471	* @}
AnnaBridge	165:d1b4690b3f8b	472	*/
AnnaBridge	165:d1b4690b3f8b	473
AnnaBridge	165:d1b4690b3f8b	474	/** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
AnnaBridge	165:d1b4690b3f8b	475	* @{
AnnaBridge	165:d1b4690b3f8b	476	*/
AnnaBridge	165:d1b4690b3f8b	477	#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM1SEL /!< PCLK1 clock used as LPTIM1 clock source /
AnnaBridge	165:d1b4690b3f8b	478	#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_0 >> 16U)) /!< LSI clock used as LPTIM1 clock source /
AnnaBridge	165:d1b4690b3f8b	479	#define LL_RCC_LPTIM1_CLKSOURCE_HSI (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL_1 >> 16U)) /!< HSI clock used as LPTIM1 clock source /
AnnaBridge	165:d1b4690b3f8b	480	#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIM1SEL \| (RCC_CCIPR_LPTIM1SEL >> 16U)) /!< LSE clock used as LPTIM1 clock source /
AnnaBridge	165:d1b4690b3f8b	481	#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 RCC_CCIPR_LPTIM2SEL /!< PCLK1 clock used as LPTIM2 clock source /
AnnaBridge	165:d1b4690b3f8b	482	#define LL_RCC_LPTIM2_CLKSOURCE_LSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_0 >> 16U)) /!< LSI clock used as LPTIM2 clock source /
AnnaBridge	165:d1b4690b3f8b	483	#define LL_RCC_LPTIM2_CLKSOURCE_HSI (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL_1 >> 16U)) /!< HSI clock used as LPTIM2 clock source /
AnnaBridge	165:d1b4690b3f8b	484	#define LL_RCC_LPTIM2_CLKSOURCE_LSE (RCC_CCIPR_LPTIM2SEL \| (RCC_CCIPR_LPTIM2SEL >> 16U)) /!< LSE clock used as LPTIM2 clock source /
AnnaBridge	165:d1b4690b3f8b	485	/**
AnnaBridge	165:d1b4690b3f8b	486	* @}
AnnaBridge	165:d1b4690b3f8b	487	*/
AnnaBridge	165:d1b4690b3f8b	488
AnnaBridge	165:d1b4690b3f8b	489	/** @defgroup RCC_LL_EC_SAI1_CLKSOURCE Peripheral SAI clock source selection
AnnaBridge	165:d1b4690b3f8b	490	* @{
AnnaBridge	165:d1b4690b3f8b	491	*/
AnnaBridge	165:d1b4690b3f8b	492	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	165:d1b4690b3f8b	493	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR2_SAI1SEL << 16U) /!< PLL clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	494	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_0) /!< PLLSAI1 clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	495	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_1) /!< PLLSAI2 clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	496	#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) \| RCC_CCIPR2_SAI1SEL_2) /!< HSI clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	497	#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) \| (RCC_CCIPR2_SAI1SEL_1 \| RCC_CCIPR2_SAI1SEL_0)) /!< External input clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	498	#else
AnnaBridge	165:d1b4690b3f8b	499	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI1SEL /!< PLLSAI1 clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	500	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	501	#define LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	502	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	503	#define LL_RCC_SAI1_CLKSOURCE_PLL (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL_1 >> 16U)) /!< PLL clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	504	#define LL_RCC_SAI1_CLKSOURCE_PIN (RCC_CCIPR_SAI1SEL \| (RCC_CCIPR_SAI1SEL >> 16U)) /!< External input clock used as SAI1 clock source /
AnnaBridge	165:d1b4690b3f8b	505	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	165:d1b4690b3f8b	506
AnnaBridge	165:d1b4690b3f8b	507	#if defined(RCC_CCIPR2_SAI2SEL)
AnnaBridge	165:d1b4690b3f8b	508	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR2_SAI2SEL << 16U) /!< PLL clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	509	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_0) /!< PLLSAI1 clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	510	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_1) /!< PLLSAI2 clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	511	#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) \| RCC_CCIPR2_SAI2SEL_2) /!< HSI clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	512	#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) \| (RCC_CCIPR2_SAI2SEL_1 \| RCC_CCIPR2_SAI2SEL_0)) /!< External input clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	513	#elif defined(RCC_CCIPR_SAI2SEL)
AnnaBridge	165:d1b4690b3f8b	514	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI1 RCC_CCIPR_SAI2SEL /!< PLLSAI1 clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	515	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	516	#define LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_0 >> 16U)) /!< PLLSAI2 clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	517	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	518	#define LL_RCC_SAI2_CLKSOURCE_PLL (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL_1 >> 16U)) /!< PLL clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	519	#define LL_RCC_SAI2_CLKSOURCE_PIN (RCC_CCIPR_SAI2SEL \| (RCC_CCIPR_SAI2SEL >> 16U)) /!< External input clock used as SAI2 clock source /
AnnaBridge	165:d1b4690b3f8b	520	#endif /* RCC_CCIPR2_SAI2SEL */
AnnaBridge	165:d1b4690b3f8b	521	/**
AnnaBridge	165:d1b4690b3f8b	522	* @}
AnnaBridge	165:d1b4690b3f8b	523	*/
AnnaBridge	165:d1b4690b3f8b	524
AnnaBridge	165:d1b4690b3f8b	525	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	165:d1b4690b3f8b	526	/** @defgroup RCC_LL_EC_SDMMC1_KERNELCLKSOURCE Peripheral SDMMC kernel clock source selection
AnnaBridge	165:d1b4690b3f8b	527	* @{
AnnaBridge	165:d1b4690b3f8b	528	*/
AnnaBridge	165:d1b4690b3f8b	529	#define LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK 0x00000000U /!< 48MHz clock from internal multiplexor used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	530	#define LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP RCC_CCIPR2_SDMMCSEL /!< PLLSAI3CLK clock used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	531	/**
AnnaBridge	165:d1b4690b3f8b	532	* @}
AnnaBridge	165:d1b4690b3f8b	533	*/
AnnaBridge	165:d1b4690b3f8b	534	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	165:d1b4690b3f8b	535
AnnaBridge	165:d1b4690b3f8b	536	/** @defgroup RCC_LL_EC_SDMMC1_CLKSOURCE Peripheral SDMMC clock source selection
AnnaBridge	165:d1b4690b3f8b	537	* @{
AnnaBridge	165:d1b4690b3f8b	538	*/
AnnaBridge	165:d1b4690b3f8b	539	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	540	#define LL_RCC_SDMMC1_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	541	#else
AnnaBridge	165:d1b4690b3f8b	542	#define LL_RCC_SDMMC1_CLKSOURCE_NONE 0x00000000U /!< No clock used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	543	#endif
AnnaBridge	165:d1b4690b3f8b	544	#define LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	545	#define LL_RCC_SDMMC1_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	546	#define LL_RCC_SDMMC1_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as SDMMC1 clock source /
AnnaBridge	165:d1b4690b3f8b	547	/**
AnnaBridge	165:d1b4690b3f8b	548	* @}
AnnaBridge	165:d1b4690b3f8b	549	*/
AnnaBridge	165:d1b4690b3f8b	550
AnnaBridge	165:d1b4690b3f8b	551	/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
AnnaBridge	165:d1b4690b3f8b	552	* @{
AnnaBridge	165:d1b4690b3f8b	553	*/
AnnaBridge	165:d1b4690b3f8b	554	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	555	#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as RNG clock source /
AnnaBridge	165:d1b4690b3f8b	556	#else
AnnaBridge	165:d1b4690b3f8b	557	#define LL_RCC_RNG_CLKSOURCE_NONE 0x00000000U /!< No clock used as RNG clock source /
AnnaBridge	165:d1b4690b3f8b	558	#endif
AnnaBridge	165:d1b4690b3f8b	559	#define LL_RCC_RNG_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as RNG clock source /
AnnaBridge	165:d1b4690b3f8b	560	#define LL_RCC_RNG_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as RNG clock source /
AnnaBridge	165:d1b4690b3f8b	561	#define LL_RCC_RNG_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as RNG clock source /
AnnaBridge	165:d1b4690b3f8b	562	/**
AnnaBridge	165:d1b4690b3f8b	563	* @}
AnnaBridge	165:d1b4690b3f8b	564	*/
AnnaBridge	165:d1b4690b3f8b	565
AnnaBridge	165:d1b4690b3f8b	566	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	165:d1b4690b3f8b	567	/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
AnnaBridge	165:d1b4690b3f8b	568	* @{
AnnaBridge	165:d1b4690b3f8b	569	*/
AnnaBridge	165:d1b4690b3f8b	570	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	571	#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /!< HSI48 clock used as USB clock source /
AnnaBridge	165:d1b4690b3f8b	572	#else
AnnaBridge	165:d1b4690b3f8b	573	#define LL_RCC_USB_CLKSOURCE_NONE 0x00000000U /!< No clock used as USB clock source /
AnnaBridge	165:d1b4690b3f8b	574	#endif
AnnaBridge	165:d1b4690b3f8b	575	#define LL_RCC_USB_CLKSOURCE_PLLSAI1 RCC_CCIPR_CLK48SEL_0 /!< PLLSAI1 clock used as USB clock source /
AnnaBridge	165:d1b4690b3f8b	576	#define LL_RCC_USB_CLKSOURCE_PLL RCC_CCIPR_CLK48SEL_1 /!< PLL clock used as USB clock source /
AnnaBridge	165:d1b4690b3f8b	577	#define LL_RCC_USB_CLKSOURCE_MSI RCC_CCIPR_CLK48SEL /!< MSI clock used as USB clock source /
AnnaBridge	165:d1b4690b3f8b	578	/**
AnnaBridge	165:d1b4690b3f8b	579	* @}
AnnaBridge	165:d1b4690b3f8b	580	*/
AnnaBridge	165:d1b4690b3f8b	581
AnnaBridge	165:d1b4690b3f8b	582	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	165:d1b4690b3f8b	583
AnnaBridge	165:d1b4690b3f8b	584	/** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
AnnaBridge	165:d1b4690b3f8b	585	* @{
AnnaBridge	165:d1b4690b3f8b	586	*/
AnnaBridge	165:d1b4690b3f8b	587	#define LL_RCC_ADC_CLKSOURCE_NONE 0x00000000U /!< No clock used as ADC clock source /
AnnaBridge	165:d1b4690b3f8b	588	#define LL_RCC_ADC_CLKSOURCE_PLLSAI1 RCC_CCIPR_ADCSEL_0 /!< PLLSAI1 clock used as ADC clock source /
AnnaBridge	165:d1b4690b3f8b	589	#if defined(RCC_PLLSAI2_SUPPORT) && !defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	590	#define LL_RCC_ADC_CLKSOURCE_PLLSAI2 RCC_CCIPR_ADCSEL_1 /!< PLLSAI2 clock used as ADC clock source /
AnnaBridge	165:d1b4690b3f8b	591	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	592	#define LL_RCC_ADC_CLKSOURCE_SYSCLK RCC_CCIPR_ADCSEL /!< SYSCLK clock used as ADC clock source /
AnnaBridge	165:d1b4690b3f8b	593	/**
AnnaBridge	165:d1b4690b3f8b	594	* @}
AnnaBridge	165:d1b4690b3f8b	595	*/
AnnaBridge	165:d1b4690b3f8b	596
AnnaBridge	165:d1b4690b3f8b	597	#if defined(SWPMI1)
AnnaBridge	165:d1b4690b3f8b	598	/** @defgroup RCC_LL_EC_SWPMI1_CLKSOURCE Peripheral SWPMI1 clock source selection
AnnaBridge	165:d1b4690b3f8b	599	* @{
AnnaBridge	165:d1b4690b3f8b	600	*/
AnnaBridge	165:d1b4690b3f8b	601	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK1 0x00000000U /!< PCLK1 used as SWPMI1 clock source /
AnnaBridge	165:d1b4690b3f8b	602	#define LL_RCC_SWPMI1_CLKSOURCE_HSI RCC_CCIPR_SWPMI1SEL /!< HSI used as SWPMI1 clock source /
AnnaBridge	165:d1b4690b3f8b	603	/**
AnnaBridge	165:d1b4690b3f8b	604	* @}
AnnaBridge	165:d1b4690b3f8b	605	*/
AnnaBridge	165:d1b4690b3f8b	606	#endif /* SWPMI1 */
AnnaBridge	165:d1b4690b3f8b	607
AnnaBridge	165:d1b4690b3f8b	608	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	609	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	610	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM1 Audio clock source selection
AnnaBridge	165:d1b4690b3f8b	611	* @{
AnnaBridge	165:d1b4690b3f8b	612	*/
AnnaBridge	165:d1b4690b3f8b	613	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /!< SAI1 clock used as DFSDM1 Audio clock /
AnnaBridge	165:d1b4690b3f8b	614	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI RCC_CCIPR2_ADFSDM1SEL_0 /!< HSI clock used as DFSDM1 Audio clock /
AnnaBridge	165:d1b4690b3f8b	615	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI RCC_CCIPR2_ADFSDM1SEL_1 /!< MSI clock used as DFSDM1 Audio clock /
AnnaBridge	165:d1b4690b3f8b	616	/**
AnnaBridge	165:d1b4690b3f8b	617	* @}
AnnaBridge	165:d1b4690b3f8b	618	*/
AnnaBridge	165:d1b4690b3f8b	619	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	620
AnnaBridge	165:d1b4690b3f8b	621	/** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM1 clock source selection
AnnaBridge	165:d1b4690b3f8b	622	* @{
AnnaBridge	165:d1b4690b3f8b	623	*/
AnnaBridge	165:d1b4690b3f8b	624	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	625	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	165:d1b4690b3f8b	626	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR2_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
AnnaBridge	165:d1b4690b3f8b	627	#else
AnnaBridge	165:d1b4690b3f8b	628	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /!< PCLK2 used as DFSDM1 clock source /
AnnaBridge	165:d1b4690b3f8b	629	#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_CCIPR_DFSDM1SEL /!< SYSCLK used as DFSDM1 clock source /
AnnaBridge	165:d1b4690b3f8b	630	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	631	/**
AnnaBridge	165:d1b4690b3f8b	632	* @}
AnnaBridge	165:d1b4690b3f8b	633	*/
AnnaBridge	165:d1b4690b3f8b	634	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	635
AnnaBridge	165:d1b4690b3f8b	636	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	637	/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
AnnaBridge	165:d1b4690b3f8b	638	* @{
AnnaBridge	165:d1b4690b3f8b	639	*/
AnnaBridge	165:d1b4690b3f8b	640	#define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /!< DSI-PHY clock used as DSI byte lane clock source /
AnnaBridge	165:d1b4690b3f8b	641	#define LL_RCC_DSI_CLKSOURCE_PLL RCC_CCIPR2_DSISEL /!< PLL clock used as DSI byte lane clock source /
AnnaBridge	165:d1b4690b3f8b	642	/**
AnnaBridge	165:d1b4690b3f8b	643	* @}
AnnaBridge	165:d1b4690b3f8b	644	*/
AnnaBridge	165:d1b4690b3f8b	645	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	646
AnnaBridge	165:d1b4690b3f8b	647	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	648	/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection
AnnaBridge	165:d1b4690b3f8b	649	* @{
AnnaBridge	165:d1b4690b3f8b	650	*/
AnnaBridge	165:d1b4690b3f8b	651	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2 0x00000000U /!< PLLSAI2DIVR divided by 2 used as LTDC clock source /
AnnaBridge	165:d1b4690b3f8b	652	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4 RCC_CCIPR2_PLLSAI2DIVR_0 /!< PLLSAI2DIVR divided by 4 used as LTDC clock source /
AnnaBridge	165:d1b4690b3f8b	653	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8 RCC_CCIPR2_PLLSAI2DIVR_1 /!< PLLSAI2DIVR divided by 8 used as LTDC clock source /
AnnaBridge	165:d1b4690b3f8b	654	#define LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16 RCC_CCIPR2_PLLSAI2DIVR /!< PLLSAI2DIVR divided by 16 used as LTDC clock source /
AnnaBridge	165:d1b4690b3f8b	655	/**
AnnaBridge	165:d1b4690b3f8b	656	* @}
AnnaBridge	165:d1b4690b3f8b	657	*/
AnnaBridge	165:d1b4690b3f8b	658	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	659
AnnaBridge	165:d1b4690b3f8b	660	#if defined(OCTOSPI1)
AnnaBridge	165:d1b4690b3f8b	661	/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
AnnaBridge	165:d1b4690b3f8b	662	* @{
AnnaBridge	165:d1b4690b3f8b	663	*/
AnnaBridge	165:d1b4690b3f8b	664	#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /!< SYSCLK used as OctoSPI clock source /
AnnaBridge	165:d1b4690b3f8b	665	#define LL_RCC_OCTOSPI_CLKSOURCE_MSI RCC_CCIPR2_OSPISEL_0 /!< MSI used as OctoSPI clock source /
AnnaBridge	165:d1b4690b3f8b	666	#define LL_RCC_OCTOSPI_CLKSOURCE_PLL RCC_CCIPR2_OSPISEL_1 /!< PLL used as OctoSPI clock source /
AnnaBridge	165:d1b4690b3f8b	667	/**
AnnaBridge	165:d1b4690b3f8b	668	* @}
AnnaBridge	165:d1b4690b3f8b	669	*/
AnnaBridge	165:d1b4690b3f8b	670	#endif /* OCTOSPI1 */
AnnaBridge	165:d1b4690b3f8b	671
AnnaBridge	165:d1b4690b3f8b	672	/** @defgroup RCC_LL_EC_USART1 Peripheral USART get clock source
AnnaBridge	165:d1b4690b3f8b	673	* @{
AnnaBridge	165:d1b4690b3f8b	674	*/
AnnaBridge	165:d1b4690b3f8b	675	#define LL_RCC_USART1_CLKSOURCE RCC_CCIPR_USART1SEL /!< USART1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	676	#define LL_RCC_USART2_CLKSOURCE RCC_CCIPR_USART2SEL /!< USART2 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	677	#if defined(RCC_CCIPR_USART3SEL)
AnnaBridge	165:d1b4690b3f8b	678	#define LL_RCC_USART3_CLKSOURCE RCC_CCIPR_USART3SEL /!< USART3 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	679	#endif /* RCC_CCIPR_USART3SEL */
AnnaBridge	165:d1b4690b3f8b	680	/**
AnnaBridge	165:d1b4690b3f8b	681	* @}
AnnaBridge	165:d1b4690b3f8b	682	*/
AnnaBridge	165:d1b4690b3f8b	683
AnnaBridge	165:d1b4690b3f8b	684	#if defined(RCC_CCIPR_UART4SEL) \|\| defined(RCC_CCIPR_UART5SEL)
AnnaBridge	165:d1b4690b3f8b	685	/** @defgroup RCC_LL_EC_UART4 Peripheral UART get clock source
AnnaBridge	165:d1b4690b3f8b	686	* @{
AnnaBridge	165:d1b4690b3f8b	687	*/
AnnaBridge	165:d1b4690b3f8b	688	#if defined(RCC_CCIPR_UART4SEL)
AnnaBridge	165:d1b4690b3f8b	689	#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR_UART4SEL /!< UART4 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	690	#endif /* RCC_CCIPR_UART4SEL */
AnnaBridge	165:d1b4690b3f8b	691	#if defined(RCC_CCIPR_UART5SEL)
AnnaBridge	165:d1b4690b3f8b	692	#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR_UART5SEL /!< UART5 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	693	#endif /* RCC_CCIPR_UART5SEL */
AnnaBridge	165:d1b4690b3f8b	694	/**
AnnaBridge	165:d1b4690b3f8b	695	* @}
AnnaBridge	165:d1b4690b3f8b	696	*/
AnnaBridge	165:d1b4690b3f8b	697	#endif /* RCC_CCIPR_UART4SEL \|\| RCC_CCIPR_UART5SEL */
AnnaBridge	165:d1b4690b3f8b	698
AnnaBridge	165:d1b4690b3f8b	699	/** @defgroup RCC_LL_EC_LPUART1 Peripheral LPUART get clock source
AnnaBridge	165:d1b4690b3f8b	700	* @{
AnnaBridge	165:d1b4690b3f8b	701	*/
AnnaBridge	165:d1b4690b3f8b	702	#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR_LPUART1SEL /!< LPUART1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	703	/**
AnnaBridge	165:d1b4690b3f8b	704	* @}
AnnaBridge	165:d1b4690b3f8b	705	*/
AnnaBridge	165:d1b4690b3f8b	706
AnnaBridge	165:d1b4690b3f8b	707	/** @defgroup RCC_LL_EC_I2C1 Peripheral I2C get clock source
AnnaBridge	165:d1b4690b3f8b	708	* @{
AnnaBridge	165:d1b4690b3f8b	709	*/
AnnaBridge	165:d1b4690b3f8b	710	#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C1SEL_Pos << 16U) \| (RCC_CCIPR_I2C1SEL >> RCC_CCIPR_I2C1SEL_Pos)) /!< I2C1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	711	#if defined(RCC_CCIPR_I2C2SEL)
AnnaBridge	165:d1b4690b3f8b	712	#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C2SEL_Pos << 16U) \| (RCC_CCIPR_I2C2SEL >> RCC_CCIPR_I2C2SEL_Pos)) /!< I2C2 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	713	#endif /* RCC_CCIPR_I2C2SEL */
AnnaBridge	165:d1b4690b3f8b	714	#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR << 24U) \| (RCC_CCIPR_I2C3SEL_Pos << 16U) \| (RCC_CCIPR_I2C3SEL >> RCC_CCIPR_I2C3SEL_Pos)) /!< I2C3 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	715	#if defined(RCC_CCIPR2_I2C4SEL)
AnnaBridge	165:d1b4690b3f8b	716	#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) \| (RCC_CCIPR2_I2C4SEL_Pos << 16U) \| (RCC_CCIPR2_I2C4SEL >> RCC_CCIPR2_I2C4SEL_Pos)) /!< I2C4 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	717	#endif /* RCC_CCIPR2_I2C4SEL */
AnnaBridge	165:d1b4690b3f8b	718	/**
AnnaBridge	165:d1b4690b3f8b	719	* @}
AnnaBridge	165:d1b4690b3f8b	720	*/
AnnaBridge	165:d1b4690b3f8b	721
AnnaBridge	165:d1b4690b3f8b	722	/** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
AnnaBridge	165:d1b4690b3f8b	723	* @{
AnnaBridge	165:d1b4690b3f8b	724	*/
AnnaBridge	165:d1b4690b3f8b	725	#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIM1SEL /!< LPTIM1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	726	#define LL_RCC_LPTIM2_CLKSOURCE RCC_CCIPR_LPTIM2SEL /!< LPTIM2 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	727	/**
AnnaBridge	165:d1b4690b3f8b	728	* @}
AnnaBridge	165:d1b4690b3f8b	729	*/
AnnaBridge	165:d1b4690b3f8b	730
AnnaBridge	165:d1b4690b3f8b	731	/** @defgroup RCC_LL_EC_SAI1 Peripheral SAI get clock source
AnnaBridge	165:d1b4690b3f8b	732	* @{
AnnaBridge	165:d1b4690b3f8b	733	*/
AnnaBridge	165:d1b4690b3f8b	734	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	165:d1b4690b3f8b	735	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	736	#else
AnnaBridge	165:d1b4690b3f8b	737	#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR_SAI1SEL /!< SAI1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	738	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	165:d1b4690b3f8b	739	#if defined(RCC_CCIPR2_SAI2SEL)
AnnaBridge	165:d1b4690b3f8b	740	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	741	#elif defined(RCC_CCIPR_SAI2SEL)
AnnaBridge	165:d1b4690b3f8b	742	#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR_SAI2SEL /!< SAI2 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	743	#endif /* RCC_CCIPR2_SAI2SEL */
AnnaBridge	165:d1b4690b3f8b	744	/**
AnnaBridge	165:d1b4690b3f8b	745	* @}
AnnaBridge	165:d1b4690b3f8b	746	*/
AnnaBridge	165:d1b4690b3f8b	747
AnnaBridge	165:d1b4690b3f8b	748	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	165:d1b4690b3f8b	749	/** @defgroup RCC_LL_EC_SDMMC1_KERNEL Peripheral SDMMC get kernel clock source
AnnaBridge	165:d1b4690b3f8b	750	* @{
AnnaBridge	165:d1b4690b3f8b	751	*/
AnnaBridge	165:d1b4690b3f8b	752	#define LL_RCC_SDMMC1_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /!< SDMMC1 Kernel Clock source selection /
AnnaBridge	165:d1b4690b3f8b	753	/**
AnnaBridge	165:d1b4690b3f8b	754	* @}
AnnaBridge	165:d1b4690b3f8b	755	*/
AnnaBridge	165:d1b4690b3f8b	756	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	165:d1b4690b3f8b	757
AnnaBridge	165:d1b4690b3f8b	758	/** @defgroup RCC_LL_EC_SDMMC1 Peripheral SDMMC get clock source
AnnaBridge	165:d1b4690b3f8b	759	* @{
AnnaBridge	165:d1b4690b3f8b	760	*/
AnnaBridge	165:d1b4690b3f8b	761	#define LL_RCC_SDMMC1_CLKSOURCE RCC_CCIPR_CLK48SEL /!< SDMMC1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	762	/**
AnnaBridge	165:d1b4690b3f8b	763	* @}
AnnaBridge	165:d1b4690b3f8b	764	*/
AnnaBridge	165:d1b4690b3f8b	765
AnnaBridge	165:d1b4690b3f8b	766	/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
AnnaBridge	165:d1b4690b3f8b	767	* @{
AnnaBridge	165:d1b4690b3f8b	768	*/
AnnaBridge	165:d1b4690b3f8b	769	#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR_CLK48SEL /!< RNG Clock source selection /
AnnaBridge	165:d1b4690b3f8b	770	/**
AnnaBridge	165:d1b4690b3f8b	771	* @}
AnnaBridge	165:d1b4690b3f8b	772	*/
AnnaBridge	165:d1b4690b3f8b	773
AnnaBridge	165:d1b4690b3f8b	774	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	165:d1b4690b3f8b	775	/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
AnnaBridge	165:d1b4690b3f8b	776	* @{
AnnaBridge	165:d1b4690b3f8b	777	*/
AnnaBridge	165:d1b4690b3f8b	778	#define LL_RCC_USB_CLKSOURCE RCC_CCIPR_CLK48SEL /!< USB Clock source selection /
AnnaBridge	165:d1b4690b3f8b	779	/**
AnnaBridge	165:d1b4690b3f8b	780	* @}
AnnaBridge	165:d1b4690b3f8b	781	*/
AnnaBridge	165:d1b4690b3f8b	782	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	165:d1b4690b3f8b	783
AnnaBridge	165:d1b4690b3f8b	784	/** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
AnnaBridge	165:d1b4690b3f8b	785	* @{
AnnaBridge	165:d1b4690b3f8b	786	*/
AnnaBridge	165:d1b4690b3f8b	787	#define LL_RCC_ADC_CLKSOURCE RCC_CCIPR_ADCSEL /!< ADC Clock source selection /
AnnaBridge	165:d1b4690b3f8b	788	/**
AnnaBridge	165:d1b4690b3f8b	789	* @}
AnnaBridge	165:d1b4690b3f8b	790	*/
AnnaBridge	165:d1b4690b3f8b	791
AnnaBridge	165:d1b4690b3f8b	792	#if defined(SWPMI1)
AnnaBridge	165:d1b4690b3f8b	793	/** @defgroup RCC_LL_EC_SWPMI1 Peripheral SWPMI1 get clock source
AnnaBridge	165:d1b4690b3f8b	794	* @{
AnnaBridge	165:d1b4690b3f8b	795	*/
AnnaBridge	165:d1b4690b3f8b	796	#define LL_RCC_SWPMI1_CLKSOURCE RCC_CCIPR_SWPMI1SEL /!< SWPMI1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	797	/**
AnnaBridge	165:d1b4690b3f8b	798	* @}
AnnaBridge	165:d1b4690b3f8b	799	*/
AnnaBridge	165:d1b4690b3f8b	800	#endif /* SWPMI1 */
AnnaBridge	165:d1b4690b3f8b	801
AnnaBridge	165:d1b4690b3f8b	802	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	803	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	804	/** @defgroup RCC_LL_EC_DFSDM1_AUDIO Peripheral DFSDM1 Audio get clock source
AnnaBridge	165:d1b4690b3f8b	805	* @{
AnnaBridge	165:d1b4690b3f8b	806	*/
AnnaBridge	165:d1b4690b3f8b	807	#define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_CCIPR2_ADFSDM1SEL /* DFSDM1 Audio Clock source selection */
AnnaBridge	165:d1b4690b3f8b	808	/**
AnnaBridge	165:d1b4690b3f8b	809	* @}
AnnaBridge	165:d1b4690b3f8b	810	*/
AnnaBridge	165:d1b4690b3f8b	811
AnnaBridge	165:d1b4690b3f8b	812	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	813	/** @defgroup RCC_LL_EC_DFSDM1 Peripheral DFSDM1 get clock source
AnnaBridge	165:d1b4690b3f8b	814	* @{
AnnaBridge	165:d1b4690b3f8b	815	*/
AnnaBridge	165:d1b4690b3f8b	816	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	817	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR2_DFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	818	#else
AnnaBridge	165:d1b4690b3f8b	819	#define LL_RCC_DFSDM1_CLKSOURCE RCC_CCIPR_DFSDM1SEL /!< DFSDM1 Clock source selection /
AnnaBridge	165:d1b4690b3f8b	820	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	821	/**
AnnaBridge	165:d1b4690b3f8b	822	* @}
AnnaBridge	165:d1b4690b3f8b	823	*/
AnnaBridge	165:d1b4690b3f8b	824	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	825
AnnaBridge	165:d1b4690b3f8b	826	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	827	/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
AnnaBridge	165:d1b4690b3f8b	828	* @{
AnnaBridge	165:d1b4690b3f8b	829	*/
AnnaBridge	165:d1b4690b3f8b	830	#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSISEL /!< DSI Clock source selection /
AnnaBridge	165:d1b4690b3f8b	831	/**
AnnaBridge	165:d1b4690b3f8b	832	* @}
AnnaBridge	165:d1b4690b3f8b	833	*/
AnnaBridge	165:d1b4690b3f8b	834	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	835
AnnaBridge	165:d1b4690b3f8b	836	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	837	/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
AnnaBridge	165:d1b4690b3f8b	838	* @{
AnnaBridge	165:d1b4690b3f8b	839	*/
AnnaBridge	165:d1b4690b3f8b	840	#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_PLLSAI2DIVR /!< LTDC Clock source selection /
AnnaBridge	165:d1b4690b3f8b	841	/**
AnnaBridge	165:d1b4690b3f8b	842	* @}
AnnaBridge	165:d1b4690b3f8b	843	*/
AnnaBridge	165:d1b4690b3f8b	844	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	845
AnnaBridge	165:d1b4690b3f8b	846	#if defined(OCTOSPI1)
AnnaBridge	165:d1b4690b3f8b	847	/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source
AnnaBridge	165:d1b4690b3f8b	848	* @{
AnnaBridge	165:d1b4690b3f8b	849	*/
AnnaBridge	165:d1b4690b3f8b	850	#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OSPISEL /!< OctoSPI Clock source selection /
AnnaBridge	165:d1b4690b3f8b	851	/**
AnnaBridge	165:d1b4690b3f8b	852	* @}
AnnaBridge	165:d1b4690b3f8b	853	*/
AnnaBridge	165:d1b4690b3f8b	854	#endif /* OCTOSPI1 */
AnnaBridge	165:d1b4690b3f8b	855
AnnaBridge	165:d1b4690b3f8b	856
AnnaBridge	165:d1b4690b3f8b	857	/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
AnnaBridge	165:d1b4690b3f8b	858	* @{
AnnaBridge	165:d1b4690b3f8b	859	*/
AnnaBridge	165:d1b4690b3f8b	860	#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /!< No clock used as RTC clock /
AnnaBridge	165:d1b4690b3f8b	861	#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /!< LSE oscillator clock used as RTC clock /
AnnaBridge	165:d1b4690b3f8b	862	#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /!< LSI oscillator clock used as RTC clock /
AnnaBridge	165:d1b4690b3f8b	863	#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /!< HSE oscillator clock divided by 32 used as RTC clock /
AnnaBridge	165:d1b4690b3f8b	864	/**
AnnaBridge	165:d1b4690b3f8b	865	* @}
AnnaBridge	165:d1b4690b3f8b	866	*/
AnnaBridge	165:d1b4690b3f8b	867
AnnaBridge	165:d1b4690b3f8b	868
AnnaBridge	165:d1b4690b3f8b	869	/** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLSAI1 and PLLSAI2 entry clock source
AnnaBridge	165:d1b4690b3f8b	870	* @{
AnnaBridge	165:d1b4690b3f8b	871	*/
AnnaBridge	165:d1b4690b3f8b	872	#define LL_RCC_PLLSOURCE_NONE 0x00000000U /!< No clock /
AnnaBridge	165:d1b4690b3f8b	873	#define LL_RCC_PLLSOURCE_MSI RCC_PLLCFGR_PLLSRC_MSI /!< MSI clock selected as PLL entry clock source /
AnnaBridge	165:d1b4690b3f8b	874	#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /!< HSI16 clock selected as PLL entry clock source /
AnnaBridge	165:d1b4690b3f8b	875	#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /!< HSE clock selected as PLL entry clock source /
AnnaBridge	165:d1b4690b3f8b	876	/**
AnnaBridge	165:d1b4690b3f8b	877	* @}
AnnaBridge	165:d1b4690b3f8b	878	*/
AnnaBridge	165:d1b4690b3f8b	879
AnnaBridge	165:d1b4690b3f8b	880	/** @defgroup RCC_LL_EC_PLLM_DIV PLL division factor
AnnaBridge	165:d1b4690b3f8b	881	* @{
AnnaBridge	165:d1b4690b3f8b	882	*/
AnnaBridge	165:d1b4690b3f8b	883	#define LL_RCC_PLLM_DIV_1 0x00000000U /!< Main PLL division factor for PLLM input by 1 /
AnnaBridge	165:d1b4690b3f8b	884	#define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 2 /
AnnaBridge	165:d1b4690b3f8b	885	#define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 3 /
AnnaBridge	165:d1b4690b3f8b	886	#define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 4 /
AnnaBridge	165:d1b4690b3f8b	887	#define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2) /!< Main PLL division factor for PLLM input by 5 /
AnnaBridge	165:d1b4690b3f8b	888	#define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 6 /
AnnaBridge	165:d1b4690b3f8b	889	#define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 7 /
AnnaBridge	165:d1b4690b3f8b	890	#define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 8 /
AnnaBridge	165:d1b4690b3f8b	891	#if defined(RCC_PLLM_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	892	#define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3) /!< Main PLL division factor for PLLM input by 9 /
AnnaBridge	165:d1b4690b3f8b	893	#define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 10 /
AnnaBridge	165:d1b4690b3f8b	894	#define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 11 /
AnnaBridge	165:d1b4690b3f8b	895	#define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 12 /
AnnaBridge	165:d1b4690b3f8b	896	#define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2) /!< Main PLL division factor for PLLM input by 13 /
AnnaBridge	165:d1b4690b3f8b	897	#define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 14 /
AnnaBridge	165:d1b4690b3f8b	898	#define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1) /!< Main PLL division factor for PLLM input by 15 /
AnnaBridge	165:d1b4690b3f8b	899	#define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_3 \| RCC_PLLCFGR_PLLM_2 \| RCC_PLLCFGR_PLLM_1 \| RCC_PLLCFGR_PLLM_0) /!< Main PLL division factor for PLLM input by 16 /
AnnaBridge	165:d1b4690b3f8b	900	#endif /* RCC_PLLM_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	901	/**
AnnaBridge	165:d1b4690b3f8b	902	* @}
AnnaBridge	165:d1b4690b3f8b	903	*/
AnnaBridge	165:d1b4690b3f8b	904
AnnaBridge	165:d1b4690b3f8b	905	/** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
AnnaBridge	165:d1b4690b3f8b	906	* @{
AnnaBridge	165:d1b4690b3f8b	907	*/
AnnaBridge	165:d1b4690b3f8b	908	#define LL_RCC_PLLR_DIV_2 0x00000000U /!< Main PLL division factor for PLLCLK (system clock) by 2 /
AnnaBridge	165:d1b4690b3f8b	909	#define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_0) /!< Main PLL division factor for PLLCLK (system clock) by 4 /
AnnaBridge	165:d1b4690b3f8b	910	#define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_1) /!< Main PLL division factor for PLLCLK (system clock) by 6 /
AnnaBridge	165:d1b4690b3f8b	911	#define LL_RCC_PLLR_DIV_8 (RCC_PLLCFGR_PLLR) /!< Main PLL division factor for PLLCLK (system clock) by 8 /
AnnaBridge	165:d1b4690b3f8b	912	/**
AnnaBridge	165:d1b4690b3f8b	913	* @}
AnnaBridge	165:d1b4690b3f8b	914	*/
AnnaBridge	165:d1b4690b3f8b	915
AnnaBridge	165:d1b4690b3f8b	916	/** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
AnnaBridge	165:d1b4690b3f8b	917	* @{
AnnaBridge	165:d1b4690b3f8b	918	*/
AnnaBridge	165:d1b4690b3f8b	919	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	920	#define LL_RCC_PLLP_DIV_2 (RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 2 /
AnnaBridge	165:d1b4690b3f8b	921	#define LL_RCC_PLLP_DIV_3 (RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 3 /
AnnaBridge	165:d1b4690b3f8b	922	#define LL_RCC_PLLP_DIV_4 (RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 4 /
AnnaBridge	165:d1b4690b3f8b	923	#define LL_RCC_PLLP_DIV_5 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 5 /
AnnaBridge	165:d1b4690b3f8b	924	#define LL_RCC_PLLP_DIV_6 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 6 /
AnnaBridge	165:d1b4690b3f8b	925	#define LL_RCC_PLLP_DIV_7 (RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 7 /
AnnaBridge	165:d1b4690b3f8b	926	#define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 8 /
AnnaBridge	165:d1b4690b3f8b	927	#define LL_RCC_PLLP_DIV_9 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 9 /
AnnaBridge	165:d1b4690b3f8b	928	#define LL_RCC_PLLP_DIV_10 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 10 /
AnnaBridge	165:d1b4690b3f8b	929	#define LL_RCC_PLLP_DIV_11 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 11 /
AnnaBridge	165:d1b4690b3f8b	930	#define LL_RCC_PLLP_DIV_12 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 12 /
AnnaBridge	165:d1b4690b3f8b	931	#define LL_RCC_PLLP_DIV_13 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 13 /
AnnaBridge	165:d1b4690b3f8b	932	#define LL_RCC_PLLP_DIV_14 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 14 /
AnnaBridge	165:d1b4690b3f8b	933	#define LL_RCC_PLLP_DIV_15 (RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 15 /
AnnaBridge	165:d1b4690b3f8b	934	#define LL_RCC_PLLP_DIV_16 (RCC_PLLCFGR_PLLPDIV_4) /!< Main PLL division factor for PLLP output by 16 /
AnnaBridge	165:d1b4690b3f8b	935	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 17 /
AnnaBridge	165:d1b4690b3f8b	936	#define LL_RCC_PLLP_DIV_18 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 18 /
AnnaBridge	165:d1b4690b3f8b	937	#define LL_RCC_PLLP_DIV_19 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 19 /
AnnaBridge	165:d1b4690b3f8b	938	#define LL_RCC_PLLP_DIV_20 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 20 /
AnnaBridge	165:d1b4690b3f8b	939	#define LL_RCC_PLLP_DIV_21 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 21 /
AnnaBridge	165:d1b4690b3f8b	940	#define LL_RCC_PLLP_DIV_22 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 22 /
AnnaBridge	165:d1b4690b3f8b	941	#define LL_RCC_PLLP_DIV_23 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 23 /
AnnaBridge	165:d1b4690b3f8b	942	#define LL_RCC_PLLP_DIV_24 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3) /!< Main PLL division factor for PLLP output by 24 /
AnnaBridge	165:d1b4690b3f8b	943	#define LL_RCC_PLLP_DIV_25 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 25 /
AnnaBridge	165:d1b4690b3f8b	944	#define LL_RCC_PLLP_DIV_26 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 26 /
AnnaBridge	165:d1b4690b3f8b	945	#define LL_RCC_PLLP_DIV_27 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 27 /
AnnaBridge	165:d1b4690b3f8b	946	#define LL_RCC_PLLP_DIV_28 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2) /!< Main PLL division factor for PLLP output by 28 /
AnnaBridge	165:d1b4690b3f8b	947	#define LL_RCC_PLLP_DIV_29 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 29 /
AnnaBridge	165:d1b4690b3f8b	948	#define LL_RCC_PLLP_DIV_30 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1) /!< Main PLL division factor for PLLP output by 30 /
AnnaBridge	165:d1b4690b3f8b	949	#define LL_RCC_PLLP_DIV_31 (RCC_PLLCFGR_PLLPDIV_4\|RCC_PLLCFGR_PLLPDIV_3\|RCC_PLLCFGR_PLLPDIV_2\|RCC_PLLCFGR_PLLPDIV_1\|RCC_PLLCFGR_PLLPDIV_0) /!< Main PLL division factor for PLLP output by 31 /
AnnaBridge	165:d1b4690b3f8b	950	#else
AnnaBridge	165:d1b4690b3f8b	951	#define LL_RCC_PLLP_DIV_7 0x00000000U /!< Main PLL division factor for PLLP output by 7 /
AnnaBridge	165:d1b4690b3f8b	952	#define LL_RCC_PLLP_DIV_17 (RCC_PLLCFGR_PLLP) /!< Main PLL division factor for PLLP output by 17 /
AnnaBridge	165:d1b4690b3f8b	953	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	954	/**
AnnaBridge	165:d1b4690b3f8b	955	* @}
AnnaBridge	165:d1b4690b3f8b	956	*/
AnnaBridge	165:d1b4690b3f8b	957
AnnaBridge	165:d1b4690b3f8b	958	/** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
AnnaBridge	165:d1b4690b3f8b	959	* @{
AnnaBridge	165:d1b4690b3f8b	960	*/
AnnaBridge	165:d1b4690b3f8b	961	#define LL_RCC_PLLQ_DIV_2 0x00000000U /!< Main PLL division factor for PLLQ output by 2 /
AnnaBridge	165:d1b4690b3f8b	962	#define LL_RCC_PLLQ_DIV_4 (RCC_PLLCFGR_PLLQ_0) /!< Main PLL division factor for PLLQ output by 4 /
AnnaBridge	165:d1b4690b3f8b	963	#define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_1) /!< Main PLL division factor for PLLQ output by 6 /
AnnaBridge	165:d1b4690b3f8b	964	#define LL_RCC_PLLQ_DIV_8 (RCC_PLLCFGR_PLLQ) /!< Main PLL division factor for PLLQ output by 8 /
AnnaBridge	165:d1b4690b3f8b	965	/**
AnnaBridge	165:d1b4690b3f8b	966	* @}
AnnaBridge	165:d1b4690b3f8b	967	*/
AnnaBridge	165:d1b4690b3f8b	968
AnnaBridge	165:d1b4690b3f8b	969	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	970	/** @defgroup RCC_LL_EC_PLLSAI1M PLLSAI1 division factor (PLLSAI1M)
AnnaBridge	165:d1b4690b3f8b	971	* @{
AnnaBridge	165:d1b4690b3f8b	972	*/
AnnaBridge	165:d1b4690b3f8b	973	#define LL_RCC_PLLSAI1M_DIV_1 0x00000000U /!< PLLSAI1 division factor for PLLSAI1M input by 1 /
AnnaBridge	165:d1b4690b3f8b	974	#define LL_RCC_PLLSAI1M_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 2 /
AnnaBridge	165:d1b4690b3f8b	975	#define LL_RCC_PLLSAI1M_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 3 /
AnnaBridge	165:d1b4690b3f8b	976	#define LL_RCC_PLLSAI1M_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 4 /
AnnaBridge	165:d1b4690b3f8b	977	#define LL_RCC_PLLSAI1M_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1M_2) /!< PLLSAI1 division factor for PLLSAI1M input by 5 /
AnnaBridge	165:d1b4690b3f8b	978	#define LL_RCC_PLLSAI1M_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 6 /
AnnaBridge	165:d1b4690b3f8b	979	#define LL_RCC_PLLSAI1M_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 7 /
AnnaBridge	165:d1b4690b3f8b	980	#define LL_RCC_PLLSAI1M_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 8 /
AnnaBridge	165:d1b4690b3f8b	981	#define LL_RCC_PLLSAI1M_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1M_3) /!< PLLSAI1 division factor for PLLSAI1M input by 9 /
AnnaBridge	165:d1b4690b3f8b	982	#define LL_RCC_PLLSAI1M_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 10 /
AnnaBridge	165:d1b4690b3f8b	983	#define LL_RCC_PLLSAI1M_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 11 /
AnnaBridge	165:d1b4690b3f8b	984	#define LL_RCC_PLLSAI1M_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 12 /
AnnaBridge	165:d1b4690b3f8b	985	#define LL_RCC_PLLSAI1M_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2) /!< PLLSAI1 division factor for PLLSAI1M input by 13 /
AnnaBridge	165:d1b4690b3f8b	986	#define LL_RCC_PLLSAI1M_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 14 /
AnnaBridge	165:d1b4690b3f8b	987	#define LL_RCC_PLLSAI1M_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1) /!< PLLSAI1 division factor for PLLSAI1M input by 15 /
AnnaBridge	165:d1b4690b3f8b	988	#define LL_RCC_PLLSAI1M_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1M_3\|RCC_PLLSAI1CFGR_PLLSAI1M_2\|RCC_PLLSAI1CFGR_PLLSAI1M_1\|RCC_PLLSAI1CFGR_PLLSAI1M_0) /!< PLLSAI1 division factor for PLLSAI1M input by 16 /
AnnaBridge	165:d1b4690b3f8b	989	/**
AnnaBridge	165:d1b4690b3f8b	990	* @}
AnnaBridge	165:d1b4690b3f8b	991	*/
AnnaBridge	165:d1b4690b3f8b	992	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	993
AnnaBridge	165:d1b4690b3f8b	994	/** @defgroup RCC_LL_EC_PLLSAI1Q PLLSAI1 division factor (PLLSAI1Q)
AnnaBridge	165:d1b4690b3f8b	995	* @{
AnnaBridge	165:d1b4690b3f8b	996	*/
AnnaBridge	165:d1b4690b3f8b	997	#define LL_RCC_PLLSAI1Q_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1Q output by 2 /
AnnaBridge	165:d1b4690b3f8b	998	#define LL_RCC_PLLSAI1Q_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1Q_0) /!< PLLSAI1 division factor for PLLSAI1Q output by 4 /
AnnaBridge	165:d1b4690b3f8b	999	#define LL_RCC_PLLSAI1Q_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1Q_1) /!< PLLSAI1 division factor for PLLSAI1Q output by 6 /
AnnaBridge	165:d1b4690b3f8b	1000	#define LL_RCC_PLLSAI1Q_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1Q) /!< PLLSAI1 division factor for PLLSAI1Q output by 8 /
AnnaBridge	165:d1b4690b3f8b	1001	/**
AnnaBridge	165:d1b4690b3f8b	1002	* @}
AnnaBridge	165:d1b4690b3f8b	1003	*/
AnnaBridge	165:d1b4690b3f8b	1004
AnnaBridge	165:d1b4690b3f8b	1005	/** @defgroup RCC_LL_EC_PLLSAI1P PLLSAI1 division factor (PLLSAI1P)
AnnaBridge	165:d1b4690b3f8b	1006	* @{
AnnaBridge	165:d1b4690b3f8b	1007	*/
AnnaBridge	165:d1b4690b3f8b	1008	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1009	#define LL_RCC_PLLSAI1P_DIV_2 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 2 /
AnnaBridge	165:d1b4690b3f8b	1010	#define LL_RCC_PLLSAI1P_DIV_3 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 3 /
AnnaBridge	165:d1b4690b3f8b	1011	#define LL_RCC_PLLSAI1P_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 4 /
AnnaBridge	165:d1b4690b3f8b	1012	#define LL_RCC_PLLSAI1P_DIV_5 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 5 /
AnnaBridge	165:d1b4690b3f8b	1013	#define LL_RCC_PLLSAI1P_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 6 /
AnnaBridge	165:d1b4690b3f8b	1014	#define LL_RCC_PLLSAI1P_DIV_7 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
AnnaBridge	165:d1b4690b3f8b	1015	#define LL_RCC_PLLSAI1P_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 8 /
AnnaBridge	165:d1b4690b3f8b	1016	#define LL_RCC_PLLSAI1P_DIV_9 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 9 /
AnnaBridge	165:d1b4690b3f8b	1017	#define LL_RCC_PLLSAI1P_DIV_10 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 10 /
AnnaBridge	165:d1b4690b3f8b	1018	#define LL_RCC_PLLSAI1P_DIV_11 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 1 /
AnnaBridge	165:d1b4690b3f8b	1019	#define LL_RCC_PLLSAI1P_DIV_12 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 12 /
AnnaBridge	165:d1b4690b3f8b	1020	#define LL_RCC_PLLSAI1P_DIV_13 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 13 /
AnnaBridge	165:d1b4690b3f8b	1021	#define LL_RCC_PLLSAI1P_DIV_14 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 14 /
AnnaBridge	165:d1b4690b3f8b	1022	#define LL_RCC_PLLSAI1P_DIV_15 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 15 /
AnnaBridge	165:d1b4690b3f8b	1023	#define LL_RCC_PLLSAI1P_DIV_16 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4) /!< PLLSAI1 division factor for PLLSAI1P output by 16 /
AnnaBridge	165:d1b4690b3f8b	1024	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
AnnaBridge	165:d1b4690b3f8b	1025	#define LL_RCC_PLLSAI1P_DIV_18 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 18 /
AnnaBridge	165:d1b4690b3f8b	1026	#define LL_RCC_PLLSAI1P_DIV_19 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 19 /
AnnaBridge	165:d1b4690b3f8b	1027	#define LL_RCC_PLLSAI1P_DIV_20 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 20 /
AnnaBridge	165:d1b4690b3f8b	1028	#define LL_RCC_PLLSAI1P_DIV_21 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division fctor for PLLSAI1P output by 21 /
AnnaBridge	165:d1b4690b3f8b	1029	#define LL_RCC_PLLSAI1P_DIV_22 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 22 /
AnnaBridge	165:d1b4690b3f8b	1030	#define LL_RCC_PLLSAI1P_DIV_23 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 23 /
AnnaBridge	165:d1b4690b3f8b	1031	#define LL_RCC_PLLSAI1P_DIV_24 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3) /!< PLLSAI1 division factor for PLLSAI1P output by 24 /
AnnaBridge	165:d1b4690b3f8b	1032	#define LL_RCC_PLLSAI1P_DIV_25 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 25 /
AnnaBridge	165:d1b4690b3f8b	1033	#define LL_RCC_PLLSAI1P_DIV_26 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 26 /
AnnaBridge	165:d1b4690b3f8b	1034	#define LL_RCC_PLLSAI1P_DIV_27 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 27 /
AnnaBridge	165:d1b4690b3f8b	1035	#define LL_RCC_PLLSAI1P_DIV_28 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2) /!< PLLSAI1 division factor for PLLSAI1P output by 28 /
AnnaBridge	165:d1b4690b3f8b	1036	#define LL_RCC_PLLSAI1P_DIV_29 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 29 /
AnnaBridge	165:d1b4690b3f8b	1037	#define LL_RCC_PLLSAI1P_DIV_30 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1) /!< PLLSAI1 division factor for PLLSAI1P output by 30 /
AnnaBridge	165:d1b4690b3f8b	1038	#define LL_RCC_PLLSAI1P_DIV_31 (RCC_PLLSAI1CFGR_PLLSAI1PDIV_4\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_3\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_2\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_1\|RCC_PLLSAI1CFGR_PLLSAI1PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
AnnaBridge	165:d1b4690b3f8b	1039	#else
AnnaBridge	165:d1b4690b3f8b	1040	#define LL_RCC_PLLSAI1P_DIV_7 0x00000000U /!< PLLSAI1 division factor for PLLSAI1P output by 7 /
AnnaBridge	165:d1b4690b3f8b	1041	#define LL_RCC_PLLSAI1P_DIV_17 (RCC_PLLSAI1CFGR_PLLSAI1P) /!< PLLSAI1 division factor for PLLSAI1P output by 17 /
AnnaBridge	165:d1b4690b3f8b	1042	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1043	/**
AnnaBridge	165:d1b4690b3f8b	1044	* @}
AnnaBridge	165:d1b4690b3f8b	1045	*/
AnnaBridge	165:d1b4690b3f8b	1046
AnnaBridge	165:d1b4690b3f8b	1047	/** @defgroup RCC_LL_EC_PLLSAI1R PLLSAI1 division factor (PLLSAI1R)
AnnaBridge	165:d1b4690b3f8b	1048	* @{
AnnaBridge	165:d1b4690b3f8b	1049	*/
AnnaBridge	165:d1b4690b3f8b	1050	#define LL_RCC_PLLSAI1R_DIV_2 0x00000000U /!< PLLSAI1 division factor for PLLSAI1R output by 2 /
AnnaBridge	165:d1b4690b3f8b	1051	#define LL_RCC_PLLSAI1R_DIV_4 (RCC_PLLSAI1CFGR_PLLSAI1R_0) /!< PLLSAI1 division factor for PLLSAI1R output by 4 /
AnnaBridge	165:d1b4690b3f8b	1052	#define LL_RCC_PLLSAI1R_DIV_6 (RCC_PLLSAI1CFGR_PLLSAI1R_1) /!< PLLSAI1 division factor for PLLSAI1R output by 6 /
AnnaBridge	165:d1b4690b3f8b	1053	#define LL_RCC_PLLSAI1R_DIV_8 (RCC_PLLSAI1CFGR_PLLSAI1R) /!< PLLSAI1 division factor for PLLSAI1R output by 8 /
AnnaBridge	165:d1b4690b3f8b	1054	/**
AnnaBridge	165:d1b4690b3f8b	1055	* @}
AnnaBridge	165:d1b4690b3f8b	1056	*/
AnnaBridge	165:d1b4690b3f8b	1057
AnnaBridge	165:d1b4690b3f8b	1058	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1059	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1060	/** @defgroup RCC_LL_EC_PLLSAI2M PLLSAI1 division factor (PLLSAI2M)
AnnaBridge	165:d1b4690b3f8b	1061	* @{
AnnaBridge	165:d1b4690b3f8b	1062	*/
AnnaBridge	165:d1b4690b3f8b	1063	#define LL_RCC_PLLSAI2M_DIV_1 0x00000000U /!< PLLSAI2 division factor for PLLSAI2M input by 1 /
AnnaBridge	165:d1b4690b3f8b	1064	#define LL_RCC_PLLSAI2M_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 2 /
AnnaBridge	165:d1b4690b3f8b	1065	#define LL_RCC_PLLSAI2M_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 3 /
AnnaBridge	165:d1b4690b3f8b	1066	#define LL_RCC_PLLSAI2M_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 4 /
AnnaBridge	165:d1b4690b3f8b	1067	#define LL_RCC_PLLSAI2M_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2M_2) /!< PLLSAI2 division factor for PLLSAI2M input by 5 /
AnnaBridge	165:d1b4690b3f8b	1068	#define LL_RCC_PLLSAI2M_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 6 /
AnnaBridge	165:d1b4690b3f8b	1069	#define LL_RCC_PLLSAI2M_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 7 /
AnnaBridge	165:d1b4690b3f8b	1070	#define LL_RCC_PLLSAI2M_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 8 /
AnnaBridge	165:d1b4690b3f8b	1071	#define LL_RCC_PLLSAI2M_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2M_3) /!< PLLSAI2 division factor for PLLSAI2M input by 9 /
AnnaBridge	165:d1b4690b3f8b	1072	#define LL_RCC_PLLSAI2M_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 10 /
AnnaBridge	165:d1b4690b3f8b	1073	#define LL_RCC_PLLSAI2M_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 11 /
AnnaBridge	165:d1b4690b3f8b	1074	#define LL_RCC_PLLSAI2M_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 12 /
AnnaBridge	165:d1b4690b3f8b	1075	#define LL_RCC_PLLSAI2M_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2) /!< PLLSAI2 division factor for PLLSAI2M input by 13 /
AnnaBridge	165:d1b4690b3f8b	1076	#define LL_RCC_PLLSAI2M_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 14 /
AnnaBridge	165:d1b4690b3f8b	1077	#define LL_RCC_PLLSAI2M_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1) /!< PLLSAI2 division factor for PLLSAI2M input by 15 /
AnnaBridge	165:d1b4690b3f8b	1078	#define LL_RCC_PLLSAI2M_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2M_3\|RCC_PLLSAI2CFGR_PLLSAI2M_2\|RCC_PLLSAI2CFGR_PLLSAI2M_1\|RCC_PLLSAI2CFGR_PLLSAI2M_0) /!< PLLSAI2 division factor for PLLSAI2M input by 16 /
AnnaBridge	165:d1b4690b3f8b	1079	/**
AnnaBridge	165:d1b4690b3f8b	1080	* @}
AnnaBridge	165:d1b4690b3f8b	1081	*/
AnnaBridge	165:d1b4690b3f8b	1082	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1083
AnnaBridge	165:d1b4690b3f8b	1084	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1085	/** @defgroup RCC_LL_EC_PLLSAI2Q PLLSAI2 division factor (PLLSAI2Q)
AnnaBridge	165:d1b4690b3f8b	1086	* @{
AnnaBridge	165:d1b4690b3f8b	1087	*/
AnnaBridge	165:d1b4690b3f8b	1088	#define LL_RCC_PLLSAI2Q_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2Q output by 2 /
AnnaBridge	165:d1b4690b3f8b	1089	#define LL_RCC_PLLSAI2Q_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2Q_0) /!< PLLSAI2 division factor for PLLSAI2Q output by 4 /
AnnaBridge	165:d1b4690b3f8b	1090	#define LL_RCC_PLLSAI2Q_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2Q_1) /!< PLLSAI2 division factor for PLLSAI2Q output by 6 /
AnnaBridge	165:d1b4690b3f8b	1091	#define LL_RCC_PLLSAI2Q_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2Q) /!< PLLSAI2 division factor for PLLSAI2Q output by 8 /
AnnaBridge	165:d1b4690b3f8b	1092	/**
AnnaBridge	165:d1b4690b3f8b	1093	* @}
AnnaBridge	165:d1b4690b3f8b	1094	*/
AnnaBridge	165:d1b4690b3f8b	1095	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1096
AnnaBridge	165:d1b4690b3f8b	1097	/** @defgroup RCC_LL_EC_PLLSAI2P PLLSAI2 division factor (PLLSAI2P)
AnnaBridge	165:d1b4690b3f8b	1098	* @{
AnnaBridge	165:d1b4690b3f8b	1099	*/
AnnaBridge	165:d1b4690b3f8b	1100	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1101	#define LL_RCC_PLLSAI2P_DIV_2 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 2 /
AnnaBridge	165:d1b4690b3f8b	1102	#define LL_RCC_PLLSAI2P_DIV_3 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 3 /
AnnaBridge	165:d1b4690b3f8b	1103	#define LL_RCC_PLLSAI2P_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 4 /
AnnaBridge	165:d1b4690b3f8b	1104	#define LL_RCC_PLLSAI2P_DIV_5 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 5 /
AnnaBridge	165:d1b4690b3f8b	1105	#define LL_RCC_PLLSAI2P_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 6 /
AnnaBridge	165:d1b4690b3f8b	1106	#define LL_RCC_PLLSAI2P_DIV_7 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
AnnaBridge	165:d1b4690b3f8b	1107	#define LL_RCC_PLLSAI2P_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /!< PLLSAI2 division factor for PLLSAI2P output by 8 /
AnnaBridge	165:d1b4690b3f8b	1108	#define LL_RCC_PLLSAI2P_DIV_9 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 9 /
AnnaBridge	165:d1b4690b3f8b	1109	#define LL_RCC_PLLSAI2P_DIV_10 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 10 /
AnnaBridge	165:d1b4690b3f8b	1110	#define LL_RCC_PLLSAI2P_DIV_11 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 1 /
AnnaBridge	165:d1b4690b3f8b	1111	#define LL_RCC_PLLSAI2P_DIV_12 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 12 /
AnnaBridge	165:d1b4690b3f8b	1112	#define LL_RCC_PLLSAI2P_DIV_13 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 13 /
AnnaBridge	165:d1b4690b3f8b	1113	#define LL_RCC_PLLSAI2P_DIV_14 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 14 /
AnnaBridge	165:d1b4690b3f8b	1114	#define LL_RCC_PLLSAI2P_DIV_15 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 15 /
AnnaBridge	165:d1b4690b3f8b	1115	#define LL_RCC_PLLSAI2P_DIV_16 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4) /!< PLLSAI2 division factor for PLLSAI2P output by 16 /
AnnaBridge	165:d1b4690b3f8b	1116	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
AnnaBridge	165:d1b4690b3f8b	1117	#define LL_RCC_PLLSAI2P_DIV_18 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 18 /
AnnaBridge	165:d1b4690b3f8b	1118	#define LL_RCC_PLLSAI2P_DIV_19 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 19 /
AnnaBridge	165:d1b4690b3f8b	1119	#define LL_RCC_PLLSAI2P_DIV_20 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 20 /
AnnaBridge	165:d1b4690b3f8b	1120	#define LL_RCC_PLLSAI2P_DIV_21 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division fctor for PLLSAI2P output by 21 /
AnnaBridge	165:d1b4690b3f8b	1121	#define LL_RCC_PLLSAI2P_DIV_22 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 22 /
AnnaBridge	165:d1b4690b3f8b	1122	#define LL_RCC_PLLSAI2P_DIV_23 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 23 /
AnnaBridge	165:d1b4690b3f8b	1123	#define LL_RCC_PLLSAI2P_DIV_24 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3) /!< PLLSAI2 division factor for PLLSAI2P output by 24 /
AnnaBridge	165:d1b4690b3f8b	1124	#define LL_RCC_PLLSAI2P_DIV_25 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 25 /
AnnaBridge	165:d1b4690b3f8b	1125	#define LL_RCC_PLLSAI2P_DIV_26 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 26 /
AnnaBridge	165:d1b4690b3f8b	1126	#define LL_RCC_PLLSAI2P_DIV_27 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 27 /
AnnaBridge	165:d1b4690b3f8b	1127	#define LL_RCC_PLLSAI2P_DIV_28 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2) /!< PLLSAI2 division factor for PLLSAI2P output by 28 /
AnnaBridge	165:d1b4690b3f8b	1128	#define LL_RCC_PLLSAI2P_DIV_29 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI2 division factor for PLLSAI2P output by 29 /
AnnaBridge	165:d1b4690b3f8b	1129	#define LL_RCC_PLLSAI2P_DIV_30 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1) /!< PLLSAI2 division factor for PLLSAI2P output by 30 /
AnnaBridge	165:d1b4690b3f8b	1130	#define LL_RCC_PLLSAI2P_DIV_31 (RCC_PLLSAI2CFGR_PLLSAI2PDIV_4\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_3\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_2\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_1\|RCC_PLLSAI2CFGR_PLLSAI2PDIV_0) /!< PLLSAI1 division factor for PLLSAI1P output by 31 /
AnnaBridge	165:d1b4690b3f8b	1131	#else
AnnaBridge	165:d1b4690b3f8b	1132	#define LL_RCC_PLLSAI2P_DIV_7 0x00000000U /!< PLLSAI2 division factor for PLLSAI2P output by 7 /
AnnaBridge	165:d1b4690b3f8b	1133	#define LL_RCC_PLLSAI2P_DIV_17 (RCC_PLLSAI2CFGR_PLLSAI2P) /!< PLLSAI2 division factor for PLLSAI2P output by 17 /
AnnaBridge	165:d1b4690b3f8b	1134	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1135	/**
AnnaBridge	165:d1b4690b3f8b	1136	* @}
AnnaBridge	165:d1b4690b3f8b	1137	*/
AnnaBridge	165:d1b4690b3f8b	1138
AnnaBridge	165:d1b4690b3f8b	1139	/** @defgroup RCC_LL_EC_PLLSAI2R PLLSAI2 division factor (PLLSAI2R)
AnnaBridge	165:d1b4690b3f8b	1140	* @{
AnnaBridge	165:d1b4690b3f8b	1141	*/
AnnaBridge	165:d1b4690b3f8b	1142	#define LL_RCC_PLLSAI2R_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2R output by 2 /
AnnaBridge	165:d1b4690b3f8b	1143	#define LL_RCC_PLLSAI2R_DIV_4 (RCC_PLLSAI2CFGR_PLLSAI2R_0) /!< PLLSAI2 division factor for PLLSAI2R output by 4 /
AnnaBridge	165:d1b4690b3f8b	1144	#define LL_RCC_PLLSAI2R_DIV_6 (RCC_PLLSAI2CFGR_PLLSAI2R_1) /!< PLLSAI2 division factor for PLLSAI2R output by 6 /
AnnaBridge	165:d1b4690b3f8b	1145	#define LL_RCC_PLLSAI2R_DIV_8 (RCC_PLLSAI2CFGR_PLLSAI2R) /!< PLLSAI2 division factor for PLLSAI2R output by 8 /
AnnaBridge	165:d1b4690b3f8b	1146	/**
AnnaBridge	165:d1b4690b3f8b	1147	* @}
AnnaBridge	165:d1b4690b3f8b	1148	*/
AnnaBridge	165:d1b4690b3f8b	1149
AnnaBridge	165:d1b4690b3f8b	1150	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	165:d1b4690b3f8b	1151	/** @defgroup RCC_LL_EC_PLLSAI2DIVR PLLSAI2DIVR division factor (PLLSAI2DIVR)
AnnaBridge	165:d1b4690b3f8b	1152	* @{
AnnaBridge	165:d1b4690b3f8b	1153	*/
AnnaBridge	165:d1b4690b3f8b	1154	#define LL_RCC_PLLSAI2DIVR_DIV_2 0x00000000U /!< PLLSAI2 division factor for PLLSAI2DIVR output by 2 /
AnnaBridge	165:d1b4690b3f8b	1155	#define LL_RCC_PLLSAI2DIVR_DIV_4 RCC_CCIPR2_PLLSAI2DIVR_0 /!< PLLSAI2 division factor for PLLSAI2DIVR output by 4 /
AnnaBridge	165:d1b4690b3f8b	1156	#define LL_RCC_PLLSAI2DIVR_DIV_8 RCC_CCIPR2_PLLSAI2DIVR_1 /!< PLLSAI2 division factor for PLLSAI2DIVR output by 8 /
AnnaBridge	165:d1b4690b3f8b	1157	#define LL_RCC_PLLSAI2DIVR_DIV_16 (RCC_CCIPR2_PLLSAI2DIVR_1 \| RCC_CCIPR2_PLLSAI2DIVR_0) /!< PLLSAI2 division factor for PLLSAI2DIVR output by 16 /
AnnaBridge	165:d1b4690b3f8b	1158	/**
AnnaBridge	165:d1b4690b3f8b	1159	* @}
AnnaBridge	165:d1b4690b3f8b	1160	*/
AnnaBridge	165:d1b4690b3f8b	1161	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	165:d1b4690b3f8b	1162	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1163
AnnaBridge	165:d1b4690b3f8b	1164	/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection
AnnaBridge	165:d1b4690b3f8b	1165	* @{
AnnaBridge	165:d1b4690b3f8b	1166	*/
AnnaBridge	165:d1b4690b3f8b	1167	#define LL_RCC_MSIRANGESEL_STANDBY 0U /!< MSI Range is provided by MSISRANGE /
AnnaBridge	165:d1b4690b3f8b	1168	#define LL_RCC_MSIRANGESEL_RUN 1U /!< MSI Range is provided by MSIRANGE /
AnnaBridge	165:d1b4690b3f8b	1169	/**
AnnaBridge	165:d1b4690b3f8b	1170	* @}
AnnaBridge	165:d1b4690b3f8b	1171	*/
AnnaBridge	165:d1b4690b3f8b	1172
AnnaBridge	165:d1b4690b3f8b	1173	/** Legacy definitions for compatibility purpose
AnnaBridge	165:d1b4690b3f8b	1174	@cond 0
AnnaBridge	165:d1b4690b3f8b	1175	*/
AnnaBridge	165:d1b4690b3f8b	1176	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	1177	#define LL_RCC_DFSDM1_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	165:d1b4690b3f8b	1178	#define LL_RCC_DFSDM_CLKSOURCE_PCLK LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	165:d1b4690b3f8b	1179	#define LL_RCC_DFSDM_CLKSOURCE_SYSCLK LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	1180	#define LL_RCC_DFSDM_CLKSOURCE LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	1181	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	1182	#if defined(SWPMI1)
AnnaBridge	165:d1b4690b3f8b	1183	#define LL_RCC_SWPMI1_CLKSOURCE_PCLK LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	1184	#endif /* SWPMI1 */
AnnaBridge	165:d1b4690b3f8b	1185	/**
AnnaBridge	165:d1b4690b3f8b	1186	@endcond
AnnaBridge	165:d1b4690b3f8b	1187	*/
AnnaBridge	165:d1b4690b3f8b	1188
AnnaBridge	165:d1b4690b3f8b	1189	/**
AnnaBridge	165:d1b4690b3f8b	1190	* @}
AnnaBridge	165:d1b4690b3f8b	1191	*/
AnnaBridge	165:d1b4690b3f8b	1192
AnnaBridge	165:d1b4690b3f8b	1193	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	1194	/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
AnnaBridge	165:d1b4690b3f8b	1195	* @{
AnnaBridge	165:d1b4690b3f8b	1196	*/
AnnaBridge	165:d1b4690b3f8b	1197
AnnaBridge	165:d1b4690b3f8b	1198	/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
AnnaBridge	165:d1b4690b3f8b	1199	* @{
AnnaBridge	165:d1b4690b3f8b	1200	*/
AnnaBridge	165:d1b4690b3f8b	1201
AnnaBridge	165:d1b4690b3f8b	1202	/**
AnnaBridge	165:d1b4690b3f8b	1203	* @brief Write a value in RCC register
AnnaBridge	165:d1b4690b3f8b	1204	* @param __REG__ Register to be written
AnnaBridge	165:d1b4690b3f8b	1205	* @param __VALUE__ Value to be written in the register
AnnaBridge	165:d1b4690b3f8b	1206	* @retval None
AnnaBridge	165:d1b4690b3f8b	1207	*/
AnnaBridge	165:d1b4690b3f8b	1208	#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
AnnaBridge	165:d1b4690b3f8b	1209
AnnaBridge	165:d1b4690b3f8b	1210	/**
AnnaBridge	165:d1b4690b3f8b	1211	* @brief Read a value in RCC register
AnnaBridge	165:d1b4690b3f8b	1212	* @param __REG__ Register to be read
AnnaBridge	165:d1b4690b3f8b	1213	* @retval Register value
AnnaBridge	165:d1b4690b3f8b	1214	*/
AnnaBridge	165:d1b4690b3f8b	1215	#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
AnnaBridge	165:d1b4690b3f8b	1216	/**
AnnaBridge	165:d1b4690b3f8b	1217	* @}
AnnaBridge	165:d1b4690b3f8b	1218	*/
AnnaBridge	165:d1b4690b3f8b	1219
AnnaBridge	165:d1b4690b3f8b	1220	/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
AnnaBridge	165:d1b4690b3f8b	1221	* @{
AnnaBridge	165:d1b4690b3f8b	1222	*/
AnnaBridge	165:d1b4690b3f8b	1223
AnnaBridge	165:d1b4690b3f8b	1224	/**
AnnaBridge	165:d1b4690b3f8b	1225	* @brief Helper macro to calculate the PLLCLK frequency on system domain
AnnaBridge	165:d1b4690b3f8b	1226	* @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1227	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
AnnaBridge	165:d1b4690b3f8b	1228	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1229	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1230	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1231	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1232	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1233	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1234	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1235	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1236	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1237	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1238	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	1239	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	1240	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	1241	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	1242	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	1243	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	1244	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	1245	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	1246	*
AnnaBridge	165:d1b4690b3f8b	1247	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	1248	* @param __PLLN__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1249	* @param __PLLR__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1250	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	165:d1b4690b3f8b	1251	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	165:d1b4690b3f8b	1252	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	165:d1b4690b3f8b	1253	* @arg @ref LL_RCC_PLLR_DIV_8
AnnaBridge	165:d1b4690b3f8b	1254	* @retval PLL clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1255	*/
AnnaBridge	165:d1b4690b3f8b	1256	#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	165:d1b4690b3f8b	1257	((((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos) + 1U) * 2U))
AnnaBridge	165:d1b4690b3f8b	1258
AnnaBridge	165:d1b4690b3f8b	1259	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1260	/**
AnnaBridge	165:d1b4690b3f8b	1261	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
AnnaBridge	165:d1b4690b3f8b	1262	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1263	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	165:d1b4690b3f8b	1264	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1265	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1266	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1267	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1268	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1269	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1270	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1271	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1272	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1273	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1274	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	1275	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	1276	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	1277	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	1278	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	1279	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	1280	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	1281	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	1282	*
AnnaBridge	165:d1b4690b3f8b	1283	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	1284	* @param __PLLN__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1285	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1286	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	165:d1b4690b3f8b	1287	* @arg @ref LL_RCC_PLLP_DIV_3
AnnaBridge	165:d1b4690b3f8b	1288	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	165:d1b4690b3f8b	1289	* @arg @ref LL_RCC_PLLP_DIV_5
AnnaBridge	165:d1b4690b3f8b	1290	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	165:d1b4690b3f8b	1291	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	165:d1b4690b3f8b	1292	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	165:d1b4690b3f8b	1293	* @arg @ref LL_RCC_PLLP_DIV_9
AnnaBridge	165:d1b4690b3f8b	1294	* @arg @ref LL_RCC_PLLP_DIV_10
AnnaBridge	165:d1b4690b3f8b	1295	* @arg @ref LL_RCC_PLLP_DIV_11
AnnaBridge	165:d1b4690b3f8b	1296	* @arg @ref LL_RCC_PLLP_DIV_12
AnnaBridge	165:d1b4690b3f8b	1297	* @arg @ref LL_RCC_PLLP_DIV_13
AnnaBridge	165:d1b4690b3f8b	1298	* @arg @ref LL_RCC_PLLP_DIV_14
AnnaBridge	165:d1b4690b3f8b	1299	* @arg @ref LL_RCC_PLLP_DIV_15
AnnaBridge	165:d1b4690b3f8b	1300	* @arg @ref LL_RCC_PLLP_DIV_16
AnnaBridge	165:d1b4690b3f8b	1301	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	165:d1b4690b3f8b	1302	* @arg @ref LL_RCC_PLLP_DIV_18
AnnaBridge	165:d1b4690b3f8b	1303	* @arg @ref LL_RCC_PLLP_DIV_19
AnnaBridge	165:d1b4690b3f8b	1304	* @arg @ref LL_RCC_PLLP_DIV_20
AnnaBridge	165:d1b4690b3f8b	1305	* @arg @ref LL_RCC_PLLP_DIV_21
AnnaBridge	165:d1b4690b3f8b	1306	* @arg @ref LL_RCC_PLLP_DIV_22
AnnaBridge	165:d1b4690b3f8b	1307	* @arg @ref LL_RCC_PLLP_DIV_23
AnnaBridge	165:d1b4690b3f8b	1308	* @arg @ref LL_RCC_PLLP_DIV_24
AnnaBridge	165:d1b4690b3f8b	1309	* @arg @ref LL_RCC_PLLP_DIV_25
AnnaBridge	165:d1b4690b3f8b	1310	* @arg @ref LL_RCC_PLLP_DIV_26
AnnaBridge	165:d1b4690b3f8b	1311	* @arg @ref LL_RCC_PLLP_DIV_27
AnnaBridge	165:d1b4690b3f8b	1312	* @arg @ref LL_RCC_PLLP_DIV_28
AnnaBridge	165:d1b4690b3f8b	1313	* @arg @ref LL_RCC_PLLP_DIV_29
AnnaBridge	165:d1b4690b3f8b	1314	* @arg @ref LL_RCC_PLLP_DIV_30
AnnaBridge	165:d1b4690b3f8b	1315	* @arg @ref LL_RCC_PLLP_DIV_31
AnnaBridge	165:d1b4690b3f8b	1316	* @retval PLL clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1317	*/
AnnaBridge	165:d1b4690b3f8b	1318	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	165:d1b4690b3f8b	1319	((__PLLP__) >> RCC_PLLCFGR_PLLPDIV_Pos))
AnnaBridge	165:d1b4690b3f8b	1320
AnnaBridge	165:d1b4690b3f8b	1321	#else
AnnaBridge	165:d1b4690b3f8b	1322	/**
AnnaBridge	165:d1b4690b3f8b	1323	* @brief Helper macro to calculate the PLLCLK frequency used on SAI domain
AnnaBridge	165:d1b4690b3f8b	1324	* @note ex: @ref __LL_RCC_CALC_PLLCLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1325	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
AnnaBridge	165:d1b4690b3f8b	1326	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1327	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1328	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1329	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1330	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1331	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1332	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1333	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1334	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1335	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1336	* @param __PLLN__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1337	* @param __PLLP__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1338	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	165:d1b4690b3f8b	1339	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	165:d1b4690b3f8b	1340	* @retval PLL clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1341	*/
AnnaBridge	165:d1b4690b3f8b	1342	#define __LL_RCC_CALC_PLLCLK_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	165:d1b4690b3f8b	1343	(((__PLLP__) == LL_RCC_PLLP_DIV_7) ? 7U : 17U))
AnnaBridge	165:d1b4690b3f8b	1344
AnnaBridge	165:d1b4690b3f8b	1345	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1346
AnnaBridge	165:d1b4690b3f8b	1347	/**
AnnaBridge	165:d1b4690b3f8b	1348	* @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
AnnaBridge	165:d1b4690b3f8b	1349	* @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1350	* @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
AnnaBridge	165:d1b4690b3f8b	1351	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1352	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1353	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1354	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1355	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1356	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1357	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1358	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1359	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1360	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1361	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	1362	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	1363	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	1364	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	1365	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	1366	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	1367	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	1368	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	1369	*
AnnaBridge	165:d1b4690b3f8b	1370	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	1371	* @param __PLLN__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1372	* @param __PLLQ__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1373	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	165:d1b4690b3f8b	1374	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	165:d1b4690b3f8b	1375	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	165:d1b4690b3f8b	1376	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	165:d1b4690b3f8b	1377	* @retval PLL clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1378	*/
AnnaBridge	165:d1b4690b3f8b	1379	#define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLN__) / \
AnnaBridge	165:d1b4690b3f8b	1380	((((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1381
AnnaBridge	165:d1b4690b3f8b	1382	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1383	/**
AnnaBridge	165:d1b4690b3f8b	1384	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	165:d1b4690b3f8b	1385	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1386	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	165:d1b4690b3f8b	1387	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1388	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1389	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	1390	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	1391	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	1392	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	1393	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	1394	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	1395	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	1396	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	1397	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	1398	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	1399	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	1400	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	1401	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	1402	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	1403	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	1404	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	1405	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1406	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1407	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	165:d1b4690b3f8b	1408	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	165:d1b4690b3f8b	1409	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	165:d1b4690b3f8b	1410	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	165:d1b4690b3f8b	1411	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	165:d1b4690b3f8b	1412	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	1413	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	165:d1b4690b3f8b	1414	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	165:d1b4690b3f8b	1415	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	165:d1b4690b3f8b	1416	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	165:d1b4690b3f8b	1417	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	165:d1b4690b3f8b	1418	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	165:d1b4690b3f8b	1419	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	165:d1b4690b3f8b	1420	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	165:d1b4690b3f8b	1421	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	165:d1b4690b3f8b	1422	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	1423	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	165:d1b4690b3f8b	1424	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	165:d1b4690b3f8b	1425	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	165:d1b4690b3f8b	1426	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	165:d1b4690b3f8b	1427	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	165:d1b4690b3f8b	1428	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	165:d1b4690b3f8b	1429	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	165:d1b4690b3f8b	1430	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	165:d1b4690b3f8b	1431	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	165:d1b4690b3f8b	1432	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	165:d1b4690b3f8b	1433	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	165:d1b4690b3f8b	1434	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	165:d1b4690b3f8b	1435	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	165:d1b4690b3f8b	1436	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	165:d1b4690b3f8b	1437	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1438	*/
AnnaBridge	165:d1b4690b3f8b	1439	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	165:d1b4690b3f8b	1440	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1441	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	165:d1b4690b3f8b	1442
AnnaBridge	165:d1b4690b3f8b	1443	#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1444	/**
AnnaBridge	165:d1b4690b3f8b	1445	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	165:d1b4690b3f8b	1446	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1447	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	165:d1b4690b3f8b	1448	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1449	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1450	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1451	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1452	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1453	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1454	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1455	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1456	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1457	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1458	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1459	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1460	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	165:d1b4690b3f8b	1461	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	165:d1b4690b3f8b	1462	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	165:d1b4690b3f8b	1463	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	165:d1b4690b3f8b	1464	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	165:d1b4690b3f8b	1465	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	1466	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	165:d1b4690b3f8b	1467	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	165:d1b4690b3f8b	1468	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	165:d1b4690b3f8b	1469	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	165:d1b4690b3f8b	1470	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	165:d1b4690b3f8b	1471	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	165:d1b4690b3f8b	1472	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	165:d1b4690b3f8b	1473	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	165:d1b4690b3f8b	1474	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	165:d1b4690b3f8b	1475	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	1476	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	165:d1b4690b3f8b	1477	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	165:d1b4690b3f8b	1478	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	165:d1b4690b3f8b	1479	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	165:d1b4690b3f8b	1480	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	165:d1b4690b3f8b	1481	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	165:d1b4690b3f8b	1482	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	165:d1b4690b3f8b	1483	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	165:d1b4690b3f8b	1484	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	165:d1b4690b3f8b	1485	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	165:d1b4690b3f8b	1486	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	165:d1b4690b3f8b	1487	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	165:d1b4690b3f8b	1488	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	165:d1b4690b3f8b	1489	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	165:d1b4690b3f8b	1490	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1491	*/
AnnaBridge	165:d1b4690b3f8b	1492	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	165:d1b4690b3f8b	1493	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1494	((__PLLSAI1P__) >> RCC_PLLSAI1CFGR_PLLSAI1PDIV_Pos))
AnnaBridge	165:d1b4690b3f8b	1495
AnnaBridge	165:d1b4690b3f8b	1496	#else
AnnaBridge	165:d1b4690b3f8b	1497	/**
AnnaBridge	165:d1b4690b3f8b	1498	* @brief Helper macro to calculate the PLLSAI1 frequency used for SAI domain
AnnaBridge	165:d1b4690b3f8b	1499	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1500	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetP ());
AnnaBridge	165:d1b4690b3f8b	1501	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1502	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1503	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1504	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1505	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1506	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1507	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1508	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1509	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1510	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1511	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1512	* @param __PLLSAI1P__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1513	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	1514	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	1515	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1516	*/
AnnaBridge	165:d1b4690b3f8b	1517	#define __LL_RCC_CALC_PLLSAI1_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1P__) \
AnnaBridge	165:d1b4690b3f8b	1518	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1519	(((__PLLSAI1P__) == LL_RCC_PLLSAI1P_DIV_7) ? 7U : 17U))
AnnaBridge	165:d1b4690b3f8b	1520
AnnaBridge	165:d1b4690b3f8b	1521	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1522
AnnaBridge	165:d1b4690b3f8b	1523	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1524	/**
AnnaBridge	165:d1b4690b3f8b	1525	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
AnnaBridge	165:d1b4690b3f8b	1526	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1527	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
AnnaBridge	165:d1b4690b3f8b	1528	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1529	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1530	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	1531	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	1532	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	1533	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	1534	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	1535	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	1536	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	1537	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	1538	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	1539	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	1540	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	1541	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	1542	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	1543	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	1544	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	1545	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	1546	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1547	* @param __PLLSAI1Q__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1548	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	1549	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	1550	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	1551	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	1552	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1553	*/
AnnaBridge	165:d1b4690b3f8b	1554	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	165:d1b4690b3f8b	1555	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1556	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1557
AnnaBridge	165:d1b4690b3f8b	1558	#else
AnnaBridge	165:d1b4690b3f8b	1559	/**
AnnaBridge	165:d1b4690b3f8b	1560	* @brief Helper macro to calculate the PLLSAI1 frequency used on 48M domain
AnnaBridge	165:d1b4690b3f8b	1561	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1562	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetQ ());
AnnaBridge	165:d1b4690b3f8b	1563	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1564	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1565	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1566	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1567	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1568	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1569	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1570	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1571	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1572	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1573	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1574	* @param __PLLSAI1Q__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1575	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	1576	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	1577	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	1578	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	1579	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1580	*/
AnnaBridge	165:d1b4690b3f8b	1581	#define __LL_RCC_CALC_PLLSAI1_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1Q__) \
AnnaBridge	165:d1b4690b3f8b	1582	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1583	((((__PLLSAI1Q__) >> RCC_PLLSAI1CFGR_PLLSAI1Q_Pos) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1584
AnnaBridge	165:d1b4690b3f8b	1585	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1586
AnnaBridge	165:d1b4690b3f8b	1587	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1588	/**
AnnaBridge	165:d1b4690b3f8b	1589	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
AnnaBridge	165:d1b4690b3f8b	1590	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI1_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1591	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
AnnaBridge	165:d1b4690b3f8b	1592	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1593	* @param __PLLSAI1M__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1594	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	1595	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	1596	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	1597	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	1598	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	1599	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	1600	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	1601	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	1602	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	1603	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	1604	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	1605	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	1606	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	1607	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	1608	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	1609	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	1610	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1611	* @param __PLLSAI1R__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1612	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	165:d1b4690b3f8b	1613	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	165:d1b4690b3f8b	1614	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	165:d1b4690b3f8b	1615	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	165:d1b4690b3f8b	1616	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1617	*/
AnnaBridge	165:d1b4690b3f8b	1618	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLSAI1M__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	165:d1b4690b3f8b	1619	((__INPUTFREQ__) / ((((__PLLSAI1M__) >> RCC_PLLSAI1CFGR_PLLSAI1M_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1620	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1621
AnnaBridge	165:d1b4690b3f8b	1622	#else
AnnaBridge	165:d1b4690b3f8b	1623	/**
AnnaBridge	165:d1b4690b3f8b	1624	* @brief Helper macro to calculate the PLLSAI1 frequency used on ADC domain
AnnaBridge	165:d1b4690b3f8b	1625	* @note ex: @ref __LL_RCC_CALC_PLLSAI1_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1626	* @ref LL_RCC_PLLSAI1_GetN (), @ref LL_RCC_PLLSAI1_GetR ());
AnnaBridge	165:d1b4690b3f8b	1627	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1628	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1629	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1630	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1631	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1632	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1633	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1634	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1635	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1636	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1637	* @param __PLLSAI1N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1638	* @param __PLLSAI1R__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1639	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	165:d1b4690b3f8b	1640	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	165:d1b4690b3f8b	1641	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	165:d1b4690b3f8b	1642	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	165:d1b4690b3f8b	1643	* @retval PLLSAI1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1644	*/
AnnaBridge	165:d1b4690b3f8b	1645	#define __LL_RCC_CALC_PLLSAI1_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI1N__, __PLLSAI1R__) \
AnnaBridge	165:d1b4690b3f8b	1646	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI1N__) / \
AnnaBridge	165:d1b4690b3f8b	1647	((((__PLLSAI1R__) >> RCC_PLLSAI1CFGR_PLLSAI1R_Pos) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1648
AnnaBridge	165:d1b4690b3f8b	1649	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1650
AnnaBridge	165:d1b4690b3f8b	1651	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1652	/**
AnnaBridge	165:d1b4690b3f8b	1653	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	165:d1b4690b3f8b	1654	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1655	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	165:d1b4690b3f8b	1656	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1657	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1658	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	1659	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	1660	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	1661	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	1662	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	1663	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	1664	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	1665	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	1666	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	1667	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	1668	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	1669	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	1670	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	1671	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	1672	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	1673	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	1674	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1675	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1676	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	165:d1b4690b3f8b	1677	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	165:d1b4690b3f8b	1678	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	165:d1b4690b3f8b	1679	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	165:d1b4690b3f8b	1680	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	165:d1b4690b3f8b	1681	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	1682	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	165:d1b4690b3f8b	1683	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	165:d1b4690b3f8b	1684	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	165:d1b4690b3f8b	1685	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	165:d1b4690b3f8b	1686	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	165:d1b4690b3f8b	1687	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	165:d1b4690b3f8b	1688	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	165:d1b4690b3f8b	1689	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	165:d1b4690b3f8b	1690	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	165:d1b4690b3f8b	1691	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	1692	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	165:d1b4690b3f8b	1693	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	165:d1b4690b3f8b	1694	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	165:d1b4690b3f8b	1695	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	165:d1b4690b3f8b	1696	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	165:d1b4690b3f8b	1697	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	165:d1b4690b3f8b	1698	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	165:d1b4690b3f8b	1699	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	165:d1b4690b3f8b	1700	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	165:d1b4690b3f8b	1701	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	165:d1b4690b3f8b	1702	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	165:d1b4690b3f8b	1703	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	165:d1b4690b3f8b	1704	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	165:d1b4690b3f8b	1705	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	165:d1b4690b3f8b	1706	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1707	*/
AnnaBridge	165:d1b4690b3f8b	1708	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	165:d1b4690b3f8b	1709	((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	165:d1b4690b3f8b	1710	((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	165:d1b4690b3f8b	1711
AnnaBridge	165:d1b4690b3f8b	1712	#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1713	/**
AnnaBridge	165:d1b4690b3f8b	1714	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	165:d1b4690b3f8b	1715	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1716	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	165:d1b4690b3f8b	1717	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1718	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1719	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1720	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1721	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1722	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1723	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1724	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1725	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1726	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1727	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1728	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1729	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	165:d1b4690b3f8b	1730	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	165:d1b4690b3f8b	1731	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	165:d1b4690b3f8b	1732	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	165:d1b4690b3f8b	1733	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	165:d1b4690b3f8b	1734	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	1735	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	165:d1b4690b3f8b	1736	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	165:d1b4690b3f8b	1737	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	165:d1b4690b3f8b	1738	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	165:d1b4690b3f8b	1739	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	165:d1b4690b3f8b	1740	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	165:d1b4690b3f8b	1741	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	165:d1b4690b3f8b	1742	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	165:d1b4690b3f8b	1743	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	165:d1b4690b3f8b	1744	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	1745	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	165:d1b4690b3f8b	1746	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	165:d1b4690b3f8b	1747	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	165:d1b4690b3f8b	1748	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	165:d1b4690b3f8b	1749	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	165:d1b4690b3f8b	1750	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	165:d1b4690b3f8b	1751	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	165:d1b4690b3f8b	1752	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	165:d1b4690b3f8b	1753	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	165:d1b4690b3f8b	1754	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	165:d1b4690b3f8b	1755	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	165:d1b4690b3f8b	1756	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	165:d1b4690b3f8b	1757	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	165:d1b4690b3f8b	1758	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	165:d1b4690b3f8b	1759	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1760	*/
AnnaBridge	165:d1b4690b3f8b	1761	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	165:d1b4690b3f8b	1762	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	165:d1b4690b3f8b	1763	((__PLLSAI2P__) >> RCC_PLLSAI2CFGR_PLLSAI2PDIV_Pos))
AnnaBridge	165:d1b4690b3f8b	1764
AnnaBridge	165:d1b4690b3f8b	1765	#else
AnnaBridge	165:d1b4690b3f8b	1766	/**
AnnaBridge	165:d1b4690b3f8b	1767	* @brief Helper macro to calculate the PLLSAI2 frequency used for SAI domain
AnnaBridge	165:d1b4690b3f8b	1768	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1769	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetP ());
AnnaBridge	165:d1b4690b3f8b	1770	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1771	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1772	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1773	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1774	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1775	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1776	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1777	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1778	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1779	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1780	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1781	* @param __PLLSAI2P__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1782	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	1783	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	1784	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1785	*/
AnnaBridge	165:d1b4690b3f8b	1786	#define __LL_RCC_CALC_PLLSAI2_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2P__) \
AnnaBridge	165:d1b4690b3f8b	1787	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1)) * (__PLLSAI2N__) / \
AnnaBridge	165:d1b4690b3f8b	1788	(((__PLLSAI2P__) == LL_RCC_PLLSAI2P_DIV_7) ? 7U : 17U))
AnnaBridge	165:d1b4690b3f8b	1789
AnnaBridge	165:d1b4690b3f8b	1790	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1791
AnnaBridge	165:d1b4690b3f8b	1792	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	1793	/**
AnnaBridge	165:d1b4690b3f8b	1794	* @brief Helper macro to calculate the PLLSAI2 frequency used for LTDC domain
AnnaBridge	165:d1b4690b3f8b	1795	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1796	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR (), @ref LL_RCC_PLLSAI2_GetDIVR ());
AnnaBridge	165:d1b4690b3f8b	1797	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
AnnaBridge	165:d1b4690b3f8b	1798	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1799	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	1800	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	1801	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	1802	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	1803	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	1804	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	1805	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	1806	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	1807	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	1808	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	1809	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	1810	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	1811	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	1812	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	1813	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	1814	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	1815	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1816	* @param __PLLSAI2R__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1817	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	165:d1b4690b3f8b	1818	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	165:d1b4690b3f8b	1819	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	165:d1b4690b3f8b	1820	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	165:d1b4690b3f8b	1821	* @param __PLLSAI2DIVR__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1822	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	165:d1b4690b3f8b	1823	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	165:d1b4690b3f8b	1824	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	165:d1b4690b3f8b	1825	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	165:d1b4690b3f8b	1826	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1827	*/
AnnaBridge	165:d1b4690b3f8b	1828	#define __LL_RCC_CALC_PLLSAI2_LTDC_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2R__, __PLLSAI2DIVR__) \
AnnaBridge	165:d1b4690b3f8b	1829	(((__INPUTFREQ__) / (((__PLLSAI2M__)>> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	165:d1b4690b3f8b	1830	(((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U) * (aRCC_PLLSAI2DIVRPrescTable[(__PLLSAI2DIVR__) >> RCC_CCIPR2_PLLSAI2DIVR_Pos])))
AnnaBridge	165:d1b4690b3f8b	1831	#else
AnnaBridge	165:d1b4690b3f8b	1832	/**
AnnaBridge	165:d1b4690b3f8b	1833	* @brief Helper macro to calculate the PLLSAI2 frequency used on ADC domain
AnnaBridge	165:d1b4690b3f8b	1834	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1835	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetR ());
AnnaBridge	165:d1b4690b3f8b	1836	* @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI)
AnnaBridge	165:d1b4690b3f8b	1837	* @param __PLLM__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1838	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	1839	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	1840	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	1841	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	1842	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	1843	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	1844	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	1845	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	1846	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1847	* @param __PLLSAI2R__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1848	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	165:d1b4690b3f8b	1849	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	165:d1b4690b3f8b	1850	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	165:d1b4690b3f8b	1851	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	165:d1b4690b3f8b	1852	* @retval PLLSAI2 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1853	*/
AnnaBridge	165:d1b4690b3f8b	1854	#define __LL_RCC_CALC_PLLSAI2_ADC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAI2N__, __PLLSAI2R__) \
AnnaBridge	165:d1b4690b3f8b	1855	((__INPUTFREQ__) / ((((__PLLM__)>> RCC_PLLCFGR_PLLM_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	165:d1b4690b3f8b	1856	((((__PLLSAI2R__) >> RCC_PLLSAI2CFGR_PLLSAI2R_Pos ) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1857
AnnaBridge	165:d1b4690b3f8b	1858	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	1859
AnnaBridge	165:d1b4690b3f8b	1860	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	1861	/**
AnnaBridge	165:d1b4690b3f8b	1862	* @brief Helper macro to calculate the PLLDSICLK frequency used on DSI
AnnaBridge	165:d1b4690b3f8b	1863	* @note ex: @ref __LL_RCC_CALC_PLLSAI2_DSI_FREQ (HSE_VALUE,@ref LL_RCC_PLLSAI2_GetDivider (),
AnnaBridge	165:d1b4690b3f8b	1864	* @ref LL_RCC_PLLSAI2_GetN (), @ref LL_RCC_PLLSAI2_GetQ ());
AnnaBridge	165:d1b4690b3f8b	1865	* @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI/MSI)
AnnaBridge	165:d1b4690b3f8b	1866	* @param __PLLSAI2M__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1867	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	1868	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	1869	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	1870	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	1871	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	1872	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	1873	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	1874	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	1875	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	1876	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	1877	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	1878	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	1879	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	1880	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	1881	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	1882	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	1883	* @param __PLLSAI2N__ Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	1884	* @param __PLLSAI2Q__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1885	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	1886	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	1887	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	1888	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	1889	* @retval PLL clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1890	*/
AnnaBridge	165:d1b4690b3f8b	1891	#define __LL_RCC_CALC_PLLSAI2_DSI_FREQ(__INPUTFREQ__, __PLLSAI2M__, __PLLSAI2N__, __PLLSAI2Q__) \
AnnaBridge	165:d1b4690b3f8b	1892	((__INPUTFREQ__) / ((((__PLLSAI2M__) >> RCC_PLLSAI2CFGR_PLLSAI2M_Pos) + 1U)) * (__PLLSAI2N__) / \
AnnaBridge	165:d1b4690b3f8b	1893	((((__PLLSAI2Q__) >> RCC_PLLSAI2CFGR_PLLSAI2Q_Pos) + 1U) << 1U))
AnnaBridge	165:d1b4690b3f8b	1894	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	1895
AnnaBridge	165:d1b4690b3f8b	1896
AnnaBridge	165:d1b4690b3f8b	1897
AnnaBridge	165:d1b4690b3f8b	1898	/**
AnnaBridge	165:d1b4690b3f8b	1899	* @brief Helper macro to calculate the HCLK frequency
AnnaBridge	165:d1b4690b3f8b	1900	* @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK)
AnnaBridge	165:d1b4690b3f8b	1901	* @param __AHBPRESCALER__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1902	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	165:d1b4690b3f8b	1903	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	165:d1b4690b3f8b	1904	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	165:d1b4690b3f8b	1905	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	165:d1b4690b3f8b	1906	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	165:d1b4690b3f8b	1907	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	165:d1b4690b3f8b	1908	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	165:d1b4690b3f8b	1909	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	165:d1b4690b3f8b	1910	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	165:d1b4690b3f8b	1911	* @retval HCLK clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1912	*/
AnnaBridge	165:d1b4690b3f8b	1913	#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
AnnaBridge	165:d1b4690b3f8b	1914
AnnaBridge	165:d1b4690b3f8b	1915	/**
AnnaBridge	165:d1b4690b3f8b	1916	* @brief Helper macro to calculate the PCLK1 frequency (ABP1)
AnnaBridge	165:d1b4690b3f8b	1917	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	165:d1b4690b3f8b	1918	* @param __APB1PRESCALER__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1919	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	165:d1b4690b3f8b	1920	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	165:d1b4690b3f8b	1921	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	165:d1b4690b3f8b	1922	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	165:d1b4690b3f8b	1923	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	165:d1b4690b3f8b	1924	* @retval PCLK1 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1925	*/
AnnaBridge	165:d1b4690b3f8b	1926	#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
AnnaBridge	165:d1b4690b3f8b	1927
AnnaBridge	165:d1b4690b3f8b	1928	/**
AnnaBridge	165:d1b4690b3f8b	1929	* @brief Helper macro to calculate the PCLK2 frequency (ABP2)
AnnaBridge	165:d1b4690b3f8b	1930	* @param __HCLKFREQ__ HCLK frequency
AnnaBridge	165:d1b4690b3f8b	1931	* @param __APB2PRESCALER__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1932	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	165:d1b4690b3f8b	1933	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	165:d1b4690b3f8b	1934	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	165:d1b4690b3f8b	1935	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	165:d1b4690b3f8b	1936	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	165:d1b4690b3f8b	1937	* @retval PCLK2 clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1938	*/
AnnaBridge	165:d1b4690b3f8b	1939	#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
AnnaBridge	165:d1b4690b3f8b	1940
AnnaBridge	165:d1b4690b3f8b	1941	/**
AnnaBridge	165:d1b4690b3f8b	1942	* @brief Helper macro to calculate the MSI frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1943	* @note __MSISEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect()
AnnaBridge	165:d1b4690b3f8b	1944	* @note if __MSISEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY,
AnnaBridge	165:d1b4690b3f8b	1945	* __MSIRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby()
AnnaBridge	165:d1b4690b3f8b	1946	* else by LL_RCC_MSI_GetRange()
AnnaBridge	165:d1b4690b3f8b	1947	* ex: __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(),
AnnaBridge	165:d1b4690b3f8b	1948	* (LL_RCC_MSI_IsEnabledRangeSelect()?
AnnaBridge	165:d1b4690b3f8b	1949	* LL_RCC_MSI_GetRange():
AnnaBridge	165:d1b4690b3f8b	1950	* LL_RCC_MSI_GetRangeAfterStandby()))
AnnaBridge	165:d1b4690b3f8b	1951	* @param __MSISEL__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1952	* @arg @ref LL_RCC_MSIRANGESEL_STANDBY
AnnaBridge	165:d1b4690b3f8b	1953	* @arg @ref LL_RCC_MSIRANGESEL_RUN
AnnaBridge	165:d1b4690b3f8b	1954	* @param __MSIRANGE__ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	1955	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	165:d1b4690b3f8b	1956	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	165:d1b4690b3f8b	1957	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	165:d1b4690b3f8b	1958	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	165:d1b4690b3f8b	1959	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	165:d1b4690b3f8b	1960	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	165:d1b4690b3f8b	1961	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	165:d1b4690b3f8b	1962	* @arg @ref LL_RCC_MSIRANGE_7
AnnaBridge	165:d1b4690b3f8b	1963	* @arg @ref LL_RCC_MSIRANGE_8
AnnaBridge	165:d1b4690b3f8b	1964	* @arg @ref LL_RCC_MSIRANGE_9
AnnaBridge	165:d1b4690b3f8b	1965	* @arg @ref LL_RCC_MSIRANGE_10
AnnaBridge	165:d1b4690b3f8b	1966	* @arg @ref LL_RCC_MSIRANGE_11
AnnaBridge	165:d1b4690b3f8b	1967	* @arg @ref LL_RCC_MSISRANGE_4
AnnaBridge	165:d1b4690b3f8b	1968	* @arg @ref LL_RCC_MSISRANGE_5
AnnaBridge	165:d1b4690b3f8b	1969	* @arg @ref LL_RCC_MSISRANGE_6
AnnaBridge	165:d1b4690b3f8b	1970	* @arg @ref LL_RCC_MSISRANGE_7
AnnaBridge	165:d1b4690b3f8b	1971	* @retval MSI clock frequency (in Hz)
AnnaBridge	165:d1b4690b3f8b	1972	*/
AnnaBridge	165:d1b4690b3f8b	1973	#define __LL_RCC_CALC_MSI_FREQ(__MSISEL__, __MSIRANGE__) (((__MSISEL__) == LL_RCC_MSIRANGESEL_STANDBY) ? \
AnnaBridge	165:d1b4690b3f8b	1974	(MSIRangeTable[(__MSIRANGE__) >> 8U]) : \
AnnaBridge	165:d1b4690b3f8b	1975	(MSIRangeTable[(__MSIRANGE__) >> 4U]))
AnnaBridge	165:d1b4690b3f8b	1976
AnnaBridge	165:d1b4690b3f8b	1977	/**
AnnaBridge	165:d1b4690b3f8b	1978	* @}
AnnaBridge	165:d1b4690b3f8b	1979	*/
AnnaBridge	165:d1b4690b3f8b	1980
AnnaBridge	165:d1b4690b3f8b	1981	/**
AnnaBridge	165:d1b4690b3f8b	1982	* @}
AnnaBridge	165:d1b4690b3f8b	1983	*/
AnnaBridge	165:d1b4690b3f8b	1984
AnnaBridge	165:d1b4690b3f8b	1985	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	1986	/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
AnnaBridge	165:d1b4690b3f8b	1987	* @{
AnnaBridge	165:d1b4690b3f8b	1988	*/
AnnaBridge	165:d1b4690b3f8b	1989
AnnaBridge	165:d1b4690b3f8b	1990	/** @defgroup RCC_LL_EF_HSE HSE
AnnaBridge	165:d1b4690b3f8b	1991	* @{
AnnaBridge	165:d1b4690b3f8b	1992	*/
AnnaBridge	165:d1b4690b3f8b	1993
AnnaBridge	165:d1b4690b3f8b	1994	/**
AnnaBridge	165:d1b4690b3f8b	1995	* @brief Enable the Clock Security System.
AnnaBridge	165:d1b4690b3f8b	1996	* @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
AnnaBridge	165:d1b4690b3f8b	1997	* @retval None
AnnaBridge	165:d1b4690b3f8b	1998	*/
AnnaBridge	165:d1b4690b3f8b	1999	__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
AnnaBridge	165:d1b4690b3f8b	2000	{
AnnaBridge	165:d1b4690b3f8b	2001	SET_BIT(RCC->CR, RCC_CR_CSSON);
AnnaBridge	165:d1b4690b3f8b	2002	}
AnnaBridge	165:d1b4690b3f8b	2003
AnnaBridge	165:d1b4690b3f8b	2004	/**
AnnaBridge	165:d1b4690b3f8b	2005	* @brief Enable HSE external oscillator (HSE Bypass)
AnnaBridge	165:d1b4690b3f8b	2006	* @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
AnnaBridge	165:d1b4690b3f8b	2007	* @retval None
AnnaBridge	165:d1b4690b3f8b	2008	*/
AnnaBridge	165:d1b4690b3f8b	2009	__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
AnnaBridge	165:d1b4690b3f8b	2010	{
AnnaBridge	165:d1b4690b3f8b	2011	SET_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	165:d1b4690b3f8b	2012	}
AnnaBridge	165:d1b4690b3f8b	2013
AnnaBridge	165:d1b4690b3f8b	2014	/**
AnnaBridge	165:d1b4690b3f8b	2015	* @brief Disable HSE external oscillator (HSE Bypass)
AnnaBridge	165:d1b4690b3f8b	2016	* @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
AnnaBridge	165:d1b4690b3f8b	2017	* @retval None
AnnaBridge	165:d1b4690b3f8b	2018	*/
AnnaBridge	165:d1b4690b3f8b	2019	__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
AnnaBridge	165:d1b4690b3f8b	2020	{
AnnaBridge	165:d1b4690b3f8b	2021	CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
AnnaBridge	165:d1b4690b3f8b	2022	}
AnnaBridge	165:d1b4690b3f8b	2023
AnnaBridge	165:d1b4690b3f8b	2024	/**
AnnaBridge	165:d1b4690b3f8b	2025	* @brief Enable HSE crystal oscillator (HSE ON)
AnnaBridge	165:d1b4690b3f8b	2026	* @rmtoll CR HSEON LL_RCC_HSE_Enable
AnnaBridge	165:d1b4690b3f8b	2027	* @retval None
AnnaBridge	165:d1b4690b3f8b	2028	*/
AnnaBridge	165:d1b4690b3f8b	2029	__STATIC_INLINE void LL_RCC_HSE_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2030	{
AnnaBridge	165:d1b4690b3f8b	2031	SET_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	165:d1b4690b3f8b	2032	}
AnnaBridge	165:d1b4690b3f8b	2033
AnnaBridge	165:d1b4690b3f8b	2034	/**
AnnaBridge	165:d1b4690b3f8b	2035	* @brief Disable HSE crystal oscillator (HSE ON)
AnnaBridge	165:d1b4690b3f8b	2036	* @rmtoll CR HSEON LL_RCC_HSE_Disable
AnnaBridge	165:d1b4690b3f8b	2037	* @retval None
AnnaBridge	165:d1b4690b3f8b	2038	*/
AnnaBridge	165:d1b4690b3f8b	2039	__STATIC_INLINE void LL_RCC_HSE_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2040	{
AnnaBridge	165:d1b4690b3f8b	2041	CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
AnnaBridge	165:d1b4690b3f8b	2042	}
AnnaBridge	165:d1b4690b3f8b	2043
AnnaBridge	165:d1b4690b3f8b	2044	/**
AnnaBridge	165:d1b4690b3f8b	2045	* @brief Check if HSE oscillator Ready
AnnaBridge	165:d1b4690b3f8b	2046	* @rmtoll CR HSERDY LL_RCC_HSE_IsReady
AnnaBridge	165:d1b4690b3f8b	2047	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2048	*/
AnnaBridge	165:d1b4690b3f8b	2049	__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	2050	{
AnnaBridge	165:d1b4690b3f8b	2051	return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
AnnaBridge	165:d1b4690b3f8b	2052	}
AnnaBridge	165:d1b4690b3f8b	2053
AnnaBridge	165:d1b4690b3f8b	2054	/**
AnnaBridge	165:d1b4690b3f8b	2055	* @}
AnnaBridge	165:d1b4690b3f8b	2056	*/
AnnaBridge	165:d1b4690b3f8b	2057
AnnaBridge	165:d1b4690b3f8b	2058	/** @defgroup RCC_LL_EF_HSI HSI
AnnaBridge	165:d1b4690b3f8b	2059	* @{
AnnaBridge	165:d1b4690b3f8b	2060	*/
AnnaBridge	165:d1b4690b3f8b	2061
AnnaBridge	165:d1b4690b3f8b	2062	/**
AnnaBridge	165:d1b4690b3f8b	2063	* @brief Enable HSI even in stop mode
AnnaBridge	165:d1b4690b3f8b	2064	* @note HSI oscillator is forced ON even in Stop mode
AnnaBridge	165:d1b4690b3f8b	2065	* @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode
AnnaBridge	165:d1b4690b3f8b	2066	* @retval None
AnnaBridge	165:d1b4690b3f8b	2067	*/
AnnaBridge	165:d1b4690b3f8b	2068	__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void)
AnnaBridge	165:d1b4690b3f8b	2069	{
AnnaBridge	165:d1b4690b3f8b	2070	SET_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	165:d1b4690b3f8b	2071	}
AnnaBridge	165:d1b4690b3f8b	2072
AnnaBridge	165:d1b4690b3f8b	2073	/**
AnnaBridge	165:d1b4690b3f8b	2074	* @brief Disable HSI in stop mode
AnnaBridge	165:d1b4690b3f8b	2075	* @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode
AnnaBridge	165:d1b4690b3f8b	2076	* @retval None
AnnaBridge	165:d1b4690b3f8b	2077	*/
AnnaBridge	165:d1b4690b3f8b	2078	__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void)
AnnaBridge	165:d1b4690b3f8b	2079	{
AnnaBridge	165:d1b4690b3f8b	2080	CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
AnnaBridge	165:d1b4690b3f8b	2081	}
AnnaBridge	165:d1b4690b3f8b	2082
AnnaBridge	165:d1b4690b3f8b	2083	/**
AnnaBridge	165:d1b4690b3f8b	2084	* @brief Check if HSI is enabled in stop mode
AnnaBridge	165:d1b4690b3f8b	2085	* @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode
AnnaBridge	165:d1b4690b3f8b	2086	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2087	*/
AnnaBridge	165:d1b4690b3f8b	2088	__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void)
AnnaBridge	165:d1b4690b3f8b	2089	{
AnnaBridge	165:d1b4690b3f8b	2090	return (READ_BIT(RCC->CR, RCC_CR_HSIKERON) == (RCC_CR_HSIKERON));
AnnaBridge	165:d1b4690b3f8b	2091	}
AnnaBridge	165:d1b4690b3f8b	2092
AnnaBridge	165:d1b4690b3f8b	2093	/**
AnnaBridge	165:d1b4690b3f8b	2094	* @brief Enable HSI oscillator
AnnaBridge	165:d1b4690b3f8b	2095	* @rmtoll CR HSION LL_RCC_HSI_Enable
AnnaBridge	165:d1b4690b3f8b	2096	* @retval None
AnnaBridge	165:d1b4690b3f8b	2097	*/
AnnaBridge	165:d1b4690b3f8b	2098	__STATIC_INLINE void LL_RCC_HSI_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2099	{
AnnaBridge	165:d1b4690b3f8b	2100	SET_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	165:d1b4690b3f8b	2101	}
AnnaBridge	165:d1b4690b3f8b	2102
AnnaBridge	165:d1b4690b3f8b	2103	/**
AnnaBridge	165:d1b4690b3f8b	2104	* @brief Disable HSI oscillator
AnnaBridge	165:d1b4690b3f8b	2105	* @rmtoll CR HSION LL_RCC_HSI_Disable
AnnaBridge	165:d1b4690b3f8b	2106	* @retval None
AnnaBridge	165:d1b4690b3f8b	2107	*/
AnnaBridge	165:d1b4690b3f8b	2108	__STATIC_INLINE void LL_RCC_HSI_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2109	{
AnnaBridge	165:d1b4690b3f8b	2110	CLEAR_BIT(RCC->CR, RCC_CR_HSION);
AnnaBridge	165:d1b4690b3f8b	2111	}
AnnaBridge	165:d1b4690b3f8b	2112
AnnaBridge	165:d1b4690b3f8b	2113	/**
AnnaBridge	165:d1b4690b3f8b	2114	* @brief Check if HSI clock is ready
AnnaBridge	165:d1b4690b3f8b	2115	* @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
AnnaBridge	165:d1b4690b3f8b	2116	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2117	*/
AnnaBridge	165:d1b4690b3f8b	2118	__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	2119	{
AnnaBridge	165:d1b4690b3f8b	2120	return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
AnnaBridge	165:d1b4690b3f8b	2121	}
AnnaBridge	165:d1b4690b3f8b	2122
AnnaBridge	165:d1b4690b3f8b	2123	/**
AnnaBridge	165:d1b4690b3f8b	2124	* @brief Enable HSI Automatic from stop mode
AnnaBridge	165:d1b4690b3f8b	2125	* @rmtoll CR HSIASFS LL_RCC_HSI_EnableAutoFromStop
AnnaBridge	165:d1b4690b3f8b	2126	* @retval None
AnnaBridge	165:d1b4690b3f8b	2127	*/
AnnaBridge	165:d1b4690b3f8b	2128	__STATIC_INLINE void LL_RCC_HSI_EnableAutoFromStop(void)
AnnaBridge	165:d1b4690b3f8b	2129	{
AnnaBridge	165:d1b4690b3f8b	2130	SET_BIT(RCC->CR, RCC_CR_HSIASFS);
AnnaBridge	165:d1b4690b3f8b	2131	}
AnnaBridge	165:d1b4690b3f8b	2132
AnnaBridge	165:d1b4690b3f8b	2133	/**
AnnaBridge	165:d1b4690b3f8b	2134	* @brief Disable HSI Automatic from stop mode
AnnaBridge	165:d1b4690b3f8b	2135	* @rmtoll CR HSIASFS LL_RCC_HSI_DisableAutoFromStop
AnnaBridge	165:d1b4690b3f8b	2136	* @retval None
AnnaBridge	165:d1b4690b3f8b	2137	*/
AnnaBridge	165:d1b4690b3f8b	2138	__STATIC_INLINE void LL_RCC_HSI_DisableAutoFromStop(void)
AnnaBridge	165:d1b4690b3f8b	2139	{
AnnaBridge	165:d1b4690b3f8b	2140	CLEAR_BIT(RCC->CR, RCC_CR_HSIASFS);
AnnaBridge	165:d1b4690b3f8b	2141	}
AnnaBridge	165:d1b4690b3f8b	2142	/**
AnnaBridge	165:d1b4690b3f8b	2143	* @brief Get HSI Calibration value
AnnaBridge	165:d1b4690b3f8b	2144	* @note When HSITRIM is written, HSICAL is updated with the sum of
AnnaBridge	165:d1b4690b3f8b	2145	* HSITRIM and the factory trim value
AnnaBridge	165:d1b4690b3f8b	2146	* @rmtoll ICSCR HSICAL LL_RCC_HSI_GetCalibration
AnnaBridge	165:d1b4690b3f8b	2147	* @retval Between Min_Data = 0x00 and Max_Data = 0xFF
AnnaBridge	165:d1b4690b3f8b	2148	*/
AnnaBridge	165:d1b4690b3f8b	2149	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
AnnaBridge	165:d1b4690b3f8b	2150	{
AnnaBridge	165:d1b4690b3f8b	2151	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSICAL) >> RCC_ICSCR_HSICAL_Pos);
AnnaBridge	165:d1b4690b3f8b	2152	}
AnnaBridge	165:d1b4690b3f8b	2153
AnnaBridge	165:d1b4690b3f8b	2154	/**
AnnaBridge	165:d1b4690b3f8b	2155	* @brief Set HSI Calibration trimming
AnnaBridge	165:d1b4690b3f8b	2156	* @note user-programmable trimming value that is added to the HSICAL
AnnaBridge	165:d1b4690b3f8b	2157	* @note Default value is 16, which, when added to the HSICAL value,
AnnaBridge	165:d1b4690b3f8b	2158	* should trim the HSI to 16 MHz +/- 1 %
AnnaBridge	165:d1b4690b3f8b	2159	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_SetCalibTrimming
AnnaBridge	165:d1b4690b3f8b	2160	* @param Value Between Min_Data = 0 and Max_Data = 31
AnnaBridge	165:d1b4690b3f8b	2161	* @retval None
AnnaBridge	165:d1b4690b3f8b	2162	*/
AnnaBridge	165:d1b4690b3f8b	2163	__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	165:d1b4690b3f8b	2164	{
AnnaBridge	165:d1b4690b3f8b	2165	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	165:d1b4690b3f8b	2166	}
AnnaBridge	165:d1b4690b3f8b	2167
AnnaBridge	165:d1b4690b3f8b	2168	/**
AnnaBridge	165:d1b4690b3f8b	2169	* @brief Get HSI Calibration trimming
AnnaBridge	165:d1b4690b3f8b	2170	* @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming
AnnaBridge	165:d1b4690b3f8b	2171	* @retval Between Min_Data = 0 and Max_Data = 31
AnnaBridge	165:d1b4690b3f8b	2172	*/
AnnaBridge	165:d1b4690b3f8b	2173	__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
AnnaBridge	165:d1b4690b3f8b	2174	{
AnnaBridge	165:d1b4690b3f8b	2175	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSITRIM) >> RCC_ICSCR_HSITRIM_Pos);
AnnaBridge	165:d1b4690b3f8b	2176	}
AnnaBridge	165:d1b4690b3f8b	2177
AnnaBridge	165:d1b4690b3f8b	2178	/**
AnnaBridge	165:d1b4690b3f8b	2179	* @}
AnnaBridge	165:d1b4690b3f8b	2180	*/
AnnaBridge	165:d1b4690b3f8b	2181
AnnaBridge	165:d1b4690b3f8b	2182	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	2183	/** @defgroup RCC_LL_EF_HSI48 HSI48
AnnaBridge	165:d1b4690b3f8b	2184	* @{
AnnaBridge	165:d1b4690b3f8b	2185	*/
AnnaBridge	165:d1b4690b3f8b	2186
AnnaBridge	165:d1b4690b3f8b	2187	/**
AnnaBridge	165:d1b4690b3f8b	2188	* @brief Enable HSI48
AnnaBridge	165:d1b4690b3f8b	2189	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Enable
AnnaBridge	165:d1b4690b3f8b	2190	* @retval None
AnnaBridge	165:d1b4690b3f8b	2191	*/
AnnaBridge	165:d1b4690b3f8b	2192	__STATIC_INLINE void LL_RCC_HSI48_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2193	{
AnnaBridge	165:d1b4690b3f8b	2194	SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
AnnaBridge	165:d1b4690b3f8b	2195	}
AnnaBridge	165:d1b4690b3f8b	2196
AnnaBridge	165:d1b4690b3f8b	2197	/**
AnnaBridge	165:d1b4690b3f8b	2198	* @brief Disable HSI48
AnnaBridge	165:d1b4690b3f8b	2199	* @rmtoll CRRCR HSI48ON LL_RCC_HSI48_Disable
AnnaBridge	165:d1b4690b3f8b	2200	* @retval None
AnnaBridge	165:d1b4690b3f8b	2201	*/
AnnaBridge	165:d1b4690b3f8b	2202	__STATIC_INLINE void LL_RCC_HSI48_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2203	{
AnnaBridge	165:d1b4690b3f8b	2204	CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON);
AnnaBridge	165:d1b4690b3f8b	2205	}
AnnaBridge	165:d1b4690b3f8b	2206
AnnaBridge	165:d1b4690b3f8b	2207	/**
AnnaBridge	165:d1b4690b3f8b	2208	* @brief Check if HSI48 oscillator Ready
AnnaBridge	165:d1b4690b3f8b	2209	* @rmtoll CRRCR HSI48RDY LL_RCC_HSI48_IsReady
AnnaBridge	165:d1b4690b3f8b	2210	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2211	*/
AnnaBridge	165:d1b4690b3f8b	2212	__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	2213	{
AnnaBridge	165:d1b4690b3f8b	2214	return (READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == (RCC_CRRCR_HSI48RDY));
AnnaBridge	165:d1b4690b3f8b	2215	}
AnnaBridge	165:d1b4690b3f8b	2216
AnnaBridge	165:d1b4690b3f8b	2217	/**
AnnaBridge	165:d1b4690b3f8b	2218	* @brief Get HSI48 Calibration value
AnnaBridge	165:d1b4690b3f8b	2219	* @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
AnnaBridge	165:d1b4690b3f8b	2220	* @retval Between Min_Data = 0x00 and Max_Data = 0x1FF
AnnaBridge	165:d1b4690b3f8b	2221	*/
AnnaBridge	165:d1b4690b3f8b	2222	__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
AnnaBridge	165:d1b4690b3f8b	2223	{
AnnaBridge	165:d1b4690b3f8b	2224	return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
AnnaBridge	165:d1b4690b3f8b	2225	}
AnnaBridge	165:d1b4690b3f8b	2226
AnnaBridge	165:d1b4690b3f8b	2227	/**
AnnaBridge	165:d1b4690b3f8b	2228	* @}
AnnaBridge	165:d1b4690b3f8b	2229	*/
AnnaBridge	165:d1b4690b3f8b	2230	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	2231
AnnaBridge	165:d1b4690b3f8b	2232	/** @defgroup RCC_LL_EF_LSE LSE
AnnaBridge	165:d1b4690b3f8b	2233	* @{
AnnaBridge	165:d1b4690b3f8b	2234	*/
AnnaBridge	165:d1b4690b3f8b	2235
AnnaBridge	165:d1b4690b3f8b	2236	/**
AnnaBridge	165:d1b4690b3f8b	2237	* @brief Enable Low Speed External (LSE) crystal.
AnnaBridge	165:d1b4690b3f8b	2238	* @rmtoll BDCR LSEON LL_RCC_LSE_Enable
AnnaBridge	165:d1b4690b3f8b	2239	* @retval None
AnnaBridge	165:d1b4690b3f8b	2240	*/
AnnaBridge	165:d1b4690b3f8b	2241	__STATIC_INLINE void LL_RCC_LSE_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2242	{
AnnaBridge	165:d1b4690b3f8b	2243	SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	165:d1b4690b3f8b	2244	}
AnnaBridge	165:d1b4690b3f8b	2245
AnnaBridge	165:d1b4690b3f8b	2246	/**
AnnaBridge	165:d1b4690b3f8b	2247	* @brief Disable Low Speed External (LSE) crystal.
AnnaBridge	165:d1b4690b3f8b	2248	* @rmtoll BDCR LSEON LL_RCC_LSE_Disable
AnnaBridge	165:d1b4690b3f8b	2249	* @retval None
AnnaBridge	165:d1b4690b3f8b	2250	*/
AnnaBridge	165:d1b4690b3f8b	2251	__STATIC_INLINE void LL_RCC_LSE_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2252	{
AnnaBridge	165:d1b4690b3f8b	2253	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
AnnaBridge	165:d1b4690b3f8b	2254	}
AnnaBridge	165:d1b4690b3f8b	2255
AnnaBridge	165:d1b4690b3f8b	2256	/**
AnnaBridge	165:d1b4690b3f8b	2257	* @brief Enable external clock source (LSE bypass).
AnnaBridge	165:d1b4690b3f8b	2258	* @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
AnnaBridge	165:d1b4690b3f8b	2259	* @retval None
AnnaBridge	165:d1b4690b3f8b	2260	*/
AnnaBridge	165:d1b4690b3f8b	2261	__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
AnnaBridge	165:d1b4690b3f8b	2262	{
AnnaBridge	165:d1b4690b3f8b	2263	SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	165:d1b4690b3f8b	2264	}
AnnaBridge	165:d1b4690b3f8b	2265
AnnaBridge	165:d1b4690b3f8b	2266	/**
AnnaBridge	165:d1b4690b3f8b	2267	* @brief Disable external clock source (LSE bypass).
AnnaBridge	165:d1b4690b3f8b	2268	* @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
AnnaBridge	165:d1b4690b3f8b	2269	* @retval None
AnnaBridge	165:d1b4690b3f8b	2270	*/
AnnaBridge	165:d1b4690b3f8b	2271	__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
AnnaBridge	165:d1b4690b3f8b	2272	{
AnnaBridge	165:d1b4690b3f8b	2273	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
AnnaBridge	165:d1b4690b3f8b	2274	}
AnnaBridge	165:d1b4690b3f8b	2275
AnnaBridge	165:d1b4690b3f8b	2276	/**
AnnaBridge	165:d1b4690b3f8b	2277	* @brief Set LSE oscillator drive capability
AnnaBridge	165:d1b4690b3f8b	2278	* @note The oscillator is in Xtal mode when it is not in bypass mode.
AnnaBridge	165:d1b4690b3f8b	2279	* @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
AnnaBridge	165:d1b4690b3f8b	2280	* @param LSEDrive This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2281	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	165:d1b4690b3f8b	2282	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	165:d1b4690b3f8b	2283	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	165:d1b4690b3f8b	2284	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	165:d1b4690b3f8b	2285	* @retval None
AnnaBridge	165:d1b4690b3f8b	2286	*/
AnnaBridge	165:d1b4690b3f8b	2287	__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
AnnaBridge	165:d1b4690b3f8b	2288	{
AnnaBridge	165:d1b4690b3f8b	2289	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
AnnaBridge	165:d1b4690b3f8b	2290	}
AnnaBridge	165:d1b4690b3f8b	2291
AnnaBridge	165:d1b4690b3f8b	2292	/**
AnnaBridge	165:d1b4690b3f8b	2293	* @brief Get LSE oscillator drive capability
AnnaBridge	165:d1b4690b3f8b	2294	* @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
AnnaBridge	165:d1b4690b3f8b	2295	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2296	* @arg @ref LL_RCC_LSEDRIVE_LOW
AnnaBridge	165:d1b4690b3f8b	2297	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
AnnaBridge	165:d1b4690b3f8b	2298	* @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
AnnaBridge	165:d1b4690b3f8b	2299	* @arg @ref LL_RCC_LSEDRIVE_HIGH
AnnaBridge	165:d1b4690b3f8b	2300	*/
AnnaBridge	165:d1b4690b3f8b	2301	__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
AnnaBridge	165:d1b4690b3f8b	2302	{
AnnaBridge	165:d1b4690b3f8b	2303	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
AnnaBridge	165:d1b4690b3f8b	2304	}
AnnaBridge	165:d1b4690b3f8b	2305
AnnaBridge	165:d1b4690b3f8b	2306	/**
AnnaBridge	165:d1b4690b3f8b	2307	* @brief Enable Clock security system on LSE.
AnnaBridge	165:d1b4690b3f8b	2308	* @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
AnnaBridge	165:d1b4690b3f8b	2309	* @retval None
AnnaBridge	165:d1b4690b3f8b	2310	*/
AnnaBridge	165:d1b4690b3f8b	2311	__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
AnnaBridge	165:d1b4690b3f8b	2312	{
AnnaBridge	165:d1b4690b3f8b	2313	SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
AnnaBridge	165:d1b4690b3f8b	2314	}
AnnaBridge	165:d1b4690b3f8b	2315
AnnaBridge	165:d1b4690b3f8b	2316	/**
AnnaBridge	165:d1b4690b3f8b	2317	* @brief Disable Clock security system on LSE.
AnnaBridge	165:d1b4690b3f8b	2318	* @note Clock security system can be disabled only after a LSE
AnnaBridge	165:d1b4690b3f8b	2319	* failure detection. In that case it MUST be disabled by software.
AnnaBridge	165:d1b4690b3f8b	2320	* @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS
AnnaBridge	165:d1b4690b3f8b	2321	* @retval None
AnnaBridge	165:d1b4690b3f8b	2322	*/
AnnaBridge	165:d1b4690b3f8b	2323	__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void)
AnnaBridge	165:d1b4690b3f8b	2324	{
AnnaBridge	165:d1b4690b3f8b	2325	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
AnnaBridge	165:d1b4690b3f8b	2326	}
AnnaBridge	165:d1b4690b3f8b	2327
AnnaBridge	165:d1b4690b3f8b	2328	/**
AnnaBridge	165:d1b4690b3f8b	2329	* @brief Check if LSE oscillator Ready
AnnaBridge	165:d1b4690b3f8b	2330	* @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
AnnaBridge	165:d1b4690b3f8b	2331	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2332	*/
AnnaBridge	165:d1b4690b3f8b	2333	__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	2334	{
AnnaBridge	165:d1b4690b3f8b	2335	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
AnnaBridge	165:d1b4690b3f8b	2336	}
AnnaBridge	165:d1b4690b3f8b	2337
AnnaBridge	165:d1b4690b3f8b	2338	/**
AnnaBridge	165:d1b4690b3f8b	2339	* @brief Check if CSS on LSE failure Detection
AnnaBridge	165:d1b4690b3f8b	2340	* @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected
AnnaBridge	165:d1b4690b3f8b	2341	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2342	*/
AnnaBridge	165:d1b4690b3f8b	2343	__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void)
AnnaBridge	165:d1b4690b3f8b	2344	{
AnnaBridge	165:d1b4690b3f8b	2345	return (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD));
AnnaBridge	165:d1b4690b3f8b	2346	}
AnnaBridge	165:d1b4690b3f8b	2347
AnnaBridge	165:d1b4690b3f8b	2348	/**
AnnaBridge	165:d1b4690b3f8b	2349	* @}
AnnaBridge	165:d1b4690b3f8b	2350	*/
AnnaBridge	165:d1b4690b3f8b	2351
AnnaBridge	165:d1b4690b3f8b	2352	/** @defgroup RCC_LL_EF_LSI LSI
AnnaBridge	165:d1b4690b3f8b	2353	* @{
AnnaBridge	165:d1b4690b3f8b	2354	*/
AnnaBridge	165:d1b4690b3f8b	2355
AnnaBridge	165:d1b4690b3f8b	2356	/**
AnnaBridge	165:d1b4690b3f8b	2357	* @brief Enable LSI Oscillator
AnnaBridge	165:d1b4690b3f8b	2358	* @rmtoll CSR LSION LL_RCC_LSI_Enable
AnnaBridge	165:d1b4690b3f8b	2359	* @retval None
AnnaBridge	165:d1b4690b3f8b	2360	*/
AnnaBridge	165:d1b4690b3f8b	2361	__STATIC_INLINE void LL_RCC_LSI_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2362	{
AnnaBridge	165:d1b4690b3f8b	2363	SET_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	165:d1b4690b3f8b	2364	}
AnnaBridge	165:d1b4690b3f8b	2365
AnnaBridge	165:d1b4690b3f8b	2366	/**
AnnaBridge	165:d1b4690b3f8b	2367	* @brief Disable LSI Oscillator
AnnaBridge	165:d1b4690b3f8b	2368	* @rmtoll CSR LSION LL_RCC_LSI_Disable
AnnaBridge	165:d1b4690b3f8b	2369	* @retval None
AnnaBridge	165:d1b4690b3f8b	2370	*/
AnnaBridge	165:d1b4690b3f8b	2371	__STATIC_INLINE void LL_RCC_LSI_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2372	{
AnnaBridge	165:d1b4690b3f8b	2373	CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
AnnaBridge	165:d1b4690b3f8b	2374	}
AnnaBridge	165:d1b4690b3f8b	2375
AnnaBridge	165:d1b4690b3f8b	2376	/**
AnnaBridge	165:d1b4690b3f8b	2377	* @brief Check if LSI is Ready
AnnaBridge	165:d1b4690b3f8b	2378	* @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
AnnaBridge	165:d1b4690b3f8b	2379	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2380	*/
AnnaBridge	165:d1b4690b3f8b	2381	__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	2382	{
AnnaBridge	165:d1b4690b3f8b	2383	return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
AnnaBridge	165:d1b4690b3f8b	2384	}
AnnaBridge	165:d1b4690b3f8b	2385
AnnaBridge	165:d1b4690b3f8b	2386	/**
AnnaBridge	165:d1b4690b3f8b	2387	* @}
AnnaBridge	165:d1b4690b3f8b	2388	*/
AnnaBridge	165:d1b4690b3f8b	2389
AnnaBridge	165:d1b4690b3f8b	2390	/** @defgroup RCC_LL_EF_MSI MSI
AnnaBridge	165:d1b4690b3f8b	2391	* @{
AnnaBridge	165:d1b4690b3f8b	2392	*/
AnnaBridge	165:d1b4690b3f8b	2393
AnnaBridge	165:d1b4690b3f8b	2394	/**
AnnaBridge	165:d1b4690b3f8b	2395	* @brief Enable MSI oscillator
AnnaBridge	165:d1b4690b3f8b	2396	* @rmtoll CR MSION LL_RCC_MSI_Enable
AnnaBridge	165:d1b4690b3f8b	2397	* @retval None
AnnaBridge	165:d1b4690b3f8b	2398	*/
AnnaBridge	165:d1b4690b3f8b	2399	__STATIC_INLINE void LL_RCC_MSI_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2400	{
AnnaBridge	165:d1b4690b3f8b	2401	SET_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	165:d1b4690b3f8b	2402	}
AnnaBridge	165:d1b4690b3f8b	2403
AnnaBridge	165:d1b4690b3f8b	2404	/**
AnnaBridge	165:d1b4690b3f8b	2405	* @brief Disable MSI oscillator
AnnaBridge	165:d1b4690b3f8b	2406	* @rmtoll CR MSION LL_RCC_MSI_Disable
AnnaBridge	165:d1b4690b3f8b	2407	* @retval None
AnnaBridge	165:d1b4690b3f8b	2408	*/
AnnaBridge	165:d1b4690b3f8b	2409	__STATIC_INLINE void LL_RCC_MSI_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2410	{
AnnaBridge	165:d1b4690b3f8b	2411	CLEAR_BIT(RCC->CR, RCC_CR_MSION);
AnnaBridge	165:d1b4690b3f8b	2412	}
AnnaBridge	165:d1b4690b3f8b	2413
AnnaBridge	165:d1b4690b3f8b	2414	/**
AnnaBridge	165:d1b4690b3f8b	2415	* @brief Check if MSI oscillator Ready
AnnaBridge	165:d1b4690b3f8b	2416	* @rmtoll CR MSIRDY LL_RCC_MSI_IsReady
AnnaBridge	165:d1b4690b3f8b	2417	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2418	*/
AnnaBridge	165:d1b4690b3f8b	2419	__STATIC_INLINE uint32_t LL_RCC_MSI_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	2420	{
AnnaBridge	165:d1b4690b3f8b	2421	return (READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY));
AnnaBridge	165:d1b4690b3f8b	2422	}
AnnaBridge	165:d1b4690b3f8b	2423
AnnaBridge	165:d1b4690b3f8b	2424	/**
AnnaBridge	165:d1b4690b3f8b	2425	* @brief Enable MSI PLL-mode (Hardware auto calibration with LSE)
AnnaBridge	165:d1b4690b3f8b	2426	* @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled)
AnnaBridge	165:d1b4690b3f8b	2427	* and ready (LSERDY set by hardware)
AnnaBridge	165:d1b4690b3f8b	2428	* @note hardware protection to avoid enabling MSIPLLEN if LSE is not
AnnaBridge	165:d1b4690b3f8b	2429	* ready
AnnaBridge	165:d1b4690b3f8b	2430	* @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode
AnnaBridge	165:d1b4690b3f8b	2431	* @retval None
AnnaBridge	165:d1b4690b3f8b	2432	*/
AnnaBridge	165:d1b4690b3f8b	2433	__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void)
AnnaBridge	165:d1b4690b3f8b	2434	{
AnnaBridge	165:d1b4690b3f8b	2435	SET_BIT(RCC->CR, RCC_CR_MSIPLLEN);
AnnaBridge	165:d1b4690b3f8b	2436	}
AnnaBridge	165:d1b4690b3f8b	2437
AnnaBridge	165:d1b4690b3f8b	2438	/**
AnnaBridge	165:d1b4690b3f8b	2439	* @brief Disable MSI-PLL mode
AnnaBridge	165:d1b4690b3f8b	2440	* @note cleared by hardware when LSE is disabled (LSEON = 0) or when
AnnaBridge	165:d1b4690b3f8b	2441	* the Clock Security System on LSE detects a LSE failure
AnnaBridge	165:d1b4690b3f8b	2442	* @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode
AnnaBridge	165:d1b4690b3f8b	2443	* @retval None
AnnaBridge	165:d1b4690b3f8b	2444	*/
AnnaBridge	165:d1b4690b3f8b	2445	__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void)
AnnaBridge	165:d1b4690b3f8b	2446	{
AnnaBridge	165:d1b4690b3f8b	2447	CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN);
AnnaBridge	165:d1b4690b3f8b	2448	}
AnnaBridge	165:d1b4690b3f8b	2449
AnnaBridge	165:d1b4690b3f8b	2450	/**
AnnaBridge	165:d1b4690b3f8b	2451	* @brief Enable MSI clock range selection with MSIRANGE register
AnnaBridge	165:d1b4690b3f8b	2452	* @note Write 0 has no effect. After a standby or a reset
AnnaBridge	165:d1b4690b3f8b	2453	* MSIRGSEL is at 0 and the MSI range value is provided by
AnnaBridge	165:d1b4690b3f8b	2454	* MSISRANGE
AnnaBridge	165:d1b4690b3f8b	2455	* @rmtoll CR MSIRGSEL LL_RCC_MSI_EnableRangeSelection
AnnaBridge	165:d1b4690b3f8b	2456	* @retval None
AnnaBridge	165:d1b4690b3f8b	2457	*/
AnnaBridge	165:d1b4690b3f8b	2458	__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void)
AnnaBridge	165:d1b4690b3f8b	2459	{
AnnaBridge	165:d1b4690b3f8b	2460	SET_BIT(RCC->CR, RCC_CR_MSIRGSEL);
AnnaBridge	165:d1b4690b3f8b	2461	}
AnnaBridge	165:d1b4690b3f8b	2462
AnnaBridge	165:d1b4690b3f8b	2463	/**
AnnaBridge	165:d1b4690b3f8b	2464	* @brief Check if MSI clock range is selected with MSIRANGE register
AnnaBridge	165:d1b4690b3f8b	2465	* @rmtoll CR MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect
AnnaBridge	165:d1b4690b3f8b	2466	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	2467	*/
AnnaBridge	165:d1b4690b3f8b	2468	__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void)
AnnaBridge	165:d1b4690b3f8b	2469	{
AnnaBridge	165:d1b4690b3f8b	2470	return (READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL));
AnnaBridge	165:d1b4690b3f8b	2471	}
AnnaBridge	165:d1b4690b3f8b	2472
AnnaBridge	165:d1b4690b3f8b	2473	/**
AnnaBridge	165:d1b4690b3f8b	2474	* @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	165:d1b4690b3f8b	2475	* @rmtoll CR MSIRANGE LL_RCC_MSI_SetRange
AnnaBridge	165:d1b4690b3f8b	2476	* @param Range This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2477	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	165:d1b4690b3f8b	2478	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	165:d1b4690b3f8b	2479	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	165:d1b4690b3f8b	2480	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	165:d1b4690b3f8b	2481	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	165:d1b4690b3f8b	2482	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	165:d1b4690b3f8b	2483	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	165:d1b4690b3f8b	2484	* @arg @ref LL_RCC_MSIRANGE_7
AnnaBridge	165:d1b4690b3f8b	2485	* @arg @ref LL_RCC_MSIRANGE_8
AnnaBridge	165:d1b4690b3f8b	2486	* @arg @ref LL_RCC_MSIRANGE_9
AnnaBridge	165:d1b4690b3f8b	2487	* @arg @ref LL_RCC_MSIRANGE_10
AnnaBridge	165:d1b4690b3f8b	2488	* @arg @ref LL_RCC_MSIRANGE_11
AnnaBridge	165:d1b4690b3f8b	2489	* @retval None
AnnaBridge	165:d1b4690b3f8b	2490	*/
AnnaBridge	165:d1b4690b3f8b	2491	__STATIC_INLINE void LL_RCC_MSI_SetRange(uint32_t Range)
AnnaBridge	165:d1b4690b3f8b	2492	{
AnnaBridge	165:d1b4690b3f8b	2493	MODIFY_REG(RCC->CR, RCC_CR_MSIRANGE, Range);
AnnaBridge	165:d1b4690b3f8b	2494	}
AnnaBridge	165:d1b4690b3f8b	2495
AnnaBridge	165:d1b4690b3f8b	2496	/**
AnnaBridge	165:d1b4690b3f8b	2497	* @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode.
AnnaBridge	165:d1b4690b3f8b	2498	* @rmtoll CR MSIRANGE LL_RCC_MSI_GetRange
AnnaBridge	165:d1b4690b3f8b	2499	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2500	* @arg @ref LL_RCC_MSIRANGE_0
AnnaBridge	165:d1b4690b3f8b	2501	* @arg @ref LL_RCC_MSIRANGE_1
AnnaBridge	165:d1b4690b3f8b	2502	* @arg @ref LL_RCC_MSIRANGE_2
AnnaBridge	165:d1b4690b3f8b	2503	* @arg @ref LL_RCC_MSIRANGE_3
AnnaBridge	165:d1b4690b3f8b	2504	* @arg @ref LL_RCC_MSIRANGE_4
AnnaBridge	165:d1b4690b3f8b	2505	* @arg @ref LL_RCC_MSIRANGE_5
AnnaBridge	165:d1b4690b3f8b	2506	* @arg @ref LL_RCC_MSIRANGE_6
AnnaBridge	165:d1b4690b3f8b	2507	* @arg @ref LL_RCC_MSIRANGE_7
AnnaBridge	165:d1b4690b3f8b	2508	* @arg @ref LL_RCC_MSIRANGE_8
AnnaBridge	165:d1b4690b3f8b	2509	* @arg @ref LL_RCC_MSIRANGE_9
AnnaBridge	165:d1b4690b3f8b	2510	* @arg @ref LL_RCC_MSIRANGE_10
AnnaBridge	165:d1b4690b3f8b	2511	* @arg @ref LL_RCC_MSIRANGE_11
AnnaBridge	165:d1b4690b3f8b	2512	*/
AnnaBridge	165:d1b4690b3f8b	2513	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRange(void)
AnnaBridge	165:d1b4690b3f8b	2514	{
AnnaBridge	165:d1b4690b3f8b	2515	return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE));
AnnaBridge	165:d1b4690b3f8b	2516	}
AnnaBridge	165:d1b4690b3f8b	2517
AnnaBridge	165:d1b4690b3f8b	2518	/**
AnnaBridge	165:d1b4690b3f8b	2519	* @brief Configure MSI range used after standby
AnnaBridge	165:d1b4690b3f8b	2520	* @rmtoll CSR MSISRANGE LL_RCC_MSI_SetRangeAfterStandby
AnnaBridge	165:d1b4690b3f8b	2521	* @param Range This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2522	* @arg @ref LL_RCC_MSISRANGE_4
AnnaBridge	165:d1b4690b3f8b	2523	* @arg @ref LL_RCC_MSISRANGE_5
AnnaBridge	165:d1b4690b3f8b	2524	* @arg @ref LL_RCC_MSISRANGE_6
AnnaBridge	165:d1b4690b3f8b	2525	* @arg @ref LL_RCC_MSISRANGE_7
AnnaBridge	165:d1b4690b3f8b	2526	* @retval None
AnnaBridge	165:d1b4690b3f8b	2527	*/
AnnaBridge	165:d1b4690b3f8b	2528	__STATIC_INLINE void LL_RCC_MSI_SetRangeAfterStandby(uint32_t Range)
AnnaBridge	165:d1b4690b3f8b	2529	{
AnnaBridge	165:d1b4690b3f8b	2530	MODIFY_REG(RCC->CSR, RCC_CSR_MSISRANGE, Range);
AnnaBridge	165:d1b4690b3f8b	2531	}
AnnaBridge	165:d1b4690b3f8b	2532
AnnaBridge	165:d1b4690b3f8b	2533	/**
AnnaBridge	165:d1b4690b3f8b	2534	* @brief Get MSI range used after standby
AnnaBridge	165:d1b4690b3f8b	2535	* @rmtoll CSR MSISRANGE LL_RCC_MSI_GetRangeAfterStandby
AnnaBridge	165:d1b4690b3f8b	2536	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2537	* @arg @ref LL_RCC_MSISRANGE_4
AnnaBridge	165:d1b4690b3f8b	2538	* @arg @ref LL_RCC_MSISRANGE_5
AnnaBridge	165:d1b4690b3f8b	2539	* @arg @ref LL_RCC_MSISRANGE_6
AnnaBridge	165:d1b4690b3f8b	2540	* @arg @ref LL_RCC_MSISRANGE_7
AnnaBridge	165:d1b4690b3f8b	2541	*/
AnnaBridge	165:d1b4690b3f8b	2542	__STATIC_INLINE uint32_t LL_RCC_MSI_GetRangeAfterStandby(void)
AnnaBridge	165:d1b4690b3f8b	2543	{
AnnaBridge	165:d1b4690b3f8b	2544	return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE));
AnnaBridge	165:d1b4690b3f8b	2545	}
AnnaBridge	165:d1b4690b3f8b	2546
AnnaBridge	165:d1b4690b3f8b	2547	/**
AnnaBridge	165:d1b4690b3f8b	2548	* @brief Get MSI Calibration value
AnnaBridge	165:d1b4690b3f8b	2549	* @note When MSITRIM is written, MSICAL is updated with the sum of
AnnaBridge	165:d1b4690b3f8b	2550	* MSITRIM and the factory trim value
AnnaBridge	165:d1b4690b3f8b	2551	* @rmtoll ICSCR MSICAL LL_RCC_MSI_GetCalibration
AnnaBridge	165:d1b4690b3f8b	2552	* @retval Between Min_Data = 0 and Max_Data = 255
AnnaBridge	165:d1b4690b3f8b	2553	*/
AnnaBridge	165:d1b4690b3f8b	2554	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(void)
AnnaBridge	165:d1b4690b3f8b	2555	{
AnnaBridge	165:d1b4690b3f8b	2556	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSICAL) >> RCC_ICSCR_MSICAL_Pos);
AnnaBridge	165:d1b4690b3f8b	2557	}
AnnaBridge	165:d1b4690b3f8b	2558
AnnaBridge	165:d1b4690b3f8b	2559	/**
AnnaBridge	165:d1b4690b3f8b	2560	* @brief Set MSI Calibration trimming
AnnaBridge	165:d1b4690b3f8b	2561	* @note user-programmable trimming value that is added to the MSICAL
AnnaBridge	165:d1b4690b3f8b	2562	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_SetCalibTrimming
AnnaBridge	165:d1b4690b3f8b	2563	* @param Value Between Min_Data = 0 and Max_Data = 255
AnnaBridge	165:d1b4690b3f8b	2564	* @retval None
AnnaBridge	165:d1b4690b3f8b	2565	*/
AnnaBridge	165:d1b4690b3f8b	2566	__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value)
AnnaBridge	165:d1b4690b3f8b	2567	{
AnnaBridge	165:d1b4690b3f8b	2568	MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos);
AnnaBridge	165:d1b4690b3f8b	2569	}
AnnaBridge	165:d1b4690b3f8b	2570
AnnaBridge	165:d1b4690b3f8b	2571	/**
AnnaBridge	165:d1b4690b3f8b	2572	* @brief Get MSI Calibration trimming
AnnaBridge	165:d1b4690b3f8b	2573	* @rmtoll ICSCR MSITRIM LL_RCC_MSI_GetCalibTrimming
AnnaBridge	165:d1b4690b3f8b	2574	* @retval Between 0 and 255
AnnaBridge	165:d1b4690b3f8b	2575	*/
AnnaBridge	165:d1b4690b3f8b	2576	__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(void)
AnnaBridge	165:d1b4690b3f8b	2577	{
AnnaBridge	165:d1b4690b3f8b	2578	return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_MSITRIM) >> RCC_ICSCR_MSITRIM_Pos);
AnnaBridge	165:d1b4690b3f8b	2579	}
AnnaBridge	165:d1b4690b3f8b	2580
AnnaBridge	165:d1b4690b3f8b	2581	/**
AnnaBridge	165:d1b4690b3f8b	2582	* @}
AnnaBridge	165:d1b4690b3f8b	2583	*/
AnnaBridge	165:d1b4690b3f8b	2584
AnnaBridge	165:d1b4690b3f8b	2585	/** @defgroup RCC_LL_EF_LSCO LSCO
AnnaBridge	165:d1b4690b3f8b	2586	* @{
AnnaBridge	165:d1b4690b3f8b	2587	*/
AnnaBridge	165:d1b4690b3f8b	2588
AnnaBridge	165:d1b4690b3f8b	2589	/**
AnnaBridge	165:d1b4690b3f8b	2590	* @brief Enable Low speed clock
AnnaBridge	165:d1b4690b3f8b	2591	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable
AnnaBridge	165:d1b4690b3f8b	2592	* @retval None
AnnaBridge	165:d1b4690b3f8b	2593	*/
AnnaBridge	165:d1b4690b3f8b	2594	__STATIC_INLINE void LL_RCC_LSCO_Enable(void)
AnnaBridge	165:d1b4690b3f8b	2595	{
AnnaBridge	165:d1b4690b3f8b	2596	SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
AnnaBridge	165:d1b4690b3f8b	2597	}
AnnaBridge	165:d1b4690b3f8b	2598
AnnaBridge	165:d1b4690b3f8b	2599	/**
AnnaBridge	165:d1b4690b3f8b	2600	* @brief Disable Low speed clock
AnnaBridge	165:d1b4690b3f8b	2601	* @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable
AnnaBridge	165:d1b4690b3f8b	2602	* @retval None
AnnaBridge	165:d1b4690b3f8b	2603	*/
AnnaBridge	165:d1b4690b3f8b	2604	__STATIC_INLINE void LL_RCC_LSCO_Disable(void)
AnnaBridge	165:d1b4690b3f8b	2605	{
AnnaBridge	165:d1b4690b3f8b	2606	CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN);
AnnaBridge	165:d1b4690b3f8b	2607	}
AnnaBridge	165:d1b4690b3f8b	2608
AnnaBridge	165:d1b4690b3f8b	2609	/**
AnnaBridge	165:d1b4690b3f8b	2610	* @brief Configure Low speed clock selection
AnnaBridge	165:d1b4690b3f8b	2611	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource
AnnaBridge	165:d1b4690b3f8b	2612	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2613	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	2614	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2615	* @retval None
AnnaBridge	165:d1b4690b3f8b	2616	*/
AnnaBridge	165:d1b4690b3f8b	2617	__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	2618	{
AnnaBridge	165:d1b4690b3f8b	2619	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source);
AnnaBridge	165:d1b4690b3f8b	2620	}
AnnaBridge	165:d1b4690b3f8b	2621
AnnaBridge	165:d1b4690b3f8b	2622	/**
AnnaBridge	165:d1b4690b3f8b	2623	* @brief Get Low speed clock selection
AnnaBridge	165:d1b4690b3f8b	2624	* @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource
AnnaBridge	165:d1b4690b3f8b	2625	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2626	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	2627	* @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2628	*/
AnnaBridge	165:d1b4690b3f8b	2629	__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void)
AnnaBridge	165:d1b4690b3f8b	2630	{
AnnaBridge	165:d1b4690b3f8b	2631	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL));
AnnaBridge	165:d1b4690b3f8b	2632	}
AnnaBridge	165:d1b4690b3f8b	2633
AnnaBridge	165:d1b4690b3f8b	2634	/**
AnnaBridge	165:d1b4690b3f8b	2635	* @}
AnnaBridge	165:d1b4690b3f8b	2636	*/
AnnaBridge	165:d1b4690b3f8b	2637
AnnaBridge	165:d1b4690b3f8b	2638	/** @defgroup RCC_LL_EF_System System
AnnaBridge	165:d1b4690b3f8b	2639	* @{
AnnaBridge	165:d1b4690b3f8b	2640	*/
AnnaBridge	165:d1b4690b3f8b	2641
AnnaBridge	165:d1b4690b3f8b	2642	/**
AnnaBridge	165:d1b4690b3f8b	2643	* @brief Configure the system clock source
AnnaBridge	165:d1b4690b3f8b	2644	* @rmtoll CFGR SW LL_RCC_SetSysClkSource
AnnaBridge	165:d1b4690b3f8b	2645	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2646	* @arg @ref LL_RCC_SYS_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	2647	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2648	* @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	2649	* @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	2650	* @retval None
AnnaBridge	165:d1b4690b3f8b	2651	*/
AnnaBridge	165:d1b4690b3f8b	2652	__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	2653	{
AnnaBridge	165:d1b4690b3f8b	2654	MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
AnnaBridge	165:d1b4690b3f8b	2655	}
AnnaBridge	165:d1b4690b3f8b	2656
AnnaBridge	165:d1b4690b3f8b	2657	/**
AnnaBridge	165:d1b4690b3f8b	2658	* @brief Get the system clock source
AnnaBridge	165:d1b4690b3f8b	2659	* @rmtoll CFGR SWS LL_RCC_GetSysClkSource
AnnaBridge	165:d1b4690b3f8b	2660	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2661	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSI
AnnaBridge	165:d1b4690b3f8b	2662	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
AnnaBridge	165:d1b4690b3f8b	2663	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
AnnaBridge	165:d1b4690b3f8b	2664	* @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
AnnaBridge	165:d1b4690b3f8b	2665	*/
AnnaBridge	165:d1b4690b3f8b	2666	__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
AnnaBridge	165:d1b4690b3f8b	2667	{
AnnaBridge	165:d1b4690b3f8b	2668	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
AnnaBridge	165:d1b4690b3f8b	2669	}
AnnaBridge	165:d1b4690b3f8b	2670
AnnaBridge	165:d1b4690b3f8b	2671	/**
AnnaBridge	165:d1b4690b3f8b	2672	* @brief Set AHB prescaler
AnnaBridge	165:d1b4690b3f8b	2673	* @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
AnnaBridge	165:d1b4690b3f8b	2674	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2675	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	165:d1b4690b3f8b	2676	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	165:d1b4690b3f8b	2677	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	165:d1b4690b3f8b	2678	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	165:d1b4690b3f8b	2679	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	165:d1b4690b3f8b	2680	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	165:d1b4690b3f8b	2681	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	165:d1b4690b3f8b	2682	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	165:d1b4690b3f8b	2683	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	165:d1b4690b3f8b	2684	* @retval None
AnnaBridge	165:d1b4690b3f8b	2685	*/
AnnaBridge	165:d1b4690b3f8b	2686	__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
AnnaBridge	165:d1b4690b3f8b	2687	{
AnnaBridge	165:d1b4690b3f8b	2688	MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
AnnaBridge	165:d1b4690b3f8b	2689	}
AnnaBridge	165:d1b4690b3f8b	2690
AnnaBridge	165:d1b4690b3f8b	2691	/**
AnnaBridge	165:d1b4690b3f8b	2692	* @brief Set APB1 prescaler
AnnaBridge	165:d1b4690b3f8b	2693	* @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
AnnaBridge	165:d1b4690b3f8b	2694	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2695	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	165:d1b4690b3f8b	2696	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	165:d1b4690b3f8b	2697	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	165:d1b4690b3f8b	2698	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	165:d1b4690b3f8b	2699	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	165:d1b4690b3f8b	2700	* @retval None
AnnaBridge	165:d1b4690b3f8b	2701	*/
AnnaBridge	165:d1b4690b3f8b	2702	__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
AnnaBridge	165:d1b4690b3f8b	2703	{
AnnaBridge	165:d1b4690b3f8b	2704	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
AnnaBridge	165:d1b4690b3f8b	2705	}
AnnaBridge	165:d1b4690b3f8b	2706
AnnaBridge	165:d1b4690b3f8b	2707	/**
AnnaBridge	165:d1b4690b3f8b	2708	* @brief Set APB2 prescaler
AnnaBridge	165:d1b4690b3f8b	2709	* @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
AnnaBridge	165:d1b4690b3f8b	2710	* @param Prescaler This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2711	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	165:d1b4690b3f8b	2712	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	165:d1b4690b3f8b	2713	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	165:d1b4690b3f8b	2714	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	165:d1b4690b3f8b	2715	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	165:d1b4690b3f8b	2716	* @retval None
AnnaBridge	165:d1b4690b3f8b	2717	*/
AnnaBridge	165:d1b4690b3f8b	2718	__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
AnnaBridge	165:d1b4690b3f8b	2719	{
AnnaBridge	165:d1b4690b3f8b	2720	MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
AnnaBridge	165:d1b4690b3f8b	2721	}
AnnaBridge	165:d1b4690b3f8b	2722
AnnaBridge	165:d1b4690b3f8b	2723	/**
AnnaBridge	165:d1b4690b3f8b	2724	* @brief Get AHB prescaler
AnnaBridge	165:d1b4690b3f8b	2725	* @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
AnnaBridge	165:d1b4690b3f8b	2726	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2727	* @arg @ref LL_RCC_SYSCLK_DIV_1
AnnaBridge	165:d1b4690b3f8b	2728	* @arg @ref LL_RCC_SYSCLK_DIV_2
AnnaBridge	165:d1b4690b3f8b	2729	* @arg @ref LL_RCC_SYSCLK_DIV_4
AnnaBridge	165:d1b4690b3f8b	2730	* @arg @ref LL_RCC_SYSCLK_DIV_8
AnnaBridge	165:d1b4690b3f8b	2731	* @arg @ref LL_RCC_SYSCLK_DIV_16
AnnaBridge	165:d1b4690b3f8b	2732	* @arg @ref LL_RCC_SYSCLK_DIV_64
AnnaBridge	165:d1b4690b3f8b	2733	* @arg @ref LL_RCC_SYSCLK_DIV_128
AnnaBridge	165:d1b4690b3f8b	2734	* @arg @ref LL_RCC_SYSCLK_DIV_256
AnnaBridge	165:d1b4690b3f8b	2735	* @arg @ref LL_RCC_SYSCLK_DIV_512
AnnaBridge	165:d1b4690b3f8b	2736	*/
AnnaBridge	165:d1b4690b3f8b	2737	__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
AnnaBridge	165:d1b4690b3f8b	2738	{
AnnaBridge	165:d1b4690b3f8b	2739	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
AnnaBridge	165:d1b4690b3f8b	2740	}
AnnaBridge	165:d1b4690b3f8b	2741
AnnaBridge	165:d1b4690b3f8b	2742	/**
AnnaBridge	165:d1b4690b3f8b	2743	* @brief Get APB1 prescaler
AnnaBridge	165:d1b4690b3f8b	2744	* @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
AnnaBridge	165:d1b4690b3f8b	2745	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2746	* @arg @ref LL_RCC_APB1_DIV_1
AnnaBridge	165:d1b4690b3f8b	2747	* @arg @ref LL_RCC_APB1_DIV_2
AnnaBridge	165:d1b4690b3f8b	2748	* @arg @ref LL_RCC_APB1_DIV_4
AnnaBridge	165:d1b4690b3f8b	2749	* @arg @ref LL_RCC_APB1_DIV_8
AnnaBridge	165:d1b4690b3f8b	2750	* @arg @ref LL_RCC_APB1_DIV_16
AnnaBridge	165:d1b4690b3f8b	2751	*/
AnnaBridge	165:d1b4690b3f8b	2752	__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
AnnaBridge	165:d1b4690b3f8b	2753	{
AnnaBridge	165:d1b4690b3f8b	2754	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
AnnaBridge	165:d1b4690b3f8b	2755	}
AnnaBridge	165:d1b4690b3f8b	2756
AnnaBridge	165:d1b4690b3f8b	2757	/**
AnnaBridge	165:d1b4690b3f8b	2758	* @brief Get APB2 prescaler
AnnaBridge	165:d1b4690b3f8b	2759	* @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
AnnaBridge	165:d1b4690b3f8b	2760	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2761	* @arg @ref LL_RCC_APB2_DIV_1
AnnaBridge	165:d1b4690b3f8b	2762	* @arg @ref LL_RCC_APB2_DIV_2
AnnaBridge	165:d1b4690b3f8b	2763	* @arg @ref LL_RCC_APB2_DIV_4
AnnaBridge	165:d1b4690b3f8b	2764	* @arg @ref LL_RCC_APB2_DIV_8
AnnaBridge	165:d1b4690b3f8b	2765	* @arg @ref LL_RCC_APB2_DIV_16
AnnaBridge	165:d1b4690b3f8b	2766	*/
AnnaBridge	165:d1b4690b3f8b	2767	__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
AnnaBridge	165:d1b4690b3f8b	2768	{
AnnaBridge	165:d1b4690b3f8b	2769	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
AnnaBridge	165:d1b4690b3f8b	2770	}
AnnaBridge	165:d1b4690b3f8b	2771
AnnaBridge	165:d1b4690b3f8b	2772	/**
AnnaBridge	165:d1b4690b3f8b	2773	* @brief Set Clock After Wake-Up From Stop mode
AnnaBridge	165:d1b4690b3f8b	2774	* @rmtoll CFGR STOPWUCK LL_RCC_SetClkAfterWakeFromStop
AnnaBridge	165:d1b4690b3f8b	2775	* @param Clock This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2776	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	165:d1b4690b3f8b	2777	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	165:d1b4690b3f8b	2778	* @retval None
AnnaBridge	165:d1b4690b3f8b	2779	*/
AnnaBridge	165:d1b4690b3f8b	2780	__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock)
AnnaBridge	165:d1b4690b3f8b	2781	{
AnnaBridge	165:d1b4690b3f8b	2782	MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock);
AnnaBridge	165:d1b4690b3f8b	2783	}
AnnaBridge	165:d1b4690b3f8b	2784
AnnaBridge	165:d1b4690b3f8b	2785	/**
AnnaBridge	165:d1b4690b3f8b	2786	* @brief Get Clock After Wake-Up From Stop mode
AnnaBridge	165:d1b4690b3f8b	2787	* @rmtoll CFGR STOPWUCK LL_RCC_GetClkAfterWakeFromStop
AnnaBridge	165:d1b4690b3f8b	2788	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2789	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSI
AnnaBridge	165:d1b4690b3f8b	2790	* @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI
AnnaBridge	165:d1b4690b3f8b	2791	*/
AnnaBridge	165:d1b4690b3f8b	2792	__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void)
AnnaBridge	165:d1b4690b3f8b	2793	{
AnnaBridge	165:d1b4690b3f8b	2794	return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
AnnaBridge	165:d1b4690b3f8b	2795	}
AnnaBridge	165:d1b4690b3f8b	2796
AnnaBridge	165:d1b4690b3f8b	2797	/**
AnnaBridge	165:d1b4690b3f8b	2798	* @}
AnnaBridge	165:d1b4690b3f8b	2799	*/
AnnaBridge	165:d1b4690b3f8b	2800
AnnaBridge	165:d1b4690b3f8b	2801	/** @defgroup RCC_LL_EF_MCO MCO
AnnaBridge	165:d1b4690b3f8b	2802	* @{
AnnaBridge	165:d1b4690b3f8b	2803	*/
AnnaBridge	165:d1b4690b3f8b	2804
AnnaBridge	165:d1b4690b3f8b	2805	/**
AnnaBridge	165:d1b4690b3f8b	2806	* @brief Configure MCOx
AnnaBridge	165:d1b4690b3f8b	2807	* @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n
AnnaBridge	165:d1b4690b3f8b	2808	* CFGR MCOPRE LL_RCC_ConfigMCO
AnnaBridge	165:d1b4690b3f8b	2809	* @param MCOxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2810	* @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK
AnnaBridge	165:d1b4690b3f8b	2811	* @arg @ref LL_RCC_MCO1SOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2812	* @arg @ref LL_RCC_MCO1SOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	2813	* @arg @ref LL_RCC_MCO1SOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2814	* @arg @ref LL_RCC_MCO1SOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	2815	* @arg @ref LL_RCC_MCO1SOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	2816	* @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
AnnaBridge	165:d1b4690b3f8b	2817	* @arg @ref LL_RCC_MCO1SOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	2818	* @arg @ref LL_RCC_MCO1SOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2819	*
AnnaBridge	165:d1b4690b3f8b	2820	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	2821	* @param MCOxPrescaler This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2822	* @arg @ref LL_RCC_MCO1_DIV_1
AnnaBridge	165:d1b4690b3f8b	2823	* @arg @ref LL_RCC_MCO1_DIV_2
AnnaBridge	165:d1b4690b3f8b	2824	* @arg @ref LL_RCC_MCO1_DIV_4
AnnaBridge	165:d1b4690b3f8b	2825	* @arg @ref LL_RCC_MCO1_DIV_8
AnnaBridge	165:d1b4690b3f8b	2826	* @arg @ref LL_RCC_MCO1_DIV_16
AnnaBridge	165:d1b4690b3f8b	2827	* @retval None
AnnaBridge	165:d1b4690b3f8b	2828	*/
AnnaBridge	165:d1b4690b3f8b	2829	__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
AnnaBridge	165:d1b4690b3f8b	2830	{
AnnaBridge	165:d1b4690b3f8b	2831	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL \| RCC_CFGR_MCOPRE, MCOxSource \| MCOxPrescaler);
AnnaBridge	165:d1b4690b3f8b	2832	}
AnnaBridge	165:d1b4690b3f8b	2833
AnnaBridge	165:d1b4690b3f8b	2834	/**
AnnaBridge	165:d1b4690b3f8b	2835	* @}
AnnaBridge	165:d1b4690b3f8b	2836	*/
AnnaBridge	165:d1b4690b3f8b	2837
AnnaBridge	165:d1b4690b3f8b	2838	/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
AnnaBridge	165:d1b4690b3f8b	2839	* @{
AnnaBridge	165:d1b4690b3f8b	2840	*/
AnnaBridge	165:d1b4690b3f8b	2841
AnnaBridge	165:d1b4690b3f8b	2842	/**
AnnaBridge	165:d1b4690b3f8b	2843	* @brief Configure USARTx clock source
AnnaBridge	165:d1b4690b3f8b	2844	* @rmtoll CCIPR USARTxSEL LL_RCC_SetUSARTClockSource
AnnaBridge	165:d1b4690b3f8b	2845	* @param USARTxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2846	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
AnnaBridge	165:d1b4690b3f8b	2847	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2848	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2849	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2850	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2851	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2852	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2853	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2854	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
AnnaBridge	165:d1b4690b3f8b	2855	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
AnnaBridge	165:d1b4690b3f8b	2856	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
AnnaBridge	165:d1b4690b3f8b	2857	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
AnnaBridge	165:d1b4690b3f8b	2858	*
AnnaBridge	165:d1b4690b3f8b	2859	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	2860	* @retval None
AnnaBridge	165:d1b4690b3f8b	2861	*/
AnnaBridge	165:d1b4690b3f8b	2862	__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
AnnaBridge	165:d1b4690b3f8b	2863	{
AnnaBridge	165:d1b4690b3f8b	2864	MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFF));
AnnaBridge	165:d1b4690b3f8b	2865	}
AnnaBridge	165:d1b4690b3f8b	2866
AnnaBridge	165:d1b4690b3f8b	2867	#if defined(UART4) \|\| defined(UART5)
AnnaBridge	165:d1b4690b3f8b	2868	/**
AnnaBridge	165:d1b4690b3f8b	2869	* @brief Configure UARTx clock source
AnnaBridge	165:d1b4690b3f8b	2870	* @rmtoll CCIPR UARTxSEL LL_RCC_SetUARTClockSource
AnnaBridge	165:d1b4690b3f8b	2871	* @param UARTxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2872	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2873	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2874	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2875	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2876	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2877	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2878	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2879	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2880	* @retval None
AnnaBridge	165:d1b4690b3f8b	2881	*/
AnnaBridge	165:d1b4690b3f8b	2882	__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
AnnaBridge	165:d1b4690b3f8b	2883	{
AnnaBridge	165:d1b4690b3f8b	2884	MODIFY_REG(RCC->CCIPR, (UARTxSource >> 16), (UARTxSource & 0x0000FFFF));
AnnaBridge	165:d1b4690b3f8b	2885	}
AnnaBridge	165:d1b4690b3f8b	2886	#endif /* UART4 \|\| UART5 */
AnnaBridge	165:d1b4690b3f8b	2887
AnnaBridge	165:d1b4690b3f8b	2888	/**
AnnaBridge	165:d1b4690b3f8b	2889	* @brief Configure LPUART1x clock source
AnnaBridge	165:d1b4690b3f8b	2890	* @rmtoll CCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
AnnaBridge	165:d1b4690b3f8b	2891	* @param LPUARTxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2892	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2893	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2894	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2895	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2896	* @retval None
AnnaBridge	165:d1b4690b3f8b	2897	*/
AnnaBridge	165:d1b4690b3f8b	2898	__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource)
AnnaBridge	165:d1b4690b3f8b	2899	{
AnnaBridge	165:d1b4690b3f8b	2900	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource);
AnnaBridge	165:d1b4690b3f8b	2901	}
AnnaBridge	165:d1b4690b3f8b	2902
AnnaBridge	165:d1b4690b3f8b	2903	/**
AnnaBridge	165:d1b4690b3f8b	2904	* @brief Configure I2Cx clock source
AnnaBridge	165:d1b4690b3f8b	2905	* @rmtoll CCIPR I2CxSEL LL_RCC_SetI2CClockSource
AnnaBridge	165:d1b4690b3f8b	2906	* @param I2CxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2907	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2908	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2909	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2910	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
AnnaBridge	165:d1b4690b3f8b	2911	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
AnnaBridge	165:d1b4690b3f8b	2912	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
AnnaBridge	165:d1b4690b3f8b	2913	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2914	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	2915	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2916	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	165:d1b4690b3f8b	2917	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	165:d1b4690b3f8b	2918	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
AnnaBridge	165:d1b4690b3f8b	2919	*
AnnaBridge	165:d1b4690b3f8b	2920	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	2921	* @retval None
AnnaBridge	165:d1b4690b3f8b	2922	*/
AnnaBridge	165:d1b4690b3f8b	2923	__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
AnnaBridge	165:d1b4690b3f8b	2924	{
AnnaBridge	165:d1b4690b3f8b	2925	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2CxSource >> 24U));
AnnaBridge	165:d1b4690b3f8b	2926	MODIFY_REG(*reg, 3U << ((I2CxSource & 0x00FF0000U) >> 16U), ((I2CxSource & 0x000000FFU) << ((I2CxSource & 0x00FF0000U) >> 16U)));
AnnaBridge	165:d1b4690b3f8b	2927	}
AnnaBridge	165:d1b4690b3f8b	2928
AnnaBridge	165:d1b4690b3f8b	2929	/**
AnnaBridge	165:d1b4690b3f8b	2930	* @brief Configure LPTIMx clock source
AnnaBridge	165:d1b4690b3f8b	2931	* @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource
AnnaBridge	165:d1b4690b3f8b	2932	* @param LPTIMxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2933	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2934	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	2935	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2936	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2937	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	2938	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	2939	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	2940	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	2941	* @retval None
AnnaBridge	165:d1b4690b3f8b	2942	*/
AnnaBridge	165:d1b4690b3f8b	2943	__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
AnnaBridge	165:d1b4690b3f8b	2944	{
AnnaBridge	165:d1b4690b3f8b	2945	MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U));
AnnaBridge	165:d1b4690b3f8b	2946	}
AnnaBridge	165:d1b4690b3f8b	2947
AnnaBridge	165:d1b4690b3f8b	2948	/**
AnnaBridge	165:d1b4690b3f8b	2949	* @brief Configure SAIx clock source
AnnaBridge	165:d1b4690b3f8b	2950	@if STM32L4S9xx
AnnaBridge	165:d1b4690b3f8b	2951	* @rmtoll CCIPR2 SAIxSEL LL_RCC_SetSAIClockSource
AnnaBridge	165:d1b4690b3f8b	2952	@else
AnnaBridge	165:d1b4690b3f8b	2953	* @rmtoll CCIPR SAIxSEL LL_RCC_SetSAIClockSource
AnnaBridge	165:d1b4690b3f8b	2954	@endif
AnnaBridge	165:d1b4690b3f8b	2955	* @param SAIxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2956	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	2957	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	165:d1b4690b3f8b	2958	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	2959	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
AnnaBridge	165:d1b4690b3f8b	2960	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	165:d1b4690b3f8b	2961	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	165:d1b4690b3f8b	2962	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
AnnaBridge	165:d1b4690b3f8b	2963	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
AnnaBridge	165:d1b4690b3f8b	2964	*
AnnaBridge	165:d1b4690b3f8b	2965	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	2966	* @retval None
AnnaBridge	165:d1b4690b3f8b	2967	*/
AnnaBridge	165:d1b4690b3f8b	2968	__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
AnnaBridge	165:d1b4690b3f8b	2969	{
AnnaBridge	165:d1b4690b3f8b	2970	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	165:d1b4690b3f8b	2971	MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU));
AnnaBridge	165:d1b4690b3f8b	2972	#else
AnnaBridge	165:d1b4690b3f8b	2973	MODIFY_REG(RCC->CCIPR, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
AnnaBridge	165:d1b4690b3f8b	2974	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	165:d1b4690b3f8b	2975	}
AnnaBridge	165:d1b4690b3f8b	2976
AnnaBridge	165:d1b4690b3f8b	2977	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	165:d1b4690b3f8b	2978	/**
AnnaBridge	165:d1b4690b3f8b	2979	* @brief Configure SDMMC1 kernel clock source
AnnaBridge	165:d1b4690b3f8b	2980	* @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource
AnnaBridge	165:d1b4690b3f8b	2981	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2982	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
AnnaBridge	165:d1b4690b3f8b	2983	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLLP (*)
AnnaBridge	165:d1b4690b3f8b	2984	*
AnnaBridge	165:d1b4690b3f8b	2985	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	2986	* @retval None
AnnaBridge	165:d1b4690b3f8b	2987	*/
AnnaBridge	165:d1b4690b3f8b	2988	__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource)
AnnaBridge	165:d1b4690b3f8b	2989	{
AnnaBridge	165:d1b4690b3f8b	2990	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource);
AnnaBridge	165:d1b4690b3f8b	2991	}
AnnaBridge	165:d1b4690b3f8b	2992	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	165:d1b4690b3f8b	2993
AnnaBridge	165:d1b4690b3f8b	2994	/**
AnnaBridge	165:d1b4690b3f8b	2995	* @brief Configure SDMMC1 clock source
AnnaBridge	165:d1b4690b3f8b	2996	* @rmtoll CCIPR CLK48SEL LL_RCC_SetSDMMCClockSource
AnnaBridge	165:d1b4690b3f8b	2997	* @param SDMMCxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	2998	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	165:d1b4690b3f8b	2999	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	3000	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	165:d1b4690b3f8b	3001	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3002	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
AnnaBridge	165:d1b4690b3f8b	3003	*
AnnaBridge	165:d1b4690b3f8b	3004	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3005	* @retval None
AnnaBridge	165:d1b4690b3f8b	3006	*/
AnnaBridge	165:d1b4690b3f8b	3007	__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
AnnaBridge	165:d1b4690b3f8b	3008	{
AnnaBridge	165:d1b4690b3f8b	3009	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, SDMMCxSource);
AnnaBridge	165:d1b4690b3f8b	3010	}
AnnaBridge	165:d1b4690b3f8b	3011
AnnaBridge	165:d1b4690b3f8b	3012	/**
AnnaBridge	165:d1b4690b3f8b	3013	* @brief Configure RNG clock source
AnnaBridge	165:d1b4690b3f8b	3014	* @rmtoll CCIPR CLK48SEL LL_RCC_SetRNGClockSource
AnnaBridge	165:d1b4690b3f8b	3015	* @param RNGxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3016	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	165:d1b4690b3f8b	3017	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	3018	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3019	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3020	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3021	*
AnnaBridge	165:d1b4690b3f8b	3022	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3023	* @retval None
AnnaBridge	165:d1b4690b3f8b	3024	*/
AnnaBridge	165:d1b4690b3f8b	3025	__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
AnnaBridge	165:d1b4690b3f8b	3026	{
AnnaBridge	165:d1b4690b3f8b	3027	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, RNGxSource);
AnnaBridge	165:d1b4690b3f8b	3028	}
AnnaBridge	165:d1b4690b3f8b	3029
AnnaBridge	165:d1b4690b3f8b	3030	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	165:d1b4690b3f8b	3031	/**
AnnaBridge	165:d1b4690b3f8b	3032	* @brief Configure USB clock source
AnnaBridge	165:d1b4690b3f8b	3033	* @rmtoll CCIPR CLK48SEL LL_RCC_SetUSBClockSource
AnnaBridge	165:d1b4690b3f8b	3034	* @param USBxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3035	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	165:d1b4690b3f8b	3036	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	3037	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3038	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3039	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3040	*
AnnaBridge	165:d1b4690b3f8b	3041	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3042	* @retval None
AnnaBridge	165:d1b4690b3f8b	3043	*/
AnnaBridge	165:d1b4690b3f8b	3044	__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
AnnaBridge	165:d1b4690b3f8b	3045	{
AnnaBridge	165:d1b4690b3f8b	3046	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_CLK48SEL, USBxSource);
AnnaBridge	165:d1b4690b3f8b	3047	}
AnnaBridge	165:d1b4690b3f8b	3048	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	165:d1b4690b3f8b	3049
AnnaBridge	165:d1b4690b3f8b	3050	/**
AnnaBridge	165:d1b4690b3f8b	3051	* @brief Configure ADC clock source
AnnaBridge	165:d1b4690b3f8b	3052	* @rmtoll CCIPR ADCSEL LL_RCC_SetADCClockSource
AnnaBridge	165:d1b4690b3f8b	3053	* @param ADCxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3054	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3055	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3056	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	165:d1b4690b3f8b	3057	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3058	*
AnnaBridge	165:d1b4690b3f8b	3059	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3060	* @retval None
AnnaBridge	165:d1b4690b3f8b	3061	*/
AnnaBridge	165:d1b4690b3f8b	3062	__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ADCxSource)
AnnaBridge	165:d1b4690b3f8b	3063	{
AnnaBridge	165:d1b4690b3f8b	3064	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource);
AnnaBridge	165:d1b4690b3f8b	3065	}
AnnaBridge	165:d1b4690b3f8b	3066
AnnaBridge	165:d1b4690b3f8b	3067	#if defined(SWPMI1)
AnnaBridge	165:d1b4690b3f8b	3068	/**
AnnaBridge	165:d1b4690b3f8b	3069	* @brief Configure SWPMI clock source
AnnaBridge	165:d1b4690b3f8b	3070	* @rmtoll CCIPR SWPMI1SEL LL_RCC_SetSWPMIClockSource
AnnaBridge	165:d1b4690b3f8b	3071	* @param SWPMIxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3072	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3073	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3074	* @retval None
AnnaBridge	165:d1b4690b3f8b	3075	*/
AnnaBridge	165:d1b4690b3f8b	3076	__STATIC_INLINE void LL_RCC_SetSWPMIClockSource(uint32_t SWPMIxSource)
AnnaBridge	165:d1b4690b3f8b	3077	{
AnnaBridge	165:d1b4690b3f8b	3078	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_SWPMI1SEL, SWPMIxSource);
AnnaBridge	165:d1b4690b3f8b	3079	}
AnnaBridge	165:d1b4690b3f8b	3080	#endif /* SWPMI1 */
AnnaBridge	165:d1b4690b3f8b	3081
AnnaBridge	165:d1b4690b3f8b	3082	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	3083	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	3084	/**
AnnaBridge	165:d1b4690b3f8b	3085	* @brief Configure DFSDM Audio clock source
AnnaBridge	165:d1b4690b3f8b	3086	* @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
AnnaBridge	165:d1b4690b3f8b	3087	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3088	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	165:d1b4690b3f8b	3089	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3090	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3091	* @retval None
AnnaBridge	165:d1b4690b3f8b	3092	*/
AnnaBridge	165:d1b4690b3f8b	3093	__STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3094	{
AnnaBridge	165:d1b4690b3f8b	3095	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_ADFSDM1SEL, Source);
AnnaBridge	165:d1b4690b3f8b	3096	}
AnnaBridge	165:d1b4690b3f8b	3097	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	3098
AnnaBridge	165:d1b4690b3f8b	3099	/**
AnnaBridge	165:d1b4690b3f8b	3100	* @brief Configure DFSDM Kernel clock source
AnnaBridge	165:d1b4690b3f8b	3101	@if STM32L4S9xx
AnnaBridge	165:d1b4690b3f8b	3102	* @rmtoll CCIPR2 DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	165:d1b4690b3f8b	3103	@else
AnnaBridge	165:d1b4690b3f8b	3104	* @rmtoll CCIPR DFSDM1SEL LL_RCC_SetDFSDMClockSource
AnnaBridge	165:d1b4690b3f8b	3105	@endif
AnnaBridge	165:d1b4690b3f8b	3106	* @param DFSDMxSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3107	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	165:d1b4690b3f8b	3108	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3109	* @retval None
AnnaBridge	165:d1b4690b3f8b	3110	*/
AnnaBridge	165:d1b4690b3f8b	3111	__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t DFSDMxSource)
AnnaBridge	165:d1b4690b3f8b	3112	{
AnnaBridge	165:d1b4690b3f8b	3113	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	3114	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DFSDM1SEL, DFSDMxSource);
AnnaBridge	165:d1b4690b3f8b	3115	#else
AnnaBridge	165:d1b4690b3f8b	3116	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_DFSDM1SEL, DFSDMxSource);
AnnaBridge	165:d1b4690b3f8b	3117	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	3118	}
AnnaBridge	165:d1b4690b3f8b	3119	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	3120
AnnaBridge	165:d1b4690b3f8b	3121	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	3122	/**
AnnaBridge	165:d1b4690b3f8b	3123	* @brief Configure DSI clock source
AnnaBridge	165:d1b4690b3f8b	3124	* @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource
AnnaBridge	165:d1b4690b3f8b	3125	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3126	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	165:d1b4690b3f8b	3127	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3128	* @retval None
AnnaBridge	165:d1b4690b3f8b	3129	*/
AnnaBridge	165:d1b4690b3f8b	3130	__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3131	{
AnnaBridge	165:d1b4690b3f8b	3132	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSISEL, Source);
AnnaBridge	165:d1b4690b3f8b	3133	}
AnnaBridge	165:d1b4690b3f8b	3134	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	3135
AnnaBridge	165:d1b4690b3f8b	3136	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	3137	/**
AnnaBridge	165:d1b4690b3f8b	3138	* @brief Configure LTDC Clock Source
AnnaBridge	165:d1b4690b3f8b	3139	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_SetLTDCClockSource
AnnaBridge	165:d1b4690b3f8b	3140	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3141	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
AnnaBridge	165:d1b4690b3f8b	3142	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
AnnaBridge	165:d1b4690b3f8b	3143	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
AnnaBridge	165:d1b4690b3f8b	3144	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
AnnaBridge	165:d1b4690b3f8b	3145	* @retval None
AnnaBridge	165:d1b4690b3f8b	3146	*/
AnnaBridge	165:d1b4690b3f8b	3147	__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3148	{
AnnaBridge	165:d1b4690b3f8b	3149	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, Source);
AnnaBridge	165:d1b4690b3f8b	3150	}
AnnaBridge	165:d1b4690b3f8b	3151	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	3152
AnnaBridge	165:d1b4690b3f8b	3153	#if defined(OCTOSPI1)
AnnaBridge	165:d1b4690b3f8b	3154	/**
AnnaBridge	165:d1b4690b3f8b	3155	* @brief Configure OCTOSPI clock source
AnnaBridge	165:d1b4690b3f8b	3156	* @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource
AnnaBridge	165:d1b4690b3f8b	3157	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3158	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3159	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3160	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3161	* @retval None
AnnaBridge	165:d1b4690b3f8b	3162	*/
AnnaBridge	165:d1b4690b3f8b	3163	__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3164	{
AnnaBridge	165:d1b4690b3f8b	3165	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OSPISEL, Source);
AnnaBridge	165:d1b4690b3f8b	3166	}
AnnaBridge	165:d1b4690b3f8b	3167	#endif /* OCTOSPI1 */
AnnaBridge	165:d1b4690b3f8b	3168
AnnaBridge	165:d1b4690b3f8b	3169	/**
AnnaBridge	165:d1b4690b3f8b	3170	* @brief Get USARTx clock source
AnnaBridge	165:d1b4690b3f8b	3171	* @rmtoll CCIPR USARTxSEL LL_RCC_GetUSARTClockSource
AnnaBridge	165:d1b4690b3f8b	3172	* @param USARTx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3173	* @arg @ref LL_RCC_USART1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3174	* @arg @ref LL_RCC_USART2_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3175	* @arg @ref LL_RCC_USART3_CLKSOURCE (*)
AnnaBridge	165:d1b4690b3f8b	3176	*
AnnaBridge	165:d1b4690b3f8b	3177	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3178	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3179	* @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
AnnaBridge	165:d1b4690b3f8b	3180	* @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3181	* @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3182	* @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3183	* @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3184	* @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3185	* @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3186	* @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3187	* @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 (*)
AnnaBridge	165:d1b4690b3f8b	3188	* @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK (*)
AnnaBridge	165:d1b4690b3f8b	3189	* @arg @ref LL_RCC_USART3_CLKSOURCE_HSI (*)
AnnaBridge	165:d1b4690b3f8b	3190	* @arg @ref LL_RCC_USART3_CLKSOURCE_LSE (*)
AnnaBridge	165:d1b4690b3f8b	3191	*
AnnaBridge	165:d1b4690b3f8b	3192	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3193	*/
AnnaBridge	165:d1b4690b3f8b	3194	__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
AnnaBridge	165:d1b4690b3f8b	3195	{
AnnaBridge	165:d1b4690b3f8b	3196	return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) \| (USARTx << 16U));
AnnaBridge	165:d1b4690b3f8b	3197	}
AnnaBridge	165:d1b4690b3f8b	3198
AnnaBridge	165:d1b4690b3f8b	3199	#if defined(UART4) \|\| defined(UART5)
AnnaBridge	165:d1b4690b3f8b	3200	/**
AnnaBridge	165:d1b4690b3f8b	3201	* @brief Get UARTx clock source
AnnaBridge	165:d1b4690b3f8b	3202	* @rmtoll CCIPR UARTxSEL LL_RCC_GetUARTClockSource
AnnaBridge	165:d1b4690b3f8b	3203	* @param UARTx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3204	* @arg @ref LL_RCC_UART4_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3205	* @arg @ref LL_RCC_UART5_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3206	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3207	* @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3208	* @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3209	* @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3210	* @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3211	* @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3212	* @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3213	* @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3214	* @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3215	*/
AnnaBridge	165:d1b4690b3f8b	3216	__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
AnnaBridge	165:d1b4690b3f8b	3217	{
AnnaBridge	165:d1b4690b3f8b	3218	return (uint32_t)(READ_BIT(RCC->CCIPR, UARTx) \| (UARTx << 16U));
AnnaBridge	165:d1b4690b3f8b	3219	}
AnnaBridge	165:d1b4690b3f8b	3220	#endif /* UART4 \|\| UART5 */
AnnaBridge	165:d1b4690b3f8b	3221
AnnaBridge	165:d1b4690b3f8b	3222	/**
AnnaBridge	165:d1b4690b3f8b	3223	* @brief Get LPUARTx clock source
AnnaBridge	165:d1b4690b3f8b	3224	* @rmtoll CCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
AnnaBridge	165:d1b4690b3f8b	3225	* @param LPUARTx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3226	* @arg @ref LL_RCC_LPUART1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3227	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3228	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3229	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3230	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3231	* @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3232	*/
AnnaBridge	165:d1b4690b3f8b	3233	__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx)
AnnaBridge	165:d1b4690b3f8b	3234	{
AnnaBridge	165:d1b4690b3f8b	3235	return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx));
AnnaBridge	165:d1b4690b3f8b	3236	}
AnnaBridge	165:d1b4690b3f8b	3237
AnnaBridge	165:d1b4690b3f8b	3238	/**
AnnaBridge	165:d1b4690b3f8b	3239	* @brief Get I2Cx clock source
AnnaBridge	165:d1b4690b3f8b	3240	* @rmtoll CCIPR I2CxSEL LL_RCC_GetI2CClockSource
AnnaBridge	165:d1b4690b3f8b	3241	* @param I2Cx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3242	* @arg @ref LL_RCC_I2C1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3243	* @arg @ref LL_RCC_I2C2_CLKSOURCE (*)
AnnaBridge	165:d1b4690b3f8b	3244	* @arg @ref LL_RCC_I2C3_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3245	* @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
AnnaBridge	165:d1b4690b3f8b	3246	*
AnnaBridge	165:d1b4690b3f8b	3247	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3248	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3249	* @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3250	* @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3251	* @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3252	* @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 (*)
AnnaBridge	165:d1b4690b3f8b	3253	* @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK (*)
AnnaBridge	165:d1b4690b3f8b	3254	* @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI (*)
AnnaBridge	165:d1b4690b3f8b	3255	* @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3256	* @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3257	* @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3258	* @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
AnnaBridge	165:d1b4690b3f8b	3259	* @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
AnnaBridge	165:d1b4690b3f8b	3260	* @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
AnnaBridge	165:d1b4690b3f8b	3261	*
AnnaBridge	165:d1b4690b3f8b	3262	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3263	*/
AnnaBridge	165:d1b4690b3f8b	3264	__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
AnnaBridge	165:d1b4690b3f8b	3265	{
AnnaBridge	165:d1b4690b3f8b	3266	__IO uint32_t reg = (__IO uint32_t )(uint32_t)(RCC_BASE + 0x88U + (I2Cx >> 24U));
AnnaBridge	165:d1b4690b3f8b	3267	return (uint32_t)((READ_BIT(*reg, 3U << ((I2Cx & 0x00FF0000U) >> 16U)) >> ((I2Cx & 0x00FF0000U) >> 16U)) \| (I2Cx & 0xFFFF0000U));
AnnaBridge	165:d1b4690b3f8b	3268	}
AnnaBridge	165:d1b4690b3f8b	3269
AnnaBridge	165:d1b4690b3f8b	3270	/**
AnnaBridge	165:d1b4690b3f8b	3271	* @brief Get LPTIMx clock source
AnnaBridge	165:d1b4690b3f8b	3272	* @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource
AnnaBridge	165:d1b4690b3f8b	3273	* @param LPTIMx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3274	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3275	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3276	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3277	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3278	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	3279	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3280	* @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3281	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3282	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	3283	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3284	* @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3285	*/
AnnaBridge	165:d1b4690b3f8b	3286	__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
AnnaBridge	165:d1b4690b3f8b	3287	{
AnnaBridge	165:d1b4690b3f8b	3288	return (uint32_t)(READ_BIT(RCC->CCIPR, LPTIMx) >> 16U \| LPTIMx);
AnnaBridge	165:d1b4690b3f8b	3289	}
AnnaBridge	165:d1b4690b3f8b	3290
AnnaBridge	165:d1b4690b3f8b	3291	/**
AnnaBridge	165:d1b4690b3f8b	3292	* @brief Get SAIx clock source
AnnaBridge	165:d1b4690b3f8b	3293	@if STM32L4S9xx
AnnaBridge	165:d1b4690b3f8b	3294	* @rmtoll CCIPR2 SAIxSEL LL_RCC_GetSAIClockSource
AnnaBridge	165:d1b4690b3f8b	3295	@else
AnnaBridge	165:d1b4690b3f8b	3296	* @rmtoll CCIPR SAIxSEL LL_RCC_GetSAIClockSource
AnnaBridge	165:d1b4690b3f8b	3297	@endif
AnnaBridge	165:d1b4690b3f8b	3298	* @param SAIx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3299	* @arg @ref LL_RCC_SAI1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3300	* @arg @ref LL_RCC_SAI2_CLKSOURCE (*)
AnnaBridge	165:d1b4690b3f8b	3301	*
AnnaBridge	165:d1b4690b3f8b	3302	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3303	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3304	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3305	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	165:d1b4690b3f8b	3306	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3307	* @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
AnnaBridge	165:d1b4690b3f8b	3308	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	165:d1b4690b3f8b	3309	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	165:d1b4690b3f8b	3310	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL (*)
AnnaBridge	165:d1b4690b3f8b	3311	* @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*)
AnnaBridge	165:d1b4690b3f8b	3312	*
AnnaBridge	165:d1b4690b3f8b	3313	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3314	*/
AnnaBridge	165:d1b4690b3f8b	3315	__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
AnnaBridge	165:d1b4690b3f8b	3316	{
AnnaBridge	165:d1b4690b3f8b	3317	#if defined(RCC_CCIPR2_SAI1SEL)
AnnaBridge	165:d1b4690b3f8b	3318	return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) \| (SAIx << 16U));
AnnaBridge	165:d1b4690b3f8b	3319	#else
AnnaBridge	165:d1b4690b3f8b	3320	return (uint32_t)(READ_BIT(RCC->CCIPR, SAIx) >> 16U \| SAIx);
AnnaBridge	165:d1b4690b3f8b	3321	#endif /* RCC_CCIPR2_SAI1SEL */
AnnaBridge	165:d1b4690b3f8b	3322	}
AnnaBridge	165:d1b4690b3f8b	3323
AnnaBridge	165:d1b4690b3f8b	3324	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	165:d1b4690b3f8b	3325	/**
AnnaBridge	165:d1b4690b3f8b	3326	* @brief Get SDMMCx kernel clock source
AnnaBridge	165:d1b4690b3f8b	3327	* @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource
AnnaBridge	165:d1b4690b3f8b	3328	* @param SDMMCx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3329	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3330	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3331	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_48CLK (*)
AnnaBridge	165:d1b4690b3f8b	3332	* @arg @ref LL_RCC_SDMMC1_KERNELCLKSOURCE_PLL (*)
AnnaBridge	165:d1b4690b3f8b	3333	*
AnnaBridge	165:d1b4690b3f8b	3334	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3335	*/
AnnaBridge	165:d1b4690b3f8b	3336	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx)
AnnaBridge	165:d1b4690b3f8b	3337	{
AnnaBridge	165:d1b4690b3f8b	3338	return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx));
AnnaBridge	165:d1b4690b3f8b	3339	}
AnnaBridge	165:d1b4690b3f8b	3340	#endif /* RCC_CCIPR2_SDMMCSEL */
AnnaBridge	165:d1b4690b3f8b	3341
AnnaBridge	165:d1b4690b3f8b	3342	/**
AnnaBridge	165:d1b4690b3f8b	3343	* @brief Get SDMMCx clock source
AnnaBridge	165:d1b4690b3f8b	3344	* @rmtoll CCIPR CLK48SEL LL_RCC_GetSDMMCClockSource
AnnaBridge	165:d1b4690b3f8b	3345	* @param SDMMCx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3346	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3347	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3348	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_NONE (*)
AnnaBridge	165:d1b4690b3f8b	3349	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	3350	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLLSAI1 (*)
AnnaBridge	165:d1b4690b3f8b	3351	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3352	* @arg @ref LL_RCC_SDMMC1_CLKSOURCE_MSI (*)
AnnaBridge	165:d1b4690b3f8b	3353	*
AnnaBridge	165:d1b4690b3f8b	3354	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3355	*/
AnnaBridge	165:d1b4690b3f8b	3356	__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
AnnaBridge	165:d1b4690b3f8b	3357	{
AnnaBridge	165:d1b4690b3f8b	3358	return (uint32_t)(READ_BIT(RCC->CCIPR, SDMMCx));
AnnaBridge	165:d1b4690b3f8b	3359	}
AnnaBridge	165:d1b4690b3f8b	3360
AnnaBridge	165:d1b4690b3f8b	3361	/**
AnnaBridge	165:d1b4690b3f8b	3362	* @brief Get RNGx clock source
AnnaBridge	165:d1b4690b3f8b	3363	* @rmtoll CCIPR CLK48SEL LL_RCC_GetRNGClockSource
AnnaBridge	165:d1b4690b3f8b	3364	* @param RNGx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3365	* @arg @ref LL_RCC_RNG_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3366	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3367	* @arg @ref LL_RCC_RNG_CLKSOURCE_NONE (*)
AnnaBridge	165:d1b4690b3f8b	3368	* @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	3369	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3370	* @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3371	* @arg @ref LL_RCC_RNG_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3372	*
AnnaBridge	165:d1b4690b3f8b	3373	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3374	*/
AnnaBridge	165:d1b4690b3f8b	3375	__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
AnnaBridge	165:d1b4690b3f8b	3376	{
AnnaBridge	165:d1b4690b3f8b	3377	return (uint32_t)(READ_BIT(RCC->CCIPR, RNGx));
AnnaBridge	165:d1b4690b3f8b	3378	}
AnnaBridge	165:d1b4690b3f8b	3379
AnnaBridge	165:d1b4690b3f8b	3380	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	165:d1b4690b3f8b	3381	/**
AnnaBridge	165:d1b4690b3f8b	3382	* @brief Get USBx clock source
AnnaBridge	165:d1b4690b3f8b	3383	* @rmtoll CCIPR CLK48SEL LL_RCC_GetUSBClockSource
AnnaBridge	165:d1b4690b3f8b	3384	* @param USBx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3385	* @arg @ref LL_RCC_USB_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3386	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3387	* @arg @ref LL_RCC_USB_CLKSOURCE_NONE (*)
AnnaBridge	165:d1b4690b3f8b	3388	* @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 (*)
AnnaBridge	165:d1b4690b3f8b	3389	* @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3390	* @arg @ref LL_RCC_USB_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3391	* @arg @ref LL_RCC_USB_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3392	*
AnnaBridge	165:d1b4690b3f8b	3393	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3394	*/
AnnaBridge	165:d1b4690b3f8b	3395	__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
AnnaBridge	165:d1b4690b3f8b	3396	{
AnnaBridge	165:d1b4690b3f8b	3397	return (uint32_t)(READ_BIT(RCC->CCIPR, USBx));
AnnaBridge	165:d1b4690b3f8b	3398	}
AnnaBridge	165:d1b4690b3f8b	3399	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	165:d1b4690b3f8b	3400
AnnaBridge	165:d1b4690b3f8b	3401	/**
AnnaBridge	165:d1b4690b3f8b	3402	* @brief Get ADCx clock source
AnnaBridge	165:d1b4690b3f8b	3403	* @rmtoll CCIPR ADCSEL LL_RCC_GetADCClockSource
AnnaBridge	165:d1b4690b3f8b	3404	* @param ADCx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3405	* @arg @ref LL_RCC_ADC_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3406	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3407	* @arg @ref LL_RCC_ADC_CLKSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3408	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI1
AnnaBridge	165:d1b4690b3f8b	3409	* @arg @ref LL_RCC_ADC_CLKSOURCE_PLLSAI2 (*)
AnnaBridge	165:d1b4690b3f8b	3410	* @arg @ref LL_RCC_ADC_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3411	*
AnnaBridge	165:d1b4690b3f8b	3412	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3413	*/
AnnaBridge	165:d1b4690b3f8b	3414	__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t ADCx)
AnnaBridge	165:d1b4690b3f8b	3415	{
AnnaBridge	165:d1b4690b3f8b	3416	return (uint32_t)(READ_BIT(RCC->CCIPR, ADCx));
AnnaBridge	165:d1b4690b3f8b	3417	}
AnnaBridge	165:d1b4690b3f8b	3418
AnnaBridge	165:d1b4690b3f8b	3419	#if defined(SWPMI1)
AnnaBridge	165:d1b4690b3f8b	3420	/**
AnnaBridge	165:d1b4690b3f8b	3421	* @brief Get SWPMIx clock source
AnnaBridge	165:d1b4690b3f8b	3422	* @rmtoll CCIPR SWPMI1SEL LL_RCC_GetSWPMIClockSource
AnnaBridge	165:d1b4690b3f8b	3423	* @param SPWMIx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3424	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3425	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3426	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_PCLK1
AnnaBridge	165:d1b4690b3f8b	3427	* @arg @ref LL_RCC_SWPMI1_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3428	*/
AnnaBridge	165:d1b4690b3f8b	3429	__STATIC_INLINE uint32_t LL_RCC_GetSWPMIClockSource(uint32_t SPWMIx)
AnnaBridge	165:d1b4690b3f8b	3430	{
AnnaBridge	165:d1b4690b3f8b	3431	return (uint32_t)(READ_BIT(RCC->CCIPR, SPWMIx));
AnnaBridge	165:d1b4690b3f8b	3432	}
AnnaBridge	165:d1b4690b3f8b	3433	#endif /* SWPMI1 */
AnnaBridge	165:d1b4690b3f8b	3434
AnnaBridge	165:d1b4690b3f8b	3435	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	3436	#if defined(RCC_CCIPR2_ADFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	3437	/**
AnnaBridge	165:d1b4690b3f8b	3438	* @brief Get DFSDM Audio Clock Source
AnnaBridge	165:d1b4690b3f8b	3439	* @rmtoll CCIPR2 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
AnnaBridge	165:d1b4690b3f8b	3440	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3441	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3442	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3443	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
AnnaBridge	165:d1b4690b3f8b	3444	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3445	* @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3446	*/
AnnaBridge	165:d1b4690b3f8b	3447	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
AnnaBridge	165:d1b4690b3f8b	3448	{
AnnaBridge	165:d1b4690b3f8b	3449	return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
AnnaBridge	165:d1b4690b3f8b	3450	}
AnnaBridge	165:d1b4690b3f8b	3451	#endif /* RCC_CCIPR2_ADFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	3452
AnnaBridge	165:d1b4690b3f8b	3453	/**
AnnaBridge	165:d1b4690b3f8b	3454	* @brief Get DFSDMx Kernel clock source
AnnaBridge	165:d1b4690b3f8b	3455	@if STM32L4S9xx
AnnaBridge	165:d1b4690b3f8b	3456	* @rmtoll CCIPR2 DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	165:d1b4690b3f8b	3457	@else
AnnaBridge	165:d1b4690b3f8b	3458	* @rmtoll CCIPR DFSDM1SEL LL_RCC_GetDFSDMClockSource
AnnaBridge	165:d1b4690b3f8b	3459	@endif
AnnaBridge	165:d1b4690b3f8b	3460	* @param DFSDMx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3461	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3462	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3463	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
AnnaBridge	165:d1b4690b3f8b	3464	* @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3465	*/
AnnaBridge	165:d1b4690b3f8b	3466	__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
AnnaBridge	165:d1b4690b3f8b	3467	{
AnnaBridge	165:d1b4690b3f8b	3468	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	3469	return (uint32_t)(READ_BIT(RCC->CCIPR2, DFSDMx));
AnnaBridge	165:d1b4690b3f8b	3470	#else
AnnaBridge	165:d1b4690b3f8b	3471	return (uint32_t)(READ_BIT(RCC->CCIPR, DFSDMx));
AnnaBridge	165:d1b4690b3f8b	3472	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	3473	}
AnnaBridge	165:d1b4690b3f8b	3474	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	3475
AnnaBridge	165:d1b4690b3f8b	3476	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	3477	/**
AnnaBridge	165:d1b4690b3f8b	3478	* @brief Get DSI Clock Source
AnnaBridge	165:d1b4690b3f8b	3479	* @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource
AnnaBridge	165:d1b4690b3f8b	3480	* @param DSIx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3481	* @arg @ref LL_RCC_DSI_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3482	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3483	* @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
AnnaBridge	165:d1b4690b3f8b	3484	* @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3485	*/
AnnaBridge	165:d1b4690b3f8b	3486	__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
AnnaBridge	165:d1b4690b3f8b	3487	{
AnnaBridge	165:d1b4690b3f8b	3488	return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx));
AnnaBridge	165:d1b4690b3f8b	3489	}
AnnaBridge	165:d1b4690b3f8b	3490	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	3491
AnnaBridge	165:d1b4690b3f8b	3492	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	3493	/**
AnnaBridge	165:d1b4690b3f8b	3494	* @brief Get LTDC Clock Source
AnnaBridge	165:d1b4690b3f8b	3495	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_GetLTDCClockSource
AnnaBridge	165:d1b4690b3f8b	3496	* @param LTDCx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3497	* @arg @ref LL_RCC_LTDC_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3498	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3499	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV2
AnnaBridge	165:d1b4690b3f8b	3500	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV4
AnnaBridge	165:d1b4690b3f8b	3501	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV8
AnnaBridge	165:d1b4690b3f8b	3502	* @arg @ref LL_RCC_LTDC_CLKSOURCE_PLLSAI2R_DIV16
AnnaBridge	165:d1b4690b3f8b	3503	*/
AnnaBridge	165:d1b4690b3f8b	3504	__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx)
AnnaBridge	165:d1b4690b3f8b	3505	{
AnnaBridge	165:d1b4690b3f8b	3506	return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx));
AnnaBridge	165:d1b4690b3f8b	3507	}
AnnaBridge	165:d1b4690b3f8b	3508	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	3509
AnnaBridge	165:d1b4690b3f8b	3510	#if defined(OCTOSPI1)
AnnaBridge	165:d1b4690b3f8b	3511	/**
AnnaBridge	165:d1b4690b3f8b	3512	* @brief Get OCTOSPI clock source
AnnaBridge	165:d1b4690b3f8b	3513	* @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource
AnnaBridge	165:d1b4690b3f8b	3514	* @param OCTOSPIx This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3515	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE
AnnaBridge	165:d1b4690b3f8b	3516	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3517	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK
AnnaBridge	165:d1b4690b3f8b	3518	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3519	* @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL
AnnaBridge	165:d1b4690b3f8b	3520	*/
AnnaBridge	165:d1b4690b3f8b	3521	__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx)
AnnaBridge	165:d1b4690b3f8b	3522	{
AnnaBridge	165:d1b4690b3f8b	3523	return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx));
AnnaBridge	165:d1b4690b3f8b	3524	}
AnnaBridge	165:d1b4690b3f8b	3525	#endif /* OCTOSPI1 */
AnnaBridge	165:d1b4690b3f8b	3526	/**
AnnaBridge	165:d1b4690b3f8b	3527	* @}
AnnaBridge	165:d1b4690b3f8b	3528	*/
AnnaBridge	165:d1b4690b3f8b	3529
AnnaBridge	165:d1b4690b3f8b	3530	/** @defgroup RCC_LL_EF_RTC RTC
AnnaBridge	165:d1b4690b3f8b	3531	* @{
AnnaBridge	165:d1b4690b3f8b	3532	*/
AnnaBridge	165:d1b4690b3f8b	3533
AnnaBridge	165:d1b4690b3f8b	3534	/**
AnnaBridge	165:d1b4690b3f8b	3535	* @brief Set RTC Clock Source
AnnaBridge	165:d1b4690b3f8b	3536	* @note Once the RTC clock source has been selected, it cannot be changed anymore unless
AnnaBridge	165:d1b4690b3f8b	3537	* the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
AnnaBridge	165:d1b4690b3f8b	3538	* set). The BDRST bit can be used to reset them.
AnnaBridge	165:d1b4690b3f8b	3539	* @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
AnnaBridge	165:d1b4690b3f8b	3540	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3541	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3542	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3543	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	3544	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
AnnaBridge	165:d1b4690b3f8b	3545	* @retval None
AnnaBridge	165:d1b4690b3f8b	3546	*/
AnnaBridge	165:d1b4690b3f8b	3547	__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
AnnaBridge	165:d1b4690b3f8b	3548	{
AnnaBridge	165:d1b4690b3f8b	3549	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
AnnaBridge	165:d1b4690b3f8b	3550	}
AnnaBridge	165:d1b4690b3f8b	3551
AnnaBridge	165:d1b4690b3f8b	3552	/**
AnnaBridge	165:d1b4690b3f8b	3553	* @brief Get RTC Clock Source
AnnaBridge	165:d1b4690b3f8b	3554	* @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
AnnaBridge	165:d1b4690b3f8b	3555	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3556	* @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3557	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
AnnaBridge	165:d1b4690b3f8b	3558	* @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
AnnaBridge	165:d1b4690b3f8b	3559	* @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32
AnnaBridge	165:d1b4690b3f8b	3560	*/
AnnaBridge	165:d1b4690b3f8b	3561	__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
AnnaBridge	165:d1b4690b3f8b	3562	{
AnnaBridge	165:d1b4690b3f8b	3563	return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
AnnaBridge	165:d1b4690b3f8b	3564	}
AnnaBridge	165:d1b4690b3f8b	3565
AnnaBridge	165:d1b4690b3f8b	3566	/**
AnnaBridge	165:d1b4690b3f8b	3567	* @brief Enable RTC
AnnaBridge	165:d1b4690b3f8b	3568	* @rmtoll BDCR RTCEN LL_RCC_EnableRTC
AnnaBridge	165:d1b4690b3f8b	3569	* @retval None
AnnaBridge	165:d1b4690b3f8b	3570	*/
AnnaBridge	165:d1b4690b3f8b	3571	__STATIC_INLINE void LL_RCC_EnableRTC(void)
AnnaBridge	165:d1b4690b3f8b	3572	{
AnnaBridge	165:d1b4690b3f8b	3573	SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	165:d1b4690b3f8b	3574	}
AnnaBridge	165:d1b4690b3f8b	3575
AnnaBridge	165:d1b4690b3f8b	3576	/**
AnnaBridge	165:d1b4690b3f8b	3577	* @brief Disable RTC
AnnaBridge	165:d1b4690b3f8b	3578	* @rmtoll BDCR RTCEN LL_RCC_DisableRTC
AnnaBridge	165:d1b4690b3f8b	3579	* @retval None
AnnaBridge	165:d1b4690b3f8b	3580	*/
AnnaBridge	165:d1b4690b3f8b	3581	__STATIC_INLINE void LL_RCC_DisableRTC(void)
AnnaBridge	165:d1b4690b3f8b	3582	{
AnnaBridge	165:d1b4690b3f8b	3583	CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
AnnaBridge	165:d1b4690b3f8b	3584	}
AnnaBridge	165:d1b4690b3f8b	3585
AnnaBridge	165:d1b4690b3f8b	3586	/**
AnnaBridge	165:d1b4690b3f8b	3587	* @brief Check if RTC has been enabled or not
AnnaBridge	165:d1b4690b3f8b	3588	* @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
AnnaBridge	165:d1b4690b3f8b	3589	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3590	*/
AnnaBridge	165:d1b4690b3f8b	3591	__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
AnnaBridge	165:d1b4690b3f8b	3592	{
AnnaBridge	165:d1b4690b3f8b	3593	return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
AnnaBridge	165:d1b4690b3f8b	3594	}
AnnaBridge	165:d1b4690b3f8b	3595
AnnaBridge	165:d1b4690b3f8b	3596	/**
AnnaBridge	165:d1b4690b3f8b	3597	* @brief Force the Backup domain reset
AnnaBridge	165:d1b4690b3f8b	3598	* @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
AnnaBridge	165:d1b4690b3f8b	3599	* @retval None
AnnaBridge	165:d1b4690b3f8b	3600	*/
AnnaBridge	165:d1b4690b3f8b	3601	__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
AnnaBridge	165:d1b4690b3f8b	3602	{
AnnaBridge	165:d1b4690b3f8b	3603	SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	165:d1b4690b3f8b	3604	}
AnnaBridge	165:d1b4690b3f8b	3605
AnnaBridge	165:d1b4690b3f8b	3606	/**
AnnaBridge	165:d1b4690b3f8b	3607	* @brief Release the Backup domain reset
AnnaBridge	165:d1b4690b3f8b	3608	* @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
AnnaBridge	165:d1b4690b3f8b	3609	* @retval None
AnnaBridge	165:d1b4690b3f8b	3610	*/
AnnaBridge	165:d1b4690b3f8b	3611	__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
AnnaBridge	165:d1b4690b3f8b	3612	{
AnnaBridge	165:d1b4690b3f8b	3613	CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
AnnaBridge	165:d1b4690b3f8b	3614	}
AnnaBridge	165:d1b4690b3f8b	3615
AnnaBridge	165:d1b4690b3f8b	3616	/**
AnnaBridge	165:d1b4690b3f8b	3617	* @}
AnnaBridge	165:d1b4690b3f8b	3618	*/
AnnaBridge	165:d1b4690b3f8b	3619
AnnaBridge	165:d1b4690b3f8b	3620
AnnaBridge	165:d1b4690b3f8b	3621	/** @defgroup RCC_LL_EF_PLL PLL
AnnaBridge	165:d1b4690b3f8b	3622	* @{
AnnaBridge	165:d1b4690b3f8b	3623	*/
AnnaBridge	165:d1b4690b3f8b	3624
AnnaBridge	165:d1b4690b3f8b	3625	/**
AnnaBridge	165:d1b4690b3f8b	3626	* @brief Enable PLL
AnnaBridge	165:d1b4690b3f8b	3627	* @rmtoll CR PLLON LL_RCC_PLL_Enable
AnnaBridge	165:d1b4690b3f8b	3628	* @retval None
AnnaBridge	165:d1b4690b3f8b	3629	*/
AnnaBridge	165:d1b4690b3f8b	3630	__STATIC_INLINE void LL_RCC_PLL_Enable(void)
AnnaBridge	165:d1b4690b3f8b	3631	{
AnnaBridge	165:d1b4690b3f8b	3632	SET_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	165:d1b4690b3f8b	3633	}
AnnaBridge	165:d1b4690b3f8b	3634
AnnaBridge	165:d1b4690b3f8b	3635	/**
AnnaBridge	165:d1b4690b3f8b	3636	* @brief Disable PLL
AnnaBridge	165:d1b4690b3f8b	3637	* @note Cannot be disabled if the PLL clock is used as the system clock
AnnaBridge	165:d1b4690b3f8b	3638	* @rmtoll CR PLLON LL_RCC_PLL_Disable
AnnaBridge	165:d1b4690b3f8b	3639	* @retval None
AnnaBridge	165:d1b4690b3f8b	3640	*/
AnnaBridge	165:d1b4690b3f8b	3641	__STATIC_INLINE void LL_RCC_PLL_Disable(void)
AnnaBridge	165:d1b4690b3f8b	3642	{
AnnaBridge	165:d1b4690b3f8b	3643	CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
AnnaBridge	165:d1b4690b3f8b	3644	}
AnnaBridge	165:d1b4690b3f8b	3645
AnnaBridge	165:d1b4690b3f8b	3646	/**
AnnaBridge	165:d1b4690b3f8b	3647	* @brief Check if PLL Ready
AnnaBridge	165:d1b4690b3f8b	3648	* @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
AnnaBridge	165:d1b4690b3f8b	3649	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	3650	*/
AnnaBridge	165:d1b4690b3f8b	3651	__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	3652	{
AnnaBridge	165:d1b4690b3f8b	3653	return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
AnnaBridge	165:d1b4690b3f8b	3654	}
AnnaBridge	165:d1b4690b3f8b	3655
AnnaBridge	165:d1b4690b3f8b	3656	/**
AnnaBridge	165:d1b4690b3f8b	3657	* @brief Configure PLL used for SYSCLK Domain
AnnaBridge	165:d1b4690b3f8b	3658	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	3659	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	3660	* @note PLLN/PLLR can be written only when PLL is disabled.
AnnaBridge	165:d1b4690b3f8b	3661	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	165:d1b4690b3f8b	3662	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	165:d1b4690b3f8b	3663	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
AnnaBridge	165:d1b4690b3f8b	3664	* PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_SYS
AnnaBridge	165:d1b4690b3f8b	3665	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3666	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3667	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3668	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3669	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	3670	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3671	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	3672	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	3673	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	3674	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	3675	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	3676	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	3677	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	3678	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	3679	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	3680	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	3681	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	3682	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	3683	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	3684	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	3685	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	3686	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	3687	*
AnnaBridge	165:d1b4690b3f8b	3688	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3689	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	3690	* @param PLLR This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3691	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	165:d1b4690b3f8b	3692	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	165:d1b4690b3f8b	3693	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	165:d1b4690b3f8b	3694	* @arg @ref LL_RCC_PLLR_DIV_8
AnnaBridge	165:d1b4690b3f8b	3695	* @retval None
AnnaBridge	165:d1b4690b3f8b	3696	*/
AnnaBridge	165:d1b4690b3f8b	3697	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	165:d1b4690b3f8b	3698	{
AnnaBridge	165:d1b4690b3f8b	3699	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLR,
AnnaBridge	165:d1b4690b3f8b	3700	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLR);
AnnaBridge	165:d1b4690b3f8b	3701	}
AnnaBridge	165:d1b4690b3f8b	3702
AnnaBridge	165:d1b4690b3f8b	3703	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	3704	/**
AnnaBridge	165:d1b4690b3f8b	3705	* @brief Configure PLL used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	3706	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	3707	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	3708	* @note PLLN/PLLP can be written only when PLL is disabled.
AnnaBridge	165:d1b4690b3f8b	3709	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	165:d1b4690b3f8b	3710	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	3711	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	3712	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	3713	* PLLCFGR PLLPDIV LL_RCC_PLL_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	3714	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3715	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3716	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3717	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3718	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	3719	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3720	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	3721	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	3722	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	3723	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	3724	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	3725	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	3726	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	3727	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	3728	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	3729	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	3730	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	3731	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	3732	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	3733	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	3734	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	3735	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	3736	*
AnnaBridge	165:d1b4690b3f8b	3737	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3738	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	3739	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3740	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	165:d1b4690b3f8b	3741	* @arg @ref LL_RCC_PLLP_DIV_3
AnnaBridge	165:d1b4690b3f8b	3742	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	165:d1b4690b3f8b	3743	* @arg @ref LL_RCC_PLLP_DIV_5
AnnaBridge	165:d1b4690b3f8b	3744	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	165:d1b4690b3f8b	3745	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	165:d1b4690b3f8b	3746	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	165:d1b4690b3f8b	3747	* @arg @ref LL_RCC_PLLP_DIV_9
AnnaBridge	165:d1b4690b3f8b	3748	* @arg @ref LL_RCC_PLLP_DIV_10
AnnaBridge	165:d1b4690b3f8b	3749	* @arg @ref LL_RCC_PLLP_DIV_11
AnnaBridge	165:d1b4690b3f8b	3750	* @arg @ref LL_RCC_PLLP_DIV_12
AnnaBridge	165:d1b4690b3f8b	3751	* @arg @ref LL_RCC_PLLP_DIV_13
AnnaBridge	165:d1b4690b3f8b	3752	* @arg @ref LL_RCC_PLLP_DIV_14
AnnaBridge	165:d1b4690b3f8b	3753	* @arg @ref LL_RCC_PLLP_DIV_15
AnnaBridge	165:d1b4690b3f8b	3754	* @arg @ref LL_RCC_PLLP_DIV_16
AnnaBridge	165:d1b4690b3f8b	3755	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	165:d1b4690b3f8b	3756	* @arg @ref LL_RCC_PLLP_DIV_18
AnnaBridge	165:d1b4690b3f8b	3757	* @arg @ref LL_RCC_PLLP_DIV_19
AnnaBridge	165:d1b4690b3f8b	3758	* @arg @ref LL_RCC_PLLP_DIV_20
AnnaBridge	165:d1b4690b3f8b	3759	* @arg @ref LL_RCC_PLLP_DIV_21
AnnaBridge	165:d1b4690b3f8b	3760	* @arg @ref LL_RCC_PLLP_DIV_22
AnnaBridge	165:d1b4690b3f8b	3761	* @arg @ref LL_RCC_PLLP_DIV_23
AnnaBridge	165:d1b4690b3f8b	3762	* @arg @ref LL_RCC_PLLP_DIV_24
AnnaBridge	165:d1b4690b3f8b	3763	* @arg @ref LL_RCC_PLLP_DIV_25
AnnaBridge	165:d1b4690b3f8b	3764	* @arg @ref LL_RCC_PLLP_DIV_26
AnnaBridge	165:d1b4690b3f8b	3765	* @arg @ref LL_RCC_PLLP_DIV_27
AnnaBridge	165:d1b4690b3f8b	3766	* @arg @ref LL_RCC_PLLP_DIV_28
AnnaBridge	165:d1b4690b3f8b	3767	* @arg @ref LL_RCC_PLLP_DIV_29
AnnaBridge	165:d1b4690b3f8b	3768	* @arg @ref LL_RCC_PLLP_DIV_30
AnnaBridge	165:d1b4690b3f8b	3769	* @arg @ref LL_RCC_PLLP_DIV_31
AnnaBridge	165:d1b4690b3f8b	3770	* @retval None
AnnaBridge	165:d1b4690b3f8b	3771	*/
AnnaBridge	165:d1b4690b3f8b	3772	#else
AnnaBridge	165:d1b4690b3f8b	3773	/**
AnnaBridge	165:d1b4690b3f8b	3774	* @brief Configure PLL used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	3775	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	3776	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	3777	* @note PLLN/PLLP can be written only when PLL is disabled.
AnnaBridge	165:d1b4690b3f8b	3778	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	165:d1b4690b3f8b	3779	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	3780	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	3781	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	3782	* PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	3783	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3784	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3785	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3786	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3787	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	3788	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3789	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	3790	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	3791	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	3792	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	3793	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	3794	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	3795	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	3796	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	3797	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	3798	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3799	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	165:d1b4690b3f8b	3800	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	165:d1b4690b3f8b	3801	* @retval None
AnnaBridge	165:d1b4690b3f8b	3802	*/
AnnaBridge	165:d1b4690b3f8b	3803	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	3804	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	3805	{
AnnaBridge	165:d1b4690b3f8b	3806	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	3807	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLPDIV,
AnnaBridge	165:d1b4690b3f8b	3808	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	3809	#else
AnnaBridge	165:d1b4690b3f8b	3810	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLP,
AnnaBridge	165:d1b4690b3f8b	3811	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	3812	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	3813	}
AnnaBridge	165:d1b4690b3f8b	3814
AnnaBridge	165:d1b4690b3f8b	3815	/**
AnnaBridge	165:d1b4690b3f8b	3816	* @brief Configure PLL used for 48Mhz domain clock
AnnaBridge	165:d1b4690b3f8b	3817	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	3818	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	3819	* @note PLLN/PLLQ can be written only when PLL is disabled.
AnnaBridge	165:d1b4690b3f8b	3820	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	165:d1b4690b3f8b	3821	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	3822	* PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	3823	* PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	3824	* PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
AnnaBridge	165:d1b4690b3f8b	3825	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3826	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3827	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3828	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3829	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	3830	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3831	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	3832	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	3833	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	3834	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	3835	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	3836	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	3837	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	3838	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	3839	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	3840	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	3841	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	3842	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	3843	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	3844	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	3845	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	3846	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	3847	*
AnnaBridge	165:d1b4690b3f8b	3848	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	3849	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	3850	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3851	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	165:d1b4690b3f8b	3852	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	165:d1b4690b3f8b	3853	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	165:d1b4690b3f8b	3854	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	165:d1b4690b3f8b	3855	* @retval None
AnnaBridge	165:d1b4690b3f8b	3856	*/
AnnaBridge	165:d1b4690b3f8b	3857	__STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	165:d1b4690b3f8b	3858	{
AnnaBridge	165:d1b4690b3f8b	3859	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM \| RCC_PLLCFGR_PLLN \| RCC_PLLCFGR_PLLQ,
AnnaBridge	165:d1b4690b3f8b	3860	Source \| PLLM \| PLLN << RCC_PLLCFGR_PLLN_Pos \| PLLQ);
AnnaBridge	165:d1b4690b3f8b	3861	}
AnnaBridge	165:d1b4690b3f8b	3862
AnnaBridge	165:d1b4690b3f8b	3863	/**
AnnaBridge	165:d1b4690b3f8b	3864	* @brief Configure PLL clock source
AnnaBridge	165:d1b4690b3f8b	3865	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
AnnaBridge	165:d1b4690b3f8b	3866	* @param PLLSource This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3867	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3868	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3869	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3870	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	3871	* @retval None
AnnaBridge	165:d1b4690b3f8b	3872	*/
AnnaBridge	165:d1b4690b3f8b	3873	__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
AnnaBridge	165:d1b4690b3f8b	3874	{
AnnaBridge	165:d1b4690b3f8b	3875	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
AnnaBridge	165:d1b4690b3f8b	3876	}
AnnaBridge	165:d1b4690b3f8b	3877
AnnaBridge	165:d1b4690b3f8b	3878	/**
AnnaBridge	165:d1b4690b3f8b	3879	* @brief Get the oscillator used as PLL clock source.
AnnaBridge	165:d1b4690b3f8b	3880	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
AnnaBridge	165:d1b4690b3f8b	3881	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3882	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	3883	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	3884	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	3885	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	3886	*/
AnnaBridge	165:d1b4690b3f8b	3887	__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
AnnaBridge	165:d1b4690b3f8b	3888	{
AnnaBridge	165:d1b4690b3f8b	3889	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
AnnaBridge	165:d1b4690b3f8b	3890	}
AnnaBridge	165:d1b4690b3f8b	3891
AnnaBridge	165:d1b4690b3f8b	3892	/**
AnnaBridge	165:d1b4690b3f8b	3893	* @brief Get Main PLL multiplication factor for VCO
AnnaBridge	165:d1b4690b3f8b	3894	* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
AnnaBridge	165:d1b4690b3f8b	3895	* @retval Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	3896	*/
AnnaBridge	165:d1b4690b3f8b	3897	__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
AnnaBridge	165:d1b4690b3f8b	3898	{
AnnaBridge	165:d1b4690b3f8b	3899	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
AnnaBridge	165:d1b4690b3f8b	3900	}
AnnaBridge	165:d1b4690b3f8b	3901
AnnaBridge	165:d1b4690b3f8b	3902	#if defined(RCC_PLLP_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	3903	/**
AnnaBridge	165:d1b4690b3f8b	3904	* @brief Get Main PLL division factor for PLLP
AnnaBridge	165:d1b4690b3f8b	3905	* @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
AnnaBridge	165:d1b4690b3f8b	3906	* @rmtoll PLLCFGR PLLPDIV LL_RCC_PLL_GetP
AnnaBridge	165:d1b4690b3f8b	3907	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3908	* @arg @ref LL_RCC_PLLP_DIV_2
AnnaBridge	165:d1b4690b3f8b	3909	* @arg @ref LL_RCC_PLLP_DIV_3
AnnaBridge	165:d1b4690b3f8b	3910	* @arg @ref LL_RCC_PLLP_DIV_4
AnnaBridge	165:d1b4690b3f8b	3911	* @arg @ref LL_RCC_PLLP_DIV_5
AnnaBridge	165:d1b4690b3f8b	3912	* @arg @ref LL_RCC_PLLP_DIV_6
AnnaBridge	165:d1b4690b3f8b	3913	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	165:d1b4690b3f8b	3914	* @arg @ref LL_RCC_PLLP_DIV_8
AnnaBridge	165:d1b4690b3f8b	3915	* @arg @ref LL_RCC_PLLP_DIV_9
AnnaBridge	165:d1b4690b3f8b	3916	* @arg @ref LL_RCC_PLLP_DIV_10
AnnaBridge	165:d1b4690b3f8b	3917	* @arg @ref LL_RCC_PLLP_DIV_11
AnnaBridge	165:d1b4690b3f8b	3918	* @arg @ref LL_RCC_PLLP_DIV_12
AnnaBridge	165:d1b4690b3f8b	3919	* @arg @ref LL_RCC_PLLP_DIV_13
AnnaBridge	165:d1b4690b3f8b	3920	* @arg @ref LL_RCC_PLLP_DIV_14
AnnaBridge	165:d1b4690b3f8b	3921	* @arg @ref LL_RCC_PLLP_DIV_15
AnnaBridge	165:d1b4690b3f8b	3922	* @arg @ref LL_RCC_PLLP_DIV_16
AnnaBridge	165:d1b4690b3f8b	3923	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	165:d1b4690b3f8b	3924	* @arg @ref LL_RCC_PLLP_DIV_18
AnnaBridge	165:d1b4690b3f8b	3925	* @arg @ref LL_RCC_PLLP_DIV_19
AnnaBridge	165:d1b4690b3f8b	3926	* @arg @ref LL_RCC_PLLP_DIV_20
AnnaBridge	165:d1b4690b3f8b	3927	* @arg @ref LL_RCC_PLLP_DIV_21
AnnaBridge	165:d1b4690b3f8b	3928	* @arg @ref LL_RCC_PLLP_DIV_22
AnnaBridge	165:d1b4690b3f8b	3929	* @arg @ref LL_RCC_PLLP_DIV_23
AnnaBridge	165:d1b4690b3f8b	3930	* @arg @ref LL_RCC_PLLP_DIV_24
AnnaBridge	165:d1b4690b3f8b	3931	* @arg @ref LL_RCC_PLLP_DIV_25
AnnaBridge	165:d1b4690b3f8b	3932	* @arg @ref LL_RCC_PLLP_DIV_26
AnnaBridge	165:d1b4690b3f8b	3933	* @arg @ref LL_RCC_PLLP_DIV_27
AnnaBridge	165:d1b4690b3f8b	3934	* @arg @ref LL_RCC_PLLP_DIV_28
AnnaBridge	165:d1b4690b3f8b	3935	* @arg @ref LL_RCC_PLLP_DIV_29
AnnaBridge	165:d1b4690b3f8b	3936	* @arg @ref LL_RCC_PLLP_DIV_30
AnnaBridge	165:d1b4690b3f8b	3937	* @arg @ref LL_RCC_PLLP_DIV_31
AnnaBridge	165:d1b4690b3f8b	3938	*/
AnnaBridge	165:d1b4690b3f8b	3939	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	165:d1b4690b3f8b	3940	{
AnnaBridge	165:d1b4690b3f8b	3941	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPDIV));
AnnaBridge	165:d1b4690b3f8b	3942	}
AnnaBridge	165:d1b4690b3f8b	3943	#else
AnnaBridge	165:d1b4690b3f8b	3944	/**
AnnaBridge	165:d1b4690b3f8b	3945	* @brief Get Main PLL division factor for PLLP
AnnaBridge	165:d1b4690b3f8b	3946	* @note Used for PLLSAI3CLK (SAI1 and SAI2 clock)
AnnaBridge	165:d1b4690b3f8b	3947	* @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
AnnaBridge	165:d1b4690b3f8b	3948	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3949	* @arg @ref LL_RCC_PLLP_DIV_7
AnnaBridge	165:d1b4690b3f8b	3950	* @arg @ref LL_RCC_PLLP_DIV_17
AnnaBridge	165:d1b4690b3f8b	3951	*/
AnnaBridge	165:d1b4690b3f8b	3952	__STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
AnnaBridge	165:d1b4690b3f8b	3953	{
AnnaBridge	165:d1b4690b3f8b	3954	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
AnnaBridge	165:d1b4690b3f8b	3955	}
AnnaBridge	165:d1b4690b3f8b	3956	#endif /* RCC_PLLP_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	3957
AnnaBridge	165:d1b4690b3f8b	3958	/**
AnnaBridge	165:d1b4690b3f8b	3959	* @brief Get Main PLL division factor for PLLQ
AnnaBridge	165:d1b4690b3f8b	3960	* @note Used for PLL48M1CLK selected for USB, RNG, SDMMC (48 MHz clock)
AnnaBridge	165:d1b4690b3f8b	3961	* @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
AnnaBridge	165:d1b4690b3f8b	3962	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3963	* @arg @ref LL_RCC_PLLQ_DIV_2
AnnaBridge	165:d1b4690b3f8b	3964	* @arg @ref LL_RCC_PLLQ_DIV_4
AnnaBridge	165:d1b4690b3f8b	3965	* @arg @ref LL_RCC_PLLQ_DIV_6
AnnaBridge	165:d1b4690b3f8b	3966	* @arg @ref LL_RCC_PLLQ_DIV_8
AnnaBridge	165:d1b4690b3f8b	3967	*/
AnnaBridge	165:d1b4690b3f8b	3968	__STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
AnnaBridge	165:d1b4690b3f8b	3969	{
AnnaBridge	165:d1b4690b3f8b	3970	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
AnnaBridge	165:d1b4690b3f8b	3971	}
AnnaBridge	165:d1b4690b3f8b	3972
AnnaBridge	165:d1b4690b3f8b	3973	/**
AnnaBridge	165:d1b4690b3f8b	3974	* @brief Get Main PLL division factor for PLLR
AnnaBridge	165:d1b4690b3f8b	3975	* @note Used for PLLCLK (system clock)
AnnaBridge	165:d1b4690b3f8b	3976	* @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
AnnaBridge	165:d1b4690b3f8b	3977	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3978	* @arg @ref LL_RCC_PLLR_DIV_2
AnnaBridge	165:d1b4690b3f8b	3979	* @arg @ref LL_RCC_PLLR_DIV_4
AnnaBridge	165:d1b4690b3f8b	3980	* @arg @ref LL_RCC_PLLR_DIV_6
AnnaBridge	165:d1b4690b3f8b	3981	* @arg @ref LL_RCC_PLLR_DIV_8
AnnaBridge	165:d1b4690b3f8b	3982	*/
AnnaBridge	165:d1b4690b3f8b	3983	__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
AnnaBridge	165:d1b4690b3f8b	3984	{
AnnaBridge	165:d1b4690b3f8b	3985	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
AnnaBridge	165:d1b4690b3f8b	3986	}
AnnaBridge	165:d1b4690b3f8b	3987
AnnaBridge	165:d1b4690b3f8b	3988	/**
AnnaBridge	165:d1b4690b3f8b	3989	* @brief Get Division factor for the main PLL and other PLL
AnnaBridge	165:d1b4690b3f8b	3990	* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
AnnaBridge	165:d1b4690b3f8b	3991	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	3992	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	3993	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	3994	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	3995	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	3996	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	3997	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	3998	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	3999	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4000	* @arg @ref LL_RCC_PLLM_DIV_9 (*)
AnnaBridge	165:d1b4690b3f8b	4001	* @arg @ref LL_RCC_PLLM_DIV_10 (*)
AnnaBridge	165:d1b4690b3f8b	4002	* @arg @ref LL_RCC_PLLM_DIV_11 (*)
AnnaBridge	165:d1b4690b3f8b	4003	* @arg @ref LL_RCC_PLLM_DIV_12 (*)
AnnaBridge	165:d1b4690b3f8b	4004	* @arg @ref LL_RCC_PLLM_DIV_13 (*)
AnnaBridge	165:d1b4690b3f8b	4005	* @arg @ref LL_RCC_PLLM_DIV_14 (*)
AnnaBridge	165:d1b4690b3f8b	4006	* @arg @ref LL_RCC_PLLM_DIV_15 (*)
AnnaBridge	165:d1b4690b3f8b	4007	* @arg @ref LL_RCC_PLLM_DIV_16 (*)
AnnaBridge	165:d1b4690b3f8b	4008	*
AnnaBridge	165:d1b4690b3f8b	4009	* (*) value not defined in all devices.
AnnaBridge	165:d1b4690b3f8b	4010	*/
AnnaBridge	165:d1b4690b3f8b	4011	__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
AnnaBridge	165:d1b4690b3f8b	4012	{
AnnaBridge	165:d1b4690b3f8b	4013	return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
AnnaBridge	165:d1b4690b3f8b	4014	}
AnnaBridge	165:d1b4690b3f8b	4015
AnnaBridge	165:d1b4690b3f8b	4016	/**
AnnaBridge	165:d1b4690b3f8b	4017	* @brief Enable PLL output mapped on SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4018	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_EnableDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4019	* @retval None
AnnaBridge	165:d1b4690b3f8b	4020	*/
AnnaBridge	165:d1b4690b3f8b	4021	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SAI(void)
AnnaBridge	165:d1b4690b3f8b	4022	{
AnnaBridge	165:d1b4690b3f8b	4023	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
AnnaBridge	165:d1b4690b3f8b	4024	}
AnnaBridge	165:d1b4690b3f8b	4025
AnnaBridge	165:d1b4690b3f8b	4026	/**
AnnaBridge	165:d1b4690b3f8b	4027	* @brief Disable PLL output mapped on SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4028	* @note Cannot be disabled if the PLL clock is used as the system
AnnaBridge	165:d1b4690b3f8b	4029	* clock
AnnaBridge	165:d1b4690b3f8b	4030	* @note In order to save power, when the PLLCLK of the PLL is
AnnaBridge	165:d1b4690b3f8b	4031	* not used, should be 0
AnnaBridge	165:d1b4690b3f8b	4032	* @rmtoll PLLCFGR PLLPEN LL_RCC_PLL_DisableDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4033	* @retval None
AnnaBridge	165:d1b4690b3f8b	4034	*/
AnnaBridge	165:d1b4690b3f8b	4035	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SAI(void)
AnnaBridge	165:d1b4690b3f8b	4036	{
AnnaBridge	165:d1b4690b3f8b	4037	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLPEN);
AnnaBridge	165:d1b4690b3f8b	4038	}
AnnaBridge	165:d1b4690b3f8b	4039
AnnaBridge	165:d1b4690b3f8b	4040	/**
AnnaBridge	165:d1b4690b3f8b	4041	* @brief Enable PLL output mapped on 48MHz domain clock
AnnaBridge	165:d1b4690b3f8b	4042	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_EnableDomain_48M
AnnaBridge	165:d1b4690b3f8b	4043	* @retval None
AnnaBridge	165:d1b4690b3f8b	4044	*/
AnnaBridge	165:d1b4690b3f8b	4045	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_48M(void)
AnnaBridge	165:d1b4690b3f8b	4046	{
AnnaBridge	165:d1b4690b3f8b	4047	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
AnnaBridge	165:d1b4690b3f8b	4048	}
AnnaBridge	165:d1b4690b3f8b	4049
AnnaBridge	165:d1b4690b3f8b	4050	/**
AnnaBridge	165:d1b4690b3f8b	4051	* @brief Disable PLL output mapped on 48MHz domain clock
AnnaBridge	165:d1b4690b3f8b	4052	* @note Cannot be disabled if the PLL clock is used as the system
AnnaBridge	165:d1b4690b3f8b	4053	* clock
AnnaBridge	165:d1b4690b3f8b	4054	* @note In order to save power, when the PLLCLK of the PLL is
AnnaBridge	165:d1b4690b3f8b	4055	* not used, should be 0
AnnaBridge	165:d1b4690b3f8b	4056	* @rmtoll PLLCFGR PLLQEN LL_RCC_PLL_DisableDomain_48M
AnnaBridge	165:d1b4690b3f8b	4057	* @retval None
AnnaBridge	165:d1b4690b3f8b	4058	*/
AnnaBridge	165:d1b4690b3f8b	4059	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_48M(void)
AnnaBridge	165:d1b4690b3f8b	4060	{
AnnaBridge	165:d1b4690b3f8b	4061	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQEN);
AnnaBridge	165:d1b4690b3f8b	4062	}
AnnaBridge	165:d1b4690b3f8b	4063
AnnaBridge	165:d1b4690b3f8b	4064	/**
AnnaBridge	165:d1b4690b3f8b	4065	* @brief Enable PLL output mapped on SYSCLK domain
AnnaBridge	165:d1b4690b3f8b	4066	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_EnableDomain_SYS
AnnaBridge	165:d1b4690b3f8b	4067	* @retval None
AnnaBridge	165:d1b4690b3f8b	4068	*/
AnnaBridge	165:d1b4690b3f8b	4069	__STATIC_INLINE void LL_RCC_PLL_EnableDomain_SYS(void)
AnnaBridge	165:d1b4690b3f8b	4070	{
AnnaBridge	165:d1b4690b3f8b	4071	SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
AnnaBridge	165:d1b4690b3f8b	4072	}
AnnaBridge	165:d1b4690b3f8b	4073
AnnaBridge	165:d1b4690b3f8b	4074	/**
AnnaBridge	165:d1b4690b3f8b	4075	* @brief Disable PLL output mapped on SYSCLK domain
AnnaBridge	165:d1b4690b3f8b	4076	* @note Cannot be disabled if the PLL clock is used as the system
AnnaBridge	165:d1b4690b3f8b	4077	* clock
AnnaBridge	165:d1b4690b3f8b	4078	* @note In order to save power, when the PLLCLK of the PLL is
AnnaBridge	165:d1b4690b3f8b	4079	* not used, Main PLL should be 0
AnnaBridge	165:d1b4690b3f8b	4080	* @rmtoll PLLCFGR PLLREN LL_RCC_PLL_DisableDomain_SYS
AnnaBridge	165:d1b4690b3f8b	4081	* @retval None
AnnaBridge	165:d1b4690b3f8b	4082	*/
AnnaBridge	165:d1b4690b3f8b	4083	__STATIC_INLINE void LL_RCC_PLL_DisableDomain_SYS(void)
AnnaBridge	165:d1b4690b3f8b	4084	{
AnnaBridge	165:d1b4690b3f8b	4085	CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLREN);
AnnaBridge	165:d1b4690b3f8b	4086	}
AnnaBridge	165:d1b4690b3f8b	4087
AnnaBridge	165:d1b4690b3f8b	4088	/**
AnnaBridge	165:d1b4690b3f8b	4089	* @}
AnnaBridge	165:d1b4690b3f8b	4090	*/
AnnaBridge	165:d1b4690b3f8b	4091
AnnaBridge	165:d1b4690b3f8b	4092	/** @defgroup RCC_LL_EF_PLLSAI1 PLLSAI1
AnnaBridge	165:d1b4690b3f8b	4093	* @{
AnnaBridge	165:d1b4690b3f8b	4094	*/
AnnaBridge	165:d1b4690b3f8b	4095
AnnaBridge	165:d1b4690b3f8b	4096	/**
AnnaBridge	165:d1b4690b3f8b	4097	* @brief Enable PLLSAI1
AnnaBridge	165:d1b4690b3f8b	4098	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Enable
AnnaBridge	165:d1b4690b3f8b	4099	* @retval None
AnnaBridge	165:d1b4690b3f8b	4100	*/
AnnaBridge	165:d1b4690b3f8b	4101	__STATIC_INLINE void LL_RCC_PLLSAI1_Enable(void)
AnnaBridge	165:d1b4690b3f8b	4102	{
AnnaBridge	165:d1b4690b3f8b	4103	SET_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
AnnaBridge	165:d1b4690b3f8b	4104	}
AnnaBridge	165:d1b4690b3f8b	4105
AnnaBridge	165:d1b4690b3f8b	4106	/**
AnnaBridge	165:d1b4690b3f8b	4107	* @brief Disable PLLSAI1
AnnaBridge	165:d1b4690b3f8b	4108	* @rmtoll CR PLLSAI1ON LL_RCC_PLLSAI1_Disable
AnnaBridge	165:d1b4690b3f8b	4109	* @retval None
AnnaBridge	165:d1b4690b3f8b	4110	*/
AnnaBridge	165:d1b4690b3f8b	4111	__STATIC_INLINE void LL_RCC_PLLSAI1_Disable(void)
AnnaBridge	165:d1b4690b3f8b	4112	{
AnnaBridge	165:d1b4690b3f8b	4113	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI1ON);
AnnaBridge	165:d1b4690b3f8b	4114	}
AnnaBridge	165:d1b4690b3f8b	4115
AnnaBridge	165:d1b4690b3f8b	4116	/**
AnnaBridge	165:d1b4690b3f8b	4117	* @brief Check if PLLSAI1 Ready
AnnaBridge	165:d1b4690b3f8b	4118	* @rmtoll CR PLLSAI1RDY LL_RCC_PLLSAI1_IsReady
AnnaBridge	165:d1b4690b3f8b	4119	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4120	*/
AnnaBridge	165:d1b4690b3f8b	4121	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	4122	{
AnnaBridge	165:d1b4690b3f8b	4123	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI1RDY) == (RCC_CR_PLLSAI1RDY));
AnnaBridge	165:d1b4690b3f8b	4124	}
AnnaBridge	165:d1b4690b3f8b	4125
AnnaBridge	165:d1b4690b3f8b	4126	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4127	/**
AnnaBridge	165:d1b4690b3f8b	4128	* @brief Configure PLLSAI1 used for 48Mhz domain clock
AnnaBridge	165:d1b4690b3f8b	4129	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4130	* @note PLLSAI1M/PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4131	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	165:d1b4690b3f8b	4132	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	4133	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	4134	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	4135	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
AnnaBridge	165:d1b4690b3f8b	4136	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4137	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4138	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4139	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4140	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4141	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4142	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4143	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4144	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4145	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4146	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4147	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4148	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4149	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4150	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4151	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4152	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4153	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4154	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4155	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4156	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4157	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4158	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4159	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4160	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	4161	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	4162	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	4163	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	4164	* @retval None
AnnaBridge	165:d1b4690b3f8b	4165	*/
AnnaBridge	165:d1b4690b3f8b	4166	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	165:d1b4690b3f8b	4167	{
AnnaBridge	165:d1b4690b3f8b	4168	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	165:d1b4690b3f8b	4169	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q,
AnnaBridge	165:d1b4690b3f8b	4170	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
AnnaBridge	165:d1b4690b3f8b	4171	}
AnnaBridge	165:d1b4690b3f8b	4172	#else
AnnaBridge	165:d1b4690b3f8b	4173	/**
AnnaBridge	165:d1b4690b3f8b	4174	* @brief Configure PLLSAI1 used for 48Mhz domain clock
AnnaBridge	165:d1b4690b3f8b	4175	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4176	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4177	* @note PLLSAI1N/PLLSAI1Q can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4178	* @note This can be selected for USB, RNG, SDMMC
AnnaBridge	165:d1b4690b3f8b	4179	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	4180	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	4181	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_48M\n
AnnaBridge	165:d1b4690b3f8b	4182	* PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_ConfigDomain_48M
AnnaBridge	165:d1b4690b3f8b	4183	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4184	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4185	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4186	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4187	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4188	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4189	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4190	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4191	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4192	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4193	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4194	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4195	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4196	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4197	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4198	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4199	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	4200	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	4201	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	4202	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	4203	* @retval None
AnnaBridge	165:d1b4690b3f8b	4204	*/
AnnaBridge	165:d1b4690b3f8b	4205	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	165:d1b4690b3f8b	4206	{
AnnaBridge	165:d1b4690b3f8b	4207	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4208	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1Q, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLQ);
AnnaBridge	165:d1b4690b3f8b	4209	}
AnnaBridge	165:d1b4690b3f8b	4210	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	4211
AnnaBridge	165:d1b4690b3f8b	4212	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4213	/**
AnnaBridge	165:d1b4690b3f8b	4214	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4215	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4216	* @note PLLSAI1M/PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4217	* @note This can be selected for SAI1 or SAI2
AnnaBridge	165:d1b4690b3f8b	4218	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4219	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4220	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4221	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4222	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4223	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4224	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4225	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4226	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4227	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4228	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4229	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4230	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4231	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4232	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4233	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4234	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4235	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4236	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4237	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4238	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4239	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4240	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4241	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4242	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4243	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4244	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4245	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4246	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	165:d1b4690b3f8b	4247	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	165:d1b4690b3f8b	4248	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	165:d1b4690b3f8b	4249	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	165:d1b4690b3f8b	4250	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	165:d1b4690b3f8b	4251	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4252	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	165:d1b4690b3f8b	4253	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	165:d1b4690b3f8b	4254	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	165:d1b4690b3f8b	4255	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	165:d1b4690b3f8b	4256	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	165:d1b4690b3f8b	4257	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	165:d1b4690b3f8b	4258	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	165:d1b4690b3f8b	4259	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	165:d1b4690b3f8b	4260	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	165:d1b4690b3f8b	4261	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4262	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	165:d1b4690b3f8b	4263	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	165:d1b4690b3f8b	4264	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	165:d1b4690b3f8b	4265	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	165:d1b4690b3f8b	4266	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	165:d1b4690b3f8b	4267	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	165:d1b4690b3f8b	4268	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	165:d1b4690b3f8b	4269	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	165:d1b4690b3f8b	4270	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	165:d1b4690b3f8b	4271	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	165:d1b4690b3f8b	4272	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	165:d1b4690b3f8b	4273	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	165:d1b4690b3f8b	4274	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	165:d1b4690b3f8b	4275	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	165:d1b4690b3f8b	4276	* @retval None
AnnaBridge	165:d1b4690b3f8b	4277	*/
AnnaBridge	165:d1b4690b3f8b	4278	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	4279	{
AnnaBridge	165:d1b4690b3f8b	4280	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	165:d1b4690b3f8b	4281	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	165:d1b4690b3f8b	4282	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	4283	}
AnnaBridge	165:d1b4690b3f8b	4284	#elif defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4285	/**
AnnaBridge	165:d1b4690b3f8b	4286	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4287	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4288	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4289	* @note PLLSAI1N/PLLSAI1PDIV can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4290	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	165:d1b4690b3f8b	4291	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4292	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4293	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4294	* PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4295	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4296	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4297	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4298	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4299	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4300	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4301	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4302	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4303	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4304	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4305	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4306	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4307	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4308	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4309	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4310	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4311	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	165:d1b4690b3f8b	4312	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	165:d1b4690b3f8b	4313	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	165:d1b4690b3f8b	4314	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	165:d1b4690b3f8b	4315	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	165:d1b4690b3f8b	4316	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4317	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	165:d1b4690b3f8b	4318	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	165:d1b4690b3f8b	4319	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	165:d1b4690b3f8b	4320	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	165:d1b4690b3f8b	4321	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	165:d1b4690b3f8b	4322	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	165:d1b4690b3f8b	4323	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	165:d1b4690b3f8b	4324	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	165:d1b4690b3f8b	4325	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	165:d1b4690b3f8b	4326	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4327	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	165:d1b4690b3f8b	4328	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	165:d1b4690b3f8b	4329	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	165:d1b4690b3f8b	4330	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	165:d1b4690b3f8b	4331	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	165:d1b4690b3f8b	4332	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	165:d1b4690b3f8b	4333	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	165:d1b4690b3f8b	4334	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	165:d1b4690b3f8b	4335	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	165:d1b4690b3f8b	4336	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	165:d1b4690b3f8b	4337	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	165:d1b4690b3f8b	4338	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	165:d1b4690b3f8b	4339	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	165:d1b4690b3f8b	4340	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	165:d1b4690b3f8b	4341	* @retval None
AnnaBridge	165:d1b4690b3f8b	4342	*/
AnnaBridge	165:d1b4690b3f8b	4343	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	4344	{
AnnaBridge	165:d1b4690b3f8b	4345	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4346	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1PDIV,
AnnaBridge	165:d1b4690b3f8b	4347	PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	4348	}
AnnaBridge	165:d1b4690b3f8b	4349	#else
AnnaBridge	165:d1b4690b3f8b	4350	/**
AnnaBridge	165:d1b4690b3f8b	4351	* @brief Configure PLLSAI1 used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4352	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4353	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4354	* @note PLLSAI1N/PLLSAI1P can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4355	* @note This can be selected for SAI1 or SAI2 (*)
AnnaBridge	165:d1b4690b3f8b	4356	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4357	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4358	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4359	* PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4360	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4361	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4362	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4363	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4364	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4365	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4366	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4367	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4368	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4369	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4370	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4371	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4372	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4373	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4374	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4375	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4376	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4377	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4378	* @retval None
AnnaBridge	165:d1b4690b3f8b	4379	*/
AnnaBridge	165:d1b4690b3f8b	4380	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	4381	{
AnnaBridge	165:d1b4690b3f8b	4382	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4383	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1P, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	4384	}
AnnaBridge	165:d1b4690b3f8b	4385	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT && RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	4386
AnnaBridge	165:d1b4690b3f8b	4387	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4388	/**
AnnaBridge	165:d1b4690b3f8b	4389	* @brief Configure PLLSAI1 used for ADC domain clock
AnnaBridge	165:d1b4690b3f8b	4390	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4391	* @note PLLSAI1M/PLLSAI1N/PLLSAI1R can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4392	* @note This can be selected for ADC
AnnaBridge	165:d1b4690b3f8b	4393	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4394	* PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4395	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4396	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
AnnaBridge	165:d1b4690b3f8b	4397	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4398	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4399	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4400	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4401	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4402	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4403	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4404	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4405	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4406	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4407	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4408	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4409	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4410	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4411	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4412	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4413	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4414	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4415	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4416	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4417	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4418	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4419	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4420	* @param PLLR This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4421	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	165:d1b4690b3f8b	4422	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	165:d1b4690b3f8b	4423	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	165:d1b4690b3f8b	4424	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	165:d1b4690b3f8b	4425	* @retval None
AnnaBridge	165:d1b4690b3f8b	4426	*/
AnnaBridge	165:d1b4690b3f8b	4427	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	165:d1b4690b3f8b	4428	{
AnnaBridge	165:d1b4690b3f8b	4429	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	165:d1b4690b3f8b	4430	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M \| RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R,
AnnaBridge	165:d1b4690b3f8b	4431	PLLM \| PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
AnnaBridge	165:d1b4690b3f8b	4432	}
AnnaBridge	165:d1b4690b3f8b	4433	#else
AnnaBridge	165:d1b4690b3f8b	4434	/**
AnnaBridge	165:d1b4690b3f8b	4435	* @brief Configure PLLSAI1 used for ADC domain clock
AnnaBridge	165:d1b4690b3f8b	4436	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4437	* PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4438	* @note PLLN/PLLR can be written only when PLLSAI1 is disabled.
AnnaBridge	165:d1b4690b3f8b	4439	* @note This can be selected for ADC
AnnaBridge	165:d1b4690b3f8b	4440	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4441	* PLLCFGR PLLM LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4442	* PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4443	* PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_ConfigDomain_ADC
AnnaBridge	165:d1b4690b3f8b	4444	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4445	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4446	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4447	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4448	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4449	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4450	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4451	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4452	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4453	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4454	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4455	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4456	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4457	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4458	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4459	* @param PLLR This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4460	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	165:d1b4690b3f8b	4461	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	165:d1b4690b3f8b	4462	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	165:d1b4690b3f8b	4463	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	165:d1b4690b3f8b	4464	* @retval None
AnnaBridge	165:d1b4690b3f8b	4465	*/
AnnaBridge	165:d1b4690b3f8b	4466	__STATIC_INLINE void LL_RCC_PLLSAI1_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	165:d1b4690b3f8b	4467	{
AnnaBridge	165:d1b4690b3f8b	4468	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4469	MODIFY_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N \| RCC_PLLSAI1CFGR_PLLSAI1R, PLLN << RCC_PLLSAI1CFGR_PLLSAI1N_Pos \| PLLR);
AnnaBridge	165:d1b4690b3f8b	4470	}
AnnaBridge	165:d1b4690b3f8b	4471	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	4472
AnnaBridge	165:d1b4690b3f8b	4473	/**
AnnaBridge	165:d1b4690b3f8b	4474	* @brief Get SAI1PLL multiplication factor for VCO
AnnaBridge	165:d1b4690b3f8b	4475	* @rmtoll PLLSAI1CFGR PLLSAI1N LL_RCC_PLLSAI1_GetN
AnnaBridge	165:d1b4690b3f8b	4476	* @retval Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4477	*/
AnnaBridge	165:d1b4690b3f8b	4478	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetN(void)
AnnaBridge	165:d1b4690b3f8b	4479	{
AnnaBridge	165:d1b4690b3f8b	4480	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1N) >> RCC_PLLSAI1CFGR_PLLSAI1N_Pos);
AnnaBridge	165:d1b4690b3f8b	4481	}
AnnaBridge	165:d1b4690b3f8b	4482
AnnaBridge	165:d1b4690b3f8b	4483	#if defined(RCC_PLLSAI1P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4484	/**
AnnaBridge	165:d1b4690b3f8b	4485	* @brief Get SAI1PLL division factor for PLLSAI1P
AnnaBridge	165:d1b4690b3f8b	4486	* @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
AnnaBridge	165:d1b4690b3f8b	4487	* @rmtoll PLLSAI1CFGR PLLSAI1PDIV LL_RCC_PLLSAI1_GetP
AnnaBridge	165:d1b4690b3f8b	4488	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4489	* @arg @ref LL_RCC_PLLSAI1P_DIV_2
AnnaBridge	165:d1b4690b3f8b	4490	* @arg @ref LL_RCC_PLLSAI1P_DIV_3
AnnaBridge	165:d1b4690b3f8b	4491	* @arg @ref LL_RCC_PLLSAI1P_DIV_4
AnnaBridge	165:d1b4690b3f8b	4492	* @arg @ref LL_RCC_PLLSAI1P_DIV_5
AnnaBridge	165:d1b4690b3f8b	4493	* @arg @ref LL_RCC_PLLSAI1P_DIV_6
AnnaBridge	165:d1b4690b3f8b	4494	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4495	* @arg @ref LL_RCC_PLLSAI1P_DIV_8
AnnaBridge	165:d1b4690b3f8b	4496	* @arg @ref LL_RCC_PLLSAI1P_DIV_9
AnnaBridge	165:d1b4690b3f8b	4497	* @arg @ref LL_RCC_PLLSAI1P_DIV_10
AnnaBridge	165:d1b4690b3f8b	4498	* @arg @ref LL_RCC_PLLSAI1P_DIV_11
AnnaBridge	165:d1b4690b3f8b	4499	* @arg @ref LL_RCC_PLLSAI1P_DIV_12
AnnaBridge	165:d1b4690b3f8b	4500	* @arg @ref LL_RCC_PLLSAI1P_DIV_13
AnnaBridge	165:d1b4690b3f8b	4501	* @arg @ref LL_RCC_PLLSAI1P_DIV_14
AnnaBridge	165:d1b4690b3f8b	4502	* @arg @ref LL_RCC_PLLSAI1P_DIV_15
AnnaBridge	165:d1b4690b3f8b	4503	* @arg @ref LL_RCC_PLLSAI1P_DIV_16
AnnaBridge	165:d1b4690b3f8b	4504	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4505	* @arg @ref LL_RCC_PLLSAI1P_DIV_18
AnnaBridge	165:d1b4690b3f8b	4506	* @arg @ref LL_RCC_PLLSAI1P_DIV_19
AnnaBridge	165:d1b4690b3f8b	4507	* @arg @ref LL_RCC_PLLSAI1P_DIV_20
AnnaBridge	165:d1b4690b3f8b	4508	* @arg @ref LL_RCC_PLLSAI1P_DIV_21
AnnaBridge	165:d1b4690b3f8b	4509	* @arg @ref LL_RCC_PLLSAI1P_DIV_22
AnnaBridge	165:d1b4690b3f8b	4510	* @arg @ref LL_RCC_PLLSAI1P_DIV_23
AnnaBridge	165:d1b4690b3f8b	4511	* @arg @ref LL_RCC_PLLSAI1P_DIV_24
AnnaBridge	165:d1b4690b3f8b	4512	* @arg @ref LL_RCC_PLLSAI1P_DIV_25
AnnaBridge	165:d1b4690b3f8b	4513	* @arg @ref LL_RCC_PLLSAI1P_DIV_26
AnnaBridge	165:d1b4690b3f8b	4514	* @arg @ref LL_RCC_PLLSAI1P_DIV_27
AnnaBridge	165:d1b4690b3f8b	4515	* @arg @ref LL_RCC_PLLSAI1P_DIV_28
AnnaBridge	165:d1b4690b3f8b	4516	* @arg @ref LL_RCC_PLLSAI1P_DIV_29
AnnaBridge	165:d1b4690b3f8b	4517	* @arg @ref LL_RCC_PLLSAI1P_DIV_30
AnnaBridge	165:d1b4690b3f8b	4518	* @arg @ref LL_RCC_PLLSAI1P_DIV_31
AnnaBridge	165:d1b4690b3f8b	4519	*/
AnnaBridge	165:d1b4690b3f8b	4520	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
AnnaBridge	165:d1b4690b3f8b	4521	{
AnnaBridge	165:d1b4690b3f8b	4522	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PDIV));
AnnaBridge	165:d1b4690b3f8b	4523	}
AnnaBridge	165:d1b4690b3f8b	4524	#else
AnnaBridge	165:d1b4690b3f8b	4525	/**
AnnaBridge	165:d1b4690b3f8b	4526	* @brief Get SAI1PLL division factor for PLLSAI1P
AnnaBridge	165:d1b4690b3f8b	4527	* @note Used for PLLSAI1CLK (SAI1 or SAI2 (*) clock).
AnnaBridge	165:d1b4690b3f8b	4528	* @rmtoll PLLSAI1CFGR PLLSAI1P LL_RCC_PLLSAI1_GetP
AnnaBridge	165:d1b4690b3f8b	4529	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4530	* @arg @ref LL_RCC_PLLSAI1P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4531	* @arg @ref LL_RCC_PLLSAI1P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4532	*/
AnnaBridge	165:d1b4690b3f8b	4533	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetP(void)
AnnaBridge	165:d1b4690b3f8b	4534	{
AnnaBridge	165:d1b4690b3f8b	4535	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1P));
AnnaBridge	165:d1b4690b3f8b	4536	}
AnnaBridge	165:d1b4690b3f8b	4537	#endif /* RCC_PLLSAI1P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	4538
AnnaBridge	165:d1b4690b3f8b	4539	/**
AnnaBridge	165:d1b4690b3f8b	4540	* @brief Get SAI1PLL division factor for PLLSAI1Q
AnnaBridge	165:d1b4690b3f8b	4541	* @note Used PLL48M2CLK selected for USB, RNG, SDMMC (48 MHz clock)
AnnaBridge	165:d1b4690b3f8b	4542	* @rmtoll PLLSAI1CFGR PLLSAI1Q LL_RCC_PLLSAI1_GetQ
AnnaBridge	165:d1b4690b3f8b	4543	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4544	* @arg @ref LL_RCC_PLLSAI1Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	4545	* @arg @ref LL_RCC_PLLSAI1Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	4546	* @arg @ref LL_RCC_PLLSAI1Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	4547	* @arg @ref LL_RCC_PLLSAI1Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	4548	*/
AnnaBridge	165:d1b4690b3f8b	4549	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetQ(void)
AnnaBridge	165:d1b4690b3f8b	4550	{
AnnaBridge	165:d1b4690b3f8b	4551	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1Q));
AnnaBridge	165:d1b4690b3f8b	4552	}
AnnaBridge	165:d1b4690b3f8b	4553
AnnaBridge	165:d1b4690b3f8b	4554	/**
AnnaBridge	165:d1b4690b3f8b	4555	* @brief Get PLLSAI1 division factor for PLLSAIR
AnnaBridge	165:d1b4690b3f8b	4556	* @note Used for PLLADC1CLK (ADC clock)
AnnaBridge	165:d1b4690b3f8b	4557	* @rmtoll PLLSAI1CFGR PLLSAI1R LL_RCC_PLLSAI1_GetR
AnnaBridge	165:d1b4690b3f8b	4558	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4559	* @arg @ref LL_RCC_PLLSAI1R_DIV_2
AnnaBridge	165:d1b4690b3f8b	4560	* @arg @ref LL_RCC_PLLSAI1R_DIV_4
AnnaBridge	165:d1b4690b3f8b	4561	* @arg @ref LL_RCC_PLLSAI1R_DIV_6
AnnaBridge	165:d1b4690b3f8b	4562	* @arg @ref LL_RCC_PLLSAI1R_DIV_8
AnnaBridge	165:d1b4690b3f8b	4563	*/
AnnaBridge	165:d1b4690b3f8b	4564	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetR(void)
AnnaBridge	165:d1b4690b3f8b	4565	{
AnnaBridge	165:d1b4690b3f8b	4566	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1R));
AnnaBridge	165:d1b4690b3f8b	4567	}
AnnaBridge	165:d1b4690b3f8b	4568
AnnaBridge	165:d1b4690b3f8b	4569	#if defined(RCC_PLLSAI1M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4570	/**
AnnaBridge	165:d1b4690b3f8b	4571	* @brief Get Division factor for the PLLSAI1
AnnaBridge	165:d1b4690b3f8b	4572	* @rmtoll PLLSAI1CFGR PLLSAI1M LL_RCC_PLLSAI1_GetDivider
AnnaBridge	165:d1b4690b3f8b	4573	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4574	* @arg @ref LL_RCC_PLLSAI1M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4575	* @arg @ref LL_RCC_PLLSAI1M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4576	* @arg @ref LL_RCC_PLLSAI1M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4577	* @arg @ref LL_RCC_PLLSAI1M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4578	* @arg @ref LL_RCC_PLLSAI1M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4579	* @arg @ref LL_RCC_PLLSAI1M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4580	* @arg @ref LL_RCC_PLLSAI1M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4581	* @arg @ref LL_RCC_PLLSAI1M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4582	* @arg @ref LL_RCC_PLLSAI1M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4583	* @arg @ref LL_RCC_PLLSAI1M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4584	* @arg @ref LL_RCC_PLLSAI1M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4585	* @arg @ref LL_RCC_PLLSAI1M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4586	* @arg @ref LL_RCC_PLLSAI1M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4587	* @arg @ref LL_RCC_PLLSAI1M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4588	* @arg @ref LL_RCC_PLLSAI1M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4589	* @arg @ref LL_RCC_PLLSAI1M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4590	*/
AnnaBridge	165:d1b4690b3f8b	4591	__STATIC_INLINE uint32_t LL_RCC_PLLSAI1_GetDivider(void)
AnnaBridge	165:d1b4690b3f8b	4592	{
AnnaBridge	165:d1b4690b3f8b	4593	return (uint32_t)(READ_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1M));
AnnaBridge	165:d1b4690b3f8b	4594	}
AnnaBridge	165:d1b4690b3f8b	4595	#endif /* RCC_PLLSAI1M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	4596
AnnaBridge	165:d1b4690b3f8b	4597	/**
AnnaBridge	165:d1b4690b3f8b	4598	* @brief Enable PLLSAI1 output mapped on SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4599	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_EnableDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4600	* @retval None
AnnaBridge	165:d1b4690b3f8b	4601	*/
AnnaBridge	165:d1b4690b3f8b	4602	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_SAI(void)
AnnaBridge	165:d1b4690b3f8b	4603	{
AnnaBridge	165:d1b4690b3f8b	4604	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
AnnaBridge	165:d1b4690b3f8b	4605	}
AnnaBridge	165:d1b4690b3f8b	4606
AnnaBridge	165:d1b4690b3f8b	4607	/**
AnnaBridge	165:d1b4690b3f8b	4608	* @brief Disable PLLSAI1 output mapped on SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4609	* @note In order to save power, when of the PLLSAI1 is
AnnaBridge	165:d1b4690b3f8b	4610	* not used, should be 0
AnnaBridge	165:d1b4690b3f8b	4611	* @rmtoll PLLSAI1CFGR PLLSAI1PEN LL_RCC_PLLSAI1_DisableDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4612	* @retval None
AnnaBridge	165:d1b4690b3f8b	4613	*/
AnnaBridge	165:d1b4690b3f8b	4614	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_SAI(void)
AnnaBridge	165:d1b4690b3f8b	4615	{
AnnaBridge	165:d1b4690b3f8b	4616	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1PEN);
AnnaBridge	165:d1b4690b3f8b	4617	}
AnnaBridge	165:d1b4690b3f8b	4618
AnnaBridge	165:d1b4690b3f8b	4619	/**
AnnaBridge	165:d1b4690b3f8b	4620	* @brief Enable PLLSAI1 output mapped on 48MHz domain clock
AnnaBridge	165:d1b4690b3f8b	4621	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_EnableDomain_48M
AnnaBridge	165:d1b4690b3f8b	4622	* @retval None
AnnaBridge	165:d1b4690b3f8b	4623	*/
AnnaBridge	165:d1b4690b3f8b	4624	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_48M(void)
AnnaBridge	165:d1b4690b3f8b	4625	{
AnnaBridge	165:d1b4690b3f8b	4626	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
AnnaBridge	165:d1b4690b3f8b	4627	}
AnnaBridge	165:d1b4690b3f8b	4628
AnnaBridge	165:d1b4690b3f8b	4629	/**
AnnaBridge	165:d1b4690b3f8b	4630	* @brief Disable PLLSAI1 output mapped on 48MHz domain clock
AnnaBridge	165:d1b4690b3f8b	4631	* @note In order to save power, when of the PLLSAI1 is
AnnaBridge	165:d1b4690b3f8b	4632	* not used, should be 0
AnnaBridge	165:d1b4690b3f8b	4633	* @rmtoll PLLSAI1CFGR PLLSAI1QEN LL_RCC_PLLSAI1_DisableDomain_48M
AnnaBridge	165:d1b4690b3f8b	4634	* @retval None
AnnaBridge	165:d1b4690b3f8b	4635	*/
AnnaBridge	165:d1b4690b3f8b	4636	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_48M(void)
AnnaBridge	165:d1b4690b3f8b	4637	{
AnnaBridge	165:d1b4690b3f8b	4638	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1QEN);
AnnaBridge	165:d1b4690b3f8b	4639	}
AnnaBridge	165:d1b4690b3f8b	4640
AnnaBridge	165:d1b4690b3f8b	4641	/**
AnnaBridge	165:d1b4690b3f8b	4642	* @brief Enable PLLSAI1 output mapped on ADC domain clock
AnnaBridge	165:d1b4690b3f8b	4643	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_EnableDomain_ADC
AnnaBridge	165:d1b4690b3f8b	4644	* @retval None
AnnaBridge	165:d1b4690b3f8b	4645	*/
AnnaBridge	165:d1b4690b3f8b	4646	__STATIC_INLINE void LL_RCC_PLLSAI1_EnableDomain_ADC(void)
AnnaBridge	165:d1b4690b3f8b	4647	{
AnnaBridge	165:d1b4690b3f8b	4648	SET_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
AnnaBridge	165:d1b4690b3f8b	4649	}
AnnaBridge	165:d1b4690b3f8b	4650
AnnaBridge	165:d1b4690b3f8b	4651	/**
AnnaBridge	165:d1b4690b3f8b	4652	* @brief Disable PLLSAI1 output mapped on ADC domain clock
AnnaBridge	165:d1b4690b3f8b	4653	* @note In order to save power, when of the PLLSAI1 is
AnnaBridge	165:d1b4690b3f8b	4654	* not used, Main PLLSAI1 should be 0
AnnaBridge	165:d1b4690b3f8b	4655	* @rmtoll PLLSAI1CFGR PLLSAI1REN LL_RCC_PLLSAI1_DisableDomain_ADC
AnnaBridge	165:d1b4690b3f8b	4656	* @retval None
AnnaBridge	165:d1b4690b3f8b	4657	*/
AnnaBridge	165:d1b4690b3f8b	4658	__STATIC_INLINE void LL_RCC_PLLSAI1_DisableDomain_ADC(void)
AnnaBridge	165:d1b4690b3f8b	4659	{
AnnaBridge	165:d1b4690b3f8b	4660	CLEAR_BIT(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLSAI1REN);
AnnaBridge	165:d1b4690b3f8b	4661	}
AnnaBridge	165:d1b4690b3f8b	4662
AnnaBridge	165:d1b4690b3f8b	4663	/**
AnnaBridge	165:d1b4690b3f8b	4664	* @}
AnnaBridge	165:d1b4690b3f8b	4665	*/
AnnaBridge	165:d1b4690b3f8b	4666
AnnaBridge	165:d1b4690b3f8b	4667	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4668	/** @defgroup RCC_LL_EF_PLLSAI2 PLLSAI2
AnnaBridge	165:d1b4690b3f8b	4669	* @{
AnnaBridge	165:d1b4690b3f8b	4670	*/
AnnaBridge	165:d1b4690b3f8b	4671
AnnaBridge	165:d1b4690b3f8b	4672	/**
AnnaBridge	165:d1b4690b3f8b	4673	* @brief Enable PLLSAI2
AnnaBridge	165:d1b4690b3f8b	4674	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Enable
AnnaBridge	165:d1b4690b3f8b	4675	* @retval None
AnnaBridge	165:d1b4690b3f8b	4676	*/
AnnaBridge	165:d1b4690b3f8b	4677	__STATIC_INLINE void LL_RCC_PLLSAI2_Enable(void)
AnnaBridge	165:d1b4690b3f8b	4678	{
AnnaBridge	165:d1b4690b3f8b	4679	SET_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
AnnaBridge	165:d1b4690b3f8b	4680	}
AnnaBridge	165:d1b4690b3f8b	4681
AnnaBridge	165:d1b4690b3f8b	4682	/**
AnnaBridge	165:d1b4690b3f8b	4683	* @brief Disable PLLSAI2
AnnaBridge	165:d1b4690b3f8b	4684	* @rmtoll CR PLLSAI2ON LL_RCC_PLLSAI2_Disable
AnnaBridge	165:d1b4690b3f8b	4685	* @retval None
AnnaBridge	165:d1b4690b3f8b	4686	*/
AnnaBridge	165:d1b4690b3f8b	4687	__STATIC_INLINE void LL_RCC_PLLSAI2_Disable(void)
AnnaBridge	165:d1b4690b3f8b	4688	{
AnnaBridge	165:d1b4690b3f8b	4689	CLEAR_BIT(RCC->CR, RCC_CR_PLLSAI2ON);
AnnaBridge	165:d1b4690b3f8b	4690	}
AnnaBridge	165:d1b4690b3f8b	4691
AnnaBridge	165:d1b4690b3f8b	4692	/**
AnnaBridge	165:d1b4690b3f8b	4693	* @brief Check if PLLSAI2 Ready
AnnaBridge	165:d1b4690b3f8b	4694	* @rmtoll CR PLLSAI2RDY LL_RCC_PLLSAI2_IsReady
AnnaBridge	165:d1b4690b3f8b	4695	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	4696	*/
AnnaBridge	165:d1b4690b3f8b	4697	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_IsReady(void)
AnnaBridge	165:d1b4690b3f8b	4698	{
AnnaBridge	165:d1b4690b3f8b	4699	return (READ_BIT(RCC->CR, RCC_CR_PLLSAI2RDY) == (RCC_CR_PLLSAI2RDY));
AnnaBridge	165:d1b4690b3f8b	4700	}
AnnaBridge	165:d1b4690b3f8b	4701
AnnaBridge	165:d1b4690b3f8b	4702	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT) && defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4703	/**
AnnaBridge	165:d1b4690b3f8b	4704	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4705	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4706	* @note PLLSAI2M/PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
AnnaBridge	165:d1b4690b3f8b	4707	* @note This can be selected for SAI1 or SAI2
AnnaBridge	165:d1b4690b3f8b	4708	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4709	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4710	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4711	* PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4712	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4713	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4714	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4715	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4716	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4717	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4718	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4719	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4720	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4721	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4722	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4723	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4724	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4725	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4726	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4727	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4728	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4729	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4730	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4731	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4732	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4733	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4734	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4735	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4736	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	165:d1b4690b3f8b	4737	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	165:d1b4690b3f8b	4738	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	165:d1b4690b3f8b	4739	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	165:d1b4690b3f8b	4740	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	165:d1b4690b3f8b	4741	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4742	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	165:d1b4690b3f8b	4743	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	165:d1b4690b3f8b	4744	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	165:d1b4690b3f8b	4745	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	165:d1b4690b3f8b	4746	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	165:d1b4690b3f8b	4747	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	165:d1b4690b3f8b	4748	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	165:d1b4690b3f8b	4749	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	165:d1b4690b3f8b	4750	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	165:d1b4690b3f8b	4751	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4752	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	165:d1b4690b3f8b	4753	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	165:d1b4690b3f8b	4754	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	165:d1b4690b3f8b	4755	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	165:d1b4690b3f8b	4756	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	165:d1b4690b3f8b	4757	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	165:d1b4690b3f8b	4758	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	165:d1b4690b3f8b	4759	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	165:d1b4690b3f8b	4760	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	165:d1b4690b3f8b	4761	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	165:d1b4690b3f8b	4762	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	165:d1b4690b3f8b	4763	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	165:d1b4690b3f8b	4764	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	165:d1b4690b3f8b	4765	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	165:d1b4690b3f8b	4766	* @retval None
AnnaBridge	165:d1b4690b3f8b	4767	*/
AnnaBridge	165:d1b4690b3f8b	4768	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	4769	{
AnnaBridge	165:d1b4690b3f8b	4770	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	165:d1b4690b3f8b	4771	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2PDIV,
AnnaBridge	165:d1b4690b3f8b	4772	PLLM \| PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	4773	}
AnnaBridge	165:d1b4690b3f8b	4774	#elif defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	4775	/**
AnnaBridge	165:d1b4690b3f8b	4776	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4777	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4778	* PLLSAI1 and PLLSAI2 are disabled.
AnnaBridge	165:d1b4690b3f8b	4779	* @note PLLSAI2N/PLLSAI2PDIV can be written only when PLLSAI2 is disabled.
AnnaBridge	165:d1b4690b3f8b	4780	* @note This can be selected for SAI1 or SAI2
AnnaBridge	165:d1b4690b3f8b	4781	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4782	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4783	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4784	* PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4785	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4786	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4787	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4788	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4789	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4790	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4791	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4792	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4793	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4794	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4795	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4796	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4797	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4798	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4799	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4800	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4801	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	165:d1b4690b3f8b	4802	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	165:d1b4690b3f8b	4803	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	165:d1b4690b3f8b	4804	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	165:d1b4690b3f8b	4805	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	165:d1b4690b3f8b	4806	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4807	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	165:d1b4690b3f8b	4808	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	165:d1b4690b3f8b	4809	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	165:d1b4690b3f8b	4810	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	165:d1b4690b3f8b	4811	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	165:d1b4690b3f8b	4812	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	165:d1b4690b3f8b	4813	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	165:d1b4690b3f8b	4814	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	165:d1b4690b3f8b	4815	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	165:d1b4690b3f8b	4816	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4817	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	165:d1b4690b3f8b	4818	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	165:d1b4690b3f8b	4819	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	165:d1b4690b3f8b	4820	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	165:d1b4690b3f8b	4821	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	165:d1b4690b3f8b	4822	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	165:d1b4690b3f8b	4823	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	165:d1b4690b3f8b	4824	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	165:d1b4690b3f8b	4825	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	165:d1b4690b3f8b	4826	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	165:d1b4690b3f8b	4827	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	165:d1b4690b3f8b	4828	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	165:d1b4690b3f8b	4829	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	165:d1b4690b3f8b	4830	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	165:d1b4690b3f8b	4831	* @retval None
AnnaBridge	165:d1b4690b3f8b	4832	*/
AnnaBridge	165:d1b4690b3f8b	4833	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	4834	{
AnnaBridge	165:d1b4690b3f8b	4835	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4836	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2PDIV, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	4837	}
AnnaBridge	165:d1b4690b3f8b	4838	#else
AnnaBridge	165:d1b4690b3f8b	4839	/**
AnnaBridge	165:d1b4690b3f8b	4840	* @brief Configure PLLSAI2 used for SAI domain clock
AnnaBridge	165:d1b4690b3f8b	4841	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4842	* PLLSAI2 and PLLSAI2 are disabled.
AnnaBridge	165:d1b4690b3f8b	4843	* @note PLLSAI2N/PLLSAI2P can be written only when PLLSAI2 is disabled.
AnnaBridge	165:d1b4690b3f8b	4844	* @note This can be selected for SAI1 or SAI2
AnnaBridge	165:d1b4690b3f8b	4845	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4846	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4847	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_SAI\n
AnnaBridge	165:d1b4690b3f8b	4848	* PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_ConfigDomain_SAI
AnnaBridge	165:d1b4690b3f8b	4849	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4850	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4851	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4852	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4853	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4854	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4855	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4856	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4857	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4858	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4859	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4860	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4861	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4862	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	4863	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4864	* @param PLLP This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4865	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	4866	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	4867	* @retval None
AnnaBridge	165:d1b4690b3f8b	4868	*/
AnnaBridge	165:d1b4690b3f8b	4869	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
AnnaBridge	165:d1b4690b3f8b	4870	{
AnnaBridge	165:d1b4690b3f8b	4871	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4872	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2P, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLP);
AnnaBridge	165:d1b4690b3f8b	4873	}
AnnaBridge	165:d1b4690b3f8b	4874	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT && RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	4875
AnnaBridge	165:d1b4690b3f8b	4876	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	4877	/**
AnnaBridge	165:d1b4690b3f8b	4878	* @brief Configure PLLSAI2 used for DSI domain clock
AnnaBridge	165:d1b4690b3f8b	4879	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4880	* @note PLLSAI2M/PLLSAI2N/PLLSAI2Q can be written only when PLLSAI2 is disabled.
AnnaBridge	165:d1b4690b3f8b	4881	* @note This can be selected for DSI
AnnaBridge	165:d1b4690b3f8b	4882	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	165:d1b4690b3f8b	4883	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	165:d1b4690b3f8b	4884	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_DSI\n
AnnaBridge	165:d1b4690b3f8b	4885	* PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_ConfigDomain_DSI
AnnaBridge	165:d1b4690b3f8b	4886	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4887	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4888	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4889	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4890	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4891	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4892	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4893	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4894	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4895	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4896	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4897	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4898	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4899	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4900	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4901	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4902	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4903	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4904	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4905	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4906	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4907	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4908	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4909	* @param PLLQ This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4910	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	4911	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	4912	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	4913	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	4914	* @retval None
AnnaBridge	165:d1b4690b3f8b	4915	*/
AnnaBridge	165:d1b4690b3f8b	4916	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
AnnaBridge	165:d1b4690b3f8b	4917	{
AnnaBridge	165:d1b4690b3f8b	4918	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	165:d1b4690b3f8b	4919	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2Q, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLQ \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4920	}
AnnaBridge	165:d1b4690b3f8b	4921	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	4922
AnnaBridge	165:d1b4690b3f8b	4923	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	4924	/**
AnnaBridge	165:d1b4690b3f8b	4925	* @brief Configure PLLSAI2 used for LTDC domain clock
AnnaBridge	165:d1b4690b3f8b	4926	* @note PLL Source can be written only when PLL, PLLSAI1 and PLLSAI2 (*) are disabled.
AnnaBridge	165:d1b4690b3f8b	4927	* @note PLLSAI2M/PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
AnnaBridge	165:d1b4690b3f8b	4928	* @note This can be selected for LTDC
AnnaBridge	165:d1b4690b3f8b	4929	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	165:d1b4690b3f8b	4930	* PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	165:d1b4690b3f8b	4931	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	165:d1b4690b3f8b	4932	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_LTDC\n
AnnaBridge	165:d1b4690b3f8b	4933	* CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_ConfigDomain_LTDC
AnnaBridge	165:d1b4690b3f8b	4934	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4935	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4936	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4937	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4938	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4939	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4940	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	4941	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	4942	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	4943	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	4944	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	4945	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	4946	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	4947	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	4948	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	4949	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	4950	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	4951	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	4952	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	4953	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	4954	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	4955	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	4956	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	4957	* @param PLLR This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4958	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	165:d1b4690b3f8b	4959	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	165:d1b4690b3f8b	4960	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	165:d1b4690b3f8b	4961	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	165:d1b4690b3f8b	4962	* @param PLLDIVR This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4963	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	165:d1b4690b3f8b	4964	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	165:d1b4690b3f8b	4965	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	165:d1b4690b3f8b	4966	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	165:d1b4690b3f8b	4967	* @retval None
AnnaBridge	165:d1b4690b3f8b	4968	*/
AnnaBridge	165:d1b4690b3f8b	4969	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
AnnaBridge	165:d1b4690b3f8b	4970	{
AnnaBridge	165:d1b4690b3f8b	4971	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, Source);
AnnaBridge	165:d1b4690b3f8b	4972	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M \| RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR \| PLLM);
AnnaBridge	165:d1b4690b3f8b	4973	MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR, PLLDIVR);
AnnaBridge	165:d1b4690b3f8b	4974	}
AnnaBridge	165:d1b4690b3f8b	4975	#else
AnnaBridge	165:d1b4690b3f8b	4976	/**
AnnaBridge	165:d1b4690b3f8b	4977	* @brief Configure PLLSAI2 used for ADC domain clock
AnnaBridge	165:d1b4690b3f8b	4978	* @note PLL Source and PLLM Divider can be written only when PLL,
AnnaBridge	165:d1b4690b3f8b	4979	* PLLSAI2 and PLLSAI2 are disabled.
AnnaBridge	165:d1b4690b3f8b	4980	* @note PLLSAI2N/PLLSAI2R can be written only when PLLSAI2 is disabled.
AnnaBridge	165:d1b4690b3f8b	4981	* @note This can be selected for ADC
AnnaBridge	165:d1b4690b3f8b	4982	* @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI2_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4983	* PLLCFGR PLLM LL_RCC_PLLSAI2_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4984	* PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_ConfigDomain_ADC\n
AnnaBridge	165:d1b4690b3f8b	4985	* PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_ConfigDomain_ADC
AnnaBridge	165:d1b4690b3f8b	4986	* @param Source This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4987	* @arg @ref LL_RCC_PLLSOURCE_NONE
AnnaBridge	165:d1b4690b3f8b	4988	* @arg @ref LL_RCC_PLLSOURCE_MSI
AnnaBridge	165:d1b4690b3f8b	4989	* @arg @ref LL_RCC_PLLSOURCE_HSI
AnnaBridge	165:d1b4690b3f8b	4990	* @arg @ref LL_RCC_PLLSOURCE_HSE
AnnaBridge	165:d1b4690b3f8b	4991	* @param PLLM This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	4992	* @arg @ref LL_RCC_PLLM_DIV_1
AnnaBridge	165:d1b4690b3f8b	4993	* @arg @ref LL_RCC_PLLM_DIV_2
AnnaBridge	165:d1b4690b3f8b	4994	* @arg @ref LL_RCC_PLLM_DIV_3
AnnaBridge	165:d1b4690b3f8b	4995	* @arg @ref LL_RCC_PLLM_DIV_4
AnnaBridge	165:d1b4690b3f8b	4996	* @arg @ref LL_RCC_PLLM_DIV_5
AnnaBridge	165:d1b4690b3f8b	4997	* @arg @ref LL_RCC_PLLM_DIV_6
AnnaBridge	165:d1b4690b3f8b	4998	* @arg @ref LL_RCC_PLLM_DIV_7
AnnaBridge	165:d1b4690b3f8b	4999	* @arg @ref LL_RCC_PLLM_DIV_8
AnnaBridge	165:d1b4690b3f8b	5000	* @param PLLN Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	5001	* @param PLLR This parameter can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5002	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	165:d1b4690b3f8b	5003	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	165:d1b4690b3f8b	5004	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	165:d1b4690b3f8b	5005	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	165:d1b4690b3f8b	5006	* @retval None
AnnaBridge	165:d1b4690b3f8b	5007	*/
AnnaBridge	165:d1b4690b3f8b	5008	__STATIC_INLINE void LL_RCC_PLLSAI2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
AnnaBridge	165:d1b4690b3f8b	5009	{
AnnaBridge	165:d1b4690b3f8b	5010	MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC \| RCC_PLLCFGR_PLLM, Source \| PLLM);
AnnaBridge	165:d1b4690b3f8b	5011	MODIFY_REG(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N \| RCC_PLLSAI2CFGR_PLLSAI2R, PLLN << RCC_PLLSAI2CFGR_PLLSAI2N_Pos \| PLLR);
AnnaBridge	165:d1b4690b3f8b	5012	}
AnnaBridge	165:d1b4690b3f8b	5013	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	5014
AnnaBridge	165:d1b4690b3f8b	5015	/**
AnnaBridge	165:d1b4690b3f8b	5016	* @brief Get SAI2PLL multiplication factor for VCO
AnnaBridge	165:d1b4690b3f8b	5017	* @rmtoll PLLSAI2CFGR PLLSAI2N LL_RCC_PLLSAI2_GetN
AnnaBridge	165:d1b4690b3f8b	5018	* @retval Between 8 and 86
AnnaBridge	165:d1b4690b3f8b	5019	*/
AnnaBridge	165:d1b4690b3f8b	5020	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetN(void)
AnnaBridge	165:d1b4690b3f8b	5021	{
AnnaBridge	165:d1b4690b3f8b	5022	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2N) >> RCC_PLLSAI2CFGR_PLLSAI2N_Pos);
AnnaBridge	165:d1b4690b3f8b	5023	}
AnnaBridge	165:d1b4690b3f8b	5024
AnnaBridge	165:d1b4690b3f8b	5025	#if defined(RCC_PLLSAI2P_DIV_2_31_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5026	/**
AnnaBridge	165:d1b4690b3f8b	5027	* @brief Get SAI2PLL division factor for PLLSAI2P
AnnaBridge	165:d1b4690b3f8b	5028	* @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
AnnaBridge	165:d1b4690b3f8b	5029	* @rmtoll PLLSAI2CFGR PLLSAI2PDIV LL_RCC_PLLSAI2_GetP
AnnaBridge	165:d1b4690b3f8b	5030	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5031	* @arg @ref LL_RCC_PLLSAI2P_DIV_2
AnnaBridge	165:d1b4690b3f8b	5032	* @arg @ref LL_RCC_PLLSAI2P_DIV_3
AnnaBridge	165:d1b4690b3f8b	5033	* @arg @ref LL_RCC_PLLSAI2P_DIV_4
AnnaBridge	165:d1b4690b3f8b	5034	* @arg @ref LL_RCC_PLLSAI2P_DIV_5
AnnaBridge	165:d1b4690b3f8b	5035	* @arg @ref LL_RCC_PLLSAI2P_DIV_6
AnnaBridge	165:d1b4690b3f8b	5036	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	5037	* @arg @ref LL_RCC_PLLSAI2P_DIV_8
AnnaBridge	165:d1b4690b3f8b	5038	* @arg @ref LL_RCC_PLLSAI2P_DIV_9
AnnaBridge	165:d1b4690b3f8b	5039	* @arg @ref LL_RCC_PLLSAI2P_DIV_10
AnnaBridge	165:d1b4690b3f8b	5040	* @arg @ref LL_RCC_PLLSAI2P_DIV_11
AnnaBridge	165:d1b4690b3f8b	5041	* @arg @ref LL_RCC_PLLSAI2P_DIV_12
AnnaBridge	165:d1b4690b3f8b	5042	* @arg @ref LL_RCC_PLLSAI2P_DIV_13
AnnaBridge	165:d1b4690b3f8b	5043	* @arg @ref LL_RCC_PLLSAI2P_DIV_14
AnnaBridge	165:d1b4690b3f8b	5044	* @arg @ref LL_RCC_PLLSAI2P_DIV_15
AnnaBridge	165:d1b4690b3f8b	5045	* @arg @ref LL_RCC_PLLSAI2P_DIV_16
AnnaBridge	165:d1b4690b3f8b	5046	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	5047	* @arg @ref LL_RCC_PLLSAI2P_DIV_18
AnnaBridge	165:d1b4690b3f8b	5048	* @arg @ref LL_RCC_PLLSAI2P_DIV_19
AnnaBridge	165:d1b4690b3f8b	5049	* @arg @ref LL_RCC_PLLSAI2P_DIV_20
AnnaBridge	165:d1b4690b3f8b	5050	* @arg @ref LL_RCC_PLLSAI2P_DIV_21
AnnaBridge	165:d1b4690b3f8b	5051	* @arg @ref LL_RCC_PLLSAI2P_DIV_22
AnnaBridge	165:d1b4690b3f8b	5052	* @arg @ref LL_RCC_PLLSAI2P_DIV_23
AnnaBridge	165:d1b4690b3f8b	5053	* @arg @ref LL_RCC_PLLSAI2P_DIV_24
AnnaBridge	165:d1b4690b3f8b	5054	* @arg @ref LL_RCC_PLLSAI2P_DIV_25
AnnaBridge	165:d1b4690b3f8b	5055	* @arg @ref LL_RCC_PLLSAI2P_DIV_26
AnnaBridge	165:d1b4690b3f8b	5056	* @arg @ref LL_RCC_PLLSAI2P_DIV_27
AnnaBridge	165:d1b4690b3f8b	5057	* @arg @ref LL_RCC_PLLSAI2P_DIV_28
AnnaBridge	165:d1b4690b3f8b	5058	* @arg @ref LL_RCC_PLLSAI2P_DIV_29
AnnaBridge	165:d1b4690b3f8b	5059	* @arg @ref LL_RCC_PLLSAI2P_DIV_30
AnnaBridge	165:d1b4690b3f8b	5060	* @arg @ref LL_RCC_PLLSAI2P_DIV_31
AnnaBridge	165:d1b4690b3f8b	5061	*/
AnnaBridge	165:d1b4690b3f8b	5062	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
AnnaBridge	165:d1b4690b3f8b	5063	{
AnnaBridge	165:d1b4690b3f8b	5064	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PDIV));
AnnaBridge	165:d1b4690b3f8b	5065	}
AnnaBridge	165:d1b4690b3f8b	5066	#else
AnnaBridge	165:d1b4690b3f8b	5067	/**
AnnaBridge	165:d1b4690b3f8b	5068	* @brief Get SAI2PLL division factor for PLLSAI2P
AnnaBridge	165:d1b4690b3f8b	5069	* @note Used for PLLSAI2CLK (SAI1 or SAI2 clock).
AnnaBridge	165:d1b4690b3f8b	5070	* @rmtoll PLLSAI2CFGR PLLSAI2P LL_RCC_PLLSAI2_GetP
AnnaBridge	165:d1b4690b3f8b	5071	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5072	* @arg @ref LL_RCC_PLLSAI2P_DIV_7
AnnaBridge	165:d1b4690b3f8b	5073	* @arg @ref LL_RCC_PLLSAI2P_DIV_17
AnnaBridge	165:d1b4690b3f8b	5074	*/
AnnaBridge	165:d1b4690b3f8b	5075	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetP(void)
AnnaBridge	165:d1b4690b3f8b	5076	{
AnnaBridge	165:d1b4690b3f8b	5077	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2P));
AnnaBridge	165:d1b4690b3f8b	5078	}
AnnaBridge	165:d1b4690b3f8b	5079	#endif /* RCC_PLLSAI2P_DIV_2_31_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5080
AnnaBridge	165:d1b4690b3f8b	5081	#if defined(RCC_PLLSAI2Q_DIV_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5082	/**
AnnaBridge	165:d1b4690b3f8b	5083	* @brief Get division factor for PLLSAI2Q
AnnaBridge	165:d1b4690b3f8b	5084	* @note Used for PLLDSICLK (DSI clock)
AnnaBridge	165:d1b4690b3f8b	5085	* @rmtoll PLLSAI2CFGR PLLSAI2Q LL_RCC_PLLSAI2_GetQ
AnnaBridge	165:d1b4690b3f8b	5086	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5087	* @arg @ref LL_RCC_PLLSAI2Q_DIV_2
AnnaBridge	165:d1b4690b3f8b	5088	* @arg @ref LL_RCC_PLLSAI2Q_DIV_4
AnnaBridge	165:d1b4690b3f8b	5089	* @arg @ref LL_RCC_PLLSAI2Q_DIV_6
AnnaBridge	165:d1b4690b3f8b	5090	* @arg @ref LL_RCC_PLLSAI2Q_DIV_8
AnnaBridge	165:d1b4690b3f8b	5091	*/
AnnaBridge	165:d1b4690b3f8b	5092	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetQ(void)
AnnaBridge	165:d1b4690b3f8b	5093	{
AnnaBridge	165:d1b4690b3f8b	5094	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2Q));
AnnaBridge	165:d1b4690b3f8b	5095	}
AnnaBridge	165:d1b4690b3f8b	5096	#endif /* RCC_PLLSAI2Q_DIV_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5097
AnnaBridge	165:d1b4690b3f8b	5098	/**
AnnaBridge	165:d1b4690b3f8b	5099	* @brief Get SAI2PLL division factor for PLLSAI2R
AnnaBridge	165:d1b4690b3f8b	5100	* @note Used for PLLADC2CLK (ADC clock) or PLLLCDCLK (LTDC clock) depending on devices
AnnaBridge	165:d1b4690b3f8b	5101	* @rmtoll PLLSAI2CFGR PLLSAI2R LL_RCC_PLLSAI2_GetR
AnnaBridge	165:d1b4690b3f8b	5102	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5103	* @arg @ref LL_RCC_PLLSAI2R_DIV_2
AnnaBridge	165:d1b4690b3f8b	5104	* @arg @ref LL_RCC_PLLSAI2R_DIV_4
AnnaBridge	165:d1b4690b3f8b	5105	* @arg @ref LL_RCC_PLLSAI2R_DIV_6
AnnaBridge	165:d1b4690b3f8b	5106	* @arg @ref LL_RCC_PLLSAI2R_DIV_8
AnnaBridge	165:d1b4690b3f8b	5107	*/
AnnaBridge	165:d1b4690b3f8b	5108	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetR(void)
AnnaBridge	165:d1b4690b3f8b	5109	{
AnnaBridge	165:d1b4690b3f8b	5110	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2R));
AnnaBridge	165:d1b4690b3f8b	5111	}
AnnaBridge	165:d1b4690b3f8b	5112
AnnaBridge	165:d1b4690b3f8b	5113	#if defined(RCC_PLLSAI2M_DIV_1_16_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5114	/**
AnnaBridge	165:d1b4690b3f8b	5115	* @brief Get Division factor for the PLLSAI2
AnnaBridge	165:d1b4690b3f8b	5116	* @rmtoll PLLSAI2CFGR PLLSAI2M LL_RCC_PLLSAI2_GetDivider
AnnaBridge	165:d1b4690b3f8b	5117	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5118	* @arg @ref LL_RCC_PLLSAI2M_DIV_1
AnnaBridge	165:d1b4690b3f8b	5119	* @arg @ref LL_RCC_PLLSAI2M_DIV_2
AnnaBridge	165:d1b4690b3f8b	5120	* @arg @ref LL_RCC_PLLSAI2M_DIV_3
AnnaBridge	165:d1b4690b3f8b	5121	* @arg @ref LL_RCC_PLLSAI2M_DIV_4
AnnaBridge	165:d1b4690b3f8b	5122	* @arg @ref LL_RCC_PLLSAI2M_DIV_5
AnnaBridge	165:d1b4690b3f8b	5123	* @arg @ref LL_RCC_PLLSAI2M_DIV_6
AnnaBridge	165:d1b4690b3f8b	5124	* @arg @ref LL_RCC_PLLSAI2M_DIV_7
AnnaBridge	165:d1b4690b3f8b	5125	* @arg @ref LL_RCC_PLLSAI2M_DIV_8
AnnaBridge	165:d1b4690b3f8b	5126	* @arg @ref LL_RCC_PLLSAI2M_DIV_9
AnnaBridge	165:d1b4690b3f8b	5127	* @arg @ref LL_RCC_PLLSAI2M_DIV_10
AnnaBridge	165:d1b4690b3f8b	5128	* @arg @ref LL_RCC_PLLSAI2M_DIV_11
AnnaBridge	165:d1b4690b3f8b	5129	* @arg @ref LL_RCC_PLLSAI2M_DIV_12
AnnaBridge	165:d1b4690b3f8b	5130	* @arg @ref LL_RCC_PLLSAI2M_DIV_13
AnnaBridge	165:d1b4690b3f8b	5131	* @arg @ref LL_RCC_PLLSAI2M_DIV_14
AnnaBridge	165:d1b4690b3f8b	5132	* @arg @ref LL_RCC_PLLSAI2M_DIV_15
AnnaBridge	165:d1b4690b3f8b	5133	* @arg @ref LL_RCC_PLLSAI2M_DIV_16
AnnaBridge	165:d1b4690b3f8b	5134	*/
AnnaBridge	165:d1b4690b3f8b	5135	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDivider(void)
AnnaBridge	165:d1b4690b3f8b	5136	{
AnnaBridge	165:d1b4690b3f8b	5137	return (uint32_t)(READ_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2M));
AnnaBridge	165:d1b4690b3f8b	5138	}
AnnaBridge	165:d1b4690b3f8b	5139	#endif /* RCC_PLLSAI2M_DIV_1_16_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5140
AnnaBridge	165:d1b4690b3f8b	5141	#if defined(RCC_CCIPR2_PLLSAI2DIVR)
AnnaBridge	165:d1b4690b3f8b	5142	/**
AnnaBridge	165:d1b4690b3f8b	5143	* @brief Get PLLSAI2 division factor for PLLSAI2DIVR
AnnaBridge	165:d1b4690b3f8b	5144	* @note Used for LTDC domain clock
AnnaBridge	165:d1b4690b3f8b	5145	* @rmtoll CCIPR2 PLLSAI2DIVR LL_RCC_PLLSAI2_GetDIVR
AnnaBridge	165:d1b4690b3f8b	5146	* @retval Returned value can be one of the following values:
AnnaBridge	165:d1b4690b3f8b	5147	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_2
AnnaBridge	165:d1b4690b3f8b	5148	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_4
AnnaBridge	165:d1b4690b3f8b	5149	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_8
AnnaBridge	165:d1b4690b3f8b	5150	* @arg @ref LL_RCC_PLLSAI2DIVR_DIV_16
AnnaBridge	165:d1b4690b3f8b	5151	*/
AnnaBridge	165:d1b4690b3f8b	5152	__STATIC_INLINE uint32_t LL_RCC_PLLSAI2_GetDIVR(void)
AnnaBridge	165:d1b4690b3f8b	5153	{
AnnaBridge	165:d1b4690b3f8b	5154	return (uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_PLLSAI2DIVR));
AnnaBridge	165:d1b4690b3f8b	5155	}
AnnaBridge	165:d1b4690b3f8b	5156	#endif /* RCC_CCIPR2_PLLSAI2DIVR */
AnnaBridge	165:d1b4690b3f8b	5157
AnnaBridge	165:d1b4690b3f8b	5158	/**
AnnaBridge	165:d1b4690b3f8b	5159	* @brief Enable PLLSAI2 output mapped on SAI domain clock
AnnaBridge	165:d1b4690b3f8b	5160	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_EnableDomain_SAI
AnnaBridge	165:d1b4690b3f8b	5161	* @retval None
AnnaBridge	165:d1b4690b3f8b	5162	*/
AnnaBridge	165:d1b4690b3f8b	5163	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_SAI(void)
AnnaBridge	165:d1b4690b3f8b	5164	{
AnnaBridge	165:d1b4690b3f8b	5165	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
AnnaBridge	165:d1b4690b3f8b	5166	}
AnnaBridge	165:d1b4690b3f8b	5167
AnnaBridge	165:d1b4690b3f8b	5168	/**
AnnaBridge	165:d1b4690b3f8b	5169	* @brief Disable PLLSAI2 output mapped on SAI domain clock
AnnaBridge	165:d1b4690b3f8b	5170	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	165:d1b4690b3f8b	5171	* not used, should be 0
AnnaBridge	165:d1b4690b3f8b	5172	* @rmtoll PLLSAI2CFGR PLLSAI2PEN LL_RCC_PLLSAI2_DisableDomain_SAI
AnnaBridge	165:d1b4690b3f8b	5173	* @retval None
AnnaBridge	165:d1b4690b3f8b	5174	*/
AnnaBridge	165:d1b4690b3f8b	5175	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_SAI(void)
AnnaBridge	165:d1b4690b3f8b	5176	{
AnnaBridge	165:d1b4690b3f8b	5177	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2PEN);
AnnaBridge	165:d1b4690b3f8b	5178	}
AnnaBridge	165:d1b4690b3f8b	5179
AnnaBridge	165:d1b4690b3f8b	5180	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	5181	/**
AnnaBridge	165:d1b4690b3f8b	5182	* @brief Enable PLLSAI2 output mapped on DSI domain clock
AnnaBridge	165:d1b4690b3f8b	5183	* @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_EnableDomain_DSI
AnnaBridge	165:d1b4690b3f8b	5184	* @retval None
AnnaBridge	165:d1b4690b3f8b	5185	*/
AnnaBridge	165:d1b4690b3f8b	5186	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_DSI(void)
AnnaBridge	165:d1b4690b3f8b	5187	{
AnnaBridge	165:d1b4690b3f8b	5188	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
AnnaBridge	165:d1b4690b3f8b	5189	}
AnnaBridge	165:d1b4690b3f8b	5190
AnnaBridge	165:d1b4690b3f8b	5191	/**
AnnaBridge	165:d1b4690b3f8b	5192	* @brief Disable PLLSAI2 output mapped on DSI domain clock
AnnaBridge	165:d1b4690b3f8b	5193	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	165:d1b4690b3f8b	5194	* not used, Main PLLSAI2 should be 0
AnnaBridge	165:d1b4690b3f8b	5195	* @rmtoll PLLSAI2CFGR PLLSAI2QEN LL_RCC_PLLSAI2_DisableDomain_DSI
AnnaBridge	165:d1b4690b3f8b	5196	* @retval None
AnnaBridge	165:d1b4690b3f8b	5197	*/
AnnaBridge	165:d1b4690b3f8b	5198	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_DSI(void)
AnnaBridge	165:d1b4690b3f8b	5199	{
AnnaBridge	165:d1b4690b3f8b	5200	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2QEN);
AnnaBridge	165:d1b4690b3f8b	5201	}
AnnaBridge	165:d1b4690b3f8b	5202	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	5203
AnnaBridge	165:d1b4690b3f8b	5204	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	5205	/**
AnnaBridge	165:d1b4690b3f8b	5206	* @brief Enable PLLSAI2 output mapped on LTDC domain clock
AnnaBridge	165:d1b4690b3f8b	5207	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_LTDC
AnnaBridge	165:d1b4690b3f8b	5208	* @retval None
AnnaBridge	165:d1b4690b3f8b	5209	*/
AnnaBridge	165:d1b4690b3f8b	5210	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_LTDC(void)
AnnaBridge	165:d1b4690b3f8b	5211	{
AnnaBridge	165:d1b4690b3f8b	5212	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	165:d1b4690b3f8b	5213	}
AnnaBridge	165:d1b4690b3f8b	5214
AnnaBridge	165:d1b4690b3f8b	5215	/**
AnnaBridge	165:d1b4690b3f8b	5216	* @brief Disable PLLSAI2 output mapped on LTDC domain clock
AnnaBridge	165:d1b4690b3f8b	5217	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	165:d1b4690b3f8b	5218	* not used, Main PLLSAI2 should be 0
AnnaBridge	165:d1b4690b3f8b	5219	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_LTDC
AnnaBridge	165:d1b4690b3f8b	5220	* @retval None
AnnaBridge	165:d1b4690b3f8b	5221	*/
AnnaBridge	165:d1b4690b3f8b	5222	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_LTDC(void)
AnnaBridge	165:d1b4690b3f8b	5223	{
AnnaBridge	165:d1b4690b3f8b	5224	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	165:d1b4690b3f8b	5225	}
AnnaBridge	165:d1b4690b3f8b	5226	#else
AnnaBridge	165:d1b4690b3f8b	5227	/**
AnnaBridge	165:d1b4690b3f8b	5228	* @brief Enable PLLSAI2 output mapped on ADC domain clock
AnnaBridge	165:d1b4690b3f8b	5229	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_EnableDomain_ADC
AnnaBridge	165:d1b4690b3f8b	5230	* @retval None
AnnaBridge	165:d1b4690b3f8b	5231	*/
AnnaBridge	165:d1b4690b3f8b	5232	__STATIC_INLINE void LL_RCC_PLLSAI2_EnableDomain_ADC(void)
AnnaBridge	165:d1b4690b3f8b	5233	{
AnnaBridge	165:d1b4690b3f8b	5234	SET_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	165:d1b4690b3f8b	5235	}
AnnaBridge	165:d1b4690b3f8b	5236
AnnaBridge	165:d1b4690b3f8b	5237	/**
AnnaBridge	165:d1b4690b3f8b	5238	* @brief Disable PLLSAI2 output mapped on ADC domain clock
AnnaBridge	165:d1b4690b3f8b	5239	* @note In order to save power, when of the PLLSAI2 is
AnnaBridge	165:d1b4690b3f8b	5240	* not used, Main PLLSAI2 should be 0
AnnaBridge	165:d1b4690b3f8b	5241	* @rmtoll PLLSAI2CFGR PLLSAI2REN LL_RCC_PLLSAI2_DisableDomain_ADC
AnnaBridge	165:d1b4690b3f8b	5242	* @retval None
AnnaBridge	165:d1b4690b3f8b	5243	*/
AnnaBridge	165:d1b4690b3f8b	5244	__STATIC_INLINE void LL_RCC_PLLSAI2_DisableDomain_ADC(void)
AnnaBridge	165:d1b4690b3f8b	5245	{
AnnaBridge	165:d1b4690b3f8b	5246	CLEAR_BIT(RCC->PLLSAI2CFGR, RCC_PLLSAI2CFGR_PLLSAI2REN);
AnnaBridge	165:d1b4690b3f8b	5247	}
AnnaBridge	165:d1b4690b3f8b	5248	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	5249
AnnaBridge	165:d1b4690b3f8b	5250	/**
AnnaBridge	165:d1b4690b3f8b	5251	* @}
AnnaBridge	165:d1b4690b3f8b	5252	*/
AnnaBridge	165:d1b4690b3f8b	5253	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5254
AnnaBridge	165:d1b4690b3f8b	5255
AnnaBridge	165:d1b4690b3f8b	5256
AnnaBridge	165:d1b4690b3f8b	5257	/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
AnnaBridge	165:d1b4690b3f8b	5258	* @{
AnnaBridge	165:d1b4690b3f8b	5259	*/
AnnaBridge	165:d1b4690b3f8b	5260
AnnaBridge	165:d1b4690b3f8b	5261	/**
AnnaBridge	165:d1b4690b3f8b	5262	* @brief Clear LSI ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5263	* @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
AnnaBridge	165:d1b4690b3f8b	5264	* @retval None
AnnaBridge	165:d1b4690b3f8b	5265	*/
AnnaBridge	165:d1b4690b3f8b	5266	__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5267	{
AnnaBridge	165:d1b4690b3f8b	5268	SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
AnnaBridge	165:d1b4690b3f8b	5269	}
AnnaBridge	165:d1b4690b3f8b	5270
AnnaBridge	165:d1b4690b3f8b	5271	/**
AnnaBridge	165:d1b4690b3f8b	5272	* @brief Clear LSE ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5273	* @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
AnnaBridge	165:d1b4690b3f8b	5274	* @retval None
AnnaBridge	165:d1b4690b3f8b	5275	*/
AnnaBridge	165:d1b4690b3f8b	5276	__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5277	{
AnnaBridge	165:d1b4690b3f8b	5278	SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
AnnaBridge	165:d1b4690b3f8b	5279	}
AnnaBridge	165:d1b4690b3f8b	5280
AnnaBridge	165:d1b4690b3f8b	5281	/**
AnnaBridge	165:d1b4690b3f8b	5282	* @brief Clear MSI ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5283	* @rmtoll CICR MSIRDYC LL_RCC_ClearFlag_MSIRDY
AnnaBridge	165:d1b4690b3f8b	5284	* @retval None
AnnaBridge	165:d1b4690b3f8b	5285	*/
AnnaBridge	165:d1b4690b3f8b	5286	__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5287	{
AnnaBridge	165:d1b4690b3f8b	5288	SET_BIT(RCC->CICR, RCC_CICR_MSIRDYC);
AnnaBridge	165:d1b4690b3f8b	5289	}
AnnaBridge	165:d1b4690b3f8b	5290
AnnaBridge	165:d1b4690b3f8b	5291	/**
AnnaBridge	165:d1b4690b3f8b	5292	* @brief Clear HSI ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5293	* @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
AnnaBridge	165:d1b4690b3f8b	5294	* @retval None
AnnaBridge	165:d1b4690b3f8b	5295	*/
AnnaBridge	165:d1b4690b3f8b	5296	__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5297	{
AnnaBridge	165:d1b4690b3f8b	5298	SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
AnnaBridge	165:d1b4690b3f8b	5299	}
AnnaBridge	165:d1b4690b3f8b	5300
AnnaBridge	165:d1b4690b3f8b	5301	/**
AnnaBridge	165:d1b4690b3f8b	5302	* @brief Clear HSE ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5303	* @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
AnnaBridge	165:d1b4690b3f8b	5304	* @retval None
AnnaBridge	165:d1b4690b3f8b	5305	*/
AnnaBridge	165:d1b4690b3f8b	5306	__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5307	{
AnnaBridge	165:d1b4690b3f8b	5308	SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
AnnaBridge	165:d1b4690b3f8b	5309	}
AnnaBridge	165:d1b4690b3f8b	5310
AnnaBridge	165:d1b4690b3f8b	5311	/**
AnnaBridge	165:d1b4690b3f8b	5312	* @brief Clear PLL ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5313	* @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY
AnnaBridge	165:d1b4690b3f8b	5314	* @retval None
AnnaBridge	165:d1b4690b3f8b	5315	*/
AnnaBridge	165:d1b4690b3f8b	5316	__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
AnnaBridge	165:d1b4690b3f8b	5317	{
AnnaBridge	165:d1b4690b3f8b	5318	SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
AnnaBridge	165:d1b4690b3f8b	5319	}
AnnaBridge	165:d1b4690b3f8b	5320
AnnaBridge	165:d1b4690b3f8b	5321	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5322	/**
AnnaBridge	165:d1b4690b3f8b	5323	* @brief Clear HSI48 ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5324	* @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
AnnaBridge	165:d1b4690b3f8b	5325	* @retval None
AnnaBridge	165:d1b4690b3f8b	5326	*/
AnnaBridge	165:d1b4690b3f8b	5327	__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
AnnaBridge	165:d1b4690b3f8b	5328	{
AnnaBridge	165:d1b4690b3f8b	5329	SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
AnnaBridge	165:d1b4690b3f8b	5330	}
AnnaBridge	165:d1b4690b3f8b	5331	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5332
AnnaBridge	165:d1b4690b3f8b	5333	/**
AnnaBridge	165:d1b4690b3f8b	5334	* @brief Clear PLLSAI1 ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5335	* @rmtoll CICR PLLSAI1RDYC LL_RCC_ClearFlag_PLLSAI1RDY
AnnaBridge	165:d1b4690b3f8b	5336	* @retval None
AnnaBridge	165:d1b4690b3f8b	5337	*/
AnnaBridge	165:d1b4690b3f8b	5338	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI1RDY(void)
AnnaBridge	165:d1b4690b3f8b	5339	{
AnnaBridge	165:d1b4690b3f8b	5340	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI1RDYC);
AnnaBridge	165:d1b4690b3f8b	5341	}
AnnaBridge	165:d1b4690b3f8b	5342
AnnaBridge	165:d1b4690b3f8b	5343	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5344	/**
AnnaBridge	165:d1b4690b3f8b	5345	* @brief Clear PLLSAI1 ready interrupt flag
AnnaBridge	165:d1b4690b3f8b	5346	* @rmtoll CICR PLLSAI2RDYC LL_RCC_ClearFlag_PLLSAI2RDY
AnnaBridge	165:d1b4690b3f8b	5347	* @retval None
AnnaBridge	165:d1b4690b3f8b	5348	*/
AnnaBridge	165:d1b4690b3f8b	5349	__STATIC_INLINE void LL_RCC_ClearFlag_PLLSAI2RDY(void)
AnnaBridge	165:d1b4690b3f8b	5350	{
AnnaBridge	165:d1b4690b3f8b	5351	SET_BIT(RCC->CICR, RCC_CICR_PLLSAI2RDYC);
AnnaBridge	165:d1b4690b3f8b	5352	}
AnnaBridge	165:d1b4690b3f8b	5353	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5354
AnnaBridge	165:d1b4690b3f8b	5355	/**
AnnaBridge	165:d1b4690b3f8b	5356	* @brief Clear Clock security system interrupt flag
AnnaBridge	165:d1b4690b3f8b	5357	* @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS
AnnaBridge	165:d1b4690b3f8b	5358	* @retval None
AnnaBridge	165:d1b4690b3f8b	5359	*/
AnnaBridge	165:d1b4690b3f8b	5360	__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5361	{
AnnaBridge	165:d1b4690b3f8b	5362	SET_BIT(RCC->CICR, RCC_CICR_CSSC);
AnnaBridge	165:d1b4690b3f8b	5363	}
AnnaBridge	165:d1b4690b3f8b	5364
AnnaBridge	165:d1b4690b3f8b	5365	/**
AnnaBridge	165:d1b4690b3f8b	5366	* @brief Clear LSE Clock security system interrupt flag
AnnaBridge	165:d1b4690b3f8b	5367	* @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
AnnaBridge	165:d1b4690b3f8b	5368	* @retval None
AnnaBridge	165:d1b4690b3f8b	5369	*/
AnnaBridge	165:d1b4690b3f8b	5370	__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5371	{
AnnaBridge	165:d1b4690b3f8b	5372	SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
AnnaBridge	165:d1b4690b3f8b	5373	}
AnnaBridge	165:d1b4690b3f8b	5374
AnnaBridge	165:d1b4690b3f8b	5375	/**
AnnaBridge	165:d1b4690b3f8b	5376	* @brief Check if LSI ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5377	* @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
AnnaBridge	165:d1b4690b3f8b	5378	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5379	*/
AnnaBridge	165:d1b4690b3f8b	5380	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5381	{
AnnaBridge	165:d1b4690b3f8b	5382	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF));
AnnaBridge	165:d1b4690b3f8b	5383	}
AnnaBridge	165:d1b4690b3f8b	5384
AnnaBridge	165:d1b4690b3f8b	5385	/**
AnnaBridge	165:d1b4690b3f8b	5386	* @brief Check if LSE ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5387	* @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
AnnaBridge	165:d1b4690b3f8b	5388	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5389	*/
AnnaBridge	165:d1b4690b3f8b	5390	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5391	{
AnnaBridge	165:d1b4690b3f8b	5392	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF));
AnnaBridge	165:d1b4690b3f8b	5393	}
AnnaBridge	165:d1b4690b3f8b	5394
AnnaBridge	165:d1b4690b3f8b	5395	/**
AnnaBridge	165:d1b4690b3f8b	5396	* @brief Check if MSI ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5397	* @rmtoll CIFR MSIRDYF LL_RCC_IsActiveFlag_MSIRDY
AnnaBridge	165:d1b4690b3f8b	5398	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5399	*/
AnnaBridge	165:d1b4690b3f8b	5400	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5401	{
AnnaBridge	165:d1b4690b3f8b	5402	return (READ_BIT(RCC->CIFR, RCC_CIFR_MSIRDYF) == (RCC_CIFR_MSIRDYF));
AnnaBridge	165:d1b4690b3f8b	5403	}
AnnaBridge	165:d1b4690b3f8b	5404
AnnaBridge	165:d1b4690b3f8b	5405	/**
AnnaBridge	165:d1b4690b3f8b	5406	* @brief Check if HSI ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5407	* @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
AnnaBridge	165:d1b4690b3f8b	5408	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5409	*/
AnnaBridge	165:d1b4690b3f8b	5410	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5411	{
AnnaBridge	165:d1b4690b3f8b	5412	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF));
AnnaBridge	165:d1b4690b3f8b	5413	}
AnnaBridge	165:d1b4690b3f8b	5414
AnnaBridge	165:d1b4690b3f8b	5415	/**
AnnaBridge	165:d1b4690b3f8b	5416	* @brief Check if HSE ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5417	* @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
AnnaBridge	165:d1b4690b3f8b	5418	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5419	*/
AnnaBridge	165:d1b4690b3f8b	5420	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5421	{
AnnaBridge	165:d1b4690b3f8b	5422	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF));
AnnaBridge	165:d1b4690b3f8b	5423	}
AnnaBridge	165:d1b4690b3f8b	5424
AnnaBridge	165:d1b4690b3f8b	5425	/**
AnnaBridge	165:d1b4690b3f8b	5426	* @brief Check if PLL ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5427	* @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
AnnaBridge	165:d1b4690b3f8b	5428	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5429	*/
AnnaBridge	165:d1b4690b3f8b	5430	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
AnnaBridge	165:d1b4690b3f8b	5431	{
AnnaBridge	165:d1b4690b3f8b	5432	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF));
AnnaBridge	165:d1b4690b3f8b	5433	}
AnnaBridge	165:d1b4690b3f8b	5434
AnnaBridge	165:d1b4690b3f8b	5435	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5436	/**
AnnaBridge	165:d1b4690b3f8b	5437	* @brief Check if HSI48 ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5438	* @rmtoll CIR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
AnnaBridge	165:d1b4690b3f8b	5439	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5440	*/
AnnaBridge	165:d1b4690b3f8b	5441	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
AnnaBridge	165:d1b4690b3f8b	5442	{
AnnaBridge	165:d1b4690b3f8b	5443	return (READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF));
AnnaBridge	165:d1b4690b3f8b	5444	}
AnnaBridge	165:d1b4690b3f8b	5445	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5446
AnnaBridge	165:d1b4690b3f8b	5447	/**
AnnaBridge	165:d1b4690b3f8b	5448	* @brief Check if PLLSAI1 ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5449	* @rmtoll CIFR PLLSAI1RDYF LL_RCC_IsActiveFlag_PLLSAI1RDY
AnnaBridge	165:d1b4690b3f8b	5450	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5451	*/
AnnaBridge	165:d1b4690b3f8b	5452	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI1RDY(void)
AnnaBridge	165:d1b4690b3f8b	5453	{
AnnaBridge	165:d1b4690b3f8b	5454	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI1RDYF) == (RCC_CIFR_PLLSAI1RDYF));
AnnaBridge	165:d1b4690b3f8b	5455	}
AnnaBridge	165:d1b4690b3f8b	5456
AnnaBridge	165:d1b4690b3f8b	5457	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5458	/**
AnnaBridge	165:d1b4690b3f8b	5459	* @brief Check if PLLSAI1 ready interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5460	* @rmtoll CIFR PLLSAI2RDYF LL_RCC_IsActiveFlag_PLLSAI2RDY
AnnaBridge	165:d1b4690b3f8b	5461	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5462	*/
AnnaBridge	165:d1b4690b3f8b	5463	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAI2RDY(void)
AnnaBridge	165:d1b4690b3f8b	5464	{
AnnaBridge	165:d1b4690b3f8b	5465	return (READ_BIT(RCC->CIFR, RCC_CIFR_PLLSAI2RDYF) == (RCC_CIFR_PLLSAI2RDYF));
AnnaBridge	165:d1b4690b3f8b	5466	}
AnnaBridge	165:d1b4690b3f8b	5467	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5468
AnnaBridge	165:d1b4690b3f8b	5469	/**
AnnaBridge	165:d1b4690b3f8b	5470	* @brief Check if Clock security system interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5471	* @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS
AnnaBridge	165:d1b4690b3f8b	5472	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5473	*/
AnnaBridge	165:d1b4690b3f8b	5474	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5475	{
AnnaBridge	165:d1b4690b3f8b	5476	return (READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF));
AnnaBridge	165:d1b4690b3f8b	5477	}
AnnaBridge	165:d1b4690b3f8b	5478
AnnaBridge	165:d1b4690b3f8b	5479	/**
AnnaBridge	165:d1b4690b3f8b	5480	* @brief Check if LSE Clock security system interrupt occurred or not
AnnaBridge	165:d1b4690b3f8b	5481	* @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
AnnaBridge	165:d1b4690b3f8b	5482	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5483	*/
AnnaBridge	165:d1b4690b3f8b	5484	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5485	{
AnnaBridge	165:d1b4690b3f8b	5486	return (READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF));
AnnaBridge	165:d1b4690b3f8b	5487	}
AnnaBridge	165:d1b4690b3f8b	5488
AnnaBridge	165:d1b4690b3f8b	5489	/**
AnnaBridge	165:d1b4690b3f8b	5490	* @brief Check if RCC flag FW reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5491	* @rmtoll CSR FWRSTF LL_RCC_IsActiveFlag_FWRST
AnnaBridge	165:d1b4690b3f8b	5492	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5493	*/
AnnaBridge	165:d1b4690b3f8b	5494	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_FWRST(void)
AnnaBridge	165:d1b4690b3f8b	5495	{
AnnaBridge	165:d1b4690b3f8b	5496	return (READ_BIT(RCC->CSR, RCC_CSR_FWRSTF) == (RCC_CSR_FWRSTF));
AnnaBridge	165:d1b4690b3f8b	5497	}
AnnaBridge	165:d1b4690b3f8b	5498
AnnaBridge	165:d1b4690b3f8b	5499	/**
AnnaBridge	165:d1b4690b3f8b	5500	* @brief Check if RCC flag Independent Watchdog reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5501	* @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
AnnaBridge	165:d1b4690b3f8b	5502	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5503	*/
AnnaBridge	165:d1b4690b3f8b	5504	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
AnnaBridge	165:d1b4690b3f8b	5505	{
AnnaBridge	165:d1b4690b3f8b	5506	return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
AnnaBridge	165:d1b4690b3f8b	5507	}
AnnaBridge	165:d1b4690b3f8b	5508
AnnaBridge	165:d1b4690b3f8b	5509	/**
AnnaBridge	165:d1b4690b3f8b	5510	* @brief Check if RCC flag Low Power reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5511	* @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
AnnaBridge	165:d1b4690b3f8b	5512	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5513	*/
AnnaBridge	165:d1b4690b3f8b	5514	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
AnnaBridge	165:d1b4690b3f8b	5515	{
AnnaBridge	165:d1b4690b3f8b	5516	return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
AnnaBridge	165:d1b4690b3f8b	5517	}
AnnaBridge	165:d1b4690b3f8b	5518
AnnaBridge	165:d1b4690b3f8b	5519	/**
AnnaBridge	165:d1b4690b3f8b	5520	* @brief Check if RCC flag is set or not.
AnnaBridge	165:d1b4690b3f8b	5521	* @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST
AnnaBridge	165:d1b4690b3f8b	5522	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5523	*/
AnnaBridge	165:d1b4690b3f8b	5524	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void)
AnnaBridge	165:d1b4690b3f8b	5525	{
AnnaBridge	165:d1b4690b3f8b	5526	return (READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF));
AnnaBridge	165:d1b4690b3f8b	5527	}
AnnaBridge	165:d1b4690b3f8b	5528
AnnaBridge	165:d1b4690b3f8b	5529	/**
AnnaBridge	165:d1b4690b3f8b	5530	* @brief Check if RCC flag Pin reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5531	* @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
AnnaBridge	165:d1b4690b3f8b	5532	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5533	*/
AnnaBridge	165:d1b4690b3f8b	5534	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
AnnaBridge	165:d1b4690b3f8b	5535	{
AnnaBridge	165:d1b4690b3f8b	5536	return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
AnnaBridge	165:d1b4690b3f8b	5537	}
AnnaBridge	165:d1b4690b3f8b	5538
AnnaBridge	165:d1b4690b3f8b	5539	/**
AnnaBridge	165:d1b4690b3f8b	5540	* @brief Check if RCC flag Software reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5541	* @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
AnnaBridge	165:d1b4690b3f8b	5542	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5543	*/
AnnaBridge	165:d1b4690b3f8b	5544	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
AnnaBridge	165:d1b4690b3f8b	5545	{
AnnaBridge	165:d1b4690b3f8b	5546	return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
AnnaBridge	165:d1b4690b3f8b	5547	}
AnnaBridge	165:d1b4690b3f8b	5548
AnnaBridge	165:d1b4690b3f8b	5549	/**
AnnaBridge	165:d1b4690b3f8b	5550	* @brief Check if RCC flag Window Watchdog reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5551	* @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
AnnaBridge	165:d1b4690b3f8b	5552	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5553	*/
AnnaBridge	165:d1b4690b3f8b	5554	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
AnnaBridge	165:d1b4690b3f8b	5555	{
AnnaBridge	165:d1b4690b3f8b	5556	return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
AnnaBridge	165:d1b4690b3f8b	5557	}
AnnaBridge	165:d1b4690b3f8b	5558
AnnaBridge	165:d1b4690b3f8b	5559	/**
AnnaBridge	165:d1b4690b3f8b	5560	* @brief Check if RCC flag BOR reset is set or not.
AnnaBridge	165:d1b4690b3f8b	5561	* @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
AnnaBridge	165:d1b4690b3f8b	5562	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5563	*/
AnnaBridge	165:d1b4690b3f8b	5564	__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
AnnaBridge	165:d1b4690b3f8b	5565	{
AnnaBridge	165:d1b4690b3f8b	5566	return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
AnnaBridge	165:d1b4690b3f8b	5567	}
AnnaBridge	165:d1b4690b3f8b	5568
AnnaBridge	165:d1b4690b3f8b	5569	/**
AnnaBridge	165:d1b4690b3f8b	5570	* @brief Set RMVF bit to clear the reset flags.
AnnaBridge	165:d1b4690b3f8b	5571	* @rmtoll CSR RMVF LL_RCC_ClearResetFlags
AnnaBridge	165:d1b4690b3f8b	5572	* @retval None
AnnaBridge	165:d1b4690b3f8b	5573	*/
AnnaBridge	165:d1b4690b3f8b	5574	__STATIC_INLINE void LL_RCC_ClearResetFlags(void)
AnnaBridge	165:d1b4690b3f8b	5575	{
AnnaBridge	165:d1b4690b3f8b	5576	SET_BIT(RCC->CSR, RCC_CSR_RMVF);
AnnaBridge	165:d1b4690b3f8b	5577	}
AnnaBridge	165:d1b4690b3f8b	5578
AnnaBridge	165:d1b4690b3f8b	5579	/**
AnnaBridge	165:d1b4690b3f8b	5580	* @}
AnnaBridge	165:d1b4690b3f8b	5581	*/
AnnaBridge	165:d1b4690b3f8b	5582
AnnaBridge	165:d1b4690b3f8b	5583	/** @defgroup RCC_LL_EF_IT_Management IT Management
AnnaBridge	165:d1b4690b3f8b	5584	* @{
AnnaBridge	165:d1b4690b3f8b	5585	*/
AnnaBridge	165:d1b4690b3f8b	5586
AnnaBridge	165:d1b4690b3f8b	5587	/**
AnnaBridge	165:d1b4690b3f8b	5588	* @brief Enable LSI ready interrupt
AnnaBridge	165:d1b4690b3f8b	5589	* @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
AnnaBridge	165:d1b4690b3f8b	5590	* @retval None
AnnaBridge	165:d1b4690b3f8b	5591	*/
AnnaBridge	165:d1b4690b3f8b	5592	__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5593	{
AnnaBridge	165:d1b4690b3f8b	5594	SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	165:d1b4690b3f8b	5595	}
AnnaBridge	165:d1b4690b3f8b	5596
AnnaBridge	165:d1b4690b3f8b	5597	/**
AnnaBridge	165:d1b4690b3f8b	5598	* @brief Enable LSE ready interrupt
AnnaBridge	165:d1b4690b3f8b	5599	* @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
AnnaBridge	165:d1b4690b3f8b	5600	* @retval None
AnnaBridge	165:d1b4690b3f8b	5601	*/
AnnaBridge	165:d1b4690b3f8b	5602	__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5603	{
AnnaBridge	165:d1b4690b3f8b	5604	SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	165:d1b4690b3f8b	5605	}
AnnaBridge	165:d1b4690b3f8b	5606
AnnaBridge	165:d1b4690b3f8b	5607	/**
AnnaBridge	165:d1b4690b3f8b	5608	* @brief Enable MSI ready interrupt
AnnaBridge	165:d1b4690b3f8b	5609	* @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY
AnnaBridge	165:d1b4690b3f8b	5610	* @retval None
AnnaBridge	165:d1b4690b3f8b	5611	*/
AnnaBridge	165:d1b4690b3f8b	5612	__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5613	{
AnnaBridge	165:d1b4690b3f8b	5614	SET_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
AnnaBridge	165:d1b4690b3f8b	5615	}
AnnaBridge	165:d1b4690b3f8b	5616
AnnaBridge	165:d1b4690b3f8b	5617	/**
AnnaBridge	165:d1b4690b3f8b	5618	* @brief Enable HSI ready interrupt
AnnaBridge	165:d1b4690b3f8b	5619	* @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
AnnaBridge	165:d1b4690b3f8b	5620	* @retval None
AnnaBridge	165:d1b4690b3f8b	5621	*/
AnnaBridge	165:d1b4690b3f8b	5622	__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5623	{
AnnaBridge	165:d1b4690b3f8b	5624	SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	165:d1b4690b3f8b	5625	}
AnnaBridge	165:d1b4690b3f8b	5626
AnnaBridge	165:d1b4690b3f8b	5627	/**
AnnaBridge	165:d1b4690b3f8b	5628	* @brief Enable HSE ready interrupt
AnnaBridge	165:d1b4690b3f8b	5629	* @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
AnnaBridge	165:d1b4690b3f8b	5630	* @retval None
AnnaBridge	165:d1b4690b3f8b	5631	*/
AnnaBridge	165:d1b4690b3f8b	5632	__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5633	{
AnnaBridge	165:d1b4690b3f8b	5634	SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	165:d1b4690b3f8b	5635	}
AnnaBridge	165:d1b4690b3f8b	5636
AnnaBridge	165:d1b4690b3f8b	5637	/**
AnnaBridge	165:d1b4690b3f8b	5638	* @brief Enable PLL ready interrupt
AnnaBridge	165:d1b4690b3f8b	5639	* @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY
AnnaBridge	165:d1b4690b3f8b	5640	* @retval None
AnnaBridge	165:d1b4690b3f8b	5641	*/
AnnaBridge	165:d1b4690b3f8b	5642	__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
AnnaBridge	165:d1b4690b3f8b	5643	{
AnnaBridge	165:d1b4690b3f8b	5644	SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
AnnaBridge	165:d1b4690b3f8b	5645	}
AnnaBridge	165:d1b4690b3f8b	5646
AnnaBridge	165:d1b4690b3f8b	5647	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5648	/**
AnnaBridge	165:d1b4690b3f8b	5649	* @brief Enable HSI48 ready interrupt
AnnaBridge	165:d1b4690b3f8b	5650	* @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
AnnaBridge	165:d1b4690b3f8b	5651	* @retval None
AnnaBridge	165:d1b4690b3f8b	5652	*/
AnnaBridge	165:d1b4690b3f8b	5653	__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
AnnaBridge	165:d1b4690b3f8b	5654	{
AnnaBridge	165:d1b4690b3f8b	5655	SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	165:d1b4690b3f8b	5656	}
AnnaBridge	165:d1b4690b3f8b	5657	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5658
AnnaBridge	165:d1b4690b3f8b	5659	/**
AnnaBridge	165:d1b4690b3f8b	5660	* @brief Enable PLLSAI1 ready interrupt
AnnaBridge	165:d1b4690b3f8b	5661	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_EnableIT_PLLSAI1RDY
AnnaBridge	165:d1b4690b3f8b	5662	* @retval None
AnnaBridge	165:d1b4690b3f8b	5663	*/
AnnaBridge	165:d1b4690b3f8b	5664	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI1RDY(void)
AnnaBridge	165:d1b4690b3f8b	5665	{
AnnaBridge	165:d1b4690b3f8b	5666	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
AnnaBridge	165:d1b4690b3f8b	5667	}
AnnaBridge	165:d1b4690b3f8b	5668
AnnaBridge	165:d1b4690b3f8b	5669	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5670	/**
AnnaBridge	165:d1b4690b3f8b	5671	* @brief Enable PLLSAI2 ready interrupt
AnnaBridge	165:d1b4690b3f8b	5672	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_EnableIT_PLLSAI2RDY
AnnaBridge	165:d1b4690b3f8b	5673	* @retval None
AnnaBridge	165:d1b4690b3f8b	5674	*/
AnnaBridge	165:d1b4690b3f8b	5675	__STATIC_INLINE void LL_RCC_EnableIT_PLLSAI2RDY(void)
AnnaBridge	165:d1b4690b3f8b	5676	{
AnnaBridge	165:d1b4690b3f8b	5677	SET_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
AnnaBridge	165:d1b4690b3f8b	5678	}
AnnaBridge	165:d1b4690b3f8b	5679	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5680
AnnaBridge	165:d1b4690b3f8b	5681	/**
AnnaBridge	165:d1b4690b3f8b	5682	* @brief Enable LSE clock security system interrupt
AnnaBridge	165:d1b4690b3f8b	5683	* @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
AnnaBridge	165:d1b4690b3f8b	5684	* @retval None
AnnaBridge	165:d1b4690b3f8b	5685	*/
AnnaBridge	165:d1b4690b3f8b	5686	__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5687	{
AnnaBridge	165:d1b4690b3f8b	5688	SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	165:d1b4690b3f8b	5689	}
AnnaBridge	165:d1b4690b3f8b	5690
AnnaBridge	165:d1b4690b3f8b	5691	/**
AnnaBridge	165:d1b4690b3f8b	5692	* @brief Disable LSI ready interrupt
AnnaBridge	165:d1b4690b3f8b	5693	* @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
AnnaBridge	165:d1b4690b3f8b	5694	* @retval None
AnnaBridge	165:d1b4690b3f8b	5695	*/
AnnaBridge	165:d1b4690b3f8b	5696	__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5697	{
AnnaBridge	165:d1b4690b3f8b	5698	CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
AnnaBridge	165:d1b4690b3f8b	5699	}
AnnaBridge	165:d1b4690b3f8b	5700
AnnaBridge	165:d1b4690b3f8b	5701	/**
AnnaBridge	165:d1b4690b3f8b	5702	* @brief Disable LSE ready interrupt
AnnaBridge	165:d1b4690b3f8b	5703	* @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
AnnaBridge	165:d1b4690b3f8b	5704	* @retval None
AnnaBridge	165:d1b4690b3f8b	5705	*/
AnnaBridge	165:d1b4690b3f8b	5706	__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5707	{
AnnaBridge	165:d1b4690b3f8b	5708	CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
AnnaBridge	165:d1b4690b3f8b	5709	}
AnnaBridge	165:d1b4690b3f8b	5710
AnnaBridge	165:d1b4690b3f8b	5711	/**
AnnaBridge	165:d1b4690b3f8b	5712	* @brief Disable MSI ready interrupt
AnnaBridge	165:d1b4690b3f8b	5713	* @rmtoll CIER MSIRDYIE LL_RCC_DisableIT_MSIRDY
AnnaBridge	165:d1b4690b3f8b	5714	* @retval None
AnnaBridge	165:d1b4690b3f8b	5715	*/
AnnaBridge	165:d1b4690b3f8b	5716	__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5717	{
AnnaBridge	165:d1b4690b3f8b	5718	CLEAR_BIT(RCC->CIER, RCC_CIER_MSIRDYIE);
AnnaBridge	165:d1b4690b3f8b	5719	}
AnnaBridge	165:d1b4690b3f8b	5720
AnnaBridge	165:d1b4690b3f8b	5721	/**
AnnaBridge	165:d1b4690b3f8b	5722	* @brief Disable HSI ready interrupt
AnnaBridge	165:d1b4690b3f8b	5723	* @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
AnnaBridge	165:d1b4690b3f8b	5724	* @retval None
AnnaBridge	165:d1b4690b3f8b	5725	*/
AnnaBridge	165:d1b4690b3f8b	5726	__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5727	{
AnnaBridge	165:d1b4690b3f8b	5728	CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
AnnaBridge	165:d1b4690b3f8b	5729	}
AnnaBridge	165:d1b4690b3f8b	5730
AnnaBridge	165:d1b4690b3f8b	5731	/**
AnnaBridge	165:d1b4690b3f8b	5732	* @brief Disable HSE ready interrupt
AnnaBridge	165:d1b4690b3f8b	5733	* @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
AnnaBridge	165:d1b4690b3f8b	5734	* @retval None
AnnaBridge	165:d1b4690b3f8b	5735	*/
AnnaBridge	165:d1b4690b3f8b	5736	__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5737	{
AnnaBridge	165:d1b4690b3f8b	5738	CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
AnnaBridge	165:d1b4690b3f8b	5739	}
AnnaBridge	165:d1b4690b3f8b	5740
AnnaBridge	165:d1b4690b3f8b	5741	/**
AnnaBridge	165:d1b4690b3f8b	5742	* @brief Disable PLL ready interrupt
AnnaBridge	165:d1b4690b3f8b	5743	* @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY
AnnaBridge	165:d1b4690b3f8b	5744	* @retval None
AnnaBridge	165:d1b4690b3f8b	5745	*/
AnnaBridge	165:d1b4690b3f8b	5746	__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
AnnaBridge	165:d1b4690b3f8b	5747	{
AnnaBridge	165:d1b4690b3f8b	5748	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE);
AnnaBridge	165:d1b4690b3f8b	5749	}
AnnaBridge	165:d1b4690b3f8b	5750
AnnaBridge	165:d1b4690b3f8b	5751	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5752	/**
AnnaBridge	165:d1b4690b3f8b	5753	* @brief Disable HSI48 ready interrupt
AnnaBridge	165:d1b4690b3f8b	5754	* @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
AnnaBridge	165:d1b4690b3f8b	5755	* @retval None
AnnaBridge	165:d1b4690b3f8b	5756	*/
AnnaBridge	165:d1b4690b3f8b	5757	__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
AnnaBridge	165:d1b4690b3f8b	5758	{
AnnaBridge	165:d1b4690b3f8b	5759	CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
AnnaBridge	165:d1b4690b3f8b	5760	}
AnnaBridge	165:d1b4690b3f8b	5761	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5762
AnnaBridge	165:d1b4690b3f8b	5763	/**
AnnaBridge	165:d1b4690b3f8b	5764	* @brief Disable PLLSAI1 ready interrupt
AnnaBridge	165:d1b4690b3f8b	5765	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_DisableIT_PLLSAI1RDY
AnnaBridge	165:d1b4690b3f8b	5766	* @retval None
AnnaBridge	165:d1b4690b3f8b	5767	*/
AnnaBridge	165:d1b4690b3f8b	5768	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI1RDY(void)
AnnaBridge	165:d1b4690b3f8b	5769	{
AnnaBridge	165:d1b4690b3f8b	5770	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE);
AnnaBridge	165:d1b4690b3f8b	5771	}
AnnaBridge	165:d1b4690b3f8b	5772
AnnaBridge	165:d1b4690b3f8b	5773	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5774	/**
AnnaBridge	165:d1b4690b3f8b	5775	* @brief Disable PLLSAI2 ready interrupt
AnnaBridge	165:d1b4690b3f8b	5776	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_DisableIT_PLLSAI2RDY
AnnaBridge	165:d1b4690b3f8b	5777	* @retval None
AnnaBridge	165:d1b4690b3f8b	5778	*/
AnnaBridge	165:d1b4690b3f8b	5779	__STATIC_INLINE void LL_RCC_DisableIT_PLLSAI2RDY(void)
AnnaBridge	165:d1b4690b3f8b	5780	{
AnnaBridge	165:d1b4690b3f8b	5781	CLEAR_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE);
AnnaBridge	165:d1b4690b3f8b	5782	}
AnnaBridge	165:d1b4690b3f8b	5783	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5784
AnnaBridge	165:d1b4690b3f8b	5785	/**
AnnaBridge	165:d1b4690b3f8b	5786	* @brief Disable LSE clock security system interrupt
AnnaBridge	165:d1b4690b3f8b	5787	* @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
AnnaBridge	165:d1b4690b3f8b	5788	* @retval None
AnnaBridge	165:d1b4690b3f8b	5789	*/
AnnaBridge	165:d1b4690b3f8b	5790	__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5791	{
AnnaBridge	165:d1b4690b3f8b	5792	CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
AnnaBridge	165:d1b4690b3f8b	5793	}
AnnaBridge	165:d1b4690b3f8b	5794
AnnaBridge	165:d1b4690b3f8b	5795	/**
AnnaBridge	165:d1b4690b3f8b	5796	* @brief Checks if LSI ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5797	* @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
AnnaBridge	165:d1b4690b3f8b	5798	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5799	*/
AnnaBridge	165:d1b4690b3f8b	5800	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5801	{
AnnaBridge	165:d1b4690b3f8b	5802	return (READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE));
AnnaBridge	165:d1b4690b3f8b	5803	}
AnnaBridge	165:d1b4690b3f8b	5804
AnnaBridge	165:d1b4690b3f8b	5805	/**
AnnaBridge	165:d1b4690b3f8b	5806	* @brief Checks if LSE ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5807	* @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY
AnnaBridge	165:d1b4690b3f8b	5808	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5809	*/
AnnaBridge	165:d1b4690b3f8b	5810	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5811	{
AnnaBridge	165:d1b4690b3f8b	5812	return (READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE));
AnnaBridge	165:d1b4690b3f8b	5813	}
AnnaBridge	165:d1b4690b3f8b	5814
AnnaBridge	165:d1b4690b3f8b	5815	/**
AnnaBridge	165:d1b4690b3f8b	5816	* @brief Checks if MSI ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5817	* @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY
AnnaBridge	165:d1b4690b3f8b	5818	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5819	*/
AnnaBridge	165:d1b4690b3f8b	5820	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5821	{
AnnaBridge	165:d1b4690b3f8b	5822	return (READ_BIT(RCC->CIER, RCC_CIER_MSIRDYIE) == (RCC_CIER_MSIRDYIE));
AnnaBridge	165:d1b4690b3f8b	5823	}
AnnaBridge	165:d1b4690b3f8b	5824
AnnaBridge	165:d1b4690b3f8b	5825	/**
AnnaBridge	165:d1b4690b3f8b	5826	* @brief Checks if HSI ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5827	* @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
AnnaBridge	165:d1b4690b3f8b	5828	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5829	*/
AnnaBridge	165:d1b4690b3f8b	5830	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
AnnaBridge	165:d1b4690b3f8b	5831	{
AnnaBridge	165:d1b4690b3f8b	5832	return (READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE));
AnnaBridge	165:d1b4690b3f8b	5833	}
AnnaBridge	165:d1b4690b3f8b	5834
AnnaBridge	165:d1b4690b3f8b	5835	/**
AnnaBridge	165:d1b4690b3f8b	5836	* @brief Checks if HSE ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5837	* @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY
AnnaBridge	165:d1b4690b3f8b	5838	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5839	*/
AnnaBridge	165:d1b4690b3f8b	5840	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
AnnaBridge	165:d1b4690b3f8b	5841	{
AnnaBridge	165:d1b4690b3f8b	5842	return (READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE));
AnnaBridge	165:d1b4690b3f8b	5843	}
AnnaBridge	165:d1b4690b3f8b	5844
AnnaBridge	165:d1b4690b3f8b	5845	/**
AnnaBridge	165:d1b4690b3f8b	5846	* @brief Checks if PLL ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5847	* @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
AnnaBridge	165:d1b4690b3f8b	5848	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5849	*/
AnnaBridge	165:d1b4690b3f8b	5850	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
AnnaBridge	165:d1b4690b3f8b	5851	{
AnnaBridge	165:d1b4690b3f8b	5852	return (READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE));
AnnaBridge	165:d1b4690b3f8b	5853	}
AnnaBridge	165:d1b4690b3f8b	5854
AnnaBridge	165:d1b4690b3f8b	5855	#if defined(RCC_HSI48_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5856	/**
AnnaBridge	165:d1b4690b3f8b	5857	* @brief Checks if HSI48 ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5858	* @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY
AnnaBridge	165:d1b4690b3f8b	5859	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5860	*/
AnnaBridge	165:d1b4690b3f8b	5861	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void)
AnnaBridge	165:d1b4690b3f8b	5862	{
AnnaBridge	165:d1b4690b3f8b	5863	return (READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == (RCC_CIER_HSI48RDYIE));
AnnaBridge	165:d1b4690b3f8b	5864	}
AnnaBridge	165:d1b4690b3f8b	5865	#endif /* RCC_HSI48_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5866
AnnaBridge	165:d1b4690b3f8b	5867	/**
AnnaBridge	165:d1b4690b3f8b	5868	* @brief Checks if PLLSAI1 ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5869	* @rmtoll CIER PLLSAI1RDYIE LL_RCC_IsEnabledIT_PLLSAI1RDY
AnnaBridge	165:d1b4690b3f8b	5870	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5871	*/
AnnaBridge	165:d1b4690b3f8b	5872	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI1RDY(void)
AnnaBridge	165:d1b4690b3f8b	5873	{
AnnaBridge	165:d1b4690b3f8b	5874	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI1RDYIE) == (RCC_CIER_PLLSAI1RDYIE));
AnnaBridge	165:d1b4690b3f8b	5875	}
AnnaBridge	165:d1b4690b3f8b	5876
AnnaBridge	165:d1b4690b3f8b	5877	#if defined(RCC_PLLSAI2_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	5878	/**
AnnaBridge	165:d1b4690b3f8b	5879	* @brief Checks if PLLSAI2 ready interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5880	* @rmtoll CIER PLLSAI2RDYIE LL_RCC_IsEnabledIT_PLLSAI2RDY
AnnaBridge	165:d1b4690b3f8b	5881	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5882	*/
AnnaBridge	165:d1b4690b3f8b	5883	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAI2RDY(void)
AnnaBridge	165:d1b4690b3f8b	5884	{
AnnaBridge	165:d1b4690b3f8b	5885	return (READ_BIT(RCC->CIER, RCC_CIER_PLLSAI2RDYIE) == (RCC_CIER_PLLSAI2RDYIE));
AnnaBridge	165:d1b4690b3f8b	5886	}
AnnaBridge	165:d1b4690b3f8b	5887	#endif /* RCC_PLLSAI2_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	5888
AnnaBridge	165:d1b4690b3f8b	5889	/**
AnnaBridge	165:d1b4690b3f8b	5890	* @brief Checks if LSECSS interrupt source is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	5891	* @rmtoll CIER LSECSSIE LL_RCC_IsEnabledIT_LSECSS
AnnaBridge	165:d1b4690b3f8b	5892	* @retval State of bit (1 or 0).
AnnaBridge	165:d1b4690b3f8b	5893	*/
AnnaBridge	165:d1b4690b3f8b	5894	__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSECSS(void)
AnnaBridge	165:d1b4690b3f8b	5895	{
AnnaBridge	165:d1b4690b3f8b	5896	return (READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == (RCC_CIER_LSECSSIE));
AnnaBridge	165:d1b4690b3f8b	5897	}
AnnaBridge	165:d1b4690b3f8b	5898
AnnaBridge	165:d1b4690b3f8b	5899	/**
AnnaBridge	165:d1b4690b3f8b	5900	* @}
AnnaBridge	165:d1b4690b3f8b	5901	*/
AnnaBridge	165:d1b4690b3f8b	5902
AnnaBridge	165:d1b4690b3f8b	5903	#if defined(USE_FULL_LL_DRIVER)
AnnaBridge	165:d1b4690b3f8b	5904	/** @defgroup RCC_LL_EF_Init De-initialization function
AnnaBridge	165:d1b4690b3f8b	5905	* @{
AnnaBridge	165:d1b4690b3f8b	5906	*/
AnnaBridge	165:d1b4690b3f8b	5907	ErrorStatus LL_RCC_DeInit(void);
AnnaBridge	165:d1b4690b3f8b	5908	/**
AnnaBridge	165:d1b4690b3f8b	5909	* @}
AnnaBridge	165:d1b4690b3f8b	5910	*/
AnnaBridge	165:d1b4690b3f8b	5911
AnnaBridge	165:d1b4690b3f8b	5912	/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
AnnaBridge	165:d1b4690b3f8b	5913	* @{
AnnaBridge	165:d1b4690b3f8b	5914	*/
AnnaBridge	165:d1b4690b3f8b	5915	void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
AnnaBridge	165:d1b4690b3f8b	5916	uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
AnnaBridge	165:d1b4690b3f8b	5917	#if defined(UART4) \|\| defined(UART5)
AnnaBridge	165:d1b4690b3f8b	5918	uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
AnnaBridge	165:d1b4690b3f8b	5919	#endif /* UART4 \|\| UART5 */
AnnaBridge	165:d1b4690b3f8b	5920	uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
AnnaBridge	165:d1b4690b3f8b	5921	uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
AnnaBridge	165:d1b4690b3f8b	5922	uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
AnnaBridge	165:d1b4690b3f8b	5923	uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
AnnaBridge	165:d1b4690b3f8b	5924	#if defined(RCC_CCIPR2_SDMMCSEL)
AnnaBridge	165:d1b4690b3f8b	5925	uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource);
AnnaBridge	165:d1b4690b3f8b	5926	#endif
AnnaBridge	165:d1b4690b3f8b	5927	uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
AnnaBridge	165:d1b4690b3f8b	5928	uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
AnnaBridge	165:d1b4690b3f8b	5929	#if defined(USB_OTG_FS) \|\| defined(USB)
AnnaBridge	165:d1b4690b3f8b	5930	uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
AnnaBridge	165:d1b4690b3f8b	5931	#endif /* USB_OTG_FS \|\| USB */
AnnaBridge	165:d1b4690b3f8b	5932	uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
AnnaBridge	165:d1b4690b3f8b	5933	#if defined(SWPMI1)
AnnaBridge	165:d1b4690b3f8b	5934	uint32_t LL_RCC_GetSWPMIClockFreq(uint32_t SWPMIxSource);
AnnaBridge	165:d1b4690b3f8b	5935	#endif /* SWPMI1 */
AnnaBridge	165:d1b4690b3f8b	5936	#if defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	5937	uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
AnnaBridge	165:d1b4690b3f8b	5938	#if defined(RCC_CCIPR2_DFSDM1SEL)
AnnaBridge	165:d1b4690b3f8b	5939	uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
AnnaBridge	165:d1b4690b3f8b	5940	#endif /* RCC_CCIPR2_DFSDM1SEL */
AnnaBridge	165:d1b4690b3f8b	5941	#endif /* DFSDM1_Channel0 */
AnnaBridge	165:d1b4690b3f8b	5942	#if defined(LTDC)
AnnaBridge	165:d1b4690b3f8b	5943	uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
AnnaBridge	165:d1b4690b3f8b	5944	#endif /* LTDC */
AnnaBridge	165:d1b4690b3f8b	5945	#if defined(DSI)
AnnaBridge	165:d1b4690b3f8b	5946	uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
AnnaBridge	165:d1b4690b3f8b	5947	#endif /* DSI */
AnnaBridge	165:d1b4690b3f8b	5948	#if defined(OCTOSPI1)
AnnaBridge	165:d1b4690b3f8b	5949	uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource);
AnnaBridge	165:d1b4690b3f8b	5950	#endif /* OCTOSPI1 */
AnnaBridge	165:d1b4690b3f8b	5951	/**
AnnaBridge	165:d1b4690b3f8b	5952	* @}
AnnaBridge	165:d1b4690b3f8b	5953	*/
AnnaBridge	165:d1b4690b3f8b	5954	#endif /* USE_FULL_LL_DRIVER */
AnnaBridge	165:d1b4690b3f8b	5955
AnnaBridge	165:d1b4690b3f8b	5956	/**
AnnaBridge	165:d1b4690b3f8b	5957	* @}
AnnaBridge	165:d1b4690b3f8b	5958	*/
AnnaBridge	165:d1b4690b3f8b	5959
AnnaBridge	165:d1b4690b3f8b	5960	/**
AnnaBridge	165:d1b4690b3f8b	5961	* @}
AnnaBridge	165:d1b4690b3f8b	5962	*/
AnnaBridge	165:d1b4690b3f8b	5963
AnnaBridge	165:d1b4690b3f8b	5964	#endif /* defined(RCC) */
AnnaBridge	165:d1b4690b3f8b	5965
AnnaBridge	165:d1b4690b3f8b	5966	/**
AnnaBridge	165:d1b4690b3f8b	5967	* @}
AnnaBridge	165:d1b4690b3f8b	5968	*/
AnnaBridge	165:d1b4690b3f8b	5969
AnnaBridge	165:d1b4690b3f8b	5970	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	5971	}
AnnaBridge	165:d1b4690b3f8b	5972	#endif
AnnaBridge	165:d1b4690b3f8b	5973
AnnaBridge	165:d1b4690b3f8b	5974	#endif /* __STM32L4xx_LL_RCC_H */
AnnaBridge	165:d1b4690b3f8b	5975
AnnaBridge	165:d1b4690b3f8b	5976	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/