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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_qspi.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:
AnnaBridge
Date:
Thu Nov 08 11:45:42 2018 +0000
Revision:
171:3a7713b1edbc
Parent:
TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h@161:aa5281ff4a02 
mbed library. Release version 164

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**
AnnaBridge 145:64910690c574 2 ******************************************************************************
AnnaBridge 145:64910690c574 3 * @file stm32l4xx_hal_qspi.h
AnnaBridge 145:64910690c574 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @brief Header file of QSPI HAL module.
AnnaBridge 145:64910690c574 6 ******************************************************************************
AnnaBridge 145:64910690c574 7 * @attention
AnnaBridge 145:64910690c574 8 *
AnnaBridge 145:64910690c574 9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 145:64910690c574 10 *
AnnaBridge 145:64910690c574 11 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 145:64910690c574 12 * are permitted provided that the following conditions are met:
AnnaBridge 145:64910690c574 13 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 145:64910690c574 14 * this list of conditions and the following disclaimer.
AnnaBridge 145:64910690c574 15 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 145:64910690c574 16 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 145:64910690c574 17 * and/or other materials provided with the distribution.
AnnaBridge 145:64910690c574 18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 145:64910690c574 19 * may be used to endorse or promote products derived from this software
AnnaBridge 145:64910690c574 20 * without specific prior written permission.
AnnaBridge 145:64910690c574 21 *
AnnaBridge 145:64910690c574 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 145:64910690c574 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 145:64910690c574 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 145:64910690c574 25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 145:64910690c574 26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 145:64910690c574 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 145:64910690c574 28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 145:64910690c574 29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 145:64910690c574 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 145:64910690c574 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 145:64910690c574 32 *
AnnaBridge 145:64910690c574 33 ******************************************************************************
AnnaBridge 145:64910690c574 34 */
AnnaBridge 145:64910690c574 35
AnnaBridge 145:64910690c574 36 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 145:64910690c574 37 #ifndef __STM32L4xx_HAL_QSPI_H
AnnaBridge 145:64910690c574 38 #define __STM32L4xx_HAL_QSPI_H
AnnaBridge 145:64910690c574 39
AnnaBridge 145:64910690c574 40 #ifdef __cplusplus
AnnaBridge 145:64910690c574 41 extern "C" {
AnnaBridge 145:64910690c574 42 #endif
AnnaBridge 145:64910690c574 43
AnnaBridge 145:64910690c574 44 /* Includes ------------------------------------------------------------------*/
AnnaBridge 145:64910690c574 45 #include "stm32l4xx_hal_def.h"
AnnaBridge 145:64910690c574 46
AnnaBridge 161:aa5281ff4a02 47 #if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2)
AnnaBridge 161:aa5281ff4a02 48
AnnaBridge 145:64910690c574 49 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 145:64910690c574 50 * @{
AnnaBridge 145:64910690c574 51 */
AnnaBridge 145:64910690c574 52
AnnaBridge 145:64910690c574 53 /** @addtogroup QSPI
AnnaBridge 145:64910690c574 54 * @{
AnnaBridge 145:64910690c574 55 */
AnnaBridge 145:64910690c574 56
AnnaBridge 145:64910690c574 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 58 /** @defgroup QSPI_Exported_Types QSPI Exported Types
AnnaBridge 145:64910690c574 59 * @{
AnnaBridge 145:64910690c574 60 */
AnnaBridge 145:64910690c574 61
AnnaBridge 145:64910690c574 62 /**
AnnaBridge 145:64910690c574 63 * @brief QSPI Init structure definition
AnnaBridge 145:64910690c574 64 */
AnnaBridge 145:64910690c574 65 typedef struct
AnnaBridge 145:64910690c574 66 {
AnnaBridge 145:64910690c574 67 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
AnnaBridge 145:64910690c574 68 This parameter can be a number between 0 and 255 */
AnnaBridge 145:64910690c574 69 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
AnnaBridge 145:64910690c574 70 This parameter can be a value between 1 and 16 */
AnnaBridge 145:64910690c574 71 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
AnnaBridge 145:64910690c574 72 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
AnnaBridge 145:64910690c574 73 This parameter can be a value of @ref QSPI_SampleShifting */
AnnaBridge 145:64910690c574 74 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
AnnaBridge 145:64910690c574 75 required to address the flash memory. The flash capacity can be up to 4GB
AnnaBridge 145:64910690c574 76 (addressed using 32 bits) in indirect mode, but the addressable space in
AnnaBridge 145:64910690c574 77 memory-mapped mode is limited to 256MB
AnnaBridge 145:64910690c574 78 This parameter can be a number between 0 and 31 */
AnnaBridge 145:64910690c574 79 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
AnnaBridge 145:64910690c574 80 of clock cycles which the chip select must remain high between commands.
AnnaBridge 145:64910690c574 81 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
AnnaBridge 145:64910690c574 82 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
AnnaBridge 145:64910690c574 83 This parameter can be a value of @ref QSPI_ClockMode */
AnnaBridge 161:aa5281ff4a02 84 #if defined(QUADSPI_CR_DFM)
AnnaBridge 145:64910690c574 85 uint32_t FlashID; /* Specifies the Flash which will be used,
AnnaBridge 145:64910690c574 86 This parameter can be a value of @ref QSPI_Flash_Select */
AnnaBridge 145:64910690c574 87 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
AnnaBridge 145:64910690c574 88 This parameter can be a value of @ref QSPI_DualFlash_Mode */
AnnaBridge 145:64910690c574 89 #endif
AnnaBridge 145:64910690c574 90 }QSPI_InitTypeDef;
AnnaBridge 145:64910690c574 91
AnnaBridge 145:64910690c574 92 /**
AnnaBridge 145:64910690c574 93 * @brief HAL QSPI State structures definition
AnnaBridge 145:64910690c574 94 */
AnnaBridge 145:64910690c574 95 typedef enum
AnnaBridge 145:64910690c574 96 {
AnnaBridge 145:64910690c574 97 HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
AnnaBridge 145:64910690c574 98 HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
AnnaBridge 145:64910690c574 99 HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
AnnaBridge 145:64910690c574 100 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
AnnaBridge 145:64910690c574 101 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
AnnaBridge 145:64910690c574 102 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
AnnaBridge 145:64910690c574 103 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
AnnaBridge 145:64910690c574 104 HAL_QSPI_STATE_ABORT = 0x08, /*!< Peripheral with abort request ongoing */
AnnaBridge 145:64910690c574 105 HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
AnnaBridge 145:64910690c574 106 }HAL_QSPI_StateTypeDef;
AnnaBridge 145:64910690c574 107
AnnaBridge 145:64910690c574 108 /**
AnnaBridge 145:64910690c574 109 * @brief QSPI Handle Structure definition
AnnaBridge 145:64910690c574 110 */
AnnaBridge 145:64910690c574 111 typedef struct
AnnaBridge 145:64910690c574 112 {
AnnaBridge 145:64910690c574 113 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
AnnaBridge 145:64910690c574 114 QSPI_InitTypeDef Init; /* QSPI communication parameters */
AnnaBridge 145:64910690c574 115 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
AnnaBridge 145:64910690c574 116 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge 145:64910690c574 117 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
AnnaBridge 145:64910690c574 118 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
AnnaBridge 145:64910690c574 119 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge 145:64910690c574 120 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
AnnaBridge 145:64910690c574 121 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
AnnaBridge 145:64910690c574 122 __IO HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge 145:64910690c574 123 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
AnnaBridge 145:64910690c574 124 __IO uint32_t ErrorCode; /* QSPI Error code */
AnnaBridge 145:64910690c574 125 uint32_t Timeout; /* Timeout for the QSPI memory access */
AnnaBridge 145:64910690c574 126 }QSPI_HandleTypeDef;
AnnaBridge 145:64910690c574 127
AnnaBridge 145:64910690c574 128 /**
AnnaBridge 145:64910690c574 129 * @brief QSPI Command structure definition
AnnaBridge 145:64910690c574 130 */
AnnaBridge 145:64910690c574 131 typedef struct
AnnaBridge 145:64910690c574 132 {
AnnaBridge 145:64910690c574 133 uint32_t Instruction; /* Specifies the Instruction to be sent
AnnaBridge 145:64910690c574 134 This parameter can be a value (8-bit) between 0x00 and 0xFF */
AnnaBridge 145:64910690c574 135 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
AnnaBridge 145:64910690c574 136 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 137 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
AnnaBridge 145:64910690c574 138 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 139 uint32_t AddressSize; /* Specifies the Address Size
AnnaBridge 145:64910690c574 140 This parameter can be a value of @ref QSPI_AddressSize */
AnnaBridge 145:64910690c574 141 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
AnnaBridge 145:64910690c574 142 This parameter can be a value of @ref QSPI_AlternateBytesSize */
AnnaBridge 145:64910690c574 143 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
AnnaBridge 145:64910690c574 144 This parameter can be a number between 0 and 31 */
AnnaBridge 145:64910690c574 145 uint32_t InstructionMode; /* Specifies the Instruction Mode
AnnaBridge 145:64910690c574 146 This parameter can be a value of @ref QSPI_InstructionMode */
AnnaBridge 145:64910690c574 147 uint32_t AddressMode; /* Specifies the Address Mode
AnnaBridge 145:64910690c574 148 This parameter can be a value of @ref QSPI_AddressMode */
AnnaBridge 145:64910690c574 149 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
AnnaBridge 145:64910690c574 150 This parameter can be a value of @ref QSPI_AlternateBytesMode */
AnnaBridge 145:64910690c574 151 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
AnnaBridge 145:64910690c574 152 This parameter can be a value of @ref QSPI_DataMode */
AnnaBridge 145:64910690c574 153 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
AnnaBridge 145:64910690c574 154 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
AnnaBridge 145:64910690c574 155 until end of memory)*/
AnnaBridge 145:64910690c574 156 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
AnnaBridge 145:64910690c574 157 This parameter can be a value of @ref QSPI_DdrMode */
AnnaBridge 145:64910690c574 158 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
AnnaBridge 145:64910690c574 159 system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
AnnaBridge 145:64910690c574 160 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
AnnaBridge 145:64910690c574 161 uint32_t SIOOMode; /* Specifies the send instruction only once mode
AnnaBridge 145:64910690c574 162 This parameter can be a value of @ref QSPI_SIOOMode */
AnnaBridge 145:64910690c574 163 }QSPI_CommandTypeDef;
AnnaBridge 145:64910690c574 164
AnnaBridge 145:64910690c574 165 /**
AnnaBridge 145:64910690c574 166 * @brief QSPI Auto Polling mode configuration structure definition
AnnaBridge 145:64910690c574 167 */
AnnaBridge 145:64910690c574 168 typedef struct
AnnaBridge 145:64910690c574 169 {
AnnaBridge 145:64910690c574 170 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
AnnaBridge 145:64910690c574 171 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 172 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
AnnaBridge 145:64910690c574 173 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 174 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
AnnaBridge 145:64910690c574 175 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 145:64910690c574 176 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
AnnaBridge 145:64910690c574 177 This parameter can be any value between 1 and 4 */
AnnaBridge 145:64910690c574 178 uint32_t MatchMode; /* Specifies the method used for determining a match.
AnnaBridge 145:64910690c574 179 This parameter can be a value of @ref QSPI_MatchMode */
AnnaBridge 145:64910690c574 180 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
AnnaBridge 145:64910690c574 181 This parameter can be a value of @ref QSPI_AutomaticStop */
AnnaBridge 145:64910690c574 182 }QSPI_AutoPollingTypeDef;
AnnaBridge 145:64910690c574 183
AnnaBridge 145:64910690c574 184 /**
AnnaBridge 145:64910690c574 185 * @brief QSPI Memory Mapped mode configuration structure definition
AnnaBridge 145:64910690c574 186 */
AnnaBridge 145:64910690c574 187 typedef struct
AnnaBridge 145:64910690c574 188 {
AnnaBridge 145:64910690c574 189 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
AnnaBridge 145:64910690c574 190 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 145:64910690c574 191 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
AnnaBridge 145:64910690c574 192 This parameter can be a value of @ref QSPI_TimeOutActivation */
AnnaBridge 145:64910690c574 193 }QSPI_MemoryMappedTypeDef;
AnnaBridge 145:64910690c574 194
AnnaBridge 145:64910690c574 195 /**
AnnaBridge 145:64910690c574 196 * @}
AnnaBridge 145:64910690c574 197 */
AnnaBridge 145:64910690c574 198
AnnaBridge 145:64910690c574 199 /* Exported constants --------------------------------------------------------*/
AnnaBridge 145:64910690c574 200 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
AnnaBridge 145:64910690c574 201 * @{
AnnaBridge 145:64910690c574 202 */
AnnaBridge 145:64910690c574 203
AnnaBridge 145:64910690c574 204 /** @defgroup QSPI_ErrorCode QSPI Error Code
AnnaBridge 145:64910690c574 205 * @{
AnnaBridge 145:64910690c574 206 */
AnnaBridge 161:aa5281ff4a02 207 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
AnnaBridge 161:aa5281ff4a02 208 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
AnnaBridge 161:aa5281ff4a02 209 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
AnnaBridge 161:aa5281ff4a02 210 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
AnnaBridge 145:64910690c574 211 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */
AnnaBridge 145:64910690c574 212 /**
AnnaBridge 145:64910690c574 213 * @}
AnnaBridge 145:64910690c574 214 */
AnnaBridge 145:64910690c574 215
AnnaBridge 145:64910690c574 216 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
AnnaBridge 145:64910690c574 217 * @{
AnnaBridge 145:64910690c574 218 */
AnnaBridge 145:64910690c574 219 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
AnnaBridge 145:64910690c574 220 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
AnnaBridge 145:64910690c574 221 /**
AnnaBridge 145:64910690c574 222 * @}
AnnaBridge 145:64910690c574 223 */
AnnaBridge 145:64910690c574 224
AnnaBridge 145:64910690c574 225 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
AnnaBridge 145:64910690c574 226 * @{
AnnaBridge 145:64910690c574 227 */
AnnaBridge 145:64910690c574 228 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
AnnaBridge 145:64910690c574 229 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
AnnaBridge 145:64910690c574 230 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
AnnaBridge 145:64910690c574 231 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
AnnaBridge 145:64910690c574 232 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
AnnaBridge 145:64910690c574 233 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
AnnaBridge 145:64910690c574 234 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
AnnaBridge 145:64910690c574 235 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
AnnaBridge 145:64910690c574 236 /**
AnnaBridge 145:64910690c574 237 * @}
AnnaBridge 145:64910690c574 238 */
AnnaBridge 145:64910690c574 239
AnnaBridge 145:64910690c574 240 /** @defgroup QSPI_ClockMode QSPI Clock Mode
AnnaBridge 145:64910690c574 241 * @{
AnnaBridge 145:64910690c574 242 */
AnnaBridge 145:64910690c574 243 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
AnnaBridge 145:64910690c574 244 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
AnnaBridge 145:64910690c574 245 /**
AnnaBridge 145:64910690c574 246 * @}
AnnaBridge 145:64910690c574 247 */
AnnaBridge 145:64910690c574 248
AnnaBridge 161:aa5281ff4a02 249 #if defined(QUADSPI_CR_DFM)
AnnaBridge 145:64910690c574 250 /** @defgroup QSPI_Flash_Select QSPI Flash Select
AnnaBridge 145:64910690c574 251 * @{
AnnaBridge 145:64910690c574 252 */
AnnaBridge 145:64910690c574 253 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
AnnaBridge 145:64910690c574 254 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
AnnaBridge 145:64910690c574 255 /**
AnnaBridge 145:64910690c574 256 * @}
AnnaBridge 145:64910690c574 257 */
AnnaBridge 145:64910690c574 258
AnnaBridge 145:64910690c574 259 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
AnnaBridge 145:64910690c574 260 * @{
AnnaBridge 145:64910690c574 261 */
AnnaBridge 145:64910690c574 262 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
AnnaBridge 145:64910690c574 263 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
AnnaBridge 145:64910690c574 264 /**
AnnaBridge 145:64910690c574 265 * @}
AnnaBridge 145:64910690c574 266 */
AnnaBridge 145:64910690c574 267 #endif
AnnaBridge 145:64910690c574 268
AnnaBridge 145:64910690c574 269 /** @defgroup QSPI_AddressSize QSPI Address Size
AnnaBridge 145:64910690c574 270 * @{
AnnaBridge 145:64910690c574 271 */
AnnaBridge 145:64910690c574 272 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
AnnaBridge 145:64910690c574 273 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
AnnaBridge 145:64910690c574 274 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
AnnaBridge 145:64910690c574 275 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
AnnaBridge 145:64910690c574 276 /**
AnnaBridge 145:64910690c574 277 * @}
AnnaBridge 145:64910690c574 278 */
AnnaBridge 145:64910690c574 279
AnnaBridge 145:64910690c574 280 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
AnnaBridge 145:64910690c574 281 * @{
AnnaBridge 145:64910690c574 282 */
AnnaBridge 145:64910690c574 283 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
AnnaBridge 145:64910690c574 284 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
AnnaBridge 145:64910690c574 285 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
AnnaBridge 145:64910690c574 286 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
AnnaBridge 145:64910690c574 287 /**
AnnaBridge 145:64910690c574 288 * @}
AnnaBridge 145:64910690c574 289 */
AnnaBridge 145:64910690c574 290
AnnaBridge 145:64910690c574 291 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
AnnaBridge 145:64910690c574 292 * @{
AnnaBridge 145:64910690c574 293 */
AnnaBridge 145:64910690c574 294 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
AnnaBridge 145:64910690c574 295 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
AnnaBridge 145:64910690c574 296 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
AnnaBridge 145:64910690c574 297 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
AnnaBridge 145:64910690c574 298 /**
AnnaBridge 145:64910690c574 299 * @}
AnnaBridge 145:64910690c574 300 */
AnnaBridge 145:64910690c574 301
AnnaBridge 145:64910690c574 302 /** @defgroup QSPI_AddressMode QSPI Address Mode
AnnaBridge 145:64910690c574 303 * @{
AnnaBridge 145:64910690c574 304 */
AnnaBridge 145:64910690c574 305 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
AnnaBridge 145:64910690c574 306 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
AnnaBridge 145:64910690c574 307 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
AnnaBridge 145:64910690c574 308 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
AnnaBridge 145:64910690c574 309 /**
AnnaBridge 145:64910690c574 310 * @}
AnnaBridge 145:64910690c574 311 */
AnnaBridge 145:64910690c574 312
AnnaBridge 145:64910690c574 313 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
AnnaBridge 145:64910690c574 314 * @{
AnnaBridge 145:64910690c574 315 */
AnnaBridge 145:64910690c574 316 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
AnnaBridge 145:64910690c574 317 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
AnnaBridge 145:64910690c574 318 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
AnnaBridge 145:64910690c574 319 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
AnnaBridge 145:64910690c574 320 /**
AnnaBridge 145:64910690c574 321 * @}
AnnaBridge 145:64910690c574 322 */
AnnaBridge 145:64910690c574 323
AnnaBridge 145:64910690c574 324 /** @defgroup QSPI_DataMode QSPI Data Mode
AnnaBridge 145:64910690c574 325 * @{
AnnaBridge 145:64910690c574 326 */
AnnaBridge 161:aa5281ff4a02 327 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
AnnaBridge 145:64910690c574 328 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
AnnaBridge 145:64910690c574 329 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
AnnaBridge 145:64910690c574 330 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
AnnaBridge 145:64910690c574 331 /**
AnnaBridge 145:64910690c574 332 * @}
AnnaBridge 145:64910690c574 333 */
AnnaBridge 145:64910690c574 334
AnnaBridge 145:64910690c574 335 /** @defgroup QSPI_DdrMode QSPI DDR Mode
AnnaBridge 145:64910690c574 336 * @{
AnnaBridge 145:64910690c574 337 */
AnnaBridge 145:64910690c574 338 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
AnnaBridge 145:64910690c574 339 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
AnnaBridge 145:64910690c574 340 /**
AnnaBridge 145:64910690c574 341 * @}
AnnaBridge 145:64910690c574 342 */
AnnaBridge 145:64910690c574 343
AnnaBridge 145:64910690c574 344 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
AnnaBridge 145:64910690c574 345 * @{
AnnaBridge 145:64910690c574 346 */
AnnaBridge 145:64910690c574 347 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
AnnaBridge 161:aa5281ff4a02 348 #if defined(QUADSPI_CCR_DHHC)
AnnaBridge 145:64910690c574 349 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
AnnaBridge 145:64910690c574 350 #endif
AnnaBridge 145:64910690c574 351 /**
AnnaBridge 145:64910690c574 352 * @}
AnnaBridge 145:64910690c574 353 */
AnnaBridge 145:64910690c574 354
AnnaBridge 145:64910690c574 355 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
AnnaBridge 145:64910690c574 356 * @{
AnnaBridge 145:64910690c574 357 */
AnnaBridge 145:64910690c574 358 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
AnnaBridge 145:64910690c574 359 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
AnnaBridge 145:64910690c574 360 /**
AnnaBridge 145:64910690c574 361 * @}
AnnaBridge 145:64910690c574 362 */
AnnaBridge 145:64910690c574 363
AnnaBridge 145:64910690c574 364 /** @defgroup QSPI_MatchMode QSPI Match Mode
AnnaBridge 145:64910690c574 365 * @{
AnnaBridge 145:64910690c574 366 */
AnnaBridge 145:64910690c574 367 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
AnnaBridge 145:64910690c574 368 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
AnnaBridge 145:64910690c574 369 /**
AnnaBridge 145:64910690c574 370 * @}
AnnaBridge 145:64910690c574 371 */
AnnaBridge 145:64910690c574 372
AnnaBridge 145:64910690c574 373 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
AnnaBridge 145:64910690c574 374 * @{
AnnaBridge 145:64910690c574 375 */
AnnaBridge 145:64910690c574 376 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
AnnaBridge 145:64910690c574 377 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
AnnaBridge 145:64910690c574 378 /**
AnnaBridge 145:64910690c574 379 * @}
AnnaBridge 145:64910690c574 380 */
AnnaBridge 145:64910690c574 381
AnnaBridge 145:64910690c574 382 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
AnnaBridge 145:64910690c574 383 * @{
AnnaBridge 145:64910690c574 384 */
AnnaBridge 145:64910690c574 385 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
AnnaBridge 145:64910690c574 386 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
AnnaBridge 145:64910690c574 387 /**
AnnaBridge 145:64910690c574 388 * @}
AnnaBridge 145:64910690c574 389 */
AnnaBridge 145:64910690c574 390
AnnaBridge 145:64910690c574 391 /** @defgroup QSPI_Flags QSPI Flags
AnnaBridge 145:64910690c574 392 * @{
AnnaBridge 145:64910690c574 393 */
AnnaBridge 145:64910690c574 394 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
AnnaBridge 145:64910690c574 395 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
AnnaBridge 145:64910690c574 396 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
AnnaBridge 145:64910690c574 397 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
AnnaBridge 145:64910690c574 398 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
AnnaBridge 145:64910690c574 399 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
AnnaBridge 145:64910690c574 400 /**
AnnaBridge 145:64910690c574 401 * @}
AnnaBridge 145:64910690c574 402 */
AnnaBridge 145:64910690c574 403
AnnaBridge 145:64910690c574 404 /** @defgroup QSPI_Interrupts QSPI Interrupts
AnnaBridge 145:64910690c574 405 * @{
AnnaBridge 145:64910690c574 406 */
AnnaBridge 145:64910690c574 407 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
AnnaBridge 145:64910690c574 408 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
AnnaBridge 145:64910690c574 409 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
AnnaBridge 145:64910690c574 410 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
AnnaBridge 145:64910690c574 411 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
AnnaBridge 145:64910690c574 412 /**
AnnaBridge 145:64910690c574 413 * @}
AnnaBridge 145:64910690c574 414 */
AnnaBridge 145:64910690c574 415
AnnaBridge 145:64910690c574 416 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
AnnaBridge 145:64910690c574 417 * @brief QSPI Timeout definition
AnnaBridge 145:64910690c574 418 * @{
AnnaBridge 145:64910690c574 419 */
AnnaBridge 145:64910690c574 420 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
AnnaBridge 145:64910690c574 421 /**
AnnaBridge 145:64910690c574 422 * @}
AnnaBridge 145:64910690c574 423 */
AnnaBridge 145:64910690c574 424
AnnaBridge 145:64910690c574 425 /**
AnnaBridge 145:64910690c574 426 * @}
AnnaBridge 145:64910690c574 427 */
AnnaBridge 145:64910690c574 428
AnnaBridge 145:64910690c574 429 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 145:64910690c574 430 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
AnnaBridge 145:64910690c574 431 * @{
AnnaBridge 145:64910690c574 432 */
AnnaBridge 145:64910690c574 433 /** @brief Reset QSPI handle state.
AnnaBridge 161:aa5281ff4a02 434 * @param __HANDLE__ : QSPI handle.
AnnaBridge 145:64910690c574 435 * @retval None
AnnaBridge 145:64910690c574 436 */
AnnaBridge 145:64910690c574 437 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
AnnaBridge 145:64910690c574 438
AnnaBridge 145:64910690c574 439 /** @brief Enable the QSPI peripheral.
AnnaBridge 161:aa5281ff4a02 440 * @param __HANDLE__ : specifies the QSPI Handle.
AnnaBridge 145:64910690c574 441 * @retval None
AnnaBridge 145:64910690c574 442 */
AnnaBridge 145:64910690c574 443 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 145:64910690c574 444
AnnaBridge 145:64910690c574 445 /** @brief Disable the QSPI peripheral.
AnnaBridge 161:aa5281ff4a02 446 * @param __HANDLE__ : specifies the QSPI Handle.
AnnaBridge 145:64910690c574 447 * @retval None
AnnaBridge 145:64910690c574 448 */
AnnaBridge 145:64910690c574 449 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 145:64910690c574 450
AnnaBridge 145:64910690c574 451 /** @brief Enable the specified QSPI interrupt.
AnnaBridge 145:64910690c574 452 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 453 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
AnnaBridge 145:64910690c574 454 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 455 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 145:64910690c574 456 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 145:64910690c574 457 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 145:64910690c574 458 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 145:64910690c574 459 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 145:64910690c574 460 * @retval None
AnnaBridge 145:64910690c574 461 */
AnnaBridge 145:64910690c574 462 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 145:64910690c574 463
AnnaBridge 145:64910690c574 464
AnnaBridge 145:64910690c574 465 /** @brief Disable the specified QSPI interrupt.
AnnaBridge 145:64910690c574 466 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 467 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
AnnaBridge 145:64910690c574 468 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 469 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 145:64910690c574 470 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 145:64910690c574 471 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 145:64910690c574 472 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 145:64910690c574 473 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 145:64910690c574 474 * @retval None
AnnaBridge 145:64910690c574 475 */
AnnaBridge 145:64910690c574 476 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 145:64910690c574 477
AnnaBridge 145:64910690c574 478 /** @brief Check whether the specified QSPI interrupt source is enabled or not.
AnnaBridge 145:64910690c574 479 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 480 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
AnnaBridge 145:64910690c574 481 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 482 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 145:64910690c574 483 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 145:64910690c574 484 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 145:64910690c574 485 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 145:64910690c574 486 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 145:64910690c574 487 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 145:64910690c574 488 */
AnnaBridge 145:64910690c574 489 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 145:64910690c574 490
AnnaBridge 145:64910690c574 491 /**
AnnaBridge 145:64910690c574 492 * @brief Check whether the selected QSPI flag is set or not.
AnnaBridge 145:64910690c574 493 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 494 * @param __FLAG__: specifies the QSPI flag to check.
AnnaBridge 145:64910690c574 495 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 496 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
AnnaBridge 145:64910690c574 497 * @arg QSPI_FLAG_TO: QSPI Timeout flag
AnnaBridge 145:64910690c574 498 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 145:64910690c574 499 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
AnnaBridge 145:64910690c574 500 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 145:64910690c574 501 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 145:64910690c574 502 * @retval None
AnnaBridge 145:64910690c574 503 */
AnnaBridge 161:aa5281ff4a02 504 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) ? SET : RESET)
AnnaBridge 145:64910690c574 505
AnnaBridge 145:64910690c574 506 /** @brief Clears the specified QSPI's flag status.
AnnaBridge 145:64910690c574 507 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 508 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
AnnaBridge 145:64910690c574 509 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 510 * @arg QSPI_FLAG_TO: QSPI Timeout flag
AnnaBridge 145:64910690c574 511 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 145:64910690c574 512 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 145:64910690c574 513 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 145:64910690c574 514 * @retval None
AnnaBridge 145:64910690c574 515 */
AnnaBridge 145:64910690c574 516 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
AnnaBridge 145:64910690c574 517 /**
AnnaBridge 145:64910690c574 518 * @}
AnnaBridge 145:64910690c574 519 */
AnnaBridge 145:64910690c574 520
AnnaBridge 145:64910690c574 521 /* Exported functions --------------------------------------------------------*/
AnnaBridge 145:64910690c574 522 /** @addtogroup QSPI_Exported_Functions
AnnaBridge 145:64910690c574 523 * @{
AnnaBridge 145:64910690c574 524 */
AnnaBridge 145:64910690c574 525 /* Initialization/de-initialization functions ********************************/
AnnaBridge 145:64910690c574 526 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 527 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 528 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 529 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 530
AnnaBridge 145:64910690c574 531 /* IO operation functions *****************************************************/
AnnaBridge 145:64910690c574 532 /* QSPI IRQ handler method */
AnnaBridge 145:64910690c574 533 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 534
AnnaBridge 145:64910690c574 535 /* QSPI indirect mode */
AnnaBridge 145:64910690c574 536 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
AnnaBridge 145:64910690c574 537 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 145:64910690c574 538 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 145:64910690c574 539 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
AnnaBridge 145:64910690c574 540 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 541 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 542 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 543 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 544
AnnaBridge 145:64910690c574 545 /* QSPI status flag polling mode */
AnnaBridge 145:64910690c574 546 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
AnnaBridge 145:64910690c574 547 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
AnnaBridge 145:64910690c574 548
AnnaBridge 145:64910690c574 549 /* QSPI memory-mapped mode */
AnnaBridge 145:64910690c574 550 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
AnnaBridge 145:64910690c574 551
AnnaBridge 145:64910690c574 552 /* Callback functions in non-blocking modes ***********************************/
AnnaBridge 145:64910690c574 553 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 554 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 555 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 556
AnnaBridge 145:64910690c574 557 /* QSPI indirect mode */
AnnaBridge 145:64910690c574 558 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 559 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 560 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 561 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 562 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 563
AnnaBridge 145:64910690c574 564 /* QSPI status flag polling mode */
AnnaBridge 145:64910690c574 565 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 566
AnnaBridge 145:64910690c574 567 /* QSPI memory-mapped mode */
AnnaBridge 145:64910690c574 568 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 569
AnnaBridge 145:64910690c574 570 /* Peripheral Control and State functions ************************************/
AnnaBridge 145:64910690c574 571 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 572 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 573 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 574 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 575 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
AnnaBridge 145:64910690c574 576 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
AnnaBridge 145:64910690c574 577 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 578 /**
AnnaBridge 145:64910690c574 579 * @}
AnnaBridge 145:64910690c574 580 */
AnnaBridge 145:64910690c574 581 /* End of exported functions -------------------------------------------------*/
AnnaBridge 145:64910690c574 582
AnnaBridge 145:64910690c574 583 /* Private macros ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 584 /** @defgroup QSPI_Private_Macros QSPI Private Macros
AnnaBridge 145:64910690c574 585 * @{
AnnaBridge 145:64910690c574 586 */
AnnaBridge 145:64910690c574 587 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
AnnaBridge 145:64910690c574 588
AnnaBridge 145:64910690c574 589 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
AnnaBridge 145:64910690c574 590
AnnaBridge 145:64910690c574 591 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
AnnaBridge 145:64910690c574 592 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
AnnaBridge 145:64910690c574 593
AnnaBridge 145:64910690c574 594 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
AnnaBridge 145:64910690c574 595
AnnaBridge 145:64910690c574 596 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
AnnaBridge 145:64910690c574 597 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
AnnaBridge 145:64910690c574 598 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
AnnaBridge 145:64910690c574 599 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
AnnaBridge 145:64910690c574 600 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
AnnaBridge 145:64910690c574 601 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
AnnaBridge 145:64910690c574 602 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
AnnaBridge 145:64910690c574 603 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
AnnaBridge 145:64910690c574 604
AnnaBridge 145:64910690c574 605 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
AnnaBridge 145:64910690c574 606 ((CLKMODE) == QSPI_CLOCK_MODE_3))
AnnaBridge 145:64910690c574 607
AnnaBridge 161:aa5281ff4a02 608 #if defined(QUADSPI_CR_DFM)
AnnaBridge 145:64910690c574 609 #define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \
AnnaBridge 145:64910690c574 610 ((FLASH) == QSPI_FLASH_ID_2))
AnnaBridge 145:64910690c574 611
AnnaBridge 145:64910690c574 612 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
AnnaBridge 145:64910690c574 613 ((MODE) == QSPI_DUALFLASH_DISABLE))
AnnaBridge 145:64910690c574 614 #endif
AnnaBridge 145:64910690c574 615
AnnaBridge 145:64910690c574 616 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
AnnaBridge 145:64910690c574 617
AnnaBridge 145:64910690c574 618 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
AnnaBridge 145:64910690c574 619 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
AnnaBridge 145:64910690c574 620 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
AnnaBridge 145:64910690c574 621 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
AnnaBridge 145:64910690c574 622
AnnaBridge 145:64910690c574 623 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
AnnaBridge 145:64910690c574 624 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
AnnaBridge 145:64910690c574 625 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
AnnaBridge 145:64910690c574 626 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
AnnaBridge 145:64910690c574 627
AnnaBridge 145:64910690c574 628 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
AnnaBridge 145:64910690c574 629
AnnaBridge 145:64910690c574 630 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
AnnaBridge 145:64910690c574 631 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
AnnaBridge 145:64910690c574 632 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
AnnaBridge 145:64910690c574 633 ((MODE) == QSPI_INSTRUCTION_4_LINES))
AnnaBridge 145:64910690c574 634
AnnaBridge 145:64910690c574 635 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
AnnaBridge 145:64910690c574 636 ((MODE) == QSPI_ADDRESS_1_LINE) || \
AnnaBridge 145:64910690c574 637 ((MODE) == QSPI_ADDRESS_2_LINES) || \
AnnaBridge 145:64910690c574 638 ((MODE) == QSPI_ADDRESS_4_LINES))
AnnaBridge 145:64910690c574 639
AnnaBridge 145:64910690c574 640 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
AnnaBridge 145:64910690c574 641 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
AnnaBridge 145:64910690c574 642 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
AnnaBridge 145:64910690c574 643 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
AnnaBridge 145:64910690c574 644
AnnaBridge 145:64910690c574 645 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
AnnaBridge 145:64910690c574 646 ((MODE) == QSPI_DATA_1_LINE) || \
AnnaBridge 145:64910690c574 647 ((MODE) == QSPI_DATA_2_LINES) || \
AnnaBridge 145:64910690c574 648 ((MODE) == QSPI_DATA_4_LINES))
AnnaBridge 145:64910690c574 649
AnnaBridge 145:64910690c574 650 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
AnnaBridge 145:64910690c574 651 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
AnnaBridge 145:64910690c574 652
AnnaBridge 161:aa5281ff4a02 653 #if defined(QUADSPI_CCR_DHHC)
AnnaBridge 145:64910690c574 654 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
AnnaBridge 145:64910690c574 655 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
AnnaBridge 145:64910690c574 656 #else
AnnaBridge 145:64910690c574 657 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
AnnaBridge 145:64910690c574 658 #endif
AnnaBridge 145:64910690c574 659
AnnaBridge 145:64910690c574 660 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
AnnaBridge 145:64910690c574 661 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
AnnaBridge 145:64910690c574 662
AnnaBridge 145:64910690c574 663 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
AnnaBridge 145:64910690c574 664
AnnaBridge 145:64910690c574 665 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
AnnaBridge 145:64910690c574 666
AnnaBridge 145:64910690c574 667 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
AnnaBridge 145:64910690c574 668 ((MODE) == QSPI_MATCH_MODE_OR))
AnnaBridge 145:64910690c574 669
AnnaBridge 145:64910690c574 670 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
AnnaBridge 145:64910690c574 671 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
AnnaBridge 145:64910690c574 672
AnnaBridge 145:64910690c574 673 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
AnnaBridge 145:64910690c574 674 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
AnnaBridge 145:64910690c574 675
AnnaBridge 145:64910690c574 676 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
AnnaBridge 145:64910690c574 677 /**
AnnaBridge 145:64910690c574 678 * @}
AnnaBridge 145:64910690c574 679 */
AnnaBridge 145:64910690c574 680 /* End of private macros -----------------------------------------------------*/
AnnaBridge 145:64910690c574 681
AnnaBridge 145:64910690c574 682 /**
AnnaBridge 145:64910690c574 683 * @}
AnnaBridge 145:64910690c574 684 */
AnnaBridge 145:64910690c574 685
AnnaBridge 145:64910690c574 686 /**
AnnaBridge 145:64910690c574 687 * @}
AnnaBridge 145:64910690c574 688 */
AnnaBridge 161:aa5281ff4a02 689
AnnaBridge 161:aa5281ff4a02 690 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */
AnnaBridge 161:aa5281ff4a02 691
AnnaBridge 145:64910690c574 692 #ifdef __cplusplus
AnnaBridge 145:64910690c574 693 }
AnnaBridge 145:64910690c574 694 #endif
AnnaBridge 145:64910690c574 695
AnnaBridge 145:64910690c574 696 #endif /* __STM32L4xx_HAL_QSPI_H */
AnnaBridge 145:64910690c574 697
AnnaBridge 145:64910690c574 698 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/