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TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_qspi.h@145:64910690c574, 2017-06-21 (annotated)

Committer:
AnnaBridge
Date:
Wed Jun 21 17:31:38 2017 +0100
Revision:
145:64910690c574
Child:
161:aa5281ff4a02
Release 145 of the mbed library.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 145:64910690c574 1 /**
AnnaBridge 145:64910690c574 2 ******************************************************************************
AnnaBridge 145:64910690c574 3 * @file stm32l4xx_hal_qspi.h
AnnaBridge 145:64910690c574 4 * @author MCD Application Team
AnnaBridge 145:64910690c574 5 * @version V1.7.1
AnnaBridge 145:64910690c574 6 * @date 21-April-2017
AnnaBridge 145:64910690c574 7 * @brief Header file of QSPI HAL module.
AnnaBridge 145:64910690c574 8 ******************************************************************************
AnnaBridge 145:64910690c574 9 * @attention
AnnaBridge 145:64910690c574 10 *
AnnaBridge 145:64910690c574 11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge 145:64910690c574 12 *
AnnaBridge 145:64910690c574 13 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 145:64910690c574 14 * are permitted provided that the following conditions are met:
AnnaBridge 145:64910690c574 15 * 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge 145:64910690c574 16 * this list of conditions and the following disclaimer.
AnnaBridge 145:64910690c574 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge 145:64910690c574 18 * this list of conditions and the following disclaimer in the documentation
AnnaBridge 145:64910690c574 19 * and/or other materials provided with the distribution.
AnnaBridge 145:64910690c574 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge 145:64910690c574 21 * may be used to endorse or promote products derived from this software
AnnaBridge 145:64910690c574 22 * without specific prior written permission.
AnnaBridge 145:64910690c574 23 *
AnnaBridge 145:64910690c574 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge 145:64910690c574 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge 145:64910690c574 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 145:64910690c574 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge 145:64910690c574 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge 145:64910690c574 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge 145:64910690c574 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge 145:64910690c574 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge 145:64910690c574 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge 145:64910690c574 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 145:64910690c574 34 *
AnnaBridge 145:64910690c574 35 ******************************************************************************
AnnaBridge 145:64910690c574 36 */
AnnaBridge 145:64910690c574 37
AnnaBridge 145:64910690c574 38 /* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge 145:64910690c574 39 #ifndef __STM32L4xx_HAL_QSPI_H
AnnaBridge 145:64910690c574 40 #define __STM32L4xx_HAL_QSPI_H
AnnaBridge 145:64910690c574 41
AnnaBridge 145:64910690c574 42 #ifdef __cplusplus
AnnaBridge 145:64910690c574 43 extern "C" {
AnnaBridge 145:64910690c574 44 #endif
AnnaBridge 145:64910690c574 45
AnnaBridge 145:64910690c574 46 /* Includes ------------------------------------------------------------------*/
AnnaBridge 145:64910690c574 47 #include "stm32l4xx_hal_def.h"
AnnaBridge 145:64910690c574 48
AnnaBridge 145:64910690c574 49 /** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge 145:64910690c574 50 * @{
AnnaBridge 145:64910690c574 51 */
AnnaBridge 145:64910690c574 52
AnnaBridge 145:64910690c574 53 /** @addtogroup QSPI
AnnaBridge 145:64910690c574 54 * @{
AnnaBridge 145:64910690c574 55 */
AnnaBridge 145:64910690c574 56
AnnaBridge 145:64910690c574 57 /* Exported types ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 58 /** @defgroup QSPI_Exported_Types QSPI Exported Types
AnnaBridge 145:64910690c574 59 * @{
AnnaBridge 145:64910690c574 60 */
AnnaBridge 145:64910690c574 61
AnnaBridge 145:64910690c574 62 /**
AnnaBridge 145:64910690c574 63 * @brief QSPI Init structure definition
AnnaBridge 145:64910690c574 64 */
AnnaBridge 145:64910690c574 65 typedef struct
AnnaBridge 145:64910690c574 66 {
AnnaBridge 145:64910690c574 67 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock.
AnnaBridge 145:64910690c574 68 This parameter can be a number between 0 and 255 */
AnnaBridge 145:64910690c574 69 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)
AnnaBridge 145:64910690c574 70 This parameter can be a value between 1 and 16 */
AnnaBridge 145:64910690c574 71 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to
AnnaBridge 145:64910690c574 72 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)
AnnaBridge 145:64910690c574 73 This parameter can be a value of @ref QSPI_SampleShifting */
AnnaBridge 145:64910690c574 74 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits
AnnaBridge 145:64910690c574 75 required to address the flash memory. The flash capacity can be up to 4GB
AnnaBridge 145:64910690c574 76 (addressed using 32 bits) in indirect mode, but the addressable space in
AnnaBridge 145:64910690c574 77 memory-mapped mode is limited to 256MB
AnnaBridge 145:64910690c574 78 This parameter can be a number between 0 and 31 */
AnnaBridge 145:64910690c574 79 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number
AnnaBridge 145:64910690c574 80 of clock cycles which the chip select must remain high between commands.
AnnaBridge 145:64910690c574 81 This parameter can be a value of @ref QSPI_ChipSelectHighTime */
AnnaBridge 145:64910690c574 82 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands.
AnnaBridge 145:64910690c574 83 This parameter can be a value of @ref QSPI_ClockMode */
AnnaBridge 145:64910690c574 84 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
AnnaBridge 145:64910690c574 85 defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 145:64910690c574 86 defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 145:64910690c574 87 uint32_t FlashID; /* Specifies the Flash which will be used,
AnnaBridge 145:64910690c574 88 This parameter can be a value of @ref QSPI_Flash_Select */
AnnaBridge 145:64910690c574 89 uint32_t DualFlash; /* Specifies the Dual Flash Mode State
AnnaBridge 145:64910690c574 90 This parameter can be a value of @ref QSPI_DualFlash_Mode */
AnnaBridge 145:64910690c574 91 #endif
AnnaBridge 145:64910690c574 92 }QSPI_InitTypeDef;
AnnaBridge 145:64910690c574 93
AnnaBridge 145:64910690c574 94 /**
AnnaBridge 145:64910690c574 95 * @brief HAL QSPI State structures definition
AnnaBridge 145:64910690c574 96 */
AnnaBridge 145:64910690c574 97 typedef enum
AnnaBridge 145:64910690c574 98 {
AnnaBridge 145:64910690c574 99 HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
AnnaBridge 145:64910690c574 100 HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
AnnaBridge 145:64910690c574 101 HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
AnnaBridge 145:64910690c574 102 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
AnnaBridge 145:64910690c574 103 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
AnnaBridge 145:64910690c574 104 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
AnnaBridge 145:64910690c574 105 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
AnnaBridge 145:64910690c574 106 HAL_QSPI_STATE_ABORT = 0x08, /*!< Peripheral with abort request ongoing */
AnnaBridge 145:64910690c574 107 HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
AnnaBridge 145:64910690c574 108 }HAL_QSPI_StateTypeDef;
AnnaBridge 145:64910690c574 109
AnnaBridge 145:64910690c574 110 /**
AnnaBridge 145:64910690c574 111 * @brief QSPI Handle Structure definition
AnnaBridge 145:64910690c574 112 */
AnnaBridge 145:64910690c574 113 typedef struct
AnnaBridge 145:64910690c574 114 {
AnnaBridge 145:64910690c574 115 QUADSPI_TypeDef *Instance; /* QSPI registers base address */
AnnaBridge 145:64910690c574 116 QSPI_InitTypeDef Init; /* QSPI communication parameters */
AnnaBridge 145:64910690c574 117 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */
AnnaBridge 145:64910690c574 118 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */
AnnaBridge 145:64910690c574 119 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */
AnnaBridge 145:64910690c574 120 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */
AnnaBridge 145:64910690c574 121 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */
AnnaBridge 145:64910690c574 122 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */
AnnaBridge 145:64910690c574 123 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */
AnnaBridge 145:64910690c574 124 __IO HAL_LockTypeDef Lock; /* Locking object */
AnnaBridge 145:64910690c574 125 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */
AnnaBridge 145:64910690c574 126 __IO uint32_t ErrorCode; /* QSPI Error code */
AnnaBridge 145:64910690c574 127 uint32_t Timeout; /* Timeout for the QSPI memory access */
AnnaBridge 145:64910690c574 128 }QSPI_HandleTypeDef;
AnnaBridge 145:64910690c574 129
AnnaBridge 145:64910690c574 130 /**
AnnaBridge 145:64910690c574 131 * @brief QSPI Command structure definition
AnnaBridge 145:64910690c574 132 */
AnnaBridge 145:64910690c574 133 typedef struct
AnnaBridge 145:64910690c574 134 {
AnnaBridge 145:64910690c574 135 uint32_t Instruction; /* Specifies the Instruction to be sent
AnnaBridge 145:64910690c574 136 This parameter can be a value (8-bit) between 0x00 and 0xFF */
AnnaBridge 145:64910690c574 137 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)
AnnaBridge 145:64910690c574 138 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 139 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)
AnnaBridge 145:64910690c574 140 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 141 uint32_t AddressSize; /* Specifies the Address Size
AnnaBridge 145:64910690c574 142 This parameter can be a value of @ref QSPI_AddressSize */
AnnaBridge 145:64910690c574 143 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size
AnnaBridge 145:64910690c574 144 This parameter can be a value of @ref QSPI_AlternateBytesSize */
AnnaBridge 145:64910690c574 145 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles.
AnnaBridge 145:64910690c574 146 This parameter can be a number between 0 and 31 */
AnnaBridge 145:64910690c574 147 uint32_t InstructionMode; /* Specifies the Instruction Mode
AnnaBridge 145:64910690c574 148 This parameter can be a value of @ref QSPI_InstructionMode */
AnnaBridge 145:64910690c574 149 uint32_t AddressMode; /* Specifies the Address Mode
AnnaBridge 145:64910690c574 150 This parameter can be a value of @ref QSPI_AddressMode */
AnnaBridge 145:64910690c574 151 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode
AnnaBridge 145:64910690c574 152 This parameter can be a value of @ref QSPI_AlternateBytesMode */
AnnaBridge 145:64910690c574 153 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases)
AnnaBridge 145:64910690c574 154 This parameter can be a value of @ref QSPI_DataMode */
AnnaBridge 145:64910690c574 155 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes)
AnnaBridge 145:64910690c574 156 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length
AnnaBridge 145:64910690c574 157 until end of memory)*/
AnnaBridge 145:64910690c574 158 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase
AnnaBridge 145:64910690c574 159 This parameter can be a value of @ref QSPI_DdrMode */
AnnaBridge 145:64910690c574 160 uint32_t DdrHoldHalfCycle; /* Specifies the DDR hold half cycle. It delays the data output by one half of
AnnaBridge 145:64910690c574 161 system clock in DDR mode. Not available on STM32L4x6 devices but in future devices.
AnnaBridge 145:64910690c574 162 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */
AnnaBridge 145:64910690c574 163 uint32_t SIOOMode; /* Specifies the send instruction only once mode
AnnaBridge 145:64910690c574 164 This parameter can be a value of @ref QSPI_SIOOMode */
AnnaBridge 145:64910690c574 165 }QSPI_CommandTypeDef;
AnnaBridge 145:64910690c574 166
AnnaBridge 145:64910690c574 167 /**
AnnaBridge 145:64910690c574 168 * @brief QSPI Auto Polling mode configuration structure definition
AnnaBridge 145:64910690c574 169 */
AnnaBridge 145:64910690c574 170 typedef struct
AnnaBridge 145:64910690c574 171 {
AnnaBridge 145:64910690c574 172 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match.
AnnaBridge 145:64910690c574 173 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 174 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received.
AnnaBridge 145:64910690c574 175 This parameter can be any value between 0 and 0xFFFFFFFF */
AnnaBridge 145:64910690c574 176 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases.
AnnaBridge 145:64910690c574 177 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 145:64910690c574 178 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received.
AnnaBridge 145:64910690c574 179 This parameter can be any value between 1 and 4 */
AnnaBridge 145:64910690c574 180 uint32_t MatchMode; /* Specifies the method used for determining a match.
AnnaBridge 145:64910690c574 181 This parameter can be a value of @ref QSPI_MatchMode */
AnnaBridge 145:64910690c574 182 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match.
AnnaBridge 145:64910690c574 183 This parameter can be a value of @ref QSPI_AutomaticStop */
AnnaBridge 145:64910690c574 184 }QSPI_AutoPollingTypeDef;
AnnaBridge 145:64910690c574 185
AnnaBridge 145:64910690c574 186 /**
AnnaBridge 145:64910690c574 187 * @brief QSPI Memory Mapped mode configuration structure definition
AnnaBridge 145:64910690c574 188 */
AnnaBridge 145:64910690c574 189 typedef struct
AnnaBridge 145:64910690c574 190 {
AnnaBridge 145:64910690c574 191 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.
AnnaBridge 145:64910690c574 192 This parameter can be any value between 0 and 0xFFFF */
AnnaBridge 145:64910690c574 193 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select.
AnnaBridge 145:64910690c574 194 This parameter can be a value of @ref QSPI_TimeOutActivation */
AnnaBridge 145:64910690c574 195 }QSPI_MemoryMappedTypeDef;
AnnaBridge 145:64910690c574 196
AnnaBridge 145:64910690c574 197 /**
AnnaBridge 145:64910690c574 198 * @}
AnnaBridge 145:64910690c574 199 */
AnnaBridge 145:64910690c574 200
AnnaBridge 145:64910690c574 201 /* Exported constants --------------------------------------------------------*/
AnnaBridge 145:64910690c574 202 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants
AnnaBridge 145:64910690c574 203 * @{
AnnaBridge 145:64910690c574 204 */
AnnaBridge 145:64910690c574 205
AnnaBridge 145:64910690c574 206 /** @defgroup QSPI_ErrorCode QSPI Error Code
AnnaBridge 145:64910690c574 207 * @{
AnnaBridge 145:64910690c574 208 */
AnnaBridge 145:64910690c574 209 #define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
AnnaBridge 145:64910690c574 210 #define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
AnnaBridge 145:64910690c574 211 #define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
AnnaBridge 145:64910690c574 212 #define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
AnnaBridge 145:64910690c574 213 #define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008) /*!< Invalid parameters error */
AnnaBridge 145:64910690c574 214 /**
AnnaBridge 145:64910690c574 215 * @}
AnnaBridge 145:64910690c574 216 */
AnnaBridge 145:64910690c574 217
AnnaBridge 145:64910690c574 218 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting
AnnaBridge 145:64910690c574 219 * @{
AnnaBridge 145:64910690c574 220 */
AnnaBridge 145:64910690c574 221 #define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
AnnaBridge 145:64910690c574 222 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
AnnaBridge 145:64910690c574 223 /**
AnnaBridge 145:64910690c574 224 * @}
AnnaBridge 145:64910690c574 225 */
AnnaBridge 145:64910690c574 226
AnnaBridge 145:64910690c574 227 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time
AnnaBridge 145:64910690c574 228 * @{
AnnaBridge 145:64910690c574 229 */
AnnaBridge 145:64910690c574 230 #define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
AnnaBridge 145:64910690c574 231 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
AnnaBridge 145:64910690c574 232 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
AnnaBridge 145:64910690c574 233 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
AnnaBridge 145:64910690c574 234 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/
AnnaBridge 145:64910690c574 235 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/
AnnaBridge 145:64910690c574 236 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/
AnnaBridge 145:64910690c574 237 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/
AnnaBridge 145:64910690c574 238 /**
AnnaBridge 145:64910690c574 239 * @}
AnnaBridge 145:64910690c574 240 */
AnnaBridge 145:64910690c574 241
AnnaBridge 145:64910690c574 242 /** @defgroup QSPI_ClockMode QSPI Clock Mode
AnnaBridge 145:64910690c574 243 * @{
AnnaBridge 145:64910690c574 244 */
AnnaBridge 145:64910690c574 245 #define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
AnnaBridge 145:64910690c574 246 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
AnnaBridge 145:64910690c574 247 /**
AnnaBridge 145:64910690c574 248 * @}
AnnaBridge 145:64910690c574 249 */
AnnaBridge 145:64910690c574 250
AnnaBridge 145:64910690c574 251 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
AnnaBridge 145:64910690c574 252 defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 145:64910690c574 253 defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 145:64910690c574 254 /** @defgroup QSPI_Flash_Select QSPI Flash Select
AnnaBridge 145:64910690c574 255 * @{
AnnaBridge 145:64910690c574 256 */
AnnaBridge 145:64910690c574 257 #define QSPI_FLASH_ID_1 ((uint32_t)0x00000000) /*!<FLASH 1 selected*/
AnnaBridge 145:64910690c574 258 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/
AnnaBridge 145:64910690c574 259 /**
AnnaBridge 145:64910690c574 260 * @}
AnnaBridge 145:64910690c574 261 */
AnnaBridge 145:64910690c574 262
AnnaBridge 145:64910690c574 263 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode
AnnaBridge 145:64910690c574 264 * @{
AnnaBridge 145:64910690c574 265 */
AnnaBridge 145:64910690c574 266 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/
AnnaBridge 145:64910690c574 267 #define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000) /*!<Dual-flash mode disabled*/
AnnaBridge 145:64910690c574 268 /**
AnnaBridge 145:64910690c574 269 * @}
AnnaBridge 145:64910690c574 270 */
AnnaBridge 145:64910690c574 271 #endif
AnnaBridge 145:64910690c574 272
AnnaBridge 145:64910690c574 273 /** @defgroup QSPI_AddressSize QSPI Address Size
AnnaBridge 145:64910690c574 274 * @{
AnnaBridge 145:64910690c574 275 */
AnnaBridge 145:64910690c574 276 #define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
AnnaBridge 145:64910690c574 277 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
AnnaBridge 145:64910690c574 278 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
AnnaBridge 145:64910690c574 279 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
AnnaBridge 145:64910690c574 280 /**
AnnaBridge 145:64910690c574 281 * @}
AnnaBridge 145:64910690c574 282 */
AnnaBridge 145:64910690c574 283
AnnaBridge 145:64910690c574 284 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
AnnaBridge 145:64910690c574 285 * @{
AnnaBridge 145:64910690c574 286 */
AnnaBridge 145:64910690c574 287 #define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
AnnaBridge 145:64910690c574 288 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
AnnaBridge 145:64910690c574 289 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
AnnaBridge 145:64910690c574 290 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
AnnaBridge 145:64910690c574 291 /**
AnnaBridge 145:64910690c574 292 * @}
AnnaBridge 145:64910690c574 293 */
AnnaBridge 145:64910690c574 294
AnnaBridge 145:64910690c574 295 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode
AnnaBridge 145:64910690c574 296 * @{
AnnaBridge 145:64910690c574 297 */
AnnaBridge 145:64910690c574 298 #define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
AnnaBridge 145:64910690c574 299 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
AnnaBridge 145:64910690c574 300 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
AnnaBridge 145:64910690c574 301 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
AnnaBridge 145:64910690c574 302 /**
AnnaBridge 145:64910690c574 303 * @}
AnnaBridge 145:64910690c574 304 */
AnnaBridge 145:64910690c574 305
AnnaBridge 145:64910690c574 306 /** @defgroup QSPI_AddressMode QSPI Address Mode
AnnaBridge 145:64910690c574 307 * @{
AnnaBridge 145:64910690c574 308 */
AnnaBridge 145:64910690c574 309 #define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
AnnaBridge 145:64910690c574 310 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
AnnaBridge 145:64910690c574 311 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
AnnaBridge 145:64910690c574 312 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
AnnaBridge 145:64910690c574 313 /**
AnnaBridge 145:64910690c574 314 * @}
AnnaBridge 145:64910690c574 315 */
AnnaBridge 145:64910690c574 316
AnnaBridge 145:64910690c574 317 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
AnnaBridge 145:64910690c574 318 * @{
AnnaBridge 145:64910690c574 319 */
AnnaBridge 145:64910690c574 320 #define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
AnnaBridge 145:64910690c574 321 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
AnnaBridge 145:64910690c574 322 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
AnnaBridge 145:64910690c574 323 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
AnnaBridge 145:64910690c574 324 /**
AnnaBridge 145:64910690c574 325 * @}
AnnaBridge 145:64910690c574 326 */
AnnaBridge 145:64910690c574 327
AnnaBridge 145:64910690c574 328 /** @defgroup QSPI_DataMode QSPI Data Mode
AnnaBridge 145:64910690c574 329 * @{
AnnaBridge 145:64910690c574 330 */
AnnaBridge 145:64910690c574 331 #define QSPI_DATA_NONE ((uint32_t)0X00000000) /*!<No data*/
AnnaBridge 145:64910690c574 332 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/
AnnaBridge 145:64910690c574 333 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/
AnnaBridge 145:64910690c574 334 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/
AnnaBridge 145:64910690c574 335 /**
AnnaBridge 145:64910690c574 336 * @}
AnnaBridge 145:64910690c574 337 */
AnnaBridge 145:64910690c574 338
AnnaBridge 145:64910690c574 339 /** @defgroup QSPI_DdrMode QSPI DDR Mode
AnnaBridge 145:64910690c574 340 * @{
AnnaBridge 145:64910690c574 341 */
AnnaBridge 145:64910690c574 342 #define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
AnnaBridge 145:64910690c574 343 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
AnnaBridge 145:64910690c574 344 /**
AnnaBridge 145:64910690c574 345 * @}
AnnaBridge 145:64910690c574 346 */
AnnaBridge 145:64910690c574 347
AnnaBridge 145:64910690c574 348 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay
AnnaBridge 145:64910690c574 349 * @{
AnnaBridge 145:64910690c574 350 */
AnnaBridge 145:64910690c574 351 #define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
AnnaBridge 145:64910690c574 352 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
AnnaBridge 145:64910690c574 353 defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 145:64910690c574 354 defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 145:64910690c574 355 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
AnnaBridge 145:64910690c574 356 #endif
AnnaBridge 145:64910690c574 357 /**
AnnaBridge 145:64910690c574 358 * @}
AnnaBridge 145:64910690c574 359 */
AnnaBridge 145:64910690c574 360
AnnaBridge 145:64910690c574 361 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode
AnnaBridge 145:64910690c574 362 * @{
AnnaBridge 145:64910690c574 363 */
AnnaBridge 145:64910690c574 364 #define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
AnnaBridge 145:64910690c574 365 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
AnnaBridge 145:64910690c574 366 /**
AnnaBridge 145:64910690c574 367 * @}
AnnaBridge 145:64910690c574 368 */
AnnaBridge 145:64910690c574 369
AnnaBridge 145:64910690c574 370 /** @defgroup QSPI_MatchMode QSPI Match Mode
AnnaBridge 145:64910690c574 371 * @{
AnnaBridge 145:64910690c574 372 */
AnnaBridge 145:64910690c574 373 #define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
AnnaBridge 145:64910690c574 374 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
AnnaBridge 145:64910690c574 375 /**
AnnaBridge 145:64910690c574 376 * @}
AnnaBridge 145:64910690c574 377 */
AnnaBridge 145:64910690c574 378
AnnaBridge 145:64910690c574 379 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
AnnaBridge 145:64910690c574 380 * @{
AnnaBridge 145:64910690c574 381 */
AnnaBridge 145:64910690c574 382 #define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
AnnaBridge 145:64910690c574 383 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
AnnaBridge 145:64910690c574 384 /**
AnnaBridge 145:64910690c574 385 * @}
AnnaBridge 145:64910690c574 386 */
AnnaBridge 145:64910690c574 387
AnnaBridge 145:64910690c574 388 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation
AnnaBridge 145:64910690c574 389 * @{
AnnaBridge 145:64910690c574 390 */
AnnaBridge 145:64910690c574 391 #define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
AnnaBridge 145:64910690c574 392 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
AnnaBridge 145:64910690c574 393 /**
AnnaBridge 145:64910690c574 394 * @}
AnnaBridge 145:64910690c574 395 */
AnnaBridge 145:64910690c574 396
AnnaBridge 145:64910690c574 397 /** @defgroup QSPI_Flags QSPI Flags
AnnaBridge 145:64910690c574 398 * @{
AnnaBridge 145:64910690c574 399 */
AnnaBridge 145:64910690c574 400 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
AnnaBridge 145:64910690c574 401 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
AnnaBridge 145:64910690c574 402 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
AnnaBridge 145:64910690c574 403 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
AnnaBridge 145:64910690c574 404 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
AnnaBridge 145:64910690c574 405 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
AnnaBridge 145:64910690c574 406 /**
AnnaBridge 145:64910690c574 407 * @}
AnnaBridge 145:64910690c574 408 */
AnnaBridge 145:64910690c574 409
AnnaBridge 145:64910690c574 410 /** @defgroup QSPI_Interrupts QSPI Interrupts
AnnaBridge 145:64910690c574 411 * @{
AnnaBridge 145:64910690c574 412 */
AnnaBridge 145:64910690c574 413 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/
AnnaBridge 145:64910690c574 414 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/
AnnaBridge 145:64910690c574 415 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/
AnnaBridge 145:64910690c574 416 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/
AnnaBridge 145:64910690c574 417 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/
AnnaBridge 145:64910690c574 418 /**
AnnaBridge 145:64910690c574 419 * @}
AnnaBridge 145:64910690c574 420 */
AnnaBridge 145:64910690c574 421
AnnaBridge 145:64910690c574 422 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition
AnnaBridge 145:64910690c574 423 * @brief QSPI Timeout definition
AnnaBridge 145:64910690c574 424 * @{
AnnaBridge 145:64910690c574 425 */
AnnaBridge 145:64910690c574 426 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000)/* 5 s */
AnnaBridge 145:64910690c574 427 /**
AnnaBridge 145:64910690c574 428 * @}
AnnaBridge 145:64910690c574 429 */
AnnaBridge 145:64910690c574 430
AnnaBridge 145:64910690c574 431 /**
AnnaBridge 145:64910690c574 432 * @}
AnnaBridge 145:64910690c574 433 */
AnnaBridge 145:64910690c574 434
AnnaBridge 145:64910690c574 435 /* Exported macros -----------------------------------------------------------*/
AnnaBridge 145:64910690c574 436 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros
AnnaBridge 145:64910690c574 437 * @{
AnnaBridge 145:64910690c574 438 */
AnnaBridge 145:64910690c574 439 /** @brief Reset QSPI handle state.
AnnaBridge 145:64910690c574 440 * @param __HANDLE__: QSPI handle.
AnnaBridge 145:64910690c574 441 * @retval None
AnnaBridge 145:64910690c574 442 */
AnnaBridge 145:64910690c574 443 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)
AnnaBridge 145:64910690c574 444
AnnaBridge 145:64910690c574 445 /** @brief Enable the QSPI peripheral.
AnnaBridge 145:64910690c574 446 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 447 * @retval None
AnnaBridge 145:64910690c574 448 */
AnnaBridge 145:64910690c574 449 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 145:64910690c574 450
AnnaBridge 145:64910690c574 451 /** @brief Disable the QSPI peripheral.
AnnaBridge 145:64910690c574 452 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 453 * @retval None
AnnaBridge 145:64910690c574 454 */
AnnaBridge 145:64910690c574 455 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)
AnnaBridge 145:64910690c574 456
AnnaBridge 145:64910690c574 457 /** @brief Enable the specified QSPI interrupt.
AnnaBridge 145:64910690c574 458 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 459 * @param __INTERRUPT__: specifies the QSPI interrupt source to enable.
AnnaBridge 145:64910690c574 460 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 461 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 145:64910690c574 462 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 145:64910690c574 463 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 145:64910690c574 464 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 145:64910690c574 465 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 145:64910690c574 466 * @retval None
AnnaBridge 145:64910690c574 467 */
AnnaBridge 145:64910690c574 468 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 145:64910690c574 469
AnnaBridge 145:64910690c574 470
AnnaBridge 145:64910690c574 471 /** @brief Disable the specified QSPI interrupt.
AnnaBridge 145:64910690c574 472 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 473 * @param __INTERRUPT__: specifies the QSPI interrupt source to disable.
AnnaBridge 145:64910690c574 474 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 475 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 145:64910690c574 476 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 145:64910690c574 477 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 145:64910690c574 478 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 145:64910690c574 479 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 145:64910690c574 480 * @retval None
AnnaBridge 145:64910690c574 481 */
AnnaBridge 145:64910690c574 482 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))
AnnaBridge 145:64910690c574 483
AnnaBridge 145:64910690c574 484 /** @brief Check whether the specified QSPI interrupt source is enabled or not.
AnnaBridge 145:64910690c574 485 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 486 * @param __INTERRUPT__: specifies the QSPI interrupt source to check.
AnnaBridge 145:64910690c574 487 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 488 * @arg QSPI_IT_TO: QSPI Timeout interrupt
AnnaBridge 145:64910690c574 489 * @arg QSPI_IT_SM: QSPI Status match interrupt
AnnaBridge 145:64910690c574 490 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt
AnnaBridge 145:64910690c574 491 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt
AnnaBridge 145:64910690c574 492 * @arg QSPI_IT_TE: QSPI Transfer error interrupt
AnnaBridge 145:64910690c574 493 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
AnnaBridge 145:64910690c574 494 */
AnnaBridge 145:64910690c574 495 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))
AnnaBridge 145:64910690c574 496
AnnaBridge 145:64910690c574 497 /**
AnnaBridge 145:64910690c574 498 * @brief Check whether the selected QSPI flag is set or not.
AnnaBridge 145:64910690c574 499 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 500 * @param __FLAG__: specifies the QSPI flag to check.
AnnaBridge 145:64910690c574 501 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 502 * @arg QSPI_FLAG_BUSY: QSPI Busy flag
AnnaBridge 145:64910690c574 503 * @arg QSPI_FLAG_TO: QSPI Timeout flag
AnnaBridge 145:64910690c574 504 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 145:64910690c574 505 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag
AnnaBridge 145:64910690c574 506 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 145:64910690c574 507 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 145:64910690c574 508 * @retval None
AnnaBridge 145:64910690c574 509 */
AnnaBridge 145:64910690c574 510 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0)
AnnaBridge 145:64910690c574 511
AnnaBridge 145:64910690c574 512 /** @brief Clears the specified QSPI's flag status.
AnnaBridge 145:64910690c574 513 * @param __HANDLE__: specifies the QSPI Handle.
AnnaBridge 145:64910690c574 514 * @param __FLAG__: specifies the QSPI clear register flag that needs to be set
AnnaBridge 145:64910690c574 515 * This parameter can be one of the following values:
AnnaBridge 145:64910690c574 516 * @arg QSPI_FLAG_TO: QSPI Timeout flag
AnnaBridge 145:64910690c574 517 * @arg QSPI_FLAG_SM: QSPI Status match flag
AnnaBridge 145:64910690c574 518 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag
AnnaBridge 145:64910690c574 519 * @arg QSPI_FLAG_TE: QSPI Transfer error flag
AnnaBridge 145:64910690c574 520 * @retval None
AnnaBridge 145:64910690c574 521 */
AnnaBridge 145:64910690c574 522 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))
AnnaBridge 145:64910690c574 523 /**
AnnaBridge 145:64910690c574 524 * @}
AnnaBridge 145:64910690c574 525 */
AnnaBridge 145:64910690c574 526
AnnaBridge 145:64910690c574 527 /* Exported functions --------------------------------------------------------*/
AnnaBridge 145:64910690c574 528 /** @addtogroup QSPI_Exported_Functions
AnnaBridge 145:64910690c574 529 * @{
AnnaBridge 145:64910690c574 530 */
AnnaBridge 145:64910690c574 531 /* Initialization/de-initialization functions ********************************/
AnnaBridge 145:64910690c574 532 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 533 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 534 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 535 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 536
AnnaBridge 145:64910690c574 537 /* IO operation functions *****************************************************/
AnnaBridge 145:64910690c574 538 /* QSPI IRQ handler method */
AnnaBridge 145:64910690c574 539 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 540
AnnaBridge 145:64910690c574 541 /* QSPI indirect mode */
AnnaBridge 145:64910690c574 542 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);
AnnaBridge 145:64910690c574 543 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 145:64910690c574 544 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);
AnnaBridge 145:64910690c574 545 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);
AnnaBridge 145:64910690c574 546 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 547 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 548 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 549 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);
AnnaBridge 145:64910690c574 550
AnnaBridge 145:64910690c574 551 /* QSPI status flag polling mode */
AnnaBridge 145:64910690c574 552 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);
AnnaBridge 145:64910690c574 553 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);
AnnaBridge 145:64910690c574 554
AnnaBridge 145:64910690c574 555 /* QSPI memory-mapped mode */
AnnaBridge 145:64910690c574 556 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);
AnnaBridge 145:64910690c574 557
AnnaBridge 145:64910690c574 558 /* Callback functions in non-blocking modes ***********************************/
AnnaBridge 145:64910690c574 559 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 560 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 561 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 562
AnnaBridge 145:64910690c574 563 /* QSPI indirect mode */
AnnaBridge 145:64910690c574 564 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 565 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 566 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 567 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 568 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 569
AnnaBridge 145:64910690c574 570 /* QSPI status flag polling mode */
AnnaBridge 145:64910690c574 571 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 572
AnnaBridge 145:64910690c574 573 /* QSPI memory-mapped mode */
AnnaBridge 145:64910690c574 574 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 575
AnnaBridge 145:64910690c574 576 /* Peripheral Control and State functions ************************************/
AnnaBridge 145:64910690c574 577 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 578 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 579 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 580 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 581 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
AnnaBridge 145:64910690c574 582 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
AnnaBridge 145:64910690c574 583 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
AnnaBridge 145:64910690c574 584 /**
AnnaBridge 145:64910690c574 585 * @}
AnnaBridge 145:64910690c574 586 */
AnnaBridge 145:64910690c574 587 /* End of exported functions -------------------------------------------------*/
AnnaBridge 145:64910690c574 588
AnnaBridge 145:64910690c574 589 /* Private macros ------------------------------------------------------------*/
AnnaBridge 145:64910690c574 590 /** @defgroup QSPI_Private_Macros QSPI Private Macros
AnnaBridge 145:64910690c574 591 * @{
AnnaBridge 145:64910690c574 592 */
AnnaBridge 145:64910690c574 593 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFF)
AnnaBridge 145:64910690c574 594
AnnaBridge 145:64910690c574 595 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0) && ((THR) <= 16))
AnnaBridge 145:64910690c574 596
AnnaBridge 145:64910690c574 597 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \
AnnaBridge 145:64910690c574 598 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))
AnnaBridge 145:64910690c574 599
AnnaBridge 145:64910690c574 600 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31))
AnnaBridge 145:64910690c574 601
AnnaBridge 145:64910690c574 602 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \
AnnaBridge 145:64910690c574 603 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \
AnnaBridge 145:64910690c574 604 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \
AnnaBridge 145:64910690c574 605 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \
AnnaBridge 145:64910690c574 606 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \
AnnaBridge 145:64910690c574 607 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \
AnnaBridge 145:64910690c574 608 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \
AnnaBridge 145:64910690c574 609 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))
AnnaBridge 145:64910690c574 610
AnnaBridge 145:64910690c574 611 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \
AnnaBridge 145:64910690c574 612 ((CLKMODE) == QSPI_CLOCK_MODE_3))
AnnaBridge 145:64910690c574 613
AnnaBridge 145:64910690c574 614 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
AnnaBridge 145:64910690c574 615 defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 145:64910690c574 616 defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 145:64910690c574 617 #define IS_QSPI_FLASH_ID(FLASH) (((FLASH) == QSPI_FLASH_ID_1) || \
AnnaBridge 145:64910690c574 618 ((FLASH) == QSPI_FLASH_ID_2))
AnnaBridge 145:64910690c574 619
AnnaBridge 145:64910690c574 620 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \
AnnaBridge 145:64910690c574 621 ((MODE) == QSPI_DUALFLASH_DISABLE))
AnnaBridge 145:64910690c574 622 #endif
AnnaBridge 145:64910690c574 623
AnnaBridge 145:64910690c574 624 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFF)
AnnaBridge 145:64910690c574 625
AnnaBridge 145:64910690c574 626 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \
AnnaBridge 145:64910690c574 627 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \
AnnaBridge 145:64910690c574 628 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \
AnnaBridge 145:64910690c574 629 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))
AnnaBridge 145:64910690c574 630
AnnaBridge 145:64910690c574 631 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \
AnnaBridge 145:64910690c574 632 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \
AnnaBridge 145:64910690c574 633 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \
AnnaBridge 145:64910690c574 634 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))
AnnaBridge 145:64910690c574 635
AnnaBridge 145:64910690c574 636 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31)
AnnaBridge 145:64910690c574 637
AnnaBridge 145:64910690c574 638 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \
AnnaBridge 145:64910690c574 639 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \
AnnaBridge 145:64910690c574 640 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \
AnnaBridge 145:64910690c574 641 ((MODE) == QSPI_INSTRUCTION_4_LINES))
AnnaBridge 145:64910690c574 642
AnnaBridge 145:64910690c574 643 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \
AnnaBridge 145:64910690c574 644 ((MODE) == QSPI_ADDRESS_1_LINE) || \
AnnaBridge 145:64910690c574 645 ((MODE) == QSPI_ADDRESS_2_LINES) || \
AnnaBridge 145:64910690c574 646 ((MODE) == QSPI_ADDRESS_4_LINES))
AnnaBridge 145:64910690c574 647
AnnaBridge 145:64910690c574 648 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \
AnnaBridge 145:64910690c574 649 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \
AnnaBridge 145:64910690c574 650 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \
AnnaBridge 145:64910690c574 651 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))
AnnaBridge 145:64910690c574 652
AnnaBridge 145:64910690c574 653 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \
AnnaBridge 145:64910690c574 654 ((MODE) == QSPI_DATA_1_LINE) || \
AnnaBridge 145:64910690c574 655 ((MODE) == QSPI_DATA_2_LINES) || \
AnnaBridge 145:64910690c574 656 ((MODE) == QSPI_DATA_4_LINES))
AnnaBridge 145:64910690c574 657
AnnaBridge 145:64910690c574 658 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \
AnnaBridge 145:64910690c574 659 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))
AnnaBridge 145:64910690c574 660
AnnaBridge 145:64910690c574 661 #if defined(STM32L431xx) || defined(STM32L432xx) || defined(STM32L433xx) || defined(STM32L442xx) || \
AnnaBridge 145:64910690c574 662 defined(STM32L443xx) || defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \
AnnaBridge 145:64910690c574 663 defined(STM32L496xx) || defined(STM32L4A6xx)
AnnaBridge 145:64910690c574 664 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \
AnnaBridge 145:64910690c574 665 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))
AnnaBridge 145:64910690c574 666 #else
AnnaBridge 145:64910690c574 667 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY))
AnnaBridge 145:64910690c574 668 #endif
AnnaBridge 145:64910690c574 669
AnnaBridge 145:64910690c574 670 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \
AnnaBridge 145:64910690c574 671 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))
AnnaBridge 145:64910690c574 672
AnnaBridge 145:64910690c574 673 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL)
AnnaBridge 145:64910690c574 674
AnnaBridge 145:64910690c574 675 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1) && ((SIZE) <= 4))
AnnaBridge 145:64910690c574 676
AnnaBridge 145:64910690c574 677 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \
AnnaBridge 145:64910690c574 678 ((MODE) == QSPI_MATCH_MODE_OR))
AnnaBridge 145:64910690c574 679
AnnaBridge 145:64910690c574 680 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \
AnnaBridge 145:64910690c574 681 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))
AnnaBridge 145:64910690c574 682
AnnaBridge 145:64910690c574 683 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \
AnnaBridge 145:64910690c574 684 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))
AnnaBridge 145:64910690c574 685
AnnaBridge 145:64910690c574 686 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFF)
AnnaBridge 145:64910690c574 687 /**
AnnaBridge 145:64910690c574 688 * @}
AnnaBridge 145:64910690c574 689 */
AnnaBridge 145:64910690c574 690 /* End of private macros -----------------------------------------------------*/
AnnaBridge 145:64910690c574 691
AnnaBridge 145:64910690c574 692 /**
AnnaBridge 145:64910690c574 693 * @}
AnnaBridge 145:64910690c574 694 */
AnnaBridge 145:64910690c574 695
AnnaBridge 145:64910690c574 696 /**
AnnaBridge 145:64910690c574 697 * @}
AnnaBridge 145:64910690c574 698 */
AnnaBridge 145:64910690c574 699
AnnaBridge 145:64910690c574 700 #ifdef __cplusplus
AnnaBridge 145:64910690c574 701 }
AnnaBridge 145:64910690c574 702 #endif
AnnaBridge 145:64910690c574 703
AnnaBridge 145:64910690c574 704 #endif /* __STM32L4xx_HAL_QSPI_H */
AnnaBridge 145:64910690c574 705
AnnaBridge 145:64910690c574 706 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/