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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_IAR/stm32l4xx_hal_adc_ex.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L496AG/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_adc_ex.h@165:d1b4690b3f8b

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	165:d1b4690b3f8b	1	/**
AnnaBridge	165:d1b4690b3f8b	2	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	3	* @file stm32l4xx_hal_adc_ex.h
AnnaBridge	165:d1b4690b3f8b	4	* @author MCD Application Team
AnnaBridge	165:d1b4690b3f8b	5	* @brief Header file of ADC HAL extended module.
AnnaBridge	165:d1b4690b3f8b	6	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	7	* @attention
AnnaBridge	165:d1b4690b3f8b	8	*
AnnaBridge	165:d1b4690b3f8b	9	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	165:d1b4690b3f8b	10	*
AnnaBridge	165:d1b4690b3f8b	11	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	165:d1b4690b3f8b	12	* are permitted provided that the following conditions are met:
AnnaBridge	165:d1b4690b3f8b	13	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	14	* this list of conditions and the following disclaimer.
AnnaBridge	165:d1b4690b3f8b	15	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	165:d1b4690b3f8b	16	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	165:d1b4690b3f8b	17	* and/or other materials provided with the distribution.
AnnaBridge	165:d1b4690b3f8b	18	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	165:d1b4690b3f8b	19	* may be used to endorse or promote products derived from this software
AnnaBridge	165:d1b4690b3f8b	20	* without specific prior written permission.
AnnaBridge	165:d1b4690b3f8b	21	*
AnnaBridge	165:d1b4690b3f8b	22	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	165:d1b4690b3f8b	23	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	165:d1b4690b3f8b	24	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	165:d1b4690b3f8b	25	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	165:d1b4690b3f8b	26	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	165:d1b4690b3f8b	27	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	165:d1b4690b3f8b	28	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	165:d1b4690b3f8b	29	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	165:d1b4690b3f8b	30	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	165:d1b4690b3f8b	31	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	165:d1b4690b3f8b	32	*
AnnaBridge	165:d1b4690b3f8b	33	******************************************************************************
AnnaBridge	165:d1b4690b3f8b	34	*/
AnnaBridge	165:d1b4690b3f8b	35
AnnaBridge	165:d1b4690b3f8b	36	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	37	#ifndef __STM32L4xx_HAL_ADC_EX_H
AnnaBridge	165:d1b4690b3f8b	38	#define __STM32L4xx_HAL_ADC_EX_H
AnnaBridge	165:d1b4690b3f8b	39
AnnaBridge	165:d1b4690b3f8b	40	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	41	extern "C" {
AnnaBridge	165:d1b4690b3f8b	42	#endif
AnnaBridge	165:d1b4690b3f8b	43
AnnaBridge	165:d1b4690b3f8b	44	/* Includes ------------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	45	#include "stm32l4xx_hal_def.h"
AnnaBridge	165:d1b4690b3f8b	46
AnnaBridge	165:d1b4690b3f8b	47	/** @addtogroup STM32L4xx_HAL_Driver
AnnaBridge	165:d1b4690b3f8b	48	* @{
AnnaBridge	165:d1b4690b3f8b	49	*/
AnnaBridge	165:d1b4690b3f8b	50
AnnaBridge	165:d1b4690b3f8b	51	/** @addtogroup ADCEx
AnnaBridge	165:d1b4690b3f8b	52	* @{
AnnaBridge	165:d1b4690b3f8b	53	*/
AnnaBridge	165:d1b4690b3f8b	54
AnnaBridge	165:d1b4690b3f8b	55	/* Exported types ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	56	/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
AnnaBridge	165:d1b4690b3f8b	57	* @{
AnnaBridge	165:d1b4690b3f8b	58	*/
AnnaBridge	165:d1b4690b3f8b	59
AnnaBridge	165:d1b4690b3f8b	60	/**
AnnaBridge	165:d1b4690b3f8b	61	* @brief ADC Injected Conversion Oversampling structure definition
AnnaBridge	165:d1b4690b3f8b	62	*/
AnnaBridge	165:d1b4690b3f8b	63	typedef struct
AnnaBridge	165:d1b4690b3f8b	64	{
AnnaBridge	165:d1b4690b3f8b	65	uint32_t Ratio; /*!< Configures the oversampling ratio.
AnnaBridge	165:d1b4690b3f8b	66	This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
AnnaBridge	165:d1b4690b3f8b	67
AnnaBridge	165:d1b4690b3f8b	68	uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
AnnaBridge	165:d1b4690b3f8b	69	This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
AnnaBridge	165:d1b4690b3f8b	70	}ADC_InjOversamplingTypeDef;
AnnaBridge	165:d1b4690b3f8b	71
AnnaBridge	165:d1b4690b3f8b	72	/**
AnnaBridge	165:d1b4690b3f8b	73	* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
AnnaBridge	165:d1b4690b3f8b	74	* @note Parameters of this structure are shared within 2 scopes:
AnnaBridge	165:d1b4690b3f8b	75	* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
AnnaBridge	165:d1b4690b3f8b	76	* - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
AnnaBridge	165:d1b4690b3f8b	77	* AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.
AnnaBridge	165:d1b4690b3f8b	78	* @note The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
AnnaBridge	165:d1b4690b3f8b	79	* ADC state can be either:
AnnaBridge	165:d1b4690b3f8b	80	* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
AnnaBridge	165:d1b4690b3f8b	81	* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
AnnaBridge	165:d1b4690b3f8b	82	* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
AnnaBridge	165:d1b4690b3f8b	83	* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
AnnaBridge	165:d1b4690b3f8b	84	* on ADC groups regular and injected.
AnnaBridge	165:d1b4690b3f8b	85	* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
AnnaBridge	165:d1b4690b3f8b	86	* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
AnnaBridge	165:d1b4690b3f8b	87	*/
AnnaBridge	165:d1b4690b3f8b	88	typedef struct
AnnaBridge	165:d1b4690b3f8b	89	{
AnnaBridge	165:d1b4690b3f8b	90	uint32_t InjectedChannel; /*!< Specifies the channel to configure into ADC group injected.
AnnaBridge	165:d1b4690b3f8b	91	This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
AnnaBridge	165:d1b4690b3f8b	92	Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */
AnnaBridge	165:d1b4690b3f8b	93
AnnaBridge	165:d1b4690b3f8b	94	uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
AnnaBridge	165:d1b4690b3f8b	95	This parameter must be a value of @ref ADC_LL_EC_INJ_SEQ_RANKS.
AnnaBridge	165:d1b4690b3f8b	96	Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
AnnaBridge	165:d1b4690b3f8b	97	the new channel setting (or parameter number of conversions adjusted) */
AnnaBridge	165:d1b4690b3f8b	98
AnnaBridge	165:d1b4690b3f8b	99	uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
AnnaBridge	165:d1b4690b3f8b	100	Unit: ADC clock cycles.
AnnaBridge	165:d1b4690b3f8b	101	Conversion time is the addition of sampling time and processing time
AnnaBridge	165:d1b4690b3f8b	102	(12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
AnnaBridge	165:d1b4690b3f8b	103	This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
AnnaBridge	165:d1b4690b3f8b	104	Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
AnnaBridge	165:d1b4690b3f8b	105	It overwrites the last setting.
AnnaBridge	165:d1b4690b3f8b	106	Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
AnnaBridge	165:d1b4690b3f8b	107	sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
AnnaBridge	165:d1b4690b3f8b	108	Refer to device datasheet for timings values. */
AnnaBridge	165:d1b4690b3f8b	109
AnnaBridge	165:d1b4690b3f8b	110	uint32_t InjectedSingleDiff; /*!< Selection of single-ended or differential input.
AnnaBridge	165:d1b4690b3f8b	111	In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).
AnnaBridge	165:d1b4690b3f8b	112	Only channel 'i' has to be configured, channel 'i+1' is configured automatically.
AnnaBridge	165:d1b4690b3f8b	113	This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
AnnaBridge	165:d1b4690b3f8b	114	Caution: This parameter applies to a channel that can be used in a regular and/or injected group.
AnnaBridge	165:d1b4690b3f8b	115	It overwrites the last setting.
AnnaBridge	165:d1b4690b3f8b	116	Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
AnnaBridge	165:d1b4690b3f8b	117	Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
AnnaBridge	165:d1b4690b3f8b	118	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
AnnaBridge	165:d1b4690b3f8b	119	If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
AnnaBridge	165:d1b4690b3f8b	120	of another parameter update on the fly) */
AnnaBridge	165:d1b4690b3f8b	121
AnnaBridge	165:d1b4690b3f8b	122	uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
AnnaBridge	165:d1b4690b3f8b	123	This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
AnnaBridge	165:d1b4690b3f8b	124	Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */
AnnaBridge	165:d1b4690b3f8b	125
AnnaBridge	165:d1b4690b3f8b	126	uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data.
AnnaBridge	165:d1b4690b3f8b	127	Offset value must be a positive number.
AnnaBridge	165:d1b4690b3f8b	128	Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
AnnaBridge	165:d1b4690b3f8b	129	between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
AnnaBridge	165:d1b4690b3f8b	130	Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
AnnaBridge	165:d1b4690b3f8b	131	without continuous mode or external trigger that could launch a conversion). */
AnnaBridge	165:d1b4690b3f8b	132
AnnaBridge	165:d1b4690b3f8b	133	uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
AnnaBridge	165:d1b4690b3f8b	134	To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
AnnaBridge	165:d1b4690b3f8b	135	This parameter must be a number between Min_Data = 1 and Max_Data = 4.
AnnaBridge	165:d1b4690b3f8b	136	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge	165:d1b4690b3f8b	137	configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge	165:d1b4690b3f8b	138
AnnaBridge	165:d1b4690b3f8b	139	uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
AnnaBridge	165:d1b4690b3f8b	140	(main sequence subdivided in successive parts).
AnnaBridge	165:d1b4690b3f8b	141	Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
AnnaBridge	165:d1b4690b3f8b	142	Discontinuous mode can be enabled only if continuous mode is disabled.
AnnaBridge	165:d1b4690b3f8b	143	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	165:d1b4690b3f8b	144	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
AnnaBridge	165:d1b4690b3f8b	145	Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
AnnaBridge	165:d1b4690b3f8b	146	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge	165:d1b4690b3f8b	147	configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge	165:d1b4690b3f8b	148
AnnaBridge	165:d1b4690b3f8b	149	uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
AnnaBridge	165:d1b4690b3f8b	150	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	165:d1b4690b3f8b	151	Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
AnnaBridge	165:d1b4690b3f8b	152	Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
AnnaBridge	165:d1b4690b3f8b	153	Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
AnnaBridge	165:d1b4690b3f8b	154	To maintain JAUTO always enabled, DMA must be configured in circular mode.
AnnaBridge	165:d1b4690b3f8b	155	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge	165:d1b4690b3f8b	156	configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge	165:d1b4690b3f8b	157
AnnaBridge	165:d1b4690b3f8b	158	uint32_t QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
AnnaBridge	165:d1b4690b3f8b	159	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	165:d1b4690b3f8b	160	If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
AnnaBridge	165:d1b4690b3f8b	161	new injected context is set when queue is full, error is triggered by interruption and through function
AnnaBridge	165:d1b4690b3f8b	162	'HAL_ADCEx_InjectedQueueOverflowCallback'.
AnnaBridge	165:d1b4690b3f8b	163	Caution: This feature request that the sequence is fully configured before injected conversion start.
AnnaBridge	165:d1b4690b3f8b	164	Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
AnnaBridge	165:d1b4690b3f8b	165	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge	165:d1b4690b3f8b	166	configure a channel on injected group can impact the configuration of other channels previously set.
AnnaBridge	165:d1b4690b3f8b	167	Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
AnnaBridge	165:d1b4690b3f8b	168
AnnaBridge	165:d1b4690b3f8b	169	uint32_t ExternalTrigInjecConv; /*!< Selects the external event used to trigger the conversion start of injected group.
AnnaBridge	165:d1b4690b3f8b	170	If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
AnnaBridge	165:d1b4690b3f8b	171	This parameter can be a value of @ref ADC_injected_external_trigger_source.
AnnaBridge	165:d1b4690b3f8b	172	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge	165:d1b4690b3f8b	173	configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge	165:d1b4690b3f8b	174
AnnaBridge	165:d1b4690b3f8b	175	uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
AnnaBridge	165:d1b4690b3f8b	176	This parameter can be a value of @ref ADC_injected_external_trigger_edge.
AnnaBridge	165:d1b4690b3f8b	177	If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
AnnaBridge	165:d1b4690b3f8b	178	Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
AnnaBridge	165:d1b4690b3f8b	179	configure a channel on injected group can impact the configuration of other channels previously set. */
AnnaBridge	165:d1b4690b3f8b	180
AnnaBridge	165:d1b4690b3f8b	181	uint32_t InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
AnnaBridge	165:d1b4690b3f8b	182	This parameter can be set to ENABLE or DISABLE.
AnnaBridge	165:d1b4690b3f8b	183	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
AnnaBridge	165:d1b4690b3f8b	184
AnnaBridge	165:d1b4690b3f8b	185	ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
AnnaBridge	165:d1b4690b3f8b	186	Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
AnnaBridge	165:d1b4690b3f8b	187	Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
AnnaBridge	165:d1b4690b3f8b	188	}ADC_InjectionConfTypeDef;
AnnaBridge	165:d1b4690b3f8b	189
AnnaBridge	165:d1b4690b3f8b	190	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	191	/**
AnnaBridge	165:d1b4690b3f8b	192	* @brief Structure definition of ADC multimode
AnnaBridge	165:d1b4690b3f8b	193	* @note The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).
AnnaBridge	165:d1b4690b3f8b	194	* Both Master and Slave ADCs must be disabled.
AnnaBridge	165:d1b4690b3f8b	195	*/
AnnaBridge	165:d1b4690b3f8b	196	typedef struct
AnnaBridge	165:d1b4690b3f8b	197	{
AnnaBridge	165:d1b4690b3f8b	198	uint32_t Mode; /*!< Configures the ADC to operate in independent or multimode.
AnnaBridge	165:d1b4690b3f8b	199	This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
AnnaBridge	165:d1b4690b3f8b	200
AnnaBridge	165:d1b4690b3f8b	201	uint32_t DMAAccessMode; /*!< Configures the DMA mode for multimode ADC:
AnnaBridge	165:d1b4690b3f8b	202	selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel (one DMA channel for both ADC, DMA of ADC master)
AnnaBridge	165:d1b4690b3f8b	203	This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
AnnaBridge	165:d1b4690b3f8b	204
AnnaBridge	165:d1b4690b3f8b	205	uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
AnnaBridge	165:d1b4690b3f8b	206	This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
AnnaBridge	165:d1b4690b3f8b	207	Delay range depends on selected resolution:
AnnaBridge	165:d1b4690b3f8b	208	from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
AnnaBridge	165:d1b4690b3f8b	209	from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits. */
AnnaBridge	165:d1b4690b3f8b	210	}ADC_MultiModeTypeDef;
AnnaBridge	165:d1b4690b3f8b	211	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	212
AnnaBridge	165:d1b4690b3f8b	213	/**
AnnaBridge	165:d1b4690b3f8b	214	* @}
AnnaBridge	165:d1b4690b3f8b	215	*/
AnnaBridge	165:d1b4690b3f8b	216
AnnaBridge	165:d1b4690b3f8b	217	/* Exported constants --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	218
AnnaBridge	165:d1b4690b3f8b	219	/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
AnnaBridge	165:d1b4690b3f8b	220	* @{
AnnaBridge	165:d1b4690b3f8b	221	*/
AnnaBridge	165:d1b4690b3f8b	222
AnnaBridge	165:d1b4690b3f8b	223	/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
AnnaBridge	165:d1b4690b3f8b	224	* @{
AnnaBridge	165:d1b4690b3f8b	225	*/
AnnaBridge	165:d1b4690b3f8b	226	/* ADC group regular trigger sources for all ADC instances */
AnnaBridge	165:d1b4690b3f8b	227	#define ADC_INJECTED_SOFTWARE_START (LL_ADC_INJ_TRIG_SOFTWARE) /!< Software triggers injected group conversion start /
AnnaBridge	165:d1b4690b3f8b	228	#define ADC_EXTERNALTRIGINJEC_T1_TRGO (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	229	#define ADC_EXTERNALTRIGINJEC_T1_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) /!< ADC group injected conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	230	#define ADC_EXTERNALTRIGINJEC_T1_CC4 (LL_ADC_INJ_TRIG_EXT_TIM1_CH4) /!< ADC group injected conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	231	#define ADC_EXTERNALTRIGINJEC_T2_TRGO (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) /!< ADC group injected conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	232	#define ADC_EXTERNALTRIGINJEC_T2_CC1 (LL_ADC_INJ_TRIG_EXT_TIM2_CH1) /!< ADC group injected conversion trigger from external IP: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	233	#define ADC_EXTERNALTRIGINJEC_T3_TRGO (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) /!< ADC group injected conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	234	#define ADC_EXTERNALTRIGINJEC_T3_CC1 (LL_ADC_INJ_TRIG_EXT_TIM3_CH1) /!< ADC group injected conversion trigger from external IP: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	235	#define ADC_EXTERNALTRIGINJEC_T3_CC3 (LL_ADC_INJ_TRIG_EXT_TIM3_CH3) /!< ADC group injected conversion trigger from external IP: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	236	#define ADC_EXTERNALTRIGINJEC_T3_CC4 (LL_ADC_INJ_TRIG_EXT_TIM3_CH4) /!< ADC group injected conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	237	#define ADC_EXTERNALTRIGINJEC_T4_TRGO (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) /!< ADC group injected conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	238	#define ADC_EXTERNALTRIGINJEC_T6_TRGO (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) /!< ADC group injected conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	239	#define ADC_EXTERNALTRIGINJEC_T8_CC4 (LL_ADC_INJ_TRIG_EXT_TIM8_CH4) /!< ADC group injected conversion trigger from external IP: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	240	#define ADC_EXTERNALTRIGINJEC_T8_TRGO (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	241	#define ADC_EXTERNALTRIGINJEC_T8_TRGO2 (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) /!< ADC group injected conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	242	#define ADC_EXTERNALTRIGINJEC_T15_TRGO (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) /!< ADC group injected conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	243	#define ADC_EXTERNALTRIGINJEC_EXT_IT15 (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) /!< ADC group injected conversion trigger from external IP: external interrupt line 15. Trigger edge set to rising edge (default setting). /
AnnaBridge	165:d1b4690b3f8b	244	/**
AnnaBridge	165:d1b4690b3f8b	245	* @}
AnnaBridge	165:d1b4690b3f8b	246	*/
AnnaBridge	165:d1b4690b3f8b	247
AnnaBridge	165:d1b4690b3f8b	248	/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
AnnaBridge	165:d1b4690b3f8b	249	* @{
AnnaBridge	165:d1b4690b3f8b	250	*/
AnnaBridge	165:d1b4690b3f8b	251	#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000U) /!< Injected conversions hardware trigger detection disabled /
AnnaBridge	165:d1b4690b3f8b	252	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /!< Injected conversions hardware trigger detection on the rising edge /
AnnaBridge	165:d1b4690b3f8b	253	#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /!< Injected conversions hardware trigger detection on the falling edge /
AnnaBridge	165:d1b4690b3f8b	254	#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /!< Injected conversions hardware trigger detection on both the rising and falling edges /
AnnaBridge	165:d1b4690b3f8b	255	/**
AnnaBridge	165:d1b4690b3f8b	256	* @}
AnnaBridge	165:d1b4690b3f8b	257	*/
AnnaBridge	165:d1b4690b3f8b	258
AnnaBridge	165:d1b4690b3f8b	259	/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING Channel - Single or differential ending
AnnaBridge	165:d1b4690b3f8b	260	* @{
AnnaBridge	165:d1b4690b3f8b	261	*/
AnnaBridge	165:d1b4690b3f8b	262	#define ADC_SINGLE_ENDED (LL_ADC_SINGLE_ENDED) /!< ADC channel ending set to single ended (literal also used to set calibration mode) /
AnnaBridge	165:d1b4690b3f8b	263	#define ADC_DIFFERENTIAL_ENDED (LL_ADC_DIFFERENTIAL_ENDED) /!< ADC channel ending set to differential (literal also used to set calibration mode) /
AnnaBridge	165:d1b4690b3f8b	264	/**
AnnaBridge	165:d1b4690b3f8b	265	* @}
AnnaBridge	165:d1b4690b3f8b	266	*/
AnnaBridge	165:d1b4690b3f8b	267
AnnaBridge	165:d1b4690b3f8b	268	/** @defgroup ADC_HAL_EC_OFFSET_NB ADC instance - Offset number
AnnaBridge	165:d1b4690b3f8b	269	* @{
AnnaBridge	165:d1b4690b3f8b	270	*/
AnnaBridge	165:d1b4690b3f8b	271	#define ADC_OFFSET_NONE (ADC_OFFSET_4 + 1U) /!< ADC offset disabled: no offset correction for the selected ADC channel /
AnnaBridge	165:d1b4690b3f8b	272	#define ADC_OFFSET_1 (LL_ADC_OFFSET_1) /!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
AnnaBridge	165:d1b4690b3f8b	273	#define ADC_OFFSET_2 (LL_ADC_OFFSET_2) /!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
AnnaBridge	165:d1b4690b3f8b	274	#define ADC_OFFSET_3 (LL_ADC_OFFSET_3) /!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
AnnaBridge	165:d1b4690b3f8b	275	#define ADC_OFFSET_4 (LL_ADC_OFFSET_4) /!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) /
AnnaBridge	165:d1b4690b3f8b	276	/**
AnnaBridge	165:d1b4690b3f8b	277	* @}
AnnaBridge	165:d1b4690b3f8b	278	*/
AnnaBridge	165:d1b4690b3f8b	279
AnnaBridge	165:d1b4690b3f8b	280	/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS ADC group injected - Sequencer ranks
AnnaBridge	165:d1b4690b3f8b	281	* @{
AnnaBridge	165:d1b4690b3f8b	282	*/
AnnaBridge	165:d1b4690b3f8b	283	#define ADC_INJECTED_RANK_1 (LL_ADC_INJ_RANK_1) /!< ADC group injected sequencer rank 1 /
AnnaBridge	165:d1b4690b3f8b	284	#define ADC_INJECTED_RANK_2 (LL_ADC_INJ_RANK_2) /!< ADC group injected sequencer rank 2 /
AnnaBridge	165:d1b4690b3f8b	285	#define ADC_INJECTED_RANK_3 (LL_ADC_INJ_RANK_3) /!< ADC group injected sequencer rank 3 /
AnnaBridge	165:d1b4690b3f8b	286	#define ADC_INJECTED_RANK_4 (LL_ADC_INJ_RANK_4) /!< ADC group injected sequencer rank 4 /
AnnaBridge	165:d1b4690b3f8b	287	/**
AnnaBridge	165:d1b4690b3f8b	288	* @}
AnnaBridge	165:d1b4690b3f8b	289	*/
AnnaBridge	165:d1b4690b3f8b	290
AnnaBridge	165:d1b4690b3f8b	291	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	292	/** @defgroup ADC_HAL_EC_MULTI_MODE Multimode - Mode
AnnaBridge	165:d1b4690b3f8b	293	* @{
AnnaBridge	165:d1b4690b3f8b	294	*/
AnnaBridge	165:d1b4690b3f8b	295	#define ADC_MODE_INDEPENDENT (LL_ADC_MULTI_INDEPENDENT) /!< ADC dual mode disabled (ADC independent mode) /
AnnaBridge	165:d1b4690b3f8b	296	#define ADC_DUALMODE_REGSIMULT (LL_ADC_MULTI_DUAL_REG_SIMULT) /!< ADC dual mode enabled: group regular simultaneous /
AnnaBridge	165:d1b4690b3f8b	297	#define ADC_DUALMODE_INTERL (LL_ADC_MULTI_DUAL_REG_INTERL) /!< ADC dual mode enabled: Combined group regular interleaved /
AnnaBridge	165:d1b4690b3f8b	298	#define ADC_DUALMODE_INJECSIMULT (LL_ADC_MULTI_DUAL_INJ_SIMULT) /!< ADC dual mode enabled: group injected simultaneous /
AnnaBridge	165:d1b4690b3f8b	299	#define ADC_DUALMODE_ALTERTRIG (LL_ADC_MULTI_DUAL_INJ_ALTERN) /!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) /
AnnaBridge	165:d1b4690b3f8b	300	#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous /
AnnaBridge	165:d1b4690b3f8b	301	#define ADC_DUALMODE_REGSIMULT_ALTERTRIG (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger /
AnnaBridge	165:d1b4690b3f8b	302	#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous /
AnnaBridge	165:d1b4690b3f8b	303
AnnaBridge	165:d1b4690b3f8b	304	/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION Multimode - DMA transfer mode depending on ADC resolution
AnnaBridge	165:d1b4690b3f8b	305	* @{
AnnaBridge	165:d1b4690b3f8b	306	*/
AnnaBridge	165:d1b4690b3f8b	307	#define ADC_DMAACCESSMODE_DISABLED (0x00000000U) /!< DMA multimode disabled: each ADC uses its own DMA channel /
AnnaBridge	165:d1b4690b3f8b	308	#define ADC_DMAACCESSMODE_12_10_BITS (ADC_CCR_MDMA_1) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 12 and 10 bits resolution /
AnnaBridge	165:d1b4690b3f8b	309	#define ADC_DMAACCESSMODE_8_6_BITS (ADC_CCR_MDMA) /!< DMA multimode enabled (one DMA channel for both ADC, DMA of ADC master) for 8 and 6 bits resolution /
AnnaBridge	165:d1b4690b3f8b	310	/**
AnnaBridge	165:d1b4690b3f8b	311	* @}
AnnaBridge	165:d1b4690b3f8b	312	*/
AnnaBridge	165:d1b4690b3f8b	313
AnnaBridge	165:d1b4690b3f8b	314	/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY Multimode - Delay between two sampling phases
AnnaBridge	165:d1b4690b3f8b	315	* @{
AnnaBridge	165:d1b4690b3f8b	316	*/
AnnaBridge	165:d1b4690b3f8b	317	#define ADC_TWOSAMPLINGDELAY_1CYCLE (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) /!< ADC multimode delay between two sampling phases: 1 ADC clock cycle /
AnnaBridge	165:d1b4690b3f8b	318	#define ADC_TWOSAMPLINGDELAY_2CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) /!< ADC multimode delay between two sampling phases: 2 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	319	#define ADC_TWOSAMPLINGDELAY_3CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) /!< ADC multimode delay between two sampling phases: 3 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	320	#define ADC_TWOSAMPLINGDELAY_4CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) /!< ADC multimode delay between two sampling phases: 4 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	321	#define ADC_TWOSAMPLINGDELAY_5CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) /!< ADC multimode delay between two sampling phases: 5 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	322	#define ADC_TWOSAMPLINGDELAY_6CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) /!< ADC multimode delay between two sampling phases: 6 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	323	#define ADC_TWOSAMPLINGDELAY_7CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) /!< ADC multimode delay between two sampling phases: 7 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	324	#define ADC_TWOSAMPLINGDELAY_8CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) /!< ADC multimode delay between two sampling phases: 8 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	325	#define ADC_TWOSAMPLINGDELAY_9CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) /!< ADC multimode delay between two sampling phases: 9 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	326	#define ADC_TWOSAMPLINGDELAY_10CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) /!< ADC multimode delay between two sampling phases: 10 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	327	#define ADC_TWOSAMPLINGDELAY_11CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) /!< ADC multimode delay between two sampling phases: 11 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	328	#define ADC_TWOSAMPLINGDELAY_12CYCLES (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) /!< ADC multimode delay between two sampling phases: 12 ADC clock cycles /
AnnaBridge	165:d1b4690b3f8b	329	/**
AnnaBridge	165:d1b4690b3f8b	330	* @}
AnnaBridge	165:d1b4690b3f8b	331	*/
AnnaBridge	165:d1b4690b3f8b	332
AnnaBridge	165:d1b4690b3f8b	333	/**
AnnaBridge	165:d1b4690b3f8b	334	* @}
AnnaBridge	165:d1b4690b3f8b	335	*/
AnnaBridge	165:d1b4690b3f8b	336	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	337
AnnaBridge	165:d1b4690b3f8b	338	/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups
AnnaBridge	165:d1b4690b3f8b	339	* @{
AnnaBridge	165:d1b4690b3f8b	340	*/
AnnaBridge	165:d1b4690b3f8b	341	#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /!< ADC group regular (available on all STM32 devices) /
AnnaBridge	165:d1b4690b3f8b	342	#define ADC_INJECTED_GROUP (LL_ADC_GROUP_INJECTED) /!< ADC group injected (not available on all STM32 devices)/
AnnaBridge	165:d1b4690b3f8b	343	#define ADC_REGULAR_INJECTED_GROUP (LL_ADC_GROUP_REGULAR_INJECTED) /!< ADC both groups regular and injected /
AnnaBridge	165:d1b4690b3f8b	344	/**
AnnaBridge	165:d1b4690b3f8b	345	* @}
AnnaBridge	165:d1b4690b3f8b	346	*/
AnnaBridge	165:d1b4690b3f8b	347
AnnaBridge	165:d1b4690b3f8b	348	/** @defgroup ADC_CFGR_fields ADCx CFGR fields
AnnaBridge	165:d1b4690b3f8b	349	* @{
AnnaBridge	165:d1b4690b3f8b	350	*/
AnnaBridge	165:d1b4690b3f8b	351	#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	352	#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH \| ADC_CFGR_JAUTO \| ADC_CFGR_JAWD1EN \|\
AnnaBridge	165:d1b4690b3f8b	353	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL \| ADC_CFGR_JQM \|\
AnnaBridge	165:d1b4690b3f8b	354	ADC_CFGR_JDISCEN \| ADC_CFGR_DISCNUM \| ADC_CFGR_DISCEN \|\
AnnaBridge	165:d1b4690b3f8b	355	ADC_CFGR_AUTDLY \| ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
AnnaBridge	165:d1b4690b3f8b	356	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL \| ADC_CFGR_ALIGN \|\
AnnaBridge	165:d1b4690b3f8b	357	ADC_CFGR_RES \| ADC_CFGR_DFSDMCFG \| ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN)
AnnaBridge	165:d1b4690b3f8b	358	#else
AnnaBridge	165:d1b4690b3f8b	359	#define ADC_CFGR_FIELDS (ADC_CFGR_AWD1CH \| ADC_CFGR_JAUTO \| ADC_CFGR_JAWD1EN \|\
AnnaBridge	165:d1b4690b3f8b	360	ADC_CFGR_AWD1EN \| ADC_CFGR_AWD1SGL \| ADC_CFGR_JQM \|\
AnnaBridge	165:d1b4690b3f8b	361	ADC_CFGR_JDISCEN \| ADC_CFGR_DISCNUM \| ADC_CFGR_DISCEN \|\
AnnaBridge	165:d1b4690b3f8b	362	ADC_CFGR_AUTDLY \| ADC_CFGR_CONT \| ADC_CFGR_OVRMOD \|\
AnnaBridge	165:d1b4690b3f8b	363	ADC_CFGR_EXTEN \| ADC_CFGR_EXTSEL \| ADC_CFGR_ALIGN \|\
AnnaBridge	165:d1b4690b3f8b	364	ADC_CFGR_RES \| ADC_CFGR_DMACFG \| ADC_CFGR_DMAEN )
AnnaBridge	165:d1b4690b3f8b	365	#endif
AnnaBridge	165:d1b4690b3f8b	366	/**
AnnaBridge	165:d1b4690b3f8b	367	* @}
AnnaBridge	165:d1b4690b3f8b	368	*/
AnnaBridge	165:d1b4690b3f8b	369
AnnaBridge	165:d1b4690b3f8b	370	/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
AnnaBridge	165:d1b4690b3f8b	371	* @{
AnnaBridge	165:d1b4690b3f8b	372	*/
AnnaBridge	165:d1b4690b3f8b	373	#if defined(ADC_SMPR1_SMPPLUS)
AnnaBridge	165:d1b4690b3f8b	374	#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 \| ADC_SMPR1_SMP8 \| ADC_SMPR1_SMP7 \|\
AnnaBridge	165:d1b4690b3f8b	375	ADC_SMPR1_SMP6 \| ADC_SMPR1_SMP5 \| ADC_SMPR1_SMP4 \|\
AnnaBridge	165:d1b4690b3f8b	376	ADC_SMPR1_SMP3 \| ADC_SMPR1_SMP2 \| ADC_SMPR1_SMP1 \|\
AnnaBridge	165:d1b4690b3f8b	377	ADC_SMPR1_SMP0 \| ADC_SMPR1_SMPPLUS)
AnnaBridge	165:d1b4690b3f8b	378	#else
AnnaBridge	165:d1b4690b3f8b	379	#define ADC_SMPR1_FIELDS (ADC_SMPR1_SMP9 \| ADC_SMPR1_SMP8 \| ADC_SMPR1_SMP7 \|\
AnnaBridge	165:d1b4690b3f8b	380	ADC_SMPR1_SMP6 \| ADC_SMPR1_SMP5 \| ADC_SMPR1_SMP4 \|\
AnnaBridge	165:d1b4690b3f8b	381	ADC_SMPR1_SMP3 \| ADC_SMPR1_SMP2 \| ADC_SMPR1_SMP1 \|\
AnnaBridge	165:d1b4690b3f8b	382	ADC_SMPR1_SMP0)
AnnaBridge	165:d1b4690b3f8b	383	#endif
AnnaBridge	165:d1b4690b3f8b	384	/**
AnnaBridge	165:d1b4690b3f8b	385	* @}
AnnaBridge	165:d1b4690b3f8b	386	*/
AnnaBridge	165:d1b4690b3f8b	387
AnnaBridge	165:d1b4690b3f8b	388	/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
AnnaBridge	165:d1b4690b3f8b	389	* @{
AnnaBridge	165:d1b4690b3f8b	390	*/
AnnaBridge	165:d1b4690b3f8b	391	/* ADC_CFGR fields of parameters that can be updated when no conversion
AnnaBridge	165:d1b4690b3f8b	392	(neither regular nor injected) is on-going */
AnnaBridge	165:d1b4690b3f8b	393	#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	394	#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG \| ADC_CFGR_AUTDLY \| ADC_CFGR_DFSDMCFG))
AnnaBridge	165:d1b4690b3f8b	395	#else
AnnaBridge	165:d1b4690b3f8b	396	#define ADC_CFGR_FIELDS_2 ((ADC_CFGR_DMACFG \| ADC_CFGR_AUTDLY))
AnnaBridge	165:d1b4690b3f8b	397	#endif
AnnaBridge	165:d1b4690b3f8b	398	/**
AnnaBridge	165:d1b4690b3f8b	399	* @}
AnnaBridge	165:d1b4690b3f8b	400	*/
AnnaBridge	165:d1b4690b3f8b	401
AnnaBridge	165:d1b4690b3f8b	402	#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	403	/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data
AnnaBridge	165:d1b4690b3f8b	404	* @{
AnnaBridge	165:d1b4690b3f8b	405	*/
AnnaBridge	165:d1b4690b3f8b	406	#define ADC_DFSDM_MODE_DISABLE (0x00000000U) /!< ADC conversions are not transferred by DFSDM. /
AnnaBridge	165:d1b4690b3f8b	407	#define ADC_DFSDM_MODE_ENABLE (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. /
AnnaBridge	165:d1b4690b3f8b	408	/**
AnnaBridge	165:d1b4690b3f8b	409	* @}
AnnaBridge	165:d1b4690b3f8b	410	*/
AnnaBridge	165:d1b4690b3f8b	411	#endif
AnnaBridge	165:d1b4690b3f8b	412
AnnaBridge	165:d1b4690b3f8b	413	/**
AnnaBridge	165:d1b4690b3f8b	414	* @}
AnnaBridge	165:d1b4690b3f8b	415	*/
AnnaBridge	165:d1b4690b3f8b	416
AnnaBridge	165:d1b4690b3f8b	417	/* Exported macros -----------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	418
AnnaBridge	165:d1b4690b3f8b	419	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	420	/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
AnnaBridge	165:d1b4690b3f8b	421	* @{
AnnaBridge	165:d1b4690b3f8b	422	*/
AnnaBridge	165:d1b4690b3f8b	423
AnnaBridge	165:d1b4690b3f8b	424	/** @brief Force ADC instance in multimode mode independant (multimode disable).
AnnaBridge	165:d1b4690b3f8b	425	* @note This macro must be used only in case of transition from multimode
AnnaBridge	165:d1b4690b3f8b	426	* to mode independent and in case of unknown previous state,
AnnaBridge	165:d1b4690b3f8b	427	* to ensure ADC configuration is in mode independent.
AnnaBridge	165:d1b4690b3f8b	428	* @note Standard way of multimode configuration change is done from
AnnaBridge	165:d1b4690b3f8b	429	* HAL ADC handle of ADC master using function
AnnaBridge	165:d1b4690b3f8b	430	* "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
AnnaBridge	165:d1b4690b3f8b	431	* Usage of this macro is not the Standard way of multimode
AnnaBridge	165:d1b4690b3f8b	432	* configuration and can lead to have HAL ADC handles status
AnnaBridge	165:d1b4690b3f8b	433	* misaligned. Usage of this macro must be limited to cases
AnnaBridge	165:d1b4690b3f8b	434	* mentionned above.
AnnaBridge	165:d1b4690b3f8b	435	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	436	* @retval None
AnnaBridge	165:d1b4690b3f8b	437	*/
AnnaBridge	165:d1b4690b3f8b	438	#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	439	LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
AnnaBridge	165:d1b4690b3f8b	440
AnnaBridge	165:d1b4690b3f8b	441	/**
AnnaBridge	165:d1b4690b3f8b	442	* @}
AnnaBridge	165:d1b4690b3f8b	443	*/
AnnaBridge	165:d1b4690b3f8b	444	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	445
AnnaBridge	165:d1b4690b3f8b	446	/* Private macros ------------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	447
AnnaBridge	165:d1b4690b3f8b	448	/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
AnnaBridge	165:d1b4690b3f8b	449	* @{
AnnaBridge	165:d1b4690b3f8b	450	*/
AnnaBridge	165:d1b4690b3f8b	451	/* Macro reserved for internal HAL driver usage, not intended to be used in */
AnnaBridge	165:d1b4690b3f8b	452	/* code of final user. */
AnnaBridge	165:d1b4690b3f8b	453
AnnaBridge	165:d1b4690b3f8b	454	/**
AnnaBridge	165:d1b4690b3f8b	455	* @brief Test if conversion trigger of injected group is software start
AnnaBridge	165:d1b4690b3f8b	456	* or external trigger.
AnnaBridge	165:d1b4690b3f8b	457	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	458	* @retval SET (software start) or RESET (external trigger).
AnnaBridge	165:d1b4690b3f8b	459	*/
AnnaBridge	165:d1b4690b3f8b	460	#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	461	(((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == RESET)
AnnaBridge	165:d1b4690b3f8b	462
AnnaBridge	165:d1b4690b3f8b	463	/**
AnnaBridge	165:d1b4690b3f8b	464	* @brief Check if conversion is on going on regular or injected groups.
AnnaBridge	165:d1b4690b3f8b	465	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	466	* @retval SET (conversion is on going) or RESET (no conversion is on going).
AnnaBridge	165:d1b4690b3f8b	467	*/
AnnaBridge	165:d1b4690b3f8b	468	#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	469	(( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART \| ADC_CR_JADSTART)) == RESET \
AnnaBridge	165:d1b4690b3f8b	470	) ? RESET : SET)
AnnaBridge	165:d1b4690b3f8b	471
AnnaBridge	165:d1b4690b3f8b	472	/**
AnnaBridge	165:d1b4690b3f8b	473	* @brief Check if conversion is on going on injected group.
AnnaBridge	165:d1b4690b3f8b	474	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	475	* @retval SET (conversion is on going) or RESET (no conversion is on going).
AnnaBridge	165:d1b4690b3f8b	476	*/
AnnaBridge	165:d1b4690b3f8b	477	#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	478	(LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))
AnnaBridge	165:d1b4690b3f8b	479
AnnaBridge	165:d1b4690b3f8b	480	/**
AnnaBridge	165:d1b4690b3f8b	481	* @brief Check whether or not ADC is independent.
AnnaBridge	165:d1b4690b3f8b	482	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	483	* @note When multimode feature is not available, the macro always returns SET.
AnnaBridge	165:d1b4690b3f8b	484	* @retval SET (ADC is independent) or RESET (ADC is not).
AnnaBridge	165:d1b4690b3f8b	485	*/
AnnaBridge	165:d1b4690b3f8b	486	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	487	#define ADC_IS_INDEPENDENT(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	488	( ( ( ((__HANDLE__)->Instance) == ADC3) \
AnnaBridge	165:d1b4690b3f8b	489	)? \
AnnaBridge	165:d1b4690b3f8b	490	SET \
AnnaBridge	165:d1b4690b3f8b	491	: \
AnnaBridge	165:d1b4690b3f8b	492	RESET \
AnnaBridge	165:d1b4690b3f8b	493	)
AnnaBridge	165:d1b4690b3f8b	494	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	495	#define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
AnnaBridge	165:d1b4690b3f8b	496	#endif
AnnaBridge	165:d1b4690b3f8b	497
AnnaBridge	165:d1b4690b3f8b	498	/**
AnnaBridge	165:d1b4690b3f8b	499	* @brief Set the selected injected Channel rank.
AnnaBridge	165:d1b4690b3f8b	500	* @param __CHANNELNB__ Channel number.
AnnaBridge	165:d1b4690b3f8b	501	* @param __RANKNB__ Rank number.
AnnaBridge	165:d1b4690b3f8b	502	* @retval None
AnnaBridge	165:d1b4690b3f8b	503	*/
AnnaBridge	165:d1b4690b3f8b	504	#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
AnnaBridge	165:d1b4690b3f8b	505
AnnaBridge	165:d1b4690b3f8b	506	/**
AnnaBridge	165:d1b4690b3f8b	507	* @brief Configure ADC injected context queue
AnnaBridge	165:d1b4690b3f8b	508	* @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
AnnaBridge	165:d1b4690b3f8b	509	* @retval None
AnnaBridge	165:d1b4690b3f8b	510	*/
AnnaBridge	165:d1b4690b3f8b	511	#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
AnnaBridge	165:d1b4690b3f8b	512
AnnaBridge	165:d1b4690b3f8b	513	/**
AnnaBridge	165:d1b4690b3f8b	514	* @brief Configure ADC discontinuous conversion mode for injected group
AnnaBridge	165:d1b4690b3f8b	515	* @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
AnnaBridge	165:d1b4690b3f8b	516	* @retval None
AnnaBridge	165:d1b4690b3f8b	517	*/
AnnaBridge	165:d1b4690b3f8b	518	#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) << ADC_CFGR_JDISCEN_Pos)
AnnaBridge	165:d1b4690b3f8b	519
AnnaBridge	165:d1b4690b3f8b	520	/**
AnnaBridge	165:d1b4690b3f8b	521	* @brief Configure ADC discontinuous conversion mode for regular group
AnnaBridge	165:d1b4690b3f8b	522	* @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
AnnaBridge	165:d1b4690b3f8b	523	* @retval None
AnnaBridge	165:d1b4690b3f8b	524	*/
AnnaBridge	165:d1b4690b3f8b	525	#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
AnnaBridge	165:d1b4690b3f8b	526
AnnaBridge	165:d1b4690b3f8b	527	/**
AnnaBridge	165:d1b4690b3f8b	528	* @brief Configure the number of discontinuous conversions for regular group.
AnnaBridge	165:d1b4690b3f8b	529	* @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
AnnaBridge	165:d1b4690b3f8b	530	* @retval None
AnnaBridge	165:d1b4690b3f8b	531	*/
AnnaBridge	165:d1b4690b3f8b	532	#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1) << ADC_CFGR_DISCNUM_Pos)
AnnaBridge	165:d1b4690b3f8b	533
AnnaBridge	165:d1b4690b3f8b	534	/**
AnnaBridge	165:d1b4690b3f8b	535	* @brief Configure the ADC auto delay mode.
AnnaBridge	165:d1b4690b3f8b	536	* @param __AUTOWAIT__ Auto delay bit enable or disable.
AnnaBridge	165:d1b4690b3f8b	537	* @retval None
AnnaBridge	165:d1b4690b3f8b	538	*/
AnnaBridge	165:d1b4690b3f8b	539	#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
AnnaBridge	165:d1b4690b3f8b	540
AnnaBridge	165:d1b4690b3f8b	541	/**
AnnaBridge	165:d1b4690b3f8b	542	* @brief Configure ADC continuous conversion mode.
AnnaBridge	165:d1b4690b3f8b	543	* @param __CONTINUOUS_MODE__ Continuous mode.
AnnaBridge	165:d1b4690b3f8b	544	* @retval None
AnnaBridge	165:d1b4690b3f8b	545	*/
AnnaBridge	165:d1b4690b3f8b	546	#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
AnnaBridge	165:d1b4690b3f8b	547
AnnaBridge	165:d1b4690b3f8b	548	/**
AnnaBridge	165:d1b4690b3f8b	549	* @brief Configure the ADC DMA continuous request.
AnnaBridge	165:d1b4690b3f8b	550	* @param __DMACONTREQ_MODE__ DMA continuous request mode.
AnnaBridge	165:d1b4690b3f8b	551	* @retval None
AnnaBridge	165:d1b4690b3f8b	552	*/
AnnaBridge	165:d1b4690b3f8b	553	#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CFGR_DMACFG_Pos)
AnnaBridge	165:d1b4690b3f8b	554
AnnaBridge	165:d1b4690b3f8b	555	/**
AnnaBridge	165:d1b4690b3f8b	556	* @brief Configure the channel number into offset OFRx register.
AnnaBridge	165:d1b4690b3f8b	557	* @param __CHANNEL__ ADC Channel.
AnnaBridge	165:d1b4690b3f8b	558	* @retval None
AnnaBridge	165:d1b4690b3f8b	559	*/
AnnaBridge	165:d1b4690b3f8b	560	#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)
AnnaBridge	165:d1b4690b3f8b	561
AnnaBridge	165:d1b4690b3f8b	562	/**
AnnaBridge	165:d1b4690b3f8b	563	* @brief Configure the channel number into differential mode selection register.
AnnaBridge	165:d1b4690b3f8b	564	* @param __CHANNEL__ ADC Channel.
AnnaBridge	165:d1b4690b3f8b	565	* @retval None
AnnaBridge	165:d1b4690b3f8b	566	*/
AnnaBridge	165:d1b4690b3f8b	567	#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1U << (__CHANNEL__))
AnnaBridge	165:d1b4690b3f8b	568
AnnaBridge	165:d1b4690b3f8b	569	/**
AnnaBridge	165:d1b4690b3f8b	570	* @brief Configure calibration factor in differential mode to be set into calibration register.
AnnaBridge	165:d1b4690b3f8b	571	* @param __CALIBRATION_FACTOR__ Calibration factor value.
AnnaBridge	165:d1b4690b3f8b	572	* @retval None
AnnaBridge	165:d1b4690b3f8b	573	*/
AnnaBridge	165:d1b4690b3f8b	574	#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)
AnnaBridge	165:d1b4690b3f8b	575
AnnaBridge	165:d1b4690b3f8b	576	/**
AnnaBridge	165:d1b4690b3f8b	577	* @brief Calibration factor in differential mode to be retrieved from calibration register.
AnnaBridge	165:d1b4690b3f8b	578	* @param __CALIBRATION_FACTOR__ Calibration factor value.
AnnaBridge	165:d1b4690b3f8b	579	* @retval None
AnnaBridge	165:d1b4690b3f8b	580	*/
AnnaBridge	165:d1b4690b3f8b	581	#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)
AnnaBridge	165:d1b4690b3f8b	582
AnnaBridge	165:d1b4690b3f8b	583	/**
AnnaBridge	165:d1b4690b3f8b	584	* @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
AnnaBridge	165:d1b4690b3f8b	585	* @param __THRESHOLD__ Threshold value.
AnnaBridge	165:d1b4690b3f8b	586	* @retval None
AnnaBridge	165:d1b4690b3f8b	587	*/
AnnaBridge	165:d1b4690b3f8b	588	#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16)
AnnaBridge	165:d1b4690b3f8b	589
AnnaBridge	165:d1b4690b3f8b	590	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	591	/**
AnnaBridge	165:d1b4690b3f8b	592	* @brief Configure the ADC DMA continuous request for ADC multimode.
AnnaBridge	165:d1b4690b3f8b	593	* @param __DMACONTREQ_MODE__ DMA continuous request mode.
AnnaBridge	165:d1b4690b3f8b	594	* @retval None
AnnaBridge	165:d1b4690b3f8b	595	*/
AnnaBridge	165:d1b4690b3f8b	596	#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
AnnaBridge	165:d1b4690b3f8b	597	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	598	/**
AnnaBridge	165:d1b4690b3f8b	599	* @brief Enable the ADC peripheral.
AnnaBridge	165:d1b4690b3f8b	600	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	601	* @retval None
AnnaBridge	165:d1b4690b3f8b	602	*/
AnnaBridge	165:d1b4690b3f8b	603	#define ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR \|= ADC_CR_ADEN)
AnnaBridge	165:d1b4690b3f8b	604
AnnaBridge	165:d1b4690b3f8b	605	/**
AnnaBridge	165:d1b4690b3f8b	606	* @brief Verification of hardware constraints before ADC can be enabled.
AnnaBridge	165:d1b4690b3f8b	607	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	608	* @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
AnnaBridge	165:d1b4690b3f8b	609	*/
AnnaBridge	165:d1b4690b3f8b	610	#define ADC_ENABLING_CONDITIONS(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	611	(( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge	165:d1b4690b3f8b	612	(ADC_CR_ADCAL \| ADC_CR_JADSTP \| ADC_CR_ADSTP \| ADC_CR_JADSTART \| \
AnnaBridge	165:d1b4690b3f8b	613	ADC_CR_ADSTART \| ADC_CR_ADDIS \| ADC_CR_ADEN ) \
AnnaBridge	165:d1b4690b3f8b	614	) == RESET \
AnnaBridge	165:d1b4690b3f8b	615	) ? SET : RESET)
AnnaBridge	165:d1b4690b3f8b	616
AnnaBridge	165:d1b4690b3f8b	617	/**
AnnaBridge	165:d1b4690b3f8b	618	* @brief Disable the ADC peripheral.
AnnaBridge	165:d1b4690b3f8b	619	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	620	* @retval None
AnnaBridge	165:d1b4690b3f8b	621	*/
AnnaBridge	165:d1b4690b3f8b	622	#define ADC_DISABLE(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	623	do{ \
AnnaBridge	165:d1b4690b3f8b	624	(__HANDLE__)->Instance->CR \|= ADC_CR_ADDIS; \
AnnaBridge	165:d1b4690b3f8b	625	__HAL_ADC_CLEAR_FLAG((__HANDLE__), (ADC_FLAG_EOSMP \| ADC_FLAG_RDY)); \
AnnaBridge	165:d1b4690b3f8b	626	} while(0)
AnnaBridge	165:d1b4690b3f8b	627
AnnaBridge	165:d1b4690b3f8b	628	/**
AnnaBridge	165:d1b4690b3f8b	629	* @brief Verification of hardware constraints before ADC can be disabled.
AnnaBridge	165:d1b4690b3f8b	630	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	631	* @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
AnnaBridge	165:d1b4690b3f8b	632	*/
AnnaBridge	165:d1b4690b3f8b	633	#define ADC_DISABLING_CONDITIONS(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	634	(( ( ((__HANDLE__)->Instance->CR) & \
AnnaBridge	165:d1b4690b3f8b	635	(ADC_CR_JADSTART \| ADC_CR_ADSTART \| ADC_CR_ADEN)) == ADC_CR_ADEN \
AnnaBridge	165:d1b4690b3f8b	636	) ? SET : RESET)
AnnaBridge	165:d1b4690b3f8b	637
AnnaBridge	165:d1b4690b3f8b	638	/**
AnnaBridge	165:d1b4690b3f8b	639	* @brief Shift the offset with respect to the selected ADC resolution.
AnnaBridge	165:d1b4690b3f8b	640	* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
AnnaBridge	165:d1b4690b3f8b	641	* If resolution 12 bits, no shift.
AnnaBridge	165:d1b4690b3f8b	642	* If resolution 10 bits, shift of 2 ranks on the left.
AnnaBridge	165:d1b4690b3f8b	643	* If resolution 8 bits, shift of 4 ranks on the left.
AnnaBridge	165:d1b4690b3f8b	644	* If resolution 6 bits, shift of 6 ranks on the left.
AnnaBridge	165:d1b4690b3f8b	645	* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
AnnaBridge	165:d1b4690b3f8b	646	* @param __HANDLE__ ADC handle
AnnaBridge	165:d1b4690b3f8b	647	* @param __OFFSET__ Value to be shifted
AnnaBridge	165:d1b4690b3f8b	648	* @retval None
AnnaBridge	165:d1b4690b3f8b	649	*/
AnnaBridge	165:d1b4690b3f8b	650	#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
AnnaBridge	165:d1b4690b3f8b	651	((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
AnnaBridge	165:d1b4690b3f8b	652
AnnaBridge	165:d1b4690b3f8b	653
AnnaBridge	165:d1b4690b3f8b	654	/**
AnnaBridge	165:d1b4690b3f8b	655	* @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
AnnaBridge	165:d1b4690b3f8b	656	* @note Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
AnnaBridge	165:d1b4690b3f8b	657	* If resolution 12 bits, no shift.
AnnaBridge	165:d1b4690b3f8b	658	* If resolution 10 bits, shift of 2 ranks on the left.
AnnaBridge	165:d1b4690b3f8b	659	* If resolution 8 bits, shift of 4 ranks on the left.
AnnaBridge	165:d1b4690b3f8b	660	* If resolution 6 bits, shift of 6 ranks on the left.
AnnaBridge	165:d1b4690b3f8b	661	* Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
AnnaBridge	165:d1b4690b3f8b	662	* @param __HANDLE__ ADC handle
AnnaBridge	165:d1b4690b3f8b	663	* @param __THRESHOLD__ Value to be shifted
AnnaBridge	165:d1b4690b3f8b	664	* @retval None
AnnaBridge	165:d1b4690b3f8b	665	*/
AnnaBridge	165:d1b4690b3f8b	666	#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
AnnaBridge	165:d1b4690b3f8b	667	((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))
AnnaBridge	165:d1b4690b3f8b	668
AnnaBridge	165:d1b4690b3f8b	669	/**
AnnaBridge	165:d1b4690b3f8b	670	* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
AnnaBridge	165:d1b4690b3f8b	671	* @note Thresholds have to be left-aligned on bit 7.
AnnaBridge	165:d1b4690b3f8b	672	* If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
AnnaBridge	165:d1b4690b3f8b	673	* If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
AnnaBridge	165:d1b4690b3f8b	674	* If resolution 8 bits, no shift.
AnnaBridge	165:d1b4690b3f8b	675	* If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
AnnaBridge	165:d1b4690b3f8b	676	* @param __HANDLE__ ADC handle
AnnaBridge	165:d1b4690b3f8b	677	* @param __THRESHOLD__ Value to be shifted
AnnaBridge	165:d1b4690b3f8b	678	* @retval None
AnnaBridge	165:d1b4690b3f8b	679	*/
AnnaBridge	165:d1b4690b3f8b	680	#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
AnnaBridge	165:d1b4690b3f8b	681	( ((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 \| ADC_CFGR_RES_0) ? \
AnnaBridge	165:d1b4690b3f8b	682	((__THRESHOLD__) >> (4- ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3)*2))) : \
AnnaBridge	165:d1b4690b3f8b	683	(__THRESHOLD__) << 2 )
AnnaBridge	165:d1b4690b3f8b	684
AnnaBridge	165:d1b4690b3f8b	685	/**
AnnaBridge	165:d1b4690b3f8b	686	* @brief Report Master Instance.
AnnaBridge	165:d1b4690b3f8b	687	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	688	* @note Return same instance if ADC of input handle is independent ADC or if
AnnaBridge	165:d1b4690b3f8b	689	* multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	690	* @retval Master Instance
AnnaBridge	165:d1b4690b3f8b	691	*/
AnnaBridge	165:d1b4690b3f8b	692	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	693	#define ADC_MASTER_REGISTER(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	694	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3)) \
AnnaBridge	165:d1b4690b3f8b	695	)? \
AnnaBridge	165:d1b4690b3f8b	696	((__HANDLE__)->Instance) \
AnnaBridge	165:d1b4690b3f8b	697	: \
AnnaBridge	165:d1b4690b3f8b	698	(ADC1) \
AnnaBridge	165:d1b4690b3f8b	699	)
AnnaBridge	165:d1b4690b3f8b	700	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	701	#define ADC_MASTER_REGISTER(__HANDLE__) ((__HANDLE__)->Instance)
AnnaBridge	165:d1b4690b3f8b	702	#endif
AnnaBridge	165:d1b4690b3f8b	703
AnnaBridge	165:d1b4690b3f8b	704	/**
AnnaBridge	165:d1b4690b3f8b	705	* @brief Clear Common Control Register.
AnnaBridge	165:d1b4690b3f8b	706	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	707	* @retval None
AnnaBridge	165:d1b4690b3f8b	708	*/
AnnaBridge	165:d1b4690b3f8b	709	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	710	#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE \| \
AnnaBridge	165:d1b4690b3f8b	711	ADC_CCR_PRESC \| \
AnnaBridge	165:d1b4690b3f8b	712	ADC_CCR_VBATEN \| \
AnnaBridge	165:d1b4690b3f8b	713	ADC_CCR_TSEN \| \
AnnaBridge	165:d1b4690b3f8b	714	ADC_CCR_VREFEN \| \
AnnaBridge	165:d1b4690b3f8b	715	ADC_CCR_MDMA \| \
AnnaBridge	165:d1b4690b3f8b	716	ADC_CCR_DMACFG \| \
AnnaBridge	165:d1b4690b3f8b	717	ADC_CCR_DELAY \| \
AnnaBridge	165:d1b4690b3f8b	718	ADC_CCR_DUAL )
AnnaBridge	165:d1b4690b3f8b	719	#else
AnnaBridge	165:d1b4690b3f8b	720	#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE \| \
AnnaBridge	165:d1b4690b3f8b	721	ADC_CCR_PRESC \| \
AnnaBridge	165:d1b4690b3f8b	722	ADC_CCR_VBATEN \| \
AnnaBridge	165:d1b4690b3f8b	723	ADC_CCR_TSEN \| \
AnnaBridge	165:d1b4690b3f8b	724	ADC_CCR_VREFEN )
AnnaBridge	165:d1b4690b3f8b	725
AnnaBridge	165:d1b4690b3f8b	726	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	727
AnnaBridge	165:d1b4690b3f8b	728	/**
AnnaBridge	165:d1b4690b3f8b	729	* @brief Check whether or not dual conversions are enabled.
AnnaBridge	165:d1b4690b3f8b	730	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	731	* @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	732	* @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
AnnaBridge	165:d1b4690b3f8b	733	*/
AnnaBridge	165:d1b4690b3f8b	734	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	735	#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	736	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
AnnaBridge	165:d1b4690b3f8b	737	)? \
AnnaBridge	165:d1b4690b3f8b	738	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) ) \
AnnaBridge	165:d1b4690b3f8b	739	: \
AnnaBridge	165:d1b4690b3f8b	740	RESET \
AnnaBridge	165:d1b4690b3f8b	741	)
AnnaBridge	165:d1b4690b3f8b	742	#else
AnnaBridge	165:d1b4690b3f8b	743	#define ADC_IS_DUAL_CONVERSION_ENABLE(__HANDLE__) (RESET)
AnnaBridge	165:d1b4690b3f8b	744	#endif
AnnaBridge	165:d1b4690b3f8b	745
AnnaBridge	165:d1b4690b3f8b	746	/**
AnnaBridge	165:d1b4690b3f8b	747	* @brief Check whether or not dual regular conversions are enabled.
AnnaBridge	165:d1b4690b3f8b	748	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	749	* @note Return RESET if ADC of input handle is independent ADC or if multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	750	* @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)
AnnaBridge	165:d1b4690b3f8b	751	*/
AnnaBridge	165:d1b4690b3f8b	752	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	753	#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	754	( ( ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC2)) \
AnnaBridge	165:d1b4690b3f8b	755	)? \
AnnaBridge	165:d1b4690b3f8b	756	( (((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT) && \
AnnaBridge	165:d1b4690b3f8b	757	(((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) && \
AnnaBridge	165:d1b4690b3f8b	758	(((__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance))->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) ) \
AnnaBridge	165:d1b4690b3f8b	759	: \
AnnaBridge	165:d1b4690b3f8b	760	RESET \
AnnaBridge	165:d1b4690b3f8b	761	)
AnnaBridge	165:d1b4690b3f8b	762	#else
AnnaBridge	165:d1b4690b3f8b	763	#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__) (RESET)
AnnaBridge	165:d1b4690b3f8b	764	#endif
AnnaBridge	165:d1b4690b3f8b	765
AnnaBridge	165:d1b4690b3f8b	766	/**
AnnaBridge	165:d1b4690b3f8b	767	* @brief Verification of condition for ADC start conversion: ADC must be in non-multimode or multimode with handle of ADC master.
AnnaBridge	165:d1b4690b3f8b	768	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	769	* @note Return SET if multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	770	* @retval SET (non-multimode or Master handle) or RESET (handle of Slave ADC in multimode)
AnnaBridge	165:d1b4690b3f8b	771	*/
AnnaBridge	165:d1b4690b3f8b	772	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	773	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	774	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
AnnaBridge	165:d1b4690b3f8b	775	)? \
AnnaBridge	165:d1b4690b3f8b	776	SET \
AnnaBridge	165:d1b4690b3f8b	777	: \
AnnaBridge	165:d1b4690b3f8b	778	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == RESET) \
AnnaBridge	165:d1b4690b3f8b	779	)
AnnaBridge	165:d1b4690b3f8b	780	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	781	#define ADC_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__) (SET)
AnnaBridge	165:d1b4690b3f8b	782	#endif
AnnaBridge	165:d1b4690b3f8b	783
AnnaBridge	165:d1b4690b3f8b	784	/**
AnnaBridge	165:d1b4690b3f8b	785	* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled.
AnnaBridge	165:d1b4690b3f8b	786	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	787	* @note Return SET if multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	788	* @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)
AnnaBridge	165:d1b4690b3f8b	789	*/
AnnaBridge	165:d1b4690b3f8b	790	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	791	#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	792	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
AnnaBridge	165:d1b4690b3f8b	793	)? \
AnnaBridge	165:d1b4690b3f8b	794	SET \
AnnaBridge	165:d1b4690b3f8b	795	: \
AnnaBridge	165:d1b4690b3f8b	796	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	797	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) \|\| \
AnnaBridge	165:d1b4690b3f8b	798	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))
AnnaBridge	165:d1b4690b3f8b	799	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined( STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	800	#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__) (SET)
AnnaBridge	165:d1b4690b3f8b	801	#endif
AnnaBridge	165:d1b4690b3f8b	802
AnnaBridge	165:d1b4690b3f8b	803	/**
AnnaBridge	165:d1b4690b3f8b	804	* @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled.
AnnaBridge	165:d1b4690b3f8b	805	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	806	* @note Return SET if multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	807	* @retval SET (non-multimode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)
AnnaBridge	165:d1b4690b3f8b	808	*/
AnnaBridge	165:d1b4690b3f8b	809	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	810	#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	811	( ( ((__HANDLE__)->Instance == ADC1) \|\| ((__HANDLE__)->Instance == ADC3) \
AnnaBridge	165:d1b4690b3f8b	812	)? \
AnnaBridge	165:d1b4690b3f8b	813	SET \
AnnaBridge	165:d1b4690b3f8b	814	: \
AnnaBridge	165:d1b4690b3f8b	815	( ((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	816	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT) \|\| \
AnnaBridge	165:d1b4690b3f8b	817	((ADC123_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))
AnnaBridge	165:d1b4690b3f8b	818	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	819	#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__) (SET)
AnnaBridge	165:d1b4690b3f8b	820	#endif
AnnaBridge	165:d1b4690b3f8b	821
AnnaBridge	165:d1b4690b3f8b	822	/**
AnnaBridge	165:d1b4690b3f8b	823	* @brief Verification of ADC state: enabled or disabled, directly checked on instance as input parameter.
AnnaBridge	165:d1b4690b3f8b	824	* @param __INSTANCE__ ADC instance.
AnnaBridge	165:d1b4690b3f8b	825	* @retval SET (ADC enabled) or RESET (ADC disabled)
AnnaBridge	165:d1b4690b3f8b	826	*/
AnnaBridge	165:d1b4690b3f8b	827	#define ADC_INSTANCE_IS_ENABLED(__INSTANCE__) \
AnnaBridge	165:d1b4690b3f8b	828	(( ((((__INSTANCE__)->CR) & (ADC_CR_ADEN \| ADC_CR_ADDIS)) == ADC_CR_ADEN) && \
AnnaBridge	165:d1b4690b3f8b	829	((((__INSTANCE__)->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \
AnnaBridge	165:d1b4690b3f8b	830	) ? SET : RESET)
AnnaBridge	165:d1b4690b3f8b	831
AnnaBridge	165:d1b4690b3f8b	832	/**
AnnaBridge	165:d1b4690b3f8b	833	* @brief Verification of enabled/disabled status of ADCs other than that associated to the input parameter handle.
AnnaBridge	165:d1b4690b3f8b	834	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	835	* @retval SET (at least one other ADC is enabled) or RESET (no other ADC is enabled, all other ADCs are disabled)
AnnaBridge	165:d1b4690b3f8b	836	*/
AnnaBridge	165:d1b4690b3f8b	837	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	838	#define ADC_ANY_OTHER_ENABLED(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	839	( ( ((__HANDLE__)->Instance == ADC1) \
AnnaBridge	165:d1b4690b3f8b	840	)? \
AnnaBridge	165:d1b4690b3f8b	841	(ADC_INSTANCE_IS_ENABLED(ADC2)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC3)) \
AnnaBridge	165:d1b4690b3f8b	842	: \
AnnaBridge	165:d1b4690b3f8b	843	( ( ((__HANDLE__)->Instance == ADC2) \
AnnaBridge	165:d1b4690b3f8b	844	)? \
AnnaBridge	165:d1b4690b3f8b	845	(ADC_INSTANCE_IS_ENABLED(ADC1)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC3)) \
AnnaBridge	165:d1b4690b3f8b	846	: \
AnnaBridge	165:d1b4690b3f8b	847	ADC_INSTANCE_IS_ENABLED(ADC1)) \|\| (ADC_INSTANCE_IS_ENABLED(ADC2)) \
AnnaBridge	165:d1b4690b3f8b	848	)
AnnaBridge	165:d1b4690b3f8b	849	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	850	#define ADC_ANY_OTHER_ENABLED(__HANDLE__) (RESET)
AnnaBridge	165:d1b4690b3f8b	851	#endif
AnnaBridge	165:d1b4690b3f8b	852
AnnaBridge	165:d1b4690b3f8b	853	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	854	/**
AnnaBridge	165:d1b4690b3f8b	855	* @brief Set handle instance of the ADC slave associated to the ADC master.
AnnaBridge	165:d1b4690b3f8b	856	* @param __HANDLE_MASTER__ ADC master handle.
AnnaBridge	165:d1b4690b3f8b	857	* @param __HANDLE_SLAVE__ ADC slave handle.
AnnaBridge	165:d1b4690b3f8b	858	* @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.
AnnaBridge	165:d1b4690b3f8b	859	* @retval None
AnnaBridge	165:d1b4690b3f8b	860	*/
AnnaBridge	165:d1b4690b3f8b	861	#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__) \
AnnaBridge	165:d1b4690b3f8b	862	( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )
AnnaBridge	165:d1b4690b3f8b	863	#endif /* defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) */
AnnaBridge	165:d1b4690b3f8b	864
AnnaBridge	165:d1b4690b3f8b	865	/**
AnnaBridge	165:d1b4690b3f8b	866	* @brief Check whether or not multimode is configured in DMA mode.
AnnaBridge	165:d1b4690b3f8b	867	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	868	* @note Return RESET if multimode feature is not available.
AnnaBridge	165:d1b4690b3f8b	869	* @retval SET (multimode is configured in DMA mode) or RESET (DMA multimode is disabled)
AnnaBridge	165:d1b4690b3f8b	870	*/
AnnaBridge	165:d1b4690b3f8b	871	#if defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	872	#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) \
AnnaBridge	165:d1b4690b3f8b	873	((READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_12_10_BITS) \
AnnaBridge	165:d1b4690b3f8b	874	\|\| (READ_BIT(ADC123_COMMON->CCR, ADC_CCR_MDMA) == ADC_DMAACCESSMODE_8_6_BITS))
AnnaBridge	165:d1b4690b3f8b	875	#elif defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	876	#define ADC_MULTIMODE_DMA_ENABLED(__HANDLE__) (RESET)
AnnaBridge	165:d1b4690b3f8b	877	#endif
AnnaBridge	165:d1b4690b3f8b	878
AnnaBridge	165:d1b4690b3f8b	879	/**
AnnaBridge	165:d1b4690b3f8b	880	* @brief Verify the ADC instance connected to the temperature sensor.
AnnaBridge	165:d1b4690b3f8b	881	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	882	* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
AnnaBridge	165:d1b4690b3f8b	883	*/
AnnaBridge	165:d1b4690b3f8b	884	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	885	/* The temperature sensor measurement path (channel 17) is available on ADC1 */
AnnaBridge	165:d1b4690b3f8b	886	#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge	165:d1b4690b3f8b	887	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	888	/* The temperature sensor measurement path (channel 17) is available on ADC1 and ADC3 */
AnnaBridge	165:d1b4690b3f8b	889	#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3))
AnnaBridge	165:d1b4690b3f8b	890	#endif
AnnaBridge	165:d1b4690b3f8b	891
AnnaBridge	165:d1b4690b3f8b	892	/**
AnnaBridge	165:d1b4690b3f8b	893	* @brief Verify the ADC instance connected to the battery voltage VBAT.
AnnaBridge	165:d1b4690b3f8b	894	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	895	* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
AnnaBridge	165:d1b4690b3f8b	896	*/
AnnaBridge	165:d1b4690b3f8b	897	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	898	/* The battery voltage measurement path (channel 18) is available on ADC1 */
AnnaBridge	165:d1b4690b3f8b	899	#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge	165:d1b4690b3f8b	900	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	901	/* The battery voltage measurement path (channel 18) is available on ADC1 and ADC3 */
AnnaBridge	165:d1b4690b3f8b	902	#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) ((((__HANDLE__)->Instance) == ADC1) \|\| (((__HANDLE__)->Instance) == ADC3))
AnnaBridge	165:d1b4690b3f8b	903	#endif
AnnaBridge	165:d1b4690b3f8b	904
AnnaBridge	165:d1b4690b3f8b	905	/**
AnnaBridge	165:d1b4690b3f8b	906	* @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
AnnaBridge	165:d1b4690b3f8b	907	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	908	* @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
AnnaBridge	165:d1b4690b3f8b	909	*/
AnnaBridge	165:d1b4690b3f8b	910	/* The internal voltage reference VREFINT measurement path (channel 0) is available on ADC1 */
AnnaBridge	165:d1b4690b3f8b	911	#define ADC_VREFINT_INSTANCE(__HANDLE__) (((__HANDLE__)->Instance) == ADC1)
AnnaBridge	165:d1b4690b3f8b	912
AnnaBridge	165:d1b4690b3f8b	913	/**
AnnaBridge	165:d1b4690b3f8b	914	* @brief Verify the length of scheduled injected conversions group.
AnnaBridge	165:d1b4690b3f8b	915	* @param __LENGTH__ number of programmed conversions.
AnnaBridge	165:d1b4690b3f8b	916	* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
AnnaBridge	165:d1b4690b3f8b	917	*/
AnnaBridge	165:d1b4690b3f8b	918	#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
AnnaBridge	165:d1b4690b3f8b	919
AnnaBridge	165:d1b4690b3f8b	920	/**
AnnaBridge	165:d1b4690b3f8b	921	* @brief Calibration factor size verification (7 bits maximum).
AnnaBridge	165:d1b4690b3f8b	922	* @param __CALIBRATION_FACTOR__ Calibration factor value.
AnnaBridge	165:d1b4690b3f8b	923	* @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
AnnaBridge	165:d1b4690b3f8b	924	*/
AnnaBridge	165:d1b4690b3f8b	925	#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
AnnaBridge	165:d1b4690b3f8b	926
AnnaBridge	165:d1b4690b3f8b	927
AnnaBridge	165:d1b4690b3f8b	928	/**
AnnaBridge	165:d1b4690b3f8b	929	* @brief Verify the ADC channel setting.
AnnaBridge	165:d1b4690b3f8b	930	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	931	* @param __CHANNEL__ programmed ADC channel.
AnnaBridge	165:d1b4690b3f8b	932	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
AnnaBridge	165:d1b4690b3f8b	933	*/
AnnaBridge	165:d1b4690b3f8b	934	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	935	#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
AnnaBridge	165:d1b4690b3f8b	936	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	937	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	938	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	939	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
AnnaBridge	165:d1b4690b3f8b	940	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
AnnaBridge	165:d1b4690b3f8b	941	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	942	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	943	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	944	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	945	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	946	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	947	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
AnnaBridge	165:d1b4690b3f8b	948	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	949	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
AnnaBridge	165:d1b4690b3f8b	950	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
AnnaBridge	165:d1b4690b3f8b	951	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
AnnaBridge	165:d1b4690b3f8b	952	((__CHANNEL__) == ADC_CHANNEL_17) \|\| \
AnnaBridge	165:d1b4690b3f8b	953	((__CHANNEL__) == ADC_CHANNEL_18) \|\| \
AnnaBridge	165:d1b4690b3f8b	954	((__CHANNEL__) == ADC_CHANNEL_VREFINT) \|\| \
AnnaBridge	165:d1b4690b3f8b	955	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	165:d1b4690b3f8b	956	((__CHANNEL__) == ADC_CHANNEL_VBAT) \|\| \
AnnaBridge	165:d1b4690b3f8b	957	((__CHANNEL__) == ADC_CHANNEL_DAC1CH1) \|\| \
AnnaBridge	165:d1b4690b3f8b	958	((__CHANNEL__) == ADC_CHANNEL_DAC1CH2)))
AnnaBridge	165:d1b4690b3f8b	959	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	960	#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) (((((__HANDLE__)->Instance) == ADC1) && \
AnnaBridge	165:d1b4690b3f8b	961	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	962	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	963	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	964	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
AnnaBridge	165:d1b4690b3f8b	965	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
AnnaBridge	165:d1b4690b3f8b	966	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	967	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	968	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	969	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	970	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	971	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	972	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
AnnaBridge	165:d1b4690b3f8b	973	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	974	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
AnnaBridge	165:d1b4690b3f8b	975	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
AnnaBridge	165:d1b4690b3f8b	976	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
AnnaBridge	165:d1b4690b3f8b	977	((__CHANNEL__) == ADC_CHANNEL_VREFINT) \|\| \
AnnaBridge	165:d1b4690b3f8b	978	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	165:d1b4690b3f8b	979	((__CHANNEL__) == ADC_CHANNEL_VBAT))) \|\| \
AnnaBridge	165:d1b4690b3f8b	980	((((__HANDLE__)->Instance) == ADC2) && \
AnnaBridge	165:d1b4690b3f8b	981	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	982	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	983	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	984	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
AnnaBridge	165:d1b4690b3f8b	985	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
AnnaBridge	165:d1b4690b3f8b	986	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	987	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	988	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	989	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	990	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	991	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	992	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
AnnaBridge	165:d1b4690b3f8b	993	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	994	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
AnnaBridge	165:d1b4690b3f8b	995	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
AnnaBridge	165:d1b4690b3f8b	996	((__CHANNEL__) == ADC_CHANNEL_16) \|\| \
AnnaBridge	165:d1b4690b3f8b	997	((__CHANNEL__) == ADC_CHANNEL_17) \|\| \
AnnaBridge	165:d1b4690b3f8b	998	((__CHANNEL__) == ADC_CHANNEL_18) \|\| \
AnnaBridge	165:d1b4690b3f8b	999	((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1000	((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2))) \|\| \
AnnaBridge	165:d1b4690b3f8b	1001	((((__HANDLE__)->Instance) == ADC3) && \
AnnaBridge	165:d1b4690b3f8b	1002	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1003	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1004	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1005	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
AnnaBridge	165:d1b4690b3f8b	1006	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	1007	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	1008	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	1009	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	1010	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	1011	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	1012	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
AnnaBridge	165:d1b4690b3f8b	1013	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	1014	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
AnnaBridge	165:d1b4690b3f8b	1015	((__CHANNEL__) == ADC_CHANNEL_15) \|\| \
AnnaBridge	165:d1b4690b3f8b	1016	((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR) \|\| \
AnnaBridge	165:d1b4690b3f8b	1017	((__CHANNEL__) == ADC_CHANNEL_VBAT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1018	((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1019	((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC3) )))
AnnaBridge	165:d1b4690b3f8b	1020	#endif
AnnaBridge	165:d1b4690b3f8b	1021
AnnaBridge	165:d1b4690b3f8b	1022	/**
AnnaBridge	165:d1b4690b3f8b	1023	* @brief Verify the ADC channel setting in differential mode.
AnnaBridge	165:d1b4690b3f8b	1024	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	1025	* @param __CHANNEL__ programmed ADC channel.
AnnaBridge	165:d1b4690b3f8b	1026	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1027	*/
AnnaBridge	165:d1b4690b3f8b	1028	#if defined (STM32L431xx) \|\| defined (STM32L432xx) \|\| defined (STM32L433xx) \|\| defined (STM32L442xx) \|\| defined (STM32L443xx) \|\| defined (STM32L451xx) \|\| defined (STM32L452xx) \|\| defined (STM32L462xx) \|\| defined (STM32L4R5xx) \|\| defined (STM32L4R7xx) \|\| defined (STM32L4R9xx) \|\| defined (STM32L4S5xx) \|\| defined (STM32L4S7xx) \|\| defined (STM32L4S9xx)
AnnaBridge	165:d1b4690b3f8b	1029	#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1030	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1031	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1032	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
AnnaBridge	165:d1b4690b3f8b	1033	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
AnnaBridge	165:d1b4690b3f8b	1034	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	1035	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	1036	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	1037	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	1038	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	1039	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	1040	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
AnnaBridge	165:d1b4690b3f8b	1041	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	1042	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
AnnaBridge	165:d1b4690b3f8b	1043	((__CHANNEL__) == ADC_CHANNEL_15) )
AnnaBridge	165:d1b4690b3f8b	1044	#elif defined (STM32L471xx) \|\| defined (STM32L475xx) \|\| defined (STM32L476xx) \|\| defined (STM32L485xx) \|\| defined (STM32L486xx) \|\| defined (STM32L496xx) \|\| defined (STM32L4A6xx)
AnnaBridge	165:d1b4690b3f8b	1045	/* For ADC1 and ADC2, channels 1 to 15 are available in differential mode,
AnnaBridge	165:d1b4690b3f8b	1046	channels 0, 16 to 18 can be only used in single-ended mode.
AnnaBridge	165:d1b4690b3f8b	1047	For ADC3, channels 1 to 3 and 6 to 12 are available in differential mode,
AnnaBridge	165:d1b4690b3f8b	1048	channels 4, 5 and 13 to 18 can only be used in single-ended mode. */
AnnaBridge	165:d1b4690b3f8b	1049	#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) ((((((__HANDLE__)->Instance) == ADC1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1050	(((__HANDLE__)->Instance) == ADC2)) && \
AnnaBridge	165:d1b4690b3f8b	1051	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1052	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1053	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1054	((__CHANNEL__) == ADC_CHANNEL_4) \|\| \
AnnaBridge	165:d1b4690b3f8b	1055	((__CHANNEL__) == ADC_CHANNEL_5) \|\| \
AnnaBridge	165:d1b4690b3f8b	1056	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	1057	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	1058	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	1059	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	1060	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	1061	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	1062	((__CHANNEL__) == ADC_CHANNEL_12) \|\| \
AnnaBridge	165:d1b4690b3f8b	1063	((__CHANNEL__) == ADC_CHANNEL_13) \|\| \
AnnaBridge	165:d1b4690b3f8b	1064	((__CHANNEL__) == ADC_CHANNEL_14) \|\| \
AnnaBridge	165:d1b4690b3f8b	1065	((__CHANNEL__) == ADC_CHANNEL_15))) \|\| \
AnnaBridge	165:d1b4690b3f8b	1066	((((__HANDLE__)->Instance) == ADC3) && \
AnnaBridge	165:d1b4690b3f8b	1067	(((__CHANNEL__) == ADC_CHANNEL_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1068	((__CHANNEL__) == ADC_CHANNEL_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1069	((__CHANNEL__) == ADC_CHANNEL_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1070	((__CHANNEL__) == ADC_CHANNEL_6) \|\| \
AnnaBridge	165:d1b4690b3f8b	1071	((__CHANNEL__) == ADC_CHANNEL_7) \|\| \
AnnaBridge	165:d1b4690b3f8b	1072	((__CHANNEL__) == ADC_CHANNEL_8) \|\| \
AnnaBridge	165:d1b4690b3f8b	1073	((__CHANNEL__) == ADC_CHANNEL_9) \|\| \
AnnaBridge	165:d1b4690b3f8b	1074	((__CHANNEL__) == ADC_CHANNEL_10) \|\| \
AnnaBridge	165:d1b4690b3f8b	1075	((__CHANNEL__) == ADC_CHANNEL_11) \|\| \
AnnaBridge	165:d1b4690b3f8b	1076	((__CHANNEL__) == ADC_CHANNEL_12) )))
AnnaBridge	165:d1b4690b3f8b	1077	#endif
AnnaBridge	165:d1b4690b3f8b	1078
AnnaBridge	165:d1b4690b3f8b	1079	/**
AnnaBridge	165:d1b4690b3f8b	1080	* @brief Verify the ADC single-ended input or differential mode setting.
AnnaBridge	165:d1b4690b3f8b	1081	* @param __SING_DIFF__ programmed channel setting.
AnnaBridge	165:d1b4690b3f8b	1082	* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1083	*/
AnnaBridge	165:d1b4690b3f8b	1084	#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) \|\| \
AnnaBridge	165:d1b4690b3f8b	1085	((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED) )
AnnaBridge	165:d1b4690b3f8b	1086
AnnaBridge	165:d1b4690b3f8b	1087	/**
AnnaBridge	165:d1b4690b3f8b	1088	* @brief Verify the ADC offset management setting.
AnnaBridge	165:d1b4690b3f8b	1089	* @param __OFFSET_NUMBER__ ADC offset management.
AnnaBridge	165:d1b4690b3f8b	1090	* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1091	*/
AnnaBridge	165:d1b4690b3f8b	1092	#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1093	((__OFFSET_NUMBER__) == ADC_OFFSET_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1094	((__OFFSET_NUMBER__) == ADC_OFFSET_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1095	((__OFFSET_NUMBER__) == ADC_OFFSET_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1096	((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
AnnaBridge	165:d1b4690b3f8b	1097
AnnaBridge	165:d1b4690b3f8b	1098	/**
AnnaBridge	165:d1b4690b3f8b	1099	* @brief Verify the ADC injected channel setting.
AnnaBridge	165:d1b4690b3f8b	1100	* @param __CHANNEL__ programmed ADC injected channel.
AnnaBridge	165:d1b4690b3f8b	1101	* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1102	*/
AnnaBridge	165:d1b4690b3f8b	1103	#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1104	((__CHANNEL__) == ADC_INJECTED_RANK_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1105	((__CHANNEL__) == ADC_INJECTED_RANK_3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1106	((__CHANNEL__) == ADC_INJECTED_RANK_4) )
AnnaBridge	165:d1b4690b3f8b	1107
AnnaBridge	165:d1b4690b3f8b	1108	/**
AnnaBridge	165:d1b4690b3f8b	1109	* @brief Verify the ADC injected conversions external trigger.
AnnaBridge	165:d1b4690b3f8b	1110	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	1111	* @param __INJTRIG__ programmed ADC injected conversions external trigger.
AnnaBridge	165:d1b4690b3f8b	1112	* @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1113	*/
AnnaBridge	165:d1b4690b3f8b	1114	#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1115	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4) \|\| \
AnnaBridge	165:d1b4690b3f8b	1116	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1117	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1118	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4) \|\| \
AnnaBridge	165:d1b4690b3f8b	1119	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1120	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15) \|\| \
AnnaBridge	165:d1b4690b3f8b	1121	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4) \|\| \
AnnaBridge	165:d1b4690b3f8b	1122	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1123	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1124	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1125	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3) \|\| \
AnnaBridge	165:d1b4690b3f8b	1126	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1127	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1128	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1129	((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO) \|\| \
AnnaBridge	165:d1b4690b3f8b	1130	((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START) )
AnnaBridge	165:d1b4690b3f8b	1131
AnnaBridge	165:d1b4690b3f8b	1132	/**
AnnaBridge	165:d1b4690b3f8b	1133	* @brief Verify the ADC edge trigger setting for injected group.
AnnaBridge	165:d1b4690b3f8b	1134	* @param __EDGE__ programmed ADC edge trigger setting.
AnnaBridge	165:d1b4690b3f8b	1135	* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1136	*/
AnnaBridge	165:d1b4690b3f8b	1137	#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1138	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) \|\| \
AnnaBridge	165:d1b4690b3f8b	1139	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) \|\| \
AnnaBridge	165:d1b4690b3f8b	1140	((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
AnnaBridge	165:d1b4690b3f8b	1141
AnnaBridge	165:d1b4690b3f8b	1142	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1143	/**
AnnaBridge	165:d1b4690b3f8b	1144	* @brief Verify the ADC multimode setting.
AnnaBridge	165:d1b4690b3f8b	1145	* @param __MODE__ programmed ADC multimode setting.
AnnaBridge	165:d1b4690b3f8b	1146	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1147	*/
AnnaBridge	165:d1b4690b3f8b	1148	#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1149	((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1150	((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) \|\| \
AnnaBridge	165:d1b4690b3f8b	1151	((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1152	((__MODE__) == ADC_DUALMODE_INJECSIMULT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1153	((__MODE__) == ADC_DUALMODE_REGSIMULT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1154	((__MODE__) == ADC_DUALMODE_INTERL) \|\| \
AnnaBridge	165:d1b4690b3f8b	1155	((__MODE__) == ADC_DUALMODE_ALTERTRIG) )
AnnaBridge	165:d1b4690b3f8b	1156
AnnaBridge	165:d1b4690b3f8b	1157	/**
AnnaBridge	165:d1b4690b3f8b	1158	* @brief Verify the ADC multimode DMA access setting.
AnnaBridge	165:d1b4690b3f8b	1159	* @param __MODE__ programmed ADC multimode DMA access setting.
AnnaBridge	165:d1b4690b3f8b	1160	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1161	*/
AnnaBridge	165:d1b4690b3f8b	1162	#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED) \|\| \
AnnaBridge	165:d1b4690b3f8b	1163	((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) \|\| \
AnnaBridge	165:d1b4690b3f8b	1164	((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS) )
AnnaBridge	165:d1b4690b3f8b	1165
AnnaBridge	165:d1b4690b3f8b	1166	/**
AnnaBridge	165:d1b4690b3f8b	1167	* @brief Verify the ADC multimode delay setting.
AnnaBridge	165:d1b4690b3f8b	1168	* @param __DELAY__ programmed ADC multimode delay setting.
AnnaBridge	165:d1b4690b3f8b	1169	* @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1170	*/
AnnaBridge	165:d1b4690b3f8b	1171	#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1172	((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1173	((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1174	((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1175	((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1176	((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1177	((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1178	((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1179	((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1180	((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1181	((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) \|\| \
AnnaBridge	165:d1b4690b3f8b	1182	((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) )
AnnaBridge	165:d1b4690b3f8b	1183	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1184
AnnaBridge	165:d1b4690b3f8b	1185	/**
AnnaBridge	165:d1b4690b3f8b	1186	* @brief Verify the ADC analog watchdog setting.
AnnaBridge	165:d1b4690b3f8b	1187	* @param __WATCHDOG__ programmed ADC analog watchdog setting.
AnnaBridge	165:d1b4690b3f8b	1188	* @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1189	*/
AnnaBridge	165:d1b4690b3f8b	1190	#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) \|\| \
AnnaBridge	165:d1b4690b3f8b	1191	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) \|\| \
AnnaBridge	165:d1b4690b3f8b	1192	((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
AnnaBridge	165:d1b4690b3f8b	1193
AnnaBridge	165:d1b4690b3f8b	1194	/**
AnnaBridge	165:d1b4690b3f8b	1195	* @brief Verify the ADC analog watchdog mode setting.
AnnaBridge	165:d1b4690b3f8b	1196	* @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
AnnaBridge	165:d1b4690b3f8b	1197	* @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1198	*/
AnnaBridge	165:d1b4690b3f8b	1199	#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1200	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG) \|\| \
AnnaBridge	165:d1b4690b3f8b	1201	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) \|\| \
AnnaBridge	165:d1b4690b3f8b	1202	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) \|\| \
AnnaBridge	165:d1b4690b3f8b	1203	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) \|\| \
AnnaBridge	165:d1b4690b3f8b	1204	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) \|\| \
AnnaBridge	165:d1b4690b3f8b	1205	((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
AnnaBridge	165:d1b4690b3f8b	1206
AnnaBridge	165:d1b4690b3f8b	1207	/**
AnnaBridge	165:d1b4690b3f8b	1208	* @brief Verify the ADC conversion (regular or injected or both).
AnnaBridge	165:d1b4690b3f8b	1209	* @param __CONVERSION__ ADC conversion group.
AnnaBridge	165:d1b4690b3f8b	1210	* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1211	*/
AnnaBridge	165:d1b4690b3f8b	1212	#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) \|\| \
AnnaBridge	165:d1b4690b3f8b	1213	((__CONVERSION__) == ADC_INJECTED_GROUP) \|\| \
AnnaBridge	165:d1b4690b3f8b	1214	((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
AnnaBridge	165:d1b4690b3f8b	1215
AnnaBridge	165:d1b4690b3f8b	1216	/**
AnnaBridge	165:d1b4690b3f8b	1217	* @brief Verify the ADC event type.
AnnaBridge	165:d1b4690b3f8b	1218	* @param __EVENT__ ADC event.
AnnaBridge	165:d1b4690b3f8b	1219	* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1220	*/
AnnaBridge	165:d1b4690b3f8b	1221	#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1222	((__EVENT__) == ADC_AWD_EVENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1223	((__EVENT__) == ADC_AWD2_EVENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1224	((__EVENT__) == ADC_AWD3_EVENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1225	((__EVENT__) == ADC_OVR_EVENT) \|\| \
AnnaBridge	165:d1b4690b3f8b	1226	((__EVENT__) == ADC_JQOVF_EVENT) )
AnnaBridge	165:d1b4690b3f8b	1227
AnnaBridge	165:d1b4690b3f8b	1228	/**
AnnaBridge	165:d1b4690b3f8b	1229	* @brief Verify the ADC oversampling ratio.
AnnaBridge	165:d1b4690b3f8b	1230	* @param __RATIO__ programmed ADC oversampling ratio.
AnnaBridge	165:d1b4690b3f8b	1231	* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1232	*/
AnnaBridge	165:d1b4690b3f8b	1233	#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1234	((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1235	((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1236	((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1237	((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1238	((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1239	((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1240	((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
AnnaBridge	165:d1b4690b3f8b	1241
AnnaBridge	165:d1b4690b3f8b	1242	/**
AnnaBridge	165:d1b4690b3f8b	1243	* @brief Verify the ADC oversampling shift.
AnnaBridge	165:d1b4690b3f8b	1244	* @param __SHIFT__ programmed ADC oversampling shift.
AnnaBridge	165:d1b4690b3f8b	1245	* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1246	*/
AnnaBridge	165:d1b4690b3f8b	1247	#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1248	((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1249	((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1250	((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1251	((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1252	((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1253	((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1254	((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) \|\| \
AnnaBridge	165:d1b4690b3f8b	1255	((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
AnnaBridge	165:d1b4690b3f8b	1256
AnnaBridge	165:d1b4690b3f8b	1257	/**
AnnaBridge	165:d1b4690b3f8b	1258	* @brief Verify the ADC oversampling triggered mode.
AnnaBridge	165:d1b4690b3f8b	1259	* @param __MODE__ programmed ADC oversampling triggered mode.
AnnaBridge	165:d1b4690b3f8b	1260	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1261	*/
AnnaBridge	165:d1b4690b3f8b	1262	#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) \|\| \
AnnaBridge	165:d1b4690b3f8b	1263	((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
AnnaBridge	165:d1b4690b3f8b	1264
AnnaBridge	165:d1b4690b3f8b	1265	/**
AnnaBridge	165:d1b4690b3f8b	1266	* @brief Verify the ADC oversampling regular conversion resumed or continued mode.
AnnaBridge	165:d1b4690b3f8b	1267	* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
AnnaBridge	165:d1b4690b3f8b	1268	* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
AnnaBridge	165:d1b4690b3f8b	1269	*/
AnnaBridge	165:d1b4690b3f8b	1270	#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1271	((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
AnnaBridge	165:d1b4690b3f8b	1272
AnnaBridge	165:d1b4690b3f8b	1273	/**
AnnaBridge	165:d1b4690b3f8b	1274	* @brief Verify the DFSDM mode configuration.
AnnaBridge	165:d1b4690b3f8b	1275	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	1276	* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
AnnaBridge	165:d1b4690b3f8b	1277	* this reason, the input parameter is the ADC handle and not the configuration parameter
AnnaBridge	165:d1b4690b3f8b	1278	* directly.
AnnaBridge	165:d1b4690b3f8b	1279	* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
AnnaBridge	165:d1b4690b3f8b	1280	*/
AnnaBridge	165:d1b4690b3f8b	1281	#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	1282	#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) \|\| \
AnnaBridge	165:d1b4690b3f8b	1283	((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )
AnnaBridge	165:d1b4690b3f8b	1284	#else
AnnaBridge	165:d1b4690b3f8b	1285	#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
AnnaBridge	165:d1b4690b3f8b	1286	#endif
AnnaBridge	165:d1b4690b3f8b	1287
AnnaBridge	165:d1b4690b3f8b	1288	/**
AnnaBridge	165:d1b4690b3f8b	1289	* @brief Return the DFSDM configuration mode.
AnnaBridge	165:d1b4690b3f8b	1290	* @param __HANDLE__ ADC handle.
AnnaBridge	165:d1b4690b3f8b	1291	* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
AnnaBridge	165:d1b4690b3f8b	1292	* For this reason, the input parameter is the ADC handle and not the configuration parameter
AnnaBridge	165:d1b4690b3f8b	1293	* directly.
AnnaBridge	165:d1b4690b3f8b	1294	* @retval DFSDM configuration mode
AnnaBridge	165:d1b4690b3f8b	1295	*/
AnnaBridge	165:d1b4690b3f8b	1296	#if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0)
AnnaBridge	165:d1b4690b3f8b	1297	#define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)
AnnaBridge	165:d1b4690b3f8b	1298	#else
AnnaBridge	165:d1b4690b3f8b	1299	#define ADC_CFGR_DFSDM(__HANDLE__) (0x0)
AnnaBridge	165:d1b4690b3f8b	1300	#endif
AnnaBridge	165:d1b4690b3f8b	1301
AnnaBridge	165:d1b4690b3f8b	1302	/**
AnnaBridge	165:d1b4690b3f8b	1303	* @}
AnnaBridge	165:d1b4690b3f8b	1304	*/
AnnaBridge	165:d1b4690b3f8b	1305
AnnaBridge	165:d1b4690b3f8b	1306
AnnaBridge	165:d1b4690b3f8b	1307	/* Exported functions --------------------------------------------------------*/
AnnaBridge	165:d1b4690b3f8b	1308	/** @addtogroup ADCEx_Exported_Functions
AnnaBridge	165:d1b4690b3f8b	1309	* @{
AnnaBridge	165:d1b4690b3f8b	1310	*/
AnnaBridge	165:d1b4690b3f8b	1311
AnnaBridge	165:d1b4690b3f8b	1312	/** @addtogroup ADCEx_Exported_Functions_Group1
AnnaBridge	165:d1b4690b3f8b	1313	* @{
AnnaBridge	165:d1b4690b3f8b	1314	*/
AnnaBridge	165:d1b4690b3f8b	1315	/* IO operation functions *****************************************************/
AnnaBridge	165:d1b4690b3f8b	1316
AnnaBridge	165:d1b4690b3f8b	1317	/* ADC calibration */
AnnaBridge	165:d1b4690b3f8b	1318	HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff);
AnnaBridge	165:d1b4690b3f8b	1319	uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
AnnaBridge	165:d1b4690b3f8b	1320	HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);
AnnaBridge	165:d1b4690b3f8b	1321
AnnaBridge	165:d1b4690b3f8b	1322	/* Blocking mode: Polling */
AnnaBridge	165:d1b4690b3f8b	1323	HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1324	HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1325	HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
AnnaBridge	165:d1b4690b3f8b	1326
AnnaBridge	165:d1b4690b3f8b	1327	/* Non-blocking mode: Interruption */
AnnaBridge	165:d1b4690b3f8b	1328	HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1329	HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1330
AnnaBridge	165:d1b4690b3f8b	1331	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1332	/* ADC multimode */
AnnaBridge	165:d1b4690b3f8b	1333	HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef hadc, uint32_t pData, uint32_t Length);
AnnaBridge	165:d1b4690b3f8b	1334	HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
AnnaBridge	165:d1b4690b3f8b	1335	uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);
AnnaBridge	165:d1b4690b3f8b	1336	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1337
AnnaBridge	165:d1b4690b3f8b	1338	/* ADC retrieve conversion value intended to be used with polling or interruption */
AnnaBridge	165:d1b4690b3f8b	1339	uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
AnnaBridge	165:d1b4690b3f8b	1340
AnnaBridge	165:d1b4690b3f8b	1341	/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
AnnaBridge	165:d1b4690b3f8b	1342	void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1343	void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1344	void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1345	void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1346	void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1347
AnnaBridge	165:d1b4690b3f8b	1348	/* ADC group regular conversions stop */
AnnaBridge	165:d1b4690b3f8b	1349	HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1350	HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1351	HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1352	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1353	HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1354	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1355
AnnaBridge	165:d1b4690b3f8b	1356	/**
AnnaBridge	165:d1b4690b3f8b	1357	* @}
AnnaBridge	165:d1b4690b3f8b	1358	*/
AnnaBridge	165:d1b4690b3f8b	1359
AnnaBridge	165:d1b4690b3f8b	1360	/** @addtogroup ADCEx_Exported_Functions_Group2
AnnaBridge	165:d1b4690b3f8b	1361	* @{
AnnaBridge	165:d1b4690b3f8b	1362	*/
AnnaBridge	165:d1b4690b3f8b	1363	/* Peripheral Control functions ***********************************************/
AnnaBridge	165:d1b4690b3f8b	1364	HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
AnnaBridge	165:d1b4690b3f8b	1365	#if defined(ADC_MULTIMODE_SUPPORT)
AnnaBridge	165:d1b4690b3f8b	1366	HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef hadc, ADC_MultiModeTypeDef multimode);
AnnaBridge	165:d1b4690b3f8b	1367	#endif /* ADC_MULTIMODE_SUPPORT */
AnnaBridge	165:d1b4690b3f8b	1368	HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1369	HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1370	HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1371	HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc);
AnnaBridge	165:d1b4690b3f8b	1372
AnnaBridge	165:d1b4690b3f8b	1373	/**
AnnaBridge	165:d1b4690b3f8b	1374	* @}
AnnaBridge	165:d1b4690b3f8b	1375	*/
AnnaBridge	165:d1b4690b3f8b	1376
AnnaBridge	165:d1b4690b3f8b	1377	/**
AnnaBridge	165:d1b4690b3f8b	1378	* @}
AnnaBridge	165:d1b4690b3f8b	1379	*/
AnnaBridge	165:d1b4690b3f8b	1380
AnnaBridge	165:d1b4690b3f8b	1381	/**
AnnaBridge	165:d1b4690b3f8b	1382	* @}
AnnaBridge	165:d1b4690b3f8b	1383	*/
AnnaBridge	165:d1b4690b3f8b	1384
AnnaBridge	165:d1b4690b3f8b	1385	/**
AnnaBridge	165:d1b4690b3f8b	1386	* @}
AnnaBridge	165:d1b4690b3f8b	1387	*/
AnnaBridge	165:d1b4690b3f8b	1388
AnnaBridge	165:d1b4690b3f8b	1389	#ifdef __cplusplus
AnnaBridge	165:d1b4690b3f8b	1390	}
AnnaBridge	165:d1b4690b3f8b	1391	#endif
AnnaBridge	165:d1b4690b3f8b	1392
AnnaBridge	165:d1b4690b3f8b	1393	#endif /* __STM32L4xx_HAL_ADC_EX_H */
AnnaBridge	165:d1b4690b3f8b	1394
AnnaBridge	165:d1b4690b3f8b	1395
AnnaBridge	165:d1b4690b3f8b	1396	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/