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TARGET_NUCLEO_L496ZG_P/TOOLCHAIN_ARM_STD/stm32l4xx_ll_bus.h@171:3a7713b1edbc, 2018-11-08 (annotated)

Committer:: AnnaBridge
Date:: Thu Nov 08 11:45:42 2018 +0000
Revision:: 171:3a7713b1edbc
Parent:: TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h@161:aa5281ff4a02

mbed library. Release version 164

Who changed what in which revision?

User	Revision	Line number	New contents of line
AnnaBridge	145:64910690c574	1	/**
AnnaBridge	145:64910690c574	2	******************************************************************************
AnnaBridge	145:64910690c574	3	* @file stm32l4xx_ll_bus.h
AnnaBridge	145:64910690c574	4	* @author MCD Application Team
AnnaBridge	145:64910690c574	5	* @brief Header file of BUS LL module.
AnnaBridge	145:64910690c574	6
AnnaBridge	145:64910690c574	7	@verbatim
AnnaBridge	145:64910690c574	8	##### RCC Limitations #####
AnnaBridge	145:64910690c574	9	==============================================================================
AnnaBridge	145:64910690c574	10	[..]
AnnaBridge	145:64910690c574	11	A delay between an RCC peripheral clock enable and the effective peripheral
AnnaBridge	145:64910690c574	12	enabling should be taken into account in order to manage the peripheral read/write
AnnaBridge	145:64910690c574	13	from/to registers.
AnnaBridge	145:64910690c574	14	(+) This delay depends on the peripheral mapping.
AnnaBridge	145:64910690c574	15	(++) AHB & APB peripherals, 1 dummy read is necessary
AnnaBridge	145:64910690c574	16
AnnaBridge	145:64910690c574	17	[..]
AnnaBridge	145:64910690c574	18	Workarounds:
AnnaBridge	145:64910690c574	19	(#) For AHB & APB peripherals, a dummy read to the peripheral register has been
AnnaBridge	145:64910690c574	20	inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
AnnaBridge	145:64910690c574	21
AnnaBridge	145:64910690c574	22	@endverbatim
AnnaBridge	145:64910690c574	23	******************************************************************************
AnnaBridge	145:64910690c574	24	* @attention
AnnaBridge	145:64910690c574	25	*
AnnaBridge	145:64910690c574	26	* <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
AnnaBridge	145:64910690c574	27	*
AnnaBridge	145:64910690c574	28	* Redistribution and use in source and binary forms, with or without modification,
AnnaBridge	145:64910690c574	29	* are permitted provided that the following conditions are met:
AnnaBridge	145:64910690c574	30	* 1. Redistributions of source code must retain the above copyright notice,
AnnaBridge	145:64910690c574	31	* this list of conditions and the following disclaimer.
AnnaBridge	145:64910690c574	32	* 2. Redistributions in binary form must reproduce the above copyright notice,
AnnaBridge	145:64910690c574	33	* this list of conditions and the following disclaimer in the documentation
AnnaBridge	145:64910690c574	34	* and/or other materials provided with the distribution.
AnnaBridge	145:64910690c574	35	* 3. Neither the name of STMicroelectronics nor the names of its contributors
AnnaBridge	145:64910690c574	36	* may be used to endorse or promote products derived from this software
AnnaBridge	145:64910690c574	37	* without specific prior written permission.
AnnaBridge	145:64910690c574	38	*
AnnaBridge	145:64910690c574	39	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AnnaBridge	145:64910690c574	40	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
AnnaBridge	145:64910690c574	41	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge	145:64910690c574	42	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
AnnaBridge	145:64910690c574	43	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
AnnaBridge	145:64910690c574	44	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
AnnaBridge	145:64910690c574	45	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
AnnaBridge	145:64910690c574	46	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
AnnaBridge	145:64910690c574	47	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
AnnaBridge	145:64910690c574	48	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge	145:64910690c574	49	*
AnnaBridge	145:64910690c574	50	******************************************************************************
AnnaBridge	145:64910690c574	51	*/
AnnaBridge	145:64910690c574	52
AnnaBridge	145:64910690c574	53	/* Define to prevent recursive inclusion -------------------------------------*/
AnnaBridge	145:64910690c574	54	#ifndef __STM32L4xx_LL_BUS_H
AnnaBridge	145:64910690c574	55	#define __STM32L4xx_LL_BUS_H
AnnaBridge	145:64910690c574	56
AnnaBridge	145:64910690c574	57	#ifdef __cplusplus
AnnaBridge	145:64910690c574	58	extern "C" {
AnnaBridge	145:64910690c574	59	#endif
AnnaBridge	145:64910690c574	60
AnnaBridge	145:64910690c574	61	/* Includes ------------------------------------------------------------------*/
AnnaBridge	145:64910690c574	62	#include "stm32l4xx.h"
AnnaBridge	145:64910690c574	63
AnnaBridge	145:64910690c574	64	/** @addtogroup STM32L4xx_LL_Driver
AnnaBridge	145:64910690c574	65	* @{
AnnaBridge	145:64910690c574	66	*/
AnnaBridge	145:64910690c574	67
AnnaBridge	145:64910690c574	68	#if defined(RCC)
AnnaBridge	145:64910690c574	69
AnnaBridge	145:64910690c574	70	/** @defgroup BUS_LL BUS
AnnaBridge	145:64910690c574	71	* @{
AnnaBridge	145:64910690c574	72	*/
AnnaBridge	145:64910690c574	73
AnnaBridge	145:64910690c574	74	/* Private types -------------------------------------------------------------*/
AnnaBridge	145:64910690c574	75	/* Private variables ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	76
AnnaBridge	145:64910690c574	77	/* Private constants ---------------------------------------------------------*/
AnnaBridge	145:64910690c574	78
AnnaBridge	145:64910690c574	79	/* Private macros ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	80
AnnaBridge	145:64910690c574	81	/* Exported types ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	82	/* Exported constants --------------------------------------------------------*/
AnnaBridge	145:64910690c574	83	/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
AnnaBridge	145:64910690c574	84	* @{
AnnaBridge	145:64910690c574	85	*/
AnnaBridge	145:64910690c574	86
AnnaBridge	145:64910690c574	87	/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
AnnaBridge	145:64910690c574	88	* @{
AnnaBridge	145:64910690c574	89	*/
AnnaBridge	145:64910690c574	90	#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	91	#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
AnnaBridge	145:64910690c574	92	#define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
AnnaBridge	161:aa5281ff4a02	93	#if defined(DMAMUX1)
AnnaBridge	161:aa5281ff4a02	94	#define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN
AnnaBridge	161:aa5281ff4a02	95	#endif /* DMAMUX1 */
AnnaBridge	145:64910690c574	96	#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN
AnnaBridge	145:64910690c574	97	#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
AnnaBridge	145:64910690c574	98	#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN
AnnaBridge	145:64910690c574	99	#if defined(DMA2D)
AnnaBridge	145:64910690c574	100	#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
AnnaBridge	145:64910690c574	101	#endif /* DMA2D */
AnnaBridge	161:aa5281ff4a02	102	#if defined(GFXMMU)
AnnaBridge	161:aa5281ff4a02	103	#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN
AnnaBridge	161:aa5281ff4a02	104	#endif /* GFXMMU */
AnnaBridge	145:64910690c574	105	#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN
AnnaBridge	145:64910690c574	106	/**
AnnaBridge	145:64910690c574	107	* @}
AnnaBridge	145:64910690c574	108	*/
AnnaBridge	145:64910690c574	109
AnnaBridge	145:64910690c574	110	/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
AnnaBridge	145:64910690c574	111	* @{
AnnaBridge	145:64910690c574	112	*/
AnnaBridge	145:64910690c574	113	#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	114	#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN
AnnaBridge	145:64910690c574	115	#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN
AnnaBridge	145:64910690c574	116	#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN
AnnaBridge	145:64910690c574	117	#if defined(GPIOD)
AnnaBridge	145:64910690c574	118	#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN
AnnaBridge	145:64910690c574	119	#endif /GPIOD/
AnnaBridge	145:64910690c574	120	#if defined(GPIOE)
AnnaBridge	145:64910690c574	121	#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN
AnnaBridge	145:64910690c574	122	#endif /GPIOE/
AnnaBridge	145:64910690c574	123	#if defined(GPIOF)
AnnaBridge	145:64910690c574	124	#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN
AnnaBridge	145:64910690c574	125	#endif /* GPIOF */
AnnaBridge	145:64910690c574	126	#if defined(GPIOG)
AnnaBridge	145:64910690c574	127	#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN
AnnaBridge	145:64910690c574	128	#endif /* GPIOG */
AnnaBridge	145:64910690c574	129	#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN
AnnaBridge	145:64910690c574	130	#if defined(GPIOI)
AnnaBridge	145:64910690c574	131	#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN
AnnaBridge	145:64910690c574	132	#endif /* GPIOI */
AnnaBridge	145:64910690c574	133	#if defined(USB_OTG_FS)
AnnaBridge	145:64910690c574	134	#define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
AnnaBridge	145:64910690c574	135	#endif /* USB_OTG_FS */
AnnaBridge	145:64910690c574	136	#define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN
AnnaBridge	145:64910690c574	137	#if defined(DCMI)
AnnaBridge	145:64910690c574	138	#define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
AnnaBridge	145:64910690c574	139	#endif /* DCMI */
AnnaBridge	145:64910690c574	140	#if defined(AES)
AnnaBridge	145:64910690c574	141	#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
AnnaBridge	145:64910690c574	142	#endif /* AES */
AnnaBridge	145:64910690c574	143	#if defined(HASH)
AnnaBridge	145:64910690c574	144	#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
AnnaBridge	145:64910690c574	145	#endif /* HASH */
AnnaBridge	145:64910690c574	146	#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
AnnaBridge	161:aa5281ff4a02	147	#if defined(OCTOSPIM)
AnnaBridge	161:aa5281ff4a02	148	#define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN
AnnaBridge	161:aa5281ff4a02	149	#endif /* OCTOSPIM */
AnnaBridge	161:aa5281ff4a02	150	#if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN)
AnnaBridge	161:aa5281ff4a02	151	#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN
AnnaBridge	161:aa5281ff4a02	152	#endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */
AnnaBridge	145:64910690c574	153	#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN
AnnaBridge	161:aa5281ff4a02	154	#if defined(SRAM3_BASE)
AnnaBridge	161:aa5281ff4a02	155	#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN
AnnaBridge	161:aa5281ff4a02	156	#endif /* SRAM3_BASE */
AnnaBridge	145:64910690c574	157	/**
AnnaBridge	145:64910690c574	158	* @}
AnnaBridge	145:64910690c574	159	*/
AnnaBridge	145:64910690c574	160
AnnaBridge	145:64910690c574	161	/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
AnnaBridge	145:64910690c574	162	* @{
AnnaBridge	145:64910690c574	163	*/
AnnaBridge	145:64910690c574	164	#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	165	#if defined(FMC_Bank1_R)
AnnaBridge	145:64910690c574	166	#define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
AnnaBridge	145:64910690c574	167	#endif /* FMC_Bank1_R */
AnnaBridge	161:aa5281ff4a02	168	#if defined(QUADSPI)
AnnaBridge	145:64910690c574	169	#define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
AnnaBridge	161:aa5281ff4a02	170	#endif /* QUADSPI */
AnnaBridge	161:aa5281ff4a02	171	#if defined(OCTOSPI1)
AnnaBridge	161:aa5281ff4a02	172	#define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN
AnnaBridge	161:aa5281ff4a02	173	#endif /* OCTOSPI1 */
AnnaBridge	161:aa5281ff4a02	174	#if defined(OCTOSPI2)
AnnaBridge	161:aa5281ff4a02	175	#define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN
AnnaBridge	161:aa5281ff4a02	176	#endif /* OCTOSPI2 */
AnnaBridge	145:64910690c574	177	/**
AnnaBridge	145:64910690c574	178	* @}
AnnaBridge	145:64910690c574	179	*/
AnnaBridge	145:64910690c574	180
AnnaBridge	145:64910690c574	181	/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
AnnaBridge	145:64910690c574	182	* @{
AnnaBridge	145:64910690c574	183	*/
AnnaBridge	145:64910690c574	184	#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	185	#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN
AnnaBridge	145:64910690c574	186	#if defined(TIM3)
AnnaBridge	145:64910690c574	187	#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN
AnnaBridge	145:64910690c574	188	#endif /* TIM3 */
AnnaBridge	145:64910690c574	189	#if defined(TIM4)
AnnaBridge	145:64910690c574	190	#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN
AnnaBridge	145:64910690c574	191	#endif /* TIM4 */
AnnaBridge	145:64910690c574	192	#if defined(TIM5)
AnnaBridge	145:64910690c574	193	#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN
AnnaBridge	145:64910690c574	194	#endif /* TIM5 */
AnnaBridge	145:64910690c574	195	#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN
AnnaBridge	145:64910690c574	196	#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN
AnnaBridge	145:64910690c574	197	#if defined(LCD)
AnnaBridge	145:64910690c574	198	#define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN
AnnaBridge	145:64910690c574	199	#endif /* LCD */
AnnaBridge	145:64910690c574	200	#if defined(RCC_APB1ENR1_RTCAPBEN)
AnnaBridge	145:64910690c574	201	#define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN
AnnaBridge	145:64910690c574	202	#endif /* RCC_APB1ENR1_RTCAPBEN */
AnnaBridge	145:64910690c574	203	#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN
AnnaBridge	145:64910690c574	204	#if defined(SPI2)
AnnaBridge	145:64910690c574	205	#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN
AnnaBridge	145:64910690c574	206	#endif /* SPI2 */
AnnaBridge	145:64910690c574	207	#define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN
AnnaBridge	145:64910690c574	208	#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN
AnnaBridge	145:64910690c574	209	#if defined(USART3)
AnnaBridge	145:64910690c574	210	#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN
AnnaBridge	145:64910690c574	211	#endif /* USART3 */
AnnaBridge	145:64910690c574	212	#if defined(UART4)
AnnaBridge	145:64910690c574	213	#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN
AnnaBridge	145:64910690c574	214	#endif /* UART4 */
AnnaBridge	145:64910690c574	215	#if defined(UART5)
AnnaBridge	145:64910690c574	216	#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN
AnnaBridge	145:64910690c574	217	#endif /* UART5 */
AnnaBridge	145:64910690c574	218	#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN
AnnaBridge	145:64910690c574	219	#if defined(I2C2)
AnnaBridge	145:64910690c574	220	#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN
AnnaBridge	145:64910690c574	221	#endif /* I2C2 */
AnnaBridge	145:64910690c574	222	#define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN
AnnaBridge	145:64910690c574	223	#if defined(CRS)
AnnaBridge	145:64910690c574	224	#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN
AnnaBridge	145:64910690c574	225	#endif /* CRS */
AnnaBridge	145:64910690c574	226	#define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN
AnnaBridge	145:64910690c574	227	#if defined(CAN2)
AnnaBridge	145:64910690c574	228	#define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN
AnnaBridge	145:64910690c574	229	#endif /* CAN2 */
AnnaBridge	145:64910690c574	230	#if defined(USB)
AnnaBridge	145:64910690c574	231	#define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN
AnnaBridge	145:64910690c574	232	#endif /* USB */
AnnaBridge	145:64910690c574	233	#define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN
AnnaBridge	145:64910690c574	234	#define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN
AnnaBridge	145:64910690c574	235	#define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN
AnnaBridge	145:64910690c574	236	#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN
AnnaBridge	145:64910690c574	237	/**
AnnaBridge	145:64910690c574	238	* @}
AnnaBridge	145:64910690c574	239	*/
AnnaBridge	145:64910690c574	240
AnnaBridge	145:64910690c574	241
AnnaBridge	145:64910690c574	242	/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
AnnaBridge	145:64910690c574	243	* @{
AnnaBridge	145:64910690c574	244	*/
AnnaBridge	145:64910690c574	245	#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	246	#define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN
AnnaBridge	145:64910690c574	247	#if defined(I2C4)
AnnaBridge	145:64910690c574	248	#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN
AnnaBridge	145:64910690c574	249	#endif /* I2C4 */
AnnaBridge	145:64910690c574	250	#if defined(SWPMI1)
AnnaBridge	145:64910690c574	251	#define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN
AnnaBridge	145:64910690c574	252	#endif /* SWPMI1 */
AnnaBridge	145:64910690c574	253	#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN
AnnaBridge	145:64910690c574	254	/**
AnnaBridge	145:64910690c574	255	* @}
AnnaBridge	145:64910690c574	256	*/
AnnaBridge	145:64910690c574	257
AnnaBridge	145:64910690c574	258	/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
AnnaBridge	145:64910690c574	259	* @{
AnnaBridge	145:64910690c574	260	*/
AnnaBridge	145:64910690c574	261	#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
AnnaBridge	145:64910690c574	262	#define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
AnnaBridge	145:64910690c574	263	#define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN
AnnaBridge	161:aa5281ff4a02	264	#if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN)
AnnaBridge	145:64910690c574	265	#define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
AnnaBridge	161:aa5281ff4a02	266	#endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */
AnnaBridge	145:64910690c574	267	#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
AnnaBridge	145:64910690c574	268	#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
AnnaBridge	145:64910690c574	269	#if defined(TIM8)
AnnaBridge	145:64910690c574	270	#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
AnnaBridge	145:64910690c574	271	#endif /* TIM8 */
AnnaBridge	145:64910690c574	272	#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
AnnaBridge	145:64910690c574	273	#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN
AnnaBridge	145:64910690c574	274	#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN
AnnaBridge	145:64910690c574	275	#if defined(TIM17)
AnnaBridge	145:64910690c574	276	#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN
AnnaBridge	145:64910690c574	277	#endif /* TIM17 */
AnnaBridge	145:64910690c574	278	#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
AnnaBridge	145:64910690c574	279	#if defined(SAI2)
AnnaBridge	145:64910690c574	280	#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
AnnaBridge	145:64910690c574	281	#endif /* SAI2 */
AnnaBridge	145:64910690c574	282	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	283	#define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
AnnaBridge	145:64910690c574	284	#endif /* DFSDM1_Channel0 */
AnnaBridge	161:aa5281ff4a02	285	#if defined(LTDC)
AnnaBridge	161:aa5281ff4a02	286	#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
AnnaBridge	161:aa5281ff4a02	287	#endif /* LTDC */
AnnaBridge	161:aa5281ff4a02	288	#if defined(DSI)
AnnaBridge	161:aa5281ff4a02	289	#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
AnnaBridge	161:aa5281ff4a02	290	#endif /* DSI */
AnnaBridge	145:64910690c574	291	/**
AnnaBridge	145:64910690c574	292	* @}
AnnaBridge	145:64910690c574	293	*/
AnnaBridge	145:64910690c574	294
AnnaBridge	145:64910690c574	295	/** Legacy definitions for compatibility purpose
AnnaBridge	145:64910690c574	296	@cond 0
AnnaBridge	145:64910690c574	297	*/
AnnaBridge	145:64910690c574	298	#if defined(DFSDM1_Channel0)
AnnaBridge	145:64910690c574	299	#define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1
AnnaBridge	145:64910690c574	300	#endif /* DFSDM1_Channel0 */
AnnaBridge	145:64910690c574	301	/**
AnnaBridge	145:64910690c574	302	@endcond
AnnaBridge	145:64910690c574	303	*/
AnnaBridge	145:64910690c574	304
AnnaBridge	145:64910690c574	305	/**
AnnaBridge	145:64910690c574	306	* @}
AnnaBridge	145:64910690c574	307	*/
AnnaBridge	145:64910690c574	308
AnnaBridge	145:64910690c574	309	/* Exported macro ------------------------------------------------------------*/
AnnaBridge	145:64910690c574	310	/* Exported functions --------------------------------------------------------*/
AnnaBridge	145:64910690c574	311	/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
AnnaBridge	145:64910690c574	312	* @{
AnnaBridge	145:64910690c574	313	*/
AnnaBridge	145:64910690c574	314
AnnaBridge	145:64910690c574	315	/** @defgroup BUS_LL_EF_AHB1 AHB1
AnnaBridge	145:64910690c574	316	* @{
AnnaBridge	145:64910690c574	317	*/
AnnaBridge	145:64910690c574	318
AnnaBridge	145:64910690c574	319	/**
AnnaBridge	145:64910690c574	320	* @brief Enable AHB1 peripherals clock.
AnnaBridge	145:64910690c574	321	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	322	* AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	323	* AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	324	* AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	325	* AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	326	* AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	327	* AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	328	* AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock
AnnaBridge	145:64910690c574	329	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	330	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	331	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	332	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	333	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	334	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	335	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	336	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	337	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	338	*
AnnaBridge	145:64910690c574	339	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	340	* @retval None
AnnaBridge	145:64910690c574	341	*/
AnnaBridge	145:64910690c574	342	__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	343	{
AnnaBridge	145:64910690c574	344	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	345	SET_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	145:64910690c574	346	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	347	tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	145:64910690c574	348	(void)tmpreg;
AnnaBridge	145:64910690c574	349	}
AnnaBridge	145:64910690c574	350
AnnaBridge	145:64910690c574	351	/**
AnnaBridge	145:64910690c574	352	* @brief Check if AHB1 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	353	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	354	* AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	355	* AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	356	* AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	357	* AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	358	* AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	359	* AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	360	* AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	361	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	362	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	363	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	364	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	365	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	366	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	367	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	368	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	369	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	370	*
AnnaBridge	145:64910690c574	371	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	372	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	373	*/
AnnaBridge	145:64910690c574	374	__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	375	{
AnnaBridge	145:64910690c574	376	return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	377	}
AnnaBridge	145:64910690c574	378
AnnaBridge	145:64910690c574	379	/**
AnnaBridge	145:64910690c574	380	* @brief Disable AHB1 peripherals clock.
AnnaBridge	145:64910690c574	381	* @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	382	* AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	383	* AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	384	* AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	385	* AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	386	* AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	387	* AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	388	* AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock
AnnaBridge	145:64910690c574	389	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	390	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	391	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	392	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	393	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	394	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	395	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	396	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	397	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	398	*
AnnaBridge	145:64910690c574	399	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	400	* @retval None
AnnaBridge	145:64910690c574	401	*/
AnnaBridge	145:64910690c574	402	__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	403	{
AnnaBridge	145:64910690c574	404	CLEAR_BIT(RCC->AHB1ENR, Periphs);
AnnaBridge	145:64910690c574	405	}
AnnaBridge	145:64910690c574	406
AnnaBridge	145:64910690c574	407	/**
AnnaBridge	145:64910690c574	408	* @brief Force AHB1 peripherals reset.
AnnaBridge	145:64910690c574	409	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	410	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	411	* AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	412	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	413	* AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	414	* AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	415	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	416	* AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset
AnnaBridge	145:64910690c574	417	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	418	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	419	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	420	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	421	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	422	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	423	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	424	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	425	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	426	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	427	*
AnnaBridge	145:64910690c574	428	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	429	* @retval None
AnnaBridge	145:64910690c574	430	*/
AnnaBridge	145:64910690c574	431	__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	432	{
AnnaBridge	145:64910690c574	433	SET_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	145:64910690c574	434	}
AnnaBridge	145:64910690c574	435
AnnaBridge	145:64910690c574	436	/**
AnnaBridge	145:64910690c574	437	* @brief Release AHB1 peripherals reset.
AnnaBridge	145:64910690c574	438	* @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	439	* AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	440	* AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	441	* AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	442	* AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	443	* AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	444	* AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	445	* AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	446	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	447	* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	448	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	449	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	450	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	451	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	452	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	453	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	454	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	455	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	456	*
AnnaBridge	145:64910690c574	457	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	458	* @retval None
AnnaBridge	145:64910690c574	459	*/
AnnaBridge	145:64910690c574	460	__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	461	{
AnnaBridge	145:64910690c574	462	CLEAR_BIT(RCC->AHB1RSTR, Periphs);
AnnaBridge	145:64910690c574	463	}
AnnaBridge	145:64910690c574	464
AnnaBridge	145:64910690c574	465	/**
AnnaBridge	145:64910690c574	466	* @brief Enable AHB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	467	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	468	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	469	* AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	470	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	471	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	472	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	473	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	474	* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	475	* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep
AnnaBridge	145:64910690c574	476	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	477	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	478	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	479	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	480	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	481	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
AnnaBridge	145:64910690c574	482	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	483	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	484	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	485	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	486	*
AnnaBridge	145:64910690c574	487	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	488	* @retval None
AnnaBridge	145:64910690c574	489	*/
AnnaBridge	145:64910690c574	490	__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	491	{
AnnaBridge	145:64910690c574	492	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	493	SET_BIT(RCC->AHB1SMENR, Periphs);
AnnaBridge	145:64910690c574	494	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	495	tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs);
AnnaBridge	145:64910690c574	496	(void)tmpreg;
AnnaBridge	145:64910690c574	497	}
AnnaBridge	145:64910690c574	498
AnnaBridge	145:64910690c574	499	/**
AnnaBridge	145:64910690c574	500	* @brief Disable AHB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	501	* @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	502	* AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	503	* AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	504	* AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	505	* AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	506	* AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	507	* AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	508	* AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	509	* AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep
AnnaBridge	145:64910690c574	510	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	511	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
AnnaBridge	145:64910690c574	512	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
AnnaBridge	161:aa5281ff4a02	513	* @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*)
AnnaBridge	145:64910690c574	514	* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
AnnaBridge	145:64910690c574	515	* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
AnnaBridge	145:64910690c574	516	* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
AnnaBridge	145:64910690c574	517	* @arg @ref LL_AHB1_GRP1_PERIPH_TSC
AnnaBridge	145:64910690c574	518	* @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
AnnaBridge	161:aa5281ff4a02	519	* @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*)
AnnaBridge	145:64910690c574	520	*
AnnaBridge	145:64910690c574	521	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	522	* @retval None
AnnaBridge	145:64910690c574	523	*/
AnnaBridge	145:64910690c574	524	__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	525	{
AnnaBridge	145:64910690c574	526	CLEAR_BIT(RCC->AHB1SMENR, Periphs);
AnnaBridge	145:64910690c574	527	}
AnnaBridge	145:64910690c574	528
AnnaBridge	145:64910690c574	529	/**
AnnaBridge	145:64910690c574	530	* @}
AnnaBridge	145:64910690c574	531	*/
AnnaBridge	145:64910690c574	532
AnnaBridge	145:64910690c574	533	/** @defgroup BUS_LL_EF_AHB2 AHB2
AnnaBridge	145:64910690c574	534	* @{
AnnaBridge	145:64910690c574	535	*/
AnnaBridge	145:64910690c574	536
AnnaBridge	145:64910690c574	537	/**
AnnaBridge	145:64910690c574	538	* @brief Enable AHB2 peripherals clock.
AnnaBridge	145:64910690c574	539	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	540	* AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	541	* AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	542	* AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	543	* AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	544	* AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	545	* AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	546	* AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	547	* AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	548	* AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	549	* AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	550	* AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	551	* AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	552	* AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	553	* AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	554	* AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	555	* AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock
AnnaBridge	145:64910690c574	556	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	557	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	558	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	559	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	560	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	561	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	562	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	563	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	564	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	565	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	566	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	567	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	568	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	569	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	570	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	571	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	572	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	573	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	574	*
AnnaBridge	145:64910690c574	575	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	576	* @retval None
AnnaBridge	145:64910690c574	577	*/
AnnaBridge	145:64910690c574	578	__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	579	{
AnnaBridge	145:64910690c574	580	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	581	SET_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	145:64910690c574	582	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	583	tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	145:64910690c574	584	(void)tmpreg;
AnnaBridge	145:64910690c574	585	}
AnnaBridge	145:64910690c574	586
AnnaBridge	145:64910690c574	587	/**
AnnaBridge	145:64910690c574	588	* @brief Check if AHB2 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	589	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	590	* AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	591	* AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	592	* AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	593	* AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	594	* AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	595	* AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	596	* AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	597	* AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	598	* AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	599	* AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	600	* AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	601	* AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	602	* AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	603	* AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	604	* AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	605	* AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	606	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	607	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	608	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	609	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	610	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	611	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	612	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	613	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	614	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	615	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	616	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	617	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	618	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	619	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	620	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	621	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	622	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	623	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	624	*
AnnaBridge	145:64910690c574	625	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	626	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	627	*/
AnnaBridge	145:64910690c574	628	__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	629	{
AnnaBridge	145:64910690c574	630	return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	631	}
AnnaBridge	145:64910690c574	632
AnnaBridge	145:64910690c574	633	/**
AnnaBridge	145:64910690c574	634	* @brief Disable AHB2 peripherals clock.
AnnaBridge	145:64910690c574	635	* @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	636	* AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	637	* AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	638	* AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	639	* AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	640	* AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	641	* AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	642	* AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	643	* AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	644	* AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	645	* AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	646	* AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	647	* AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	648	* AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	649	* AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	650	* AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	651	* AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock
AnnaBridge	145:64910690c574	652	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	653	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	654	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	655	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	656	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	657	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	658	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	659	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	660	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	661	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	662	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	663	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	664	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	665	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	666	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	667	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	668	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	669	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	670	*
AnnaBridge	145:64910690c574	671	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	672	* @retval None
AnnaBridge	145:64910690c574	673	*/
AnnaBridge	145:64910690c574	674	__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	675	{
AnnaBridge	145:64910690c574	676	CLEAR_BIT(RCC->AHB2ENR, Periphs);
AnnaBridge	145:64910690c574	677	}
AnnaBridge	145:64910690c574	678
AnnaBridge	145:64910690c574	679	/**
AnnaBridge	145:64910690c574	680	* @brief Force AHB2 peripherals reset.
AnnaBridge	145:64910690c574	681	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	682	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	683	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	684	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	685	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	686	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	687	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	688	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	689	* AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	690	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	691	* AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	692	* AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	693	* AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	694	* AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	695	* AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	696	* AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	697	* AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset
AnnaBridge	145:64910690c574	698	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	699	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	700	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	701	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	702	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	703	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	704	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	705	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	706	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	707	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	708	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	709	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	710	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	711	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	712	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	713	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	714	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	715	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	716	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	717	*
AnnaBridge	145:64910690c574	718	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	719	* @retval None
AnnaBridge	145:64910690c574	720	*/
AnnaBridge	145:64910690c574	721	__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	722	{
AnnaBridge	145:64910690c574	723	SET_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	145:64910690c574	724	}
AnnaBridge	145:64910690c574	725
AnnaBridge	145:64910690c574	726	/**
AnnaBridge	145:64910690c574	727	* @brief Release AHB2 peripherals reset.
AnnaBridge	145:64910690c574	728	* @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	729	* AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	730	* AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	731	* AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	732	* AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	733	* AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	734	* AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	735	* AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	736	* AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	737	* AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	738	* AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	739	* AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	740	* AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	741	* AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	742	* AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	743	* AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	744	* AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	745	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	746	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	747	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	748	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	749	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	750	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	751	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	752	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	753	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	754	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	755	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	756	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	757	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	758	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	759	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	760	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	761	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	762	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	763	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	764	*
AnnaBridge	145:64910690c574	765	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	766	* @retval None
AnnaBridge	145:64910690c574	767	*/
AnnaBridge	145:64910690c574	768	__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	769	{
AnnaBridge	145:64910690c574	770	CLEAR_BIT(RCC->AHB2RSTR, Periphs);
AnnaBridge	145:64910690c574	771	}
AnnaBridge	145:64910690c574	772
AnnaBridge	145:64910690c574	773	/**
AnnaBridge	145:64910690c574	774	* @brief Enable AHB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	775	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	776	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	777	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	778	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	779	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	780	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	781	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	782	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	783	* AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	784	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	785	* AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	786	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	787	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	788	* AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	789	* AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	790	* AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	791	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	792	* AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	793	* AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep
AnnaBridge	145:64910690c574	794	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	795	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	796	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	797	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	798	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	799	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	800	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	801	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	802	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	803	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	804	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
AnnaBridge	161:aa5281ff4a02	805	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
AnnaBridge	145:64910690c574	806	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	807	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	808	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	809	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	810	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	811	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	812	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	813	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	814	*
AnnaBridge	145:64910690c574	815	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	816	* @retval None
AnnaBridge	145:64910690c574	817	*/
AnnaBridge	145:64910690c574	818	__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	819	{
AnnaBridge	145:64910690c574	820	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	821	SET_BIT(RCC->AHB2SMENR, Periphs);
AnnaBridge	145:64910690c574	822	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	823	tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs);
AnnaBridge	145:64910690c574	824	(void)tmpreg;
AnnaBridge	145:64910690c574	825	}
AnnaBridge	145:64910690c574	826
AnnaBridge	145:64910690c574	827	/**
AnnaBridge	145:64910690c574	828	* @brief Disable AHB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	829	* @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	830	* AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	831	* AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	832	* AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	833	* AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	834	* AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	835	* AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	836	* AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	837	* AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	838	* AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	839	* AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	840	* AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	841	* AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	842	* AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	843	* AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	844	* AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	845	* AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	846	* AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	847	* AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep
AnnaBridge	145:64910690c574	848	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	849	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA
AnnaBridge	145:64910690c574	850	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB
AnnaBridge	145:64910690c574	851	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC
AnnaBridge	145:64910690c574	852	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*)
AnnaBridge	145:64910690c574	853	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*)
AnnaBridge	145:64910690c574	854	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*)
AnnaBridge	145:64910690c574	855	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*)
AnnaBridge	145:64910690c574	856	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH
AnnaBridge	145:64910690c574	857	* @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*)
AnnaBridge	145:64910690c574	858	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2
AnnaBridge	161:aa5281ff4a02	859	* @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*)
AnnaBridge	145:64910690c574	860	* @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*)
AnnaBridge	145:64910690c574	861	* @arg @ref LL_AHB2_GRP1_PERIPH_ADC
AnnaBridge	145:64910690c574	862	* @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
AnnaBridge	145:64910690c574	863	* @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
AnnaBridge	145:64910690c574	864	* @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
AnnaBridge	145:64910690c574	865	* @arg @ref LL_AHB2_GRP1_PERIPH_RNG
AnnaBridge	161:aa5281ff4a02	866	* @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*)
AnnaBridge	161:aa5281ff4a02	867	* @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	868	*
AnnaBridge	145:64910690c574	869	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	870	* @retval None
AnnaBridge	145:64910690c574	871	*/
AnnaBridge	145:64910690c574	872	__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	873	{
AnnaBridge	145:64910690c574	874	CLEAR_BIT(RCC->AHB2SMENR, Periphs);
AnnaBridge	145:64910690c574	875	}
AnnaBridge	145:64910690c574	876
AnnaBridge	145:64910690c574	877	/**
AnnaBridge	145:64910690c574	878	* @}
AnnaBridge	145:64910690c574	879	*/
AnnaBridge	145:64910690c574	880
AnnaBridge	145:64910690c574	881	/** @defgroup BUS_LL_EF_AHB3 AHB3
AnnaBridge	145:64910690c574	882	* @{
AnnaBridge	145:64910690c574	883	*/
AnnaBridge	145:64910690c574	884
AnnaBridge	145:64910690c574	885	/**
AnnaBridge	145:64910690c574	886	* @brief Enable AHB3 peripherals clock.
AnnaBridge	145:64910690c574	887	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	888	* AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	889	* AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	890	* AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock
AnnaBridge	145:64910690c574	891	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	892	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	893	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	894	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	895	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	896	*
AnnaBridge	145:64910690c574	897	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	898	* @retval None
AnnaBridge	145:64910690c574	899	*/
AnnaBridge	145:64910690c574	900	__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	901	{
AnnaBridge	145:64910690c574	902	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	903	SET_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	145:64910690c574	904	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	905	tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	145:64910690c574	906	(void)tmpreg;
AnnaBridge	145:64910690c574	907	}
AnnaBridge	145:64910690c574	908
AnnaBridge	145:64910690c574	909	/**
AnnaBridge	145:64910690c574	910	* @brief Check if AHB3 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	911	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	912	* AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	913	* AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	914	* AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	915	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	916	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	917	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	918	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	919	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	920	*
AnnaBridge	145:64910690c574	921	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	922	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	923	*/
AnnaBridge	145:64910690c574	924	__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	925	{
AnnaBridge	145:64910690c574	926	return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	927	}
AnnaBridge	145:64910690c574	928
AnnaBridge	145:64910690c574	929	/**
AnnaBridge	145:64910690c574	930	* @brief Disable AHB3 peripherals clock.
AnnaBridge	145:64910690c574	931	* @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	932	* AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	933	* AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	934	* AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock
AnnaBridge	145:64910690c574	935	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	936	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	937	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	938	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	939	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	940	*
AnnaBridge	145:64910690c574	941	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	942	* @retval None
AnnaBridge	145:64910690c574	943	*/
AnnaBridge	145:64910690c574	944	__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	945	{
AnnaBridge	145:64910690c574	946	CLEAR_BIT(RCC->AHB3ENR, Periphs);
AnnaBridge	145:64910690c574	947	}
AnnaBridge	145:64910690c574	948
AnnaBridge	145:64910690c574	949	/**
AnnaBridge	145:64910690c574	950	* @brief Force AHB3 peripherals reset.
AnnaBridge	145:64910690c574	951	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	952	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	953	* AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	954	* AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset
AnnaBridge	145:64910690c574	955	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	956	* @arg @ref LL_AHB3_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	957	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	958	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	959	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	960	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	961	*
AnnaBridge	145:64910690c574	962	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	963	* @retval None
AnnaBridge	145:64910690c574	964	*/
AnnaBridge	145:64910690c574	965	__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	966	{
AnnaBridge	145:64910690c574	967	SET_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	145:64910690c574	968	}
AnnaBridge	145:64910690c574	969
AnnaBridge	145:64910690c574	970	/**
AnnaBridge	145:64910690c574	971	* @brief Release AHB3 peripherals reset.
AnnaBridge	145:64910690c574	972	* @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	973	* AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	974	* AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	975	* AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	976	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	977	* @arg @ref LL_AHB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	978	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	979	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	980	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	981	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	982	*
AnnaBridge	145:64910690c574	983	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	984	* @retval None
AnnaBridge	145:64910690c574	985	*/
AnnaBridge	145:64910690c574	986	__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	987	{
AnnaBridge	145:64910690c574	988	CLEAR_BIT(RCC->AHB3RSTR, Periphs);
AnnaBridge	145:64910690c574	989	}
AnnaBridge	145:64910690c574	990
AnnaBridge	145:64910690c574	991	/**
AnnaBridge	145:64910690c574	992	* @brief Enable AHB3 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	993	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	994	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	995	* AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	996	* AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep
AnnaBridge	145:64910690c574	997	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	998	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	999	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	1000	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	1001	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	1002	*
AnnaBridge	145:64910690c574	1003	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1004	* @retval None
AnnaBridge	145:64910690c574	1005	*/
AnnaBridge	145:64910690c574	1006	__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1007	{
AnnaBridge	145:64910690c574	1008	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1009	SET_BIT(RCC->AHB3SMENR, Periphs);
AnnaBridge	145:64910690c574	1010	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1011	tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs);
AnnaBridge	145:64910690c574	1012	(void)tmpreg;
AnnaBridge	145:64910690c574	1013	}
AnnaBridge	145:64910690c574	1014
AnnaBridge	145:64910690c574	1015	/**
AnnaBridge	145:64910690c574	1016	* @brief Disable AHB3 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1017	* @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1018	* AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1019	* AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1020	* AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1021	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1022	* @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
AnnaBridge	161:aa5281ff4a02	1023	* @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)
AnnaBridge	161:aa5281ff4a02	1024	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)
AnnaBridge	161:aa5281ff4a02	1025	* @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)
AnnaBridge	145:64910690c574	1026	*
AnnaBridge	145:64910690c574	1027	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1028	* @retval None
AnnaBridge	145:64910690c574	1029	*/
AnnaBridge	145:64910690c574	1030	__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1031	{
AnnaBridge	145:64910690c574	1032	CLEAR_BIT(RCC->AHB3SMENR, Periphs);
AnnaBridge	145:64910690c574	1033	}
AnnaBridge	145:64910690c574	1034
AnnaBridge	145:64910690c574	1035	/**
AnnaBridge	145:64910690c574	1036	* @}
AnnaBridge	145:64910690c574	1037	*/
AnnaBridge	145:64910690c574	1038
AnnaBridge	145:64910690c574	1039	/** @defgroup BUS_LL_EF_APB1 APB1
AnnaBridge	145:64910690c574	1040	* @{
AnnaBridge	145:64910690c574	1041	*/
AnnaBridge	145:64910690c574	1042
AnnaBridge	145:64910690c574	1043	/**
AnnaBridge	145:64910690c574	1044	* @brief Enable APB1 peripherals clock.
AnnaBridge	145:64910690c574	1045	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1046	* APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1047	* APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1048	* APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1049	* APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1050	* APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1051	* APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1052	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1053	* APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1054	* APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1055	* APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1056	* APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1057	* APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1058	* APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1059	* APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1060	* APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1061	* APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1062	* APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1063	* APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1064	* APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1065	* APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1066	* APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1067	* APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1068	* APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1069	* APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1070	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock
AnnaBridge	145:64910690c574	1071	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1072	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1073	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1074	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1075	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1076	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1077	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1078	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1079	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1080	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1081	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1082	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1083	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1084	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1085	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1086	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1087	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1088	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1089	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1090	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1091	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1092	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1093	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1094	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1095	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1096	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1097	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1098	*
AnnaBridge	145:64910690c574	1099	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1100	* @retval None
AnnaBridge	145:64910690c574	1101	*/
AnnaBridge	145:64910690c574	1102	__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1103	{
AnnaBridge	145:64910690c574	1104	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1105	SET_BIT(RCC->APB1ENR1, Periphs);
AnnaBridge	145:64910690c574	1106	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1107	tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);
AnnaBridge	145:64910690c574	1108	(void)tmpreg;
AnnaBridge	145:64910690c574	1109	}
AnnaBridge	145:64910690c574	1110
AnnaBridge	145:64910690c574	1111	/**
AnnaBridge	145:64910690c574	1112	* @brief Enable APB1 peripherals clock.
AnnaBridge	145:64910690c574	1113	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n
AnnaBridge	145:64910690c574	1114	* APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n
AnnaBridge	145:64910690c574	1115	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n
AnnaBridge	145:64910690c574	1116	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock
AnnaBridge	145:64910690c574	1117	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1118	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1119	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1120	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1121	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1122	*
AnnaBridge	145:64910690c574	1123	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1124	* @retval None
AnnaBridge	145:64910690c574	1125	*/
AnnaBridge	145:64910690c574	1126	__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1127	{
AnnaBridge	145:64910690c574	1128	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1129	SET_BIT(RCC->APB1ENR2, Periphs);
AnnaBridge	145:64910690c574	1130	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1131	tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);
AnnaBridge	145:64910690c574	1132	(void)tmpreg;
AnnaBridge	145:64910690c574	1133	}
AnnaBridge	145:64910690c574	1134
AnnaBridge	145:64910690c574	1135	/**
AnnaBridge	145:64910690c574	1136	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	1137	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1138	* APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1139	* APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1140	* APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1141	* APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1142	* APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1143	* APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1144	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1145	* APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1146	* APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1147	* APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1148	* APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1149	* APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1150	* APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1151	* APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1152	* APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1153	* APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1154	* APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1155	* APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1156	* APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1157	* APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1158	* APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1159	* APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1160	* APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1161	* APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1162	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	1163	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1164	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1165	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1166	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1167	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1168	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1169	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1170	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1171	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1172	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1173	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1174	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1175	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1176	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1177	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1178	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1179	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1180	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1181	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1182	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1183	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1184	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1185	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1186	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1187	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1188	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1189	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1190	*
AnnaBridge	145:64910690c574	1191	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1192	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	1193	*/
AnnaBridge	145:64910690c574	1194	__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1195	{
AnnaBridge	145:64910690c574	1196	return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs);
AnnaBridge	145:64910690c574	1197	}
AnnaBridge	145:64910690c574	1198
AnnaBridge	145:64910690c574	1199	/**
AnnaBridge	145:64910690c574	1200	* @brief Check if APB1 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	1201	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	145:64910690c574	1202	* APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	145:64910690c574	1203	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n
AnnaBridge	145:64910690c574	1204	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock
AnnaBridge	145:64910690c574	1205	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1206	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1207	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1208	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1209	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1210	*
AnnaBridge	145:64910690c574	1211	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1212	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	1213	*/
AnnaBridge	145:64910690c574	1214	__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1215	{
AnnaBridge	145:64910690c574	1216	return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs);
AnnaBridge	145:64910690c574	1217	}
AnnaBridge	145:64910690c574	1218
AnnaBridge	145:64910690c574	1219	/**
AnnaBridge	145:64910690c574	1220	* @brief Disable APB1 peripherals clock.
AnnaBridge	145:64910690c574	1221	* @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1222	* APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1223	* APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1224	* APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1225	* APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1226	* APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1227	* APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1228	* APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1229	* APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1230	* APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1231	* APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1232	* APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1233	* APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1234	* APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1235	* APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1236	* APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1237	* APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1238	* APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1239	* APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1240	* APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1241	* APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1242	* APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1243	* APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1244	* APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1245	* APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1246	* APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock
AnnaBridge	145:64910690c574	1247	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1248	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1249	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1250	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1251	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1252	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1253	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1254	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1255	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1256	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1257	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1258	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1259	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1260	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1261	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1262	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1263	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1264	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1265	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1266	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1267	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1268	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1269	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1270	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1271	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1272	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1273	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1274	*
AnnaBridge	145:64910690c574	1275	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1276	* @retval None
AnnaBridge	145:64910690c574	1277	*/
AnnaBridge	145:64910690c574	1278	__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1279	{
AnnaBridge	145:64910690c574	1280	CLEAR_BIT(RCC->APB1ENR1, Periphs);
AnnaBridge	145:64910690c574	1281	}
AnnaBridge	145:64910690c574	1282
AnnaBridge	145:64910690c574	1283	/**
AnnaBridge	145:64910690c574	1284	* @brief Disable APB1 peripherals clock.
AnnaBridge	145:64910690c574	1285	* @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n
AnnaBridge	145:64910690c574	1286	* APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n
AnnaBridge	145:64910690c574	1287	* APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n
AnnaBridge	145:64910690c574	1288	* APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock
AnnaBridge	145:64910690c574	1289	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1290	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1291	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1292	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1293	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1294	*
AnnaBridge	145:64910690c574	1295	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1296	* @retval None
AnnaBridge	145:64910690c574	1297	*/
AnnaBridge	145:64910690c574	1298	__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1299	{
AnnaBridge	145:64910690c574	1300	CLEAR_BIT(RCC->APB1ENR2, Periphs);
AnnaBridge	145:64910690c574	1301	}
AnnaBridge	145:64910690c574	1302
AnnaBridge	145:64910690c574	1303	/**
AnnaBridge	145:64910690c574	1304	* @brief Force APB1 peripherals reset.
AnnaBridge	145:64910690c574	1305	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1306	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1307	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1308	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1309	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1310	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1311	* APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1312	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1313	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1314	* APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1315	* APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1316	* APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1317	* APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1318	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1319	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1320	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1321	* APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1322	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1323	* APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1324	* APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1325	* APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1326	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1327	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1328	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset
AnnaBridge	145:64910690c574	1329	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1330	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1331	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1332	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1333	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1334	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1335	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1336	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1337	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1338	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1339	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1340	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1341	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1342	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1343	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1344	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1345	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1346	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1347	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1348	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1349	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1350	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1351	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1352	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1353	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1354	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1355	*
AnnaBridge	145:64910690c574	1356	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1357	* @retval None
AnnaBridge	145:64910690c574	1358	*/
AnnaBridge	145:64910690c574	1359	__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1360	{
AnnaBridge	145:64910690c574	1361	SET_BIT(RCC->APB1RSTR1, Periphs);
AnnaBridge	145:64910690c574	1362	}
AnnaBridge	145:64910690c574	1363
AnnaBridge	145:64910690c574	1364	/**
AnnaBridge	145:64910690c574	1365	* @brief Force APB1 peripherals reset.
AnnaBridge	145:64910690c574	1366	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n
AnnaBridge	145:64910690c574	1367	* APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n
AnnaBridge	145:64910690c574	1368	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n
AnnaBridge	145:64910690c574	1369	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset
AnnaBridge	145:64910690c574	1370	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1371	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
AnnaBridge	145:64910690c574	1372	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1373	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1374	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1375	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1376	*
AnnaBridge	145:64910690c574	1377	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1378	* @retval None
AnnaBridge	145:64910690c574	1379	*/
AnnaBridge	145:64910690c574	1380	__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1381	{
AnnaBridge	145:64910690c574	1382	SET_BIT(RCC->APB1RSTR2, Periphs);
AnnaBridge	145:64910690c574	1383	}
AnnaBridge	145:64910690c574	1384
AnnaBridge	145:64910690c574	1385	/**
AnnaBridge	145:64910690c574	1386	* @brief Release APB1 peripherals reset.
AnnaBridge	145:64910690c574	1387	* @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1388	* APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1389	* APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1390	* APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1391	* APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1392	* APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1393	* APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1394	* APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1395	* APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1396	* APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1397	* APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1398	* APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1399	* APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1400	* APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1401	* APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1402	* APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1403	* APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1404	* APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1405	* APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1406	* APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1407	* APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1408	* APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1409	* APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1410	* APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	1411	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1412	* @arg @ref LL_APB1_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1413	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1414	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1415	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1416	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1417	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1418	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1419	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1420	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1421	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1422	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1423	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1424	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1425	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1426	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1427	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1428	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1429	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1430	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1431	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1432	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1433	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1434	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1435	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1436	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1437	*
AnnaBridge	145:64910690c574	1438	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1439	* @retval None
AnnaBridge	145:64910690c574	1440	*/
AnnaBridge	145:64910690c574	1441	__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1442	{
AnnaBridge	145:64910690c574	1443	CLEAR_BIT(RCC->APB1RSTR1, Periphs);
AnnaBridge	145:64910690c574	1444	}
AnnaBridge	145:64910690c574	1445
AnnaBridge	145:64910690c574	1446	/**
AnnaBridge	145:64910690c574	1447	* @brief Release APB1 peripherals reset.
AnnaBridge	145:64910690c574	1448	* @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	145:64910690c574	1449	* APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	145:64910690c574	1450	* APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n
AnnaBridge	145:64910690c574	1451	* APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset
AnnaBridge	145:64910690c574	1452	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1453	* @arg @ref LL_APB1_GRP2_PERIPH_ALL
AnnaBridge	145:64910690c574	1454	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1455	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1456	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1457	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1458	*
AnnaBridge	145:64910690c574	1459	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1460	* @retval None
AnnaBridge	145:64910690c574	1461	*/
AnnaBridge	145:64910690c574	1462	__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1463	{
AnnaBridge	145:64910690c574	1464	CLEAR_BIT(RCC->APB1RSTR2, Periphs);
AnnaBridge	145:64910690c574	1465	}
AnnaBridge	145:64910690c574	1466
AnnaBridge	145:64910690c574	1467	/**
AnnaBridge	145:64910690c574	1468	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1469	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1470	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1471	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1472	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1473	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1474	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1475	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1476	* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1477	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1478	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1479	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1480	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1481	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1482	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1483	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1484	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1485	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1486	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1487	* APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1488	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1489	* APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1490	* APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1491	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1492	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1493	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1494	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep
AnnaBridge	145:64910690c574	1495	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1496	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1497	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1498	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1499	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1500	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1501	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1502	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1503	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1504	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1505	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1506	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1507	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1508	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1509	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1510	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1511	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1512	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1513	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1514	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1515	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1516	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1517	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1518	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1519	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1520	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1521	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1522	*
AnnaBridge	145:64910690c574	1523	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1524	* @retval None
AnnaBridge	145:64910690c574	1525	*/
AnnaBridge	145:64910690c574	1526	__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1527	{
AnnaBridge	145:64910690c574	1528	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1529	SET_BIT(RCC->APB1SMENR1, Periphs);
AnnaBridge	145:64910690c574	1530	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1531	tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs);
AnnaBridge	145:64910690c574	1532	(void)tmpreg;
AnnaBridge	145:64910690c574	1533	}
AnnaBridge	145:64910690c574	1534
AnnaBridge	145:64910690c574	1535	/**
AnnaBridge	145:64910690c574	1536	* @brief Enable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1537	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1538	* APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1539	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1540	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep
AnnaBridge	145:64910690c574	1541	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1542	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1543	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1544	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1545	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1546	*
AnnaBridge	145:64910690c574	1547	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1548	* @retval None
AnnaBridge	145:64910690c574	1549	*/
AnnaBridge	145:64910690c574	1550	__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1551	{
AnnaBridge	145:64910690c574	1552	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1553	SET_BIT(RCC->APB1SMENR2, Periphs);
AnnaBridge	145:64910690c574	1554	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1555	tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs);
AnnaBridge	145:64910690c574	1556	(void)tmpreg;
AnnaBridge	145:64910690c574	1557	}
AnnaBridge	145:64910690c574	1558
AnnaBridge	145:64910690c574	1559	/**
AnnaBridge	145:64910690c574	1560	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1561	* @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1562	* APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1563	* APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1564	* APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1565	* APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1566	* APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1567	* APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1568	* APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1569	* APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1570	* APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1571	* APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1572	* APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1573	* APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1574	* APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1575	* APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1576	* APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1577	* APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1578	* APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1579	* APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1580	* APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1581	* APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1582	* APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1583	* APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1584	* APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1585	* APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1586	* APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep
AnnaBridge	145:64910690c574	1587	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1588	* @arg @ref LL_APB1_GRP1_PERIPH_TIM2
AnnaBridge	145:64910690c574	1589	* @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*)
AnnaBridge	145:64910690c574	1590	* @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*)
AnnaBridge	145:64910690c574	1591	* @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*)
AnnaBridge	145:64910690c574	1592	* @arg @ref LL_APB1_GRP1_PERIPH_TIM6
AnnaBridge	145:64910690c574	1593	* @arg @ref LL_APB1_GRP1_PERIPH_TIM7
AnnaBridge	145:64910690c574	1594	* @arg @ref LL_APB1_GRP1_PERIPH_LCD (*)
AnnaBridge	145:64910690c574	1595	* @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
AnnaBridge	145:64910690c574	1596	* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
AnnaBridge	145:64910690c574	1597	* @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*)
AnnaBridge	145:64910690c574	1598	* @arg @ref LL_APB1_GRP1_PERIPH_SPI3
AnnaBridge	145:64910690c574	1599	* @arg @ref LL_APB1_GRP1_PERIPH_USART2
AnnaBridge	145:64910690c574	1600	* @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*)
AnnaBridge	145:64910690c574	1601	* @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*)
AnnaBridge	145:64910690c574	1602	* @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*)
AnnaBridge	145:64910690c574	1603	* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
AnnaBridge	145:64910690c574	1604	* @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*)
AnnaBridge	145:64910690c574	1605	* @arg @ref LL_APB1_GRP1_PERIPH_I2C3
AnnaBridge	145:64910690c574	1606	* @arg @ref LL_APB1_GRP1_PERIPH_CRS (*)
AnnaBridge	145:64910690c574	1607	* @arg @ref LL_APB1_GRP1_PERIPH_CAN1
AnnaBridge	145:64910690c574	1608	* @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
AnnaBridge	145:64910690c574	1609	* @arg @ref LL_APB1_GRP1_PERIPH_USB (*)
AnnaBridge	145:64910690c574	1610	* @arg @ref LL_APB1_GRP1_PERIPH_PWR
AnnaBridge	145:64910690c574	1611	* @arg @ref LL_APB1_GRP1_PERIPH_DAC1
AnnaBridge	145:64910690c574	1612	* @arg @ref LL_APB1_GRP1_PERIPH_OPAMP
AnnaBridge	145:64910690c574	1613	* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
AnnaBridge	145:64910690c574	1614	*
AnnaBridge	145:64910690c574	1615	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1616	* @retval None
AnnaBridge	145:64910690c574	1617	*/
AnnaBridge	145:64910690c574	1618	__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1619	{
AnnaBridge	145:64910690c574	1620	CLEAR_BIT(RCC->APB1SMENR1, Periphs);
AnnaBridge	145:64910690c574	1621	}
AnnaBridge	145:64910690c574	1622
AnnaBridge	145:64910690c574	1623	/**
AnnaBridge	145:64910690c574	1624	* @brief Disable APB1 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1625	* @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1626	* APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1627	* APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1628	* APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep
AnnaBridge	145:64910690c574	1629	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1630	* @arg @ref LL_APB1_GRP2_PERIPH_LPUART1
AnnaBridge	145:64910690c574	1631	* @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*)
AnnaBridge	145:64910690c574	1632	* @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*)
AnnaBridge	145:64910690c574	1633	* @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2
AnnaBridge	145:64910690c574	1634	*
AnnaBridge	145:64910690c574	1635	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1636	* @retval None
AnnaBridge	145:64910690c574	1637	*/
AnnaBridge	145:64910690c574	1638	__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1639	{
AnnaBridge	145:64910690c574	1640	CLEAR_BIT(RCC->APB1SMENR2, Periphs);
AnnaBridge	145:64910690c574	1641	}
AnnaBridge	145:64910690c574	1642
AnnaBridge	145:64910690c574	1643	/**
AnnaBridge	145:64910690c574	1644	* @}
AnnaBridge	145:64910690c574	1645	*/
AnnaBridge	145:64910690c574	1646
AnnaBridge	145:64910690c574	1647	/** @defgroup BUS_LL_EF_APB2 APB2
AnnaBridge	145:64910690c574	1648	* @{
AnnaBridge	145:64910690c574	1649	*/
AnnaBridge	145:64910690c574	1650
AnnaBridge	145:64910690c574	1651	/**
AnnaBridge	145:64910690c574	1652	* @brief Enable APB2 peripherals clock.
AnnaBridge	145:64910690c574	1653	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1654	* APB2ENR FWEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1655	* APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1656	* APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1657	* APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1658	* APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1659	* APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1660	* APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1661	* APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1662	* APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1663	* APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	145:64910690c574	1664	* APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	1665	* APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	1666	* APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
AnnaBridge	161:aa5281ff4a02	1667	* APB2ENR DSIEN LL_APB2_GRP1_EnableClock
AnnaBridge	145:64910690c574	1668	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1669	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1670	* @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge	145:64910690c574	1671	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1672	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1673	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1674	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1675	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1676	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1677	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1678	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1679	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1680	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1681	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1682	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1683	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1684	*
AnnaBridge	145:64910690c574	1685	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1686	* @retval None
AnnaBridge	145:64910690c574	1687	*/
AnnaBridge	145:64910690c574	1688	__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1689	{
AnnaBridge	145:64910690c574	1690	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1691	SET_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	145:64910690c574	1692	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1693	tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	145:64910690c574	1694	(void)tmpreg;
AnnaBridge	145:64910690c574	1695	}
AnnaBridge	145:64910690c574	1696
AnnaBridge	145:64910690c574	1697	/**
AnnaBridge	145:64910690c574	1698	* @brief Check if APB2 peripheral clock is enabled or not
AnnaBridge	145:64910690c574	1699	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1700	* APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1701	* APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1702	* APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1703	* APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1704	* APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1705	* APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1706	* APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1707	* APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1708	* APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1709	* APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	145:64910690c574	1710	* APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	1711	* APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	1712	* APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
AnnaBridge	161:aa5281ff4a02	1713	* APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock
AnnaBridge	145:64910690c574	1714	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1715	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1716	* @arg @ref LL_APB2_GRP1_PERIPH_FW
AnnaBridge	145:64910690c574	1717	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1718	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1719	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1720	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1721	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1722	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1723	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1724	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1725	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1726	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1727	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1728	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1729	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1730	*
AnnaBridge	145:64910690c574	1731	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1732	* @retval State of Periphs (1 or 0).
AnnaBridge	145:64910690c574	1733	*/
AnnaBridge	145:64910690c574	1734	__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1735	{
AnnaBridge	145:64910690c574	1736	return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
AnnaBridge	145:64910690c574	1737	}
AnnaBridge	145:64910690c574	1738
AnnaBridge	145:64910690c574	1739	/**
AnnaBridge	145:64910690c574	1740	* @brief Disable APB2 peripherals clock.
AnnaBridge	145:64910690c574	1741	* @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1742	* APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1743	* APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1744	* APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1745	* APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1746	* APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1747	* APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1748	* APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1749	* APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1750	* APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	145:64910690c574	1751	* APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	1752	* APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	1753	* APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
AnnaBridge	161:aa5281ff4a02	1754	* APB2ENR DSIEN LL_APB2_GRP1_DisableClock
AnnaBridge	145:64910690c574	1755	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1756	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1757	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1758	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1759	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1760	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1761	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1762	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1763	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1764	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1765	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1766	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1767	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1768	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1769	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1770	*
AnnaBridge	145:64910690c574	1771	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1772	* @retval None
AnnaBridge	145:64910690c574	1773	*/
AnnaBridge	145:64910690c574	1774	__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
AnnaBridge	145:64910690c574	1775	{
AnnaBridge	145:64910690c574	1776	CLEAR_BIT(RCC->APB2ENR, Periphs);
AnnaBridge	145:64910690c574	1777	}
AnnaBridge	145:64910690c574	1778
AnnaBridge	145:64910690c574	1779	/**
AnnaBridge	145:64910690c574	1780	* @brief Force APB2 peripherals reset.
AnnaBridge	145:64910690c574	1781	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1782	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1783	* APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1784	* APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1785	* APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1786	* APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1787	* APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1788	* APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1789	* APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1790	* APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	145:64910690c574	1791	* APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	1792	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	1793	* APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
AnnaBridge	161:aa5281ff4a02	1794	* APB2RSTR DSIRST LL_APB2_GRP1_ForceReset
AnnaBridge	145:64910690c574	1795	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1796	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1797	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1798	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1799	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1800	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1801	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1802	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1803	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1804	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1805	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1806	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1807	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1808	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1809	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1810	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1811	*
AnnaBridge	145:64910690c574	1812	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1813	* @retval None
AnnaBridge	145:64910690c574	1814	*/
AnnaBridge	145:64910690c574	1815	__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1816	{
AnnaBridge	145:64910690c574	1817	SET_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	145:64910690c574	1818	}
AnnaBridge	145:64910690c574	1819
AnnaBridge	145:64910690c574	1820	/**
AnnaBridge	145:64910690c574	1821	* @brief Release APB2 peripherals reset.
AnnaBridge	145:64910690c574	1822	* @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1823	* APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1824	* APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1825	* APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1826	* APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1827	* APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1828	* APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1829	* APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1830	* APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1831	* APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	145:64910690c574	1832	* APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	1833	* APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	1834	* APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
AnnaBridge	161:aa5281ff4a02	1835	* APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset
AnnaBridge	145:64910690c574	1836	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1837	* @arg @ref LL_APB2_GRP1_PERIPH_ALL
AnnaBridge	145:64910690c574	1838	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1839	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1840	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1841	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1842	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1843	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1844	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1845	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1846	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1847	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1848	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1849	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1850	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1851	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1852	*
AnnaBridge	145:64910690c574	1853	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1854	* @retval None
AnnaBridge	145:64910690c574	1855	*/
AnnaBridge	145:64910690c574	1856	__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
AnnaBridge	145:64910690c574	1857	{
AnnaBridge	145:64910690c574	1858	CLEAR_BIT(RCC->APB2RSTR, Periphs);
AnnaBridge	145:64910690c574	1859	}
AnnaBridge	145:64910690c574	1860
AnnaBridge	145:64910690c574	1861	/**
AnnaBridge	145:64910690c574	1862	* @brief Enable APB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1863	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1864	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1865	* APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1866	* APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1867	* APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1868	* APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1869	* APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1870	* APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1871	* APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1872	* APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	145:64910690c574	1873	* APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1874	* APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1875	* APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1876	* APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep
AnnaBridge	145:64910690c574	1877	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1878	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1879	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1880	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1881	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1882	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1883	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1884	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1885	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1886	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1887	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1888	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1889	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1890	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1891	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1892	*
AnnaBridge	145:64910690c574	1893	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1894	* @retval None
AnnaBridge	145:64910690c574	1895	*/
AnnaBridge	145:64910690c574	1896	__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1897	{
AnnaBridge	145:64910690c574	1898	__IO uint32_t tmpreg;
AnnaBridge	145:64910690c574	1899	SET_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge	145:64910690c574	1900	/* Delay after an RCC peripheral clock enabling */
AnnaBridge	145:64910690c574	1901	tmpreg = READ_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge	145:64910690c574	1902	(void)tmpreg;
AnnaBridge	145:64910690c574	1903	}
AnnaBridge	145:64910690c574	1904
AnnaBridge	145:64910690c574	1905	/**
AnnaBridge	145:64910690c574	1906	* @brief Disable APB2 peripheral clocks in Sleep and Stop modes
AnnaBridge	145:64910690c574	1907	* @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1908	* APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1909	* APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1910	* APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1911	* APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1912	* APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1913	* APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1914	* APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1915	* APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1916	* APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	145:64910690c574	1917	* APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1918	* APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1919	* APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n
AnnaBridge	161:aa5281ff4a02	1920	* APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep
AnnaBridge	145:64910690c574	1921	* @param Periphs This parameter can be a combination of the following values:
AnnaBridge	145:64910690c574	1922	* @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
AnnaBridge	145:64910690c574	1923	* @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
AnnaBridge	145:64910690c574	1924	* @arg @ref LL_APB2_GRP1_PERIPH_TIM1
AnnaBridge	145:64910690c574	1925	* @arg @ref LL_APB2_GRP1_PERIPH_SPI1
AnnaBridge	145:64910690c574	1926	* @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*)
AnnaBridge	145:64910690c574	1927	* @arg @ref LL_APB2_GRP1_PERIPH_USART1
AnnaBridge	145:64910690c574	1928	* @arg @ref LL_APB2_GRP1_PERIPH_TIM15
AnnaBridge	145:64910690c574	1929	* @arg @ref LL_APB2_GRP1_PERIPH_TIM16
AnnaBridge	145:64910690c574	1930	* @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*)
AnnaBridge	145:64910690c574	1931	* @arg @ref LL_APB2_GRP1_PERIPH_SAI1
AnnaBridge	145:64910690c574	1932	* @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*)
AnnaBridge	145:64910690c574	1933	* @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
AnnaBridge	161:aa5281ff4a02	1934	* @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
AnnaBridge	161:aa5281ff4a02	1935	* @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
AnnaBridge	145:64910690c574	1936	*
AnnaBridge	145:64910690c574	1937	* (*) value not defined in all devices.
AnnaBridge	145:64910690c574	1938	* @retval None
AnnaBridge	145:64910690c574	1939	*/
AnnaBridge	145:64910690c574	1940	__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs)
AnnaBridge	145:64910690c574	1941	{
AnnaBridge	145:64910690c574	1942	CLEAR_BIT(RCC->APB2SMENR, Periphs);
AnnaBridge	145:64910690c574	1943	}
AnnaBridge	145:64910690c574	1944
AnnaBridge	145:64910690c574	1945	/**
AnnaBridge	145:64910690c574	1946	* @}
AnnaBridge	145:64910690c574	1947	*/
AnnaBridge	145:64910690c574	1948
AnnaBridge	145:64910690c574	1949
AnnaBridge	145:64910690c574	1950	/**
AnnaBridge	145:64910690c574	1951	* @}
AnnaBridge	145:64910690c574	1952	*/
AnnaBridge	145:64910690c574	1953
AnnaBridge	145:64910690c574	1954	/**
AnnaBridge	145:64910690c574	1955	* @}
AnnaBridge	145:64910690c574	1956	*/
AnnaBridge	145:64910690c574	1957
AnnaBridge	145:64910690c574	1958	#endif /* defined(RCC) */
AnnaBridge	145:64910690c574	1959
AnnaBridge	145:64910690c574	1960	/**
AnnaBridge	145:64910690c574	1961	* @}
AnnaBridge	145:64910690c574	1962	*/
AnnaBridge	145:64910690c574	1963
AnnaBridge	145:64910690c574	1964	#ifdef __cplusplus
AnnaBridge	145:64910690c574	1965	}
AnnaBridge	145:64910690c574	1966	#endif
AnnaBridge	145:64910690c574	1967
AnnaBridge	145:64910690c574	1968	#endif /* __STM32L4xx_LL_BUS_H */
AnnaBridge	145:64910690c574	1969
AnnaBridge	145:64910690c574	1970	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/