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TARGET_DISCO_L475VG_IOT01A/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_bus.h@145:64910690c574, 2017-06-21 (annotated)
- Committer:
- AnnaBridge
- Date:
- Wed Jun 21 17:31:38 2017 +0100
- Revision:
- 145:64910690c574
- Child:
- 161:aa5281ff4a02
Release 145 of the mbed library.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| AnnaBridge | 145:64910690c574 | 1 | /** |
| AnnaBridge | 145:64910690c574 | 2 | ****************************************************************************** |
| AnnaBridge | 145:64910690c574 | 3 | * @file stm32l4xx_ll_bus.h |
| AnnaBridge | 145:64910690c574 | 4 | * @author MCD Application Team |
| AnnaBridge | 145:64910690c574 | 5 | * @version V1.7.1 |
| AnnaBridge | 145:64910690c574 | 6 | * @date 21-April-2017 |
| AnnaBridge | 145:64910690c574 | 7 | * @brief Header file of BUS LL module. |
| AnnaBridge | 145:64910690c574 | 8 | |
| AnnaBridge | 145:64910690c574 | 9 | @verbatim |
| AnnaBridge | 145:64910690c574 | 10 | ##### RCC Limitations ##### |
| AnnaBridge | 145:64910690c574 | 11 | ============================================================================== |
| AnnaBridge | 145:64910690c574 | 12 | [..] |
| AnnaBridge | 145:64910690c574 | 13 | A delay between an RCC peripheral clock enable and the effective peripheral |
| AnnaBridge | 145:64910690c574 | 14 | enabling should be taken into account in order to manage the peripheral read/write |
| AnnaBridge | 145:64910690c574 | 15 | from/to registers. |
| AnnaBridge | 145:64910690c574 | 16 | (+) This delay depends on the peripheral mapping. |
| AnnaBridge | 145:64910690c574 | 17 | (++) AHB & APB peripherals, 1 dummy read is necessary |
| AnnaBridge | 145:64910690c574 | 18 | |
| AnnaBridge | 145:64910690c574 | 19 | [..] |
| AnnaBridge | 145:64910690c574 | 20 | Workarounds: |
| AnnaBridge | 145:64910690c574 | 21 | (#) For AHB & APB peripherals, a dummy read to the peripheral register has been |
| AnnaBridge | 145:64910690c574 | 22 | inserted in each LL_{BUS}_GRP{x}_EnableClock() function. |
| AnnaBridge | 145:64910690c574 | 23 | |
| AnnaBridge | 145:64910690c574 | 24 | @endverbatim |
| AnnaBridge | 145:64910690c574 | 25 | ****************************************************************************** |
| AnnaBridge | 145:64910690c574 | 26 | * @attention |
| AnnaBridge | 145:64910690c574 | 27 | * |
| AnnaBridge | 145:64910690c574 | 28 | * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> |
| AnnaBridge | 145:64910690c574 | 29 | * |
| AnnaBridge | 145:64910690c574 | 30 | * Redistribution and use in source and binary forms, with or without modification, |
| AnnaBridge | 145:64910690c574 | 31 | * are permitted provided that the following conditions are met: |
| AnnaBridge | 145:64910690c574 | 32 | * 1. Redistributions of source code must retain the above copyright notice, |
| AnnaBridge | 145:64910690c574 | 33 | * this list of conditions and the following disclaimer. |
| AnnaBridge | 145:64910690c574 | 34 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| AnnaBridge | 145:64910690c574 | 35 | * this list of conditions and the following disclaimer in the documentation |
| AnnaBridge | 145:64910690c574 | 36 | * and/or other materials provided with the distribution. |
| AnnaBridge | 145:64910690c574 | 37 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| AnnaBridge | 145:64910690c574 | 38 | * may be used to endorse or promote products derived from this software |
| AnnaBridge | 145:64910690c574 | 39 | * without specific prior written permission. |
| AnnaBridge | 145:64910690c574 | 40 | * |
| AnnaBridge | 145:64910690c574 | 41 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| AnnaBridge | 145:64910690c574 | 42 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| AnnaBridge | 145:64910690c574 | 43 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| AnnaBridge | 145:64910690c574 | 44 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| AnnaBridge | 145:64910690c574 | 45 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| AnnaBridge | 145:64910690c574 | 46 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| AnnaBridge | 145:64910690c574 | 47 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| AnnaBridge | 145:64910690c574 | 48 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| AnnaBridge | 145:64910690c574 | 49 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| AnnaBridge | 145:64910690c574 | 50 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| AnnaBridge | 145:64910690c574 | 51 | * |
| AnnaBridge | 145:64910690c574 | 52 | ****************************************************************************** |
| AnnaBridge | 145:64910690c574 | 53 | */ |
| AnnaBridge | 145:64910690c574 | 54 | |
| AnnaBridge | 145:64910690c574 | 55 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 56 | #ifndef __STM32L4xx_LL_BUS_H |
| AnnaBridge | 145:64910690c574 | 57 | #define __STM32L4xx_LL_BUS_H |
| AnnaBridge | 145:64910690c574 | 58 | |
| AnnaBridge | 145:64910690c574 | 59 | #ifdef __cplusplus |
| AnnaBridge | 145:64910690c574 | 60 | extern "C" { |
| AnnaBridge | 145:64910690c574 | 61 | #endif |
| AnnaBridge | 145:64910690c574 | 62 | |
| AnnaBridge | 145:64910690c574 | 63 | /* Includes ------------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 64 | #include "stm32l4xx.h" |
| AnnaBridge | 145:64910690c574 | 65 | |
| AnnaBridge | 145:64910690c574 | 66 | /** @addtogroup STM32L4xx_LL_Driver |
| AnnaBridge | 145:64910690c574 | 67 | * @{ |
| AnnaBridge | 145:64910690c574 | 68 | */ |
| AnnaBridge | 145:64910690c574 | 69 | |
| AnnaBridge | 145:64910690c574 | 70 | #if defined(RCC) |
| AnnaBridge | 145:64910690c574 | 71 | |
| AnnaBridge | 145:64910690c574 | 72 | /** @defgroup BUS_LL BUS |
| AnnaBridge | 145:64910690c574 | 73 | * @{ |
| AnnaBridge | 145:64910690c574 | 74 | */ |
| AnnaBridge | 145:64910690c574 | 75 | |
| AnnaBridge | 145:64910690c574 | 76 | /* Private types -------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 77 | /* Private variables ---------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 78 | |
| AnnaBridge | 145:64910690c574 | 79 | /* Private constants ---------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 80 | |
| AnnaBridge | 145:64910690c574 | 81 | /* Private macros ------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 82 | |
| AnnaBridge | 145:64910690c574 | 83 | /* Exported types ------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 84 | /* Exported constants --------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 85 | /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants |
| AnnaBridge | 145:64910690c574 | 86 | * @{ |
| AnnaBridge | 145:64910690c574 | 87 | */ |
| AnnaBridge | 145:64910690c574 | 88 | |
| AnnaBridge | 145:64910690c574 | 89 | /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH |
| AnnaBridge | 145:64910690c574 | 90 | * @{ |
| AnnaBridge | 145:64910690c574 | 91 | */ |
| AnnaBridge | 145:64910690c574 | 92 | #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 145:64910690c574 | 93 | #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN |
| AnnaBridge | 145:64910690c574 | 94 | #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN |
| AnnaBridge | 145:64910690c574 | 95 | #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN |
| AnnaBridge | 145:64910690c574 | 96 | #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN |
| AnnaBridge | 145:64910690c574 | 97 | #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN |
| AnnaBridge | 145:64910690c574 | 98 | #if defined(DMA2D) |
| AnnaBridge | 145:64910690c574 | 99 | #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN |
| AnnaBridge | 145:64910690c574 | 100 | #endif /* DMA2D */ |
| AnnaBridge | 145:64910690c574 | 101 | #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN |
| AnnaBridge | 145:64910690c574 | 102 | /** |
| AnnaBridge | 145:64910690c574 | 103 | * @} |
| AnnaBridge | 145:64910690c574 | 104 | */ |
| AnnaBridge | 145:64910690c574 | 105 | |
| AnnaBridge | 145:64910690c574 | 106 | /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH |
| AnnaBridge | 145:64910690c574 | 107 | * @{ |
| AnnaBridge | 145:64910690c574 | 108 | */ |
| AnnaBridge | 145:64910690c574 | 109 | #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 145:64910690c574 | 110 | #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN |
| AnnaBridge | 145:64910690c574 | 111 | #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN |
| AnnaBridge | 145:64910690c574 | 112 | #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN |
| AnnaBridge | 145:64910690c574 | 113 | #if defined(GPIOD) |
| AnnaBridge | 145:64910690c574 | 114 | #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN |
| AnnaBridge | 145:64910690c574 | 115 | #endif /*GPIOD*/ |
| AnnaBridge | 145:64910690c574 | 116 | #if defined(GPIOE) |
| AnnaBridge | 145:64910690c574 | 117 | #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN |
| AnnaBridge | 145:64910690c574 | 118 | #endif /*GPIOE*/ |
| AnnaBridge | 145:64910690c574 | 119 | #if defined(GPIOF) |
| AnnaBridge | 145:64910690c574 | 120 | #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN |
| AnnaBridge | 145:64910690c574 | 121 | #endif /* GPIOF */ |
| AnnaBridge | 145:64910690c574 | 122 | #if defined(GPIOG) |
| AnnaBridge | 145:64910690c574 | 123 | #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN |
| AnnaBridge | 145:64910690c574 | 124 | #endif /* GPIOG */ |
| AnnaBridge | 145:64910690c574 | 125 | #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN |
| AnnaBridge | 145:64910690c574 | 126 | #if defined(GPIOI) |
| AnnaBridge | 145:64910690c574 | 127 | #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN |
| AnnaBridge | 145:64910690c574 | 128 | #endif /* GPIOI */ |
| AnnaBridge | 145:64910690c574 | 129 | #if defined(USB_OTG_FS) |
| AnnaBridge | 145:64910690c574 | 130 | #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN |
| AnnaBridge | 145:64910690c574 | 131 | #endif /* USB_OTG_FS */ |
| AnnaBridge | 145:64910690c574 | 132 | #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN |
| AnnaBridge | 145:64910690c574 | 133 | #if defined(DCMI) |
| AnnaBridge | 145:64910690c574 | 134 | #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN |
| AnnaBridge | 145:64910690c574 | 135 | #endif /* DCMI */ |
| AnnaBridge | 145:64910690c574 | 136 | #if defined(AES) |
| AnnaBridge | 145:64910690c574 | 137 | #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN |
| AnnaBridge | 145:64910690c574 | 138 | #endif /* AES */ |
| AnnaBridge | 145:64910690c574 | 139 | #if defined(HASH) |
| AnnaBridge | 145:64910690c574 | 140 | #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN |
| AnnaBridge | 145:64910690c574 | 141 | #endif /* HASH */ |
| AnnaBridge | 145:64910690c574 | 142 | #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN |
| AnnaBridge | 145:64910690c574 | 143 | #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN |
| AnnaBridge | 145:64910690c574 | 144 | /** |
| AnnaBridge | 145:64910690c574 | 145 | * @} |
| AnnaBridge | 145:64910690c574 | 146 | */ |
| AnnaBridge | 145:64910690c574 | 147 | |
| AnnaBridge | 145:64910690c574 | 148 | /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH |
| AnnaBridge | 145:64910690c574 | 149 | * @{ |
| AnnaBridge | 145:64910690c574 | 150 | */ |
| AnnaBridge | 145:64910690c574 | 151 | #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 145:64910690c574 | 152 | #if defined(FMC_Bank1_R) |
| AnnaBridge | 145:64910690c574 | 153 | #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN |
| AnnaBridge | 145:64910690c574 | 154 | #endif /* FMC_Bank1_R */ |
| AnnaBridge | 145:64910690c574 | 155 | #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN |
| AnnaBridge | 145:64910690c574 | 156 | /** |
| AnnaBridge | 145:64910690c574 | 157 | * @} |
| AnnaBridge | 145:64910690c574 | 158 | */ |
| AnnaBridge | 145:64910690c574 | 159 | |
| AnnaBridge | 145:64910690c574 | 160 | /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH |
| AnnaBridge | 145:64910690c574 | 161 | * @{ |
| AnnaBridge | 145:64910690c574 | 162 | */ |
| AnnaBridge | 145:64910690c574 | 163 | #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 145:64910690c574 | 164 | #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN |
| AnnaBridge | 145:64910690c574 | 165 | #if defined(TIM3) |
| AnnaBridge | 145:64910690c574 | 166 | #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN |
| AnnaBridge | 145:64910690c574 | 167 | #endif /* TIM3 */ |
| AnnaBridge | 145:64910690c574 | 168 | #if defined(TIM4) |
| AnnaBridge | 145:64910690c574 | 169 | #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN |
| AnnaBridge | 145:64910690c574 | 170 | #endif /* TIM4 */ |
| AnnaBridge | 145:64910690c574 | 171 | #if defined(TIM5) |
| AnnaBridge | 145:64910690c574 | 172 | #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN |
| AnnaBridge | 145:64910690c574 | 173 | #endif /* TIM5 */ |
| AnnaBridge | 145:64910690c574 | 174 | #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN |
| AnnaBridge | 145:64910690c574 | 175 | #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN |
| AnnaBridge | 145:64910690c574 | 176 | #if defined(LCD) |
| AnnaBridge | 145:64910690c574 | 177 | #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN |
| AnnaBridge | 145:64910690c574 | 178 | #endif /* LCD */ |
| AnnaBridge | 145:64910690c574 | 179 | #if defined(RCC_APB1ENR1_RTCAPBEN) |
| AnnaBridge | 145:64910690c574 | 180 | #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN |
| AnnaBridge | 145:64910690c574 | 181 | #endif /* RCC_APB1ENR1_RTCAPBEN */ |
| AnnaBridge | 145:64910690c574 | 182 | #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN |
| AnnaBridge | 145:64910690c574 | 183 | #if defined(SPI2) |
| AnnaBridge | 145:64910690c574 | 184 | #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN |
| AnnaBridge | 145:64910690c574 | 185 | #endif /* SPI2 */ |
| AnnaBridge | 145:64910690c574 | 186 | #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN |
| AnnaBridge | 145:64910690c574 | 187 | #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN |
| AnnaBridge | 145:64910690c574 | 188 | #if defined(USART3) |
| AnnaBridge | 145:64910690c574 | 189 | #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN |
| AnnaBridge | 145:64910690c574 | 190 | #endif /* USART3 */ |
| AnnaBridge | 145:64910690c574 | 191 | #if defined(UART4) |
| AnnaBridge | 145:64910690c574 | 192 | #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN |
| AnnaBridge | 145:64910690c574 | 193 | #endif /* UART4 */ |
| AnnaBridge | 145:64910690c574 | 194 | #if defined(UART5) |
| AnnaBridge | 145:64910690c574 | 195 | #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN |
| AnnaBridge | 145:64910690c574 | 196 | #endif /* UART5 */ |
| AnnaBridge | 145:64910690c574 | 197 | #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN |
| AnnaBridge | 145:64910690c574 | 198 | #if defined(I2C2) |
| AnnaBridge | 145:64910690c574 | 199 | #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN |
| AnnaBridge | 145:64910690c574 | 200 | #endif /* I2C2 */ |
| AnnaBridge | 145:64910690c574 | 201 | #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN |
| AnnaBridge | 145:64910690c574 | 202 | #if defined(CRS) |
| AnnaBridge | 145:64910690c574 | 203 | #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN |
| AnnaBridge | 145:64910690c574 | 204 | #endif /* CRS */ |
| AnnaBridge | 145:64910690c574 | 205 | #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN |
| AnnaBridge | 145:64910690c574 | 206 | #if defined(CAN2) |
| AnnaBridge | 145:64910690c574 | 207 | #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN |
| AnnaBridge | 145:64910690c574 | 208 | #endif /* CAN2 */ |
| AnnaBridge | 145:64910690c574 | 209 | #if defined(USB) |
| AnnaBridge | 145:64910690c574 | 210 | #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN |
| AnnaBridge | 145:64910690c574 | 211 | #endif /* USB */ |
| AnnaBridge | 145:64910690c574 | 212 | #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN |
| AnnaBridge | 145:64910690c574 | 213 | #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN |
| AnnaBridge | 145:64910690c574 | 214 | #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN |
| AnnaBridge | 145:64910690c574 | 215 | #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN |
| AnnaBridge | 145:64910690c574 | 216 | /** |
| AnnaBridge | 145:64910690c574 | 217 | * @} |
| AnnaBridge | 145:64910690c574 | 218 | */ |
| AnnaBridge | 145:64910690c574 | 219 | |
| AnnaBridge | 145:64910690c574 | 220 | |
| AnnaBridge | 145:64910690c574 | 221 | /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH |
| AnnaBridge | 145:64910690c574 | 222 | * @{ |
| AnnaBridge | 145:64910690c574 | 223 | */ |
| AnnaBridge | 145:64910690c574 | 224 | #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 145:64910690c574 | 225 | #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN |
| AnnaBridge | 145:64910690c574 | 226 | #if defined(I2C4) |
| AnnaBridge | 145:64910690c574 | 227 | #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN |
| AnnaBridge | 145:64910690c574 | 228 | #endif /* I2C4 */ |
| AnnaBridge | 145:64910690c574 | 229 | #if defined(SWPMI1) |
| AnnaBridge | 145:64910690c574 | 230 | #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN |
| AnnaBridge | 145:64910690c574 | 231 | #endif /* SWPMI1 */ |
| AnnaBridge | 145:64910690c574 | 232 | #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN |
| AnnaBridge | 145:64910690c574 | 233 | /** |
| AnnaBridge | 145:64910690c574 | 234 | * @} |
| AnnaBridge | 145:64910690c574 | 235 | */ |
| AnnaBridge | 145:64910690c574 | 236 | |
| AnnaBridge | 145:64910690c574 | 237 | /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH |
| AnnaBridge | 145:64910690c574 | 238 | * @{ |
| AnnaBridge | 145:64910690c574 | 239 | */ |
| AnnaBridge | 145:64910690c574 | 240 | #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU |
| AnnaBridge | 145:64910690c574 | 241 | #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN |
| AnnaBridge | 145:64910690c574 | 242 | #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN |
| AnnaBridge | 145:64910690c574 | 243 | #if defined(SDMMC1) |
| AnnaBridge | 145:64910690c574 | 244 | #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN |
| AnnaBridge | 145:64910690c574 | 245 | #endif /* SDMMC1 */ |
| AnnaBridge | 145:64910690c574 | 246 | #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN |
| AnnaBridge | 145:64910690c574 | 247 | #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN |
| AnnaBridge | 145:64910690c574 | 248 | #if defined(TIM8) |
| AnnaBridge | 145:64910690c574 | 249 | #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN |
| AnnaBridge | 145:64910690c574 | 250 | #endif /* TIM8 */ |
| AnnaBridge | 145:64910690c574 | 251 | #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN |
| AnnaBridge | 145:64910690c574 | 252 | #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN |
| AnnaBridge | 145:64910690c574 | 253 | #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN |
| AnnaBridge | 145:64910690c574 | 254 | #if defined(TIM17) |
| AnnaBridge | 145:64910690c574 | 255 | #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN |
| AnnaBridge | 145:64910690c574 | 256 | #endif /* TIM17 */ |
| AnnaBridge | 145:64910690c574 | 257 | #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN |
| AnnaBridge | 145:64910690c574 | 258 | #if defined(SAI2) |
| AnnaBridge | 145:64910690c574 | 259 | #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN |
| AnnaBridge | 145:64910690c574 | 260 | #endif /* SAI2 */ |
| AnnaBridge | 145:64910690c574 | 261 | #if defined(DFSDM1_Channel0) |
| AnnaBridge | 145:64910690c574 | 262 | #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN |
| AnnaBridge | 145:64910690c574 | 263 | #endif /* DFSDM1_Channel0 */ |
| AnnaBridge | 145:64910690c574 | 264 | /** |
| AnnaBridge | 145:64910690c574 | 265 | * @} |
| AnnaBridge | 145:64910690c574 | 266 | */ |
| AnnaBridge | 145:64910690c574 | 267 | |
| AnnaBridge | 145:64910690c574 | 268 | /** Legacy definitions for compatibility purpose |
| AnnaBridge | 145:64910690c574 | 269 | @cond 0 |
| AnnaBridge | 145:64910690c574 | 270 | */ |
| AnnaBridge | 145:64910690c574 | 271 | #if defined(DFSDM1_Channel0) |
| AnnaBridge | 145:64910690c574 | 272 | #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1 |
| AnnaBridge | 145:64910690c574 | 273 | #endif /* DFSDM1_Channel0 */ |
| AnnaBridge | 145:64910690c574 | 274 | /** |
| AnnaBridge | 145:64910690c574 | 275 | @endcond |
| AnnaBridge | 145:64910690c574 | 276 | */ |
| AnnaBridge | 145:64910690c574 | 277 | |
| AnnaBridge | 145:64910690c574 | 278 | /** |
| AnnaBridge | 145:64910690c574 | 279 | * @} |
| AnnaBridge | 145:64910690c574 | 280 | */ |
| AnnaBridge | 145:64910690c574 | 281 | |
| AnnaBridge | 145:64910690c574 | 282 | /* Exported macro ------------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 283 | /* Exported functions --------------------------------------------------------*/ |
| AnnaBridge | 145:64910690c574 | 284 | /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions |
| AnnaBridge | 145:64910690c574 | 285 | * @{ |
| AnnaBridge | 145:64910690c574 | 286 | */ |
| AnnaBridge | 145:64910690c574 | 287 | |
| AnnaBridge | 145:64910690c574 | 288 | /** @defgroup BUS_LL_EF_AHB1 AHB1 |
| AnnaBridge | 145:64910690c574 | 289 | * @{ |
| AnnaBridge | 145:64910690c574 | 290 | */ |
| AnnaBridge | 145:64910690c574 | 291 | |
| AnnaBridge | 145:64910690c574 | 292 | /** |
| AnnaBridge | 145:64910690c574 | 293 | * @brief Enable AHB1 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 294 | * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 295 | * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 296 | * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 297 | * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 298 | * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 299 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock |
| AnnaBridge | 145:64910690c574 | 300 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 301 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 302 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 303 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 304 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 305 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 306 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 307 | * |
| AnnaBridge | 145:64910690c574 | 308 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 309 | * @retval None |
| AnnaBridge | 145:64910690c574 | 310 | */ |
| AnnaBridge | 145:64910690c574 | 311 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 312 | { |
| AnnaBridge | 145:64910690c574 | 313 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 314 | SET_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 315 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 316 | tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 317 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 318 | } |
| AnnaBridge | 145:64910690c574 | 319 | |
| AnnaBridge | 145:64910690c574 | 320 | /** |
| AnnaBridge | 145:64910690c574 | 321 | * @brief Check if AHB1 peripheral clock is enabled or not |
| AnnaBridge | 145:64910690c574 | 322 | * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 323 | * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 324 | * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 325 | * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 326 | * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 327 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock |
| AnnaBridge | 145:64910690c574 | 328 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 329 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 330 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 331 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 332 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 333 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 334 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 335 | * |
| AnnaBridge | 145:64910690c574 | 336 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 337 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 145:64910690c574 | 338 | */ |
| AnnaBridge | 145:64910690c574 | 339 | __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 340 | { |
| AnnaBridge | 145:64910690c574 | 341 | return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); |
| AnnaBridge | 145:64910690c574 | 342 | } |
| AnnaBridge | 145:64910690c574 | 343 | |
| AnnaBridge | 145:64910690c574 | 344 | /** |
| AnnaBridge | 145:64910690c574 | 345 | * @brief Disable AHB1 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 346 | * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 347 | * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 348 | * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 349 | * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 350 | * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 351 | * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock |
| AnnaBridge | 145:64910690c574 | 352 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 353 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 354 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 355 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 356 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 357 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 358 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 359 | * |
| AnnaBridge | 145:64910690c574 | 360 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 361 | * @retval None |
| AnnaBridge | 145:64910690c574 | 362 | */ |
| AnnaBridge | 145:64910690c574 | 363 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 364 | { |
| AnnaBridge | 145:64910690c574 | 365 | CLEAR_BIT(RCC->AHB1ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 366 | } |
| AnnaBridge | 145:64910690c574 | 367 | |
| AnnaBridge | 145:64910690c574 | 368 | /** |
| AnnaBridge | 145:64910690c574 | 369 | * @brief Force AHB1 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 370 | * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 371 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 372 | * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 373 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 374 | * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 375 | * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset |
| AnnaBridge | 145:64910690c574 | 376 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 377 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 378 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 379 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 380 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 381 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 382 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 383 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 384 | * |
| AnnaBridge | 145:64910690c574 | 385 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 386 | * @retval None |
| AnnaBridge | 145:64910690c574 | 387 | */ |
| AnnaBridge | 145:64910690c574 | 388 | __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 389 | { |
| AnnaBridge | 145:64910690c574 | 390 | SET_BIT(RCC->AHB1RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 391 | } |
| AnnaBridge | 145:64910690c574 | 392 | |
| AnnaBridge | 145:64910690c574 | 393 | /** |
| AnnaBridge | 145:64910690c574 | 394 | * @brief Release AHB1 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 395 | * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 396 | * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 397 | * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 398 | * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 399 | * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 400 | * AHB1ENR DMA2DRST LL_AHB1_GRP1_ReleaseReset |
| AnnaBridge | 145:64910690c574 | 401 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 402 | * @arg @ref LL_AHB1_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 403 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 404 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 405 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 406 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 407 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 408 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 409 | * |
| AnnaBridge | 145:64910690c574 | 410 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 411 | * @retval None |
| AnnaBridge | 145:64910690c574 | 412 | */ |
| AnnaBridge | 145:64910690c574 | 413 | __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 414 | { |
| AnnaBridge | 145:64910690c574 | 415 | CLEAR_BIT(RCC->AHB1RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 416 | } |
| AnnaBridge | 145:64910690c574 | 417 | |
| AnnaBridge | 145:64910690c574 | 418 | /** |
| AnnaBridge | 145:64910690c574 | 419 | * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 420 | * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 421 | * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 422 | * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 423 | * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 424 | * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 425 | * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 426 | * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 427 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 428 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 429 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 430 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 431 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| AnnaBridge | 145:64910690c574 | 432 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 433 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 434 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 435 | * |
| AnnaBridge | 145:64910690c574 | 436 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 437 | * @retval None |
| AnnaBridge | 145:64910690c574 | 438 | */ |
| AnnaBridge | 145:64910690c574 | 439 | __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 440 | { |
| AnnaBridge | 145:64910690c574 | 441 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 442 | SET_BIT(RCC->AHB1SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 443 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 444 | tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 445 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 446 | } |
| AnnaBridge | 145:64910690c574 | 447 | |
| AnnaBridge | 145:64910690c574 | 448 | /** |
| AnnaBridge | 145:64910690c574 | 449 | * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 450 | * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 451 | * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 452 | * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 453 | * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 454 | * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 455 | * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 456 | * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 457 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 458 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 |
| AnnaBridge | 145:64910690c574 | 459 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 |
| AnnaBridge | 145:64910690c574 | 460 | * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH |
| AnnaBridge | 145:64910690c574 | 461 | * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 |
| AnnaBridge | 145:64910690c574 | 462 | * @arg @ref LL_AHB1_GRP1_PERIPH_CRC |
| AnnaBridge | 145:64910690c574 | 463 | * @arg @ref LL_AHB1_GRP1_PERIPH_TSC |
| AnnaBridge | 145:64910690c574 | 464 | * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) |
| AnnaBridge | 145:64910690c574 | 465 | * |
| AnnaBridge | 145:64910690c574 | 466 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 467 | * @retval None |
| AnnaBridge | 145:64910690c574 | 468 | */ |
| AnnaBridge | 145:64910690c574 | 469 | __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 470 | { |
| AnnaBridge | 145:64910690c574 | 471 | CLEAR_BIT(RCC->AHB1SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 472 | } |
| AnnaBridge | 145:64910690c574 | 473 | |
| AnnaBridge | 145:64910690c574 | 474 | /** |
| AnnaBridge | 145:64910690c574 | 475 | * @} |
| AnnaBridge | 145:64910690c574 | 476 | */ |
| AnnaBridge | 145:64910690c574 | 477 | |
| AnnaBridge | 145:64910690c574 | 478 | /** @defgroup BUS_LL_EF_AHB2 AHB2 |
| AnnaBridge | 145:64910690c574 | 479 | * @{ |
| AnnaBridge | 145:64910690c574 | 480 | */ |
| AnnaBridge | 145:64910690c574 | 481 | |
| AnnaBridge | 145:64910690c574 | 482 | /** |
| AnnaBridge | 145:64910690c574 | 483 | * @brief Enable AHB2 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 484 | * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 485 | * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 486 | * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 487 | * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 488 | * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 489 | * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 490 | * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 491 | * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 492 | * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 493 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 494 | * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 495 | * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 496 | * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 497 | * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 498 | * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock |
| AnnaBridge | 145:64910690c574 | 499 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 500 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 501 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 502 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 503 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 504 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 505 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 506 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 507 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 508 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 509 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 510 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 511 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 512 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 513 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 514 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 515 | * |
| AnnaBridge | 145:64910690c574 | 516 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 517 | * @retval None |
| AnnaBridge | 145:64910690c574 | 518 | */ |
| AnnaBridge | 145:64910690c574 | 519 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 520 | { |
| AnnaBridge | 145:64910690c574 | 521 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 522 | SET_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 523 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 524 | tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 525 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 526 | } |
| AnnaBridge | 145:64910690c574 | 527 | |
| AnnaBridge | 145:64910690c574 | 528 | /** |
| AnnaBridge | 145:64910690c574 | 529 | * @brief Check if AHB2 peripheral clock is enabled or not |
| AnnaBridge | 145:64910690c574 | 530 | * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 531 | * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 532 | * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 533 | * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 534 | * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 535 | * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 536 | * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 537 | * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 538 | * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 539 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 540 | * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 541 | * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 542 | * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 543 | * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 544 | * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock |
| AnnaBridge | 145:64910690c574 | 545 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 546 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 547 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 548 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 549 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 550 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 551 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 552 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 553 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 554 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 555 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 556 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 557 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 558 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 559 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 560 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 561 | * |
| AnnaBridge | 145:64910690c574 | 562 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 563 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 145:64910690c574 | 564 | */ |
| AnnaBridge | 145:64910690c574 | 565 | __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 566 | { |
| AnnaBridge | 145:64910690c574 | 567 | return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); |
| AnnaBridge | 145:64910690c574 | 568 | } |
| AnnaBridge | 145:64910690c574 | 569 | |
| AnnaBridge | 145:64910690c574 | 570 | /** |
| AnnaBridge | 145:64910690c574 | 571 | * @brief Disable AHB2 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 572 | * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 573 | * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 574 | * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 575 | * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 576 | * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 577 | * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 578 | * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 579 | * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 580 | * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 581 | * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 582 | * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 583 | * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 584 | * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 585 | * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 586 | * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock |
| AnnaBridge | 145:64910690c574 | 587 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 588 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 589 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 590 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 591 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 592 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 593 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 594 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 595 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 596 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 597 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 598 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 599 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 600 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 601 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 602 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 603 | * |
| AnnaBridge | 145:64910690c574 | 604 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 605 | * @retval None |
| AnnaBridge | 145:64910690c574 | 606 | */ |
| AnnaBridge | 145:64910690c574 | 607 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 608 | { |
| AnnaBridge | 145:64910690c574 | 609 | CLEAR_BIT(RCC->AHB2ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 610 | } |
| AnnaBridge | 145:64910690c574 | 611 | |
| AnnaBridge | 145:64910690c574 | 612 | /** |
| AnnaBridge | 145:64910690c574 | 613 | * @brief Force AHB2 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 614 | * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 615 | * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 616 | * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 617 | * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 618 | * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 619 | * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 620 | * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 621 | * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 622 | * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 623 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 624 | * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 625 | * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 626 | * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 627 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 628 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset |
| AnnaBridge | 145:64910690c574 | 629 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 630 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 631 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 632 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 633 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 634 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 635 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 636 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 637 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 638 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 639 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 640 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 641 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 642 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 643 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 644 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 645 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 646 | * |
| AnnaBridge | 145:64910690c574 | 647 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 648 | * @retval None |
| AnnaBridge | 145:64910690c574 | 649 | */ |
| AnnaBridge | 145:64910690c574 | 650 | __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 651 | { |
| AnnaBridge | 145:64910690c574 | 652 | SET_BIT(RCC->AHB2RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 653 | } |
| AnnaBridge | 145:64910690c574 | 654 | |
| AnnaBridge | 145:64910690c574 | 655 | /** |
| AnnaBridge | 145:64910690c574 | 656 | * @brief Release AHB2 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 657 | * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 658 | * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 659 | * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 660 | * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 661 | * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 662 | * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 663 | * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 664 | * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 665 | * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 666 | * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 667 | * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 668 | * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 669 | * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 670 | * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 671 | * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset |
| AnnaBridge | 145:64910690c574 | 672 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 673 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 674 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 675 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 676 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 677 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 678 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 679 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 680 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 681 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 682 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 683 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 684 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 685 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 686 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 687 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 688 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 689 | * |
| AnnaBridge | 145:64910690c574 | 690 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 691 | * @retval None |
| AnnaBridge | 145:64910690c574 | 692 | */ |
| AnnaBridge | 145:64910690c574 | 693 | __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 694 | { |
| AnnaBridge | 145:64910690c574 | 695 | CLEAR_BIT(RCC->AHB2RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 696 | } |
| AnnaBridge | 145:64910690c574 | 697 | |
| AnnaBridge | 145:64910690c574 | 698 | /** |
| AnnaBridge | 145:64910690c574 | 699 | * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 700 | * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 701 | * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 702 | * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 703 | * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 704 | * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 705 | * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 706 | * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 707 | * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 708 | * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 709 | * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 710 | * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 711 | * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 712 | * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 713 | * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 714 | * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 715 | * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 716 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 717 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 718 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 719 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 720 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 721 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 722 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 723 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 724 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 725 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 726 | * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 |
| AnnaBridge | 145:64910690c574 | 727 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 728 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 729 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 730 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 731 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 732 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 733 | * |
| AnnaBridge | 145:64910690c574 | 734 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 735 | * @retval None |
| AnnaBridge | 145:64910690c574 | 736 | */ |
| AnnaBridge | 145:64910690c574 | 737 | __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 738 | { |
| AnnaBridge | 145:64910690c574 | 739 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 740 | SET_BIT(RCC->AHB2SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 741 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 742 | tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 743 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 744 | } |
| AnnaBridge | 145:64910690c574 | 745 | |
| AnnaBridge | 145:64910690c574 | 746 | /** |
| AnnaBridge | 145:64910690c574 | 747 | * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 748 | * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 749 | * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 750 | * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 751 | * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 752 | * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 753 | * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 754 | * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 755 | * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 756 | * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 757 | * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 758 | * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 759 | * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 760 | * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 761 | * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 762 | * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 763 | * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 764 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 765 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA |
| AnnaBridge | 145:64910690c574 | 766 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB |
| AnnaBridge | 145:64910690c574 | 767 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC |
| AnnaBridge | 145:64910690c574 | 768 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) |
| AnnaBridge | 145:64910690c574 | 769 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) |
| AnnaBridge | 145:64910690c574 | 770 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) |
| AnnaBridge | 145:64910690c574 | 771 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) |
| AnnaBridge | 145:64910690c574 | 772 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH |
| AnnaBridge | 145:64910690c574 | 773 | * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) |
| AnnaBridge | 145:64910690c574 | 774 | * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 |
| AnnaBridge | 145:64910690c574 | 775 | * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) |
| AnnaBridge | 145:64910690c574 | 776 | * @arg @ref LL_AHB2_GRP1_PERIPH_ADC |
| AnnaBridge | 145:64910690c574 | 777 | * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) |
| AnnaBridge | 145:64910690c574 | 778 | * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) |
| AnnaBridge | 145:64910690c574 | 779 | * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) |
| AnnaBridge | 145:64910690c574 | 780 | * @arg @ref LL_AHB2_GRP1_PERIPH_RNG |
| AnnaBridge | 145:64910690c574 | 781 | * |
| AnnaBridge | 145:64910690c574 | 782 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 783 | * @retval None |
| AnnaBridge | 145:64910690c574 | 784 | */ |
| AnnaBridge | 145:64910690c574 | 785 | __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 786 | { |
| AnnaBridge | 145:64910690c574 | 787 | CLEAR_BIT(RCC->AHB2SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 788 | } |
| AnnaBridge | 145:64910690c574 | 789 | |
| AnnaBridge | 145:64910690c574 | 790 | /** |
| AnnaBridge | 145:64910690c574 | 791 | * @} |
| AnnaBridge | 145:64910690c574 | 792 | */ |
| AnnaBridge | 145:64910690c574 | 793 | |
| AnnaBridge | 145:64910690c574 | 794 | /** @defgroup BUS_LL_EF_AHB3 AHB3 |
| AnnaBridge | 145:64910690c574 | 795 | * @{ |
| AnnaBridge | 145:64910690c574 | 796 | */ |
| AnnaBridge | 145:64910690c574 | 797 | |
| AnnaBridge | 145:64910690c574 | 798 | /** |
| AnnaBridge | 145:64910690c574 | 799 | * @brief Enable AHB3 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 800 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 801 | * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock |
| AnnaBridge | 145:64910690c574 | 802 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 803 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 804 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 805 | * |
| AnnaBridge | 145:64910690c574 | 806 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 807 | * @retval None |
| AnnaBridge | 145:64910690c574 | 808 | */ |
| AnnaBridge | 145:64910690c574 | 809 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 810 | { |
| AnnaBridge | 145:64910690c574 | 811 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 812 | SET_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 813 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 814 | tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 815 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 816 | } |
| AnnaBridge | 145:64910690c574 | 817 | |
| AnnaBridge | 145:64910690c574 | 818 | /** |
| AnnaBridge | 145:64910690c574 | 819 | * @brief Check if AHB3 peripheral clock is enabled or not |
| AnnaBridge | 145:64910690c574 | 820 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 821 | * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock |
| AnnaBridge | 145:64910690c574 | 822 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 823 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 824 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 825 | * |
| AnnaBridge | 145:64910690c574 | 826 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 827 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 145:64910690c574 | 828 | */ |
| AnnaBridge | 145:64910690c574 | 829 | __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 830 | { |
| AnnaBridge | 145:64910690c574 | 831 | return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); |
| AnnaBridge | 145:64910690c574 | 832 | } |
| AnnaBridge | 145:64910690c574 | 833 | |
| AnnaBridge | 145:64910690c574 | 834 | /** |
| AnnaBridge | 145:64910690c574 | 835 | * @brief Disable AHB3 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 836 | * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 837 | * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock |
| AnnaBridge | 145:64910690c574 | 838 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 839 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 840 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 841 | * |
| AnnaBridge | 145:64910690c574 | 842 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 843 | * @retval None |
| AnnaBridge | 145:64910690c574 | 844 | */ |
| AnnaBridge | 145:64910690c574 | 845 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 846 | { |
| AnnaBridge | 145:64910690c574 | 847 | CLEAR_BIT(RCC->AHB3ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 848 | } |
| AnnaBridge | 145:64910690c574 | 849 | |
| AnnaBridge | 145:64910690c574 | 850 | /** |
| AnnaBridge | 145:64910690c574 | 851 | * @brief Force AHB3 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 852 | * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 853 | * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset |
| AnnaBridge | 145:64910690c574 | 854 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 855 | * @arg @ref LL_AHB3_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 856 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 857 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 858 | * |
| AnnaBridge | 145:64910690c574 | 859 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 860 | * @retval None |
| AnnaBridge | 145:64910690c574 | 861 | */ |
| AnnaBridge | 145:64910690c574 | 862 | __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 863 | { |
| AnnaBridge | 145:64910690c574 | 864 | SET_BIT(RCC->AHB3RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 865 | } |
| AnnaBridge | 145:64910690c574 | 866 | |
| AnnaBridge | 145:64910690c574 | 867 | /** |
| AnnaBridge | 145:64910690c574 | 868 | * @brief Release AHB3 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 869 | * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 870 | * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset |
| AnnaBridge | 145:64910690c574 | 871 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 872 | * @arg @ref LL_AHB2_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 873 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 874 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 875 | * |
| AnnaBridge | 145:64910690c574 | 876 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 877 | * @retval None |
| AnnaBridge | 145:64910690c574 | 878 | */ |
| AnnaBridge | 145:64910690c574 | 879 | __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 880 | { |
| AnnaBridge | 145:64910690c574 | 881 | CLEAR_BIT(RCC->AHB3RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 882 | } |
| AnnaBridge | 145:64910690c574 | 883 | |
| AnnaBridge | 145:64910690c574 | 884 | /** |
| AnnaBridge | 145:64910690c574 | 885 | * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 886 | * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 887 | * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 888 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 889 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 890 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 891 | * |
| AnnaBridge | 145:64910690c574 | 892 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 893 | * @retval None |
| AnnaBridge | 145:64910690c574 | 894 | */ |
| AnnaBridge | 145:64910690c574 | 895 | __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 896 | { |
| AnnaBridge | 145:64910690c574 | 897 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 898 | SET_BIT(RCC->AHB3SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 899 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 900 | tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 901 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 902 | } |
| AnnaBridge | 145:64910690c574 | 903 | |
| AnnaBridge | 145:64910690c574 | 904 | /** |
| AnnaBridge | 145:64910690c574 | 905 | * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 906 | * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 907 | * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 908 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 909 | * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) |
| AnnaBridge | 145:64910690c574 | 910 | * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI |
| AnnaBridge | 145:64910690c574 | 911 | * |
| AnnaBridge | 145:64910690c574 | 912 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 913 | * @retval None |
| AnnaBridge | 145:64910690c574 | 914 | */ |
| AnnaBridge | 145:64910690c574 | 915 | __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 916 | { |
| AnnaBridge | 145:64910690c574 | 917 | CLEAR_BIT(RCC->AHB3SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 918 | } |
| AnnaBridge | 145:64910690c574 | 919 | |
| AnnaBridge | 145:64910690c574 | 920 | /** |
| AnnaBridge | 145:64910690c574 | 921 | * @} |
| AnnaBridge | 145:64910690c574 | 922 | */ |
| AnnaBridge | 145:64910690c574 | 923 | |
| AnnaBridge | 145:64910690c574 | 924 | /** @defgroup BUS_LL_EF_APB1 APB1 |
| AnnaBridge | 145:64910690c574 | 925 | * @{ |
| AnnaBridge | 145:64910690c574 | 926 | */ |
| AnnaBridge | 145:64910690c574 | 927 | |
| AnnaBridge | 145:64910690c574 | 928 | /** |
| AnnaBridge | 145:64910690c574 | 929 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 930 | * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 931 | * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 932 | * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 933 | * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 934 | * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 935 | * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 936 | * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 937 | * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 938 | * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 939 | * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 940 | * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 941 | * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 942 | * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 943 | * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 944 | * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 945 | * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 946 | * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 947 | * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 948 | * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 949 | * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 950 | * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 951 | * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 952 | * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 953 | * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 954 | * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 955 | * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock |
| AnnaBridge | 145:64910690c574 | 956 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 957 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 958 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 959 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 960 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 961 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 962 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 963 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 964 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 145:64910690c574 | 965 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 145:64910690c574 | 966 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 967 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 968 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 969 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 970 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 971 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 972 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 973 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 974 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 975 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 976 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 977 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 978 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 979 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 980 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 981 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 982 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 983 | * |
| AnnaBridge | 145:64910690c574 | 984 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 985 | * @retval None |
| AnnaBridge | 145:64910690c574 | 986 | */ |
| AnnaBridge | 145:64910690c574 | 987 | __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 988 | { |
| AnnaBridge | 145:64910690c574 | 989 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 990 | SET_BIT(RCC->APB1ENR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 991 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 992 | tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 993 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 994 | } |
| AnnaBridge | 145:64910690c574 | 995 | |
| AnnaBridge | 145:64910690c574 | 996 | /** |
| AnnaBridge | 145:64910690c574 | 997 | * @brief Enable APB1 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 998 | * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 999 | * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1000 | * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1001 | * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock |
| AnnaBridge | 145:64910690c574 | 1002 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1003 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1004 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1005 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1006 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1007 | * |
| AnnaBridge | 145:64910690c574 | 1008 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1009 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1010 | */ |
| AnnaBridge | 145:64910690c574 | 1011 | __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1012 | { |
| AnnaBridge | 145:64910690c574 | 1013 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 1014 | SET_BIT(RCC->APB1ENR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1015 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 1016 | tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1017 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 1018 | } |
| AnnaBridge | 145:64910690c574 | 1019 | |
| AnnaBridge | 145:64910690c574 | 1020 | /** |
| AnnaBridge | 145:64910690c574 | 1021 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 145:64910690c574 | 1022 | * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1023 | * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1024 | * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1025 | * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1026 | * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1027 | * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1028 | * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1029 | * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1030 | * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1031 | * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1032 | * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1033 | * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1034 | * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1035 | * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1036 | * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1037 | * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1038 | * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1039 | * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1040 | * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1041 | * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1042 | * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1043 | * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1044 | * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1045 | * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1046 | * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1047 | * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock |
| AnnaBridge | 145:64910690c574 | 1048 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1049 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 1050 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 1051 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 1052 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 1053 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 1054 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 1055 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 1056 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 145:64910690c574 | 1057 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 145:64910690c574 | 1058 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 1059 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 1060 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 1061 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 1062 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 1063 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 1064 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 1065 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 1066 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 1067 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 1068 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 1069 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 1070 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 1071 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 1072 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 1073 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 1074 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 1075 | * |
| AnnaBridge | 145:64910690c574 | 1076 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1077 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 145:64910690c574 | 1078 | */ |
| AnnaBridge | 145:64910690c574 | 1079 | __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1080 | { |
| AnnaBridge | 145:64910690c574 | 1081 | return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs); |
| AnnaBridge | 145:64910690c574 | 1082 | } |
| AnnaBridge | 145:64910690c574 | 1083 | |
| AnnaBridge | 145:64910690c574 | 1084 | /** |
| AnnaBridge | 145:64910690c574 | 1085 | * @brief Check if APB1 peripheral clock is enabled or not |
| AnnaBridge | 145:64910690c574 | 1086 | * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1087 | * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1088 | * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1089 | * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock |
| AnnaBridge | 145:64910690c574 | 1090 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1091 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1092 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1093 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1094 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1095 | * |
| AnnaBridge | 145:64910690c574 | 1096 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1097 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 145:64910690c574 | 1098 | */ |
| AnnaBridge | 145:64910690c574 | 1099 | __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1100 | { |
| AnnaBridge | 145:64910690c574 | 1101 | return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs); |
| AnnaBridge | 145:64910690c574 | 1102 | } |
| AnnaBridge | 145:64910690c574 | 1103 | |
| AnnaBridge | 145:64910690c574 | 1104 | /** |
| AnnaBridge | 145:64910690c574 | 1105 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 1106 | * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1107 | * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1108 | * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1109 | * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1110 | * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1111 | * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1112 | * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1113 | * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1114 | * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1115 | * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1116 | * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1117 | * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1118 | * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1119 | * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1120 | * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1121 | * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1122 | * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1123 | * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1124 | * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1125 | * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1126 | * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1127 | * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1128 | * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1129 | * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1130 | * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1131 | * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock |
| AnnaBridge | 145:64910690c574 | 1132 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1133 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 1134 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 1135 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 1136 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 1137 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 1138 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 1139 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 1140 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 145:64910690c574 | 1141 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 145:64910690c574 | 1142 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 1143 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 1144 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 1145 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 1146 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 1147 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 1148 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 1149 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 1150 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 1151 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 1152 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 1153 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 1154 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 1155 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 1156 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 1157 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 1158 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 1159 | * |
| AnnaBridge | 145:64910690c574 | 1160 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1161 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1162 | */ |
| AnnaBridge | 145:64910690c574 | 1163 | __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1164 | { |
| AnnaBridge | 145:64910690c574 | 1165 | CLEAR_BIT(RCC->APB1ENR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 1166 | } |
| AnnaBridge | 145:64910690c574 | 1167 | |
| AnnaBridge | 145:64910690c574 | 1168 | /** |
| AnnaBridge | 145:64910690c574 | 1169 | * @brief Disable APB1 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 1170 | * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1171 | * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1172 | * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1173 | * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock |
| AnnaBridge | 145:64910690c574 | 1174 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1175 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1176 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1177 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1178 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1179 | * |
| AnnaBridge | 145:64910690c574 | 1180 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1181 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1182 | */ |
| AnnaBridge | 145:64910690c574 | 1183 | __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1184 | { |
| AnnaBridge | 145:64910690c574 | 1185 | CLEAR_BIT(RCC->APB1ENR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1186 | } |
| AnnaBridge | 145:64910690c574 | 1187 | |
| AnnaBridge | 145:64910690c574 | 1188 | /** |
| AnnaBridge | 145:64910690c574 | 1189 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 1190 | * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1191 | * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1192 | * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1193 | * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1194 | * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1195 | * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1196 | * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1197 | * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1198 | * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1199 | * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1200 | * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1201 | * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1202 | * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1203 | * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1204 | * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1205 | * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1206 | * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1207 | * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1208 | * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1209 | * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1210 | * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1211 | * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1212 | * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1213 | * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset |
| AnnaBridge | 145:64910690c574 | 1214 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1215 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 1216 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 1217 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 1218 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 1219 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 1220 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 1221 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 1222 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 1223 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 1224 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 1225 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 1226 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 1227 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 1228 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 1229 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 1230 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 1231 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 1232 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 1233 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 1234 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 1235 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 1236 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 1237 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 1238 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 1239 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 1240 | * |
| AnnaBridge | 145:64910690c574 | 1241 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1242 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1243 | */ |
| AnnaBridge | 145:64910690c574 | 1244 | __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1245 | { |
| AnnaBridge | 145:64910690c574 | 1246 | SET_BIT(RCC->APB1RSTR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 1247 | } |
| AnnaBridge | 145:64910690c574 | 1248 | |
| AnnaBridge | 145:64910690c574 | 1249 | /** |
| AnnaBridge | 145:64910690c574 | 1250 | * @brief Force APB1 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 1251 | * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1252 | * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1253 | * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1254 | * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset |
| AnnaBridge | 145:64910690c574 | 1255 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1256 | * @arg @ref LL_APB1_GRP2_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 1257 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1258 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1259 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1260 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1261 | * |
| AnnaBridge | 145:64910690c574 | 1262 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1263 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1264 | */ |
| AnnaBridge | 145:64910690c574 | 1265 | __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1266 | { |
| AnnaBridge | 145:64910690c574 | 1267 | SET_BIT(RCC->APB1RSTR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1268 | } |
| AnnaBridge | 145:64910690c574 | 1269 | |
| AnnaBridge | 145:64910690c574 | 1270 | /** |
| AnnaBridge | 145:64910690c574 | 1271 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 1272 | * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1273 | * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1274 | * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1275 | * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1276 | * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1277 | * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1278 | * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1279 | * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1280 | * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1281 | * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1282 | * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1283 | * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1284 | * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1285 | * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1286 | * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1287 | * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1288 | * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1289 | * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1290 | * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1291 | * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1292 | * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1293 | * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1294 | * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1295 | * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset |
| AnnaBridge | 145:64910690c574 | 1296 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1297 | * @arg @ref LL_APB1_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 1298 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 1299 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 1300 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 1301 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 1302 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 1303 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 1304 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 1305 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 1306 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 1307 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 1308 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 1309 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 1310 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 1311 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 1312 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 1313 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 1314 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 1315 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 1316 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 1317 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 1318 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 1319 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 1320 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 1321 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 1322 | * |
| AnnaBridge | 145:64910690c574 | 1323 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1324 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1325 | */ |
| AnnaBridge | 145:64910690c574 | 1326 | __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1327 | { |
| AnnaBridge | 145:64910690c574 | 1328 | CLEAR_BIT(RCC->APB1RSTR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 1329 | } |
| AnnaBridge | 145:64910690c574 | 1330 | |
| AnnaBridge | 145:64910690c574 | 1331 | /** |
| AnnaBridge | 145:64910690c574 | 1332 | * @brief Release APB1 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 1333 | * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1334 | * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1335 | * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1336 | * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset |
| AnnaBridge | 145:64910690c574 | 1337 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1338 | * @arg @ref LL_APB1_GRP2_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 1339 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1340 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1341 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1342 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1343 | * |
| AnnaBridge | 145:64910690c574 | 1344 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1345 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1346 | */ |
| AnnaBridge | 145:64910690c574 | 1347 | __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1348 | { |
| AnnaBridge | 145:64910690c574 | 1349 | CLEAR_BIT(RCC->APB1RSTR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1350 | } |
| AnnaBridge | 145:64910690c574 | 1351 | |
| AnnaBridge | 145:64910690c574 | 1352 | /** |
| AnnaBridge | 145:64910690c574 | 1353 | * @brief Enable APB1 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 1354 | * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1355 | * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1356 | * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1357 | * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1358 | * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1359 | * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1360 | * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1361 | * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1362 | * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1363 | * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1364 | * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1365 | * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1366 | * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1367 | * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1368 | * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1369 | * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1370 | * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1371 | * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1372 | * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1373 | * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1374 | * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1375 | * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1376 | * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1377 | * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1378 | * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1379 | * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 1380 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1381 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 1382 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 1383 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 1384 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 1385 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 1386 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 1387 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 1388 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 145:64910690c574 | 1389 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 145:64910690c574 | 1390 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 1391 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 1392 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 1393 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 1394 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 1395 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 1396 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 1397 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 1398 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 1399 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 1400 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 1401 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 1402 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 1403 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 1404 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 1405 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 1406 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 1407 | * |
| AnnaBridge | 145:64910690c574 | 1408 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1409 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1410 | */ |
| AnnaBridge | 145:64910690c574 | 1411 | __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1412 | { |
| AnnaBridge | 145:64910690c574 | 1413 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 1414 | SET_BIT(RCC->APB1SMENR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 1415 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 1416 | tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 1417 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 1418 | } |
| AnnaBridge | 145:64910690c574 | 1419 | |
| AnnaBridge | 145:64910690c574 | 1420 | /** |
| AnnaBridge | 145:64910690c574 | 1421 | * @brief Enable APB1 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 1422 | * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1423 | * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1424 | * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1425 | * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 1426 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1427 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1428 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1429 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1430 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1431 | * |
| AnnaBridge | 145:64910690c574 | 1432 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1433 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1434 | */ |
| AnnaBridge | 145:64910690c574 | 1435 | __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1436 | { |
| AnnaBridge | 145:64910690c574 | 1437 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 1438 | SET_BIT(RCC->APB1SMENR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1439 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 1440 | tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1441 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 1442 | } |
| AnnaBridge | 145:64910690c574 | 1443 | |
| AnnaBridge | 145:64910690c574 | 1444 | /** |
| AnnaBridge | 145:64910690c574 | 1445 | * @brief Disable APB1 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 1446 | * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1447 | * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1448 | * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1449 | * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1450 | * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1451 | * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1452 | * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1453 | * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1454 | * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1455 | * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1456 | * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1457 | * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1458 | * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1459 | * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1460 | * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1461 | * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1462 | * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1463 | * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1464 | * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1465 | * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1466 | * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1467 | * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1468 | * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1469 | * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1470 | * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1471 | * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 1472 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1473 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 |
| AnnaBridge | 145:64910690c574 | 1474 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) |
| AnnaBridge | 145:64910690c574 | 1475 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) |
| AnnaBridge | 145:64910690c574 | 1476 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) |
| AnnaBridge | 145:64910690c574 | 1477 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 |
| AnnaBridge | 145:64910690c574 | 1478 | * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 |
| AnnaBridge | 145:64910690c574 | 1479 | * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) |
| AnnaBridge | 145:64910690c574 | 1480 | * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) |
| AnnaBridge | 145:64910690c574 | 1481 | * @arg @ref LL_APB1_GRP1_PERIPH_WWDG |
| AnnaBridge | 145:64910690c574 | 1482 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) |
| AnnaBridge | 145:64910690c574 | 1483 | * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 |
| AnnaBridge | 145:64910690c574 | 1484 | * @arg @ref LL_APB1_GRP1_PERIPH_USART2 |
| AnnaBridge | 145:64910690c574 | 1485 | * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) |
| AnnaBridge | 145:64910690c574 | 1486 | * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) |
| AnnaBridge | 145:64910690c574 | 1487 | * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) |
| AnnaBridge | 145:64910690c574 | 1488 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 |
| AnnaBridge | 145:64910690c574 | 1489 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) |
| AnnaBridge | 145:64910690c574 | 1490 | * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 |
| AnnaBridge | 145:64910690c574 | 1491 | * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) |
| AnnaBridge | 145:64910690c574 | 1492 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 |
| AnnaBridge | 145:64910690c574 | 1493 | * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) |
| AnnaBridge | 145:64910690c574 | 1494 | * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) |
| AnnaBridge | 145:64910690c574 | 1495 | * @arg @ref LL_APB1_GRP1_PERIPH_PWR |
| AnnaBridge | 145:64910690c574 | 1496 | * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 |
| AnnaBridge | 145:64910690c574 | 1497 | * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP |
| AnnaBridge | 145:64910690c574 | 1498 | * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 |
| AnnaBridge | 145:64910690c574 | 1499 | * |
| AnnaBridge | 145:64910690c574 | 1500 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1501 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1502 | */ |
| AnnaBridge | 145:64910690c574 | 1503 | __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1504 | { |
| AnnaBridge | 145:64910690c574 | 1505 | CLEAR_BIT(RCC->APB1SMENR1, Periphs); |
| AnnaBridge | 145:64910690c574 | 1506 | } |
| AnnaBridge | 145:64910690c574 | 1507 | |
| AnnaBridge | 145:64910690c574 | 1508 | /** |
| AnnaBridge | 145:64910690c574 | 1509 | * @brief Disable APB1 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 1510 | * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1511 | * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1512 | * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1513 | * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 1514 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1515 | * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 |
| AnnaBridge | 145:64910690c574 | 1516 | * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) |
| AnnaBridge | 145:64910690c574 | 1517 | * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) |
| AnnaBridge | 145:64910690c574 | 1518 | * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 |
| AnnaBridge | 145:64910690c574 | 1519 | * |
| AnnaBridge | 145:64910690c574 | 1520 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1521 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1522 | */ |
| AnnaBridge | 145:64910690c574 | 1523 | __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1524 | { |
| AnnaBridge | 145:64910690c574 | 1525 | CLEAR_BIT(RCC->APB1SMENR2, Periphs); |
| AnnaBridge | 145:64910690c574 | 1526 | } |
| AnnaBridge | 145:64910690c574 | 1527 | |
| AnnaBridge | 145:64910690c574 | 1528 | /** |
| AnnaBridge | 145:64910690c574 | 1529 | * @} |
| AnnaBridge | 145:64910690c574 | 1530 | */ |
| AnnaBridge | 145:64910690c574 | 1531 | |
| AnnaBridge | 145:64910690c574 | 1532 | /** @defgroup BUS_LL_EF_APB2 APB2 |
| AnnaBridge | 145:64910690c574 | 1533 | * @{ |
| AnnaBridge | 145:64910690c574 | 1534 | */ |
| AnnaBridge | 145:64910690c574 | 1535 | |
| AnnaBridge | 145:64910690c574 | 1536 | /** |
| AnnaBridge | 145:64910690c574 | 1537 | * @brief Enable APB2 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 1538 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1539 | * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1540 | * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1541 | * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1542 | * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1543 | * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1544 | * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1545 | * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1546 | * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1547 | * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1548 | * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1549 | * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n |
| AnnaBridge | 145:64910690c574 | 1550 | * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock |
| AnnaBridge | 145:64910690c574 | 1551 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1552 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1553 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| AnnaBridge | 145:64910690c574 | 1554 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1555 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1556 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1557 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1558 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1559 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1560 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1561 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1562 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1563 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1564 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1565 | * |
| AnnaBridge | 145:64910690c574 | 1566 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1567 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1568 | */ |
| AnnaBridge | 145:64910690c574 | 1569 | __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1570 | { |
| AnnaBridge | 145:64910690c574 | 1571 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 1572 | SET_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1573 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 1574 | tmpreg = READ_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1575 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 1576 | } |
| AnnaBridge | 145:64910690c574 | 1577 | |
| AnnaBridge | 145:64910690c574 | 1578 | /** |
| AnnaBridge | 145:64910690c574 | 1579 | * @brief Check if APB2 peripheral clock is enabled or not |
| AnnaBridge | 145:64910690c574 | 1580 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1581 | * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1582 | * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1583 | * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1584 | * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1585 | * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1586 | * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1587 | * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1588 | * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1589 | * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1590 | * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1591 | * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n |
| AnnaBridge | 145:64910690c574 | 1592 | * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock |
| AnnaBridge | 145:64910690c574 | 1593 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1594 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1595 | * @arg @ref LL_APB2_GRP1_PERIPH_FW |
| AnnaBridge | 145:64910690c574 | 1596 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1597 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1598 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1599 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1600 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1601 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1602 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1603 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1604 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1605 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1606 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1607 | * |
| AnnaBridge | 145:64910690c574 | 1608 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1609 | * @retval State of Periphs (1 or 0). |
| AnnaBridge | 145:64910690c574 | 1610 | */ |
| AnnaBridge | 145:64910690c574 | 1611 | __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1612 | { |
| AnnaBridge | 145:64910690c574 | 1613 | return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); |
| AnnaBridge | 145:64910690c574 | 1614 | } |
| AnnaBridge | 145:64910690c574 | 1615 | |
| AnnaBridge | 145:64910690c574 | 1616 | /** |
| AnnaBridge | 145:64910690c574 | 1617 | * @brief Disable APB2 peripherals clock. |
| AnnaBridge | 145:64910690c574 | 1618 | * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1619 | * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1620 | * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1621 | * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1622 | * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1623 | * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1624 | * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1625 | * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1626 | * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1627 | * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1628 | * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n |
| AnnaBridge | 145:64910690c574 | 1629 | * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock |
| AnnaBridge | 145:64910690c574 | 1630 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1631 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1632 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1633 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1634 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1635 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1636 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1637 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1638 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1639 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1640 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1641 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1642 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1643 | * |
| AnnaBridge | 145:64910690c574 | 1644 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1645 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1646 | */ |
| AnnaBridge | 145:64910690c574 | 1647 | __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1648 | { |
| AnnaBridge | 145:64910690c574 | 1649 | CLEAR_BIT(RCC->APB2ENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1650 | } |
| AnnaBridge | 145:64910690c574 | 1651 | |
| AnnaBridge | 145:64910690c574 | 1652 | /** |
| AnnaBridge | 145:64910690c574 | 1653 | * @brief Force APB2 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 1654 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1655 | * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1656 | * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1657 | * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1658 | * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1659 | * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1660 | * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1661 | * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1662 | * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1663 | * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1664 | * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n |
| AnnaBridge | 145:64910690c574 | 1665 | * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset |
| AnnaBridge | 145:64910690c574 | 1666 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1667 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 1668 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1669 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1670 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1671 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1672 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1673 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1674 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1675 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1676 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1677 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1678 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1679 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1680 | * |
| AnnaBridge | 145:64910690c574 | 1681 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1682 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1683 | */ |
| AnnaBridge | 145:64910690c574 | 1684 | __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1685 | { |
| AnnaBridge | 145:64910690c574 | 1686 | SET_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1687 | } |
| AnnaBridge | 145:64910690c574 | 1688 | |
| AnnaBridge | 145:64910690c574 | 1689 | /** |
| AnnaBridge | 145:64910690c574 | 1690 | * @brief Release APB2 peripherals reset. |
| AnnaBridge | 145:64910690c574 | 1691 | * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1692 | * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1693 | * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1694 | * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1695 | * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1696 | * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1697 | * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1698 | * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1699 | * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1700 | * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1701 | * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n |
| AnnaBridge | 145:64910690c574 | 1702 | * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset |
| AnnaBridge | 145:64910690c574 | 1703 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1704 | * @arg @ref LL_APB2_GRP1_PERIPH_ALL |
| AnnaBridge | 145:64910690c574 | 1705 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1706 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1707 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1708 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1709 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1710 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1711 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1712 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1713 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1714 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1715 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1716 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1717 | * |
| AnnaBridge | 145:64910690c574 | 1718 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1719 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1720 | */ |
| AnnaBridge | 145:64910690c574 | 1721 | __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1722 | { |
| AnnaBridge | 145:64910690c574 | 1723 | CLEAR_BIT(RCC->APB2RSTR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1724 | } |
| AnnaBridge | 145:64910690c574 | 1725 | |
| AnnaBridge | 145:64910690c574 | 1726 | /** |
| AnnaBridge | 145:64910690c574 | 1727 | * @brief Enable APB2 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 1728 | * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1729 | * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1730 | * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1731 | * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1732 | * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1733 | * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1734 | * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1735 | * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1736 | * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1737 | * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1738 | * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1739 | * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 1740 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1741 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1742 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1743 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1744 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1745 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1746 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1747 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1748 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1749 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1750 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1751 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1752 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1753 | * |
| AnnaBridge | 145:64910690c574 | 1754 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1755 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1756 | */ |
| AnnaBridge | 145:64910690c574 | 1757 | __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1758 | { |
| AnnaBridge | 145:64910690c574 | 1759 | __IO uint32_t tmpreg; |
| AnnaBridge | 145:64910690c574 | 1760 | SET_BIT(RCC->APB2SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1761 | /* Delay after an RCC peripheral clock enabling */ |
| AnnaBridge | 145:64910690c574 | 1762 | tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1763 | (void)tmpreg; |
| AnnaBridge | 145:64910690c574 | 1764 | } |
| AnnaBridge | 145:64910690c574 | 1765 | |
| AnnaBridge | 145:64910690c574 | 1766 | /** |
| AnnaBridge | 145:64910690c574 | 1767 | * @brief Disable APB2 peripheral clocks in Sleep and Stop modes |
| AnnaBridge | 145:64910690c574 | 1768 | * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1769 | * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1770 | * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1771 | * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1772 | * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1773 | * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1774 | * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1775 | * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1776 | * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1777 | * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1778 | * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n |
| AnnaBridge | 145:64910690c574 | 1779 | * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep |
| AnnaBridge | 145:64910690c574 | 1780 | * @param Periphs This parameter can be a combination of the following values: |
| AnnaBridge | 145:64910690c574 | 1781 | * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG |
| AnnaBridge | 145:64910690c574 | 1782 | * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) |
| AnnaBridge | 145:64910690c574 | 1783 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 |
| AnnaBridge | 145:64910690c574 | 1784 | * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 |
| AnnaBridge | 145:64910690c574 | 1785 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) |
| AnnaBridge | 145:64910690c574 | 1786 | * @arg @ref LL_APB2_GRP1_PERIPH_USART1 |
| AnnaBridge | 145:64910690c574 | 1787 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 |
| AnnaBridge | 145:64910690c574 | 1788 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 |
| AnnaBridge | 145:64910690c574 | 1789 | * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) |
| AnnaBridge | 145:64910690c574 | 1790 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 |
| AnnaBridge | 145:64910690c574 | 1791 | * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) |
| AnnaBridge | 145:64910690c574 | 1792 | * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) |
| AnnaBridge | 145:64910690c574 | 1793 | * |
| AnnaBridge | 145:64910690c574 | 1794 | * (*) value not defined in all devices. |
| AnnaBridge | 145:64910690c574 | 1795 | * @retval None |
| AnnaBridge | 145:64910690c574 | 1796 | */ |
| AnnaBridge | 145:64910690c574 | 1797 | __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) |
| AnnaBridge | 145:64910690c574 | 1798 | { |
| AnnaBridge | 145:64910690c574 | 1799 | CLEAR_BIT(RCC->APB2SMENR, Periphs); |
| AnnaBridge | 145:64910690c574 | 1800 | } |
| AnnaBridge | 145:64910690c574 | 1801 | |
| AnnaBridge | 145:64910690c574 | 1802 | /** |
| AnnaBridge | 145:64910690c574 | 1803 | * @} |
| AnnaBridge | 145:64910690c574 | 1804 | */ |
| AnnaBridge | 145:64910690c574 | 1805 | |
| AnnaBridge | 145:64910690c574 | 1806 | |
| AnnaBridge | 145:64910690c574 | 1807 | /** |
| AnnaBridge | 145:64910690c574 | 1808 | * @} |
| AnnaBridge | 145:64910690c574 | 1809 | */ |
| AnnaBridge | 145:64910690c574 | 1810 | |
| AnnaBridge | 145:64910690c574 | 1811 | /** |
| AnnaBridge | 145:64910690c574 | 1812 | * @} |
| AnnaBridge | 145:64910690c574 | 1813 | */ |
| AnnaBridge | 145:64910690c574 | 1814 | |
| AnnaBridge | 145:64910690c574 | 1815 | #endif /* defined(RCC) */ |
| AnnaBridge | 145:64910690c574 | 1816 | |
| AnnaBridge | 145:64910690c574 | 1817 | /** |
| AnnaBridge | 145:64910690c574 | 1818 | * @} |
| AnnaBridge | 145:64910690c574 | 1819 | */ |
| AnnaBridge | 145:64910690c574 | 1820 | |
| AnnaBridge | 145:64910690c574 | 1821 | #ifdef __cplusplus |
| AnnaBridge | 145:64910690c574 | 1822 | } |
| AnnaBridge | 145:64910690c574 | 1823 | #endif |
| AnnaBridge | 145:64910690c574 | 1824 | |
| AnnaBridge | 145:64910690c574 | 1825 | #endif /* __STM32L4xx_LL_BUS_H */ |
| AnnaBridge | 145:64910690c574 | 1826 | |
| AnnaBridge | 145:64910690c574 | 1827 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
